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Generate the Verilog code corresponding to the following Chisel files.
File Periphery.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.debug
import chisel3._
import chisel3.experimental.{noPrefix, IntParam}
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.apb.{APBBundle, APBBundleParameters, APBMasterNode, APBMasterParameters, APBMasterPortParameters}
import freechips.rocketchip.interrupts.{IntSyncXbar, NullIntSyncSource}
import freechips.rocketchip.jtag.JTAGIO
import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters}
import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, FBUS, ResetSynchronous, SubsystemResetSchemeKey, TLBusWrapperLocation}
import freechips.rocketchip.tilelink.{TLFragmenter, TLWidthWidget}
import freechips.rocketchip.util.{AsyncResetSynchronizerShiftReg, CanHavePSDTestModeIO, ClockGate, PSDTestMode, PlusArg, ResetSynchronizerShiftReg}
import freechips.rocketchip.util.BooleanToAugmentedBoolean
/** Protocols used for communicating with external debugging tools */
sealed trait DebugExportProtocol
case object DMI extends DebugExportProtocol
case object JTAG extends DebugExportProtocol
case object CJTAG extends DebugExportProtocol
case object APB extends DebugExportProtocol
/** Options for possible debug interfaces */
case class DebugAttachParams(
protocols: Set[DebugExportProtocol] = Set(DMI),
externalDisable: Boolean = false,
masterWhere: TLBusWrapperLocation = FBUS,
slaveWhere: TLBusWrapperLocation = CBUS
) {
def dmi = protocols.contains(DMI)
def jtag = protocols.contains(JTAG)
def cjtag = protocols.contains(CJTAG)
def apb = protocols.contains(APB)
}
case object ExportDebug extends Field(DebugAttachParams())
class ClockedAPBBundle(params: APBBundleParameters) extends APBBundle(params) {
val clock = Clock()
val reset = Reset()
}
class DebugIO(implicit val p: Parameters) extends Bundle {
val clock = Input(Clock())
val reset = Input(Reset())
val clockeddmi = p(ExportDebug).dmi.option(Flipped(new ClockedDMIIO()))
val systemjtag = p(ExportDebug).jtag.option(new SystemJTAGIO)
val apb = p(ExportDebug).apb.option(Flipped(new ClockedAPBBundle(APBBundleParameters(addrBits=12, dataBits=32))))
//------------------------------
val ndreset = Output(Bool())
val dmactive = Output(Bool())
val dmactiveAck = Input(Bool())
val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO())
val disableDebug = p(ExportDebug).externalDisable.option(Input(Bool()))
}
class PSDIO(implicit val p: Parameters) extends Bundle with CanHavePSDTestModeIO {
}
class ResetCtrlIO(val nComponents: Int)(implicit val p: Parameters) extends Bundle {
val hartResetReq = (p(DebugModuleKey).exists(x=>x.hasHartResets)).option(Output(Vec(nComponents, Bool())))
val hartIsInReset = Input(Vec(nComponents, Bool()))
}
/** Either adds a JTAG DTM to system, and exports a JTAG interface,
* or exports the Debug Module Interface (DMI), or exports and hooks up APB,
* based on a global parameter.
*/
trait HasPeripheryDebug { this: BaseSubsystem =>
private lazy val tlbus = locateTLBusWrapper(p(ExportDebug).slaveWhere)
lazy val debugCustomXbarOpt = p(DebugModuleKey).map(params => LazyModule( new DebugCustomXbar(outputRequiresInput = false)))
lazy val apbDebugNodeOpt = p(ExportDebug).apb.option(APBMasterNode(Seq(APBMasterPortParameters(Seq(APBMasterParameters("debugAPB"))))))
val debugTLDomainOpt = p(DebugModuleKey).map { _ =>
val domain = ClockSinkNode(Seq(ClockSinkParameters()))
domain := tlbus.fixedClockNode
domain
}
lazy val debugOpt = p(DebugModuleKey).map { params =>
val tlDM = LazyModule(new TLDebugModule(tlbus.beatBytes))
tlDM.node := tlbus.coupleTo("debug"){ TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("Debug")) := _ }
tlDM.dmInner.dmInner.customNode := debugCustomXbarOpt.get.node
(apbDebugNodeOpt zip tlDM.apbNodeOpt) foreach { case (master, slave) =>
slave := master
}
tlDM.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
locateTLBusWrapper(p(ExportDebug).masterWhere).coupleFrom("debug_sb") {
_ := TLWidthWidget(1) := sb2tl.node
}
}
tlDM
}
val debugNode = debugOpt.map(_.intnode)
val psd = InModuleBody {
val psd = IO(new PSDIO)
psd
}
val resetctrl = InModuleBody {
debugOpt.map { debug =>
debug.module.io.tl_reset := debugTLDomainOpt.get.in.head._1.reset
debug.module.io.tl_clock := debugTLDomainOpt.get.in.head._1.clock
val resetctrl = IO(new ResetCtrlIO(debug.dmOuter.dmOuter.intnode.edges.out.size))
debug.module.io.hartIsInReset := resetctrl.hartIsInReset
resetctrl.hartResetReq.foreach { rcio => debug.module.io.hartResetReq.foreach { rcdm => rcio := rcdm }}
resetctrl
}
}
// noPrefix is workaround https://github.com/freechipsproject/chisel3/issues/1603
val debug = InModuleBody { noPrefix(debugOpt.map { debugmod =>
val debug = IO(new DebugIO)
require(!(debug.clockeddmi.isDefined && debug.systemjtag.isDefined),
"You cannot have both DMI and JTAG interface in HasPeripheryDebug")
require(!(debug.clockeddmi.isDefined && debug.apb.isDefined),
"You cannot have both DMI and APB interface in HasPeripheryDebug")
require(!(debug.systemjtag.isDefined && debug.apb.isDefined),
"You cannot have both APB and JTAG interface in HasPeripheryDebug")
debug.clockeddmi.foreach { dbg => debugmod.module.io.dmi.get <> dbg }
(debug.apb
zip apbDebugNodeOpt
zip debugmod.module.io.apb_clock
zip debugmod.module.io.apb_reset).foreach {
case (((io, apb), c ), r) =>
apb.out(0)._1 <> io
c:= io.clock
r:= io.reset
}
debugmod.module.io.debug_reset := debug.reset
debugmod.module.io.debug_clock := debug.clock
debug.ndreset := debugmod.module.io.ctrl.ndreset
debug.dmactive := debugmod.module.io.ctrl.dmactive
debugmod.module.io.ctrl.dmactiveAck := debug.dmactiveAck
debug.extTrigger.foreach { x => debugmod.module.io.extTrigger.foreach {y => x <> y}}
// TODO in inheriting traits: Set this to something meaningful, e.g. "component is in reset or powered down"
debugmod.module.io.ctrl.debugUnavail.foreach { _ := false.B }
debug
})}
val dtm = InModuleBody { debug.flatMap(_.systemjtag.map(instantiateJtagDTM(_))) }
def instantiateJtagDTM(sj: SystemJTAGIO): DebugTransportModuleJTAG = {
val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleKey).get.nDMIAddrSize, p(JtagDTMKey)))
dtm.io.jtag <> sj.jtag
debug.map(_.disableDebug.foreach { x => dtm.io.jtag.TMS := sj.jtag.TMS | x }) // force TMS high when debug is disabled
dtm.io.jtag_clock := sj.jtag.TCK
dtm.io.jtag_reset := sj.reset
dtm.io.jtag_mfr_id := sj.mfr_id
dtm.io.jtag_part_number := sj.part_number
dtm.io.jtag_version := sj.version
dtm.rf_reset := sj.reset
debugOpt.map { outerdebug =>
outerdebug.module.io.dmi.get.dmi <> dtm.io.dmi
outerdebug.module.io.dmi.get.dmiClock := sj.jtag.TCK
outerdebug.module.io.dmi.get.dmiReset := sj.reset
}
dtm
}
}
/** BlackBox to export DMI interface */
class SimDTM(implicit p: Parameters) extends BlackBox with HasBlackBoxResource {
val io = IO(new Bundle {
val clk = Input(Clock())
val reset = Input(Bool())
val debug = new DMIIO
val exit = Output(UInt(32.W))
})
def connect(tbclk: Clock, tbreset: Bool, dutio: ClockedDMIIO, tbsuccess: Bool) = {
io.clk := tbclk
io.reset := tbreset
dutio.dmi <> io.debug
dutio.dmiClock := tbclk
dutio.dmiReset := tbreset
tbsuccess := io.exit === 1.U
assert(io.exit < 2.U, "*** FAILED *** (exit code = %d)\n", io.exit >> 1.U)
}
addResource("/vsrc/SimDTM.v")
addResource("/csrc/SimDTM.cc")
}
/** BlackBox to export JTAG interface */
class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam(tickDelay)))
with HasBlackBoxResource {
val io = IO(new Bundle {
val clock = Input(Clock())
val reset = Input(Bool())
val jtag = new JTAGIO(hasTRSTn = true)
val enable = Input(Bool())
val init_done = Input(Bool())
val exit = Output(UInt(32.W))
})
def connect(dutio: JTAGIO, tbclock: Clock, tbreset: Bool, init_done: Bool, tbsuccess: Bool) = {
dutio.TCK := io.jtag.TCK
dutio.TMS := io.jtag.TMS
dutio.TDI := io.jtag.TDI
io.jtag.TDO := dutio.TDO
io.clock := tbclock
io.reset := tbreset
io.enable := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.")
io.init_done := init_done
// Success is determined by the gdbserver
// which is controlling this simulation.
tbsuccess := io.exit === 1.U
assert(io.exit < 2.U, "*** FAILED *** (exit code = %d)\n", io.exit >> 1.U)
}
addResource("/vsrc/SimJTAG.v")
addResource("/csrc/SimJTAG.cc")
addResource("/csrc/remote_bitbang.h")
addResource("/csrc/remote_bitbang.cc")
}
object Debug {
def connectDebug(
debugOpt: Option[DebugIO],
resetctrlOpt: Option[ResetCtrlIO],
psdio: PSDIO,
c: Clock,
r: Bool,
out: Bool,
tckHalfPeriod: Int = 2,
cmdDelay: Int = 2,
psd: PSDTestMode = 0.U.asTypeOf(new PSDTestMode()))
(implicit p: Parameters): Unit = {
connectDebugClockAndReset(debugOpt, c)
resetctrlOpt.map { rcio => rcio.hartIsInReset.map { _ := r }}
debugOpt.map { debug =>
debug.clockeddmi.foreach { d =>
val dtm = Module(new SimDTM).connect(c, r, d, out)
}
debug.systemjtag.foreach { sj =>
val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, c, r, ~r, out)
sj.reset := r.asAsyncReset
sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
sj.part_number := p(JtagDTMKey).idcodePartNum.U(16.W)
sj.version := p(JtagDTMKey).idcodeVersion.U(4.W)
}
debug.apb.foreach { apb =>
require(false, "No support for connectDebug for an APB debug connection.")
}
psdio.psd.foreach { _ <> psd }
debug.disableDebug.foreach { x => x := false.B }
}
}
def connectDebugClockAndReset(debugOpt: Option[DebugIO], c: Clock, sync: Boolean = true)(implicit p: Parameters): Unit = {
debugOpt.foreach { debug =>
val dmi_reset = debug.clockeddmi.map(_.dmiReset.asBool).getOrElse(false.B) |
debug.systemjtag.map(_.reset.asBool).getOrElse(false.B) |
debug.apb.map(_.reset.asBool).getOrElse(false.B)
connectDebugClockHelper(debug, dmi_reset, c, sync)
}
}
def connectDebugClockHelper(debug: DebugIO, dmi_reset: Reset, c: Clock, sync: Boolean = true)(implicit p: Parameters): Unit = {
val debug_reset = Wire(Bool())
withClockAndReset(c, dmi_reset) {
val debug_reset_syncd = if(sync) ~AsyncResetSynchronizerShiftReg(in=true.B, sync=3, name=Some("debug_reset_sync")) else dmi_reset
debug_reset := debug_reset_syncd
}
// Need to clock DM during debug_reset because of synchronous reset, so keep
// the clock alive for one cycle after debug_reset asserts to action this behavior.
// The unit should also be clocked when dmactive is high.
withClockAndReset(c, debug_reset.asAsyncReset) {
val dmactiveAck = if (sync) ResetSynchronizerShiftReg(in=debug.dmactive, sync=3, name=Some("dmactiveAck")) else debug.dmactive
val clock_en = RegNext(next=dmactiveAck, init=true.B)
val gated_clock =
if (!p(DebugModuleKey).get.clockGate) c
else ClockGate(c, clock_en, "debug_clock_gate")
debug.clock := gated_clock
debug.reset := (if (p(SubsystemResetSchemeKey)==ResetSynchronous) debug_reset else debug_reset.asAsyncReset)
debug.dmactiveAck := dmactiveAck
}
}
def tieoffDebug(debugOpt: Option[DebugIO], resetctrlOpt: Option[ResetCtrlIO] = None, psdio: Option[PSDIO] = None)(implicit p: Parameters): Bool = {
psdio.foreach(_.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode()) } )
resetctrlOpt.map { rcio => rcio.hartIsInReset.map { _ := false.B }}
debugOpt.map { debug =>
debug.clock := true.B.asClock
debug.reset := (if (p(SubsystemResetSchemeKey)==ResetSynchronous) true.B else true.B.asAsyncReset)
debug.systemjtag.foreach { sj =>
sj.jtag.TCK := true.B.asClock
sj.jtag.TMS := true.B
sj.jtag.TDI := true.B
sj.jtag.TRSTn.foreach { r => r := true.B }
sj.reset := true.B.asAsyncReset
sj.mfr_id := 0.U
sj.part_number := 0.U
sj.version := 0.U
}
debug.clockeddmi.foreach { d =>
d.dmi.req.valid := false.B
d.dmi.req.bits.addr := 0.U
d.dmi.req.bits.data := 0.U
d.dmi.req.bits.op := 0.U
d.dmi.resp.ready := true.B
d.dmiClock := false.B.asClock
d.dmiReset := true.B.asAsyncReset
}
debug.apb.foreach { apb =>
apb.clock := false.B.asClock
apb.reset := true.B.asAsyncReset
apb.pready := false.B
apb.pslverr := false.B
apb.prdata := 0.U
apb.pduser := 0.U.asTypeOf(chiselTypeOf(apb.pduser))
apb.psel := false.B
apb.penable := false.B
}
debug.extTrigger.foreach { t =>
t.in.req := false.B
t.out.ack := t.out.req
}
debug.disableDebug.foreach { x => x := false.B }
debug.dmactiveAck := false.B
debug.ndreset
}.getOrElse(false.B)
}
}
File ResetCatchAndSync.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.{withClockAndReset, withReset}
/** Reset: asynchronous assert,
* synchronous de-assert
*
*/
class ResetCatchAndSync (sync: Int = 3) extends Module {
override def desiredName = s"ResetCatchAndSync_d${sync}"
val io = IO(new Bundle {
val sync_reset = Output(Bool())
val psd = Input(new PSDTestMode())
})
// Bypass both the resets to the flops themselves (to prevent DFT holes on
// those flops) and on the output of the synchronizer circuit (to control
// reset to any flops this circuit drives).
val post_psd_reset = Mux(io.psd.test_mode, io.psd.test_mode_reset, reset.asBool)
withReset(post_psd_reset) {
io.sync_reset := Mux(io.psd.test_mode, io.psd.test_mode_reset,
~AsyncResetSynchronizerShiftReg(true.B, sync))
}
}
object ResetCatchAndSync {
def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None,
psd: Option[PSDTestMode] = None): Bool = {
withClockAndReset(clk, rst) {
val catcher = Module (new ResetCatchAndSync(sync))
if (name.isDefined) {catcher.suggestName(name.get)}
catcher.io.psd <> psd.getOrElse(WireDefault(0.U.asTypeOf(new PSDTestMode())))
catcher.io.sync_reset
}
}
def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name))
def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name))
def apply(clk: Clock, rst: Bool, sync: Int, name: String, psd: PSDTestMode): Bool =
apply(clk, rst, sync, Some(name), Some(psd))
def apply(clk: Clock, rst: Bool, name: String, psd: PSDTestMode): Bool =
apply(clk, rst, name = Some(name), psd = Some(psd))
}
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File IOCell.scala:
// See LICENSE for license details
package chipyard.iocell
import chisel3._
import chisel3.util.{Cat, HasBlackBoxInline}
import chisel3.reflect.DataMirror
import chisel3.experimental.{Analog, BaseModule}
// The following four IO cell bundle types are bare-minimum functional connections
// for modeling 4 different IO cell scenarios. The intention is that the user
// would create wrapper modules that extend these interfaces with additional
// control signals. These are loosely similar to the sifive-blocks PinCtrl bundles
// (https://github.com/sifive/sifive-blocks/blob/master/src/main/scala/devices/pinctrl/PinCtrl.scala),
// but we want to avoid a dependency on an external libraries.
/** The base IO bundle for an analog signal (typically something with no digital buffers inside)
* pad: off-chip (external) connection
* core: internal connection
*/
class AnalogIOCellBundle extends Bundle {
val pad = Analog(1.W) // Pad/bump signal (off-chip)
val core = Analog(1.W) // core signal (on-chip)
}
/** The base IO bundle for a signal with runtime-controllable direction
* pad: off-chip (external) connection
* i: input to chip logic (output from IO cell)
* ie: enable signal for i
* o: output from chip logic (input to IO cell)
* oe: enable signal for o
*/
class DigitalGPIOCellBundle extends Bundle {
val pad = Analog(1.W)
val i = Output(Bool())
val ie = Input(Bool())
val o = Input(Bool())
val oe = Input(Bool())
}
/** The base IO bundle for a digital output signal
* pad: off-chip (external) connection
* o: output from chip logic (input to IO cell)
* oe: enable signal for o
*/
class DigitalOutIOCellBundle extends Bundle {
val pad = Output(Bool())
val o = Input(Bool())
val oe = Input(Bool())
}
/** The base IO bundle for a digital input signal
* pad: off-chip (external) connection
* i: input to chip logic (output from IO cell)
* ie: enable signal for i
*/
class DigitalInIOCellBundle extends Bundle {
val pad = Input(Bool())
val i = Output(Bool())
val ie = Input(Bool())
}
trait IOCell extends BaseModule {
var iocell_name: Option[String] = None
/** Set IOCell name
* @param s Proposed name for the IOCell
*
* @return An inherited IOCell with given the proposed name
*/
def suggestName(s: String): this.type = {
iocell_name = Some(s)
super.suggestName(s)
}
}
trait AnalogIOCell extends IOCell {
val io: AnalogIOCellBundle
}
trait DigitalGPIOCell extends IOCell {
val io: DigitalGPIOCellBundle
}
trait DigitalInIOCell extends IOCell {
val io: DigitalInIOCellBundle
}
trait DigitalOutIOCell extends IOCell {
val io: DigitalOutIOCellBundle
}
// The following Generic IO cell black boxes have verilog models that mimic a very simple
// implementation of an IO cell. For building a real chip, it is important to implement
// and use similar classes which wrap the foundry-specific IO cells.
abstract class GenericIOCell extends BlackBox with HasBlackBoxInline {
val impl: String
val moduleName = this.getClass.getSimpleName
setInline(s"$moduleName.v", impl);
}
class GenericAnalogIOCell extends GenericIOCell with AnalogIOCell {
val io = IO(new AnalogIOCellBundle)
lazy val impl = s"""
`timescale 1ns/1ps
module GenericAnalogIOCell(
inout pad,
inout core
);
assign core = 1'bz;
assign pad = core;
endmodule"""
}
class GenericDigitalGPIOCell extends GenericIOCell with DigitalGPIOCell {
val io = IO(new DigitalGPIOCellBundle)
lazy val impl = s"""
`timescale 1ns/1ps
module GenericDigitalGPIOCell(
inout pad,
output i,
input ie,
input o,
input oe
);
assign pad = oe ? o : 1'bz;
assign i = ie ? pad : 1'b0;
endmodule"""
}
class GenericDigitalInIOCell extends GenericIOCell with DigitalInIOCell {
val io = IO(new DigitalInIOCellBundle)
lazy val impl = s"""
`timescale 1ns/1ps
module GenericDigitalInIOCell(
input pad,
output i,
input ie
);
assign i = ie ? pad : 1'b0;
endmodule"""
}
class GenericDigitalOutIOCell extends GenericIOCell with DigitalOutIOCell {
val io = IO(new DigitalOutIOCellBundle)
lazy val impl = s"""
`timescale 1ns/1ps
module GenericDigitalOutIOCell(
output pad,
input o,
input oe
);
assign pad = oe ? o : 1'bz;
endmodule"""
}
trait IOCellTypeParams {
def analog(): AnalogIOCell
def gpio(): DigitalGPIOCell
def input(): DigitalInIOCell
def output(): DigitalOutIOCell
}
case class GenericIOCellParams() extends IOCellTypeParams {
def analog() = Module(new GenericAnalogIOCell)
def gpio() = Module(new GenericDigitalGPIOCell)
def input() = Module(new GenericDigitalInIOCell)
def output() = Module(new GenericDigitalOutIOCell)
}
object IOCell {
/** From within a RawModule or MultiIOModule context, generate new module IOs from a given
* signal and return the new IO and a Seq containing all generated IO cells.
* @param coreSignal The signal onto which to add IO cells
* @param name An optional name or name prefix to use for naming IO cells
* @param abstractResetAsAsync When set, will coerce abstract resets to
* AsyncReset, and otherwise to Bool (sync reset)
* @return A tuple of (the generated IO data node, a Seq of all generated IO cell instances)
*/
def generateIOFromSignal[T <: Data](
coreSignal: T,
name: String,
typeParams: IOCellTypeParams = GenericIOCellParams(),
abstractResetAsAsync: Boolean = false
): (T, Seq[IOCell]) = {
val padSignal = IO(DataMirror.internal.chiselTypeClone[T](coreSignal)).suggestName(name)
val resetFn = if (abstractResetAsAsync) toAsyncReset else toSyncReset
val iocells = IOCell.generateFromSignal(coreSignal, padSignal, Some(s"iocell_$name"), typeParams, resetFn)
(padSignal, iocells)
}
/** Connect two identical signals together by adding IO cells between them and return a Seq
* containing all generated IO cells.
* @param coreSignal The core-side (internal) signal onto which to connect/add IO cells
* @param padSignal The pad-side (external) signal onto which to connect IO cells
* @param name An optional name or name prefix to use for naming IO cells
* @return A Seq of all generated IO cell instances
*/
val toSyncReset: (Reset) => Bool = _.asBool
val toAsyncReset: (Reset) => AsyncReset = _.asAsyncReset
def generateFromSignal[T <: Data, R <: Reset](
coreSignal: T,
padSignal: T,
name: Option[String] = None,
typeParams: IOCellTypeParams = GenericIOCellParams(),
concretizeResetFn: (Reset) => R = toSyncReset
): Seq[IOCell] = {
def genCell[T <: Data](
castToBool: (T) => Bool,
castFromBool: (Bool) => T
)(coreSignal: T,
padSignal: T
): Seq[IOCell] = {
DataMirror.directionOf(coreSignal) match {
case ActualDirection.Input => {
val iocell = typeParams.input()
name.foreach(n => {
iocell.suggestName(n)
})
coreSignal := castFromBool(iocell.io.i)
iocell.io.ie := true.B
iocell.io.pad := castToBool(padSignal)
Seq(iocell)
}
case ActualDirection.Output => {
val iocell = typeParams.output()
name.foreach(n => {
iocell.suggestName(n)
})
iocell.io.o := castToBool(coreSignal)
iocell.io.oe := true.B
padSignal := castFromBool(iocell.io.pad)
Seq(iocell)
}
case _ => throw new Exception(s"Signal does not have a direction and cannot be matched to an IOCell")
}
}
def genCellForClock = genCell[Clock](_.asUInt.asBool, _.asClock) _
def genCellForAsyncReset = genCell[AsyncReset](_.asBool, _.asAsyncReset) _
def genCellForAbstractReset = genCell[Reset](_.asBool, concretizeResetFn) _
(coreSignal, padSignal) match {
case (coreSignal: Analog, padSignal: Analog) => {
if (coreSignal.getWidth == 0) {
Seq()
} else {
require(
coreSignal.getWidth == 1,
"Analogs wider than 1 bit are not supported because we can't bit-select Analogs (https://github.com/freechipsproject/chisel3/issues/536)"
)
val iocell = typeParams.analog()
name.foreach(n => iocell.suggestName(n))
iocell.io.core <> coreSignal
padSignal <> iocell.io.pad
Seq(iocell)
}
}
case (coreSignal: Clock, padSignal: Clock) => genCellForClock(coreSignal, padSignal)
case (coreSignal: AsyncReset, padSignal: AsyncReset) => genCellForAsyncReset(coreSignal, padSignal)
case (coreSignal: Bits, padSignal: Bits) => {
require(padSignal.getWidth == coreSignal.getWidth, "padSignal and coreSignal must be the same width")
if (padSignal.getWidth == 0) {
// This dummy assignment will prevent invalid firrtl from being emitted
DataMirror.directionOf(coreSignal) match {
case ActualDirection.Input => coreSignal := 0.U
case _ => {}
}
Seq()
} else {
DataMirror.directionOf(coreSignal) match {
case ActualDirection.Input => {
val iocells = padSignal.asBools.zipWithIndex.map { case (sig, i) =>
val iocell = typeParams.input()
// Note that we are relying on chisel deterministically naming this in the index order (which it does)
// This has the side-effect of naming index 0 with no _0 suffix, which is how chisel names other signals
// An alternative solution would be to suggestName(n + "_" + i)
name.foreach(n => {
iocell.suggestName(n)
})
iocell.io.pad := sig
iocell.io.ie := true.B
iocell
}
// Note that the reverse here is because Cat(Seq(a,b,c,d)) yields abcd, but a is index 0 of the Seq
coreSignal := Cat(iocells.map(_.io.i).reverse)
iocells
}
case ActualDirection.Output => {
val iocells = coreSignal.asBools.zipWithIndex.map { case (sig, i) =>
val iocell = typeParams.output()
// Note that we are relying on chisel deterministically naming this in the index order (which it does)
// This has the side-effect of naming index 0 with no _0 suffix, which is how chisel names other signals
// An alternative solution would be to suggestName(n + "_" + i)
name.foreach(n => {
iocell.suggestName(n)
})
iocell.io.o := sig
iocell.io.oe := true.B
iocell
}
// Note that the reverse here is because Cat(Seq(a,b,c,d)) yields abcd, but a is index 0 of the Seq
padSignal := Cat(iocells.map(_.io.pad).reverse)
iocells
}
case _ => throw new Exception("Bits signal does not have a direction and cannot be matched to IOCell(s)")
}
}
}
case (coreSignal: Reset, padSignal: Reset) => genCellForAbstractReset(coreSignal, padSignal)
case (coreSignal: Vec[_], padSignal: Vec[_]) => {
require(padSignal.size == coreSignal.size, "size of Vec for padSignal and coreSignal must be the same")
coreSignal.zip(padSignal).zipWithIndex.foldLeft(Seq.empty[IOCell]) { case (total, ((core, pad), i)) =>
val ios = IOCell.generateFromSignal(core, pad, name.map(_ + "_" + i), typeParams)
total ++ ios
}
}
case (coreSignal: Record, padSignal: Record) => {
coreSignal.elements.foldLeft(Seq.empty[IOCell]) { case (total, (eltName, core)) =>
val pad = padSignal.elements(eltName)
val ios = IOCell.generateFromSignal(core, pad, name.map(_ + "_" + eltName), typeParams)
total ++ ios
}
}
case _ => { throw new Exception("Oops, I don't know how to handle this signal.") }
}
}
}
File ChipTop.scala:
package chipyard
import chisel3._
import scala.collection.mutable.{ArrayBuffer}
import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup}
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope}
import freechips.rocketchip.util.{DontTouch}
import chipyard.iobinders._
import chipyard.iocell._
case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => new DigitalTop()(p))
/**
* The base class used for building chips. This constructor instantiates a module specified by the BuildSystem parameter,
* named "system", which is an instance of DigitalTop by default. The diplomatic clocks of System, as well as its implicit clock,
* is aggregated into the clockGroupNode. The parameterized functions controlled by ClockingSchemeKey and GlobalResetSchemeKey
* drive clock and reset generation
*/
class ChipTop(implicit p: Parameters) extends LazyModule with BindingScope
with HasIOBinders {
// The system module specified by BuildSystem
lazy val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system")
// NOTE: Making this a LazyRawModule is moderately dangerous, as anonymous children
// of ChipTop (ex: ClockGroup) do not receive clock or reset.
// However. anonymous children of ChipTop should not need an implicit Clock or Reset
// anyways, they probably need to be explicitly clocked.
lazy val module: LazyModuleImpLike = new LazyRawModuleImp(this) with DontTouch { }
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File ClockGate.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{HasBlackBoxResource, HasBlackBoxPath}
import org.chipsalliance.cde.config.{Field, Parameters}
import java.nio.file.{Files, Paths}
case object ClockGateImpl extends Field[() => ClockGate](() => new EICG_wrapper)
case object ClockGateModelFile extends Field[Option[String]](None)
abstract class ClockGate extends BlackBox
with HasBlackBoxResource with HasBlackBoxPath {
val io = IO(new Bundle{
val in = Input(Clock())
val test_en = Input(Bool())
val en = Input(Bool())
val out = Output(Clock())
})
def addVerilogResource(vsrc: String): Unit = {
if (Files.exists(Paths.get(vsrc)))
addPath(vsrc)
else
addResource(vsrc)
}
}
object ClockGate {
def apply[T <: ClockGate](
in: Clock,
en: Bool,
name: Option[String] = None)(implicit p: Parameters): Clock = {
val cg = Module(p(ClockGateImpl)())
name.foreach(cg.suggestName(_))
p(ClockGateModelFile).map(cg.addVerilogResource(_))
cg.io.in := in
cg.io.test_en := false.B
cg.io.en := en
cg.io.out
}
def apply[T <: ClockGate](
in: Clock,
en: Bool,
name: String)(implicit p: Parameters): Clock =
apply(in, en, Some(name))
}
// behavioral model of Integrated Clock Gating cell
class EICG_wrapper extends ClockGate
File IOBinders.scala:
package chipyard.iobinders
import chisel3._
import chisel3.reflect.DataMirror
import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import org.chipsalliance.diplomacy.aop._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.bundlebridge._
import freechips.rocketchip.diplomacy.{Resource, ResourceBinding, ResourceAddress, RegionType}
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system.{SimAXIMem}
import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}
import freechips.rocketchip.util._
import freechips.rocketchip.prci._
import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem}
import freechips.rocketchip.tilelink.{TLBundle}
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.i2c._
import tracegen.{TraceGenSystemModuleImp}
import chipyard.iocell._
import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}
import testchipip.spi.{SPIChipIO}
import testchipip.boot.{CanHavePeripheryCustomBootPin}
import testchipip.soc.{CanHavePeripheryChipIdPin}
import testchipip.util.{ClockedIO}
import testchipip.iceblk.{CanHavePeripheryBlockDevice, BlockDeviceKey, BlockDeviceIO}
import testchipip.cosim.{CanHaveTraceIO, TraceOutputTop, SpikeCosimConfig}
import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO}
import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
import chipyard.{CanHaveMasterTLMemPort, ChipyardSystem, ChipyardSystemModule}
import chipyard.example.{CanHavePeripheryGCD}
import scala.reflect.{ClassTag}
object IOBinderTypes {
type IOBinderTuple = (Seq[Port[_]], Seq[IOCell])
type IOBinderFunction = (Boolean, => Any) => ModuleValue[IOBinderTuple]
}
import IOBinderTypes._
// System for instantiating binders based
// on the scala type of the Target (_not_ its IO). This avoids needing to
// duplicate harnesses (essentially test harnesses) for each target.
// IOBinders is map between string representations of traits to the desired
// IO connection behavior for tops matching that trait. We use strings to enable
// composition and overriding of IOBinders, much like how normal Keys in the config
// system are used/ At elaboration, the testharness traverses this set of functions,
// and functions which match the type of the DigitalTop are evaluated.
// You can add your own binder by adding a new (key, fn) pair, typically by using
// the OverrideIOBinder or ComposeIOBinder macros
case object IOBinders extends Field[Map[String, Seq[IOBinderFunction]]](
Map[String, Seq[IOBinderFunction]]().withDefaultValue(Nil)
)
abstract trait HasIOBinders extends HasChipyardPorts { this: LazyModule =>
val lazySystem: LazyModule
private val iobinders = p(IOBinders)
// Note: IOBinders cannot rely on the implicit clock/reset, as they may be called from the
// context of a LazyRawModuleImp
private val lzy = iobinders.map({ case (s,fns) => s -> fns.map(f => f(true, lazySystem)) })
private val imp = iobinders.map({ case (s,fns) => s -> fns.map(f => f(false, lazySystem.module)) })
private lazy val lzyFlattened: Map[String, IOBinderTuple] = lzy.map({
case (s,ms) => s -> (ms.map(_._1).flatten, ms.map(_._2).flatten)
})
private lazy val impFlattened: Map[String, IOBinderTuple] = imp.map({
case (s,ms) => s -> (ms.map(_._1).flatten, ms.map(_._2).flatten)
})
// A publicly accessible list of IO cells (useful for a floorplanning tool, for example)
val iocells = InModuleBody { (lzyFlattened.values ++ impFlattened.values).unzip._2.flatten.toBuffer }
// A mapping between stringified DigitalSystem traits and their corresponding ChipTop ports
val portMap = InModuleBody { iobinders.keys.map(k => k -> (lzyFlattened(k)._1 ++ impFlattened(k)._1)).toMap }
// A mapping between stringified DigitalSystem traits and their corresponding ChipTop iocells
val iocellMap = InModuleBody { iobinders.keys.map(k => k -> (lzyFlattened(k)._2 ++ impFlattened(k)._2)).toMap }
def ports = portMap.getWrappedValue.values.flatten.toSeq
InModuleBody {
println("IOCells generated by IOBinders:")
for ((k, v) <- iocellMap) {
if (!v.isEmpty) {
val cells = v.map(_.getClass.getSimpleName).groupBy(identity).mapValues(_.size)
println(s" IOBinder for $k generated:")
for ((t, c) <- cells) { println(s" $c X $t") }
}
}
println()
val totals = iocells.map(_.getClass.getSimpleName).groupBy(identity).mapValues(_.size)
println(s" Total generated ${iocells.size} IOCells:")
for ((t, c) <- totals) { println(s" $c X $t") }
}
}
// Note: The parameters instance is accessible only through LazyModule
// or LazyModuleImpLike. The self-type requirement in traits like
// CanHaveMasterAXI4MemPort is insufficient to make it accessible to the IOBinder
// As a result, IOBinders only work on Modules which inherit LazyModule or
// or LazyModuleImpLike
object GetSystemParameters {
def apply(s: Any): Parameters = {
s match {
case s: LazyModule => s.p
case s: LazyModuleImpLike => s.p
case _ => throw new Exception(s"Trying to get Parameters from a system that is not LazyModule or LazyModuleImpLike")
}
}
}
class IOBinder[T](composer: Seq[IOBinderFunction] => Seq[IOBinderFunction])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
case IOBinders => {
val upMap = up(IOBinders)
upMap + (tag.runtimeClass.toString -> composer(upMap(tag.runtimeClass.toString)))
}
})
class ConcreteIOBinder[T](composes: Boolean, fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends IOBinder[T](
up => (if (composes) up else Nil) ++ Seq(((_, t) => { InModuleBody {
t match {
case system: T => fn(system)
case _ => (Nil, Nil)
}
}}): IOBinderFunction)
)
class LazyIOBinder[T](composes: Boolean, fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends IOBinder[T](
up => (if (composes) up else Nil) ++ Seq(((isLazy, t) => {
val empty = new ModuleValue[IOBinderTuple] {
def getWrappedValue: IOBinderTuple = (Nil, Nil)
}
if (isLazy) {
t match {
case system: T => fn(system)
case _ => empty
}
} else {
empty
}
}): IOBinderFunction)
)
// The "Override" binders override any previous IOBinders (lazy or concrete) defined on the same trait.
// The "Compose" binders do not override previously defined IOBinders on the same trait
// The default IOBinders evaluate only in the concrete "ModuleImp" phase of elaboration
// The "Lazy" IOBinders evaluate in the LazyModule phase, but can also generate hardware through InModuleBody
class OverrideIOBinder[T](fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends ConcreteIOBinder[T](false, fn)
class ComposeIOBinder[T](fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends ConcreteIOBinder[T](true, fn)
class OverrideLazyIOBinder[T](fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends LazyIOBinder[T](false, fn)
class ComposeLazyIOBinder[T](fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends LazyIOBinder[T](true, fn)
case object IOCellKey extends Field[IOCellTypeParams](GenericIOCellParams())
class WithGPIOCells extends OverrideIOBinder({
(system: HasPeripheryGPIO) => {
val (ports2d, cells2d) = system.gpio.zipWithIndex.map({ case (gpio, i) =>
gpio.pins.zipWithIndex.map({ case (pin, j) =>
val p = system.asInstanceOf[BaseSubsystem].p
val g = IO(Analog(1.W)).suggestName(s"gpio_${i}_${j}")
val iocell = p(IOCellKey).gpio().suggestName(s"iocell_gpio_${i}_${j}")
iocell.io.o := pin.o.oval
iocell.io.oe := pin.o.oe
iocell.io.ie := pin.o.ie
pin.i.ival := iocell.io.i
pin.i.po.foreach(_ := DontCare)
iocell.io.pad <> g
(GPIOPort(() => g, i, j), iocell)
}).unzip
}).unzip
(ports2d.flatten, cells2d.flatten)
}
})
class WithGPIOPunchthrough extends OverrideIOBinder({
(system: HasPeripheryGPIO) => {
val ports = system.gpio.zipWithIndex.map { case (gpio, i) =>
val io_gpio = IO(gpio.cloneType).suggestName(s"gpio_$i")
io_gpio <> gpio
GPIOPinsPort(() => io_gpio, i)
}
(ports, Nil)
}
})
class WithI2CPunchthrough extends OverrideIOBinder({
(system: HasPeripheryI2C) => {
val ports = system.i2c.zipWithIndex.map { case (i2c, i) =>
val io_i2c = IO(i2c.cloneType).suggestName(s"i2c_$i")
io_i2c <> i2c
I2CPort(() => i2c)
}
(ports, Nil)
}
})
// DOC include start: WithUARTIOCells
class WithUARTIOCells extends OverrideIOBinder({
(system: HasPeripheryUART) => {
val (ports: Seq[UARTPort], cells2d) = system.uart.zipWithIndex.map({ case (u, i) =>
val p = system.asInstanceOf[BaseSubsystem].p
val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", p(IOCellKey), abstractResetAsAsync = true)
val where = PBUS // TODO fix
val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
val freqMHz = bus.dtsFrequency.get / 1000000
(UARTPort(() => port, i, freqMHz.toInt), ios)
}).unzip
(ports, cells2d.flatten)
}
})
// DOC include end: WithUARTIOCells
class WithSPIIOPunchthrough extends OverrideLazyIOBinder({
(system: HasPeripherySPI) => {
// attach resource to 1st SPI
if (system.tlSpiNodes.size > 0) ResourceBinding {
Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0))
}
InModuleBody {
val spi = system.spi
val ports = spi.zipWithIndex.map({ case (s, i) =>
val io_spi = IO(s.cloneType).suggestName(s"spi_$i")
io_spi <> s
SPIPort(() => io_spi)
})
(ports, Nil)
}
}
})
class WithSPIFlashIOCells extends OverrideIOBinder({
(system: HasPeripherySPIFlash) => {
val (ports: Seq[SPIFlashPort], cells2d) = system.qspi.zipWithIndex.map({ case (s, i) =>
val p = system.asInstanceOf[BaseSubsystem].p
val name = s"spi_${i}"
val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(name)
val iocellBase = s"iocell_${name}"
// SCK and CS are unidirectional outputs
val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), p(IOCellKey), IOCell.toAsyncReset)
val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), p(IOCellKey), IOCell.toAsyncReset)
// DQ are bidirectional, so then need special treatment
val dqIOs = s.dq.zip(port.dq).zipWithIndex.map { case ((pin, ana), j) =>
val iocell = p(IOCellKey).gpio().suggestName(s"${iocellBase}_dq_${j}")
iocell.io.o := pin.o
iocell.io.oe := pin.oe
iocell.io.ie := true.B
pin.i := iocell.io.i
iocell.io.pad <> ana
iocell
}
(SPIFlashPort(() => port, p(PeripherySPIFlashKey)(i), i), dqIOs ++ csIOs ++ sckIOs)
}).unzip
(ports, cells2d.flatten)
}
})
class WithExtInterruptIOCells extends OverrideIOBinder({
(system: HasExtInterruptsModuleImp) => {
if (system.outer.nExtInterrupts > 0) {
val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, "ext_interrupts", system.p(IOCellKey), abstractResetAsAsync = true)
(Seq(ExtIntPort(() => port)), cells)
} else {
system.interrupts := DontCare // why do I have to drive this 0-wide wire???
(Nil, Nil)
}
}
})
// Rocketchip's JTAGIO exposes the oe signal, which doesn't go off-chip
class JTAGChipIO extends Bundle {
val TCK = Input(Clock())
val TMS = Input(Bool())
val TDI = Input(Bool())
val TDO = Output(Bool())
}
// WARNING: Don't disable syncReset unless you are trying to
// get around bugs in RTL simulators
class WithDebugIOCells(syncReset: Boolean = true) extends OverrideLazyIOBinder({
(system: HasPeripheryDebug) => {
implicit val p = GetSystemParameters(system)
val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(p(ExportDebug).slaveWhere)
val clockSinkNode = system.debugOpt.map(_ => ClockSinkNode(Seq(ClockSinkParameters())))
clockSinkNode.map(_ := tlbus.fixedClockNode)
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody { system.asInstanceOf[BaseSubsystem] match { case system: HasPeripheryDebug => {
system.debug.map({ debug =>
// We never use the PSDIO, so tie it off on-chip
system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) }
system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := clockBundle.reset.asBool } }
system.debug.map { d =>
// Tie off extTrigger
d.extTrigger.foreach { t =>
t.in.req := false.B
t.out.ack := t.out.req
}
// Tie off disableDebug
d.disableDebug.foreach { d => d := false.B }
// Drive JTAG on-chip IOs
d.systemjtag.map { j =>
j.reset := (if (syncReset) ResetCatchAndSync(j.jtag.TCK, clockBundle.reset.asBool) else clockBundle.reset.asBool)
j.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
j.part_number := p(JtagDTMKey).idcodePartNum.U(16.W)
j.version := p(JtagDTMKey).idcodeVersion.U(4.W)
}
}
Debug.connectDebugClockAndReset(Some(debug), clockBundle.clock)
// Add IOCells for the DMI/JTAG/APB ports
val dmiTuple = debug.clockeddmi.map { d =>
val (port, cells) = IOCell.generateIOFromSignal(d, "dmi", p(IOCellKey), abstractResetAsAsync = true)
(DMIPort(() => port), cells)
}
val jtagTuple = debug.systemjtag.map { j =>
val jtag_wire = Wire(new JTAGChipIO)
j.jtag.TCK := jtag_wire.TCK
j.jtag.TMS := jtag_wire.TMS
j.jtag.TDI := jtag_wire.TDI
jtag_wire.TDO := j.jtag.TDO.data
val (port, cells) = IOCell.generateIOFromSignal(jtag_wire, "jtag", p(IOCellKey), abstractResetAsAsync = true)
(JTAGPort(() => port), cells)
}
require(!debug.apb.isDefined)
val allTuples = (dmiTuple ++ jtagTuple).toSeq
(allTuples.map(_._1).toSeq, allTuples.flatMap(_._2).toSeq)
}).getOrElse((Nil, Nil))
}}}
}
})
class WithSerialTLIOCells extends OverrideIOBinder({
(system: CanHavePeripheryTLSerial) => {
val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) =>
val sys = system.asInstanceOf[BaseSubsystem]
val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, s"serial_tl_$id", sys.p(IOCellKey), abstractResetAsAsync = true)
(SerialTLPort(() => port, sys.p(SerialTLKey)(id), system.serdessers(id), id), cells)
}).unzip
(ports.toSeq, cells.flatten.toSeq)
}
})
class WithChipIdIOCells extends OverrideIOBinder({
(system: CanHavePeripheryChipIdPin) => system.chip_id_pin.map({ p =>
val sys = system.asInstanceOf[BaseSubsystem]
val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, s"chip_id", sys.p(IOCellKey), abstractResetAsAsync = true)
(Seq(ChipIdPort(() => port)), cells)
}).getOrElse(Nil, Nil)
})
class WithSerialTLPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryTLSerial) => {
val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) =>
val sys = system.asInstanceOf[BaseSubsystem]
val port = IO(chiselTypeOf(s.getWrappedValue))
port <> s.getWrappedValue
(SerialTLPort(() => port, sys.p(SerialTLKey)(id), system.serdessers(id), id), Nil)
}).unzip
(ports.toSeq, cells.flatten.toSeq)
}
})
class WithAXI4MemPunchthrough extends OverrideLazyIOBinder({
(system: CanHaveMasterAXI4MemPort) => {
implicit val p: Parameters = GetSystemParameters(system)
val clockSinkNode = p(ExtMem).map(_ => ClockSinkNode(Seq(ClockSinkParameters())))
clockSinkNode.map(_ := system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(MBUS).fixedClockNode)
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody {
val ports: Seq[AXI4MemPort] = system.mem_axi4.zipWithIndex.map({ case (m, i) =>
val port = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mem_${i}")
port.bits <> m
port.clock := clockBundle.clock
AXI4MemPort(() => port, p(ExtMem).get, system.memAXI4Node.edges.in(i), p(MemoryBusKey).dtsFrequency.get.toInt)
}).toSeq
(ports, Nil)
}
}
})
class WithAXI4MMIOPunchthrough extends OverrideLazyIOBinder({
(system: CanHaveMasterAXI4MMIOPort) => {
implicit val p: Parameters = GetSystemParameters(system)
val clockSinkNode = p(ExtBus).map(_ => ClockSinkNode(Seq(ClockSinkParameters())))
clockSinkNode.map(_ := system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(SBUS).fixedClockNode)
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody {
val ports: Seq[AXI4MMIOPort] = system.mmio_axi4.zipWithIndex.map({ case (m, i) =>
val port = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mmio_${i}")
port.bits <> m
port.clock := clockBundle.clock
AXI4MMIOPort(() => port, p(ExtBus).get, system.mmioAXI4Node.edges.in(i))
}).toSeq
(ports, Nil)
}
}
})
class WithL2FBusAXI4Punchthrough extends OverrideLazyIOBinder({
(system: CanHaveSlaveAXI4Port) => {
implicit val p: Parameters = GetSystemParameters(system)
val clockSinkNode = p(ExtIn).map(_ => ClockSinkNode(Seq(ClockSinkParameters())))
val fbus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(FBUS)
clockSinkNode.map(_ := fbus.fixedClockNode)
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody {
val ports: Seq[AXI4InPort] = system.l2_frontend_bus_axi4.zipWithIndex.map({ case (m, i) =>
val port = IO(new ClockedIO(Flipped(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)))).suggestName(s"axi4_fbus_${i}")
m <> port.bits
port.clock := clockBundle.clock
AXI4InPort(() => port, p(ExtIn).get)
}).toSeq
(ports, Nil)
}
}
})
class WithBlockDeviceIOPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryBlockDevice) => {
val ports: Seq[BlockDevicePort] = system.bdev.map({ bdev =>
val p = GetSystemParameters(system)
val bdParams = p(BlockDeviceKey).get
val port = IO(new ClockedIO(new BlockDeviceIO(bdParams))).suggestName("blockdev")
port <> bdev
BlockDevicePort(() => port, bdParams)
}).toSeq
(ports, Nil)
}
})
class WithNICIOPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryIceNIC) => {
val ports: Seq[NICPort] = system.icenicOpt.map({ n =>
val p = GetSystemParameters(system)
val port = IO(new ClockedIO(new NICIOvonly)).suggestName("nic")
port <> n
NICPort(() => port, p(NICKey).get)
}).toSeq
(ports, Nil)
}
})
class WithTraceGenSuccessPunchthrough extends OverrideIOBinder({
(system: TraceGenSystemModuleImp) => {
val success: Bool = IO(Output(Bool())).suggestName("success")
success := system.success
(Seq(SuccessPort(() => success)), Nil)
}
})
class WithTraceIOPunchthrough extends OverrideLazyIOBinder({
(system: CanHaveTraceIO) => InModuleBody {
val ports: Option[TracePort] = system.traceIO.map { t =>
val trace = IO(DataMirror.internal.chiselTypeClone[TraceOutputTop](t)).suggestName("trace")
trace <> t
val p = GetSystemParameters(system)
val chipyardSystem = system.asInstanceOf[ChipyardSystem]
val tiles = chipyardSystem.totalTiles.values
val viewpointBus = system.asInstanceOf[HasConfigurableTLNetworkTopology].viewpointBus
val mems = viewpointBus.unifyManagers.filter { m =>
val regionTypes = Seq(RegionType.CACHED, RegionType.TRACKED, RegionType.UNCACHED, RegionType.IDEMPOTENT)
val ignoreAddresses = Seq(
0x10000 // bootrom is handled specially
)
regionTypes.contains(m.regionType) && !ignoreAddresses.contains(m.address.map(_.base).min)
}.map { m =>
val base = m.address.map(_.base).min
val size = m.address.map(_.max).max - base + 1
(base, size)
}
val useSimDTM = p(ExportDebug).protocols.contains(DMI) // assume that exposing clockeddmi means we will connect SimDTM
val cfg = SpikeCosimConfig(
isa = tiles.headOption.map(_.isaDTS).getOrElse(""),
priv = tiles.headOption.map(t => if (t.usingUser) "MSU" else if (t.usingSupervisor) "MS" else "M").getOrElse(""),
maxpglevels = tiles.headOption.map(_.tileParams.core.pgLevels).getOrElse(0),
pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0),
nharts = tiles.size,
bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse(""),
has_dtm = useSimDTM,
mems = mems,
// Connect using the legacy API for firesim only
mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)),
mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)),
)
TracePort(() => trace, cfg)
}
(ports.toSeq, Nil)
}
})
class WithCustomBootPin extends OverrideIOBinder({
(system: CanHavePeripheryCustomBootPin) => system.custom_boot_pin.map({ p =>
val sys = system.asInstanceOf[BaseSubsystem]
val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, "custom_boot", sys.p(IOCellKey), abstractResetAsAsync = true)
(Seq(CustomBootPort(() => port)), cells)
}).getOrElse((Nil, Nil))
})
class WithUARTTSIPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryUARTTSI) => system.uart_tsi.map({ p =>
val sys = system.asInstanceOf[BaseSubsystem]
val uart_tsi = IO(new UARTTSIIO(p.uartParams))
uart_tsi <> p
(Seq(UARTTSIPort(() => uart_tsi)), Nil)
}).getOrElse((Nil, Nil))
})
class WithTLMemPunchthrough extends OverrideIOBinder({
(system: CanHaveMasterTLMemPort) => {
val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave")
io_tl_mem_pins_temp <> system.mem_tl
(Seq(TLMemPort(() => io_tl_mem_pins_temp)), Nil)
}
})
class WithDontTouchPorts extends OverrideIOBinder({
(system: DontTouch) => system.dontTouchPorts(); (Nil, Nil)
})
class WithNMITiedOff extends ComposeIOBinder({
(system: HasHierarchicalElementsRootContextModuleImp) => {
system.nmi.foreach { nmi =>
nmi.rnmi := false.B
nmi.rnmi_interrupt_vector := 0.U
nmi.rnmi_exception_vector := 0.U
}
(Nil, Nil)
}
})
class WithGCDBusyPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryGCD) => system.gcd_busy.map { busy =>
val io_gcd_busy = IO(Output(Bool()))
io_gcd_busy := busy
(Seq(GCDBusyPort(() => io_gcd_busy)), Nil)
}.getOrElse((Nil, Nil))
})
File ClockBinders.scala:
package chipyard.clocking
import chisel3._
import chisel3.util._
import chipyard.iobinders._
import freechips.rocketchip.prci._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import chipyard.iocell._
// This uses the FakePLL, which uses a ClockAtFreq Verilog blackbox to generate
// the requested clocks. This also adds TileLink ClockDivider and ClockSelector
// blocks, which allow memory-mapped control of clock division, and clock muxing
// between the FakePLL and the slow off-chip clock
// Note: This will not simulate properly with firesim
// Unsetting enable will prevent the divider/selector from actually modifying the clock,
// while preserving the address map. Unsetting enable should only be done for RTL
// simulators (Verilator) which do not model reset properly
class WithPLLSelectorDividerClockGenerator(enable: Boolean = true) extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
// Connect the implicit clock
implicit val p = GetSystemParameters(system)
val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(system.prciParams.slaveWhere)
val baseAddress = system.prciParams.baseAddress
val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes, enable=enable)) }
val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes, enable=enable)) }
val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) }
clockDivider.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockDivider")) := system.prci_ctrl_bus.get }
clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockSelector")) := system.prci_ctrl_bus.get }
pllCtrl.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("PLLCtrl")) := system.prci_ctrl_bus.get }
system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
// Connect all other requested clocks
val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
val pllClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
// The order of the connections to clockSelector.clockNode configures the inputs
// of the clockSelector's clockMux. Default to using the slowClockSource,
// software should enable the PLL, then switch to the pllClockSource
clockSelector.clockNode := slowClockSource
clockSelector.clockNode := pllClockSource
val pllCtrlSink = BundleBridgeSink[FakePLLCtrlBundle]()
pllCtrlSink := pllCtrl.ctrlNode
InModuleBody {
val clock_wire = Wire(Input(Clock()))
val reset_wire = Wire(Input(AsyncReset()))
val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey))
slowClockSource.out.unzip._1.map { o =>
o.clock := clock_wire
o.reset := reset_wire
}
// For a real chip you should replace this ClockSourceAtFreqFromPlusArg
// with a blackbox of whatever PLL is being integrated
val fake_pll = Module(new ClockSourceAtFreqFromPlusArg("pll_freq_mhz"))
fake_pll.io.power := pllCtrlSink.in(0)._1.power
fake_pll.io.gate := pllCtrlSink.in(0)._1.gate
pllClockSource.out.unzip._1.map { o =>
o.clock := fake_pll.io.clk
o.reset := reset_wire
}
(Seq(ClockPort(() => clock_io, 100), ResetPort(() => reset_io)), clockIOCell ++ resetIOCell)
}
}
})
// This passes all clocks through to the TestHarness
class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
implicit val p = GetSystemParameters(system)
// This aggregate node should do nothing
val clockGroupAggNode = ClockGroupAggregateNode("fake")
val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
system.chiptopClockGroupsNode := clockGroupAggNode := clockGroupsSourceNode
InModuleBody {
val reset_io = IO(Input(AsyncReset()))
require(clockGroupAggNode.out.size == 1)
val (bundle, edge) = clockGroupAggNode.out(0)
val clock_ios = (bundle.member.data zip edge.sink.members).map { case (b, m) =>
require(m.take.isDefined, s"""Clock ${m.name.get} has no requested frequency
|Clocks: ${edge.sink.members.map(_.name.get)}""".stripMargin)
val freq = m.take.get.freqMHz
val clock_io = IO(Input(Clock())).suggestName(s"clock_${m.name.get}")
b.clock := clock_io
b.reset := reset_io
ClockPort(() => clock_io, freq)
}.toSeq
((clock_ios :+ ResetPort(() => reset_io)), Nil)
}
}
})
// Broadcasts a single clock IO to all clock domains. Ignores all requested frequencies
class WithSingleClockBroadcastClockGenerator(freqMHz: Int = 100) extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
implicit val p = GetSystemParameters(system)
val clockGroupsAggregator = LazyModule(new ClockGroupAggregator("single_clock"))
val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
system.chiptopClockGroupsNode :*= clockGroupsAggregator.node := clockGroupsSourceNode
InModuleBody {
val clock_wire = Wire(Input(Clock()))
val reset_wire = Wire(Input(AsyncReset()))
val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey))
clockGroupsSourceNode.out.foreach { case (bundle, edge) =>
bundle.member.data.foreach { b =>
b.clock := clock_io
b.reset := reset_io
}
}
(Seq(ClockPort(() => clock_io, freqMHz), ResetPort(() => reset_io)), clockIOCell ++ resetIOCell)
}
}
})
class WithClockTapIOCells extends OverrideIOBinder({
(system: CanHaveClockTap) => {
system.clockTapIO.map { tap =>
val (clock_tap_io, clock_tap_cell) = IOCell.generateIOFromSignal(tap.getWrappedValue, "clock_tap")
(Seq(ClockTapPort(() => clock_tap_io)), clock_tap_cell)
}.getOrElse((Nil, Nil))
}
})
|
module ChipTop( // @[ChipTop.scala:33:44]
output uart_0_txd, // @[IOCell.scala:196:23]
input uart_0_rxd, // @[IOCell.scala:196:23]
input custom_boot, // @[IOCell.scala:196:23]
input jtag_TCK, // @[IOCell.scala:196:23]
input jtag_TMS, // @[IOCell.scala:196:23]
input jtag_TDI, // @[IOCell.scala:196:23]
output jtag_TDO, // @[IOCell.scala:196:23]
input reset_io, // @[ClockBinders.scala:87:24]
input clock_uncore, // @[ClockBinders.scala:95:26]
output clock_tap, // @[IOCell.scala:196:23]
output serial_tl_0_in_ready, // @[IOCell.scala:196:23]
input serial_tl_0_in_valid, // @[IOCell.scala:196:23]
input [31:0] serial_tl_0_in_bits_phit, // @[IOCell.scala:196:23]
input serial_tl_0_out_ready, // @[IOCell.scala:196:23]
output serial_tl_0_out_valid, // @[IOCell.scala:196:23]
output [31:0] serial_tl_0_out_bits_phit, // @[IOCell.scala:196:23]
input serial_tl_0_clock_in // @[IOCell.scala:196:23]
);
wire _iocell_serial_tl_0_in_valid_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_31_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_30_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_29_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_28_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_27_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_26_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_25_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_24_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_23_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_22_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_21_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_20_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_19_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_18_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_17_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_16_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_15_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_14_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_13_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_12_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_11_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_10_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_9_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_8_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_7_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_6_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_5_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_4_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_3_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_2_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_1_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_out_ready_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_out_bits_phit_31_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_30_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_29_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_28_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_27_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_26_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_25_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_24_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_23_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_22_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_21_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_20_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_19_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_18_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_17_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_16_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_15_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_14_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_13_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_12_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_11_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_10_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_9_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_8_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_7_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_6_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_5_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_4_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_3_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_2_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_1_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_pad; // @[IOCell.scala:177:24]
wire _gated_clock_debug_clock_gate_out; // @[ClockGate.scala:36:20]
wire _system_debug_systemjtag_reset_catcher_io_sync_reset; // @[ResetCatchAndSync.scala:39:28]
wire _iocell_custom_boot_i; // @[IOCell.scala:176:23]
wire _iocell_uart_0_rxd_i; // @[IOCell.scala:176:23]
wire _system_debug_dmactive; // @[ChipTop.scala:27:35]
wire _system_serial_tl_0_in_ready; // @[ChipTop.scala:27:35]
wire _system_serial_tl_0_out_valid; // @[ChipTop.scala:27:35]
wire [31:0] _system_serial_tl_0_out_bits_phit; // @[ChipTop.scala:27:35]
wire _system_uart_0_txd; // @[ChipTop.scala:27:35]
wire uart_0_rxd_0 = uart_0_rxd; // @[ChipTop.scala:33:44]
wire jtag_TCK_0 = jtag_TCK; // @[ChipTop.scala:33:44]
wire jtag_TMS_0 = jtag_TMS; // @[ChipTop.scala:33:44]
wire jtag_TDI_0 = jtag_TDI; // @[ChipTop.scala:33:44]
wire serial_tl_0_in_valid_0 = serial_tl_0_in_valid; // @[ChipTop.scala:33:44]
wire [31:0] serial_tl_0_in_bits_phit_0 = serial_tl_0_in_bits_phit; // @[ChipTop.scala:33:44]
wire serial_tl_0_out_ready_0 = serial_tl_0_out_ready; // @[ChipTop.scala:33:44]
wire serial_tl_0_clock_in_0 = serial_tl_0_clock_in; // @[ChipTop.scala:33:44]
wire clockGroupAggNodeOut_member_allClocks_uncore_clock = clock_uncore; // @[MixedNode.scala:542:17]
wire clockGroupAggNodeOut_member_allClocks_uncore_reset = reset_io; // @[MixedNode.scala:542:17]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockGroupAggNodeIn_member_fake_uncore_clock = 1'h0; // @[MixedNode.scala:551:17]
wire clockGroupAggNodeIn_member_fake_uncore_reset = 1'h0; // @[MixedNode.scala:551:17]
wire clockGroupsSourceNodeOut_member_fake_uncore_clock = 1'h0; // @[MixedNode.scala:542:17]
wire clockGroupsSourceNodeOut_member_fake_uncore_reset = 1'h0; // @[MixedNode.scala:542:17]
wire _system_debug_systemjtag_reset_catcher_io_psd_WIRE_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:63]
wire _system_debug_systemjtag_reset_catcher_io_psd_WIRE_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:63]
wire _system_debug_systemjtag_reset_catcher_io_psd_WIRE_1_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:50]
wire _system_debug_systemjtag_reset_catcher_io_psd_WIRE_1_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:50]
wire _iocell_jtag_TCK_io_pad_T = jtag_TCK_0; // @[IOCell.scala:248:44]
wire [31:0] _serial_tl_0_out_bits_phit_T; // @[IOCell.scala:312:31]
wire _iocell_serial_tl_0_clock_in_io_pad_T = serial_tl_0_clock_in_0; // @[IOCell.scala:248:44]
wire uart_0_txd_0; // @[ChipTop.scala:33:44]
wire jtag_TDO_0; // @[ChipTop.scala:33:44]
wire _clock_tap_T; // @[IOCell.scala:248:61]
wire serial_tl_0_in_ready_0; // @[ChipTop.scala:33:44]
wire [31:0] serial_tl_0_out_bits_phit_0; // @[ChipTop.scala:33:44]
wire serial_tl_0_out_valid_0; // @[ChipTop.scala:33:44]
wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire _system_resetctrl_hartIsInReset_0_T = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire _system_debug_systemjtag_reset_T = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire _dmi_reset_T; // @[Periphery.scala:281:38]
wire _dmi_reset_T_1 = _dmi_reset_T; // @[Periphery.scala:280:82, :281:38]
wire dmi_reset = _dmi_reset_T_1; // @[Periphery.scala:280:82, :281:65]
wire debug_reset_syncd; // @[Periphery.scala:290:40]
wire debug_reset; // @[Periphery.scala:288:27]
wire _debug_reset_syncd_WIRE; // @[ShiftReg.scala:48:24]
assign debug_reset_syncd = ~_debug_reset_syncd_WIRE; // @[ShiftReg.scala:48:24]
assign debug_reset = debug_reset_syncd; // @[Periphery.scala:288:27, :290:40]
wire dmactiveAck; // @[ShiftReg.scala:48:24]
reg clock_en; // @[Periphery.scala:298:29]
wire _jtag_wire_TCK_T; // @[IOCell.scala:248:61]
wire jtag_wire_TCK; // @[IOBinders.scala:339:31]
wire jtag_wire_TMS; // @[IOBinders.scala:339:31]
wire jtag_wire_TDI; // @[IOBinders.scala:339:31]
wire jtag_wire_TDO; // @[IOBinders.scala:339:31]
assign jtag_wire_TCK = _jtag_wire_TCK_T; // @[IOCell.scala:248:61]
wire _iocell_jtag_TCK_io_pad_T_1 = _iocell_jtag_TCK_io_pad_T; // @[IOCell.scala:248:{44,51}]
wire _iocell_clock_tap_io_o_T; // @[IOCell.scala:248:44]
wire _iocell_clock_tap_io_o_T_1 = _iocell_clock_tap_io_o_T; // @[IOCell.scala:248:{44,51}]
wire _iocell_serial_tl_0_clock_in_io_pad_T_1 = _iocell_serial_tl_0_clock_in_io_pad_T; // @[IOCell.scala:248:{44,51}]
wire [1:0] serial_tl_0_out_bits_phit_lo_lo_lo_lo = {_iocell_serial_tl_0_out_bits_phit_1_pad, _iocell_serial_tl_0_out_bits_phit_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_lo_lo_hi = {_iocell_serial_tl_0_out_bits_phit_3_pad, _iocell_serial_tl_0_out_bits_phit_2_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_lo_lo_lo = {serial_tl_0_out_bits_phit_lo_lo_lo_hi, serial_tl_0_out_bits_phit_lo_lo_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_lo_hi_lo = {_iocell_serial_tl_0_out_bits_phit_5_pad, _iocell_serial_tl_0_out_bits_phit_4_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_lo_hi_hi = {_iocell_serial_tl_0_out_bits_phit_7_pad, _iocell_serial_tl_0_out_bits_phit_6_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_lo_lo_hi = {serial_tl_0_out_bits_phit_lo_lo_hi_hi, serial_tl_0_out_bits_phit_lo_lo_hi_lo}; // @[IOCell.scala:312:31]
wire [7:0] serial_tl_0_out_bits_phit_lo_lo = {serial_tl_0_out_bits_phit_lo_lo_hi, serial_tl_0_out_bits_phit_lo_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_hi_lo_lo = {_iocell_serial_tl_0_out_bits_phit_9_pad, _iocell_serial_tl_0_out_bits_phit_8_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_hi_lo_hi = {_iocell_serial_tl_0_out_bits_phit_11_pad, _iocell_serial_tl_0_out_bits_phit_10_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_lo_hi_lo = {serial_tl_0_out_bits_phit_lo_hi_lo_hi, serial_tl_0_out_bits_phit_lo_hi_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_hi_hi_lo = {_iocell_serial_tl_0_out_bits_phit_13_pad, _iocell_serial_tl_0_out_bits_phit_12_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_hi_hi_hi = {_iocell_serial_tl_0_out_bits_phit_15_pad, _iocell_serial_tl_0_out_bits_phit_14_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_lo_hi_hi = {serial_tl_0_out_bits_phit_lo_hi_hi_hi, serial_tl_0_out_bits_phit_lo_hi_hi_lo}; // @[IOCell.scala:312:31]
wire [7:0] serial_tl_0_out_bits_phit_lo_hi = {serial_tl_0_out_bits_phit_lo_hi_hi, serial_tl_0_out_bits_phit_lo_hi_lo}; // @[IOCell.scala:312:31]
wire [15:0] serial_tl_0_out_bits_phit_lo = {serial_tl_0_out_bits_phit_lo_hi, serial_tl_0_out_bits_phit_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_lo_lo_lo = {_iocell_serial_tl_0_out_bits_phit_17_pad, _iocell_serial_tl_0_out_bits_phit_16_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_lo_lo_hi = {_iocell_serial_tl_0_out_bits_phit_19_pad, _iocell_serial_tl_0_out_bits_phit_18_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_hi_lo_lo = {serial_tl_0_out_bits_phit_hi_lo_lo_hi, serial_tl_0_out_bits_phit_hi_lo_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_lo_hi_lo = {_iocell_serial_tl_0_out_bits_phit_21_pad, _iocell_serial_tl_0_out_bits_phit_20_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_lo_hi_hi = {_iocell_serial_tl_0_out_bits_phit_23_pad, _iocell_serial_tl_0_out_bits_phit_22_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_hi_lo_hi = {serial_tl_0_out_bits_phit_hi_lo_hi_hi, serial_tl_0_out_bits_phit_hi_lo_hi_lo}; // @[IOCell.scala:312:31]
wire [7:0] serial_tl_0_out_bits_phit_hi_lo = {serial_tl_0_out_bits_phit_hi_lo_hi, serial_tl_0_out_bits_phit_hi_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_hi_lo_lo = {_iocell_serial_tl_0_out_bits_phit_25_pad, _iocell_serial_tl_0_out_bits_phit_24_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_hi_lo_hi = {_iocell_serial_tl_0_out_bits_phit_27_pad, _iocell_serial_tl_0_out_bits_phit_26_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_hi_hi_lo = {serial_tl_0_out_bits_phit_hi_hi_lo_hi, serial_tl_0_out_bits_phit_hi_hi_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_hi_hi_lo = {_iocell_serial_tl_0_out_bits_phit_29_pad, _iocell_serial_tl_0_out_bits_phit_28_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_hi_hi_hi = {_iocell_serial_tl_0_out_bits_phit_31_pad, _iocell_serial_tl_0_out_bits_phit_30_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_hi_hi_hi = {serial_tl_0_out_bits_phit_hi_hi_hi_hi, serial_tl_0_out_bits_phit_hi_hi_hi_lo}; // @[IOCell.scala:312:31]
wire [7:0] serial_tl_0_out_bits_phit_hi_hi = {serial_tl_0_out_bits_phit_hi_hi_hi, serial_tl_0_out_bits_phit_hi_hi_lo}; // @[IOCell.scala:312:31]
wire [15:0] serial_tl_0_out_bits_phit_hi = {serial_tl_0_out_bits_phit_hi_hi, serial_tl_0_out_bits_phit_hi_lo}; // @[IOCell.scala:312:31]
assign _serial_tl_0_out_bits_phit_T = {serial_tl_0_out_bits_phit_hi, serial_tl_0_out_bits_phit_lo}; // @[IOCell.scala:312:31]
assign serial_tl_0_out_bits_phit_0 = _serial_tl_0_out_bits_phit_T; // @[IOCell.scala:312:31]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_lo_lo_lo = {_iocell_serial_tl_0_in_bits_phit_1_i, _iocell_serial_tl_0_in_bits_phit_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_lo_lo_hi = {_iocell_serial_tl_0_in_bits_phit_3_i, _iocell_serial_tl_0_in_bits_phit_2_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_lo_lo_lo = {system_serial_tl_0_in_bits_phit_lo_lo_lo_hi, system_serial_tl_0_in_bits_phit_lo_lo_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_lo_hi_lo = {_iocell_serial_tl_0_in_bits_phit_5_i, _iocell_serial_tl_0_in_bits_phit_4_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_lo_hi_hi = {_iocell_serial_tl_0_in_bits_phit_7_i, _iocell_serial_tl_0_in_bits_phit_6_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_lo_lo_hi = {system_serial_tl_0_in_bits_phit_lo_lo_hi_hi, system_serial_tl_0_in_bits_phit_lo_lo_hi_lo}; // @[IOCell.scala:295:32]
wire [7:0] system_serial_tl_0_in_bits_phit_lo_lo = {system_serial_tl_0_in_bits_phit_lo_lo_hi, system_serial_tl_0_in_bits_phit_lo_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_hi_lo_lo = {_iocell_serial_tl_0_in_bits_phit_9_i, _iocell_serial_tl_0_in_bits_phit_8_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_hi_lo_hi = {_iocell_serial_tl_0_in_bits_phit_11_i, _iocell_serial_tl_0_in_bits_phit_10_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_lo_hi_lo = {system_serial_tl_0_in_bits_phit_lo_hi_lo_hi, system_serial_tl_0_in_bits_phit_lo_hi_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_hi_hi_lo = {_iocell_serial_tl_0_in_bits_phit_13_i, _iocell_serial_tl_0_in_bits_phit_12_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_hi_hi_hi = {_iocell_serial_tl_0_in_bits_phit_15_i, _iocell_serial_tl_0_in_bits_phit_14_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_lo_hi_hi = {system_serial_tl_0_in_bits_phit_lo_hi_hi_hi, system_serial_tl_0_in_bits_phit_lo_hi_hi_lo}; // @[IOCell.scala:295:32]
wire [7:0] system_serial_tl_0_in_bits_phit_lo_hi = {system_serial_tl_0_in_bits_phit_lo_hi_hi, system_serial_tl_0_in_bits_phit_lo_hi_lo}; // @[IOCell.scala:295:32]
wire [15:0] system_serial_tl_0_in_bits_phit_lo = {system_serial_tl_0_in_bits_phit_lo_hi, system_serial_tl_0_in_bits_phit_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_lo_lo_lo = {_iocell_serial_tl_0_in_bits_phit_17_i, _iocell_serial_tl_0_in_bits_phit_16_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_lo_lo_hi = {_iocell_serial_tl_0_in_bits_phit_19_i, _iocell_serial_tl_0_in_bits_phit_18_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_hi_lo_lo = {system_serial_tl_0_in_bits_phit_hi_lo_lo_hi, system_serial_tl_0_in_bits_phit_hi_lo_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_lo_hi_lo = {_iocell_serial_tl_0_in_bits_phit_21_i, _iocell_serial_tl_0_in_bits_phit_20_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_lo_hi_hi = {_iocell_serial_tl_0_in_bits_phit_23_i, _iocell_serial_tl_0_in_bits_phit_22_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_hi_lo_hi = {system_serial_tl_0_in_bits_phit_hi_lo_hi_hi, system_serial_tl_0_in_bits_phit_hi_lo_hi_lo}; // @[IOCell.scala:295:32]
wire [7:0] system_serial_tl_0_in_bits_phit_hi_lo = {system_serial_tl_0_in_bits_phit_hi_lo_hi, system_serial_tl_0_in_bits_phit_hi_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_hi_lo_lo = {_iocell_serial_tl_0_in_bits_phit_25_i, _iocell_serial_tl_0_in_bits_phit_24_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_hi_lo_hi = {_iocell_serial_tl_0_in_bits_phit_27_i, _iocell_serial_tl_0_in_bits_phit_26_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_hi_hi_lo = {system_serial_tl_0_in_bits_phit_hi_hi_lo_hi, system_serial_tl_0_in_bits_phit_hi_hi_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_hi_hi_lo = {_iocell_serial_tl_0_in_bits_phit_29_i, _iocell_serial_tl_0_in_bits_phit_28_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_hi_hi_hi = {_iocell_serial_tl_0_in_bits_phit_31_i, _iocell_serial_tl_0_in_bits_phit_30_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_hi_hi_hi = {system_serial_tl_0_in_bits_phit_hi_hi_hi_hi, system_serial_tl_0_in_bits_phit_hi_hi_hi_lo}; // @[IOCell.scala:295:32]
wire [7:0] system_serial_tl_0_in_bits_phit_hi_hi = {system_serial_tl_0_in_bits_phit_hi_hi_hi, system_serial_tl_0_in_bits_phit_hi_hi_lo}; // @[IOCell.scala:295:32]
wire [15:0] system_serial_tl_0_in_bits_phit_hi = {system_serial_tl_0_in_bits_phit_hi_hi, system_serial_tl_0_in_bits_phit_hi_lo}; // @[IOCell.scala:295:32]
wire [31:0] _system_serial_tl_0_in_bits_phit_T = {system_serial_tl_0_in_bits_phit_hi, system_serial_tl_0_in_bits_phit_lo}; // @[IOCell.scala:295:32]
always @(posedge clockSinkNodeIn_clock or posedge debug_reset) begin // @[Periphery.scala:288:27]
if (debug_reset) // @[Periphery.scala:288:27]
clock_en <= 1'h1; // @[Periphery.scala:298:29]
else // @[MixedNode.scala:551:17]
clock_en <= dmactiveAck; // @[ShiftReg.scala:48:24]
always @(posedge, posedge)
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
package constellation.channel
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.util._
import constellation.noc.{HasNoCParams}
class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams {
val io = IO(new Bundle {
val in = Input(new Channel(cParam))
})
val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B }))
for (i <- 0 until cParam.srcSpeedup) {
val flit = io.in.flit(i)
when (flit.valid) {
when (flit.bits.head) {
in_flight(flit.bits.virt_channel_id) := true.B
assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken")
}
when (flit.bits.tail) {
in_flight(flit.bits.virt_channel_id) := false.B
}
}
val possibleFlows = cParam.possibleFlows
when (flit.valid && flit.bits.head) {
cParam match {
case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) =>
assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
}
}
}
File Types.scala:
package constellation.routing
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import constellation.noc.{HasNoCParams}
import constellation.channel.{Flit}
/** A representation for 1 specific virtual channel in wormhole routing
*
* @param src the source node
* @param vc ID for the virtual channel
* @param dst the destination node
* @param n_vc the number of virtual channels
*/
// BEGIN: ChannelRoutingInfo
case class ChannelRoutingInfo(
src: Int,
dst: Int,
vc: Int,
n_vc: Int
) {
// END: ChannelRoutingInfo
require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this")
require (!(src == -1 && dst == -1), s"Illegal $this")
require (vc < n_vc, s"Illegal $this")
val isIngress = src == -1
val isEgress = dst == -1
}
/** Represents the properties of a packet that are relevant for routing
* ingressId and egressId uniquely identify a flow, but vnet and dst are used here
* to simplify the implementation of routingrelations
*
* @param ingressId packet's source ingress point
* @param egressId packet's destination egress point
* @param vNet virtual subnetwork identifier
* @param dst packet's destination node ID
*/
// BEGIN: FlowRoutingInfo
case class FlowRoutingInfo(
ingressId: Int,
egressId: Int,
vNetId: Int,
ingressNode: Int,
ingressNodeId: Int,
egressNode: Int,
egressNodeId: Int,
fifo: Boolean
) {
// END: FlowRoutingInfo
def isFlow(f: FlowRoutingBundle): Bool = {
(f.ingress_node === ingressNode.U &&
f.egress_node === egressNode.U &&
f.ingress_node_id === ingressNodeId.U &&
f.egress_node_id === egressNodeId.U)
}
def asLiteral(b: FlowRoutingBundle): BigInt = {
Seq(
(vNetId , b.vnet_id),
(ingressNode , b.ingress_node),
(ingressNodeId , b.ingress_node_id),
(egressNode , b.egress_node),
(egressNodeId , b.egress_node_id)
).foldLeft(0)((l, t) => {
(l << t._2.getWidth) | t._1
})
}
}
class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams {
// Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination
// This simplifies the routing tables
val vnet_id = UInt(log2Ceil(nVirtualNetworks).W)
val ingress_node = UInt(log2Ceil(nNodes).W)
val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W)
val egress_node = UInt(log2Ceil(nNodes).W)
val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W)
}
|
module NoCMonitor_39( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 2'h1; // @[Monitor.scala:21:46]
wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 2'h2; // @[Monitor.scala:21:46]
|
Generate the Verilog code corresponding to the following Chisel files.
File core.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISC-V Processor Core
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// BOOM has the following (conceptual) stages:
// if0 - Instruction Fetch 0 (next-pc select)
// if1 - Instruction Fetch 1 (I$ access)
// if2 - Instruction Fetch 2 (instruction return)
// if3 - Instruction Fetch 3 (enqueue to fetch buffer)
// if4 - Instruction Fetch 4 (redirect from bpd)
// dec - Decode
// ren - Rename1
// dis - Rename2/Dispatch
// iss - Issue
// rrd - Register Read
// exe - Execute
// mem - Memory
// sxt - Sign-extend
// wb - Writeback
// com - Commit
package boom.v3.exu
import java.nio.file.{Paths}
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.tile.{TraceBundle}
import freechips.rocketchip.rocket.{Causes, PRV, TracedInstruction}
import freechips.rocketchip.util.{Str, UIntIsOneOf, CoreMonitorBundle}
import freechips.rocketchip.devices.tilelink.{PLICConsts, CLINTConsts}
import boom.v3.common._
import boom.v3.ifu.{GlobalHistory, HasBoomFrontendParameters}
import boom.v3.exu.FUConstants._
import boom.v3.util._
/**
* Top level core object that connects the Frontend to the rest of the pipeline.
*/
class BoomCore()(implicit p: Parameters) extends BoomModule
with HasBoomFrontendParameters // TODO: Don't add this trait
{
val io = IO(new Bundle {
val hartid = Input(UInt(hartIdLen.W))
val interrupts = Input(new freechips.rocketchip.rocket.CoreInterrupts(false))
val ifu = new boom.v3.ifu.BoomFrontendIO
val ptw = Flipped(new freechips.rocketchip.rocket.DatapathPTWIO())
val rocc = Flipped(new freechips.rocketchip.tile.RoCCCoreIO())
val lsu = Flipped(new boom.v3.lsu.LSUCoreIO)
val ptw_tlb = new freechips.rocketchip.rocket.TLBPTWIO()
val trace = Output(new TraceBundle)
val fcsr_rm = UInt(freechips.rocketchip.tile.FPConstants.RM_SZ.W)
})
io.ptw_tlb := DontCare
io.ptw := DontCare
io.ifu := DontCare
//**********************************
// construct all of the modules
// Only holds integer-registerfile execution units.
val exe_units = new boom.v3.exu.ExecutionUnits(fpu=false)
val jmp_unit_idx = exe_units.jmp_unit_idx
val jmp_unit = exe_units(jmp_unit_idx)
// Meanwhile, the FP pipeline holds the FP issue window, FP regfile, and FP arithmetic units.
var fp_pipeline: FpPipeline = null
if (usingFPU) fp_pipeline = Module(new FpPipeline)
// ********************************************************
// Clear fp_pipeline before use
if (usingFPU) {
fp_pipeline.io.ll_wports := DontCare
fp_pipeline.io.wb_valids := DontCare
fp_pipeline.io.wb_pdsts := DontCare
}
val numIrfWritePorts = exe_units.numIrfWritePorts + memWidth
val numLlIrfWritePorts = exe_units.numLlIrfWritePorts
val numIrfReadPorts = exe_units.numIrfReadPorts
val numFastWakeupPorts = exe_units.count(_.bypassable)
val numAlwaysBypassable = exe_units.count(_.alwaysBypassable)
val numIntIssueWakeupPorts = numIrfWritePorts + numFastWakeupPorts - numAlwaysBypassable // + memWidth for ll_wb
val numIntRenameWakeupPorts = numIntIssueWakeupPorts
val numFpWakeupPorts = if (usingFPU) fp_pipeline.io.wakeups.length else 0
val decode_units = for (w <- 0 until decodeWidth) yield { val d = Module(new DecodeUnit); d }
val dec_brmask_logic = Module(new BranchMaskGenerationLogic(coreWidth))
val rename_stage = Module(new RenameStage(coreWidth, numIntPhysRegs, numIntRenameWakeupPorts, false))
val fp_rename_stage = if (usingFPU) Module(new RenameStage(coreWidth, numFpPhysRegs, numFpWakeupPorts, true)) else null
val pred_rename_stage = Module(new PredRenameStage(coreWidth, ftqSz, 1))
val rename_stages = if (usingFPU) Seq(rename_stage, fp_rename_stage, pred_rename_stage) else Seq(rename_stage, pred_rename_stage)
val mem_iss_unit = Module(new IssueUnitCollapsing(memIssueParam, numIntIssueWakeupPorts))
mem_iss_unit.suggestName("mem_issue_unit")
val int_iss_unit = Module(new IssueUnitCollapsing(intIssueParam, numIntIssueWakeupPorts))
int_iss_unit.suggestName("int_issue_unit")
val issue_units = Seq(mem_iss_unit, int_iss_unit)
val dispatcher = Module(new BasicDispatcher)
val iregfile = Module(new RegisterFileSynthesizable(
numIntPhysRegs,
numIrfReadPorts,
numIrfWritePorts,
xLen,
Seq.fill(memWidth) {true} ++ exe_units.bypassable_write_port_mask)) // bypassable ll_wb
val pregfile = Module(new RegisterFileSynthesizable(
ftqSz,
exe_units.numIrfReaders,
1,
1,
Seq(true))) // The jmp unit is always bypassable
pregfile.io := DontCare // Only use the IO if enableSFBOpt
// wb arbiter for the 0th ll writeback
// TODO: should this be a multi-arb?
val ll_wbarb = Module(new Arbiter(new ExeUnitResp(xLen), 1 +
(if (usingFPU) 1 else 0) +
(if (usingRoCC) 1 else 0)))
val iregister_read = Module(new RegisterRead(
issue_units.map(_.issueWidth).sum,
exe_units.withFilter(_.readsIrf).map(_.supportedFuncUnits).toSeq,
numIrfReadPorts,
exe_units.withFilter(_.readsIrf).map(x => 2).toSeq,
exe_units.numTotalBypassPorts,
jmp_unit.numBypassStages,
xLen))
val rob = Module(new Rob(
numIrfWritePorts + numFpWakeupPorts, // +memWidth for ll writebacks
numFpWakeupPorts))
// Used to wakeup registers in rename and issue. ROB needs to listen to something else.
val int_iss_wakeups = Wire(Vec(numIntIssueWakeupPorts, Valid(new ExeUnitResp(xLen))))
val int_ren_wakeups = Wire(Vec(numIntRenameWakeupPorts, Valid(new ExeUnitResp(xLen))))
val pred_wakeup = Wire(Valid(new ExeUnitResp(1)))
require (exe_units.length == issue_units.map(_.issueWidth).sum)
//***********************************
// Pipeline State Registers and Wires
// Decode/Rename1 Stage
val dec_valids = Wire(Vec(coreWidth, Bool())) // are the decoded instruction valid? It may be held up though.
val dec_uops = Wire(Vec(coreWidth, new MicroOp()))
val dec_fire = Wire(Vec(coreWidth, Bool())) // can the instruction fire beyond decode?
// (can still be stopped in ren or dis)
val dec_ready = Wire(Bool())
val dec_xcpts = Wire(Vec(coreWidth, Bool()))
val ren_stalls = Wire(Vec(coreWidth, Bool()))
// Rename2/Dispatch stage
val dis_valids = Wire(Vec(coreWidth, Bool()))
val dis_uops = Wire(Vec(coreWidth, new MicroOp))
val dis_fire = Wire(Vec(coreWidth, Bool()))
val dis_ready = Wire(Bool())
// Issue Stage/Register Read
val iss_valids = Wire(Vec(exe_units.numIrfReaders, Bool()))
val iss_uops = Wire(Vec(exe_units.numIrfReaders, new MicroOp()))
val bypasses = Wire(Vec(exe_units.numTotalBypassPorts, Valid(new ExeUnitResp(xLen))))
val pred_bypasses = Wire(Vec(jmp_unit.numBypassStages, Valid(new ExeUnitResp(1))))
require(jmp_unit.bypassable)
// --------------------------------------
// Dealing with branch resolutions
// The individual branch resolutions from each ALU
val brinfos = Reg(Vec(coreWidth, new BrResolutionInfo()))
// "Merged" branch update info from all ALUs
// brmask contains masks for rapidly clearing mispredicted instructions
// brindices contains indices to reset pointers for allocated structures
// brindices is delayed a cycle
val brupdate = Wire(new BrUpdateInfo)
val b1 = Wire(new BrUpdateMasks)
val b2 = Reg(new BrResolutionInfo)
brupdate.b1 := b1
brupdate.b2 := b2
for ((b, a) <- brinfos zip exe_units.alu_units) {
b := a.io.brinfo
b.valid := a.io.brinfo.valid && !rob.io.flush.valid
}
b1.resolve_mask := brinfos.map(x => x.valid << x.uop.br_tag).reduce(_|_)
b1.mispredict_mask := brinfos.map(x => (x.valid && x.mispredict) << x.uop.br_tag).reduce(_|_)
// Find the oldest mispredict and use it to update indices
var mispredict_val = false.B
var oldest_mispredict = brinfos(0)
for (b <- brinfos) {
val use_this_mispredict = !mispredict_val ||
b.valid && b.mispredict && IsOlder(b.uop.rob_idx, oldest_mispredict.uop.rob_idx, rob.io.rob_head_idx)
mispredict_val = mispredict_val || (b.valid && b.mispredict)
oldest_mispredict = Mux(use_this_mispredict, b, oldest_mispredict)
}
b2.mispredict := mispredict_val
b2.cfi_type := oldest_mispredict.cfi_type
b2.taken := oldest_mispredict.taken
b2.pc_sel := oldest_mispredict.pc_sel
b2.uop := UpdateBrMask(brupdate, oldest_mispredict.uop)
b2.jalr_target := RegNext(jmp_unit.io.brinfo.jalr_target)
b2.target_offset := oldest_mispredict.target_offset
val oldest_mispredict_ftq_idx = oldest_mispredict.uop.ftq_idx
assert (!((brupdate.b1.mispredict_mask =/= 0.U || brupdate.b2.mispredict)
&& rob.io.commit.rollback), "Can't have a mispredict during rollback.")
io.ifu.brupdate := brupdate
for (eu <- exe_units) {
eu.io.brupdate := brupdate
}
if (usingFPU) {
fp_pipeline.io.brupdate := brupdate
}
// Load/Store Unit & ExeUnits
val mem_units = exe_units.memory_units
val mem_resps = mem_units.map(_.io.ll_iresp)
for (i <- 0 until memWidth) {
mem_units(i).io.lsu_io <> io.lsu.exe(i)
}
//-------------------------------------------------------------
// Uarch Hardware Performance Events (HPEs)
val perfEvents = new freechips.rocketchip.rocket.EventSets(Seq(
new freechips.rocketchip.rocket.EventSet((mask, hits) => (mask & hits).orR, Seq(
("exception", () => rob.io.com_xcpt.valid),
("nop", () => false.B),
("nop", () => false.B),
("nop", () => false.B))),
new freechips.rocketchip.rocket.EventSet((mask, hits) => (mask & hits).orR, Seq(
// ("I$ blocked", () => icache_blocked),
("nop", () => false.B),
("branch misprediction", () => b2.mispredict),
("control-flow target misprediction", () => b2.mispredict &&
b2.cfi_type === CFI_JALR),
("flush", () => rob.io.flush.valid),
("branch resolved", () => b2.valid)
)),
new freechips.rocketchip.rocket.EventSet((mask, hits) => (mask & hits).orR, Seq(
("I$ miss", () => io.ifu.perf.acquire),
("D$ miss", () => io.lsu.perf.acquire),
("D$ release", () => io.lsu.perf.release),
("ITLB miss", () => io.ifu.perf.tlbMiss),
("DTLB miss", () => io.lsu.perf.tlbMiss),
("L2 TLB miss", () => io.ptw.perf.l2miss)))))
val csr = Module(new freechips.rocketchip.rocket.CSRFile(perfEvents, boomParams.customCSRs.decls))
csr.io.inst foreach { c => c := DontCare }
csr.io.rocc_interrupt := io.rocc.interrupt
csr.io.mhtinst_read_pseudo := false.B
val custom_csrs = Wire(new BoomCustomCSRs)
custom_csrs.csrs.foreach { c => c.stall := false.B; c.set := false.B; c.sdata := DontCare }
(custom_csrs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs }
//val icache_blocked = !(io.ifu.fetchpacket.valid || RegNext(io.ifu.fetchpacket.valid))
val icache_blocked = false.B
csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) }
//****************************************
// Time Stamp Counter & Retired Instruction Counter
// (only used for printf and vcd dumps - the actual counters are in the CSRFile)
val debug_tsc_reg = RegInit(0.U(xLen.W))
val debug_irt_reg = RegInit(0.U(xLen.W))
val debug_brs = Reg(Vec(4, UInt(xLen.W)))
val debug_jals = Reg(Vec(4, UInt(xLen.W)))
val debug_jalrs = Reg(Vec(4, UInt(xLen.W)))
for (j <- 0 until 4) {
debug_brs(j) := debug_brs(j) + PopCount(VecInit((0 until coreWidth) map {i =>
rob.io.commit.arch_valids(i) &&
(rob.io.commit.uops(i).debug_fsrc === j.U) &&
rob.io.commit.uops(i).is_br
}))
debug_jals(j) := debug_jals(j) + PopCount(VecInit((0 until coreWidth) map {i =>
rob.io.commit.arch_valids(i) &&
(rob.io.commit.uops(i).debug_fsrc === j.U) &&
rob.io.commit.uops(i).is_jal
}))
debug_jalrs(j) := debug_jalrs(j) + PopCount(VecInit((0 until coreWidth) map {i =>
rob.io.commit.arch_valids(i) &&
(rob.io.commit.uops(i).debug_fsrc === j.U) &&
rob.io.commit.uops(i).is_jalr
}))
}
dontTouch(debug_brs)
dontTouch(debug_jals)
dontTouch(debug_jalrs)
debug_tsc_reg := debug_tsc_reg + 1.U
debug_irt_reg := debug_irt_reg + PopCount(rob.io.commit.arch_valids.asUInt)
dontTouch(debug_tsc_reg)
dontTouch(debug_irt_reg)
//****************************************
// Print-out information about the machine
val issStr =
if (enableAgePriorityIssue) " (Age-based Priority)"
else " (Unordered Priority)"
// val btbStr =
// if (enableBTB) ("" + boomParams.btb.nSets * boomParams.btb.nWays + " entries (" + boomParams.btb.nSets + " x " + boomParams.btb.nWays + " ways)")
// else 0
val btbStr = ""
val fpPipelineStr =
if (usingFPU) fp_pipeline.toString
else ""
override def toString: String =
(BoomCoreStringPrefix("====Overall Core Params====") + "\n"
+ exe_units.toString + "\n"
+ fpPipelineStr + "\n"
+ rob.toString + "\n"
+ BoomCoreStringPrefix(
"===Other Core Params===",
"Fetch Width : " + fetchWidth,
"Decode Width : " + coreWidth,
"Issue Width : " + issueParams.map(_.issueWidth).sum,
"ROB Size : " + numRobEntries,
"Issue Window Size : " + issueParams.map(_.numEntries) + issStr,
"Load/Store Unit Size : " + numLdqEntries + "/" + numStqEntries,
"Num Int Phys Registers: " + numIntPhysRegs,
"Num FP Phys Registers: " + numFpPhysRegs,
"Max Branch Count : " + maxBrCount)
+ iregfile.toString + "\n"
+ BoomCoreStringPrefix(
"Num Slow Wakeup Ports : " + numIrfWritePorts,
"Num Fast Wakeup Ports : " + exe_units.count(_.bypassable),
"Num Bypass Ports : " + exe_units.numTotalBypassPorts) + "\n"
+ BoomCoreStringPrefix(
"DCache Ways : " + dcacheParams.nWays,
"DCache Sets : " + dcacheParams.nSets,
"DCache nMSHRs : " + dcacheParams.nMSHRs,
"ICache Ways : " + icacheParams.nWays,
"ICache Sets : " + icacheParams.nSets,
"D-TLB Ways : " + dcacheParams.nTLBWays,
"I-TLB Ways : " + icacheParams.nTLBWays,
"Paddr Bits : " + paddrBits,
"Vaddr Bits : " + vaddrBits) + "\n"
+ BoomCoreStringPrefix(
"Using FPU Unit? : " + usingFPU.toString,
"Using FDivSqrt? : " + usingFDivSqrt.toString,
"Using VM? : " + usingVM.toString) + "\n")
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Fetch Stage/Frontend ****
//-------------------------------------------------------------
//-------------------------------------------------------------
io.ifu.redirect_val := false.B
io.ifu.redirect_flush := false.B
// Breakpoint info
io.ifu.status := csr.io.status
io.ifu.bp := csr.io.bp
io.ifu.mcontext := csr.io.mcontext
io.ifu.scontext := csr.io.scontext
io.ifu.flush_icache := (0 until coreWidth).map { i =>
(rob.io.commit.arch_valids(i) && rob.io.commit.uops(i).is_fencei) ||
(RegNext(dec_valids(i) && dec_uops(i).is_jalr && csr.io.status.debug))
}.reduce(_||_)
// TODO FIX THIS HACK
// The below code works because of two quirks with the flush mechanism
// 1 ) All flush_on_commit instructions are also is_unique,
// In the future, this constraint will be relaxed.
// 2 ) We send out flush signals one cycle after the commit signal. We need to
// mux between one/two cycle delay for the following cases:
// ERETs are reported to the CSR two cycles before we send the flush
// Exceptions are reported to the CSR on the cycle we send the flush
// This discrepency should be resolved elsewhere.
when (RegNext(rob.io.flush.valid)) {
io.ifu.redirect_val := true.B
io.ifu.redirect_flush := true.B
val flush_typ = RegNext(rob.io.flush.bits.flush_typ)
// Clear the global history when we flush the ROB (exceptions, AMOs, unique instructions, etc.)
val new_ghist = WireInit((0.U).asTypeOf(new GlobalHistory))
new_ghist.current_saw_branch_not_taken := true.B
new_ghist.ras_idx := io.ifu.get_pc(0).entry.ras_idx
io.ifu.redirect_ghist := new_ghist
when (FlushTypes.useCsrEvec(flush_typ)) {
io.ifu.redirect_pc := Mux(flush_typ === FlushTypes.eret,
RegNext(RegNext(csr.io.evec)),
csr.io.evec)
} .otherwise {
val flush_pc = (AlignPCToBoundary(io.ifu.get_pc(0).pc, icBlockBytes)
+ RegNext(rob.io.flush.bits.pc_lob)
- Mux(RegNext(rob.io.flush.bits.edge_inst), 2.U, 0.U))
val flush_pc_next = flush_pc + Mux(RegNext(rob.io.flush.bits.is_rvc), 2.U, 4.U)
io.ifu.redirect_pc := Mux(FlushTypes.useSamePC(flush_typ),
flush_pc, flush_pc_next)
}
io.ifu.redirect_ftq_idx := RegNext(rob.io.flush.bits.ftq_idx)
} .elsewhen (brupdate.b2.mispredict && !RegNext(rob.io.flush.valid)) {
val block_pc = AlignPCToBoundary(io.ifu.get_pc(1).pc, icBlockBytes)
val uop_maybe_pc = block_pc | brupdate.b2.uop.pc_lob
val npc = uop_maybe_pc + Mux(brupdate.b2.uop.is_rvc || brupdate.b2.uop.edge_inst, 2.U, 4.U)
val jal_br_target = Wire(UInt(vaddrBitsExtended.W))
jal_br_target := (uop_maybe_pc.asSInt + brupdate.b2.target_offset +
(Fill(vaddrBitsExtended-1, brupdate.b2.uop.edge_inst) << 1).asSInt).asUInt
val bj_addr = Mux(brupdate.b2.cfi_type === CFI_JALR, brupdate.b2.jalr_target, jal_br_target)
val mispredict_target = Mux(brupdate.b2.pc_sel === PC_PLUS4, npc, bj_addr)
io.ifu.redirect_val := true.B
io.ifu.redirect_pc := mispredict_target
io.ifu.redirect_flush := true.B
io.ifu.redirect_ftq_idx := brupdate.b2.uop.ftq_idx
val use_same_ghist = (brupdate.b2.cfi_type === CFI_BR &&
!brupdate.b2.taken &&
bankAlign(block_pc) === bankAlign(npc))
val ftq_entry = io.ifu.get_pc(1).entry
val cfi_idx = (brupdate.b2.uop.pc_lob ^
Mux(ftq_entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U))(log2Ceil(fetchWidth), 1)
val ftq_ghist = io.ifu.get_pc(1).ghist
val next_ghist = ftq_ghist.update(
ftq_entry.br_mask.asUInt,
brupdate.b2.taken,
brupdate.b2.cfi_type === CFI_BR,
cfi_idx,
true.B,
io.ifu.get_pc(1).pc,
ftq_entry.cfi_is_call && ftq_entry.cfi_idx.bits === cfi_idx,
ftq_entry.cfi_is_ret && ftq_entry.cfi_idx.bits === cfi_idx)
io.ifu.redirect_ghist := Mux(
use_same_ghist,
ftq_ghist,
next_ghist)
io.ifu.redirect_ghist.current_saw_branch_not_taken := use_same_ghist
} .elsewhen (rob.io.flush_frontend || brupdate.b1.mispredict_mask =/= 0.U) {
io.ifu.redirect_flush := true.B
}
// Tell the FTQ it can deallocate entries by passing youngest ftq_idx.
val youngest_com_idx = (coreWidth-1).U - PriorityEncoder(rob.io.commit.valids.reverse)
io.ifu.commit.valid := rob.io.commit.valids.reduce(_|_) || rob.io.com_xcpt.valid
io.ifu.commit.bits := Mux(rob.io.com_xcpt.valid,
rob.io.com_xcpt.bits.ftq_idx,
rob.io.commit.uops(youngest_com_idx).ftq_idx)
assert(!(rob.io.commit.valids.reduce(_|_) && rob.io.com_xcpt.valid),
"ROB can't commit and except in same cycle!")
for (i <- 0 until memWidth) {
when (RegNext(io.lsu.exe(i).req.bits.sfence.valid)) {
io.ifu.sfence := RegNext(io.lsu.exe(i).req.bits.sfence)
}
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Branch Prediction ****
//-------------------------------------------------------------
//-------------------------------------------------------------
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Decode Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
// track mask of finished instructions in the bundle
// use this to mask out insts coming from FetchBuffer that have been finished
// for example, back pressure may cause us to only issue some instructions from FetchBuffer
// but on the next cycle, we only want to retry a subset
val dec_finished_mask = RegInit(0.U(coreWidth.W))
//-------------------------------------------------------------
// Pull out instructions and send to the Decoders
io.ifu.fetchpacket.ready := dec_ready
val dec_fbundle = io.ifu.fetchpacket.bits
//-------------------------------------------------------------
// Decoders
for (w <- 0 until coreWidth) {
dec_valids(w) := io.ifu.fetchpacket.valid && dec_fbundle.uops(w).valid &&
!dec_finished_mask(w)
decode_units(w).io.enq.uop := dec_fbundle.uops(w).bits
decode_units(w).io.status := csr.io.status
decode_units(w).io.csr_decode <> csr.io.decode(w)
decode_units(w).io.interrupt := csr.io.interrupt
decode_units(w).io.interrupt_cause := csr.io.interrupt_cause
dec_uops(w) := decode_units(w).io.deq.uop
}
//-------------------------------------------------------------
// FTQ GetPC Port Arbitration
val jmp_pc_req = Wire(Decoupled(UInt(log2Ceil(ftqSz).W)))
val xcpt_pc_req = Wire(Decoupled(UInt(log2Ceil(ftqSz).W)))
val flush_pc_req = Wire(Decoupled(UInt(log2Ceil(ftqSz).W)))
val ftq_arb = Module(new Arbiter(UInt(log2Ceil(ftqSz).W), 3))
// Order by the oldest. Flushes come from the oldest instructions in pipe
// Decoding exceptions come from youngest
ftq_arb.io.in(0) <> flush_pc_req
ftq_arb.io.in(1) <> jmp_pc_req
ftq_arb.io.in(2) <> xcpt_pc_req
// Hookup FTQ
io.ifu.get_pc(0).ftq_idx := ftq_arb.io.out.bits
ftq_arb.io.out.ready := true.B
// Branch Unit Requests (for JALs) (Should delay issue of JALs if this not ready)
jmp_pc_req.valid := RegNext(iss_valids(jmp_unit_idx) && iss_uops(jmp_unit_idx).fu_code === FU_JMP)
jmp_pc_req.bits := RegNext(iss_uops(jmp_unit_idx).ftq_idx)
jmp_unit.io.get_ftq_pc := DontCare
jmp_unit.io.get_ftq_pc.pc := io.ifu.get_pc(0).pc
jmp_unit.io.get_ftq_pc.entry := io.ifu.get_pc(0).entry
jmp_unit.io.get_ftq_pc.next_val := io.ifu.get_pc(0).next_val
jmp_unit.io.get_ftq_pc.next_pc := io.ifu.get_pc(0).next_pc
// Frontend Exception Requests
val xcpt_idx = PriorityEncoder(dec_xcpts)
xcpt_pc_req.valid := dec_xcpts.reduce(_||_)
xcpt_pc_req.bits := dec_uops(xcpt_idx).ftq_idx
//rob.io.xcpt_fetch_pc := RegEnable(io.ifu.get_pc.fetch_pc, dis_ready)
rob.io.xcpt_fetch_pc := io.ifu.get_pc(0).pc
flush_pc_req.valid := rob.io.flush.valid
flush_pc_req.bits := rob.io.flush.bits.ftq_idx
// Mispredict requests (to get the correct target)
io.ifu.get_pc(1).ftq_idx := oldest_mispredict_ftq_idx
//-------------------------------------------------------------
// Decode/Rename1 pipeline logic
dec_xcpts := dec_uops zip dec_valids map {case (u,v) => u.exception && v}
val dec_xcpt_stall = dec_xcpts.reduce(_||_) && !xcpt_pc_req.ready
// stall fetch/dcode because we ran out of branch tags
val branch_mask_full = Wire(Vec(coreWidth, Bool()))
val dec_hazards = (0 until coreWidth).map(w =>
dec_valids(w) &&
( !dis_ready
|| rob.io.commit.rollback
|| dec_xcpt_stall
|| branch_mask_full(w)
|| brupdate.b1.mispredict_mask =/= 0.U
|| brupdate.b2.mispredict
|| io.ifu.redirect_flush))
val dec_stalls = dec_hazards.scanLeft(false.B) ((s,h) => s || h).takeRight(coreWidth)
dec_fire := (0 until coreWidth).map(w => dec_valids(w) && !dec_stalls(w))
// all decoders are empty and ready for new instructions
dec_ready := dec_fire.last
when (dec_ready || io.ifu.redirect_flush) {
dec_finished_mask := 0.U
} .otherwise {
dec_finished_mask := dec_fire.asUInt | dec_finished_mask
}
//-------------------------------------------------------------
// Branch Mask Logic
dec_brmask_logic.io.brupdate := brupdate
dec_brmask_logic.io.flush_pipeline := RegNext(rob.io.flush.valid)
for (w <- 0 until coreWidth) {
dec_brmask_logic.io.is_branch(w) := !dec_finished_mask(w) && dec_uops(w).allocate_brtag
dec_brmask_logic.io.will_fire(w) := dec_fire(w) &&
dec_uops(w).allocate_brtag // ren, dis can back pressure us
dec_uops(w).br_tag := dec_brmask_logic.io.br_tag(w)
dec_uops(w).br_mask := dec_brmask_logic.io.br_mask(w)
}
branch_mask_full := dec_brmask_logic.io.is_full
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Register Rename Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
// Inputs
for (rename <- rename_stages) {
rename.io.kill := io.ifu.redirect_flush
rename.io.brupdate := brupdate
rename.io.debug_rob_empty := rob.io.empty
rename.io.dec_fire := dec_fire
rename.io.dec_uops := dec_uops
rename.io.dis_fire := dis_fire
rename.io.dis_ready := dis_ready
rename.io.com_valids := rob.io.commit.valids
rename.io.com_uops := rob.io.commit.uops
rename.io.rbk_valids := rob.io.commit.rbk_valids
rename.io.rollback := rob.io.commit.rollback
}
// Outputs
dis_uops := rename_stage.io.ren2_uops
dis_valids := rename_stage.io.ren2_mask
ren_stalls := rename_stage.io.ren_stalls
/**
* TODO This is a bit nasty, but it's currently necessary to
* split the INT/FP rename pipelines into separate instantiations.
* Won't have to do this anymore with a properly decoupled FP pipeline.
*/
for (w <- 0 until coreWidth) {
val i_uop = rename_stage.io.ren2_uops(w)
val f_uop = if (usingFPU) fp_rename_stage.io.ren2_uops(w) else NullMicroOp
val p_uop = if (enableSFBOpt) pred_rename_stage.io.ren2_uops(w) else NullMicroOp
val f_stall = if (usingFPU) fp_rename_stage.io.ren_stalls(w) else false.B
val p_stall = if (enableSFBOpt) pred_rename_stage.io.ren_stalls(w) else false.B
// lrs1 can "pass through" to prs1. Used solely to index the csr file.
dis_uops(w).prs1 := Mux(dis_uops(w).lrs1_rtype === RT_FLT, f_uop.prs1,
Mux(dis_uops(w).lrs1_rtype === RT_FIX, i_uop.prs1, dis_uops(w).lrs1))
dis_uops(w).prs2 := Mux(dis_uops(w).lrs2_rtype === RT_FLT, f_uop.prs2, i_uop.prs2)
dis_uops(w).prs3 := f_uop.prs3
dis_uops(w).ppred := p_uop.ppred
dis_uops(w).pdst := Mux(dis_uops(w).dst_rtype === RT_FLT, f_uop.pdst,
Mux(dis_uops(w).dst_rtype === RT_FIX, i_uop.pdst,
p_uop.pdst))
dis_uops(w).stale_pdst := Mux(dis_uops(w).dst_rtype === RT_FLT, f_uop.stale_pdst, i_uop.stale_pdst)
dis_uops(w).prs1_busy := i_uop.prs1_busy && (dis_uops(w).lrs1_rtype === RT_FIX) ||
f_uop.prs1_busy && (dis_uops(w).lrs1_rtype === RT_FLT)
dis_uops(w).prs2_busy := i_uop.prs2_busy && (dis_uops(w).lrs2_rtype === RT_FIX) ||
f_uop.prs2_busy && (dis_uops(w).lrs2_rtype === RT_FLT)
dis_uops(w).prs3_busy := f_uop.prs3_busy && dis_uops(w).frs3_en
dis_uops(w).ppred_busy := p_uop.ppred_busy && dis_uops(w).is_sfb_shadow
ren_stalls(w) := rename_stage.io.ren_stalls(w) || f_stall || p_stall
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Dispatch Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
//-------------------------------------------------------------
// Rename2/Dispatch pipeline logic
val dis_prior_slot_valid = dis_valids.scanLeft(false.B) ((s,v) => s || v)
val dis_prior_slot_unique = (dis_uops zip dis_valids).scanLeft(false.B) {case (s,(u,v)) => s || v && u.is_unique}
val wait_for_empty_pipeline = (0 until coreWidth).map(w => (dis_uops(w).is_unique || custom_csrs.disableOOO) &&
(!rob.io.empty || !io.lsu.fencei_rdy || dis_prior_slot_valid(w)))
val rocc_shim_busy = if (usingRoCC) !exe_units.rocc_unit.io.rocc.rxq_empty else false.B
val wait_for_rocc = (0 until coreWidth).map(w =>
(dis_uops(w).is_fence || dis_uops(w).is_fencei) && (io.rocc.busy || rocc_shim_busy))
val rxq_full = if (usingRoCC) exe_units.rocc_unit.io.rocc.rxq_full else false.B
val block_rocc = (dis_uops zip dis_valids).map{case (u,v) => v && u.uopc === uopROCC}.scanLeft(rxq_full)(_||_)
val dis_rocc_alloc_stall = (dis_uops.map(_.uopc === uopROCC) zip block_rocc) map {case (p,r) =>
if (usingRoCC) p && r else false.B}
val dis_hazards = (0 until coreWidth).map(w =>
dis_valids(w) &&
( !rob.io.ready
|| ren_stalls(w)
|| io.lsu.ldq_full(w) && dis_uops(w).uses_ldq
|| io.lsu.stq_full(w) && dis_uops(w).uses_stq
|| !dispatcher.io.ren_uops(w).ready
|| wait_for_empty_pipeline(w)
|| wait_for_rocc(w)
|| dis_prior_slot_unique(w)
|| dis_rocc_alloc_stall(w)
|| brupdate.b1.mispredict_mask =/= 0.U
|| brupdate.b2.mispredict
|| io.ifu.redirect_flush))
io.lsu.fence_dmem := (dis_valids zip wait_for_empty_pipeline).map {case (v,w) => v && w} .reduce(_||_)
val dis_stalls = dis_hazards.scanLeft(false.B) ((s,h) => s || h).takeRight(coreWidth)
dis_fire := dis_valids zip dis_stalls map {case (v,s) => v && !s}
dis_ready := !dis_stalls.last
//-------------------------------------------------------------
// LDQ/STQ Allocation Logic
for (w <- 0 until coreWidth) {
// Dispatching instructions request load/store queue entries when they can proceed.
dis_uops(w).ldq_idx := io.lsu.dis_ldq_idx(w)
dis_uops(w).stq_idx := io.lsu.dis_stq_idx(w)
}
//-------------------------------------------------------------
// Rob Allocation Logic
rob.io.enq_valids := dis_fire
rob.io.enq_uops := dis_uops
rob.io.enq_partial_stall := dis_stalls.last // TODO come up with better ROB compacting scheme.
rob.io.debug_tsc := debug_tsc_reg
rob.io.csr_stall := csr.io.csr_stall
// Minor hack: ecall and breaks need to increment the FTQ deq ptr earlier than commit, since
// they write their PC into the CSR the cycle before they commit.
// Since these are also unique, increment the FTQ ptr when they are dispatched
when (RegNext(dis_fire.reduce(_||_) && dis_uops(PriorityEncoder(dis_fire)).is_sys_pc2epc)) {
io.ifu.commit.valid := true.B
io.ifu.commit.bits := RegNext(dis_uops(PriorityEncoder(dis_valids)).ftq_idx)
}
for (w <- 0 until coreWidth) {
// note: this assumes uops haven't been shifted - there's a 1:1 match between PC's LSBs and "w" here
// (thus the LSB of the rob_idx gives part of the PC)
if (coreWidth == 1) {
dis_uops(w).rob_idx := rob.io.rob_tail_idx
} else {
dis_uops(w).rob_idx := Cat(rob.io.rob_tail_idx >> log2Ceil(coreWidth).U,
w.U(log2Ceil(coreWidth).W))
}
}
//-------------------------------------------------------------
// RoCC allocation logic
if (usingRoCC) {
for (w <- 0 until coreWidth) {
// We guarantee only decoding 1 RoCC instruction per cycle
dis_uops(w).rxq_idx := exe_units.rocc_unit.io.rocc.rxq_idx(w)
}
}
//-------------------------------------------------------------
// Dispatch to issue queues
// Get uops from rename2
for (w <- 0 until coreWidth) {
dispatcher.io.ren_uops(w).valid := dis_fire(w)
dispatcher.io.ren_uops(w).bits := dis_uops(w)
}
var iu_idx = 0
// Send dispatched uops to correct issue queues
// Backpressure through dispatcher if necessary
for (i <- 0 until issueParams.size) {
if (issueParams(i).iqType == IQT_FP.litValue) {
fp_pipeline.io.dis_uops <> dispatcher.io.dis_uops(i)
} else {
issue_units(iu_idx).io.dis_uops <> dispatcher.io.dis_uops(i)
iu_idx += 1
}
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Issue Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
require (issue_units.map(_.issueWidth).sum == exe_units.length)
var iss_wu_idx = 1
var ren_wu_idx = 1
// The 0th wakeup port goes to the ll_wbarb
int_iss_wakeups(0).valid := ll_wbarb.io.out.fire && ll_wbarb.io.out.bits.uop.dst_rtype === RT_FIX
int_iss_wakeups(0).bits := ll_wbarb.io.out.bits
int_ren_wakeups(0).valid := ll_wbarb.io.out.fire && ll_wbarb.io.out.bits.uop.dst_rtype === RT_FIX
int_ren_wakeups(0).bits := ll_wbarb.io.out.bits
for (i <- 1 until memWidth) {
int_iss_wakeups(i).valid := mem_resps(i).valid && mem_resps(i).bits.uop.dst_rtype === RT_FIX
int_iss_wakeups(i).bits := mem_resps(i).bits
int_ren_wakeups(i).valid := mem_resps(i).valid && mem_resps(i).bits.uop.dst_rtype === RT_FIX
int_ren_wakeups(i).bits := mem_resps(i).bits
iss_wu_idx += 1
ren_wu_idx += 1
}
// loop through each issue-port (exe_units are statically connected to an issue-port)
for (i <- 0 until exe_units.length) {
if (exe_units(i).writesIrf) {
val fast_wakeup = Wire(Valid(new ExeUnitResp(xLen)))
val slow_wakeup = Wire(Valid(new ExeUnitResp(xLen)))
fast_wakeup := DontCare
slow_wakeup := DontCare
val resp = exe_units(i).io.iresp
assert(!(resp.valid && resp.bits.uop.rf_wen && resp.bits.uop.dst_rtype =/= RT_FIX))
// Fast Wakeup (uses just-issued uops that have known latencies)
fast_wakeup.bits.uop := iss_uops(i)
fast_wakeup.valid := iss_valids(i) &&
iss_uops(i).bypassable &&
iss_uops(i).dst_rtype === RT_FIX &&
iss_uops(i).ldst_val &&
!(io.lsu.ld_miss && (iss_uops(i).iw_p1_poisoned || iss_uops(i).iw_p2_poisoned))
// Slow Wakeup (uses write-port to register file)
slow_wakeup.bits.uop := resp.bits.uop
slow_wakeup.valid := resp.valid &&
resp.bits.uop.rf_wen &&
!resp.bits.uop.bypassable &&
resp.bits.uop.dst_rtype === RT_FIX
if (exe_units(i).bypassable) {
int_iss_wakeups(iss_wu_idx) := fast_wakeup
iss_wu_idx += 1
}
if (!exe_units(i).alwaysBypassable) {
int_iss_wakeups(iss_wu_idx) := slow_wakeup
iss_wu_idx += 1
}
if (exe_units(i).bypassable) {
int_ren_wakeups(ren_wu_idx) := fast_wakeup
ren_wu_idx += 1
}
if (!exe_units(i).alwaysBypassable) {
int_ren_wakeups(ren_wu_idx) := slow_wakeup
ren_wu_idx += 1
}
}
}
require (iss_wu_idx == numIntIssueWakeupPorts)
require (ren_wu_idx == numIntRenameWakeupPorts)
require (iss_wu_idx == ren_wu_idx)
// jmp unit performs fast wakeup of the predicate bits
require (jmp_unit.bypassable)
pred_wakeup.valid := (iss_valids(jmp_unit_idx) &&
iss_uops(jmp_unit_idx).is_sfb_br &&
!(io.lsu.ld_miss && (iss_uops(jmp_unit_idx).iw_p1_poisoned || iss_uops(jmp_unit_idx).iw_p2_poisoned))
)
pred_wakeup.bits.uop := iss_uops(jmp_unit_idx)
pred_wakeup.bits.fflags := DontCare
pred_wakeup.bits.data := DontCare
pred_wakeup.bits.predicated := DontCare
// Perform load-hit speculative wakeup through a special port (performs a poison wake-up).
issue_units map { iu =>
iu.io.spec_ld_wakeup := io.lsu.spec_ld_wakeup
}
// Connect the predicate wakeup port
issue_units map { iu =>
iu.io.pred_wakeup_port.valid := false.B
iu.io.pred_wakeup_port.bits := DontCare
}
if (enableSFBOpt) {
int_iss_unit.io.pred_wakeup_port.valid := pred_wakeup.valid
int_iss_unit.io.pred_wakeup_port.bits := pred_wakeup.bits.uop.pdst
}
// ----------------------------------------------------------------
// Connect the wakeup ports to the busy tables in the rename stages
for ((renport, intport) <- rename_stage.io.wakeups zip int_ren_wakeups) {
renport <> intport
}
if (usingFPU) {
for ((renport, fpport) <- fp_rename_stage.io.wakeups zip fp_pipeline.io.wakeups) {
renport <> fpport
}
}
if (enableSFBOpt) {
pred_rename_stage.io.wakeups(0) := pred_wakeup
} else {
pred_rename_stage.io.wakeups := DontCare
}
// If we issue loads back-to-back endlessly (probably because we are executing some tight loop)
// the store buffer will never drain, breaking the memory-model forward-progress guarantee
// If we see a large number of loads saturate the LSU, pause for a cycle to let a store drain
val loads_saturating = (mem_iss_unit.io.iss_valids(0) && mem_iss_unit.io.iss_uops(0).uses_ldq)
val saturating_loads_counter = RegInit(0.U(5.W))
when (loads_saturating) { saturating_loads_counter := saturating_loads_counter + 1.U }
.otherwise { saturating_loads_counter := 0.U }
val pause_mem = RegNext(loads_saturating) && saturating_loads_counter === ~(0.U(5.W))
var iss_idx = 0
var int_iss_cnt = 0
var mem_iss_cnt = 0
for (w <- 0 until exe_units.length) {
var fu_types = exe_units(w).io.fu_types
val exe_unit = exe_units(w)
if (exe_unit.readsIrf) {
if (exe_unit.supportedFuncUnits.muld) {
// Supress just-issued divides from issuing back-to-back, since it's an iterative divider.
// But it takes a cycle to get to the Exe stage, so it can't tell us it is busy yet.
val idiv_issued = iss_valids(iss_idx) && iss_uops(iss_idx).fu_code_is(FU_DIV)
fu_types = fu_types & RegNext(~Mux(idiv_issued, FU_DIV, 0.U))
}
if (exe_unit.hasMem) {
iss_valids(iss_idx) := mem_iss_unit.io.iss_valids(mem_iss_cnt)
iss_uops(iss_idx) := mem_iss_unit.io.iss_uops(mem_iss_cnt)
mem_iss_unit.io.fu_types(mem_iss_cnt) := Mux(pause_mem, 0.U, fu_types)
mem_iss_cnt += 1
} else {
iss_valids(iss_idx) := int_iss_unit.io.iss_valids(int_iss_cnt)
iss_uops(iss_idx) := int_iss_unit.io.iss_uops(int_iss_cnt)
int_iss_unit.io.fu_types(int_iss_cnt) := fu_types
int_iss_cnt += 1
}
iss_idx += 1
}
}
require(iss_idx == exe_units.numIrfReaders)
issue_units.map(_.io.tsc_reg := debug_tsc_reg)
issue_units.map(_.io.brupdate := brupdate)
issue_units.map(_.io.flush_pipeline := RegNext(rob.io.flush.valid))
// Load-hit Misspeculations
require (mem_iss_unit.issueWidth <= 2)
issue_units.map(_.io.ld_miss := io.lsu.ld_miss)
mem_units.map(u => u.io.com_exception := RegNext(rob.io.flush.valid))
// Wakeup (Issue & Writeback)
for {
iu <- issue_units
(issport, wakeup) <- iu.io.wakeup_ports zip int_iss_wakeups
}{
issport.valid := wakeup.valid
issport.bits.pdst := wakeup.bits.uop.pdst
issport.bits.poisoned := wakeup.bits.uop.iw_p1_poisoned || wakeup.bits.uop.iw_p2_poisoned
require (iu.io.wakeup_ports.length == int_iss_wakeups.length)
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Register Read Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
// Register Read <- Issue (rrd <- iss)
iregister_read.io.rf_read_ports <> iregfile.io.read_ports
iregister_read.io.prf_read_ports := DontCare
if (enableSFBOpt) {
iregister_read.io.prf_read_ports <> pregfile.io.read_ports
}
for (w <- 0 until exe_units.numIrfReaders) {
iregister_read.io.iss_valids(w) :=
iss_valids(w) && !(io.lsu.ld_miss && (iss_uops(w).iw_p1_poisoned || iss_uops(w).iw_p2_poisoned))
}
iregister_read.io.iss_uops := iss_uops
iregister_read.io.iss_uops map { u => u.iw_p1_poisoned := false.B; u.iw_p2_poisoned := false.B }
iregister_read.io.brupdate := brupdate
iregister_read.io.kill := RegNext(rob.io.flush.valid)
iregister_read.io.bypass := bypasses
iregister_read.io.pred_bypass := pred_bypasses
//-------------------------------------------------------------
// Privileged Co-processor 0 Register File
// Note: Normally this would be bad in that I'm writing state before
// committing, so to get this to work I stall the entire pipeline for
// CSR instructions so I never speculate these instructions.
val csr_exe_unit = exe_units.csr_unit
// for critical path reasons, we aren't zero'ing this out if resp is not valid
val csr_rw_cmd = csr_exe_unit.io.iresp.bits.uop.ctrl.csr_cmd
val wb_wdata = csr_exe_unit.io.iresp.bits.data
csr.io.rw.addr := csr_exe_unit.io.iresp.bits.uop.csr_addr
csr.io.rw.cmd := freechips.rocketchip.rocket.CSR.maskCmd(csr_exe_unit.io.iresp.valid, csr_rw_cmd)
csr.io.rw.wdata := wb_wdata
rob.io.csr_replay.valid := csr_exe_unit.io.iresp.valid && csr.io.rw_stall
rob.io.csr_replay.bits.uop := csr_exe_unit.io.iresp.bits.uop
rob.io.csr_replay.bits.cause := MINI_EXCEPTION_CSR_REPLAY
rob.io.csr_replay.bits.badvaddr := DontCare
// Extra I/O
// Delay retire/exception 1 cycle
csr.io.retire := RegNext(PopCount(rob.io.commit.arch_valids.asUInt))
csr.io.exception := RegNext(rob.io.com_xcpt.valid)
// csr.io.pc used for setting EPC during exception or CSR.io.trace.
csr.io.pc := (boom.v3.util.AlignPCToBoundary(io.ifu.get_pc(0).com_pc, icBlockBytes)
+ RegNext(rob.io.com_xcpt.bits.pc_lob)
- Mux(RegNext(rob.io.com_xcpt.bits.edge_inst), 2.U, 0.U))
// Cause not valid for for CALL or BREAKPOINTs (CSRFile will override it).
csr.io.cause := RegNext(rob.io.com_xcpt.bits.cause)
csr.io.ungated_clock := clock
val tval_valid = csr.io.exception &&
csr.io.cause.isOneOf(
//Causes.illegal_instruction.U, we currently only write 0x0 for illegal instructions
Causes.breakpoint.U,
Causes.misaligned_load.U,
Causes.misaligned_store.U,
Causes.load_access.U,
Causes.store_access.U,
Causes.fetch_access.U,
Causes.load_page_fault.U,
Causes.store_page_fault.U,
Causes.fetch_page_fault.U)
csr.io.tval := Mux(tval_valid,
RegNext(encodeVirtualAddress(rob.io.com_xcpt.bits.badvaddr, rob.io.com_xcpt.bits.badvaddr)), 0.U)
// TODO move this function to some central location (since this is used elsewhere).
def encodeVirtualAddress(a0: UInt, ea: UInt) =
if (vaddrBitsExtended == vaddrBits) {
ea
} else {
// Efficient means to compress 64-bit VA into vaddrBits+1 bits.
// (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)).
val a = a0.asSInt >> vaddrBits
val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1))
Cat(msb, ea(vaddrBits-1,0))
}
// reading requires serializing the entire pipeline
csr.io.fcsr_flags.valid := rob.io.commit.fflags.valid
csr.io.fcsr_flags.bits := rob.io.commit.fflags.bits
csr.io.set_fs_dirty.get := rob.io.commit.fflags.valid
exe_units.withFilter(_.hasFcsr).map(_.io.fcsr_rm := csr.io.fcsr_rm)
io.fcsr_rm := csr.io.fcsr_rm
if (usingFPU) {
fp_pipeline.io.fcsr_rm := csr.io.fcsr_rm
}
csr.io.hartid := io.hartid
csr.io.interrupts := io.interrupts
// we do not support the H-extension
csr.io.htval := DontCare
csr.io.gva := DontCare
// TODO can we add this back in, but handle reset properly and save us
// the mux above on csr.io.rw.cmd?
// assert (!(csr_rw_cmd =/= rocket.CSR.N && !exe_units(0).io.resp(0).valid),
// "CSRFile is being written to spuriously.")
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Execute Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
iss_idx = 0
var bypass_idx = 0
for (w <- 0 until exe_units.length) {
val exe_unit = exe_units(w)
if (exe_unit.readsIrf) {
exe_unit.io.req <> iregister_read.io.exe_reqs(iss_idx)
if (exe_unit.bypassable) {
for (i <- 0 until exe_unit.numBypassStages) {
bypasses(bypass_idx) := exe_unit.io.bypass(i)
bypass_idx += 1
}
}
iss_idx += 1
}
}
require (bypass_idx == exe_units.numTotalBypassPorts)
for (i <- 0 until jmp_unit.numBypassStages) {
pred_bypasses(i) := jmp_unit.io.bypass(i)
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Load/Store Unit ****
//-------------------------------------------------------------
//-------------------------------------------------------------
// enqueue basic load/store info in Decode
for (w <- 0 until coreWidth) {
io.lsu.dis_uops(w).valid := dis_fire(w)
io.lsu.dis_uops(w).bits := dis_uops(w)
}
// tell LSU about committing loads and stores to clear entries
io.lsu.commit := rob.io.commit
// tell LSU that it should fire a load that waits for the rob to clear
io.lsu.commit_load_at_rob_head := rob.io.com_load_is_at_rob_head
//com_xcpt.valid comes too early, will fight against a branch that resolves same cycle as an exception
io.lsu.exception := RegNext(rob.io.flush.valid)
// Handle Branch Mispeculations
io.lsu.brupdate := brupdate
io.lsu.rob_head_idx := rob.io.rob_head_idx
io.lsu.rob_pnr_idx := rob.io.rob_pnr_idx
io.lsu.tsc_reg := debug_tsc_reg
if (usingFPU) {
io.lsu.fp_stdata <> fp_pipeline.io.to_sdq
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Writeback Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
var w_cnt = 1
iregfile.io.write_ports(0) := WritePort(ll_wbarb.io.out, ipregSz, xLen, RT_FIX)
ll_wbarb.io.in(0) <> mem_resps(0)
assert (ll_wbarb.io.in(0).ready) // never backpressure the memory unit.
for (i <- 1 until memWidth) {
iregfile.io.write_ports(w_cnt) := WritePort(mem_resps(i), ipregSz, xLen, RT_FIX)
w_cnt += 1
}
for (i <- 0 until exe_units.length) {
if (exe_units(i).writesIrf) {
val wbresp = exe_units(i).io.iresp
val wbpdst = wbresp.bits.uop.pdst
val wbdata = wbresp.bits.data
def wbIsValid(rtype: UInt) =
wbresp.valid && wbresp.bits.uop.rf_wen && wbresp.bits.uop.dst_rtype === rtype
val wbReadsCSR = wbresp.bits.uop.ctrl.csr_cmd =/= freechips.rocketchip.rocket.CSR.N
iregfile.io.write_ports(w_cnt).valid := wbIsValid(RT_FIX)
iregfile.io.write_ports(w_cnt).bits.addr := wbpdst
wbresp.ready := true.B
if (exe_units(i).hasCSR) {
iregfile.io.write_ports(w_cnt).bits.data := Mux(wbReadsCSR, csr.io.rw.rdata, wbdata)
} else {
iregfile.io.write_ports(w_cnt).bits.data := wbdata
}
assert (!wbIsValid(RT_FLT), "[fppipeline] An FP writeback is being attempted to the Int Regfile.")
assert (!(wbresp.valid &&
!wbresp.bits.uop.rf_wen &&
wbresp.bits.uop.dst_rtype === RT_FIX),
"[fppipeline] An Int writeback is being attempted with rf_wen disabled.")
assert (!(wbresp.valid &&
wbresp.bits.uop.rf_wen &&
wbresp.bits.uop.dst_rtype =/= RT_FIX),
"[fppipeline] writeback being attempted to Int RF with dst != Int type exe_units("+i+").iresp")
w_cnt += 1
}
}
require(w_cnt == iregfile.io.write_ports.length)
if (enableSFBOpt) {
pregfile.io.write_ports(0).valid := jmp_unit.io.iresp.valid && jmp_unit.io.iresp.bits.uop.is_sfb_br
pregfile.io.write_ports(0).bits.addr := jmp_unit.io.iresp.bits.uop.pdst
pregfile.io.write_ports(0).bits.data := jmp_unit.io.iresp.bits.data
}
if (usingFPU) {
// Connect IFPU
fp_pipeline.io.from_int <> exe_units.ifpu_unit.io.ll_fresp
// Connect FPIU
ll_wbarb.io.in(1) <> fp_pipeline.io.to_int
// Connect FLDs
fp_pipeline.io.ll_wports <> exe_units.memory_units.map(_.io.ll_fresp).toSeq
}
if (usingRoCC) {
require(usingFPU)
ll_wbarb.io.in(2) <> exe_units.rocc_unit.io.ll_iresp
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Commit Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
// Writeback
// ---------
// First connect the ll_wport
val ll_uop = ll_wbarb.io.out.bits.uop
rob.io.wb_resps(0).valid := ll_wbarb.io.out.valid && !(ll_uop.uses_stq && !ll_uop.is_amo)
rob.io.wb_resps(0).bits <> ll_wbarb.io.out.bits
rob.io.debug_wb_valids(0) := ll_wbarb.io.out.valid && ll_uop.dst_rtype =/= RT_X
rob.io.debug_wb_wdata(0) := ll_wbarb.io.out.bits.data
var cnt = 1
for (i <- 1 until memWidth) {
val mem_uop = mem_resps(i).bits.uop
rob.io.wb_resps(cnt).valid := mem_resps(i).valid && !(mem_uop.uses_stq && !mem_uop.is_amo)
rob.io.wb_resps(cnt).bits := mem_resps(i).bits
rob.io.debug_wb_valids(cnt) := mem_resps(i).valid && mem_uop.dst_rtype =/= RT_X
rob.io.debug_wb_wdata(cnt) := mem_resps(i).bits.data
cnt += 1
}
var f_cnt = 0 // rob fflags port index
for (eu <- exe_units) {
if (eu.writesIrf)
{
val resp = eu.io.iresp
val wb_uop = resp.bits.uop
val data = resp.bits.data
rob.io.wb_resps(cnt).valid := resp.valid && !(wb_uop.uses_stq && !wb_uop.is_amo)
rob.io.wb_resps(cnt).bits <> resp.bits
rob.io.debug_wb_valids(cnt) := resp.valid && wb_uop.rf_wen && wb_uop.dst_rtype === RT_FIX
if (eu.hasFFlags) {
rob.io.fflags(f_cnt) <> resp.bits.fflags
f_cnt += 1
}
if (eu.hasCSR) {
rob.io.debug_wb_wdata(cnt) := Mux(wb_uop.ctrl.csr_cmd =/= freechips.rocketchip.rocket.CSR.N,
csr.io.rw.rdata,
data)
} else {
rob.io.debug_wb_wdata(cnt) := data
}
cnt += 1
}
}
require(cnt == numIrfWritePorts)
if (usingFPU) {
for ((wdata, wakeup) <- fp_pipeline.io.debug_wb_wdata zip fp_pipeline.io.wakeups) {
rob.io.wb_resps(cnt) <> wakeup
rob.io.fflags(f_cnt) <> wakeup.bits.fflags
rob.io.debug_wb_valids(cnt) := wakeup.valid
rob.io.debug_wb_wdata(cnt) := wdata
cnt += 1
f_cnt += 1
assert (!(wakeup.valid && wakeup.bits.uop.dst_rtype =/= RT_FLT),
"[core] FP wakeup does not write back to a FP register.")
assert (!(wakeup.valid && !wakeup.bits.uop.fp_val),
"[core] FP wakeup does not involve an FP instruction.")
}
}
require (cnt == rob.numWakeupPorts)
require (f_cnt == rob.numFpuPorts)
// branch resolution
rob.io.brupdate <> brupdate
exe_units.map(u => u.io.status := csr.io.status)
if (usingFPU)
fp_pipeline.io.status := csr.io.status
// Connect breakpoint info to memaddrcalcunit
for (i <- 0 until memWidth) {
mem_units(i).io.status := csr.io.status
mem_units(i).io.bp := csr.io.bp
mem_units(i).io.mcontext := csr.io.mcontext
mem_units(i).io.scontext := csr.io.scontext
}
// LSU <> ROB
rob.io.lsu_clr_bsy := io.lsu.clr_bsy
rob.io.lsu_clr_unsafe := io.lsu.clr_unsafe
rob.io.lxcpt <> io.lsu.lxcpt
assert (!(csr.io.singleStep), "[core] single-step is unsupported.")
//-------------------------------------------------------------
// **** Flush Pipeline ****
//-------------------------------------------------------------
// flush on exceptions, miniexeptions, and after some special instructions
if (usingFPU) {
fp_pipeline.io.flush_pipeline := RegNext(rob.io.flush.valid)
}
for (w <- 0 until exe_units.length) {
exe_units(w).io.req.bits.kill := RegNext(rob.io.flush.valid)
}
assert (!(rob.io.com_xcpt.valid && !rob.io.flush.valid),
"[core] exception occurred, but pipeline flush signal not set!")
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Outputs to the External World ****
//-------------------------------------------------------------
//-------------------------------------------------------------
// detect pipeline freezes and throw error
val idle_cycles = freechips.rocketchip.util.WideCounter(32)
when (rob.io.commit.valids.asUInt.orR ||
csr.io.csr_stall ||
io.rocc.busy ||
reset.asBool) {
idle_cycles := 0.U
}
assert (!(idle_cycles.value(13)), "Pipeline has hung.")
if (usingFPU) {
fp_pipeline.io.debug_tsc_reg := debug_tsc_reg
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Handle Cycle-by-Cycle Printouts ****
//-------------------------------------------------------------
//-------------------------------------------------------------
if (COMMIT_LOG_PRINTF) {
var new_commit_cnt = 0.U
for (w <- 0 until coreWidth) {
val priv = RegNext(csr.io.status.prv) // erets change the privilege. Get the old one
// To allow for diffs against spike :/
def printf_inst(uop: MicroOp) = {
when (uop.is_rvc) {
printf("(0x%x)", uop.debug_inst(15,0))
} .otherwise {
printf("(0x%x)", uop.debug_inst)
}
}
when (rob.io.commit.arch_valids(w)) {
printf("%d 0x%x ",
priv,
Sext(rob.io.commit.uops(w).debug_pc(vaddrBits-1,0), xLen))
printf_inst(rob.io.commit.uops(w))
when (rob.io.commit.uops(w).dst_rtype === RT_FIX && rob.io.commit.uops(w).ldst =/= 0.U) {
printf(" x%d 0x%x\n",
rob.io.commit.uops(w).ldst,
rob.io.commit.debug_wdata(w))
} .elsewhen (rob.io.commit.uops(w).dst_rtype === RT_FLT) {
printf(" f%d 0x%x\n",
rob.io.commit.uops(w).ldst,
rob.io.commit.debug_wdata(w))
} .otherwise {
printf("\n")
}
}
}
} else if (BRANCH_PRINTF) {
val debug_ghist = RegInit(0.U(globalHistoryLength.W))
when (rob.io.flush.valid && FlushTypes.useCsrEvec(rob.io.flush.bits.flush_typ)) {
debug_ghist := 0.U
}
var new_ghist = debug_ghist
for (w <- 0 until coreWidth) {
when (rob.io.commit.arch_valids(w) &&
(rob.io.commit.uops(w).is_br || rob.io.commit.uops(w).is_jal || rob.io.commit.uops(w).is_jalr)) {
// for (i <- 0 until globalHistoryLength) {
// printf("%x", new_ghist(globalHistoryLength-i-1))
// }
// printf("\n")
printf("%x %x %x %x %x %x\n",
rob.io.commit.uops(w).debug_fsrc, rob.io.commit.uops(w).taken,
rob.io.commit.uops(w).is_br, rob.io.commit.uops(w).is_jal,
rob.io.commit.uops(w).is_jalr, Sext(rob.io.commit.uops(w).debug_pc(vaddrBits-1,0), xLen))
}
new_ghist = Mux(rob.io.commit.arch_valids(w) && rob.io.commit.uops(w).is_br,
Mux(rob.io.commit.uops(w).taken, new_ghist << 1 | 1.U(1.W), new_ghist << 1),
new_ghist)
}
debug_ghist := new_ghist
}
// TODO: Does anyone want this debugging functionality?
val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen))
coreMonitorBundle := DontCare
coreMonitorBundle.clock := clock
coreMonitorBundle.reset := reset
//-------------------------------------------------------------
//-------------------------------------------------------------
// Page Table Walker
io.ptw.ptbr := csr.io.ptbr
io.ptw.status := csr.io.status
io.ptw.pmp := csr.io.pmp
io.ptw.sfence := io.ifu.sfence
//-------------------------------------------------------------
//-------------------------------------------------------------
io.rocc := DontCare
io.rocc.exception := csr.io.exception && csr.io.status.xs.orR
io.rocc.csrs <> csr.io.roccCSRs
if (usingRoCC) {
exe_units.rocc_unit.io.rocc.rocc <> io.rocc
exe_units.rocc_unit.io.rocc.dis_uops := dis_uops
exe_units.rocc_unit.io.rocc.rob_head_idx := rob.io.rob_head_idx
exe_units.rocc_unit.io.rocc.rob_pnr_idx := rob.io.rob_pnr_idx
exe_units.rocc_unit.io.com_exception := rob.io.flush.valid
exe_units.rocc_unit.io.status := csr.io.status
for (w <- 0 until coreWidth) {
exe_units.rocc_unit.io.rocc.dis_rocc_vals(w) := (
dis_fire(w) &&
dis_uops(w).uopc === uopROCC &&
!dis_uops(w).exception
)
}
}
io.trace := DontCare
io.trace.time := csr.io.time
io.trace.insns map (t => t.valid := false.B)
io.trace.custom.get.asInstanceOf[BoomTraceBundle].rob_empty := rob.io.empty
if (trace) {
for (w <- 0 until coreWidth) {
// Delay the trace so we have a cycle to pull PCs out of the FTQ
io.trace.insns(w).valid := RegNext(rob.io.commit.arch_valids(w))
// Recalculate the PC
io.ifu.debug_ftq_idx(w) := rob.io.commit.uops(w).ftq_idx
val iaddr = (AlignPCToBoundary(io.ifu.debug_fetch_pc(w), icBlockBytes)
+ RegNext(rob.io.commit.uops(w).pc_lob)
- Mux(RegNext(rob.io.commit.uops(w).edge_inst), 2.U, 0.U))(vaddrBits-1,0)
io.trace.insns(w).iaddr := Sext(iaddr, xLen)
def getInst(uop: MicroOp, inst: UInt): UInt = {
Mux(uop.is_rvc, Cat(0.U(16.W), inst(15,0)), inst)
}
def getWdata(uop: MicroOp, wdata: UInt): UInt = {
Mux((uop.dst_rtype === RT_FIX && uop.ldst =/= 0.U) || (uop.dst_rtype === RT_FLT), wdata, 0.U(xLen.W))
}
// use debug_insts instead of uop.debug_inst to use the rob's debug_inst_mem
// note: rob.debug_insts comes 1 cycle later
io.trace.insns(w).insn := getInst(RegNext(rob.io.commit.uops(w)), rob.io.commit.debug_insts(w))
io.trace.insns(w).wdata.map { _ := RegNext(getWdata(rob.io.commit.uops(w), rob.io.commit.debug_wdata(w))) }
// Comment out this assert because it blows up FPGA synth-asserts
// This tests correctedness of the debug_inst mem
// when (RegNext(rob.io.commit.valids(w))) {
// assert(rob.io.commit.debug_insts(w) === RegNext(rob.io.commit.uops(w).debug_inst))
// }
// This tests correctedness of recovering pcs through ftq debug ports
// when (RegNext(rob.io.commit.valids(w))) {
// assert(Sext(io.trace.insns(w).iaddr, xLen) ===
// RegNext(Sext(rob.io.commit.uops(w).debug_pc(vaddrBits-1,0), xLen)))
// }
// These csr signals do not exactly match up with the ROB commit signals.
io.trace.insns(w).priv := RegNext(Cat(RegNext(csr.io.status.debug), csr.io.status.prv))
// Can determine if it is an interrupt or not based on the MSB of the cause
io.trace.insns(w).exception := RegNext(rob.io.com_xcpt.valid && !rob.io.com_xcpt.bits.cause(xLen - 1)) && (w == 0).B
io.trace.insns(w).interrupt := RegNext(rob.io.com_xcpt.valid && rob.io.com_xcpt.bits.cause(xLen - 1)) && (w == 0).B
io.trace.insns(w).cause := RegNext(rob.io.com_xcpt.bits.cause)
io.trace.insns(w).tval := RegNext(csr.io.tval)
}
dontTouch(io.trace)
} else {
io.ifu.debug_ftq_idx := DontCare
}
}
File Counters.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
// Produces 0-width value when counting to 1
class ZCounter(val n: Int) {
val value = RegInit(0.U(log2Ceil(n).W))
def inc(): Bool = {
if (n == 1) true.B
else {
val wrap = value === (n-1).U
value := Mux(!isPow2(n).B && wrap, 0.U, value + 1.U)
wrap
}
}
}
object ZCounter {
def apply(n: Int) = new ZCounter(n)
def apply(cond: Bool, n: Int): (UInt, Bool) = {
val c = new ZCounter(n)
var wrap: Bool = null
when (cond) { wrap = c.inc() }
(c.value, cond && wrap)
}
}
object TwoWayCounter {
def apply(up: Bool, down: Bool, max: Int): UInt = {
val cnt = RegInit(0.U(log2Up(max + 1).W))
when (up && !down) { cnt := cnt + 1.U }
when (down && !up) { cnt := cnt - 1.U }
cnt
}
}
// a counter that clock gates most of its MSBs using the LSB carry-out
case class WideCounter(width: Int, inc: UInt = 1.U, reset: Boolean = true, inhibit: Bool = false.B) {
private val isWide = width > (2 * inc.getWidth)
private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width
private val small = if (reset) RegInit(0.U(smallWidth.W)) else Reg(UInt(smallWidth.W))
private val nextSmall = small +& inc
when (!inhibit) { small := nextSmall }
private val large = if (isWide) {
val r = if (reset) RegInit(0.U((width - smallWidth).W)) else Reg(UInt((width - smallWidth).W))
when (nextSmall(smallWidth) && !inhibit) { r := r + 1.U }
r
} else null
val value = if (isWide) Cat(large, small) else small
lazy val carryOut = {
val lo = (small ^ nextSmall) >> 1
if (!isWide)
lo
else {
val hi = Mux(nextSmall(smallWidth), large ^ (large +& 1.U), 0.U) >> 1
Cat(hi, lo)
}
}
def := (x: UInt) = {
small := x
if (isWide) large := x >> smallWidth
}
}
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File Events.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.log2Ceil
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
class EventSet(val gate: (UInt, UInt) => Bool, val events: Seq[(String, () => Bool)]) {
def size = events.size
val hits = WireDefault(VecInit(Seq.fill(size)(false.B)))
def check(mask: UInt) = {
hits := events.map(_._2())
gate(mask, hits.asUInt)
}
def dump(): Unit = {
for (((name, _), i) <- events.zipWithIndex)
when (check(1.U << i)) { printf(s"Event $name\n") }
}
def withCovers: Unit = {
events.zipWithIndex.foreach {
case ((name, func), i) => property.cover(gate((1.U << i), (func() << i)), name)
}
}
}
class EventSets(val eventSets: Seq[EventSet]) {
def maskEventSelector(eventSel: UInt): UInt = {
// allow full associativity between counters and event sets (for now?)
val setMask = (BigInt(1) << eventSetIdBits) - 1
val maskMask = ((BigInt(1) << eventSets.map(_.size).max) - 1) << maxEventSetIdBits
eventSel & (setMask | maskMask).U
}
private def decode(counter: UInt): (UInt, UInt) = {
require(eventSets.size <= (1 << maxEventSetIdBits))
require(eventSetIdBits > 0)
(counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits)
}
def evaluate(eventSel: UInt): Bool = {
val (set, mask) = decode(eventSel)
val sets = for (e <- eventSets) yield {
require(e.hits.getWidth <= mask.getWidth, s"too many events ${e.hits.getWidth} wider than mask ${mask.getWidth}")
e check mask
}
sets(set)
}
def cover() = eventSets.foreach { _.withCovers }
private def eventSetIdBits = log2Ceil(eventSets.size)
private def maxEventSetIdBits = 8
require(eventSetIdBits <= maxEventSetIdBits)
}
class SuperscalarEventSets(val eventSets: Seq[(Seq[EventSet], (UInt, UInt) => UInt)]) {
def evaluate(eventSel: UInt): UInt = {
val (set, mask) = decode(eventSel)
val sets = for ((sets, reducer) <- eventSets) yield {
sets.map { set =>
require(set.hits.getWidth <= mask.getWidth, s"too many events ${set.hits.getWidth} wider than mask ${mask.getWidth}")
set.check(mask)
}.reduce(reducer)
}
val zeroPadded = sets.padTo(1 << eventSetIdBits, 0.U)
zeroPadded(set)
}
def toScalarEventSets: EventSets = new EventSets(eventSets.map(_._1.head))
def cover(): Unit = { eventSets.foreach(_._1.foreach(_.withCovers)) }
private def decode(counter: UInt): (UInt, UInt) = {
require(eventSets.size <= (1 << maxEventSetIdBits))
require(eventSetIdBits > 0)
(counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits)
}
private def eventSetIdBits = log2Ceil(eventSets.size)
private def maxEventSetIdBits = 8
require(eventSets.forall(s => s._1.forall(_.size == s._1.head.size)))
require(eventSetIdBits <= maxEventSetIdBits)
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
File frontend.scala:
//******************************************************************************
// Copyright (c) 2017 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Frontend
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.rocket._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property._
import boom.v3.common._
import boom.v3.exu.{CommitExceptionSignals, BranchDecode, BrUpdateInfo, BranchDecodeSignals}
import boom.v3.util._
class FrontendResp(implicit p: Parameters) extends BoomBundle()(p) {
val pc = UInt(vaddrBitsExtended.W) // ID stage PC
val data = UInt((fetchWidth * coreInstBits).W)
val mask = UInt(fetchWidth.W)
val xcpt = new FrontendExceptions
val ghist = new GlobalHistory
// fsrc provides the prediction FROM a branch in this packet
// tsrc provides the prediction TO this packet
val fsrc = UInt(BSRC_SZ.W)
val tsrc = UInt(BSRC_SZ.W)
}
class GlobalHistory(implicit p: Parameters) extends BoomBundle()(p)
with HasBoomFrontendParameters
{
// For the dual banked case, each bank ignores the contribution of the
// last bank to the history. Thus we have to track the most recent update to the
// history in that case
val old_history = UInt(globalHistoryLength.W)
val current_saw_branch_not_taken = Bool()
val new_saw_branch_not_taken = Bool()
val new_saw_branch_taken = Bool()
val ras_idx = UInt(log2Ceil(nRasEntries).W)
def histories(bank: Int) = {
if (nBanks == 1) {
old_history
} else {
require(nBanks == 2)
if (bank == 0) {
old_history
} else {
Mux(new_saw_branch_taken , old_history << 1 | 1.U,
Mux(new_saw_branch_not_taken , old_history << 1,
old_history))
}
}
}
def ===(other: GlobalHistory): Bool = {
((old_history === other.old_history) &&
(new_saw_branch_not_taken === other.new_saw_branch_not_taken) &&
(new_saw_branch_taken === other.new_saw_branch_taken)
)
}
def =/=(other: GlobalHistory): Bool = !(this === other)
def update(branches: UInt, cfi_taken: Bool, cfi_is_br: Bool, cfi_idx: UInt,
cfi_valid: Bool, addr: UInt,
cfi_is_call: Bool, cfi_is_ret: Bool): GlobalHistory = {
val cfi_idx_fixed = cfi_idx(log2Ceil(fetchWidth)-1,0)
val cfi_idx_oh = UIntToOH(cfi_idx_fixed)
val new_history = Wire(new GlobalHistory)
val not_taken_branches = branches & Mux(cfi_valid,
MaskLower(cfi_idx_oh) & ~Mux(cfi_is_br && cfi_taken, cfi_idx_oh, 0.U(fetchWidth.W)),
~(0.U(fetchWidth.W)))
if (nBanks == 1) {
// In the single bank case every bank sees the history including the previous bank
new_history := DontCare
new_history.current_saw_branch_not_taken := false.B
val saw_not_taken_branch = not_taken_branches =/= 0.U || current_saw_branch_not_taken
new_history.old_history := Mux(cfi_is_br && cfi_taken && cfi_valid , histories(0) << 1 | 1.U,
Mux(saw_not_taken_branch , histories(0) << 1,
histories(0)))
} else {
// In the two bank case every bank ignore the history added by the previous bank
val base = histories(1)
val cfi_in_bank_0 = cfi_valid && cfi_taken && cfi_idx_fixed < bankWidth.U
val ignore_second_bank = cfi_in_bank_0 || mayNotBeDualBanked(addr)
val first_bank_saw_not_taken = not_taken_branches(bankWidth-1,0) =/= 0.U || current_saw_branch_not_taken
new_history.current_saw_branch_not_taken := false.B
when (ignore_second_bank) {
new_history.old_history := histories(1)
new_history.new_saw_branch_not_taken := first_bank_saw_not_taken
new_history.new_saw_branch_taken := cfi_is_br && cfi_in_bank_0
} .otherwise {
new_history.old_history := Mux(cfi_is_br && cfi_in_bank_0 , histories(1) << 1 | 1.U,
Mux(first_bank_saw_not_taken , histories(1) << 1,
histories(1)))
new_history.new_saw_branch_not_taken := not_taken_branches(fetchWidth-1,bankWidth) =/= 0.U
new_history.new_saw_branch_taken := cfi_valid && cfi_taken && cfi_is_br && !cfi_in_bank_0
}
}
new_history.ras_idx := Mux(cfi_valid && cfi_is_call, WrapInc(ras_idx, nRasEntries),
Mux(cfi_valid && cfi_is_ret , WrapDec(ras_idx, nRasEntries), ras_idx))
new_history
}
}
/**
* Parameters to manage a L1 Banked ICache
*/
trait HasBoomFrontendParameters extends HasL1ICacheParameters
{
// How many banks does the ICache use?
val nBanks = if (cacheParams.fetchBytes <= 8) 1 else 2
// How many bytes wide is a bank?
val bankBytes = fetchBytes/nBanks
val bankWidth = fetchWidth/nBanks
require(nBanks == 1 || nBanks == 2)
// How many "chunks"/interleavings make up a cache line?
val numChunks = cacheParams.blockBytes / bankBytes
// Which bank is the address pointing to?
def bank(addr: UInt) = if (nBanks == 2) addr(log2Ceil(bankBytes)) else 0.U
def isLastBankInBlock(addr: UInt) = {
(nBanks == 2).B && addr(blockOffBits-1, log2Ceil(bankBytes)) === (numChunks-1).U
}
def mayNotBeDualBanked(addr: UInt) = {
require(nBanks == 2)
isLastBankInBlock(addr)
}
def blockAlign(addr: UInt) = ~(~addr | (cacheParams.blockBytes-1).U)
def bankAlign(addr: UInt) = ~(~addr | (bankBytes-1).U)
def fetchIdx(addr: UInt) = addr >> log2Ceil(fetchBytes)
def nextBank(addr: UInt) = bankAlign(addr) + bankBytes.U
def nextFetch(addr: UInt) = {
if (nBanks == 1) {
bankAlign(addr) + bankBytes.U
} else {
require(nBanks == 2)
bankAlign(addr) + Mux(mayNotBeDualBanked(addr), bankBytes.U, fetchBytes.U)
}
}
def fetchMask(addr: UInt) = {
val idx = addr.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))
if (nBanks == 1) {
((1 << fetchWidth)-1).U << idx
} else {
val shamt = idx.extract(log2Ceil(fetchWidth)-2, 0)
val end_mask = Mux(mayNotBeDualBanked(addr), Fill(fetchWidth/2, 1.U), Fill(fetchWidth, 1.U))
((1 << fetchWidth)-1).U << shamt & end_mask
}
}
def bankMask(addr: UInt) = {
val idx = addr.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))
if (nBanks == 1) {
1.U(1.W)
} else {
Mux(mayNotBeDualBanked(addr), 1.U(2.W), 3.U(2.W))
}
}
}
/**
* Bundle passed into the FetchBuffer and used to combine multiple
* relevant signals together.
*/
class FetchBundle(implicit p: Parameters) extends BoomBundle
with HasBoomFrontendParameters
{
val pc = UInt(vaddrBitsExtended.W)
val next_pc = UInt(vaddrBitsExtended.W)
val edge_inst = Vec(nBanks, Bool()) // True if 1st instruction in this bundle is pc - 2
val insts = Vec(fetchWidth, Bits(32.W))
val exp_insts = Vec(fetchWidth, Bits(32.W))
// Information for sfb folding
// NOTE: This IS NOT equivalent to uop.pc_lob, that gets calculated in the FB
val sfbs = Vec(fetchWidth, Bool())
val sfb_masks = Vec(fetchWidth, UInt((2*fetchWidth).W))
val sfb_dests = Vec(fetchWidth, UInt((1+log2Ceil(fetchBytes)).W))
val shadowable_mask = Vec(fetchWidth, Bool())
val shadowed_mask = Vec(fetchWidth, Bool())
val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W))
val cfi_type = UInt(CFI_SZ.W)
val cfi_is_call = Bool()
val cfi_is_ret = Bool()
val cfi_npc_plus4 = Bool()
val ras_top = UInt(vaddrBitsExtended.W)
val ftq_idx = UInt(log2Ceil(ftqSz).W)
val mask = UInt(fetchWidth.W) // mark which words are valid instructions
val br_mask = UInt(fetchWidth.W)
val ghist = new GlobalHistory
val lhist = Vec(nBanks, UInt(localHistoryLength.W))
val xcpt_pf_if = Bool() // I-TLB miss (instruction fetch fault).
val xcpt_ae_if = Bool() // Access exception.
val bp_debug_if_oh= Vec(fetchWidth, Bool())
val bp_xcpt_if_oh = Vec(fetchWidth, Bool())
val end_half = Valid(UInt(16.W))
val bpd_meta = Vec(nBanks, UInt())
// Source of the prediction from this bundle
val fsrc = UInt(BSRC_SZ.W)
// Source of the prediction to this bundle
val tsrc = UInt(BSRC_SZ.W)
}
/**
* IO for the BOOM Frontend to/from the CPU
*/
class BoomFrontendIO(implicit p: Parameters) extends BoomBundle
{
// Give the backend a packet of instructions.
val fetchpacket = Flipped(new DecoupledIO(new FetchBufferResp))
// 1 for xcpt/jalr/auipc/flush
val get_pc = Flipped(Vec(2, new GetPCFromFtqIO()))
val debug_ftq_idx = Output(Vec(coreWidth, UInt(log2Ceil(ftqSz).W)))
val debug_fetch_pc = Input(Vec(coreWidth, UInt(vaddrBitsExtended.W)))
// Breakpoint info
val status = Output(new MStatus)
val bp = Output(Vec(nBreakpoints, new BP))
val mcontext = Output(UInt(coreParams.mcontextWidth.W))
val scontext = Output(UInt(coreParams.scontextWidth.W))
val sfence = Valid(new SFenceReq)
val brupdate = Output(new BrUpdateInfo)
// Redirects change the PC
val redirect_flush = Output(Bool()) // Flush and hang the frontend?
val redirect_val = Output(Bool()) // Redirect the frontend?
val redirect_pc = Output(UInt()) // Where do we redirect to?
val redirect_ftq_idx = Output(UInt()) // Which ftq entry should we reset to?
val redirect_ghist = Output(new GlobalHistory) // What are we setting as the global history?
val commit = Valid(UInt(ftqSz.W))
val flush_icache = Output(Bool())
val perf = Input(new FrontendPerfEvents)
}
/**
* Top level Frontend class
*
* @param icacheParams parameters for the icache
* @param hartid id for the hardware thread of the core
*/
class BoomFrontend(val icacheParams: ICacheParams, staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends LazyModule
{
lazy val module = new BoomFrontendModule(this)
val icache = LazyModule(new boom.v3.ifu.ICache(icacheParams, staticIdForMetadataUseOnly))
val masterNode = icache.masterNode
val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() =>
UInt(masterNode.edges.out.head.bundle.addressBits.W)))
}
/**
* Bundle wrapping the IO for the Frontend as a whole
*
* @param outer top level Frontend class
*/
class BoomFrontendBundle(val outer: BoomFrontend) extends CoreBundle()(outer.p)
{
val cpu = Flipped(new BoomFrontendIO())
val ptw = new TLBPTWIO()
}
/**
* Main Frontend module that connects the icache, TLB, fetch controller,
* and branch prediction pipeline together.
*
* @param outer top level Frontend class
*/
class BoomFrontendModule(outer: BoomFrontend) extends LazyModuleImp(outer)
with HasBoomCoreParameters
with HasBoomFrontendParameters
{
val io = IO(new BoomFrontendBundle(outer))
val io_reset_vector = outer.resetVectorSinkNode.bundle
implicit val edge = outer.masterNode.edges.out(0)
require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes)
val bpd = Module(new BranchPredictor)
bpd.io.f3_fire := false.B
val ras = Module(new BoomRAS)
val icache = outer.icache.module
icache.io.invalidate := io.cpu.flush_icache
val tlb = Module(new TLB(true, log2Ceil(fetchBytes), TLBConfig(nTLBSets, nTLBWays)))
io.ptw <> tlb.io.ptw
io.cpu.perf.tlbMiss := io.ptw.req.fire
io.cpu.perf.acquire := icache.io.perf.acquire
// --------------------------------------------------------
// **** NextPC Select (F0) ****
// Send request to ICache
// --------------------------------------------------------
val s0_vpc = WireInit(0.U(vaddrBitsExtended.W))
val s0_ghist = WireInit((0.U).asTypeOf(new GlobalHistory))
val s0_tsrc = WireInit(0.U(BSRC_SZ.W))
val s0_valid = WireInit(false.B)
val s0_is_replay = WireInit(false.B)
val s0_is_sfence = WireInit(false.B)
val s0_replay_resp = Wire(new TLBResp(log2Ceil(fetchBytes)))
val s0_replay_bpd_resp = Wire(new BranchPredictionBundle)
val s0_replay_ppc = Wire(UInt())
val s0_s1_use_f3_bpd_resp = WireInit(false.B)
when (RegNext(reset.asBool) && !reset.asBool) {
s0_valid := true.B
s0_vpc := io_reset_vector
s0_ghist := (0.U).asTypeOf(new GlobalHistory)
s0_tsrc := BSRC_C
}
icache.io.req.valid := s0_valid
icache.io.req.bits.addr := s0_vpc
bpd.io.f0_req.valid := s0_valid
bpd.io.f0_req.bits.pc := s0_vpc
bpd.io.f0_req.bits.ghist := s0_ghist
// --------------------------------------------------------
// **** ICache Access (F1) ****
// Translate VPC
// --------------------------------------------------------
val s1_vpc = RegNext(s0_vpc)
val s1_valid = RegNext(s0_valid, false.B)
val s1_ghist = RegNext(s0_ghist)
val s1_is_replay = RegNext(s0_is_replay)
val s1_is_sfence = RegNext(s0_is_sfence)
val f1_clear = WireInit(false.B)
val s1_tsrc = RegNext(s0_tsrc)
tlb.io.req.valid := (s1_valid && !s1_is_replay && !f1_clear) || s1_is_sfence
tlb.io.req.bits.cmd := DontCare
tlb.io.req.bits.vaddr := s1_vpc
tlb.io.req.bits.passthrough := false.B
tlb.io.req.bits.size := log2Ceil(coreInstBytes * fetchWidth).U
tlb.io.req.bits.v := io.ptw.status.v
tlb.io.req.bits.prv := io.ptw.status.prv
tlb.io.sfence := RegNext(io.cpu.sfence)
tlb.io.kill := false.B
val s1_tlb_miss = !s1_is_replay && tlb.io.resp.miss
val s1_tlb_resp = Mux(s1_is_replay, RegNext(s0_replay_resp), tlb.io.resp)
val s1_ppc = Mux(s1_is_replay, RegNext(s0_replay_ppc), tlb.io.resp.paddr)
val s1_bpd_resp = bpd.io.resp.f1
icache.io.s1_paddr := s1_ppc
icache.io.s1_kill := tlb.io.resp.miss || f1_clear
val f1_mask = fetchMask(s1_vpc)
val f1_redirects = (0 until fetchWidth) map { i =>
s1_valid && f1_mask(i) && s1_bpd_resp.preds(i).predicted_pc.valid &&
(s1_bpd_resp.preds(i).is_jal ||
(s1_bpd_resp.preds(i).is_br && s1_bpd_resp.preds(i).taken))
}
val f1_redirect_idx = PriorityEncoder(f1_redirects)
val f1_do_redirect = f1_redirects.reduce(_||_) && useBPD.B
val f1_targs = s1_bpd_resp.preds.map(_.predicted_pc.bits)
val f1_predicted_target = Mux(f1_do_redirect,
f1_targs(f1_redirect_idx),
nextFetch(s1_vpc))
val f1_predicted_ghist = s1_ghist.update(
s1_bpd_resp.preds.map(p => p.is_br && p.predicted_pc.valid).asUInt & f1_mask,
s1_bpd_resp.preds(f1_redirect_idx).taken && f1_do_redirect,
s1_bpd_resp.preds(f1_redirect_idx).is_br,
f1_redirect_idx,
f1_do_redirect,
s1_vpc,
false.B,
false.B)
when (s1_valid && !s1_tlb_miss) {
// Stop fetching on fault
s0_valid := !(s1_tlb_resp.ae.inst || s1_tlb_resp.pf.inst)
s0_tsrc := BSRC_1
s0_vpc := f1_predicted_target
s0_ghist := f1_predicted_ghist
s0_is_replay := false.B
}
// --------------------------------------------------------
// **** ICache Response (F2) ****
// --------------------------------------------------------
val s2_valid = RegNext(s1_valid && !f1_clear, false.B)
val s2_vpc = RegNext(s1_vpc)
val s2_ghist = Reg(new GlobalHistory)
s2_ghist := s1_ghist
val s2_ppc = RegNext(s1_ppc)
val s2_tsrc = RegNext(s1_tsrc) // tsrc provides the predictor component which provided the prediction TO this instruction
val s2_fsrc = WireInit(BSRC_1) // fsrc provides the predictor component which provided the prediction FROM this instruction
val f2_clear = WireInit(false.B)
val s2_tlb_resp = RegNext(s1_tlb_resp)
val s2_tlb_miss = RegNext(s1_tlb_miss)
val s2_is_replay = RegNext(s1_is_replay) && s2_valid
val s2_xcpt = s2_valid && (s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst) && !s2_is_replay
val f3_ready = Wire(Bool())
icache.io.s2_kill := s2_xcpt
val f2_bpd_resp = bpd.io.resp.f2
val f2_mask = fetchMask(s2_vpc)
val f2_redirects = (0 until fetchWidth) map { i =>
s2_valid && f2_mask(i) && f2_bpd_resp.preds(i).predicted_pc.valid &&
(f2_bpd_resp.preds(i).is_jal ||
(f2_bpd_resp.preds(i).is_br && f2_bpd_resp.preds(i).taken))
}
val f2_redirect_idx = PriorityEncoder(f2_redirects)
val f2_targs = f2_bpd_resp.preds.map(_.predicted_pc.bits)
val f2_do_redirect = f2_redirects.reduce(_||_) && useBPD.B
val f2_predicted_target = Mux(f2_do_redirect,
f2_targs(f2_redirect_idx),
nextFetch(s2_vpc))
val f2_predicted_ghist = s2_ghist.update(
f2_bpd_resp.preds.map(p => p.is_br && p.predicted_pc.valid).asUInt & f2_mask,
f2_bpd_resp.preds(f2_redirect_idx).taken && f2_do_redirect,
f2_bpd_resp.preds(f2_redirect_idx).is_br,
f2_redirect_idx,
f2_do_redirect,
s2_vpc,
false.B,
false.B)
val f2_correct_f1_ghist = s1_ghist =/= f2_predicted_ghist && enableGHistStallRepair.B
when ((s2_valid && !icache.io.resp.valid) ||
(s2_valid && icache.io.resp.valid && !f3_ready)) {
s0_valid := (!s2_tlb_resp.ae.inst && !s2_tlb_resp.pf.inst) || s2_is_replay || s2_tlb_miss
s0_vpc := s2_vpc
s0_is_replay := s2_valid && icache.io.resp.valid
// When this is not a replay (it queried the BPDs, we should use f3 resp in the replaying s1)
s0_s1_use_f3_bpd_resp := !s2_is_replay
s0_ghist := s2_ghist
s0_tsrc := s2_tsrc
f1_clear := true.B
} .elsewhen (s2_valid && f3_ready) {
when (s1_valid && s1_vpc === f2_predicted_target && !f2_correct_f1_ghist) {
// We trust our prediction of what the global history for the next branch should be
s2_ghist := f2_predicted_ghist
}
when ((s1_valid && (s1_vpc =/= f2_predicted_target || f2_correct_f1_ghist)) || !s1_valid) {
f1_clear := true.B
s0_valid := !((s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst) && !s2_is_replay)
s0_vpc := f2_predicted_target
s0_is_replay := false.B
s0_ghist := f2_predicted_ghist
s2_fsrc := BSRC_2
s0_tsrc := BSRC_2
}
}
s0_replay_bpd_resp := f2_bpd_resp
s0_replay_resp := s2_tlb_resp
s0_replay_ppc := s2_ppc
// --------------------------------------------------------
// **** F3 ****
// --------------------------------------------------------
val f3_clear = WireInit(false.B)
val f3 = withReset(reset.asBool || f3_clear) {
Module(new Queue(new FrontendResp, 1, pipe=true, flow=false)) }
// Queue up the bpd resp as well, incase f4 backpressures f3
// This is "flow" because the response (enq) arrives in f3, not f2
val f3_bpd_resp = withReset(reset.asBool || f3_clear) {
Module(new Queue(new BranchPredictionBundle, 1, pipe=true, flow=true)) }
val f4_ready = Wire(Bool())
f3_ready := f3.io.enq.ready
f3.io.enq.valid := (s2_valid && !f2_clear &&
(icache.io.resp.valid || ((s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst) && !s2_tlb_miss))
)
f3.io.enq.bits.pc := s2_vpc
f3.io.enq.bits.data := Mux(s2_xcpt, 0.U, icache.io.resp.bits.data)
f3.io.enq.bits.ghist := s2_ghist
f3.io.enq.bits.mask := fetchMask(s2_vpc)
f3.io.enq.bits.xcpt := s2_tlb_resp
f3.io.enq.bits.fsrc := s2_fsrc
f3.io.enq.bits.tsrc := s2_tsrc
// RAS takes a cycle to read
val ras_read_idx = RegInit(0.U(log2Ceil(nRasEntries).W))
ras.io.read_idx := ras_read_idx
when (f3.io.enq.fire) {
ras_read_idx := f3.io.enq.bits.ghist.ras_idx
ras.io.read_idx := f3.io.enq.bits.ghist.ras_idx
}
// The BPD resp comes in f3
f3_bpd_resp.io.enq.valid := f3.io.deq.valid && RegNext(f3.io.enq.ready)
f3_bpd_resp.io.enq.bits := bpd.io.resp.f3
when (f3_bpd_resp.io.enq.fire) {
bpd.io.f3_fire := true.B
}
f3.io.deq.ready := f4_ready
f3_bpd_resp.io.deq.ready := f4_ready
val f3_imemresp = f3.io.deq.bits
val f3_bank_mask = bankMask(f3_imemresp.pc)
val f3_data = f3_imemresp.data
val f3_aligned_pc = bankAlign(f3_imemresp.pc)
val f3_is_last_bank_in_block = isLastBankInBlock(f3_aligned_pc)
val f3_is_rvc = Wire(Vec(fetchWidth, Bool()))
val f3_redirects = Wire(Vec(fetchWidth, Bool()))
val f3_targs = Wire(Vec(fetchWidth, UInt(vaddrBitsExtended.W)))
val f3_cfi_types = Wire(Vec(fetchWidth, UInt(CFI_SZ.W)))
val f3_shadowed_mask = Wire(Vec(fetchWidth, Bool()))
val f3_fetch_bundle = Wire(new FetchBundle)
val f3_mask = Wire(Vec(fetchWidth, Bool()))
val f3_br_mask = Wire(Vec(fetchWidth, Bool()))
val f3_call_mask = Wire(Vec(fetchWidth, Bool()))
val f3_ret_mask = Wire(Vec(fetchWidth, Bool()))
val f3_npc_plus4_mask = Wire(Vec(fetchWidth, Bool()))
val f3_btb_mispredicts = Wire(Vec(fetchWidth, Bool()))
f3_fetch_bundle.mask := f3_mask.asUInt
f3_fetch_bundle.br_mask := f3_br_mask.asUInt
f3_fetch_bundle.pc := f3_imemresp.pc
f3_fetch_bundle.ftq_idx := 0.U // This gets assigned later
f3_fetch_bundle.xcpt_pf_if := f3_imemresp.xcpt.pf.inst
f3_fetch_bundle.xcpt_ae_if := f3_imemresp.xcpt.ae.inst
f3_fetch_bundle.fsrc := f3_imemresp.fsrc
f3_fetch_bundle.tsrc := f3_imemresp.tsrc
f3_fetch_bundle.shadowed_mask := f3_shadowed_mask
// Tracks trailing 16b of previous fetch packet
val f3_prev_half = Reg(UInt(16.W))
// Tracks if last fetchpacket contained a half-inst
val f3_prev_is_half = RegInit(false.B)
require(fetchWidth >= 4) // Logic gets kind of annoying with fetchWidth = 2
def isRVC(inst: UInt) = (inst(1,0) =/= 3.U)
var redirect_found = false.B
var bank_prev_is_half = f3_prev_is_half
var bank_prev_half = f3_prev_half
var last_inst = 0.U(16.W)
for (b <- 0 until nBanks) {
val bank_data = f3_data((b+1)*bankWidth*16-1, b*bankWidth*16)
val bank_mask = Wire(Vec(bankWidth, Bool()))
val bank_insts = Wire(Vec(bankWidth, UInt(32.W)))
for (w <- 0 until bankWidth) {
val i = (b * bankWidth) + w
val valid = Wire(Bool())
val bpu = Module(new BreakpointUnit(nBreakpoints))
bpu.io.status := io.cpu.status
bpu.io.bp := io.cpu.bp
bpu.io.ea := DontCare
bpu.io.mcontext := io.cpu.mcontext
bpu.io.scontext := io.cpu.scontext
val brsigs = Wire(new BranchDecodeSignals)
if (w == 0) {
val inst0 = Cat(bank_data(15,0), f3_prev_half)
val inst1 = bank_data(31,0)
val exp_inst0 = ExpandRVC(inst0)
val exp_inst1 = ExpandRVC(inst1)
val pc0 = (f3_aligned_pc + (i << log2Ceil(coreInstBytes)).U - 2.U)
val pc1 = (f3_aligned_pc + (i << log2Ceil(coreInstBytes)).U)
val bpd_decoder0 = Module(new BranchDecode)
bpd_decoder0.io.inst := exp_inst0
bpd_decoder0.io.pc := pc0
val bpd_decoder1 = Module(new BranchDecode)
bpd_decoder1.io.inst := exp_inst1
bpd_decoder1.io.pc := pc1
when (bank_prev_is_half) {
bank_insts(w) := inst0
f3_fetch_bundle.insts(i) := inst0
f3_fetch_bundle.exp_insts(i) := exp_inst0
bpu.io.pc := pc0
brsigs := bpd_decoder0.io.out
f3_fetch_bundle.edge_inst(b) := true.B
if (b > 0) {
val inst0b = Cat(bank_data(15,0), last_inst)
val exp_inst0b = ExpandRVC(inst0b)
val bpd_decoder0b = Module(new BranchDecode)
bpd_decoder0b.io.inst := exp_inst0b
bpd_decoder0b.io.pc := pc0
when (f3_bank_mask(b-1)) {
bank_insts(w) := inst0b
f3_fetch_bundle.insts(i) := inst0b
f3_fetch_bundle.exp_insts(i) := exp_inst0b
brsigs := bpd_decoder0b.io.out
}
}
} .otherwise {
bank_insts(w) := inst1
f3_fetch_bundle.insts(i) := inst1
f3_fetch_bundle.exp_insts(i) := exp_inst1
bpu.io.pc := pc1
brsigs := bpd_decoder1.io.out
f3_fetch_bundle.edge_inst(b) := false.B
}
valid := true.B
} else {
val inst = Wire(UInt(32.W))
val exp_inst = ExpandRVC(inst)
val pc = f3_aligned_pc + (i << log2Ceil(coreInstBytes)).U
val bpd_decoder = Module(new BranchDecode)
bpd_decoder.io.inst := exp_inst
bpd_decoder.io.pc := pc
bank_insts(w) := inst
f3_fetch_bundle.insts(i) := inst
f3_fetch_bundle.exp_insts(i) := exp_inst
bpu.io.pc := pc
brsigs := bpd_decoder.io.out
if (w == 1) {
// Need special case since 0th instruction may carry over the wrap around
inst := bank_data(47,16)
valid := bank_prev_is_half || !(bank_mask(0) && !isRVC(bank_insts(0)))
} else if (w == bankWidth - 1) {
inst := Cat(0.U(16.W), bank_data(bankWidth*16-1,(bankWidth-1)*16))
valid := !((bank_mask(w-1) && !isRVC(bank_insts(w-1))) ||
!isRVC(inst))
} else {
inst := bank_data(w*16+32-1,w*16)
valid := !(bank_mask(w-1) && !isRVC(bank_insts(w-1)))
}
}
f3_is_rvc(i) := isRVC(bank_insts(w))
bank_mask(w) := f3.io.deq.valid && f3_imemresp.mask(i) && valid && !redirect_found
f3_mask (i) := f3.io.deq.valid && f3_imemresp.mask(i) && valid && !redirect_found
f3_targs (i) := Mux(brsigs.cfi_type === CFI_JALR,
f3_bpd_resp.io.deq.bits.preds(i).predicted_pc.bits,
brsigs.target)
// Flush BTB entries for JALs if we mispredict the target
f3_btb_mispredicts(i) := (brsigs.cfi_type === CFI_JAL && valid &&
f3_bpd_resp.io.deq.bits.preds(i).predicted_pc.valid &&
(f3_bpd_resp.io.deq.bits.preds(i).predicted_pc.bits =/= brsigs.target)
)
f3_npc_plus4_mask(i) := (if (w == 0) {
!f3_is_rvc(i) && !bank_prev_is_half
} else {
!f3_is_rvc(i)
})
val offset_from_aligned_pc = (
(i << 1).U((log2Ceil(icBlockBytes)+1).W) +
brsigs.sfb_offset.bits -
Mux(bank_prev_is_half && (w == 0).B, 2.U, 0.U)
)
val lower_mask = Wire(UInt((2*fetchWidth).W))
val upper_mask = Wire(UInt((2*fetchWidth).W))
lower_mask := UIntToOH(i.U)
upper_mask := UIntToOH(offset_from_aligned_pc(log2Ceil(fetchBytes)+1,1)) << Mux(f3_is_last_bank_in_block, bankWidth.U, 0.U)
f3_fetch_bundle.sfbs(i) := (
f3_mask(i) &&
brsigs.sfb_offset.valid &&
(offset_from_aligned_pc <= Mux(f3_is_last_bank_in_block, (fetchBytes+bankBytes).U,(2*fetchBytes).U))
)
f3_fetch_bundle.sfb_masks(i) := ~MaskLower(lower_mask) & ~MaskUpper(upper_mask)
f3_fetch_bundle.shadowable_mask(i) := (!(f3_fetch_bundle.xcpt_pf_if || f3_fetch_bundle.xcpt_ae_if || bpu.io.debug_if || bpu.io.xcpt_if) &&
f3_bank_mask(b) &&
(brsigs.shadowable || !f3_mask(i)))
f3_fetch_bundle.sfb_dests(i) := offset_from_aligned_pc
// Redirect if
// 1) its a JAL/JALR (unconditional)
// 2) the BPD believes this is a branch and says we should take it
f3_redirects(i) := f3_mask(i) && (
brsigs.cfi_type === CFI_JAL || brsigs.cfi_type === CFI_JALR ||
(brsigs.cfi_type === CFI_BR && f3_bpd_resp.io.deq.bits.preds(i).taken && useBPD.B)
)
f3_br_mask(i) := f3_mask(i) && brsigs.cfi_type === CFI_BR
f3_cfi_types(i) := brsigs.cfi_type
f3_call_mask(i) := brsigs.is_call
f3_ret_mask(i) := brsigs.is_ret
f3_fetch_bundle.bp_debug_if_oh(i) := bpu.io.debug_if
f3_fetch_bundle.bp_xcpt_if_oh (i) := bpu.io.xcpt_if
redirect_found = redirect_found || f3_redirects(i)
}
last_inst = bank_insts(bankWidth-1)(15,0)
bank_prev_is_half = Mux(f3_bank_mask(b),
(!(bank_mask(bankWidth-2) && !isRVC(bank_insts(bankWidth-2))) && !isRVC(last_inst)),
bank_prev_is_half)
bank_prev_half = Mux(f3_bank_mask(b),
last_inst(15,0),
bank_prev_half)
}
f3_fetch_bundle.cfi_type := f3_cfi_types(f3_fetch_bundle.cfi_idx.bits)
f3_fetch_bundle.cfi_is_call := f3_call_mask(f3_fetch_bundle.cfi_idx.bits)
f3_fetch_bundle.cfi_is_ret := f3_ret_mask (f3_fetch_bundle.cfi_idx.bits)
f3_fetch_bundle.cfi_npc_plus4 := f3_npc_plus4_mask(f3_fetch_bundle.cfi_idx.bits)
f3_fetch_bundle.ghist := f3.io.deq.bits.ghist
f3_fetch_bundle.lhist := f3_bpd_resp.io.deq.bits.lhist
f3_fetch_bundle.bpd_meta := f3_bpd_resp.io.deq.bits.meta
f3_fetch_bundle.end_half.valid := bank_prev_is_half
f3_fetch_bundle.end_half.bits := bank_prev_half
when (f3.io.deq.fire) {
f3_prev_is_half := bank_prev_is_half
f3_prev_half := bank_prev_half
assert(f3_bpd_resp.io.deq.bits.pc === f3_fetch_bundle.pc)
}
when (f3_clear) {
f3_prev_is_half := false.B
}
f3_fetch_bundle.cfi_idx.valid := f3_redirects.reduce(_||_)
f3_fetch_bundle.cfi_idx.bits := PriorityEncoder(f3_redirects)
f3_fetch_bundle.ras_top := ras.io.read_addr
// Redirect earlier stages only if the later stage
// can consume this packet
val f3_predicted_target = Mux(f3_redirects.reduce(_||_),
Mux(f3_fetch_bundle.cfi_is_ret && useBPD.B && useRAS.B,
ras.io.read_addr,
f3_targs(PriorityEncoder(f3_redirects))
),
nextFetch(f3_fetch_bundle.pc)
)
f3_fetch_bundle.next_pc := f3_predicted_target
val f3_predicted_ghist = f3_fetch_bundle.ghist.update(
f3_fetch_bundle.br_mask,
f3_fetch_bundle.cfi_idx.valid,
f3_fetch_bundle.br_mask(f3_fetch_bundle.cfi_idx.bits),
f3_fetch_bundle.cfi_idx.bits,
f3_fetch_bundle.cfi_idx.valid,
f3_fetch_bundle.pc,
f3_fetch_bundle.cfi_is_call,
f3_fetch_bundle.cfi_is_ret
)
ras.io.write_valid := false.B
ras.io.write_addr := f3_aligned_pc + (f3_fetch_bundle.cfi_idx.bits << 1) + Mux(
f3_fetch_bundle.cfi_npc_plus4, 4.U, 2.U)
ras.io.write_idx := WrapInc(f3_fetch_bundle.ghist.ras_idx, nRasEntries)
val f3_correct_f1_ghist = s1_ghist =/= f3_predicted_ghist && enableGHistStallRepair.B
val f3_correct_f2_ghist = s2_ghist =/= f3_predicted_ghist && enableGHistStallRepair.B
when (f3.io.deq.valid && f4_ready) {
when (f3_fetch_bundle.cfi_is_call && f3_fetch_bundle.cfi_idx.valid) {
ras.io.write_valid := true.B
}
when (f3_redirects.reduce(_||_)) {
f3_prev_is_half := false.B
}
when (s2_valid && s2_vpc === f3_predicted_target && !f3_correct_f2_ghist) {
f3.io.enq.bits.ghist := f3_predicted_ghist
} .elsewhen (!s2_valid && s1_valid && s1_vpc === f3_predicted_target && !f3_correct_f1_ghist) {
s2_ghist := f3_predicted_ghist
} .elsewhen (( s2_valid && (s2_vpc =/= f3_predicted_target || f3_correct_f2_ghist)) ||
(!s2_valid && s1_valid && (s1_vpc =/= f3_predicted_target || f3_correct_f1_ghist)) ||
(!s2_valid && !s1_valid)) {
f2_clear := true.B
f1_clear := true.B
s0_valid := !(f3_fetch_bundle.xcpt_pf_if || f3_fetch_bundle.xcpt_ae_if)
s0_vpc := f3_predicted_target
s0_is_replay := false.B
s0_ghist := f3_predicted_ghist
s0_tsrc := BSRC_3
f3_fetch_bundle.fsrc := BSRC_3
}
}
// When f3 finds a btb mispredict, queue up a bpd correction update
val f4_btb_corrections = Module(new Queue(new BranchPredictionUpdate, 2))
f4_btb_corrections.io.enq.valid := f3.io.deq.fire && f3_btb_mispredicts.reduce(_||_) && enableBTBFastRepair.B
f4_btb_corrections.io.enq.bits := DontCare
f4_btb_corrections.io.enq.bits.is_mispredict_update := false.B
f4_btb_corrections.io.enq.bits.is_repair_update := false.B
f4_btb_corrections.io.enq.bits.btb_mispredicts := f3_btb_mispredicts.asUInt
f4_btb_corrections.io.enq.bits.pc := f3_fetch_bundle.pc
f4_btb_corrections.io.enq.bits.ghist := f3_fetch_bundle.ghist
f4_btb_corrections.io.enq.bits.lhist := f3_fetch_bundle.lhist
f4_btb_corrections.io.enq.bits.meta := f3_fetch_bundle.bpd_meta
// -------------------------------------------------------
// **** F4 ****
// -------------------------------------------------------
val f4_clear = WireInit(false.B)
val f4 = withReset(reset.asBool || f4_clear) {
Module(new Queue(new FetchBundle, 1, pipe=true, flow=false))}
val fb = Module(new FetchBuffer)
val ftq = Module(new FetchTargetQueue)
// When we mispredict, we need to repair
// Deal with sfbs
val f4_shadowable_masks = VecInit((0 until fetchWidth) map { i =>
f4.io.deq.bits.shadowable_mask.asUInt |
~f4.io.deq.bits.sfb_masks(i)(fetchWidth-1,0)
})
val f3_shadowable_masks = VecInit((0 until fetchWidth) map { i =>
Mux(f4.io.enq.valid, f4.io.enq.bits.shadowable_mask.asUInt, 0.U) |
~f4.io.deq.bits.sfb_masks(i)(2*fetchWidth-1,fetchWidth)
})
val f4_sfbs = VecInit((0 until fetchWidth) map { i =>
enableSFBOpt.B &&
((~f4_shadowable_masks(i) === 0.U) &&
(~f3_shadowable_masks(i) === 0.U) &&
f4.io.deq.bits.sfbs(i) &&
!(f4.io.deq.bits.cfi_idx.valid && f4.io.deq.bits.cfi_idx.bits === i.U) &&
Mux(f4.io.deq.bits.sfb_dests(i) === 0.U,
!bank_prev_is_half,
Mux(f4.io.deq.bits.sfb_dests(i) === fetchBytes.U,
!f4.io.deq.bits.end_half.valid,
true.B)
)
)
})
val f4_sfb_valid = f4_sfbs.reduce(_||_) && f4.io.deq.valid
val f4_sfb_idx = PriorityEncoder(f4_sfbs)
val f4_sfb_mask = f4.io.deq.bits.sfb_masks(f4_sfb_idx)
// If we have a SFB, wait for next fetch to be available in f3
val f4_delay = (
f4.io.deq.bits.sfbs.reduce(_||_) &&
!f4.io.deq.bits.cfi_idx.valid &&
!f4.io.enq.valid &&
!f4.io.deq.bits.xcpt_pf_if &&
!f4.io.deq.bits.xcpt_ae_if
)
when (f4_sfb_valid) {
f3_shadowed_mask := f4_sfb_mask(2*fetchWidth-1,fetchWidth).asBools
} .otherwise {
f3_shadowed_mask := VecInit(0.U(fetchWidth.W).asBools)
}
f4_ready := f4.io.enq.ready
f4.io.enq.valid := f3.io.deq.valid && !f3_clear
f4.io.enq.bits := f3_fetch_bundle
f4.io.deq.ready := fb.io.enq.ready && ftq.io.enq.ready && !f4_delay
fb.io.enq.valid := f4.io.deq.valid && ftq.io.enq.ready && !f4_delay
fb.io.enq.bits := f4.io.deq.bits
fb.io.enq.bits.ftq_idx := ftq.io.enq_idx
fb.io.enq.bits.sfbs := Mux(f4_sfb_valid, UIntToOH(f4_sfb_idx), 0.U(fetchWidth.W)).asBools
fb.io.enq.bits.shadowed_mask := (
Mux(f4_sfb_valid, f4_sfb_mask(fetchWidth-1,0), 0.U(fetchWidth.W)) |
f4.io.deq.bits.shadowed_mask.asUInt
).asBools
ftq.io.enq.valid := f4.io.deq.valid && fb.io.enq.ready && !f4_delay
ftq.io.enq.bits := f4.io.deq.bits
val bpd_update_arbiter = Module(new Arbiter(new BranchPredictionUpdate, 2))
bpd_update_arbiter.io.in(0).valid := ftq.io.bpdupdate.valid
bpd_update_arbiter.io.in(0).bits := ftq.io.bpdupdate.bits
assert(bpd_update_arbiter.io.in(0).ready)
bpd_update_arbiter.io.in(1) <> f4_btb_corrections.io.deq
bpd.io.update := bpd_update_arbiter.io.out
bpd_update_arbiter.io.out.ready := true.B
when (ftq.io.ras_update && enableRasTopRepair.B) {
ras.io.write_valid := true.B
ras.io.write_idx := ftq.io.ras_update_idx
ras.io.write_addr := ftq.io.ras_update_pc
}
// -------------------------------------------------------
// **** To Core (F5) ****
// -------------------------------------------------------
io.cpu.fetchpacket <> fb.io.deq
io.cpu.get_pc <> ftq.io.get_ftq_pc
ftq.io.deq := io.cpu.commit
ftq.io.brupdate := io.cpu.brupdate
ftq.io.redirect.valid := io.cpu.redirect_val
ftq.io.redirect.bits := io.cpu.redirect_ftq_idx
fb.io.clear := false.B
when (io.cpu.sfence.valid) {
fb.io.clear := true.B
f4_clear := true.B
f3_clear := true.B
f2_clear := true.B
f1_clear := true.B
s0_valid := false.B
s0_vpc := io.cpu.sfence.bits.addr
s0_is_replay := false.B
s0_is_sfence := true.B
}.elsewhen (io.cpu.redirect_flush) {
fb.io.clear := true.B
f4_clear := true.B
f3_clear := true.B
f2_clear := true.B
f1_clear := true.B
f3_prev_is_half := false.B
s0_valid := io.cpu.redirect_val
s0_vpc := io.cpu.redirect_pc
s0_ghist := io.cpu.redirect_ghist
s0_tsrc := BSRC_C
s0_is_replay := false.B
ftq.io.redirect.valid := io.cpu.redirect_val
ftq.io.redirect.bits := io.cpu.redirect_ftq_idx
}
ftq.io.debug_ftq_idx := io.cpu.debug_ftq_idx
io.cpu.debug_fetch_pc := ftq.io.debug_fetch_pc
override def toString: String =
(BoomCoreStringPrefix("====Overall Frontend Params====") + "\n"
+ icache.toString + bpd.toString)
}
File regfile.scala:
//******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Register File (Abstract class and Synthesizable RegFile)
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.exu
import scala.collection.mutable.ArrayBuffer
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
/**
* IO bundle for a register read port
*
* @param addrWidth size of register address in bits
* @param dataWidth size of register in bits
*/
class RegisterFileReadPortIO(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
{
val addr = Input(UInt(addrWidth.W))
val data = Output(UInt(dataWidth.W))
}
/**
* IO bundle for the register write port
*
* @param addrWidth size of register address in bits
* @param dataWidth size of register in bits
*/
class RegisterFileWritePort(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
{
val addr = UInt(addrWidth.W)
val data = UInt(dataWidth.W)
}
/**
* Utility function to turn ExeUnitResps to match the regfile's WritePort I/Os.
*/
object WritePort
{
def apply(enq: DecoupledIO[ExeUnitResp], addrWidth: Int, dataWidth: Int, rtype: UInt)
(implicit p: Parameters): Valid[RegisterFileWritePort] = {
val wport = Wire(Valid(new RegisterFileWritePort(addrWidth, dataWidth)))
wport.valid := enq.valid && enq.bits.uop.dst_rtype === rtype
wport.bits.addr := enq.bits.uop.pdst
wport.bits.data := enq.bits.data
enq.ready := true.B
wport
}
}
/**
* Register file abstract class
*
* @param numRegisters number of registers
* @param numReadPorts number of read ports
* @param numWritePorts number of write ports
* @param registerWidth size of registers in bits
* @param bypassableArray list of write ports from func units to the read port of the regfile
*/
abstract class RegisterFile(
numRegisters: Int,
numReadPorts: Int,
numWritePorts: Int,
registerWidth: Int,
bypassableArray: Seq[Boolean]) // which write ports can be bypassed to the read ports?
(implicit p: Parameters) extends BoomModule
{
val io = IO(new BoomBundle {
val read_ports = Vec(numReadPorts, new RegisterFileReadPortIO(maxPregSz, registerWidth))
val write_ports = Flipped(Vec(numWritePorts, Valid(new RegisterFileWritePort(maxPregSz, registerWidth))))
})
private val rf_cost = (numReadPorts + numWritePorts) * (numReadPorts + 2*numWritePorts)
private val type_str = if (registerWidth == fLen+1) "Floating Point" else "Integer"
override def toString: String = BoomCoreStringPrefix(
"==" + type_str + " Regfile==",
"Num RF Read Ports : " + numReadPorts,
"Num RF Write Ports : " + numWritePorts,
"RF Cost (R+W)*(R+2W) : " + rf_cost,
"Bypassable Units : " + bypassableArray)
}
/**
* A synthesizable model of a Register File. You will likely want to blackbox this for more than modest port counts.
*
* @param numRegisters number of registers
* @param numReadPorts number of read ports
* @param numWritePorts number of write ports
* @param registerWidth size of registers in bits
* @param bypassableArray list of write ports from func units to the read port of the regfile
*/
class RegisterFileSynthesizable(
numRegisters: Int,
numReadPorts: Int,
numWritePorts: Int,
registerWidth: Int,
bypassableArray: Seq[Boolean])
(implicit p: Parameters)
extends RegisterFile(numRegisters, numReadPorts, numWritePorts, registerWidth, bypassableArray)
{
// --------------------------------------------------------------
val regfile = Mem(numRegisters, UInt(registerWidth.W))
// --------------------------------------------------------------
// Read ports.
val read_data = Wire(Vec(numReadPorts, UInt(registerWidth.W)))
// Register the read port addresses to give a full cycle to the RegisterRead Stage (if desired).
val read_addrs = io.read_ports.map(p => RegNext(p.addr))
for (i <- 0 until numReadPorts) {
read_data(i) := regfile(read_addrs(i))
}
// --------------------------------------------------------------
// Bypass out of the ALU's write ports.
// We are assuming we cannot bypass a writer to a reader within the regfile memory
// for a write that occurs at the end of cycle S1 and a read that returns data on cycle S1.
// But since these bypasses are expensive, and not all write ports need to bypass their data,
// only perform the w->r bypass on a select number of write ports.
require (bypassableArray.length == io.write_ports.length)
if (bypassableArray.reduce(_||_)) {
val bypassable_wports = ArrayBuffer[Valid[RegisterFileWritePort]]()
io.write_ports zip bypassableArray map { case (wport, b) => if (b) { bypassable_wports += wport} }
for (i <- 0 until numReadPorts) {
val bypass_ens = bypassable_wports.map(x => x.valid &&
x.bits.addr === read_addrs(i))
val bypass_data = Mux1H(VecInit(bypass_ens.toSeq), VecInit(bypassable_wports.map(_.bits.data).toSeq))
io.read_ports(i).data := Mux(bypass_ens.reduce(_|_), bypass_data, read_data(i))
}
} else {
for (i <- 0 until numReadPorts) {
io.read_ports(i).data := read_data(i)
}
}
// --------------------------------------------------------------
// Write ports.
for (wport <- io.write_ports) {
when (wport.valid) {
regfile(wport.bits.addr) := wport.bits.data
}
}
// ensure there is only 1 writer per register (unless to preg0)
if (numWritePorts > 1) {
for (i <- 0 until (numWritePorts - 1)) {
for (j <- (i + 1) until numWritePorts) {
assert(!io.write_ports(i).valid ||
!io.write_ports(j).valid ||
(io.write_ports(i).bits.addr =/= io.write_ports(j).bits.addr) ||
(io.write_ports(i).bits.addr === 0.U), // note: you only have to check one here
"[regfile] too many writers a register")
}
}
}
}
File execution-units.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISC-V Constructing the Execution Units
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.exu
import scala.collection.mutable.{ArrayBuffer}
import chisel3._
import org.chipsalliance.cde.config.{Parameters}
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
/**
* Top level class to wrap all execution units together into a "collection"
*
* @param fpu using a FPU?
*/
class ExecutionUnits(val fpu: Boolean)(implicit val p: Parameters) extends HasBoomCoreParameters
{
val totalIssueWidth = issueParams.map(_.issueWidth).sum
//*******************************
// Instantiate the ExecutionUnits
private val exe_units = ArrayBuffer[ExecutionUnit]()
//*******************************
// Act like a collection
def length = exe_units.length
def apply(n: Int) = exe_units(n)
def map[T](f: ExecutionUnit => T) = {
exe_units.map(f)
}
def withFilter(f: ExecutionUnit => Boolean) = {
exe_units.withFilter(f)
}
def foreach[U](f: ExecutionUnit => U) = {
exe_units.foreach(f)
}
def zipWithIndex = {
exe_units.zipWithIndex
}
def indexWhere(f: ExecutionUnit => Boolean) = {
exe_units.indexWhere(f)
}
def count(f: ExecutionUnit => Boolean) = {
exe_units.count(f)
}
lazy val memory_units = {
exe_units.filter(_.hasMem)
}
lazy val alu_units = {
exe_units.filter(_.hasAlu)
}
lazy val csr_unit = {
require (exe_units.count(_.hasCSR) == 1)
exe_units.find(_.hasCSR).get
}
lazy val ifpu_unit = {
require (usingFPU)
require (exe_units.count(_.hasIfpu) == 1)
exe_units.find(_.hasIfpu).get
}
lazy val fpiu_unit = {
require (usingFPU)
require (exe_units.count(_.hasFpiu) == 1)
exe_units.find(_.hasFpiu).get
}
lazy val jmp_unit_idx = {
exe_units.indexWhere(_.hasJmpUnit)
}
lazy val rocc_unit = {
require (usingRoCC)
require (exe_units.count(_.hasRocc) == 1)
exe_units.find(_.hasRocc).get
}
if (!fpu) {
val int_width = issueParams.find(_.iqType == IQT_INT.litValue).get.issueWidth
for (w <- 0 until memWidth) {
val memExeUnit = Module(new ALUExeUnit(
hasAlu = false,
hasMem = true))
memExeUnit.io.ll_iresp.ready := DontCare
exe_units += memExeUnit
}
for (w <- 0 until int_width) {
def is_nth(n: Int): Boolean = w == ((n) % int_width)
val alu_exe_unit = Module(new ALUExeUnit(
hasJmpUnit = is_nth(0),
hasCSR = is_nth(1),
hasRocc = is_nth(1) && usingRoCC,
hasMul = is_nth(2),
hasDiv = is_nth(3),
hasIfpu = is_nth(4) && usingFPU))
exe_units += alu_exe_unit
}
} else {
val fp_width = issueParams.find(_.iqType == IQT_FP.litValue).get.issueWidth
for (w <- 0 until fp_width) {
val fpu_exe_unit = Module(new FPUExeUnit(hasFpu = true,
hasFdiv = usingFDivSqrt && (w==0),
hasFpiu = (w==0)))
exe_units += fpu_exe_unit
}
}
val exeUnitsStr = new StringBuilder
for (exe_unit <- exe_units) {
exeUnitsStr.append(exe_unit.toString)
}
override def toString: String =
(BoomCoreStringPrefix("===ExecutionUnits===") + "\n"
+ (if (!fpu) {
BoomCoreStringPrefix(
"==" + coreWidth + "-wide Machine==",
"==" + totalIssueWidth + " Issue==")
} else {
""
}) + "\n"
+ exeUnitsStr.toString)
require (exe_units.length != 0)
if (!fpu) {
// if this is for FPU units, we don't need a memory unit (or other integer units).
require (exe_units.map(_.hasMem).reduce(_|_), "Datapath is missing a memory unit.")
require (exe_units.map(_.hasMul).reduce(_|_), "Datapath is missing a multiplier.")
require (exe_units.map(_.hasDiv).reduce(_|_), "Datapath is missing a divider.")
} else {
require (exe_units.map(_.hasFpu).reduce(_|_),
"Datapath is missing a fpu (or has an fpu and shouldnt).")
}
val numIrfReaders = exe_units.count(_.readsIrf)
val numIrfReadPorts = exe_units.count(_.readsIrf) * 2
val numIrfWritePorts = exe_units.count(_.writesIrf)
val numLlIrfWritePorts = exe_units.count(_.writesLlIrf)
val numTotalBypassPorts = exe_units.withFilter(_.bypassable).map(_.numBypassStages).foldLeft(0)(_+_)
val numFrfReaders = exe_units.count(_.readsFrf)
val numFrfReadPorts = exe_units.count(_.readsFrf) * 3
val numFrfWritePorts = exe_units.count(_.writesFrf)
val numLlFrfWritePorts = exe_units.count(_.writesLlFrf)
// The mem-unit will also bypass writes to readers in the RRD stage.
// NOTE: This does NOT include the ll_wport
val bypassable_write_port_mask = exe_units.withFilter(x => x.writesIrf).map(u => u.bypassable)
}
File micro-op.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// MicroOp
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.exu.FUConstants
/**
* Extension to BoomBundle to add a MicroOp
*/
abstract trait HasBoomUOP extends BoomBundle
{
val uop = new MicroOp()
}
/**
* MicroOp passing through the pipeline
*/
class MicroOp(implicit p: Parameters) extends BoomBundle
with freechips.rocketchip.rocket.constants.MemoryOpConstants
with freechips.rocketchip.rocket.constants.ScalarOpConstants
{
val uopc = UInt(UOPC_SZ.W) // micro-op code
val inst = UInt(32.W)
val debug_inst = UInt(32.W)
val is_rvc = Bool()
val debug_pc = UInt(coreMaxAddrBits.W)
val iq_type = UInt(IQT_SZ.W) // which issue unit do we use?
val fu_code = UInt(FUConstants.FUC_SZ.W) // which functional unit do we use?
val ctrl = new CtrlSignals
// What is the next state of this uop in the issue window? useful
// for the compacting queue.
val iw_state = UInt(2.W)
// Has operand 1 or 2 been waken speculatively by a load?
// Only integer operands are speculaively woken up,
// so we can ignore p3.
val iw_p1_poisoned = Bool()
val iw_p2_poisoned = Bool()
val is_br = Bool() // is this micro-op a (branch) vs a regular PC+4 inst?
val is_jalr = Bool() // is this a jump? (jal or jalr)
val is_jal = Bool() // is this a JAL (doesn't include JR)? used for branch unit
val is_sfb = Bool() // is this a sfb or in the shadow of a sfb
val br_mask = UInt(maxBrCount.W) // which branches are we being speculated under?
val br_tag = UInt(brTagSz.W)
// Index into FTQ to figure out our fetch PC.
val ftq_idx = UInt(log2Ceil(ftqSz).W)
// This inst straddles two fetch packets
val edge_inst = Bool()
// Low-order bits of our own PC. Combine with ftq[ftq_idx] to get PC.
// Aligned to a cache-line size, as that is the greater fetch granularity.
// TODO: Shouldn't this be aligned to fetch-width size?
val pc_lob = UInt(log2Ceil(icBlockBytes).W)
// Was this a branch that was predicted taken?
val taken = Bool()
val imm_packed = UInt(LONGEST_IMM_SZ.W) // densely pack the imm in decode...
// then translate and sign-extend in execute
val csr_addr = UInt(CSR_ADDR_SZ.W) // only used for critical path reasons in Exe
val rob_idx = UInt(robAddrSz.W)
val ldq_idx = UInt(ldqAddrSz.W)
val stq_idx = UInt(stqAddrSz.W)
val rxq_idx = UInt(log2Ceil(numRxqEntries).W)
val pdst = UInt(maxPregSz.W)
val prs1 = UInt(maxPregSz.W)
val prs2 = UInt(maxPregSz.W)
val prs3 = UInt(maxPregSz.W)
val ppred = UInt(log2Ceil(ftqSz).W)
val prs1_busy = Bool()
val prs2_busy = Bool()
val prs3_busy = Bool()
val ppred_busy = Bool()
val stale_pdst = UInt(maxPregSz.W)
val exception = Bool()
val exc_cause = UInt(xLen.W) // TODO compress this down, xlen is insanity
val bypassable = Bool() // can we bypass ALU results? (doesn't include loads, csr, etc...)
val mem_cmd = UInt(M_SZ.W) // sync primitives/cache flushes
val mem_size = UInt(2.W)
val mem_signed = Bool()
val is_fence = Bool()
val is_fencei = Bool()
val is_amo = Bool()
val uses_ldq = Bool()
val uses_stq = Bool()
val is_sys_pc2epc = Bool() // Is a ECall or Breakpoint -- both set EPC to PC.
val is_unique = Bool() // only allow this instruction in the pipeline, wait for STQ to
// drain, clear fetcha fter it (tell ROB to un-ready until empty)
val flush_on_commit = Bool() // some instructions need to flush the pipeline behind them
// Preditation
def is_sfb_br = is_br && is_sfb && enableSFBOpt.B // Does this write a predicate
def is_sfb_shadow = !is_br && is_sfb && enableSFBOpt.B // Is this predicated
val ldst_is_rs1 = Bool() // If this is set and we are predicated off, copy rs1 to dst,
// else copy rs2 to dst
// logical specifiers (only used in Decode->Rename), except rollback (ldst)
val ldst = UInt(lregSz.W)
val lrs1 = UInt(lregSz.W)
val lrs2 = UInt(lregSz.W)
val lrs3 = UInt(lregSz.W)
val ldst_val = Bool() // is there a destination? invalid for stores, rd==x0, etc.
val dst_rtype = UInt(2.W)
val lrs1_rtype = UInt(2.W)
val lrs2_rtype = UInt(2.W)
val frs3_en = Bool()
// floating point information
val fp_val = Bool() // is a floating-point instruction (F- or D-extension)?
// If it's non-ld/st it will write back exception bits to the fcsr.
val fp_single = Bool() // single-precision floating point instruction (F-extension)
// frontend exception information
val xcpt_pf_if = Bool() // I-TLB page fault.
val xcpt_ae_if = Bool() // I$ access exception.
val xcpt_ma_if = Bool() // Misaligned fetch (jal/brjumping to misaligned addr).
val bp_debug_if = Bool() // Breakpoint
val bp_xcpt_if = Bool() // Breakpoint
// What prediction structure provides the prediction FROM this op
val debug_fsrc = UInt(BSRC_SZ.W)
// What prediction structure provides the prediction TO this op
val debug_tsrc = UInt(BSRC_SZ.W)
// Do we allocate a branch tag for this?
// SFB branches don't get a mask, they get a predicate bit
def allocate_brtag = (is_br && !is_sfb) || is_jalr
// Does this register write-back
def rf_wen = dst_rtype =/= RT_X
// Is it possible for this uop to misspeculate, preventing the commit of subsequent uops?
def unsafe = uses_ldq || (uses_stq && !is_fence) || is_br || is_jalr
def fu_code_is(_fu: UInt) = (fu_code & _fu) =/= 0.U
}
/**
* Control signals within a MicroOp
*
* TODO REFACTOR this, as this should no longer be true, as bypass occurs in stage before branch resolution
*/
class CtrlSignals extends Bundle()
{
val br_type = UInt(BR_N.getWidth.W)
val op1_sel = UInt(OP1_X.getWidth.W)
val op2_sel = UInt(OP2_X.getWidth.W)
val imm_sel = UInt(IS_X.getWidth.W)
val op_fcn = UInt(freechips.rocketchip.rocket.ALU.SZ_ALU_FN.W)
val fcn_dw = Bool()
val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W)
val is_load = Bool() // will invoke TLB address lookup
val is_sta = Bool() // will invoke TLB address lookup
val is_std = Bool()
}
File CSR.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{BitPat, Cat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.devices.debug.DebugModuleKey
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
import scala.collection.mutable.LinkedHashMap
import Instructions._
import CustomInstructions._
class MStatus extends Bundle {
// not truly part of mstatus, but convenient
val debug = Bool()
val cease = Bool()
val wfi = Bool()
val isa = UInt(32.W)
val dprv = UInt(PRV.SZ.W) // effective prv for data accesses
val dv = Bool() // effective v for data accesses
val prv = UInt(PRV.SZ.W)
val v = Bool()
val sd = Bool()
val zero2 = UInt(23.W)
val mpv = Bool()
val gva = Bool()
val mbe = Bool()
val sbe = Bool()
val sxl = UInt(2.W)
val uxl = UInt(2.W)
val sd_rv32 = Bool()
val zero1 = UInt(8.W)
val tsr = Bool()
val tw = Bool()
val tvm = Bool()
val mxr = Bool()
val sum = Bool()
val mprv = Bool()
val xs = UInt(2.W)
val fs = UInt(2.W)
val mpp = UInt(2.W)
val vs = UInt(2.W)
val spp = UInt(1.W)
val mpie = Bool()
val ube = Bool()
val spie = Bool()
val upie = Bool()
val mie = Bool()
val hie = Bool()
val sie = Bool()
val uie = Bool()
}
class MNStatus extends Bundle {
val mpp = UInt(2.W)
val zero3 = UInt(3.W)
val mpv = Bool()
val zero2 = UInt(3.W)
val mie = Bool()
val zero1 = UInt(3.W)
}
class HStatus extends Bundle {
val zero6 = UInt(30.W)
val vsxl = UInt(2.W)
val zero5 = UInt(9.W)
val vtsr = Bool()
val vtw = Bool()
val vtvm = Bool()
val zero3 = UInt(2.W)
val vgein = UInt(6.W)
val zero2 = UInt(2.W)
val hu = Bool()
val spvp = Bool()
val spv = Bool()
val gva = Bool()
val vsbe = Bool()
val zero1 = UInt(5.W)
}
class DCSR extends Bundle {
val xdebugver = UInt(2.W)
val zero4 = UInt(2.W)
val zero3 = UInt(12.W)
val ebreakm = Bool()
val ebreakh = Bool()
val ebreaks = Bool()
val ebreaku = Bool()
val zero2 = Bool()
val stopcycle = Bool()
val stoptime = Bool()
val cause = UInt(3.W)
val v = Bool()
val zero1 = UInt(2.W)
val step = Bool()
val prv = UInt(PRV.SZ.W)
}
class MIP(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
val lip = Vec(coreParams.nLocalInterrupts, Bool())
val zero1 = Bool()
val debug = Bool() // keep in sync with CSR.debugIntCause
val rocc = Bool()
val sgeip = Bool()
val meip = Bool()
val vseip = Bool()
val seip = Bool()
val ueip = Bool()
val mtip = Bool()
val vstip = Bool()
val stip = Bool()
val utip = Bool()
val msip = Bool()
val vssip = Bool()
val ssip = Bool()
val usip = Bool()
}
class Envcfg extends Bundle {
val stce = Bool() // only for menvcfg/henvcfg
val pbmte = Bool() // only for menvcfg/henvcfg
val zero54 = UInt(54.W)
val cbze = Bool()
val cbcfe = Bool()
val cbie = UInt(2.W)
val zero3 = UInt(3.W)
val fiom = Bool()
def write(wdata: UInt) {
val new_envcfg = wdata.asTypeOf(new Envcfg)
fiom := new_envcfg.fiom // only FIOM is writable currently
}
}
class PTBR(implicit p: Parameters) extends CoreBundle()(p) {
def additionalPgLevels = mode.extract(log2Ceil(pgLevels-minPgLevels+1)-1, 0)
def pgLevelsToMode(i: Int) = (xLen, i) match {
case (32, 2) => 1
case (64, x) if x >= 3 && x <= 6 => x + 5
}
val (modeBits, maxASIdBits) = xLen match {
case 32 => (1, 9)
case 64 => (4, 16)
}
require(modeBits + maxASIdBits + maxPAddrBits - pgIdxBits == xLen)
val mode = UInt(modeBits.W)
val asid = UInt(maxASIdBits.W)
val ppn = UInt((maxPAddrBits - pgIdxBits).W)
}
object PRV
{
val SZ = 2
val U = 0
val S = 1
val H = 2
val M = 3
}
object CSR
{
// commands
val SZ = 3
def X = BitPat.dontCare(SZ)
def N = 0.U(SZ.W)
def R = 2.U(SZ.W)
def I = 4.U(SZ.W)
def W = 5.U(SZ.W)
def S = 6.U(SZ.W)
def C = 7.U(SZ.W)
// mask a CSR cmd with a valid bit
def maskCmd(valid: Bool, cmd: UInt): UInt = {
// all commands less than CSR.I are treated by CSRFile as NOPs
cmd & ~Mux(valid, 0.U, CSR.I)
}
val ADDRSZ = 12
def modeLSB: Int = 8
def mode(addr: Int): Int = (addr >> modeLSB) % (1 << PRV.SZ)
def mode(addr: UInt): UInt = addr(modeLSB + PRV.SZ - 1, modeLSB)
def busErrorIntCause = 128
def debugIntCause = 14 // keep in sync with MIP.debug
def debugTriggerCause = {
val res = debugIntCause
require(!(Causes.all contains res))
res
}
def rnmiIntCause = 13 // NMI: Higher numbers = higher priority, must not reuse debugIntCause
def rnmiBEUCause = 12
val firstCtr = CSRs.cycle
val firstCtrH = CSRs.cycleh
val firstHPC = CSRs.hpmcounter3
val firstHPCH = CSRs.hpmcounter3h
val firstHPE = CSRs.mhpmevent3
val firstMHPC = CSRs.mhpmcounter3
val firstMHPCH = CSRs.mhpmcounter3h
val firstHPM = 3
val nCtr = 32
val nHPM = nCtr - firstHPM
val hpmWidth = 40
val maxPMPs = 16
}
class PerfCounterIO(implicit p: Parameters) extends CoreBundle
with HasCoreParameters {
val eventSel = Output(UInt(xLen.W))
val inc = Input(UInt(log2Ceil(1+retireWidth).W))
}
class TracedInstruction(implicit p: Parameters) extends CoreBundle {
val valid = Bool()
val iaddr = UInt(coreMaxAddrBits.W)
val insn = UInt(iLen.W)
val priv = UInt(3.W)
val exception = Bool()
val interrupt = Bool()
val cause = UInt(xLen.W)
val tval = UInt((coreMaxAddrBits max iLen).W)
val wdata = Option.when(traceHasWdata)(UInt((vLen max xLen).W))
}
class TraceAux extends Bundle {
val enable = Bool()
val stall = Bool()
}
class CSRDecodeIO(implicit p: Parameters) extends CoreBundle {
val inst = Input(UInt(iLen.W))
def csr_addr = (inst >> 20)(CSR.ADDRSZ-1, 0)
val fp_illegal = Output(Bool())
val vector_illegal = Output(Bool())
val fp_csr = Output(Bool())
val vector_csr = Output(Bool())
val rocc_illegal = Output(Bool())
val read_illegal = Output(Bool())
val write_illegal = Output(Bool())
val write_flush = Output(Bool())
val system_illegal = Output(Bool())
val virtual_access_illegal = Output(Bool())
val virtual_system_illegal = Output(Bool())
}
class CSRFileIO(hasBeu: Boolean)(implicit p: Parameters) extends CoreBundle
with HasCoreParameters {
val ungated_clock = Input(Clock())
val interrupts = Input(new CoreInterrupts(hasBeu))
val hartid = Input(UInt(hartIdLen.W))
val rw = new Bundle {
val addr = Input(UInt(CSR.ADDRSZ.W))
val cmd = Input(Bits(CSR.SZ.W))
val rdata = Output(Bits(xLen.W))
val wdata = Input(Bits(xLen.W))
}
val decode = Vec(decodeWidth, new CSRDecodeIO)
val csr_stall = Output(Bool()) // stall retire for wfi
val rw_stall = Output(Bool()) // stall rw, rw will have no effect while rw_stall
val eret = Output(Bool())
val singleStep = Output(Bool())
val status = Output(new MStatus())
val hstatus = Output(new HStatus())
val gstatus = Output(new MStatus())
val ptbr = Output(new PTBR())
val hgatp = Output(new PTBR())
val vsatp = Output(new PTBR())
val evec = Output(UInt(vaddrBitsExtended.W))
val exception = Input(Bool())
val retire = Input(UInt(log2Up(1+retireWidth).W))
val cause = Input(UInt(xLen.W))
val pc = Input(UInt(vaddrBitsExtended.W))
val tval = Input(UInt(vaddrBitsExtended.W))
val htval = Input(UInt(((maxSVAddrBits + 1) min xLen).W))
val mhtinst_read_pseudo = Input(Bool())
val gva = Input(Bool())
val time = Output(UInt(xLen.W))
val fcsr_rm = Output(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Flipped(Valid(Bits(FPConstants.FLAGS_SZ.W)))
val set_fs_dirty = coreParams.haveFSDirty.option(Input(Bool()))
val rocc_interrupt = Input(Bool())
val interrupt = Output(Bool())
val interrupt_cause = Output(UInt(xLen.W))
val bp = Output(Vec(nBreakpoints, new BP))
val pmp = Output(Vec(nPMPs, new PMP))
val counters = Vec(nPerfCounters, new PerfCounterIO)
val csrw_counter = Output(UInt(CSR.nCtr.W))
val inhibit_cycle = Output(Bool())
val inst = Input(Vec(retireWidth, UInt(iLen.W)))
val trace = Output(Vec(retireWidth, new TracedInstruction))
val mcontext = Output(UInt(coreParams.mcontextWidth.W))
val scontext = Output(UInt(coreParams.scontextWidth.W))
val fiom = Output(Bool())
val vector = usingVector.option(new Bundle {
val vconfig = Output(new VConfig())
val vstart = Output(UInt(maxVLMax.log2.W))
val vxrm = Output(UInt(2.W))
val set_vs_dirty = Input(Bool())
val set_vconfig = Flipped(Valid(new VConfig))
val set_vstart = Flipped(Valid(vstart))
val set_vxsat = Input(Bool())
})
}
class VConfig(implicit p: Parameters) extends CoreBundle {
val vl = UInt((maxVLMax.log2 + 1).W)
val vtype = new VType
}
object VType {
def fromUInt(that: UInt, ignore_vill: Boolean = false)(implicit p: Parameters): VType = {
val res = 0.U.asTypeOf(new VType)
val in = that.asTypeOf(res)
val vill = (in.max_vsew.U < in.vsew) || !in.lmul_ok || in.reserved =/= 0.U || in.vill
when (!vill || ignore_vill.B) {
res := in
res.vsew := in.vsew(log2Ceil(1 + in.max_vsew) - 1, 0)
}
res.reserved := 0.U
res.vill := vill
res
}
def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool)(implicit p: Parameters): UInt =
VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useMax, useZero)
}
class VType(implicit p: Parameters) extends CoreBundle {
val vill = Bool()
val reserved = UInt((xLen - 9).W)
val vma = Bool()
val vta = Bool()
val vsew = UInt(3.W)
val vlmul_sign = Bool()
val vlmul_mag = UInt(2.W)
def vlmul_signed: SInt = Cat(vlmul_sign, vlmul_mag).asSInt
@deprecated("use vlmul_sign, vlmul_mag, or vlmul_signed", "RVV 0.9")
def vlmul: UInt = vlmul_mag
def max_vsew = log2Ceil(eLen/8)
def max_vlmul = (1 << vlmul_mag.getWidth) - 1
def lmul_ok: Bool = Mux(this.vlmul_sign, this.vlmul_mag =/= 0.U && ~this.vlmul_mag < max_vsew.U - this.vsew, true.B)
def minVLMax: Int = ((maxVLMax / eLen) >> ((1 << vlmul_mag.getWidth) - 1)) max 1
def vlMax: UInt = (maxVLMax.U >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).andNot((minVLMax-1).U)
def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool): UInt = {
val atLeastMaxVLMax = useMax || Mux(useCurrentVL, currentVL >= maxVLMax.U, avl >= maxVLMax.U)
val avl_lsbs = Mux(useCurrentVL, currentVL, avl)(maxVLMax.log2 - 1, 0)
val atLeastVLMax = atLeastMaxVLMax || (avl_lsbs & (-maxVLMax.S >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).asUInt.andNot((minVLMax-1).U)).orR
val isZero = vill || useZero
Mux(!isZero && atLeastVLMax, vlMax, 0.U) | Mux(!isZero && !atLeastVLMax, avl_lsbs, 0.U)
}
}
class CSRFile(
perfEventSets: EventSets = new EventSets(Seq()),
customCSRs: Seq[CustomCSR] = Nil,
roccCSRs: Seq[CustomCSR] = Nil,
hasBeu: Boolean = false)(implicit p: Parameters)
extends CoreModule()(p)
with HasCoreParameters {
val io = IO(new CSRFileIO(hasBeu) {
val customCSRs = Vec(CSRFile.this.customCSRs.size, new CustomCSRIO)
val roccCSRs = Vec(CSRFile.this.roccCSRs.size, new CustomCSRIO)
})
io.rw_stall := false.B
val reset_mstatus = WireDefault(0.U.asTypeOf(new MStatus()))
reset_mstatus.mpp := PRV.M.U
reset_mstatus.prv := PRV.M.U
reset_mstatus.xs := (if (usingRoCC) 3.U else 0.U)
val reg_mstatus = RegInit(reset_mstatus)
val new_prv = WireDefault(reg_mstatus.prv)
reg_mstatus.prv := legalizePrivilege(new_prv)
val reset_dcsr = WireDefault(0.U.asTypeOf(new DCSR()))
reset_dcsr.xdebugver := 1.U
reset_dcsr.prv := PRV.M.U
val reg_dcsr = RegInit(reset_dcsr)
val (supported_interrupts, delegable_interrupts) = {
val sup = Wire(new MIP)
sup.usip := false.B
sup.ssip := usingSupervisor.B
sup.vssip := usingHypervisor.B
sup.msip := true.B
sup.utip := false.B
sup.stip := usingSupervisor.B
sup.vstip := usingHypervisor.B
sup.mtip := true.B
sup.ueip := false.B
sup.seip := usingSupervisor.B
sup.vseip := usingHypervisor.B
sup.meip := true.B
sup.sgeip := false.B
sup.rocc := usingRoCC.B
sup.debug := false.B
sup.zero1 := false.B
sup.lip foreach { _ := true.B }
val supported_high_interrupts = if (io.interrupts.buserror.nonEmpty && !usingNMI) (BigInt(1) << CSR.busErrorIntCause).U else 0.U
val del = WireDefault(sup)
del.msip := false.B
del.mtip := false.B
del.meip := false.B
(sup.asUInt | supported_high_interrupts, del.asUInt)
}
val delegable_base_exceptions = Seq(
Causes.misaligned_fetch,
Causes.fetch_page_fault,
Causes.breakpoint,
Causes.load_page_fault,
Causes.store_page_fault,
Causes.misaligned_load,
Causes.misaligned_store,
Causes.illegal_instruction,
Causes.user_ecall,
)
val delegable_hypervisor_exceptions = Seq(
Causes.virtual_supervisor_ecall,
Causes.fetch_guest_page_fault,
Causes.load_guest_page_fault,
Causes.virtual_instruction,
Causes.store_guest_page_fault,
)
val delegable_exceptions = (
delegable_base_exceptions
++ (if (usingHypervisor) delegable_hypervisor_exceptions else Seq())
).map(1 << _).sum.U
val hs_delegable_exceptions = Seq(
Causes.misaligned_fetch,
Causes.fetch_access,
Causes.illegal_instruction,
Causes.breakpoint,
Causes.misaligned_load,
Causes.load_access,
Causes.misaligned_store,
Causes.store_access,
Causes.user_ecall,
Causes.fetch_page_fault,
Causes.load_page_fault,
Causes.store_page_fault).map(1 << _).sum.U
val (hs_delegable_interrupts, mideleg_always_hs) = {
val always = WireDefault(0.U.asTypeOf(new MIP()))
always.vssip := usingHypervisor.B
always.vstip := usingHypervisor.B
always.vseip := usingHypervisor.B
val deleg = WireDefault(always)
deleg.lip.foreach { _ := usingHypervisor.B }
(deleg.asUInt, always.asUInt)
}
val reg_debug = RegInit(false.B)
val reg_dpc = Reg(UInt(vaddrBitsExtended.W))
val reg_dscratch0 = Reg(UInt(xLen.W))
val reg_dscratch1 = (p(DebugModuleKey).map(_.nDscratch).getOrElse(1) > 1).option(Reg(UInt(xLen.W)))
val reg_singleStepped = Reg(Bool())
val reg_mcontext = (coreParams.mcontextWidth > 0).option(RegInit(0.U(coreParams.mcontextWidth.W)))
val reg_scontext = (coreParams.scontextWidth > 0).option(RegInit(0.U(coreParams.scontextWidth.W)))
val reg_tselect = Reg(UInt(log2Up(nBreakpoints).W))
val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP))
val reg_pmp = Reg(Vec(nPMPs, new PMPReg))
val reg_mie = Reg(UInt(xLen.W))
val (reg_mideleg, read_mideleg) = {
val reg = Reg(UInt(xLen.W))
(reg, Mux(usingSupervisor.B, reg & delegable_interrupts | mideleg_always_hs, 0.U))
}
val (reg_medeleg, read_medeleg) = {
val reg = Reg(UInt(xLen.W))
(reg, Mux(usingSupervisor.B, reg & delegable_exceptions, 0.U))
}
val reg_mip = Reg(new MIP)
val reg_mepc = Reg(UInt(vaddrBitsExtended.W))
val reg_mcause = RegInit(0.U(xLen.W))
val reg_mtval = Reg(UInt(vaddrBitsExtended.W))
val reg_mtval2 = Reg(UInt(((maxSVAddrBits + 1) min xLen).W))
val reg_mscratch = Reg(Bits(xLen.W))
val mtvecWidth = paddrBits min xLen
val reg_mtvec = mtvecInit match {
case Some(addr) => RegInit(addr.U(mtvecWidth.W))
case None => Reg(UInt(mtvecWidth.W))
}
val reset_mnstatus = WireDefault(0.U.asTypeOf(new MNStatus()))
reset_mnstatus.mpp := PRV.M.U
val reg_mnscratch = Reg(Bits(xLen.W))
val reg_mnepc = Reg(UInt(vaddrBitsExtended.W))
val reg_mncause = RegInit(0.U(xLen.W))
val reg_mnstatus = RegInit(reset_mnstatus)
val reg_rnmie = RegInit(true.B)
val nmie = reg_rnmie
val reg_menvcfg = RegInit(0.U.asTypeOf(new Envcfg))
val reg_senvcfg = RegInit(0.U.asTypeOf(new Envcfg))
val reg_henvcfg = RegInit(0.U.asTypeOf(new Envcfg))
val delegable_counters = ((BigInt(1) << (nPerfCounters + CSR.firstHPM)) - 1).U
val (reg_mcounteren, read_mcounteren) = {
val reg = Reg(UInt(32.W))
(reg, Mux(usingUser.B, reg & delegable_counters, 0.U))
}
val (reg_scounteren, read_scounteren) = {
val reg = Reg(UInt(32.W))
(reg, Mux(usingSupervisor.B, reg & delegable_counters, 0.U))
}
val (reg_hideleg, read_hideleg) = {
val reg = Reg(UInt(xLen.W))
(reg, Mux(usingHypervisor.B, reg & hs_delegable_interrupts, 0.U))
}
val (reg_hedeleg, read_hedeleg) = {
val reg = Reg(UInt(xLen.W))
(reg, Mux(usingHypervisor.B, reg & hs_delegable_exceptions, 0.U))
}
val hs_delegable_counters = delegable_counters
val (reg_hcounteren, read_hcounteren) = {
val reg = Reg(UInt(32.W))
(reg, Mux(usingHypervisor.B, reg & hs_delegable_counters, 0.U))
}
val reg_hstatus = RegInit(0.U.asTypeOf(new HStatus))
val reg_hgatp = Reg(new PTBR)
val reg_htval = Reg(reg_mtval2.cloneType)
val read_hvip = reg_mip.asUInt & hs_delegable_interrupts
val read_hie = reg_mie & hs_delegable_interrupts
val (reg_vstvec, read_vstvec) = {
val reg = Reg(UInt(vaddrBitsExtended.W))
(reg, formTVec(reg).sextTo(xLen))
}
val reg_vsstatus = Reg(new MStatus)
val reg_vsscratch = Reg(Bits(xLen.W))
val reg_vsepc = Reg(UInt(vaddrBitsExtended.W))
val reg_vscause = Reg(Bits(xLen.W))
val reg_vstval = Reg(UInt(vaddrBitsExtended.W))
val reg_vsatp = Reg(new PTBR)
val reg_sepc = Reg(UInt(vaddrBitsExtended.W))
val reg_scause = Reg(Bits(xLen.W))
val reg_stval = Reg(UInt(vaddrBitsExtended.W))
val reg_sscratch = Reg(Bits(xLen.W))
val reg_stvec = Reg(UInt((if (usingHypervisor) vaddrBitsExtended else vaddrBits).W))
val reg_satp = Reg(new PTBR)
val reg_wfi = withClock(io.ungated_clock) { RegInit(false.B) }
val reg_fflags = Reg(UInt(5.W))
val reg_frm = Reg(UInt(3.W))
val reg_vconfig = usingVector.option(Reg(new VConfig))
val reg_vstart = usingVector.option(Reg(UInt(maxVLMax.log2.W)))
val reg_vxsat = usingVector.option(Reg(Bool()))
val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W)))
val reg_mtinst_read_pseudo = Reg(Bool())
val reg_htinst_read_pseudo = Reg(Bool())
// XLEN=32: 0x00002000
// XLEN=64: 0x00003000
val Seq(read_mtinst, read_htinst) = Seq(reg_mtinst_read_pseudo, reg_htinst_read_pseudo).map(r => Cat(r, (xLen == 32).option(0.U).getOrElse(r), 0.U(12.W)))
val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W))
io.inhibit_cycle := reg_mcountinhibit(0)
val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2))
val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire, inhibit = reg_mcountinhibit(0))
else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) }
val reg_hpmevent = io.counters.map(c => RegInit(0.U(xLen.W)))
(io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e }
val reg_hpmcounter = io.counters.zipWithIndex.map { case (c, i) =>
WideCounter(CSR.hpmWidth, c.inc, reset = false, inhibit = reg_mcountinhibit(CSR.firstHPM+i)) }
val mip = WireDefault(reg_mip)
mip.lip := (io.interrupts.lip: Seq[Bool])
mip.mtip := io.interrupts.mtip
mip.msip := io.interrupts.msip
mip.meip := io.interrupts.meip
// seip is the OR of reg_mip.seip and the actual line from the PLIC
io.interrupts.seip.foreach { mip.seip := reg_mip.seip || _ }
// Simimlar sort of thing would apply if the PLIC had a VSEIP line:
//io.interrupts.vseip.foreach { mip.vseip := reg_mip.vseip || _ }
mip.rocc := io.rocc_interrupt
val read_mip = mip.asUInt & supported_interrupts
val read_hip = read_mip & hs_delegable_interrupts
val high_interrupts = (if (usingNMI) 0.U else io.interrupts.buserror.map(_ << CSR.busErrorIntCause).getOrElse(0.U))
val pending_interrupts = high_interrupts | (read_mip & reg_mie)
val d_interrupts = io.interrupts.debug << CSR.debugIntCause
val (nmi_interrupts, nmiFlag) = io.interrupts.nmi.map(nmi =>
(((nmi.rnmi && reg_rnmie) << CSR.rnmiIntCause) |
io.interrupts.buserror.map(_ << CSR.rnmiBEUCause).getOrElse(0.U),
!io.interrupts.debug && nmi.rnmi && reg_rnmie)).getOrElse(0.U, false.B)
val m_interrupts = Mux(nmie && (reg_mstatus.prv <= PRV.S.U || reg_mstatus.mie), ~(~pending_interrupts | read_mideleg), 0.U)
val s_interrupts = Mux(nmie && (reg_mstatus.v || reg_mstatus.prv < PRV.S.U || (reg_mstatus.prv === PRV.S.U && reg_mstatus.sie)), pending_interrupts & read_mideleg & ~read_hideleg, 0.U)
val vs_interrupts = Mux(nmie && (reg_mstatus.v && (reg_mstatus.prv < PRV.S.U || reg_mstatus.prv === PRV.S.U && reg_vsstatus.sie)), pending_interrupts & read_hideleg, 0.U)
val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(vs_interrupts, s_interrupts, m_interrupts, nmi_interrupts, d_interrupts))
val interruptMSB = BigInt(1) << (xLen-1)
val interruptCause = interruptMSB.U + (nmiFlag << (xLen-2)) + whichInterrupt
io.interrupt := (anyInterrupt && !io.singleStep || reg_singleStepped) && !(reg_debug || io.status.cease)
io.interrupt_cause := interruptCause
io.bp := reg_bp take nBreakpoints
io.mcontext := reg_mcontext.getOrElse(0.U)
io.scontext := reg_scontext.getOrElse(0.U)
io.fiom := (reg_mstatus.prv < PRV.M.U && reg_menvcfg.fiom) || (reg_mstatus.prv < PRV.S.U && reg_senvcfg.fiom) || (reg_mstatus.v && reg_henvcfg.fiom)
io.pmp := reg_pmp.map(PMP(_))
val isaMaskString =
(if (usingMulDiv) "M" else "") +
(if (usingAtomics) "A" else "") +
(if (fLen >= 32) "F" else "") +
(if (fLen >= 64) "D" else "") +
(if (coreParams.hasV) "V" else "") +
(if (usingCompressed) "C" else "")
val isaString = (if (coreParams.useRVE) "E" else "I") +
isaMaskString +
(if (customIsaExt.isDefined || usingRoCC) "X" else "") +
(if (usingSupervisor) "S" else "") +
(if (usingHypervisor) "H" else "") +
(if (usingUser) "U" else "")
val isaMax = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) | isaStringToMask(isaString)
val reg_misa = RegInit(isaMax.U)
val read_mstatus = io.status.asUInt.extract(xLen-1,0)
val read_mtvec = formTVec(reg_mtvec).padTo(xLen)
val read_stvec = formTVec(reg_stvec).sextTo(xLen)
val read_mapping = LinkedHashMap[Int,Bits](
CSRs.tselect -> reg_tselect,
CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt,
CSRs.tdata2 -> reg_bp(reg_tselect).address.sextTo(xLen),
CSRs.tdata3 -> reg_bp(reg_tselect).textra.asUInt,
CSRs.misa -> reg_misa,
CSRs.mstatus -> read_mstatus,
CSRs.mtvec -> read_mtvec,
CSRs.mip -> read_mip,
CSRs.mie -> reg_mie,
CSRs.mscratch -> reg_mscratch,
CSRs.mepc -> readEPC(reg_mepc).sextTo(xLen),
CSRs.mtval -> reg_mtval.sextTo(xLen),
CSRs.mcause -> reg_mcause,
CSRs.mhartid -> io.hartid)
val debug_csrs = if (!usingDebug) LinkedHashMap() else LinkedHashMap[Int,Bits](
CSRs.dcsr -> reg_dcsr.asUInt,
CSRs.dpc -> readEPC(reg_dpc).sextTo(xLen),
CSRs.dscratch0 -> reg_dscratch0.asUInt) ++
reg_dscratch1.map(r => CSRs.dscratch1 -> r)
val read_mnstatus = WireInit(0.U.asTypeOf(new MNStatus()))
read_mnstatus.mpp := reg_mnstatus.mpp
read_mnstatus.mpv := reg_mnstatus.mpv
read_mnstatus.mie := reg_rnmie
val nmi_csrs = if (!usingNMI) LinkedHashMap() else LinkedHashMap[Int,Bits](
CustomCSRs.mnscratch -> reg_mnscratch,
CustomCSRs.mnepc -> readEPC(reg_mnepc).sextTo(xLen),
CustomCSRs.mncause -> reg_mncause,
CustomCSRs.mnstatus -> read_mnstatus.asUInt)
val context_csrs = LinkedHashMap[Int,Bits]() ++
reg_mcontext.map(r => CSRs.mcontext -> r) ++
reg_scontext.map(r => CSRs.scontext -> r)
val read_fcsr = Cat(reg_frm, reg_fflags)
val fp_csrs = LinkedHashMap[Int,Bits]() ++
usingFPU.option(CSRs.fflags -> reg_fflags) ++
usingFPU.option(CSRs.frm -> reg_frm) ++
(usingFPU || usingVector).option(CSRs.fcsr -> read_fcsr)
val read_vcsr = Cat(reg_vxrm.getOrElse(0.U), reg_vxsat.getOrElse(0.U))
val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits](
CSRs.vxsat -> reg_vxsat.get,
CSRs.vxrm -> reg_vxrm.get,
CSRs.vcsr -> read_vcsr,
CSRs.vstart -> reg_vstart.get,
CSRs.vtype -> reg_vconfig.get.vtype.asUInt,
CSRs.vl -> reg_vconfig.get.vl,
CSRs.vlenb -> (vLen / 8).U)
read_mapping ++= debug_csrs
read_mapping ++= nmi_csrs
read_mapping ++= context_csrs
read_mapping ++= fp_csrs
read_mapping ++= vector_csrs
if (coreParams.haveBasicCounters) {
read_mapping += CSRs.mcountinhibit -> reg_mcountinhibit
read_mapping += CSRs.mcycle -> reg_cycle
read_mapping += CSRs.minstret -> reg_instret
for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, 0.U)
zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, 0.U)).zipWithIndex) {
read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN
read_mapping += (i + CSR.firstMHPC) -> c // mhpmcounterN
read_mapping += (i + CSR.firstHPC) -> c // hpmcounterN
if (xLen == 32) {
read_mapping += (i + CSR.firstMHPCH) -> (c >> 32) // mhpmcounterNh
read_mapping += (i + CSR.firstHPCH) -> (c >> 32) // hpmcounterNh
}
}
if (usingUser) {
read_mapping += CSRs.mcounteren -> read_mcounteren
}
read_mapping += CSRs.cycle -> reg_cycle
read_mapping += CSRs.instret -> reg_instret
if (xLen == 32) {
read_mapping += CSRs.mcycleh -> (reg_cycle >> 32)
read_mapping += CSRs.minstreth -> (reg_instret >> 32)
read_mapping += CSRs.cycleh -> (reg_cycle >> 32)
read_mapping += CSRs.instreth -> (reg_instret >> 32)
}
}
if (usingUser) {
read_mapping += CSRs.menvcfg -> reg_menvcfg.asUInt
if (xLen == 32)
read_mapping += CSRs.menvcfgh -> (reg_menvcfg.asUInt >> 32)
}
val sie_mask = {
val sgeip_mask = WireInit(0.U.asTypeOf(new MIP))
sgeip_mask.sgeip := true.B
read_mideleg & ~(hs_delegable_interrupts | sgeip_mask.asUInt)
}
if (usingSupervisor) {
val read_sie = reg_mie & sie_mask
val read_sip = read_mip & sie_mask
val read_sstatus = WireDefault(0.U.asTypeOf(new MStatus))
read_sstatus.sd := io.status.sd
read_sstatus.uxl := io.status.uxl
read_sstatus.sd_rv32 := io.status.sd_rv32
read_sstatus.mxr := io.status.mxr
read_sstatus.sum := io.status.sum
read_sstatus.xs := io.status.xs
read_sstatus.fs := io.status.fs
read_sstatus.vs := io.status.vs
read_sstatus.spp := io.status.spp
read_sstatus.spie := io.status.spie
read_sstatus.sie := io.status.sie
read_mapping += CSRs.sstatus -> (read_sstatus.asUInt)(xLen-1,0)
read_mapping += CSRs.sip -> read_sip.asUInt
read_mapping += CSRs.sie -> read_sie.asUInt
read_mapping += CSRs.sscratch -> reg_sscratch
read_mapping += CSRs.scause -> reg_scause
read_mapping += CSRs.stval -> reg_stval.sextTo(xLen)
read_mapping += CSRs.satp -> reg_satp.asUInt
read_mapping += CSRs.sepc -> readEPC(reg_sepc).sextTo(xLen)
read_mapping += CSRs.stvec -> read_stvec
read_mapping += CSRs.scounteren -> read_scounteren
read_mapping += CSRs.mideleg -> read_mideleg
read_mapping += CSRs.medeleg -> read_medeleg
read_mapping += CSRs.senvcfg -> reg_senvcfg.asUInt
}
val pmpCfgPerCSR = xLen / new PMPConfig().getWidth
def pmpCfgIndex(i: Int) = (xLen / 32) * (i / pmpCfgPerCSR)
if (reg_pmp.nonEmpty) {
require(reg_pmp.size <= CSR.maxPMPs)
val read_pmp = reg_pmp.padTo(CSR.maxPMPs, 0.U.asTypeOf(new PMP))
for (i <- 0 until read_pmp.size by pmpCfgPerCSR)
read_mapping += (CSRs.pmpcfg0 + pmpCfgIndex(i)) -> read_pmp.map(_.cfg).slice(i, i + pmpCfgPerCSR).asUInt
for ((pmp, i) <- read_pmp.zipWithIndex)
read_mapping += (CSRs.pmpaddr0 + i) -> pmp.readAddr
}
// implementation-defined CSRs
def generateCustomCSR(csr: CustomCSR, csr_io: CustomCSRIO) = {
require(csr.mask >= 0 && csr.mask.bitLength <= xLen)
require(!read_mapping.contains(csr.id))
val reg = csr.init.map(init => RegInit(init.U(xLen.W))).getOrElse(Reg(UInt(xLen.W)))
val read = io.rw.cmd =/= CSR.N && io.rw.addr === csr.id.U
csr_io.ren := read
when (read && csr_io.stall) { io.rw_stall := true.B }
read_mapping += csr.id -> reg
reg
}
val reg_custom = customCSRs.zip(io.customCSRs).map(t => generateCustomCSR(t._1, t._2))
val reg_rocc = roccCSRs.zip(io.roccCSRs).map(t => generateCustomCSR(t._1, t._2))
if (usingHypervisor) {
read_mapping += CSRs.mtinst -> read_mtinst
read_mapping += CSRs.mtval2 -> reg_mtval2
val read_hstatus = io.hstatus.asUInt.extract(xLen-1,0)
read_mapping += CSRs.hstatus -> read_hstatus
read_mapping += CSRs.hedeleg -> read_hedeleg
read_mapping += CSRs.hideleg -> read_hideleg
read_mapping += CSRs.hcounteren-> read_hcounteren
read_mapping += CSRs.hgatp -> reg_hgatp.asUInt
read_mapping += CSRs.hip -> read_hip
read_mapping += CSRs.hie -> read_hie
read_mapping += CSRs.hvip -> read_hvip
read_mapping += CSRs.hgeie -> 0.U
read_mapping += CSRs.hgeip -> 0.U
read_mapping += CSRs.htval -> reg_htval
read_mapping += CSRs.htinst -> read_htinst
read_mapping += CSRs.henvcfg -> reg_henvcfg.asUInt
if (xLen == 32)
read_mapping += CSRs.henvcfgh -> (reg_henvcfg.asUInt >> 32)
val read_vsie = (read_hie & read_hideleg) >> 1
val read_vsip = (read_hip & read_hideleg) >> 1
val read_vsepc = readEPC(reg_vsepc).sextTo(xLen)
val read_vstval = reg_vstval.sextTo(xLen)
val read_vsstatus = io.gstatus.asUInt.extract(xLen-1,0)
read_mapping += CSRs.vsstatus -> read_vsstatus
read_mapping += CSRs.vsip -> read_vsip
read_mapping += CSRs.vsie -> read_vsie
read_mapping += CSRs.vsscratch -> reg_vsscratch
read_mapping += CSRs.vscause -> reg_vscause
read_mapping += CSRs.vstval -> read_vstval
read_mapping += CSRs.vsatp -> reg_vsatp.asUInt
read_mapping += CSRs.vsepc -> read_vsepc
read_mapping += CSRs.vstvec -> read_vstvec
}
// mimpid, marchid, mvendorid, and mconfigptr are 0 unless overridden by customCSRs
Seq(CSRs.mimpid, CSRs.marchid, CSRs.mvendorid, CSRs.mconfigptr).foreach(id => read_mapping.getOrElseUpdate(id, 0.U))
val decoded_addr = {
val addr = Cat(io.status.v, io.rw.addr)
val pats = for (((k, _), i) <- read_mapping.zipWithIndex)
yield (BitPat(k.U), (0 until read_mapping.size).map(j => BitPat((i == j).B)))
val decoded = DecodeLogic(addr, Seq.fill(read_mapping.size)(X), pats)
val unvirtualized_mapping = (for (((k, _), v) <- read_mapping zip decoded) yield k -> v.asBool).toMap
for ((k, v) <- unvirtualized_mapping) yield k -> {
val alt: Option[Bool] = CSR.mode(k) match {
// hcontext was assigned an unfortunate address; it lives where a
// hypothetical vscontext will live. Exclude them from the S/VS remapping.
// (on separate lines so scala-lint doesnt do something stupid)
case _ if k == CSRs.scontext => None
case _ if k == CSRs.hcontext => None
// When V=1, if a corresponding VS CSR exists, access it instead...
case PRV.H => unvirtualized_mapping.lift(k - (1 << CSR.modeLSB))
// ...and don't access the original S-mode version.
case PRV.S => unvirtualized_mapping.contains(k + (1 << CSR.modeLSB)).option(false.B)
case _ => None
}
alt.map(Mux(reg_mstatus.v, _, v)).getOrElse(v)
}
}
val wdata = readModifyWriteCSR(io.rw.cmd, io.rw.rdata, io.rw.wdata)
val system_insn = io.rw.cmd === CSR.I
val hlsv = Seq(HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HLV_WU, HLV_D, HSV_B, HSV_H, HSV_W, HSV_D, HLVX_HU, HLVX_WU)
val decode_table = Seq( ECALL-> List(Y,N,N,N,N,N,N,N,N),
EBREAK-> List(N,Y,N,N,N,N,N,N,N),
MRET-> List(N,N,Y,N,N,N,N,N,N),
CEASE-> List(N,N,N,Y,N,N,N,N,N),
WFI-> List(N,N,N,N,Y,N,N,N,N)) ++
usingDebug.option( DRET-> List(N,N,Y,N,N,N,N,N,N)) ++
usingNMI.option( MNRET-> List(N,N,Y,N,N,N,N,N,N)) ++
coreParams.haveCFlush.option(CFLUSH_D_L1-> List(N,N,N,N,N,N,N,N,N)) ++
usingSupervisor.option( SRET-> List(N,N,Y,N,N,N,N,N,N)) ++
usingVM.option( SFENCE_VMA-> List(N,N,N,N,N,Y,N,N,N)) ++
usingHypervisor.option( HFENCE_VVMA-> List(N,N,N,N,N,N,Y,N,N)) ++
usingHypervisor.option( HFENCE_GVMA-> List(N,N,N,N,N,N,N,Y,N)) ++
(if (usingHypervisor) hlsv.map(_-> List(N,N,N,N,N,N,N,N,Y)) else Seq())
val insn_call :: insn_break :: insn_ret :: insn_cease :: insn_wfi :: _ :: _ :: _ :: _ :: Nil = {
val insn = ECALL.value.U | (io.rw.addr << 20)
DecodeLogic(insn, decode_table(0)._2.map(x=>X), decode_table).map(system_insn && _.asBool)
}
for (io_dec <- io.decode) {
val addr = io_dec.inst(31, 20)
def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map { case(k: Int, _: Bits) => addr === k.U }.reduce(_||_)
def decodeFast(s: Seq[Int]): Bool = DecodeLogic(addr, s.map(_.U), (read_mapping -- s).keys.toList.map(_.U))
val _ :: is_break :: is_ret :: _ :: is_wfi :: is_sfence :: is_hfence_vvma :: is_hfence_gvma :: is_hlsv :: Nil =
DecodeLogic(io_dec.inst, decode_table(0)._2.map(x=>X), decode_table).map(_.asBool)
val is_counter = (addr.inRange(CSR.firstCtr.U, (CSR.firstCtr + CSR.nCtr).U) || addr.inRange(CSR.firstCtrH.U, (CSR.firstCtrH + CSR.nCtr).U))
val allow_wfi = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !reg_mstatus.tw && (!reg_mstatus.v || !reg_hstatus.vtw)
val allow_sfence_vma = (!usingVM).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm)
val allow_hfence_vvma = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U)
val allow_hlsv = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U || reg_hstatus.hu)
val allow_sret = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr)
val counter_addr = addr(log2Ceil(read_mcounteren.getWidth)-1, 0)
val allow_counter = (reg_mstatus.prv > PRV.S.U || read_mcounteren(counter_addr)) &&
(!usingSupervisor.B || reg_mstatus.prv >= PRV.S.U || read_scounteren(counter_addr)) &&
(!usingHypervisor.B || !reg_mstatus.v || read_hcounteren(counter_addr))
io_dec.fp_illegal := io.status.fs === 0.U || reg_mstatus.v && reg_vsstatus.fs === 0.U || !reg_misa('f'-'a')
io_dec.vector_illegal := io.status.vs === 0.U || reg_mstatus.v && reg_vsstatus.vs === 0.U || !reg_misa('v'-'a')
io_dec.fp_csr := decodeFast(fp_csrs.keys.toList)
io_dec.vector_csr := decodeFast(vector_csrs.keys.toList)
io_dec.rocc_illegal := io.status.xs === 0.U || reg_mstatus.v && reg_vsstatus.xs === 0.U || !reg_misa('x'-'a')
val csr_addr_legal = reg_mstatus.prv >= CSR.mode(addr) ||
usingHypervisor.B && !reg_mstatus.v && reg_mstatus.prv === PRV.S.U && CSR.mode(addr) === PRV.H.U
val csr_exists = decodeAny(read_mapping)
io_dec.read_illegal := !csr_addr_legal ||
!csr_exists ||
((addr === CSRs.satp.U || addr === CSRs.hgatp.U) && !allow_sfence_vma) ||
is_counter && !allow_counter ||
decodeFast(debug_csrs.keys.toList) && !reg_debug ||
decodeFast(vector_csrs.keys.toList) && io_dec.vector_illegal ||
io_dec.fp_csr && io_dec.fp_illegal
io_dec.write_illegal := addr(11,10).andR
io_dec.write_flush := {
val addr_m = addr | (PRV.M.U << CSR.modeLSB)
!(addr_m >= CSRs.mscratch.U && addr_m <= CSRs.mtval.U)
}
io_dec.system_illegal := !csr_addr_legal && !is_hlsv ||
is_wfi && !allow_wfi ||
is_ret && !allow_sret ||
is_ret && addr(10) && addr(7) && !reg_debug ||
(is_sfence || is_hfence_gvma) && !allow_sfence_vma ||
is_hfence_vvma && !allow_hfence_vvma ||
is_hlsv && !allow_hlsv
io_dec.virtual_access_illegal := reg_mstatus.v && csr_exists && (
CSR.mode(addr) === PRV.H.U ||
is_counter && read_mcounteren(counter_addr) && (!read_hcounteren(counter_addr) || !reg_mstatus.prv(0) && !read_scounteren(counter_addr)) ||
CSR.mode(addr) === PRV.S.U && !reg_mstatus.prv(0) ||
addr === CSRs.satp.U && reg_mstatus.prv(0) && reg_hstatus.vtvm)
io_dec.virtual_system_illegal := reg_mstatus.v && (
is_hfence_vvma ||
is_hfence_gvma ||
is_hlsv ||
is_wfi && (!reg_mstatus.prv(0) || !reg_mstatus.tw && reg_hstatus.vtw) ||
is_ret && CSR.mode(addr) === PRV.S.U && (!reg_mstatus.prv(0) || reg_hstatus.vtsr) ||
is_sfence && (!reg_mstatus.prv(0) || reg_hstatus.vtvm))
}
val cause =
Mux(insn_call, Causes.user_ecall.U + Mux(reg_mstatus.prv(0) && reg_mstatus.v, PRV.H.U, reg_mstatus.prv),
Mux[UInt](insn_break, Causes.breakpoint.U, io.cause))
val cause_lsbs = cause(log2Ceil(1 + CSR.busErrorIntCause)-1, 0)
val cause_deleg_lsbs = cause(log2Ceil(xLen)-1,0)
val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause.U
val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause.U
val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv)
val trapToDebug = usingDebug.B && (reg_singleStepped || causeIsDebugInt || causeIsDebugTrigger || causeIsDebugBreak || reg_debug)
val debugEntry = p(DebugModuleKey).map(_.debugEntry).getOrElse(BigInt(0x800))
val debugException = p(DebugModuleKey).map(_.debugException).getOrElse(BigInt(0x808))
val debugTVec = Mux(reg_debug, Mux(insn_break, debugEntry.U, debugException.U), debugEntry.U)
val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_deleg_lsbs), read_medeleg(cause_deleg_lsbs))
val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_deleg_lsbs), read_hedeleg(cause_deleg_lsbs))
def mtvecBaseAlign = 2
def mtvecInterruptAlign = {
require(reg_mip.getWidth <= xLen)
log2Ceil(xLen)
}
val notDebugTVec = {
val base = Mux(delegate, Mux(delegateVS, read_vstvec, read_stvec), read_mtvec)
val interruptOffset = cause(mtvecInterruptAlign-1, 0) << mtvecBaseAlign
val interruptVec = Cat(base >> (mtvecInterruptAlign + mtvecBaseAlign), interruptOffset)
val doVector = base(0) && cause(cause.getWidth-1) && (cause_lsbs >> mtvecInterruptAlign) === 0.U
Mux(doVector, interruptVec, base >> mtvecBaseAlign << mtvecBaseAlign)
}
val causeIsRnmiInt = cause(xLen-1) && cause(xLen-2) && (cause_lsbs === CSR.rnmiIntCause.U || cause_lsbs === CSR.rnmiBEUCause.U)
val causeIsRnmiBEU = cause(xLen-1) && cause(xLen-2) && cause_lsbs === CSR.rnmiBEUCause.U
val causeIsNmi = causeIsRnmiInt
val nmiTVecInt = io.interrupts.nmi.map(nmi => nmi.rnmi_interrupt_vector).getOrElse(0.U)
val nmiTVecXcpt = io.interrupts.nmi.map(nmi => nmi.rnmi_exception_vector).getOrElse(0.U)
val trapToNmiInt = usingNMI.B && causeIsNmi
val trapToNmiXcpt = usingNMI.B && !nmie
val trapToNmi = trapToNmiInt || trapToNmiXcpt
val nmiTVec = (Mux(causeIsNmi, nmiTVecInt, nmiTVecXcpt)>>1)<<1
val tvec = Mux(trapToDebug, debugTVec, Mux(trapToNmi, nmiTVec, notDebugTVec))
io.evec := tvec
io.ptbr := reg_satp
io.hgatp := reg_hgatp
io.vsatp := reg_vsatp
io.eret := insn_call || insn_break || insn_ret
io.singleStep := reg_dcsr.step && !reg_debug
io.status := reg_mstatus
io.status.sd := io.status.fs.andR || io.status.xs.andR || io.status.vs.andR
io.status.debug := reg_debug
io.status.isa := reg_misa
io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U
io.status.sxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U
io.status.dprv := Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpp, reg_mstatus.prv)
io.status.dv := reg_mstatus.v || Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpv, false.B)
io.status.sd_rv32 := (xLen == 32).B && io.status.sd
io.status.mpv := reg_mstatus.mpv
io.status.gva := reg_mstatus.gva
io.hstatus := reg_hstatus
io.hstatus.vsxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U
io.gstatus := reg_vsstatus
io.gstatus.sd := io.gstatus.fs.andR || io.gstatus.xs.andR || io.gstatus.vs.andR
io.gstatus.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U
io.gstatus.sd_rv32 := (xLen == 32).B && io.gstatus.sd
val exception = insn_call || insn_break || io.exception
assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, "these conditions must be mutually exclusive")
when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true.B }
when (pending_interrupts.orR || io.interrupts.debug || exception) { reg_wfi := false.B }
io.interrupts.nmi.map(nmi => when (nmi.rnmi) { reg_wfi := false.B } )
when (io.retire(0) || exception) { reg_singleStepped := true.B }
when (!io.singleStep) { reg_singleStepped := false.B }
assert(!io.singleStep || io.retire <= 1.U)
assert(!reg_singleStepped || io.retire === 0.U)
val epc = formEPC(io.pc)
val tval = Mux(insn_break, epc, io.tval)
when (exception) {
when (trapToDebug) {
when (!reg_debug) {
reg_mstatus.v := false.B
reg_debug := true.B
reg_dpc := epc
reg_dcsr.cause := Mux(reg_singleStepped, 4.U, Mux(causeIsDebugInt, 3.U, Mux[UInt](causeIsDebugTrigger, 2.U, 1.U)))
reg_dcsr.prv := trimPrivilege(reg_mstatus.prv)
reg_dcsr.v := reg_mstatus.v
new_prv := PRV.M.U
}
}.elsewhen (trapToNmiInt) {
when (reg_rnmie) {
reg_mstatus.v := false.B
reg_mnstatus.mpv := reg_mstatus.v
reg_rnmie := false.B
reg_mnepc := epc
reg_mncause := (BigInt(1) << (xLen-1)).U | Mux(causeIsRnmiBEU, 3.U, 2.U)
reg_mnstatus.mpp := trimPrivilege(reg_mstatus.prv)
new_prv := PRV.M.U
}
}.elsewhen (delegateVS && nmie) {
reg_mstatus.v := true.B
reg_vsstatus.spp := reg_mstatus.prv
reg_vsepc := epc
reg_vscause := Mux(cause(xLen-1), Cat(cause(xLen-1, 2), 1.U(2.W)), cause)
reg_vstval := tval
reg_vsstatus.spie := reg_vsstatus.sie
reg_vsstatus.sie := false.B
new_prv := PRV.S.U
}.elsewhen (delegate && nmie) {
reg_mstatus.v := false.B
reg_hstatus.spvp := Mux(reg_mstatus.v, reg_mstatus.prv(0),reg_hstatus.spvp)
reg_hstatus.gva := io.gva
reg_hstatus.spv := reg_mstatus.v
reg_sepc := epc
reg_scause := cause
reg_stval := tval
reg_htval := io.htval
reg_htinst_read_pseudo := io.mhtinst_read_pseudo
reg_mstatus.spie := reg_mstatus.sie
reg_mstatus.spp := reg_mstatus.prv
reg_mstatus.sie := false.B
new_prv := PRV.S.U
}.otherwise {
reg_mstatus.v := false.B
reg_mstatus.mpv := reg_mstatus.v
reg_mstatus.gva := io.gva
reg_mepc := epc
reg_mcause := cause
reg_mtval := tval
reg_mtval2 := io.htval
reg_mtinst_read_pseudo := io.mhtinst_read_pseudo
reg_mstatus.mpie := reg_mstatus.mie
reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv)
reg_mstatus.mie := false.B
new_prv := PRV.M.U
}
}
for (i <- 0 until supported_interrupts.getWidth) {
val en = exception && (supported_interrupts & (BigInt(1) << i).U) =/= 0.U && cause === (BigInt(1) << (xLen - 1)).U + i.U
val delegable = (delegable_interrupts & (BigInt(1) << i).U) =/= 0.U
property.cover(en && !delegate, s"INTERRUPT_M_$i")
property.cover(en && delegable && delegate, s"INTERRUPT_S_$i")
}
for (i <- 0 until xLen) {
val supported_exceptions: BigInt = 0x8fe |
(if (usingCompressed && !coreParams.misaWritable) 0 else 1) |
(if (usingUser) 0x100 else 0) |
(if (usingSupervisor) 0x200 else 0) |
(if (usingVM) 0xb000 else 0)
if (((supported_exceptions >> i) & 1) != 0) {
val en = exception && cause === i.U
val delegable = (delegable_exceptions & (BigInt(1) << i).U) =/= 0.U
property.cover(en && !delegate, s"EXCEPTION_M_$i")
property.cover(en && delegable && delegate, s"EXCEPTION_S_$i")
}
}
when (insn_ret) {
val ret_prv = WireInit(UInt(), DontCare)
when (usingSupervisor.B && !io.rw.addr(9)) {
when (!reg_mstatus.v) {
reg_mstatus.sie := reg_mstatus.spie
reg_mstatus.spie := true.B
reg_mstatus.spp := PRV.U.U
ret_prv := reg_mstatus.spp
reg_mstatus.v := usingHypervisor.B && reg_hstatus.spv
io.evec := readEPC(reg_sepc)
reg_hstatus.spv := false.B
}.otherwise {
reg_vsstatus.sie := reg_vsstatus.spie
reg_vsstatus.spie := true.B
reg_vsstatus.spp := PRV.U.U
ret_prv := reg_vsstatus.spp
reg_mstatus.v := usingHypervisor.B
io.evec := readEPC(reg_vsepc)
}
}.elsewhen (usingDebug.B && io.rw.addr(10) && io.rw.addr(7)) {
ret_prv := reg_dcsr.prv
reg_mstatus.v := usingHypervisor.B && reg_dcsr.v && reg_dcsr.prv <= PRV.S.U
reg_debug := false.B
io.evec := readEPC(reg_dpc)
}.elsewhen (usingNMI.B && io.rw.addr(10) && !io.rw.addr(7)) {
ret_prv := reg_mnstatus.mpp
reg_mstatus.v := usingHypervisor.B && reg_mnstatus.mpv && reg_mnstatus.mpp <= PRV.S.U
reg_rnmie := true.B
io.evec := readEPC(reg_mnepc)
}.otherwise {
reg_mstatus.mie := reg_mstatus.mpie
reg_mstatus.mpie := true.B
reg_mstatus.mpp := legalizePrivilege(PRV.U.U)
reg_mstatus.mpv := false.B
ret_prv := reg_mstatus.mpp
reg_mstatus.v := usingHypervisor.B && reg_mstatus.mpv && reg_mstatus.mpp <= PRV.S.U
io.evec := readEPC(reg_mepc)
}
new_prv := ret_prv
when (usingUser.B && ret_prv <= PRV.S.U) {
reg_mstatus.mprv := false.B
}
}
io.time := reg_cycle
io.csr_stall := reg_wfi || io.status.cease
io.status.cease := RegEnable(true.B, false.B, insn_cease)
io.status.wfi := reg_wfi
for ((io, reg) <- io.customCSRs zip reg_custom) {
io.wen := false.B
io.wdata := wdata
io.value := reg
}
for ((io, reg) <- io.roccCSRs zip reg_rocc) {
io.wen := false.B
io.wdata := wdata
io.value := reg
}
io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v)
// cover access to register
val coverable_counters = read_mapping.filterNot { case (k, _) =>
k >= CSR.firstHPC + nPerfCounters && k < CSR.firstHPC + CSR.nHPM
}
coverable_counters.foreach( {case (k, v) => {
when (!k.U(11,10).andR) { // Cover points for RW CSR registers
property.cover(io.rw.cmd.isOneOf(CSR.W, CSR.S, CSR.C) && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field")
} .otherwise { // Cover points for RO CSR registers
property.cover(io.rw.cmd===CSR.R && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field")
}
}})
val set_vs_dirty = WireDefault(io.vector.map(_.set_vs_dirty).getOrElse(false.B))
io.vector.foreach { vio =>
when (set_vs_dirty) {
assert(reg_mstatus.vs > 0.U)
when (reg_mstatus.v) { reg_vsstatus.vs := 3.U }
reg_mstatus.vs := 3.U
}
}
val set_fs_dirty = WireDefault(io.set_fs_dirty.getOrElse(false.B))
if (coreParams.haveFSDirty) {
when (set_fs_dirty) {
assert(reg_mstatus.fs > 0.U)
when (reg_mstatus.v) { reg_vsstatus.fs := 3.U }
reg_mstatus.fs := 3.U
}
}
io.fcsr_rm := reg_frm
when (io.fcsr_flags.valid) {
reg_fflags := reg_fflags | io.fcsr_flags.bits
set_fs_dirty := true.B
}
io.vector.foreach { vio =>
when (vio.set_vxsat) {
reg_vxsat.get := true.B
set_vs_dirty := true.B
}
}
val csr_wen = io.rw.cmd.isOneOf(CSR.S, CSR.C, CSR.W) && !io.rw_stall
io.csrw_counter := Mux(coreParams.haveBasicCounters.B && csr_wen && (io.rw.addr.inRange(CSRs.mcycle.U, (CSRs.mcycle + CSR.nCtr).U) || io.rw.addr.inRange(CSRs.mcycleh.U, (CSRs.mcycleh + CSR.nCtr).U)), UIntToOH(io.rw.addr(log2Ceil(CSR.nCtr+nPerfCounters)-1, 0)), 0.U)
when (csr_wen) {
val scause_mask = ((BigInt(1) << (xLen-1)) + 31).U /* only implement 5 LSBs and MSB */
val satp_valid_modes = 0 +: (minPgLevels to pgLevels).map(new PTBR().pgLevelsToMode(_))
when (decoded_addr(CSRs.mstatus)) {
val new_mstatus = wdata.asTypeOf(new MStatus())
reg_mstatus.mie := new_mstatus.mie
reg_mstatus.mpie := new_mstatus.mpie
if (usingUser) {
reg_mstatus.mprv := new_mstatus.mprv
reg_mstatus.mpp := legalizePrivilege(new_mstatus.mpp)
if (usingSupervisor) {
reg_mstatus.spp := new_mstatus.spp
reg_mstatus.spie := new_mstatus.spie
reg_mstatus.sie := new_mstatus.sie
reg_mstatus.tw := new_mstatus.tw
reg_mstatus.tsr := new_mstatus.tsr
}
if (usingVM) {
reg_mstatus.mxr := new_mstatus.mxr
reg_mstatus.sum := new_mstatus.sum
reg_mstatus.tvm := new_mstatus.tvm
}
if (usingHypervisor) {
reg_mstatus.mpv := new_mstatus.mpv
reg_mstatus.gva := new_mstatus.gva
}
}
if (usingSupervisor || usingFPU) reg_mstatus.fs := formFS(new_mstatus.fs)
reg_mstatus.vs := formVS(new_mstatus.vs)
}
when (decoded_addr(CSRs.misa)) {
val mask = isaStringToMask(isaMaskString).U(xLen.W)
val f = wdata('f' - 'a')
// suppress write if it would cause the next fetch to be misaligned
when (!usingCompressed.B || !io.pc(1) || wdata('c' - 'a')) {
if (coreParams.misaWritable)
reg_misa := ~(~wdata | (!f << ('d' - 'a'))) & mask | reg_misa & ~mask
}
}
when (decoded_addr(CSRs.mip)) {
// MIP should be modified based on the value in reg_mip, not the value
// in read_mip, since read_mip.seip is the OR of reg_mip.seip and
// io.interrupts.seip. We don't want the value on the PLIC line to
// inadvertently be OR'd into read_mip.seip.
val new_mip = readModifyWriteCSR(io.rw.cmd, reg_mip.asUInt, io.rw.wdata).asTypeOf(new MIP)
if (usingSupervisor) {
reg_mip.ssip := new_mip.ssip
reg_mip.stip := new_mip.stip
reg_mip.seip := new_mip.seip
}
if (usingHypervisor) {
reg_mip.vssip := new_mip.vssip
}
}
when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts }
when (decoded_addr(CSRs.mepc)) { reg_mepc := formEPC(wdata) }
when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata }
if (mtvecWritable)
when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata }
when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & ((BigInt(1) << (xLen-1)) + (BigInt(1) << whichInterrupt.getWidth) - 1).U }
when (decoded_addr(CSRs.mtval)) { reg_mtval := wdata }
if (usingNMI) {
val new_mnstatus = wdata.asTypeOf(new MNStatus())
when (decoded_addr(CustomCSRs.mnscratch)) { reg_mnscratch := wdata }
when (decoded_addr(CustomCSRs.mnepc)) { reg_mnepc := formEPC(wdata) }
when (decoded_addr(CustomCSRs.mncause)) { reg_mncause := wdata & ((BigInt(1) << (xLen-1)) + BigInt(3)).U }
when (decoded_addr(CustomCSRs.mnstatus)) {
reg_mnstatus.mpp := legalizePrivilege(new_mnstatus.mpp)
reg_mnstatus.mpv := usingHypervisor.B && new_mnstatus.mpv
reg_rnmie := reg_rnmie | new_mnstatus.mie // mnie bit settable but not clearable from software
}
}
for (((e, c), i) <- (reg_hpmevent zip reg_hpmcounter).zipWithIndex) {
writeCounter(i + CSR.firstMHPC, c, wdata)
when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) }
}
if (coreParams.haveBasicCounters) {
when (decoded_addr(CSRs.mcountinhibit)) { reg_mcountinhibit := wdata & ~2.U(xLen.W) } // mcountinhibit bit [1] is tied zero
writeCounter(CSRs.mcycle, reg_cycle, wdata)
writeCounter(CSRs.minstret, reg_instret, wdata)
}
if (usingFPU) {
when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true.B; reg_fflags := wdata }
when (decoded_addr(CSRs.frm)) { set_fs_dirty := true.B; reg_frm := wdata }
when (decoded_addr(CSRs.fcsr)) {
set_fs_dirty := true.B
reg_fflags := wdata
reg_frm := wdata >> reg_fflags.getWidth
}
}
if (usingDebug) {
when (decoded_addr(CSRs.dcsr)) {
val new_dcsr = wdata.asTypeOf(new DCSR())
reg_dcsr.step := new_dcsr.step
reg_dcsr.ebreakm := new_dcsr.ebreakm
if (usingSupervisor) reg_dcsr.ebreaks := new_dcsr.ebreaks
if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku
if (usingUser) reg_dcsr.prv := legalizePrivilege(new_dcsr.prv)
if (usingHypervisor) reg_dcsr.v := new_dcsr.v
}
when (decoded_addr(CSRs.dpc)) { reg_dpc := formEPC(wdata) }
when (decoded_addr(CSRs.dscratch0)) { reg_dscratch0 := wdata }
reg_dscratch1.foreach { r =>
when (decoded_addr(CSRs.dscratch1)) { r := wdata }
}
}
if (usingSupervisor) {
when (decoded_addr(CSRs.sstatus)) {
val new_sstatus = wdata.asTypeOf(new MStatus())
reg_mstatus.sie := new_sstatus.sie
reg_mstatus.spie := new_sstatus.spie
reg_mstatus.spp := new_sstatus.spp
reg_mstatus.fs := formFS(new_sstatus.fs)
reg_mstatus.vs := formVS(new_sstatus.vs)
if (usingVM) {
reg_mstatus.mxr := new_sstatus.mxr
reg_mstatus.sum := new_sstatus.sum
}
}
when (decoded_addr(CSRs.sip)) {
val new_sip = ((read_mip & ~read_mideleg) | (wdata & read_mideleg)).asTypeOf(new MIP())
reg_mip.ssip := new_sip.ssip
}
when (decoded_addr(CSRs.satp)) {
if (usingVM) {
val new_satp = wdata.asTypeOf(new PTBR())
when (new_satp.mode.isOneOf(satp_valid_modes.map(_.U))) {
reg_satp.mode := new_satp.mode & satp_valid_modes.reduce(_|_).U
reg_satp.ppn := new_satp.ppn(ppnBits-1,0)
if (asIdBits > 0) reg_satp.asid := new_satp.asid(asIdBits-1,0)
}
}
}
when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~sie_mask) | (wdata & sie_mask) }
when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata }
when (decoded_addr(CSRs.sepc)) { reg_sepc := formEPC(wdata) }
when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata }
when (decoded_addr(CSRs.scause)) { reg_scause := wdata & scause_mask }
when (decoded_addr(CSRs.stval)) { reg_stval := wdata }
when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata }
when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata }
when (decoded_addr(CSRs.scounteren)) { reg_scounteren := wdata }
when (decoded_addr(CSRs.senvcfg)) { reg_senvcfg.write(wdata) }
}
if (usingHypervisor) {
when (decoded_addr(CSRs.hstatus)) {
val new_hstatus = wdata.asTypeOf(new HStatus())
reg_hstatus.gva := new_hstatus.gva
reg_hstatus.spv := new_hstatus.spv
reg_hstatus.spvp := new_hstatus.spvp
reg_hstatus.hu := new_hstatus.hu
reg_hstatus.vtvm := new_hstatus.vtvm
reg_hstatus.vtw := new_hstatus.vtw
reg_hstatus.vtsr := new_hstatus.vtsr
reg_hstatus.vsxl := new_hstatus.vsxl
}
when (decoded_addr(CSRs.hideleg)) { reg_hideleg := wdata }
when (decoded_addr(CSRs.hedeleg)) { reg_hedeleg := wdata }
when (decoded_addr(CSRs.hgatp)) {
val new_hgatp = wdata.asTypeOf(new PTBR())
val valid_modes = 0 +: (minPgLevels to pgLevels).map(new_hgatp.pgLevelsToMode(_))
when (new_hgatp.mode.isOneOf(valid_modes.map(_.U))) {
reg_hgatp.mode := new_hgatp.mode & valid_modes.reduce(_|_).U
}
reg_hgatp.ppn := Cat(new_hgatp.ppn(ppnBits-1,2), 0.U(2.W))
if (vmIdBits > 0) reg_hgatp.asid := new_hgatp.asid(vmIdBits-1,0)
}
when (decoded_addr(CSRs.hip)) {
val new_hip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP())
reg_mip.vssip := new_hip.vssip
}
when (decoded_addr(CSRs.hie)) { reg_mie := (reg_mie & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts) }
when (decoded_addr(CSRs.hvip)) {
val new_sip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP())
reg_mip.vssip := new_sip.vssip
reg_mip.vstip := new_sip.vstip
reg_mip.vseip := new_sip.vseip
}
when (decoded_addr(CSRs.hcounteren)) { reg_hcounteren := wdata }
when (decoded_addr(CSRs.htval)) { reg_htval := wdata }
when (decoded_addr(CSRs.mtval2)) { reg_mtval2 := wdata }
val write_mhtinst_read_pseudo = wdata(13) && (xLen == 32).option(true.B).getOrElse(wdata(12))
when(decoded_addr(CSRs.mtinst)) { reg_mtinst_read_pseudo := write_mhtinst_read_pseudo }
when(decoded_addr(CSRs.htinst)) { reg_htinst_read_pseudo := write_mhtinst_read_pseudo }
when (decoded_addr(CSRs.vsstatus)) {
val new_vsstatus = wdata.asTypeOf(new MStatus())
reg_vsstatus.sie := new_vsstatus.sie
reg_vsstatus.spie := new_vsstatus.spie
reg_vsstatus.spp := new_vsstatus.spp
reg_vsstatus.mxr := new_vsstatus.mxr
reg_vsstatus.sum := new_vsstatus.sum
reg_vsstatus.fs := formFS(new_vsstatus.fs)
reg_vsstatus.vs := formVS(new_vsstatus.vs)
}
when (decoded_addr(CSRs.vsip)) {
val new_vsip = ((read_hip & ~read_hideleg) | ((wdata << 1) & read_hideleg)).asTypeOf(new MIP())
reg_mip.vssip := new_vsip.vssip
}
when (decoded_addr(CSRs.vsatp)) {
val new_vsatp = wdata.asTypeOf(new PTBR())
val mode_ok = new_vsatp.mode.isOneOf(satp_valid_modes.map(_.U))
when (mode_ok) {
reg_vsatp.mode := new_vsatp.mode & satp_valid_modes.reduce(_|_).U
}
when (mode_ok || !reg_mstatus.v) {
reg_vsatp.ppn := new_vsatp.ppn(vpnBits.min(new_vsatp.ppn.getWidth)-1,0)
if (asIdBits > 0) reg_vsatp.asid := new_vsatp.asid(asIdBits-1,0)
}
}
when (decoded_addr(CSRs.vsie)) { reg_mie := (reg_mie & ~read_hideleg) | ((wdata << 1) & read_hideleg) }
when (decoded_addr(CSRs.vsscratch)) { reg_vsscratch := wdata }
when (decoded_addr(CSRs.vsepc)) { reg_vsepc := formEPC(wdata) }
when (decoded_addr(CSRs.vstvec)) { reg_vstvec := wdata }
when (decoded_addr(CSRs.vscause)) { reg_vscause := wdata & scause_mask }
when (decoded_addr(CSRs.vstval)) { reg_vstval := wdata }
when (decoded_addr(CSRs.henvcfg)) { reg_henvcfg.write(wdata) }
}
if (usingUser) {
when (decoded_addr(CSRs.mcounteren)) { reg_mcounteren := wdata }
when (decoded_addr(CSRs.menvcfg)) { reg_menvcfg.write(wdata) }
}
if (nBreakpoints > 0) {
when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata }
for ((bp, i) <- reg_bp.zipWithIndex) {
when (i.U === reg_tselect && (!bp.control.dmode || reg_debug)) {
when (decoded_addr(CSRs.tdata2)) { bp.address := wdata }
when (decoded_addr(CSRs.tdata3)) {
if (coreParams.mcontextWidth > 0) {
bp.textra.mselect := wdata(bp.textra.mselectPos)
bp.textra.mvalue := wdata >> bp.textra.mvaluePos
}
if (coreParams.scontextWidth > 0) {
bp.textra.sselect := wdata(bp.textra.sselectPos)
bp.textra.svalue := wdata >> bp.textra.svaluePos
}
}
when (decoded_addr(CSRs.tdata1)) {
bp.control := wdata.asTypeOf(bp.control)
val prevChain = if (i == 0) false.B else reg_bp(i-1).control.chain
val prevDMode = if (i == 0) false.B else reg_bp(i-1).control.dmode
val nextChain = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.chain
val nextDMode = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.dmode
val newBPC = readModifyWriteCSR(io.rw.cmd, bp.control.asUInt, io.rw.wdata).asTypeOf(bp.control)
val dMode = newBPC.dmode && reg_debug && (prevDMode || !prevChain)
bp.control.dmode := dMode
when (dMode || (newBPC.action > 1.U)) { bp.control.action := newBPC.action }.otherwise { bp.control.action := 0.U }
bp.control.chain := newBPC.chain && !(prevChain || nextChain) && (dMode || !nextDMode)
}
}
}
}
reg_mcontext.foreach { r => when (decoded_addr(CSRs.mcontext)) { r := wdata }}
reg_scontext.foreach { r => when (decoded_addr(CSRs.scontext)) { r := wdata }}
if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)).zipWithIndex) {
require(xLen % pmp.cfg.getWidth == 0)
when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.cfgLocked) {
val newCfg = (wdata >> ((i * pmp.cfg.getWidth) % xLen)).asTypeOf(new PMPConfig())
pmp.cfg := newCfg
// disallow unreadable but writable PMPs
pmp.cfg.w := newCfg.w && newCfg.r
// can't select a=NA4 with coarse-grained PMPs
if (pmpGranularity.log2 > PMP.lgAlign)
pmp.cfg.a := Cat(newCfg.a(1), newCfg.a.orR)
}
when (decoded_addr(CSRs.pmpaddr0 + i) && !pmp.addrLocked(next)) {
pmp.addr := wdata
}
}
def writeCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = {
val mask = csr.mask.U(xLen.W)
when (decoded_addr(csr.id)) {
reg := (wdata & mask) | (reg & ~mask)
io.wen := true.B
}
}
for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) {
writeCustomCSR(io, csr, reg)
}
for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) {
writeCustomCSR(io, csr, reg)
}
if (usingVector) {
when (decoded_addr(CSRs.vstart)) { set_vs_dirty := true.B; reg_vstart.get := wdata }
when (decoded_addr(CSRs.vxrm)) { set_vs_dirty := true.B; reg_vxrm.get := wdata }
when (decoded_addr(CSRs.vxsat)) { set_vs_dirty := true.B; reg_vxsat.get := wdata }
when (decoded_addr(CSRs.vcsr)) {
set_vs_dirty := true.B
reg_vxsat.get := wdata
reg_vxrm.get := wdata >> 1
}
}
}
def setCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = {
val mask = csr.mask.U(xLen.W)
when (io.set) {
reg := (io.sdata & mask) | (reg & ~mask)
}
}
for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) {
setCustomCSR(io, csr, reg)
}
for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) {
setCustomCSR(io, csr, reg)
}
io.vector.map { vio =>
when (vio.set_vconfig.valid) {
// user of CSRFile is responsible for set_vs_dirty in this case
assert(vio.set_vconfig.bits.vl <= vio.set_vconfig.bits.vtype.vlMax)
reg_vconfig.get := vio.set_vconfig.bits
}
when (vio.set_vstart.valid) {
set_vs_dirty := true.B
reg_vstart.get := vio.set_vstart.bits
}
vio.vstart := reg_vstart.get
vio.vconfig := reg_vconfig.get
vio.vxrm := reg_vxrm.get
when (reset.asBool) {
reg_vconfig.get.vl := 0.U
reg_vconfig.get.vtype := 0.U.asTypeOf(new VType)
reg_vconfig.get.vtype.vill := true.B
}
}
when(reset.asBool) {
reg_satp.mode := 0.U
reg_vsatp.mode := 0.U
reg_hgatp.mode := 0.U
}
if (!usingVM) {
reg_satp.mode := 0.U
reg_satp.ppn := 0.U
reg_satp.asid := 0.U
}
if (!usingHypervisor) {
reg_vsatp.mode := 0.U
reg_vsatp.ppn := 0.U
reg_vsatp.asid := 0.U
reg_hgatp.mode := 0.U
reg_hgatp.ppn := 0.U
reg_hgatp.asid := 0.U
}
if (!(asIdBits > 0)) {
reg_satp.asid := 0.U
reg_vsatp.asid := 0.U
}
if (!(vmIdBits > 0)) {
reg_hgatp.asid := 0.U
}
reg_vsstatus.xs := (if (usingRoCC) 3.U else 0.U)
if (nBreakpoints <= 1) reg_tselect := 0.U
for (bpc <- reg_bp map {_.control}) {
bpc.ttype := bpc.tType.U
bpc.maskmax := bpc.maskMax.U
bpc.reserved := 0.U
bpc.zero := 0.U
bpc.h := false.B
if (!usingSupervisor) bpc.s := false.B
if (!usingUser) bpc.u := false.B
if (!usingSupervisor && !usingUser) bpc.m := true.B
when (reset.asBool) {
bpc.action := 0.U
bpc.dmode := false.B
bpc.chain := false.B
bpc.r := false.B
bpc.w := false.B
bpc.x := false.B
}
}
for (bpx <- reg_bp map {_.textra}) {
if (coreParams.mcontextWidth == 0) bpx.mselect := false.B
if (coreParams.scontextWidth == 0) bpx.sselect := false.B
}
for (bp <- reg_bp drop nBreakpoints)
bp := 0.U.asTypeOf(new BP())
for (pmp <- reg_pmp) {
pmp.cfg.res := 0.U
when (reset.asBool) { pmp.reset() }
}
for (((t, insn), i) <- (io.trace zip io.inst).zipWithIndex) {
t.exception := io.retire >= i.U && exception
t.valid := io.retire > i.U || t.exception
t.insn := insn
t.iaddr := io.pc
t.priv := Cat(reg_debug, reg_mstatus.prv)
t.cause := cause
t.interrupt := cause(xLen-1)
t.tval := io.tval
t.wdata.foreach(_ := DontCare)
}
def chooseInterrupt(masksIn: Seq[UInt]): (Bool, UInt) = {
val nonstandard = supported_interrupts.getWidth-1 to 12 by -1
// MEI, MSI, MTI, SEI, SSI, STI, VSEI, VSSI, VSTI, UEI, USI, UTI
val standard = Seq(11, 3, 7, 9, 1, 5, 10, 2, 6, 8, 0, 4)
val priority = nonstandard ++ standard
val masks = masksIn.reverse
val any = masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => m(i))).reduce(_||_)
val which = PriorityMux(masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => (m(i), i.U))))
(any, which)
}
def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = {
(Mux(cmd(1), rdata, 0.U) | wdata) & ~Mux(cmd(1,0).andR, wdata, 0.U)
}
def legalizePrivilege(priv: UInt): UInt =
if (usingSupervisor) Mux(priv === PRV.H.U, PRV.U.U, priv)
else if (usingUser) Fill(2, priv(0))
else PRV.M.U
def trimPrivilege(priv: UInt): UInt =
if (usingSupervisor) priv
else legalizePrivilege(priv)
def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = {
if (xLen == 32) {
val hi = lo + CSRs.mcycleh - CSRs.mcycle
when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) }
when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) }
} else {
when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) }
}
}
def formEPC(x: UInt) = ~(~x | (if (usingCompressed) 1.U else 3.U))
def readEPC(x: UInt) = ~(~x | Mux(reg_misa('c' - 'a'), 1.U, 3.U))
def formTVec(x: UInt) = x andNot Mux(x(0), ((((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign) | 2).U, 2.U)
def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_|_)
def formFS(fs: UInt) = if (coreParams.haveFSDirty) fs else Fill(2, fs.orR)
def formVS(vs: UInt) = if (usingVector) vs else 0.U
}
|
module BoomCore_1( // @[core.scala:51:7]
input clock, // @[core.scala:51:7]
input reset, // @[core.scala:51:7]
input io_hartid, // @[core.scala:54:14]
input io_interrupts_debug, // @[core.scala:54:14]
input io_interrupts_mtip, // @[core.scala:54:14]
input io_interrupts_msip, // @[core.scala:54:14]
input io_interrupts_meip, // @[core.scala:54:14]
input io_interrupts_seip, // @[core.scala:54:14]
output io_ifu_fetchpacket_ready, // @[core.scala:54:14]
input io_ifu_fetchpacket_valid, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_0_valid, // @[core.scala:54:14]
input [31:0] io_ifu_fetchpacket_bits_uops_0_bits_inst, // @[core.scala:54:14]
input [31:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_inst, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_0_bits_is_rvc, // @[core.scala:54:14]
input [39:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_pc, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_0_bits_is_sfb, // @[core.scala:54:14]
input [3:0] io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_0_bits_edge_inst, // @[core.scala:54:14]
input [5:0] io_ifu_fetchpacket_bits_uops_0_bits_pc_lob, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_0_bits_taken, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if, // @[core.scala:54:14]
input [1:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc, // @[core.scala:54:14]
output [3:0] io_ifu_get_pc_0_ftq_idx, // @[core.scala:54:14]
input io_ifu_get_pc_0_entry_cfi_idx_valid, // @[core.scala:54:14]
input [1:0] io_ifu_get_pc_0_entry_cfi_idx_bits, // @[core.scala:54:14]
input io_ifu_get_pc_0_entry_cfi_taken, // @[core.scala:54:14]
input io_ifu_get_pc_0_entry_cfi_mispredicted, // @[core.scala:54:14]
input [2:0] io_ifu_get_pc_0_entry_cfi_type, // @[core.scala:54:14]
input [3:0] io_ifu_get_pc_0_entry_br_mask, // @[core.scala:54:14]
input io_ifu_get_pc_0_entry_cfi_is_call, // @[core.scala:54:14]
input io_ifu_get_pc_0_entry_cfi_is_ret, // @[core.scala:54:14]
input io_ifu_get_pc_0_entry_cfi_npc_plus4, // @[core.scala:54:14]
input [39:0] io_ifu_get_pc_0_entry_ras_top, // @[core.scala:54:14]
input [4:0] io_ifu_get_pc_0_entry_ras_idx, // @[core.scala:54:14]
input io_ifu_get_pc_0_entry_start_bank, // @[core.scala:54:14]
input [39:0] io_ifu_get_pc_0_pc, // @[core.scala:54:14]
input [39:0] io_ifu_get_pc_0_com_pc, // @[core.scala:54:14]
input io_ifu_get_pc_0_next_val, // @[core.scala:54:14]
input [39:0] io_ifu_get_pc_0_next_pc, // @[core.scala:54:14]
output [3:0] io_ifu_get_pc_1_ftq_idx, // @[core.scala:54:14]
input io_ifu_get_pc_1_entry_cfi_idx_valid, // @[core.scala:54:14]
input [1:0] io_ifu_get_pc_1_entry_cfi_idx_bits, // @[core.scala:54:14]
input io_ifu_get_pc_1_entry_cfi_taken, // @[core.scala:54:14]
input io_ifu_get_pc_1_entry_cfi_mispredicted, // @[core.scala:54:14]
input [2:0] io_ifu_get_pc_1_entry_cfi_type, // @[core.scala:54:14]
input [3:0] io_ifu_get_pc_1_entry_br_mask, // @[core.scala:54:14]
input io_ifu_get_pc_1_entry_cfi_is_call, // @[core.scala:54:14]
input io_ifu_get_pc_1_entry_cfi_is_ret, // @[core.scala:54:14]
input io_ifu_get_pc_1_entry_cfi_npc_plus4, // @[core.scala:54:14]
input [39:0] io_ifu_get_pc_1_entry_ras_top, // @[core.scala:54:14]
input [4:0] io_ifu_get_pc_1_entry_ras_idx, // @[core.scala:54:14]
input io_ifu_get_pc_1_entry_start_bank, // @[core.scala:54:14]
input [63:0] io_ifu_get_pc_1_ghist_old_history, // @[core.scala:54:14]
input io_ifu_get_pc_1_ghist_current_saw_branch_not_taken, // @[core.scala:54:14]
input io_ifu_get_pc_1_ghist_new_saw_branch_not_taken, // @[core.scala:54:14]
input io_ifu_get_pc_1_ghist_new_saw_branch_taken, // @[core.scala:54:14]
input [4:0] io_ifu_get_pc_1_ghist_ras_idx, // @[core.scala:54:14]
input [39:0] io_ifu_get_pc_1_pc, // @[core.scala:54:14]
input [39:0] io_ifu_get_pc_1_com_pc, // @[core.scala:54:14]
input io_ifu_get_pc_1_next_val, // @[core.scala:54:14]
input [39:0] io_ifu_get_pc_1_next_pc, // @[core.scala:54:14]
input [39:0] io_ifu_debug_fetch_pc_0, // @[core.scala:54:14]
output io_ifu_status_debug, // @[core.scala:54:14]
output io_ifu_status_cease, // @[core.scala:54:14]
output io_ifu_status_wfi, // @[core.scala:54:14]
output [1:0] io_ifu_status_dprv, // @[core.scala:54:14]
output io_ifu_status_dv, // @[core.scala:54:14]
output [1:0] io_ifu_status_prv, // @[core.scala:54:14]
output io_ifu_status_v, // @[core.scala:54:14]
output io_ifu_status_sd, // @[core.scala:54:14]
output io_ifu_status_mpv, // @[core.scala:54:14]
output io_ifu_status_gva, // @[core.scala:54:14]
output io_ifu_status_tsr, // @[core.scala:54:14]
output io_ifu_status_tw, // @[core.scala:54:14]
output io_ifu_status_tvm, // @[core.scala:54:14]
output io_ifu_status_mxr, // @[core.scala:54:14]
output io_ifu_status_sum, // @[core.scala:54:14]
output io_ifu_status_mprv, // @[core.scala:54:14]
output [1:0] io_ifu_status_fs, // @[core.scala:54:14]
output [1:0] io_ifu_status_mpp, // @[core.scala:54:14]
output io_ifu_status_spp, // @[core.scala:54:14]
output io_ifu_status_mpie, // @[core.scala:54:14]
output io_ifu_status_spie, // @[core.scala:54:14]
output io_ifu_status_mie, // @[core.scala:54:14]
output io_ifu_status_sie, // @[core.scala:54:14]
output io_ifu_sfence_valid, // @[core.scala:54:14]
output io_ifu_sfence_bits_rs1, // @[core.scala:54:14]
output io_ifu_sfence_bits_rs2, // @[core.scala:54:14]
output [38:0] io_ifu_sfence_bits_addr, // @[core.scala:54:14]
output io_ifu_sfence_bits_asid, // @[core.scala:54:14]
output [7:0] io_ifu_brupdate_b1_resolve_mask, // @[core.scala:54:14]
output [7:0] io_ifu_brupdate_b1_mispredict_mask, // @[core.scala:54:14]
output [6:0] io_ifu_brupdate_b2_uop_uopc, // @[core.scala:54:14]
output [31:0] io_ifu_brupdate_b2_uop_inst, // @[core.scala:54:14]
output [31:0] io_ifu_brupdate_b2_uop_debug_inst, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_is_rvc, // @[core.scala:54:14]
output [39:0] io_ifu_brupdate_b2_uop_debug_pc, // @[core.scala:54:14]
output [2:0] io_ifu_brupdate_b2_uop_iq_type, // @[core.scala:54:14]
output [9:0] io_ifu_brupdate_b2_uop_fu_code, // @[core.scala:54:14]
output [3:0] io_ifu_brupdate_b2_uop_ctrl_br_type, // @[core.scala:54:14]
output [1:0] io_ifu_brupdate_b2_uop_ctrl_op1_sel, // @[core.scala:54:14]
output [2:0] io_ifu_brupdate_b2_uop_ctrl_op2_sel, // @[core.scala:54:14]
output [2:0] io_ifu_brupdate_b2_uop_ctrl_imm_sel, // @[core.scala:54:14]
output [4:0] io_ifu_brupdate_b2_uop_ctrl_op_fcn, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_ctrl_fcn_dw, // @[core.scala:54:14]
output [2:0] io_ifu_brupdate_b2_uop_ctrl_csr_cmd, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_ctrl_is_load, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_ctrl_is_sta, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_ctrl_is_std, // @[core.scala:54:14]
output [1:0] io_ifu_brupdate_b2_uop_iw_state, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_iw_p1_poisoned, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_iw_p2_poisoned, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_is_br, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_is_jalr, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_is_jal, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_is_sfb, // @[core.scala:54:14]
output [7:0] io_ifu_brupdate_b2_uop_br_mask, // @[core.scala:54:14]
output [2:0] io_ifu_brupdate_b2_uop_br_tag, // @[core.scala:54:14]
output [3:0] io_ifu_brupdate_b2_uop_ftq_idx, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_edge_inst, // @[core.scala:54:14]
output [5:0] io_ifu_brupdate_b2_uop_pc_lob, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_taken, // @[core.scala:54:14]
output [19:0] io_ifu_brupdate_b2_uop_imm_packed, // @[core.scala:54:14]
output [11:0] io_ifu_brupdate_b2_uop_csr_addr, // @[core.scala:54:14]
output [4:0] io_ifu_brupdate_b2_uop_rob_idx, // @[core.scala:54:14]
output [2:0] io_ifu_brupdate_b2_uop_ldq_idx, // @[core.scala:54:14]
output [2:0] io_ifu_brupdate_b2_uop_stq_idx, // @[core.scala:54:14]
output [1:0] io_ifu_brupdate_b2_uop_rxq_idx, // @[core.scala:54:14]
output [5:0] io_ifu_brupdate_b2_uop_pdst, // @[core.scala:54:14]
output [5:0] io_ifu_brupdate_b2_uop_prs1, // @[core.scala:54:14]
output [5:0] io_ifu_brupdate_b2_uop_prs2, // @[core.scala:54:14]
output [5:0] io_ifu_brupdate_b2_uop_prs3, // @[core.scala:54:14]
output [3:0] io_ifu_brupdate_b2_uop_ppred, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_prs1_busy, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_prs2_busy, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_prs3_busy, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_ppred_busy, // @[core.scala:54:14]
output [5:0] io_ifu_brupdate_b2_uop_stale_pdst, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_exception, // @[core.scala:54:14]
output [63:0] io_ifu_brupdate_b2_uop_exc_cause, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_bypassable, // @[core.scala:54:14]
output [4:0] io_ifu_brupdate_b2_uop_mem_cmd, // @[core.scala:54:14]
output [1:0] io_ifu_brupdate_b2_uop_mem_size, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_mem_signed, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_is_fence, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_is_fencei, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_is_amo, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_uses_ldq, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_uses_stq, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_is_sys_pc2epc, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_is_unique, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_flush_on_commit, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_ldst_is_rs1, // @[core.scala:54:14]
output [5:0] io_ifu_brupdate_b2_uop_ldst, // @[core.scala:54:14]
output [5:0] io_ifu_brupdate_b2_uop_lrs1, // @[core.scala:54:14]
output [5:0] io_ifu_brupdate_b2_uop_lrs2, // @[core.scala:54:14]
output [5:0] io_ifu_brupdate_b2_uop_lrs3, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_ldst_val, // @[core.scala:54:14]
output [1:0] io_ifu_brupdate_b2_uop_dst_rtype, // @[core.scala:54:14]
output [1:0] io_ifu_brupdate_b2_uop_lrs1_rtype, // @[core.scala:54:14]
output [1:0] io_ifu_brupdate_b2_uop_lrs2_rtype, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_frs3_en, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_fp_val, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_fp_single, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_xcpt_pf_if, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_xcpt_ae_if, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_xcpt_ma_if, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_bp_debug_if, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_bp_xcpt_if, // @[core.scala:54:14]
output [1:0] io_ifu_brupdate_b2_uop_debug_fsrc, // @[core.scala:54:14]
output [1:0] io_ifu_brupdate_b2_uop_debug_tsrc, // @[core.scala:54:14]
output io_ifu_brupdate_b2_valid, // @[core.scala:54:14]
output io_ifu_brupdate_b2_mispredict, // @[core.scala:54:14]
output io_ifu_brupdate_b2_taken, // @[core.scala:54:14]
output [2:0] io_ifu_brupdate_b2_cfi_type, // @[core.scala:54:14]
output [1:0] io_ifu_brupdate_b2_pc_sel, // @[core.scala:54:14]
output [39:0] io_ifu_brupdate_b2_jalr_target, // @[core.scala:54:14]
output [20:0] io_ifu_brupdate_b2_target_offset, // @[core.scala:54:14]
output io_ifu_redirect_flush, // @[core.scala:54:14]
output io_ifu_redirect_val, // @[core.scala:54:14]
output [39:0] io_ifu_redirect_pc, // @[core.scala:54:14]
output [3:0] io_ifu_redirect_ftq_idx, // @[core.scala:54:14]
output [63:0] io_ifu_redirect_ghist_old_history, // @[core.scala:54:14]
output io_ifu_redirect_ghist_current_saw_branch_not_taken, // @[core.scala:54:14]
output io_ifu_redirect_ghist_new_saw_branch_not_taken, // @[core.scala:54:14]
output io_ifu_redirect_ghist_new_saw_branch_taken, // @[core.scala:54:14]
output [4:0] io_ifu_redirect_ghist_ras_idx, // @[core.scala:54:14]
output io_ifu_commit_valid, // @[core.scala:54:14]
output [15:0] io_ifu_commit_bits, // @[core.scala:54:14]
output io_ifu_flush_icache, // @[core.scala:54:14]
input io_ifu_perf_acquire, // @[core.scala:54:14]
input io_ifu_perf_tlbMiss, // @[core.scala:54:14]
output [3:0] io_ptw_ptbr_mode, // @[core.scala:54:14]
output [43:0] io_ptw_ptbr_ppn, // @[core.scala:54:14]
output io_ptw_sfence_valid, // @[core.scala:54:14]
output io_ptw_sfence_bits_rs1, // @[core.scala:54:14]
output io_ptw_sfence_bits_rs2, // @[core.scala:54:14]
output [38:0] io_ptw_sfence_bits_addr, // @[core.scala:54:14]
output io_ptw_sfence_bits_asid, // @[core.scala:54:14]
output io_ptw_status_debug, // @[core.scala:54:14]
output io_ptw_status_cease, // @[core.scala:54:14]
output io_ptw_status_wfi, // @[core.scala:54:14]
output [1:0] io_ptw_status_dprv, // @[core.scala:54:14]
output io_ptw_status_dv, // @[core.scala:54:14]
output [1:0] io_ptw_status_prv, // @[core.scala:54:14]
output io_ptw_status_v, // @[core.scala:54:14]
output io_ptw_status_sd, // @[core.scala:54:14]
output io_ptw_status_mpv, // @[core.scala:54:14]
output io_ptw_status_gva, // @[core.scala:54:14]
output io_ptw_status_tsr, // @[core.scala:54:14]
output io_ptw_status_tw, // @[core.scala:54:14]
output io_ptw_status_tvm, // @[core.scala:54:14]
output io_ptw_status_mxr, // @[core.scala:54:14]
output io_ptw_status_sum, // @[core.scala:54:14]
output io_ptw_status_mprv, // @[core.scala:54:14]
output [1:0] io_ptw_status_fs, // @[core.scala:54:14]
output [1:0] io_ptw_status_mpp, // @[core.scala:54:14]
output io_ptw_status_spp, // @[core.scala:54:14]
output io_ptw_status_mpie, // @[core.scala:54:14]
output io_ptw_status_spie, // @[core.scala:54:14]
output io_ptw_status_mie, // @[core.scala:54:14]
output io_ptw_status_sie, // @[core.scala:54:14]
output io_ptw_pmp_0_cfg_l, // @[core.scala:54:14]
output [1:0] io_ptw_pmp_0_cfg_a, // @[core.scala:54:14]
output io_ptw_pmp_0_cfg_x, // @[core.scala:54:14]
output io_ptw_pmp_0_cfg_w, // @[core.scala:54:14]
output io_ptw_pmp_0_cfg_r, // @[core.scala:54:14]
output [29:0] io_ptw_pmp_0_addr, // @[core.scala:54:14]
output [31:0] io_ptw_pmp_0_mask, // @[core.scala:54:14]
output io_ptw_pmp_1_cfg_l, // @[core.scala:54:14]
output [1:0] io_ptw_pmp_1_cfg_a, // @[core.scala:54:14]
output io_ptw_pmp_1_cfg_x, // @[core.scala:54:14]
output io_ptw_pmp_1_cfg_w, // @[core.scala:54:14]
output io_ptw_pmp_1_cfg_r, // @[core.scala:54:14]
output [29:0] io_ptw_pmp_1_addr, // @[core.scala:54:14]
output [31:0] io_ptw_pmp_1_mask, // @[core.scala:54:14]
output io_ptw_pmp_2_cfg_l, // @[core.scala:54:14]
output [1:0] io_ptw_pmp_2_cfg_a, // @[core.scala:54:14]
output io_ptw_pmp_2_cfg_x, // @[core.scala:54:14]
output io_ptw_pmp_2_cfg_w, // @[core.scala:54:14]
output io_ptw_pmp_2_cfg_r, // @[core.scala:54:14]
output [29:0] io_ptw_pmp_2_addr, // @[core.scala:54:14]
output [31:0] io_ptw_pmp_2_mask, // @[core.scala:54:14]
output io_ptw_pmp_3_cfg_l, // @[core.scala:54:14]
output [1:0] io_ptw_pmp_3_cfg_a, // @[core.scala:54:14]
output io_ptw_pmp_3_cfg_x, // @[core.scala:54:14]
output io_ptw_pmp_3_cfg_w, // @[core.scala:54:14]
output io_ptw_pmp_3_cfg_r, // @[core.scala:54:14]
output [29:0] io_ptw_pmp_3_addr, // @[core.scala:54:14]
output [31:0] io_ptw_pmp_3_mask, // @[core.scala:54:14]
output io_ptw_pmp_4_cfg_l, // @[core.scala:54:14]
output [1:0] io_ptw_pmp_4_cfg_a, // @[core.scala:54:14]
output io_ptw_pmp_4_cfg_x, // @[core.scala:54:14]
output io_ptw_pmp_4_cfg_w, // @[core.scala:54:14]
output io_ptw_pmp_4_cfg_r, // @[core.scala:54:14]
output [29:0] io_ptw_pmp_4_addr, // @[core.scala:54:14]
output [31:0] io_ptw_pmp_4_mask, // @[core.scala:54:14]
output io_ptw_pmp_5_cfg_l, // @[core.scala:54:14]
output [1:0] io_ptw_pmp_5_cfg_a, // @[core.scala:54:14]
output io_ptw_pmp_5_cfg_x, // @[core.scala:54:14]
output io_ptw_pmp_5_cfg_w, // @[core.scala:54:14]
output io_ptw_pmp_5_cfg_r, // @[core.scala:54:14]
output [29:0] io_ptw_pmp_5_addr, // @[core.scala:54:14]
output [31:0] io_ptw_pmp_5_mask, // @[core.scala:54:14]
output io_ptw_pmp_6_cfg_l, // @[core.scala:54:14]
output [1:0] io_ptw_pmp_6_cfg_a, // @[core.scala:54:14]
output io_ptw_pmp_6_cfg_x, // @[core.scala:54:14]
output io_ptw_pmp_6_cfg_w, // @[core.scala:54:14]
output io_ptw_pmp_6_cfg_r, // @[core.scala:54:14]
output [29:0] io_ptw_pmp_6_addr, // @[core.scala:54:14]
output [31:0] io_ptw_pmp_6_mask, // @[core.scala:54:14]
output io_ptw_pmp_7_cfg_l, // @[core.scala:54:14]
output [1:0] io_ptw_pmp_7_cfg_a, // @[core.scala:54:14]
output io_ptw_pmp_7_cfg_x, // @[core.scala:54:14]
output io_ptw_pmp_7_cfg_w, // @[core.scala:54:14]
output io_ptw_pmp_7_cfg_r, // @[core.scala:54:14]
output [29:0] io_ptw_pmp_7_addr, // @[core.scala:54:14]
output [31:0] io_ptw_pmp_7_mask, // @[core.scala:54:14]
input io_ptw_perf_l2miss, // @[core.scala:54:14]
input io_ptw_perf_l2hit, // @[core.scala:54:14]
input io_ptw_perf_pte_miss, // @[core.scala:54:14]
input io_ptw_perf_pte_hit, // @[core.scala:54:14]
input io_ptw_clock_enabled, // @[core.scala:54:14]
output io_lsu_exe_0_req_valid, // @[core.scala:54:14]
output [6:0] io_lsu_exe_0_req_bits_uop_uopc, // @[core.scala:54:14]
output [31:0] io_lsu_exe_0_req_bits_uop_inst, // @[core.scala:54:14]
output [31:0] io_lsu_exe_0_req_bits_uop_debug_inst, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_is_rvc, // @[core.scala:54:14]
output [39:0] io_lsu_exe_0_req_bits_uop_debug_pc, // @[core.scala:54:14]
output [2:0] io_lsu_exe_0_req_bits_uop_iq_type, // @[core.scala:54:14]
output [9:0] io_lsu_exe_0_req_bits_uop_fu_code, // @[core.scala:54:14]
output [3:0] io_lsu_exe_0_req_bits_uop_ctrl_br_type, // @[core.scala:54:14]
output [1:0] io_lsu_exe_0_req_bits_uop_ctrl_op1_sel, // @[core.scala:54:14]
output [2:0] io_lsu_exe_0_req_bits_uop_ctrl_op2_sel, // @[core.scala:54:14]
output [2:0] io_lsu_exe_0_req_bits_uop_ctrl_imm_sel, // @[core.scala:54:14]
output [4:0] io_lsu_exe_0_req_bits_uop_ctrl_op_fcn, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14]
output [2:0] io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_ctrl_is_load, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_ctrl_is_sta, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_ctrl_is_std, // @[core.scala:54:14]
output [1:0] io_lsu_exe_0_req_bits_uop_iw_state, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_iw_p1_poisoned, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_iw_p2_poisoned, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_is_br, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_is_jalr, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_is_jal, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_is_sfb, // @[core.scala:54:14]
output [7:0] io_lsu_exe_0_req_bits_uop_br_mask, // @[core.scala:54:14]
output [2:0] io_lsu_exe_0_req_bits_uop_br_tag, // @[core.scala:54:14]
output [3:0] io_lsu_exe_0_req_bits_uop_ftq_idx, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_edge_inst, // @[core.scala:54:14]
output [5:0] io_lsu_exe_0_req_bits_uop_pc_lob, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_taken, // @[core.scala:54:14]
output [19:0] io_lsu_exe_0_req_bits_uop_imm_packed, // @[core.scala:54:14]
output [11:0] io_lsu_exe_0_req_bits_uop_csr_addr, // @[core.scala:54:14]
output [4:0] io_lsu_exe_0_req_bits_uop_rob_idx, // @[core.scala:54:14]
output [2:0] io_lsu_exe_0_req_bits_uop_ldq_idx, // @[core.scala:54:14]
output [2:0] io_lsu_exe_0_req_bits_uop_stq_idx, // @[core.scala:54:14]
output [1:0] io_lsu_exe_0_req_bits_uop_rxq_idx, // @[core.scala:54:14]
output [5:0] io_lsu_exe_0_req_bits_uop_pdst, // @[core.scala:54:14]
output [5:0] io_lsu_exe_0_req_bits_uop_prs1, // @[core.scala:54:14]
output [5:0] io_lsu_exe_0_req_bits_uop_prs2, // @[core.scala:54:14]
output [5:0] io_lsu_exe_0_req_bits_uop_prs3, // @[core.scala:54:14]
output [3:0] io_lsu_exe_0_req_bits_uop_ppred, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_prs1_busy, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_prs2_busy, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_prs3_busy, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_ppred_busy, // @[core.scala:54:14]
output [5:0] io_lsu_exe_0_req_bits_uop_stale_pdst, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_exception, // @[core.scala:54:14]
output [63:0] io_lsu_exe_0_req_bits_uop_exc_cause, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_bypassable, // @[core.scala:54:14]
output [4:0] io_lsu_exe_0_req_bits_uop_mem_cmd, // @[core.scala:54:14]
output [1:0] io_lsu_exe_0_req_bits_uop_mem_size, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_mem_signed, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_is_fence, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_is_fencei, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_is_amo, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_uses_ldq, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_uses_stq, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_is_sys_pc2epc, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_is_unique, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_flush_on_commit, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_ldst_is_rs1, // @[core.scala:54:14]
output [5:0] io_lsu_exe_0_req_bits_uop_ldst, // @[core.scala:54:14]
output [5:0] io_lsu_exe_0_req_bits_uop_lrs1, // @[core.scala:54:14]
output [5:0] io_lsu_exe_0_req_bits_uop_lrs2, // @[core.scala:54:14]
output [5:0] io_lsu_exe_0_req_bits_uop_lrs3, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_ldst_val, // @[core.scala:54:14]
output [1:0] io_lsu_exe_0_req_bits_uop_dst_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_exe_0_req_bits_uop_lrs1_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_exe_0_req_bits_uop_lrs2_rtype, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_frs3_en, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_fp_val, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_fp_single, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_xcpt_pf_if, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_xcpt_ae_if, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_xcpt_ma_if, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_bp_debug_if, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_bp_xcpt_if, // @[core.scala:54:14]
output [1:0] io_lsu_exe_0_req_bits_uop_debug_fsrc, // @[core.scala:54:14]
output [1:0] io_lsu_exe_0_req_bits_uop_debug_tsrc, // @[core.scala:54:14]
output [63:0] io_lsu_exe_0_req_bits_data, // @[core.scala:54:14]
output [39:0] io_lsu_exe_0_req_bits_addr, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_mxcpt_valid, // @[core.scala:54:14]
output [24:0] io_lsu_exe_0_req_bits_mxcpt_bits, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_sfence_valid, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_sfence_bits_rs1, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_sfence_bits_rs2, // @[core.scala:54:14]
output [38:0] io_lsu_exe_0_req_bits_sfence_bits_addr, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_sfence_bits_asid, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_valid, // @[core.scala:54:14]
input [6:0] io_lsu_exe_0_iresp_bits_uop_uopc, // @[core.scala:54:14]
input [31:0] io_lsu_exe_0_iresp_bits_uop_inst, // @[core.scala:54:14]
input [31:0] io_lsu_exe_0_iresp_bits_uop_debug_inst, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_is_rvc, // @[core.scala:54:14]
input [39:0] io_lsu_exe_0_iresp_bits_uop_debug_pc, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_iresp_bits_uop_iq_type, // @[core.scala:54:14]
input [9:0] io_lsu_exe_0_iresp_bits_uop_fu_code, // @[core.scala:54:14]
input [3:0] io_lsu_exe_0_iresp_bits_uop_ctrl_br_type, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel, // @[core.scala:54:14]
input [4:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_ctrl_is_load, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_ctrl_is_std, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_iw_state, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_is_br, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_is_jalr, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_is_jal, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_is_sfb, // @[core.scala:54:14]
input [7:0] io_lsu_exe_0_iresp_bits_uop_br_mask, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_iresp_bits_uop_br_tag, // @[core.scala:54:14]
input [3:0] io_lsu_exe_0_iresp_bits_uop_ftq_idx, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_edge_inst, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_pc_lob, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_taken, // @[core.scala:54:14]
input [19:0] io_lsu_exe_0_iresp_bits_uop_imm_packed, // @[core.scala:54:14]
input [11:0] io_lsu_exe_0_iresp_bits_uop_csr_addr, // @[core.scala:54:14]
input [4:0] io_lsu_exe_0_iresp_bits_uop_rob_idx, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_iresp_bits_uop_ldq_idx, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_iresp_bits_uop_stq_idx, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_rxq_idx, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_pdst, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_prs1, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_prs2, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_prs3, // @[core.scala:54:14]
input [3:0] io_lsu_exe_0_iresp_bits_uop_ppred, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_prs1_busy, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_prs2_busy, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_prs3_busy, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_ppred_busy, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_stale_pdst, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_exception, // @[core.scala:54:14]
input [63:0] io_lsu_exe_0_iresp_bits_uop_exc_cause, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_bypassable, // @[core.scala:54:14]
input [4:0] io_lsu_exe_0_iresp_bits_uop_mem_cmd, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_mem_size, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_mem_signed, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_is_fence, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_is_fencei, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_is_amo, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_uses_ldq, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_uses_stq, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_is_unique, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_flush_on_commit, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_ldst, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs1, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs2, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs3, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_ldst_val, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_dst_rtype, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_lrs1_rtype, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_lrs2_rtype, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_frs3_en, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_fp_val, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_fp_single, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_bp_debug_if, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_debug_fsrc, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_debug_tsrc, // @[core.scala:54:14]
input [63:0] io_lsu_exe_0_iresp_bits_data, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_valid, // @[core.scala:54:14]
input [6:0] io_lsu_exe_0_fresp_bits_uop_uopc, // @[core.scala:54:14]
input [31:0] io_lsu_exe_0_fresp_bits_uop_inst, // @[core.scala:54:14]
input [31:0] io_lsu_exe_0_fresp_bits_uop_debug_inst, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_is_rvc, // @[core.scala:54:14]
input [39:0] io_lsu_exe_0_fresp_bits_uop_debug_pc, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_fresp_bits_uop_iq_type, // @[core.scala:54:14]
input [9:0] io_lsu_exe_0_fresp_bits_uop_fu_code, // @[core.scala:54:14]
input [3:0] io_lsu_exe_0_fresp_bits_uop_ctrl_br_type, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel, // @[core.scala:54:14]
input [4:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_ctrl_is_load, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_ctrl_is_std, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_iw_state, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_is_br, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_is_jalr, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_is_jal, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_is_sfb, // @[core.scala:54:14]
input [7:0] io_lsu_exe_0_fresp_bits_uop_br_mask, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_fresp_bits_uop_br_tag, // @[core.scala:54:14]
input [3:0] io_lsu_exe_0_fresp_bits_uop_ftq_idx, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_edge_inst, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_pc_lob, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_taken, // @[core.scala:54:14]
input [19:0] io_lsu_exe_0_fresp_bits_uop_imm_packed, // @[core.scala:54:14]
input [11:0] io_lsu_exe_0_fresp_bits_uop_csr_addr, // @[core.scala:54:14]
input [4:0] io_lsu_exe_0_fresp_bits_uop_rob_idx, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_fresp_bits_uop_ldq_idx, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_fresp_bits_uop_stq_idx, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_rxq_idx, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_pdst, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_prs1, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_prs2, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_prs3, // @[core.scala:54:14]
input [3:0] io_lsu_exe_0_fresp_bits_uop_ppred, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_prs1_busy, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_prs2_busy, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_prs3_busy, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_ppred_busy, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_stale_pdst, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_exception, // @[core.scala:54:14]
input [63:0] io_lsu_exe_0_fresp_bits_uop_exc_cause, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_bypassable, // @[core.scala:54:14]
input [4:0] io_lsu_exe_0_fresp_bits_uop_mem_cmd, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_mem_size, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_mem_signed, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_is_fence, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_is_fencei, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_is_amo, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_uses_ldq, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_uses_stq, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_is_unique, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_flush_on_commit, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_ldst, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs1, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs2, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs3, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_ldst_val, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_dst_rtype, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_lrs1_rtype, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_lrs2_rtype, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_frs3_en, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_fp_val, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_fp_single, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_bp_debug_if, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_debug_fsrc, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_debug_tsrc, // @[core.scala:54:14]
input [64:0] io_lsu_exe_0_fresp_bits_data, // @[core.scala:54:14]
output io_lsu_dis_uops_0_valid, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_0_bits_uopc, // @[core.scala:54:14]
output [31:0] io_lsu_dis_uops_0_bits_inst, // @[core.scala:54:14]
output [31:0] io_lsu_dis_uops_0_bits_debug_inst, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_is_rvc, // @[core.scala:54:14]
output [39:0] io_lsu_dis_uops_0_bits_debug_pc, // @[core.scala:54:14]
output [2:0] io_lsu_dis_uops_0_bits_iq_type, // @[core.scala:54:14]
output [9:0] io_lsu_dis_uops_0_bits_fu_code, // @[core.scala:54:14]
output [3:0] io_lsu_dis_uops_0_bits_ctrl_br_type, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_0_bits_ctrl_op1_sel, // @[core.scala:54:14]
output [2:0] io_lsu_dis_uops_0_bits_ctrl_op2_sel, // @[core.scala:54:14]
output [2:0] io_lsu_dis_uops_0_bits_ctrl_imm_sel, // @[core.scala:54:14]
output [4:0] io_lsu_dis_uops_0_bits_ctrl_op_fcn, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_ctrl_fcn_dw, // @[core.scala:54:14]
output [2:0] io_lsu_dis_uops_0_bits_ctrl_csr_cmd, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_ctrl_is_load, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_ctrl_is_sta, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_ctrl_is_std, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_0_bits_iw_state, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_iw_p1_poisoned, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_iw_p2_poisoned, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_is_br, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_is_jalr, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_is_jal, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_is_sfb, // @[core.scala:54:14]
output [7:0] io_lsu_dis_uops_0_bits_br_mask, // @[core.scala:54:14]
output [2:0] io_lsu_dis_uops_0_bits_br_tag, // @[core.scala:54:14]
output [3:0] io_lsu_dis_uops_0_bits_ftq_idx, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_edge_inst, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_0_bits_pc_lob, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_taken, // @[core.scala:54:14]
output [19:0] io_lsu_dis_uops_0_bits_imm_packed, // @[core.scala:54:14]
output [11:0] io_lsu_dis_uops_0_bits_csr_addr, // @[core.scala:54:14]
output [4:0] io_lsu_dis_uops_0_bits_rob_idx, // @[core.scala:54:14]
output [2:0] io_lsu_dis_uops_0_bits_ldq_idx, // @[core.scala:54:14]
output [2:0] io_lsu_dis_uops_0_bits_stq_idx, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_0_bits_rxq_idx, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_0_bits_pdst, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_0_bits_prs1, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_0_bits_prs2, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_0_bits_prs3, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_prs1_busy, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_prs2_busy, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_prs3_busy, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_0_bits_stale_pdst, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_exception, // @[core.scala:54:14]
output [63:0] io_lsu_dis_uops_0_bits_exc_cause, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_bypassable, // @[core.scala:54:14]
output [4:0] io_lsu_dis_uops_0_bits_mem_cmd, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_0_bits_mem_size, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_mem_signed, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_is_fence, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_is_fencei, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_is_amo, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_uses_ldq, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_uses_stq, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_is_sys_pc2epc, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_is_unique, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_flush_on_commit, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_ldst_is_rs1, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_0_bits_ldst, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_0_bits_lrs1, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_0_bits_lrs2, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_0_bits_lrs3, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_ldst_val, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_0_bits_dst_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_0_bits_lrs1_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_0_bits_lrs2_rtype, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_frs3_en, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_fp_val, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_fp_single, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_xcpt_pf_if, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_xcpt_ae_if, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_xcpt_ma_if, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_bp_debug_if, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_bp_xcpt_if, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_0_bits_debug_fsrc, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_0_bits_debug_tsrc, // @[core.scala:54:14]
input [2:0] io_lsu_dis_ldq_idx_0, // @[core.scala:54:14]
input [2:0] io_lsu_dis_stq_idx_0, // @[core.scala:54:14]
input io_lsu_ldq_full_0, // @[core.scala:54:14]
input io_lsu_stq_full_0, // @[core.scala:54:14]
input io_lsu_fp_stdata_ready, // @[core.scala:54:14]
output io_lsu_fp_stdata_valid, // @[core.scala:54:14]
output [6:0] io_lsu_fp_stdata_bits_uop_uopc, // @[core.scala:54:14]
output [31:0] io_lsu_fp_stdata_bits_uop_inst, // @[core.scala:54:14]
output [31:0] io_lsu_fp_stdata_bits_uop_debug_inst, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_is_rvc, // @[core.scala:54:14]
output [39:0] io_lsu_fp_stdata_bits_uop_debug_pc, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_uop_iq_type, // @[core.scala:54:14]
output [9:0] io_lsu_fp_stdata_bits_uop_fu_code, // @[core.scala:54:14]
output [3:0] io_lsu_fp_stdata_bits_uop_ctrl_br_type, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_uop_ctrl_op1_sel, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_uop_ctrl_op2_sel, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_uop_ctrl_imm_sel, // @[core.scala:54:14]
output [4:0] io_lsu_fp_stdata_bits_uop_ctrl_op_fcn, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_ctrl_is_load, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_ctrl_is_sta, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_ctrl_is_std, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_uop_iw_state, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_iw_p1_poisoned, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_iw_p2_poisoned, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_is_br, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_is_jalr, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_is_jal, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_is_sfb, // @[core.scala:54:14]
output [7:0] io_lsu_fp_stdata_bits_uop_br_mask, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_uop_br_tag, // @[core.scala:54:14]
output [3:0] io_lsu_fp_stdata_bits_uop_ftq_idx, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_edge_inst, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_uop_pc_lob, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_taken, // @[core.scala:54:14]
output [19:0] io_lsu_fp_stdata_bits_uop_imm_packed, // @[core.scala:54:14]
output [11:0] io_lsu_fp_stdata_bits_uop_csr_addr, // @[core.scala:54:14]
output [4:0] io_lsu_fp_stdata_bits_uop_rob_idx, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_uop_ldq_idx, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_uop_stq_idx, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_uop_rxq_idx, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_uop_pdst, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_uop_prs1, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_uop_prs2, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_uop_prs3, // @[core.scala:54:14]
output [3:0] io_lsu_fp_stdata_bits_uop_ppred, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_prs1_busy, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_prs2_busy, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_prs3_busy, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_ppred_busy, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_uop_stale_pdst, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_exception, // @[core.scala:54:14]
output [63:0] io_lsu_fp_stdata_bits_uop_exc_cause, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_bypassable, // @[core.scala:54:14]
output [4:0] io_lsu_fp_stdata_bits_uop_mem_cmd, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_uop_mem_size, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_mem_signed, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_is_fence, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_is_fencei, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_is_amo, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_uses_ldq, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_uses_stq, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_is_sys_pc2epc, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_is_unique, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_flush_on_commit, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_ldst_is_rs1, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_uop_ldst, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_uop_lrs1, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_uop_lrs2, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_uop_lrs3, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_ldst_val, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_uop_dst_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_uop_lrs1_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_uop_lrs2_rtype, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_frs3_en, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_fp_val, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_fp_single, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_xcpt_pf_if, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_xcpt_ae_if, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_xcpt_ma_if, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_bp_debug_if, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_bp_xcpt_if, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_uop_debug_fsrc, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_uop_debug_tsrc, // @[core.scala:54:14]
output [63:0] io_lsu_fp_stdata_bits_data, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_predicated, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_valid, // @[core.scala:54:14]
output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_uopc, // @[core.scala:54:14]
output [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_inst, // @[core.scala:54:14]
output [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc, // @[core.scala:54:14]
output [39:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type, // @[core.scala:54:14]
output [9:0] io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code, // @[core.scala:54:14]
output [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel, // @[core.scala:54:14]
output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_is_br, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb, // @[core.scala:54:14]
output [7:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag, // @[core.scala:54:14]
output [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_taken, // @[core.scala:54:14]
output [19:0] io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed, // @[core.scala:54:14]
output [11:0] io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr, // @[core.scala:54:14]
output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pdst, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs1, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs2, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs3, // @[core.scala:54:14]
output [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ppred, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_exception, // @[core.scala:54:14]
output [63:0] io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable, // @[core.scala:54:14]
output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldst, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc, // @[core.scala:54:14]
output [4:0] io_lsu_fp_stdata_bits_fflags_bits_flags, // @[core.scala:54:14]
output io_lsu_commit_valids_0, // @[core.scala:54:14]
output io_lsu_commit_arch_valids_0, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_0_uopc, // @[core.scala:54:14]
output [31:0] io_lsu_commit_uops_0_inst, // @[core.scala:54:14]
output [31:0] io_lsu_commit_uops_0_debug_inst, // @[core.scala:54:14]
output io_lsu_commit_uops_0_is_rvc, // @[core.scala:54:14]
output [39:0] io_lsu_commit_uops_0_debug_pc, // @[core.scala:54:14]
output [2:0] io_lsu_commit_uops_0_iq_type, // @[core.scala:54:14]
output [9:0] io_lsu_commit_uops_0_fu_code, // @[core.scala:54:14]
output [3:0] io_lsu_commit_uops_0_ctrl_br_type, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_0_ctrl_op1_sel, // @[core.scala:54:14]
output [2:0] io_lsu_commit_uops_0_ctrl_op2_sel, // @[core.scala:54:14]
output [2:0] io_lsu_commit_uops_0_ctrl_imm_sel, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_0_ctrl_op_fcn, // @[core.scala:54:14]
output io_lsu_commit_uops_0_ctrl_fcn_dw, // @[core.scala:54:14]
output [2:0] io_lsu_commit_uops_0_ctrl_csr_cmd, // @[core.scala:54:14]
output io_lsu_commit_uops_0_ctrl_is_load, // @[core.scala:54:14]
output io_lsu_commit_uops_0_ctrl_is_sta, // @[core.scala:54:14]
output io_lsu_commit_uops_0_ctrl_is_std, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_0_iw_state, // @[core.scala:54:14]
output io_lsu_commit_uops_0_iw_p1_poisoned, // @[core.scala:54:14]
output io_lsu_commit_uops_0_iw_p2_poisoned, // @[core.scala:54:14]
output io_lsu_commit_uops_0_is_br, // @[core.scala:54:14]
output io_lsu_commit_uops_0_is_jalr, // @[core.scala:54:14]
output io_lsu_commit_uops_0_is_jal, // @[core.scala:54:14]
output io_lsu_commit_uops_0_is_sfb, // @[core.scala:54:14]
output [7:0] io_lsu_commit_uops_0_br_mask, // @[core.scala:54:14]
output [2:0] io_lsu_commit_uops_0_br_tag, // @[core.scala:54:14]
output [3:0] io_lsu_commit_uops_0_ftq_idx, // @[core.scala:54:14]
output io_lsu_commit_uops_0_edge_inst, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_0_pc_lob, // @[core.scala:54:14]
output io_lsu_commit_uops_0_taken, // @[core.scala:54:14]
output [19:0] io_lsu_commit_uops_0_imm_packed, // @[core.scala:54:14]
output [11:0] io_lsu_commit_uops_0_csr_addr, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_0_rob_idx, // @[core.scala:54:14]
output [2:0] io_lsu_commit_uops_0_ldq_idx, // @[core.scala:54:14]
output [2:0] io_lsu_commit_uops_0_stq_idx, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_0_rxq_idx, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_0_pdst, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_0_prs1, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_0_prs2, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_0_prs3, // @[core.scala:54:14]
output [3:0] io_lsu_commit_uops_0_ppred, // @[core.scala:54:14]
output io_lsu_commit_uops_0_prs1_busy, // @[core.scala:54:14]
output io_lsu_commit_uops_0_prs2_busy, // @[core.scala:54:14]
output io_lsu_commit_uops_0_prs3_busy, // @[core.scala:54:14]
output io_lsu_commit_uops_0_ppred_busy, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_0_stale_pdst, // @[core.scala:54:14]
output io_lsu_commit_uops_0_exception, // @[core.scala:54:14]
output [63:0] io_lsu_commit_uops_0_exc_cause, // @[core.scala:54:14]
output io_lsu_commit_uops_0_bypassable, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_0_mem_cmd, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_0_mem_size, // @[core.scala:54:14]
output io_lsu_commit_uops_0_mem_signed, // @[core.scala:54:14]
output io_lsu_commit_uops_0_is_fence, // @[core.scala:54:14]
output io_lsu_commit_uops_0_is_fencei, // @[core.scala:54:14]
output io_lsu_commit_uops_0_is_amo, // @[core.scala:54:14]
output io_lsu_commit_uops_0_uses_ldq, // @[core.scala:54:14]
output io_lsu_commit_uops_0_uses_stq, // @[core.scala:54:14]
output io_lsu_commit_uops_0_is_sys_pc2epc, // @[core.scala:54:14]
output io_lsu_commit_uops_0_is_unique, // @[core.scala:54:14]
output io_lsu_commit_uops_0_flush_on_commit, // @[core.scala:54:14]
output io_lsu_commit_uops_0_ldst_is_rs1, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_0_ldst, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_0_lrs1, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_0_lrs2, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_0_lrs3, // @[core.scala:54:14]
output io_lsu_commit_uops_0_ldst_val, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_0_dst_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_0_lrs1_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_0_lrs2_rtype, // @[core.scala:54:14]
output io_lsu_commit_uops_0_frs3_en, // @[core.scala:54:14]
output io_lsu_commit_uops_0_fp_val, // @[core.scala:54:14]
output io_lsu_commit_uops_0_fp_single, // @[core.scala:54:14]
output io_lsu_commit_uops_0_xcpt_pf_if, // @[core.scala:54:14]
output io_lsu_commit_uops_0_xcpt_ae_if, // @[core.scala:54:14]
output io_lsu_commit_uops_0_xcpt_ma_if, // @[core.scala:54:14]
output io_lsu_commit_uops_0_bp_debug_if, // @[core.scala:54:14]
output io_lsu_commit_uops_0_bp_xcpt_if, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_0_debug_fsrc, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_0_debug_tsrc, // @[core.scala:54:14]
output io_lsu_commit_fflags_valid, // @[core.scala:54:14]
output [4:0] io_lsu_commit_fflags_bits, // @[core.scala:54:14]
output [31:0] io_lsu_commit_debug_insts_0, // @[core.scala:54:14]
output io_lsu_commit_rbk_valids_0, // @[core.scala:54:14]
output io_lsu_commit_rollback, // @[core.scala:54:14]
output [63:0] io_lsu_commit_debug_wdata_0, // @[core.scala:54:14]
output io_lsu_commit_load_at_rob_head, // @[core.scala:54:14]
input io_lsu_clr_bsy_0_valid, // @[core.scala:54:14]
input [4:0] io_lsu_clr_bsy_0_bits, // @[core.scala:54:14]
input io_lsu_clr_bsy_1_valid, // @[core.scala:54:14]
input [4:0] io_lsu_clr_bsy_1_bits, // @[core.scala:54:14]
input [4:0] io_lsu_clr_unsafe_0_bits, // @[core.scala:54:14]
output io_lsu_fence_dmem, // @[core.scala:54:14]
input io_lsu_spec_ld_wakeup_0_valid, // @[core.scala:54:14]
input [5:0] io_lsu_spec_ld_wakeup_0_bits, // @[core.scala:54:14]
input io_lsu_ld_miss, // @[core.scala:54:14]
output [7:0] io_lsu_brupdate_b1_resolve_mask, // @[core.scala:54:14]
output [7:0] io_lsu_brupdate_b1_mispredict_mask, // @[core.scala:54:14]
output [6:0] io_lsu_brupdate_b2_uop_uopc, // @[core.scala:54:14]
output [31:0] io_lsu_brupdate_b2_uop_inst, // @[core.scala:54:14]
output [31:0] io_lsu_brupdate_b2_uop_debug_inst, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_is_rvc, // @[core.scala:54:14]
output [39:0] io_lsu_brupdate_b2_uop_debug_pc, // @[core.scala:54:14]
output [2:0] io_lsu_brupdate_b2_uop_iq_type, // @[core.scala:54:14]
output [9:0] io_lsu_brupdate_b2_uop_fu_code, // @[core.scala:54:14]
output [3:0] io_lsu_brupdate_b2_uop_ctrl_br_type, // @[core.scala:54:14]
output [1:0] io_lsu_brupdate_b2_uop_ctrl_op1_sel, // @[core.scala:54:14]
output [2:0] io_lsu_brupdate_b2_uop_ctrl_op2_sel, // @[core.scala:54:14]
output [2:0] io_lsu_brupdate_b2_uop_ctrl_imm_sel, // @[core.scala:54:14]
output [4:0] io_lsu_brupdate_b2_uop_ctrl_op_fcn, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_ctrl_fcn_dw, // @[core.scala:54:14]
output [2:0] io_lsu_brupdate_b2_uop_ctrl_csr_cmd, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_ctrl_is_load, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_ctrl_is_sta, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_ctrl_is_std, // @[core.scala:54:14]
output [1:0] io_lsu_brupdate_b2_uop_iw_state, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_iw_p1_poisoned, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_iw_p2_poisoned, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_is_br, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_is_jalr, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_is_jal, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_is_sfb, // @[core.scala:54:14]
output [7:0] io_lsu_brupdate_b2_uop_br_mask, // @[core.scala:54:14]
output [2:0] io_lsu_brupdate_b2_uop_br_tag, // @[core.scala:54:14]
output [3:0] io_lsu_brupdate_b2_uop_ftq_idx, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_edge_inst, // @[core.scala:54:14]
output [5:0] io_lsu_brupdate_b2_uop_pc_lob, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_taken, // @[core.scala:54:14]
output [19:0] io_lsu_brupdate_b2_uop_imm_packed, // @[core.scala:54:14]
output [11:0] io_lsu_brupdate_b2_uop_csr_addr, // @[core.scala:54:14]
output [4:0] io_lsu_brupdate_b2_uop_rob_idx, // @[core.scala:54:14]
output [2:0] io_lsu_brupdate_b2_uop_ldq_idx, // @[core.scala:54:14]
output [2:0] io_lsu_brupdate_b2_uop_stq_idx, // @[core.scala:54:14]
output [1:0] io_lsu_brupdate_b2_uop_rxq_idx, // @[core.scala:54:14]
output [5:0] io_lsu_brupdate_b2_uop_pdst, // @[core.scala:54:14]
output [5:0] io_lsu_brupdate_b2_uop_prs1, // @[core.scala:54:14]
output [5:0] io_lsu_brupdate_b2_uop_prs2, // @[core.scala:54:14]
output [5:0] io_lsu_brupdate_b2_uop_prs3, // @[core.scala:54:14]
output [3:0] io_lsu_brupdate_b2_uop_ppred, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_prs1_busy, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_prs2_busy, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_prs3_busy, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_ppred_busy, // @[core.scala:54:14]
output [5:0] io_lsu_brupdate_b2_uop_stale_pdst, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_exception, // @[core.scala:54:14]
output [63:0] io_lsu_brupdate_b2_uop_exc_cause, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_bypassable, // @[core.scala:54:14]
output [4:0] io_lsu_brupdate_b2_uop_mem_cmd, // @[core.scala:54:14]
output [1:0] io_lsu_brupdate_b2_uop_mem_size, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_mem_signed, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_is_fence, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_is_fencei, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_is_amo, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_uses_ldq, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_uses_stq, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_is_sys_pc2epc, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_is_unique, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_flush_on_commit, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_ldst_is_rs1, // @[core.scala:54:14]
output [5:0] io_lsu_brupdate_b2_uop_ldst, // @[core.scala:54:14]
output [5:0] io_lsu_brupdate_b2_uop_lrs1, // @[core.scala:54:14]
output [5:0] io_lsu_brupdate_b2_uop_lrs2, // @[core.scala:54:14]
output [5:0] io_lsu_brupdate_b2_uop_lrs3, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_ldst_val, // @[core.scala:54:14]
output [1:0] io_lsu_brupdate_b2_uop_dst_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_frs3_en, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_fp_val, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_fp_single, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_xcpt_pf_if, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_xcpt_ae_if, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_xcpt_ma_if, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_bp_debug_if, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_bp_xcpt_if, // @[core.scala:54:14]
output [1:0] io_lsu_brupdate_b2_uop_debug_fsrc, // @[core.scala:54:14]
output [1:0] io_lsu_brupdate_b2_uop_debug_tsrc, // @[core.scala:54:14]
output io_lsu_brupdate_b2_valid, // @[core.scala:54:14]
output io_lsu_brupdate_b2_mispredict, // @[core.scala:54:14]
output io_lsu_brupdate_b2_taken, // @[core.scala:54:14]
output [2:0] io_lsu_brupdate_b2_cfi_type, // @[core.scala:54:14]
output [1:0] io_lsu_brupdate_b2_pc_sel, // @[core.scala:54:14]
output [39:0] io_lsu_brupdate_b2_jalr_target, // @[core.scala:54:14]
output [20:0] io_lsu_brupdate_b2_target_offset, // @[core.scala:54:14]
output [4:0] io_lsu_rob_pnr_idx, // @[core.scala:54:14]
output [4:0] io_lsu_rob_head_idx, // @[core.scala:54:14]
output io_lsu_exception, // @[core.scala:54:14]
input io_lsu_fencei_rdy, // @[core.scala:54:14]
input io_lsu_lxcpt_valid, // @[core.scala:54:14]
input [6:0] io_lsu_lxcpt_bits_uop_uopc, // @[core.scala:54:14]
input [31:0] io_lsu_lxcpt_bits_uop_inst, // @[core.scala:54:14]
input [31:0] io_lsu_lxcpt_bits_uop_debug_inst, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_is_rvc, // @[core.scala:54:14]
input [39:0] io_lsu_lxcpt_bits_uop_debug_pc, // @[core.scala:54:14]
input [2:0] io_lsu_lxcpt_bits_uop_iq_type, // @[core.scala:54:14]
input [9:0] io_lsu_lxcpt_bits_uop_fu_code, // @[core.scala:54:14]
input [3:0] io_lsu_lxcpt_bits_uop_ctrl_br_type, // @[core.scala:54:14]
input [1:0] io_lsu_lxcpt_bits_uop_ctrl_op1_sel, // @[core.scala:54:14]
input [2:0] io_lsu_lxcpt_bits_uop_ctrl_op2_sel, // @[core.scala:54:14]
input [2:0] io_lsu_lxcpt_bits_uop_ctrl_imm_sel, // @[core.scala:54:14]
input [4:0] io_lsu_lxcpt_bits_uop_ctrl_op_fcn, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14]
input [2:0] io_lsu_lxcpt_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_ctrl_is_load, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_ctrl_is_sta, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_ctrl_is_std, // @[core.scala:54:14]
input [1:0] io_lsu_lxcpt_bits_uop_iw_state, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_iw_p1_poisoned, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_iw_p2_poisoned, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_is_br, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_is_jalr, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_is_jal, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_is_sfb, // @[core.scala:54:14]
input [7:0] io_lsu_lxcpt_bits_uop_br_mask, // @[core.scala:54:14]
input [2:0] io_lsu_lxcpt_bits_uop_br_tag, // @[core.scala:54:14]
input [3:0] io_lsu_lxcpt_bits_uop_ftq_idx, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_edge_inst, // @[core.scala:54:14]
input [5:0] io_lsu_lxcpt_bits_uop_pc_lob, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_taken, // @[core.scala:54:14]
input [19:0] io_lsu_lxcpt_bits_uop_imm_packed, // @[core.scala:54:14]
input [11:0] io_lsu_lxcpt_bits_uop_csr_addr, // @[core.scala:54:14]
input [4:0] io_lsu_lxcpt_bits_uop_rob_idx, // @[core.scala:54:14]
input [2:0] io_lsu_lxcpt_bits_uop_ldq_idx, // @[core.scala:54:14]
input [2:0] io_lsu_lxcpt_bits_uop_stq_idx, // @[core.scala:54:14]
input [1:0] io_lsu_lxcpt_bits_uop_rxq_idx, // @[core.scala:54:14]
input [5:0] io_lsu_lxcpt_bits_uop_pdst, // @[core.scala:54:14]
input [5:0] io_lsu_lxcpt_bits_uop_prs1, // @[core.scala:54:14]
input [5:0] io_lsu_lxcpt_bits_uop_prs2, // @[core.scala:54:14]
input [5:0] io_lsu_lxcpt_bits_uop_prs3, // @[core.scala:54:14]
input [3:0] io_lsu_lxcpt_bits_uop_ppred, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_prs1_busy, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_prs2_busy, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_prs3_busy, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_ppred_busy, // @[core.scala:54:14]
input [5:0] io_lsu_lxcpt_bits_uop_stale_pdst, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_exception, // @[core.scala:54:14]
input [63:0] io_lsu_lxcpt_bits_uop_exc_cause, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_bypassable, // @[core.scala:54:14]
input [4:0] io_lsu_lxcpt_bits_uop_mem_cmd, // @[core.scala:54:14]
input [1:0] io_lsu_lxcpt_bits_uop_mem_size, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_mem_signed, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_is_fence, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_is_fencei, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_is_amo, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_uses_ldq, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_uses_stq, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_is_sys_pc2epc, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_is_unique, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_flush_on_commit, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_ldst_is_rs1, // @[core.scala:54:14]
input [5:0] io_lsu_lxcpt_bits_uop_ldst, // @[core.scala:54:14]
input [5:0] io_lsu_lxcpt_bits_uop_lrs1, // @[core.scala:54:14]
input [5:0] io_lsu_lxcpt_bits_uop_lrs2, // @[core.scala:54:14]
input [5:0] io_lsu_lxcpt_bits_uop_lrs3, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_ldst_val, // @[core.scala:54:14]
input [1:0] io_lsu_lxcpt_bits_uop_dst_rtype, // @[core.scala:54:14]
input [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype, // @[core.scala:54:14]
input [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_frs3_en, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_fp_val, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_fp_single, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_xcpt_pf_if, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_xcpt_ae_if, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_xcpt_ma_if, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_bp_debug_if, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_bp_xcpt_if, // @[core.scala:54:14]
input [1:0] io_lsu_lxcpt_bits_uop_debug_fsrc, // @[core.scala:54:14]
input [1:0] io_lsu_lxcpt_bits_uop_debug_tsrc, // @[core.scala:54:14]
input [4:0] io_lsu_lxcpt_bits_cause, // @[core.scala:54:14]
input [39:0] io_lsu_lxcpt_bits_badvaddr, // @[core.scala:54:14]
output [63:0] io_lsu_tsc_reg, // @[core.scala:54:14]
input io_lsu_perf_acquire, // @[core.scala:54:14]
input io_lsu_perf_release, // @[core.scala:54:14]
input io_lsu_perf_tlbMiss, // @[core.scala:54:14]
input io_ptw_tlb_req_ready, // @[core.scala:54:14]
input io_ptw_tlb_resp_valid, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_ae_ptw, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_ae_final, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_pf, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_gf, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_hr, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_hw, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_hx, // @[core.scala:54:14]
input [9:0] io_ptw_tlb_resp_bits_pte_reserved_for_future, // @[core.scala:54:14]
input [43:0] io_ptw_tlb_resp_bits_pte_ppn, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_resp_bits_pte_reserved_for_software, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_pte_d, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_pte_a, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_pte_g, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_pte_u, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_pte_x, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_pte_w, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_pte_r, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_pte_v, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_resp_bits_level, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_homogeneous, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_gpa_valid, // @[core.scala:54:14]
input [38:0] io_ptw_tlb_resp_bits_gpa_bits, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_gpa_is_pte, // @[core.scala:54:14]
input [3:0] io_ptw_tlb_ptbr_mode, // @[core.scala:54:14]
input [43:0] io_ptw_tlb_ptbr_ppn, // @[core.scala:54:14]
input io_ptw_tlb_status_debug, // @[core.scala:54:14]
input io_ptw_tlb_status_cease, // @[core.scala:54:14]
input io_ptw_tlb_status_wfi, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_status_dprv, // @[core.scala:54:14]
input io_ptw_tlb_status_dv, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_status_prv, // @[core.scala:54:14]
input io_ptw_tlb_status_v, // @[core.scala:54:14]
input io_ptw_tlb_status_sd, // @[core.scala:54:14]
input io_ptw_tlb_status_mpv, // @[core.scala:54:14]
input io_ptw_tlb_status_gva, // @[core.scala:54:14]
input io_ptw_tlb_status_tsr, // @[core.scala:54:14]
input io_ptw_tlb_status_tw, // @[core.scala:54:14]
input io_ptw_tlb_status_tvm, // @[core.scala:54:14]
input io_ptw_tlb_status_mxr, // @[core.scala:54:14]
input io_ptw_tlb_status_sum, // @[core.scala:54:14]
input io_ptw_tlb_status_mprv, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_status_fs, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_status_mpp, // @[core.scala:54:14]
input io_ptw_tlb_status_spp, // @[core.scala:54:14]
input io_ptw_tlb_status_mpie, // @[core.scala:54:14]
input io_ptw_tlb_status_spie, // @[core.scala:54:14]
input io_ptw_tlb_status_mie, // @[core.scala:54:14]
input io_ptw_tlb_status_sie, // @[core.scala:54:14]
input io_ptw_tlb_pmp_0_cfg_l, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_pmp_0_cfg_a, // @[core.scala:54:14]
input io_ptw_tlb_pmp_0_cfg_x, // @[core.scala:54:14]
input io_ptw_tlb_pmp_0_cfg_w, // @[core.scala:54:14]
input io_ptw_tlb_pmp_0_cfg_r, // @[core.scala:54:14]
input [29:0] io_ptw_tlb_pmp_0_addr, // @[core.scala:54:14]
input [31:0] io_ptw_tlb_pmp_0_mask, // @[core.scala:54:14]
input io_ptw_tlb_pmp_1_cfg_l, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_pmp_1_cfg_a, // @[core.scala:54:14]
input io_ptw_tlb_pmp_1_cfg_x, // @[core.scala:54:14]
input io_ptw_tlb_pmp_1_cfg_w, // @[core.scala:54:14]
input io_ptw_tlb_pmp_1_cfg_r, // @[core.scala:54:14]
input [29:0] io_ptw_tlb_pmp_1_addr, // @[core.scala:54:14]
input [31:0] io_ptw_tlb_pmp_1_mask, // @[core.scala:54:14]
input io_ptw_tlb_pmp_2_cfg_l, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_pmp_2_cfg_a, // @[core.scala:54:14]
input io_ptw_tlb_pmp_2_cfg_x, // @[core.scala:54:14]
input io_ptw_tlb_pmp_2_cfg_w, // @[core.scala:54:14]
input io_ptw_tlb_pmp_2_cfg_r, // @[core.scala:54:14]
input [29:0] io_ptw_tlb_pmp_2_addr, // @[core.scala:54:14]
input [31:0] io_ptw_tlb_pmp_2_mask, // @[core.scala:54:14]
input io_ptw_tlb_pmp_3_cfg_l, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_pmp_3_cfg_a, // @[core.scala:54:14]
input io_ptw_tlb_pmp_3_cfg_x, // @[core.scala:54:14]
input io_ptw_tlb_pmp_3_cfg_w, // @[core.scala:54:14]
input io_ptw_tlb_pmp_3_cfg_r, // @[core.scala:54:14]
input [29:0] io_ptw_tlb_pmp_3_addr, // @[core.scala:54:14]
input [31:0] io_ptw_tlb_pmp_3_mask, // @[core.scala:54:14]
input io_ptw_tlb_pmp_4_cfg_l, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_pmp_4_cfg_a, // @[core.scala:54:14]
input io_ptw_tlb_pmp_4_cfg_x, // @[core.scala:54:14]
input io_ptw_tlb_pmp_4_cfg_w, // @[core.scala:54:14]
input io_ptw_tlb_pmp_4_cfg_r, // @[core.scala:54:14]
input [29:0] io_ptw_tlb_pmp_4_addr, // @[core.scala:54:14]
input [31:0] io_ptw_tlb_pmp_4_mask, // @[core.scala:54:14]
input io_ptw_tlb_pmp_5_cfg_l, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_pmp_5_cfg_a, // @[core.scala:54:14]
input io_ptw_tlb_pmp_5_cfg_x, // @[core.scala:54:14]
input io_ptw_tlb_pmp_5_cfg_w, // @[core.scala:54:14]
input io_ptw_tlb_pmp_5_cfg_r, // @[core.scala:54:14]
input [29:0] io_ptw_tlb_pmp_5_addr, // @[core.scala:54:14]
input [31:0] io_ptw_tlb_pmp_5_mask, // @[core.scala:54:14]
input io_ptw_tlb_pmp_6_cfg_l, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_pmp_6_cfg_a, // @[core.scala:54:14]
input io_ptw_tlb_pmp_6_cfg_x, // @[core.scala:54:14]
input io_ptw_tlb_pmp_6_cfg_w, // @[core.scala:54:14]
input io_ptw_tlb_pmp_6_cfg_r, // @[core.scala:54:14]
input [29:0] io_ptw_tlb_pmp_6_addr, // @[core.scala:54:14]
input [31:0] io_ptw_tlb_pmp_6_mask, // @[core.scala:54:14]
input io_ptw_tlb_pmp_7_cfg_l, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_pmp_7_cfg_a, // @[core.scala:54:14]
input io_ptw_tlb_pmp_7_cfg_x, // @[core.scala:54:14]
input io_ptw_tlb_pmp_7_cfg_w, // @[core.scala:54:14]
input io_ptw_tlb_pmp_7_cfg_r, // @[core.scala:54:14]
input [29:0] io_ptw_tlb_pmp_7_addr, // @[core.scala:54:14]
input [31:0] io_ptw_tlb_pmp_7_mask, // @[core.scala:54:14]
output [63:0] io_trace_time, // @[core.scala:54:14]
output io_trace_custom_rob_empty // @[core.scala:54:14]
);
wire [3:0] dec_uops_0_ftq_idx; // @[core.scala:158:24]
wire io_ifu_sfence_bits_asid_0; // @[core.scala:51:7]
wire [38:0] io_ifu_sfence_bits_addr_0; // @[core.scala:51:7]
wire io_ifu_sfence_bits_rs2_0; // @[core.scala:51:7]
wire io_ifu_sfence_bits_rs1_0; // @[core.scala:51:7]
wire io_ifu_sfence_valid_0; // @[core.scala:51:7]
wire [63:0] _csr_io_rw_rdata; // @[core.scala:271:19]
wire _csr_io_decode_0_fp_illegal; // @[core.scala:271:19]
wire _csr_io_decode_0_fp_csr; // @[core.scala:271:19]
wire _csr_io_decode_0_read_illegal; // @[core.scala:271:19]
wire _csr_io_decode_0_write_illegal; // @[core.scala:271:19]
wire _csr_io_decode_0_write_flush; // @[core.scala:271:19]
wire _csr_io_decode_0_system_illegal; // @[core.scala:271:19]
wire _csr_io_decode_0_virtual_access_illegal; // @[core.scala:271:19]
wire _csr_io_decode_0_virtual_system_illegal; // @[core.scala:271:19]
wire _csr_io_csr_stall; // @[core.scala:271:19]
wire _csr_io_singleStep; // @[core.scala:271:19]
wire _csr_io_status_debug; // @[core.scala:271:19]
wire _csr_io_status_cease; // @[core.scala:271:19]
wire _csr_io_status_wfi; // @[core.scala:271:19]
wire [1:0] _csr_io_status_dprv; // @[core.scala:271:19]
wire _csr_io_status_dv; // @[core.scala:271:19]
wire [1:0] _csr_io_status_prv; // @[core.scala:271:19]
wire _csr_io_status_v; // @[core.scala:271:19]
wire _csr_io_status_sd; // @[core.scala:271:19]
wire _csr_io_status_mpv; // @[core.scala:271:19]
wire _csr_io_status_gva; // @[core.scala:271:19]
wire _csr_io_status_tsr; // @[core.scala:271:19]
wire _csr_io_status_tw; // @[core.scala:271:19]
wire _csr_io_status_tvm; // @[core.scala:271:19]
wire _csr_io_status_mxr; // @[core.scala:271:19]
wire _csr_io_status_sum; // @[core.scala:271:19]
wire _csr_io_status_mprv; // @[core.scala:271:19]
wire [1:0] _csr_io_status_fs; // @[core.scala:271:19]
wire [1:0] _csr_io_status_mpp; // @[core.scala:271:19]
wire _csr_io_status_spp; // @[core.scala:271:19]
wire _csr_io_status_mpie; // @[core.scala:271:19]
wire _csr_io_status_spie; // @[core.scala:271:19]
wire _csr_io_status_mie; // @[core.scala:271:19]
wire _csr_io_status_sie; // @[core.scala:271:19]
wire [39:0] _csr_io_evec; // @[core.scala:271:19]
wire [2:0] _csr_io_fcsr_rm; // @[core.scala:271:19]
wire _csr_io_interrupt; // @[core.scala:271:19]
wire [63:0] _csr_io_interrupt_cause; // @[core.scala:271:19]
wire [63:0] _csr_io_counters_0_eventSel; // @[core.scala:271:19]
wire [63:0] _csr_io_counters_1_eventSel; // @[core.scala:271:19]
wire [4:0] _rob_io_rob_head_idx; // @[core.scala:143:32]
wire _rob_io_commit_valids_0; // @[core.scala:143:32]
wire _rob_io_commit_arch_valids_0; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_0_uopc; // @[core.scala:143:32]
wire [31:0] _rob_io_commit_uops_0_inst; // @[core.scala:143:32]
wire [31:0] _rob_io_commit_uops_0_debug_inst; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_is_rvc; // @[core.scala:143:32]
wire [39:0] _rob_io_commit_uops_0_debug_pc; // @[core.scala:143:32]
wire [2:0] _rob_io_commit_uops_0_iq_type; // @[core.scala:143:32]
wire [9:0] _rob_io_commit_uops_0_fu_code; // @[core.scala:143:32]
wire [3:0] _rob_io_commit_uops_0_ctrl_br_type; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_0_ctrl_op1_sel; // @[core.scala:143:32]
wire [2:0] _rob_io_commit_uops_0_ctrl_op2_sel; // @[core.scala:143:32]
wire [2:0] _rob_io_commit_uops_0_ctrl_imm_sel; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_0_ctrl_op_fcn; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_ctrl_fcn_dw; // @[core.scala:143:32]
wire [2:0] _rob_io_commit_uops_0_ctrl_csr_cmd; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_ctrl_is_load; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_ctrl_is_sta; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_ctrl_is_std; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_0_iw_state; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_iw_p1_poisoned; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_iw_p2_poisoned; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_is_br; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_is_jalr; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_is_jal; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_is_sfb; // @[core.scala:143:32]
wire [7:0] _rob_io_commit_uops_0_br_mask; // @[core.scala:143:32]
wire [2:0] _rob_io_commit_uops_0_br_tag; // @[core.scala:143:32]
wire [3:0] _rob_io_commit_uops_0_ftq_idx; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_edge_inst; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_0_pc_lob; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_taken; // @[core.scala:143:32]
wire [19:0] _rob_io_commit_uops_0_imm_packed; // @[core.scala:143:32]
wire [11:0] _rob_io_commit_uops_0_csr_addr; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_0_rob_idx; // @[core.scala:143:32]
wire [2:0] _rob_io_commit_uops_0_ldq_idx; // @[core.scala:143:32]
wire [2:0] _rob_io_commit_uops_0_stq_idx; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_0_rxq_idx; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_0_pdst; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_0_prs1; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_0_prs2; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_0_prs3; // @[core.scala:143:32]
wire [3:0] _rob_io_commit_uops_0_ppred; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_prs1_busy; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_prs2_busy; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_prs3_busy; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_ppred_busy; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_0_stale_pdst; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_exception; // @[core.scala:143:32]
wire [63:0] _rob_io_commit_uops_0_exc_cause; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_bypassable; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_0_mem_cmd; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_0_mem_size; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_mem_signed; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_is_fence; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_is_fencei; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_is_amo; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_uses_ldq; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_uses_stq; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_is_sys_pc2epc; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_is_unique; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_flush_on_commit; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_ldst_is_rs1; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_0_ldst; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_0_lrs1; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_0_lrs2; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_0_lrs3; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_ldst_val; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_0_dst_rtype; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_0_lrs1_rtype; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_0_lrs2_rtype; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_frs3_en; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_fp_val; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_fp_single; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_xcpt_pf_if; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_xcpt_ae_if; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_xcpt_ma_if; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_bp_debug_if; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_bp_xcpt_if; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_0_debug_fsrc; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_0_debug_tsrc; // @[core.scala:143:32]
wire _rob_io_commit_fflags_valid; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_fflags_bits; // @[core.scala:143:32]
wire _rob_io_commit_rbk_valids_0; // @[core.scala:143:32]
wire _rob_io_commit_rollback; // @[core.scala:143:32]
wire _rob_io_com_xcpt_valid; // @[core.scala:143:32]
wire [3:0] _rob_io_com_xcpt_bits_ftq_idx; // @[core.scala:143:32]
wire _rob_io_com_xcpt_bits_edge_inst; // @[core.scala:143:32]
wire [5:0] _rob_io_com_xcpt_bits_pc_lob; // @[core.scala:143:32]
wire [63:0] _rob_io_com_xcpt_bits_cause; // @[core.scala:143:32]
wire [63:0] _rob_io_com_xcpt_bits_badvaddr; // @[core.scala:143:32]
wire _rob_io_flush_valid; // @[core.scala:143:32]
wire [3:0] _rob_io_flush_bits_ftq_idx; // @[core.scala:143:32]
wire _rob_io_flush_bits_edge_inst; // @[core.scala:143:32]
wire _rob_io_flush_bits_is_rvc; // @[core.scala:143:32]
wire [5:0] _rob_io_flush_bits_pc_lob; // @[core.scala:143:32]
wire [2:0] _rob_io_flush_bits_flush_typ; // @[core.scala:143:32]
wire _rob_io_empty; // @[core.scala:143:32]
wire _rob_io_ready; // @[core.scala:143:32]
wire _rob_io_flush_frontend; // @[core.scala:143:32]
wire [5:0] _iregister_read_io_rf_read_ports_0_addr; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_rf_read_ports_1_addr; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_rf_read_ports_2_addr; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_rf_read_ports_3_addr; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_valid; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_uopc; // @[core.scala:135:32]
wire [31:0] _iregister_read_io_exe_reqs_0_bits_uop_inst; // @[core.scala:135:32]
wire [31:0] _iregister_read_io_exe_reqs_0_bits_uop_debug_inst; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_is_rvc; // @[core.scala:135:32]
wire [39:0] _iregister_read_io_exe_reqs_0_bits_uop_debug_pc; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_iq_type; // @[core.scala:135:32]
wire [9:0] _iregister_read_io_exe_reqs_0_bits_uop_fu_code; // @[core.scala:135:32]
wire [3:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_br_type; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_op1_sel; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_op2_sel; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_imm_sel; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_op_fcn; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_ctrl_fcn_dw; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_csr_cmd; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_ctrl_is_load; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_ctrl_is_sta; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_ctrl_is_std; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_iw_state; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_iw_p1_poisoned; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_iw_p2_poisoned; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_is_br; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_is_jalr; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_is_jal; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_is_sfb; // @[core.scala:135:32]
wire [7:0] _iregister_read_io_exe_reqs_0_bits_uop_br_mask; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_br_tag; // @[core.scala:135:32]
wire [3:0] _iregister_read_io_exe_reqs_0_bits_uop_ftq_idx; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_edge_inst; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_pc_lob; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_taken; // @[core.scala:135:32]
wire [19:0] _iregister_read_io_exe_reqs_0_bits_uop_imm_packed; // @[core.scala:135:32]
wire [11:0] _iregister_read_io_exe_reqs_0_bits_uop_csr_addr; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_rob_idx; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_ldq_idx; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_stq_idx; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_rxq_idx; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_pdst; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_prs1; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_prs2; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_prs3; // @[core.scala:135:32]
wire [3:0] _iregister_read_io_exe_reqs_0_bits_uop_ppred; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_prs1_busy; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_prs2_busy; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_prs3_busy; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_ppred_busy; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_stale_pdst; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_exception; // @[core.scala:135:32]
wire [63:0] _iregister_read_io_exe_reqs_0_bits_uop_exc_cause; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_bypassable; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_mem_cmd; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_mem_size; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_mem_signed; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_is_fence; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_is_fencei; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_is_amo; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_uses_ldq; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_uses_stq; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_is_sys_pc2epc; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_is_unique; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_flush_on_commit; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_ldst_is_rs1; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_ldst; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs1; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs2; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs3; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_ldst_val; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_dst_rtype; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs1_rtype; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs2_rtype; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_frs3_en; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_fp_val; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_fp_single; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_xcpt_pf_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_xcpt_ae_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_xcpt_ma_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_bp_debug_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_bp_xcpt_if; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_debug_fsrc; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_debug_tsrc; // @[core.scala:135:32]
wire [63:0] _iregister_read_io_exe_reqs_0_bits_rs1_data; // @[core.scala:135:32]
wire [63:0] _iregister_read_io_exe_reqs_0_bits_rs2_data; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_valid; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_uopc; // @[core.scala:135:32]
wire [31:0] _iregister_read_io_exe_reqs_1_bits_uop_inst; // @[core.scala:135:32]
wire [31:0] _iregister_read_io_exe_reqs_1_bits_uop_debug_inst; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_is_rvc; // @[core.scala:135:32]
wire [39:0] _iregister_read_io_exe_reqs_1_bits_uop_debug_pc; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_iq_type; // @[core.scala:135:32]
wire [9:0] _iregister_read_io_exe_reqs_1_bits_uop_fu_code; // @[core.scala:135:32]
wire [3:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_br_type; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_op1_sel; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_op2_sel; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_imm_sel; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_op_fcn; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_ctrl_fcn_dw; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_csr_cmd; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_ctrl_is_load; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_ctrl_is_sta; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_ctrl_is_std; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_iw_state; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_iw_p1_poisoned; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_iw_p2_poisoned; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_is_br; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_is_jalr; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_is_jal; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_is_sfb; // @[core.scala:135:32]
wire [7:0] _iregister_read_io_exe_reqs_1_bits_uop_br_mask; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_br_tag; // @[core.scala:135:32]
wire [3:0] _iregister_read_io_exe_reqs_1_bits_uop_ftq_idx; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_edge_inst; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_pc_lob; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_taken; // @[core.scala:135:32]
wire [19:0] _iregister_read_io_exe_reqs_1_bits_uop_imm_packed; // @[core.scala:135:32]
wire [11:0] _iregister_read_io_exe_reqs_1_bits_uop_csr_addr; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_rob_idx; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_ldq_idx; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_stq_idx; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_rxq_idx; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_pdst; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_prs1; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_prs2; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_prs3; // @[core.scala:135:32]
wire [3:0] _iregister_read_io_exe_reqs_1_bits_uop_ppred; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_prs1_busy; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_prs2_busy; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_prs3_busy; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_ppred_busy; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_stale_pdst; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_exception; // @[core.scala:135:32]
wire [63:0] _iregister_read_io_exe_reqs_1_bits_uop_exc_cause; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_bypassable; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_mem_cmd; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_mem_size; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_mem_signed; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_is_fence; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_is_fencei; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_is_amo; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_uses_ldq; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_uses_stq; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_is_sys_pc2epc; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_is_unique; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_flush_on_commit; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_ldst_is_rs1; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_ldst; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs1; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs2; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs3; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_ldst_val; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_dst_rtype; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs1_rtype; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs2_rtype; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_frs3_en; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_fp_val; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_fp_single; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_xcpt_pf_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_xcpt_ae_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_xcpt_ma_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_bp_debug_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_bp_xcpt_if; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_debug_fsrc; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_debug_tsrc; // @[core.scala:135:32]
wire [63:0] _iregister_read_io_exe_reqs_1_bits_rs1_data; // @[core.scala:135:32]
wire [63:0] _iregister_read_io_exe_reqs_1_bits_rs2_data; // @[core.scala:135:32]
wire _ll_wbarb_io_in_1_ready; // @[core.scala:132:32]
wire _ll_wbarb_io_out_valid; // @[core.scala:132:32]
wire [6:0] _ll_wbarb_io_out_bits_uop_uopc; // @[core.scala:132:32]
wire [31:0] _ll_wbarb_io_out_bits_uop_inst; // @[core.scala:132:32]
wire [31:0] _ll_wbarb_io_out_bits_uop_debug_inst; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_is_rvc; // @[core.scala:132:32]
wire [39:0] _ll_wbarb_io_out_bits_uop_debug_pc; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_uop_iq_type; // @[core.scala:132:32]
wire [9:0] _ll_wbarb_io_out_bits_uop_fu_code; // @[core.scala:132:32]
wire [3:0] _ll_wbarb_io_out_bits_uop_ctrl_br_type; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_uop_ctrl_op1_sel; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_uop_ctrl_op2_sel; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_uop_ctrl_imm_sel; // @[core.scala:132:32]
wire [4:0] _ll_wbarb_io_out_bits_uop_ctrl_op_fcn; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_ctrl_fcn_dw; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_uop_ctrl_csr_cmd; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_ctrl_is_load; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_ctrl_is_sta; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_ctrl_is_std; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_uop_iw_state; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_iw_p1_poisoned; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_iw_p2_poisoned; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_is_br; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_is_jalr; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_is_jal; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_is_sfb; // @[core.scala:132:32]
wire [7:0] _ll_wbarb_io_out_bits_uop_br_mask; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_uop_br_tag; // @[core.scala:132:32]
wire [3:0] _ll_wbarb_io_out_bits_uop_ftq_idx; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_edge_inst; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_uop_pc_lob; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_taken; // @[core.scala:132:32]
wire [19:0] _ll_wbarb_io_out_bits_uop_imm_packed; // @[core.scala:132:32]
wire [11:0] _ll_wbarb_io_out_bits_uop_csr_addr; // @[core.scala:132:32]
wire [4:0] _ll_wbarb_io_out_bits_uop_rob_idx; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_uop_ldq_idx; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_uop_stq_idx; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_uop_rxq_idx; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_uop_pdst; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_uop_prs1; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_uop_prs2; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_uop_prs3; // @[core.scala:132:32]
wire [3:0] _ll_wbarb_io_out_bits_uop_ppred; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_prs1_busy; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_prs2_busy; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_prs3_busy; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_ppred_busy; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_uop_stale_pdst; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_exception; // @[core.scala:132:32]
wire [63:0] _ll_wbarb_io_out_bits_uop_exc_cause; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_bypassable; // @[core.scala:132:32]
wire [4:0] _ll_wbarb_io_out_bits_uop_mem_cmd; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_uop_mem_size; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_mem_signed; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_is_fence; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_is_fencei; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_is_amo; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_uses_ldq; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_uses_stq; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_is_sys_pc2epc; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_is_unique; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_flush_on_commit; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_ldst_is_rs1; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_uop_ldst; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_uop_lrs1; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_uop_lrs2; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_uop_lrs3; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_ldst_val; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_uop_dst_rtype; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_uop_lrs1_rtype; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_uop_lrs2_rtype; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_frs3_en; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_fp_val; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_fp_single; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_xcpt_pf_if; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_xcpt_ae_if; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_xcpt_ma_if; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_bp_debug_if; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_bp_xcpt_if; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_uop_debug_fsrc; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_uop_debug_tsrc; // @[core.scala:132:32]
wire [63:0] _ll_wbarb_io_out_bits_data; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_predicated; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_valid; // @[core.scala:132:32]
wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_uopc; // @[core.scala:132:32]
wire [31:0] _ll_wbarb_io_out_bits_fflags_bits_uop_inst; // @[core.scala:132:32]
wire [31:0] _ll_wbarb_io_out_bits_fflags_bits_uop_debug_inst; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_rvc; // @[core.scala:132:32]
wire [39:0] _ll_wbarb_io_out_bits_fflags_bits_uop_debug_pc; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_iq_type; // @[core.scala:132:32]
wire [9:0] _ll_wbarb_io_out_bits_fflags_bits_uop_fu_code; // @[core.scala:132:32]
wire [3:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:132:32]
wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_iw_state; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_br; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_jalr; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_jal; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_sfb; // @[core.scala:132:32]
wire [7:0] _ll_wbarb_io_out_bits_fflags_bits_uop_br_mask; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_br_tag; // @[core.scala:132:32]
wire [3:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ftq_idx; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_edge_inst; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_pc_lob; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_taken; // @[core.scala:132:32]
wire [19:0] _ll_wbarb_io_out_bits_fflags_bits_uop_imm_packed; // @[core.scala:132:32]
wire [11:0] _ll_wbarb_io_out_bits_fflags_bits_uop_csr_addr; // @[core.scala:132:32]
wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_rob_idx; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ldq_idx; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_stq_idx; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_rxq_idx; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_pdst; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_prs1; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_prs2; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_prs3; // @[core.scala:132:32]
wire [3:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ppred; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_prs1_busy; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_prs2_busy; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_prs3_busy; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_ppred_busy; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_stale_pdst; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_exception; // @[core.scala:132:32]
wire [63:0] _ll_wbarb_io_out_bits_fflags_bits_uop_exc_cause; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_bypassable; // @[core.scala:132:32]
wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_mem_cmd; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_mem_size; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_mem_signed; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_fence; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_fencei; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_amo; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_uses_ldq; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_uses_stq; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_unique; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ldst; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs1; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs2; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs3; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_ldst_val; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_dst_rtype; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_frs3_en; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_fp_val; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_fp_single; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:132:32]
wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_flags; // @[core.scala:132:32]
wire [63:0] _iregfile_io_read_ports_0_data; // @[core.scala:116:32]
wire [63:0] _iregfile_io_read_ports_1_data; // @[core.scala:116:32]
wire [63:0] _iregfile_io_read_ports_2_data; // @[core.scala:116:32]
wire [63:0] _iregfile_io_read_ports_3_data; // @[core.scala:116:32]
wire _dispatcher_io_ren_uops_0_ready; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_valid; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_0_bits_uopc; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_2_0_bits_inst; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_2_0_bits_debug_inst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_is_rvc; // @[core.scala:114:32]
wire [39:0] _dispatcher_io_dis_uops_2_0_bits_debug_pc; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_2_0_bits_iq_type; // @[core.scala:114:32]
wire [9:0] _dispatcher_io_dis_uops_2_0_bits_fu_code; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_br_type; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_op1_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_op2_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_imm_sel; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_op_fcn; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_ctrl_fcn_dw; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_csr_cmd; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_ctrl_is_load; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_ctrl_is_sta; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_ctrl_is_std; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_0_bits_iw_state; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_iw_p1_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_iw_p2_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_is_br; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_is_jalr; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_is_jal; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_is_sfb; // @[core.scala:114:32]
wire [7:0] _dispatcher_io_dis_uops_2_0_bits_br_mask; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_2_0_bits_br_tag; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_2_0_bits_ftq_idx; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_edge_inst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_0_bits_pc_lob; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_taken; // @[core.scala:114:32]
wire [19:0] _dispatcher_io_dis_uops_2_0_bits_imm_packed; // @[core.scala:114:32]
wire [11:0] _dispatcher_io_dis_uops_2_0_bits_csr_addr; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_2_0_bits_rob_idx; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_2_0_bits_ldq_idx; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_2_0_bits_stq_idx; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_0_bits_rxq_idx; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_0_bits_pdst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_0_bits_prs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_0_bits_prs2; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_0_bits_prs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_prs1_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_prs2_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_prs3_busy; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_0_bits_stale_pdst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_exception; // @[core.scala:114:32]
wire [63:0] _dispatcher_io_dis_uops_2_0_bits_exc_cause; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_bypassable; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_2_0_bits_mem_cmd; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_0_bits_mem_size; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_mem_signed; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_is_fence; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_is_fencei; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_is_amo; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_uses_ldq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_uses_stq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_is_sys_pc2epc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_is_unique; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_flush_on_commit; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_ldst_is_rs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_0_bits_ldst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_0_bits_lrs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_0_bits_lrs2; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_0_bits_lrs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_ldst_val; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_0_bits_dst_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_0_bits_lrs1_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_0_bits_lrs2_rtype; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_frs3_en; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_fp_val; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_fp_single; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_xcpt_pf_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_xcpt_ae_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_xcpt_ma_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_bp_debug_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_bp_xcpt_if; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_0_bits_debug_fsrc; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_0_bits_debug_tsrc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_valid; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_0_bits_uopc; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_1_0_bits_inst; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_1_0_bits_debug_inst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_is_rvc; // @[core.scala:114:32]
wire [39:0] _dispatcher_io_dis_uops_1_0_bits_debug_pc; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_1_0_bits_iq_type; // @[core.scala:114:32]
wire [9:0] _dispatcher_io_dis_uops_1_0_bits_fu_code; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_br_type; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_op1_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_op2_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_imm_sel; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_op_fcn; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_ctrl_fcn_dw; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_csr_cmd; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_ctrl_is_load; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_ctrl_is_sta; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_ctrl_is_std; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_0_bits_iw_state; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_iw_p1_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_iw_p2_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_is_br; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_is_jalr; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_is_jal; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_is_sfb; // @[core.scala:114:32]
wire [7:0] _dispatcher_io_dis_uops_1_0_bits_br_mask; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_1_0_bits_br_tag; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_1_0_bits_ftq_idx; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_edge_inst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_0_bits_pc_lob; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_taken; // @[core.scala:114:32]
wire [19:0] _dispatcher_io_dis_uops_1_0_bits_imm_packed; // @[core.scala:114:32]
wire [11:0] _dispatcher_io_dis_uops_1_0_bits_csr_addr; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_1_0_bits_rob_idx; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_1_0_bits_ldq_idx; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_1_0_bits_stq_idx; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_0_bits_rxq_idx; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_0_bits_pdst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_0_bits_prs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_0_bits_prs2; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_0_bits_prs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_prs1_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_prs2_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_prs3_busy; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_0_bits_stale_pdst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_exception; // @[core.scala:114:32]
wire [63:0] _dispatcher_io_dis_uops_1_0_bits_exc_cause; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_bypassable; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_1_0_bits_mem_cmd; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_0_bits_mem_size; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_mem_signed; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_is_fence; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_is_fencei; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_is_amo; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_uses_ldq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_uses_stq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_is_sys_pc2epc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_is_unique; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_flush_on_commit; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_ldst_is_rs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_0_bits_ldst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_0_bits_lrs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_0_bits_lrs2; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_0_bits_lrs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_ldst_val; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_0_bits_dst_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_0_bits_lrs1_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_0_bits_lrs2_rtype; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_frs3_en; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_fp_val; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_fp_single; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_xcpt_pf_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_xcpt_ae_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_xcpt_ma_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_bp_debug_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_bp_xcpt_if; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_0_bits_debug_fsrc; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_0_bits_debug_tsrc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_valid; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_0_bits_uopc; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_0_0_bits_inst; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_0_0_bits_debug_inst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_is_rvc; // @[core.scala:114:32]
wire [39:0] _dispatcher_io_dis_uops_0_0_bits_debug_pc; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_0_0_bits_iq_type; // @[core.scala:114:32]
wire [9:0] _dispatcher_io_dis_uops_0_0_bits_fu_code; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_br_type; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_op1_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_op2_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_imm_sel; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_op_fcn; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_ctrl_fcn_dw; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_csr_cmd; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_ctrl_is_load; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_ctrl_is_sta; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_ctrl_is_std; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_0_bits_iw_state; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_iw_p1_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_iw_p2_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_is_br; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_is_jalr; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_is_jal; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_is_sfb; // @[core.scala:114:32]
wire [7:0] _dispatcher_io_dis_uops_0_0_bits_br_mask; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_0_0_bits_br_tag; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_0_0_bits_ftq_idx; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_edge_inst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_0_bits_pc_lob; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_taken; // @[core.scala:114:32]
wire [19:0] _dispatcher_io_dis_uops_0_0_bits_imm_packed; // @[core.scala:114:32]
wire [11:0] _dispatcher_io_dis_uops_0_0_bits_csr_addr; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_0_0_bits_rob_idx; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_0_0_bits_ldq_idx; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_0_0_bits_stq_idx; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_0_bits_rxq_idx; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_0_bits_pdst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_0_bits_prs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_0_bits_prs2; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_0_bits_prs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_prs1_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_prs2_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_prs3_busy; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_0_bits_stale_pdst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_exception; // @[core.scala:114:32]
wire [63:0] _dispatcher_io_dis_uops_0_0_bits_exc_cause; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_bypassable; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_0_0_bits_mem_cmd; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_0_bits_mem_size; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_mem_signed; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_is_fence; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_is_fencei; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_is_amo; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_uses_ldq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_uses_stq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_is_sys_pc2epc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_is_unique; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_flush_on_commit; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_ldst_is_rs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_0_bits_ldst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_0_bits_lrs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_0_bits_lrs2; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_0_bits_lrs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_ldst_val; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_0_bits_dst_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_0_bits_lrs1_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_0_bits_lrs2_rtype; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_frs3_en; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_fp_val; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_fp_single; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_xcpt_pf_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_xcpt_ae_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_xcpt_ma_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_bp_debug_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_bp_xcpt_if; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_0_bits_debug_fsrc; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_0_bits_debug_tsrc; // @[core.scala:114:32]
wire _int_issue_unit_io_dis_uops_0_ready; // @[core.scala:110:32]
wire _mem_issue_unit_io_dis_uops_0_ready; // @[core.scala:108:32]
wire _mem_issue_unit_io_iss_valids_0; // @[core.scala:108:32]
wire _mem_issue_unit_io_iss_uops_0_uses_ldq; // @[core.scala:108:32]
wire _fp_rename_stage_io_ren_stalls_0; // @[core.scala:104:46]
wire [5:0] _fp_rename_stage_io_ren2_uops_0_pdst; // @[core.scala:104:46]
wire [5:0] _fp_rename_stage_io_ren2_uops_0_prs1; // @[core.scala:104:46]
wire [5:0] _fp_rename_stage_io_ren2_uops_0_prs2; // @[core.scala:104:46]
wire _fp_rename_stage_io_ren2_uops_0_prs1_busy; // @[core.scala:104:46]
wire _fp_rename_stage_io_ren2_uops_0_prs2_busy; // @[core.scala:104:46]
wire _fp_rename_stage_io_ren2_uops_0_prs3_busy; // @[core.scala:104:46]
wire [5:0] _fp_rename_stage_io_ren2_uops_0_stale_pdst; // @[core.scala:104:46]
wire _rename_stage_io_ren_stalls_0; // @[core.scala:103:32]
wire [5:0] _rename_stage_io_ren2_uops_0_pdst; // @[core.scala:103:32]
wire [5:0] _rename_stage_io_ren2_uops_0_prs1; // @[core.scala:103:32]
wire [5:0] _rename_stage_io_ren2_uops_0_prs2; // @[core.scala:103:32]
wire _rename_stage_io_ren2_uops_0_prs1_busy; // @[core.scala:103:32]
wire _rename_stage_io_ren2_uops_0_prs2_busy; // @[core.scala:103:32]
wire [5:0] _rename_stage_io_ren2_uops_0_stale_pdst; // @[core.scala:103:32]
wire [31:0] _decode_units_0_io_csr_decode_inst; // @[core.scala:101:79]
wire _FpPipeline_io_dis_uops_0_ready; // @[core.scala:80:37]
wire _FpPipeline_io_from_int_ready; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_valid; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_to_int_bits_uop_uopc; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_to_int_bits_uop_inst; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_to_int_bits_uop_debug_inst; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_is_rvc; // @[core.scala:80:37]
wire [39:0] _FpPipeline_io_to_int_bits_uop_debug_pc; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_uop_iq_type; // @[core.scala:80:37]
wire [9:0] _FpPipeline_io_to_int_bits_uop_fu_code; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_to_int_bits_uop_ctrl_br_type; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_uop_ctrl_op1_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_uop_ctrl_op2_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_uop_ctrl_imm_sel; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_to_int_bits_uop_ctrl_op_fcn; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_ctrl_is_load; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_ctrl_is_sta; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_ctrl_is_std; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_uop_iw_state; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_iw_p1_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_iw_p2_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_is_br; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_is_jalr; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_is_jal; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_is_sfb; // @[core.scala:80:37]
wire [7:0] _FpPipeline_io_to_int_bits_uop_br_mask; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_uop_br_tag; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_to_int_bits_uop_ftq_idx; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_edge_inst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_uop_pc_lob; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_taken; // @[core.scala:80:37]
wire [19:0] _FpPipeline_io_to_int_bits_uop_imm_packed; // @[core.scala:80:37]
wire [11:0] _FpPipeline_io_to_int_bits_uop_csr_addr; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_to_int_bits_uop_rob_idx; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_uop_ldq_idx; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_uop_stq_idx; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_uop_rxq_idx; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_uop_pdst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_uop_prs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_uop_prs2; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_uop_prs3; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_to_int_bits_uop_ppred; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_prs1_busy; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_prs2_busy; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_prs3_busy; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_ppred_busy; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_uop_stale_pdst; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_exception; // @[core.scala:80:37]
wire [63:0] _FpPipeline_io_to_int_bits_uop_exc_cause; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_bypassable; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_to_int_bits_uop_mem_cmd; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_uop_mem_size; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_mem_signed; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_is_fence; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_is_fencei; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_is_amo; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_uses_ldq; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_uses_stq; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_is_sys_pc2epc; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_is_unique; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_flush_on_commit; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_ldst_is_rs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_uop_ldst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_uop_lrs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_uop_lrs2; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_uop_lrs3; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_ldst_val; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_uop_dst_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_uop_lrs1_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_uop_lrs2_rtype; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_frs3_en; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_fp_val; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_fp_single; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_xcpt_pf_if; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_xcpt_ae_if; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_xcpt_ma_if; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_bp_debug_if; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_bp_xcpt_if; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_uop_debug_fsrc; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_uop_debug_tsrc; // @[core.scala:80:37]
wire [63:0] _FpPipeline_io_to_int_bits_data; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_predicated; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_valid; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_uopc; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_inst; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_debug_inst; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_rvc; // @[core.scala:80:37]
wire [39:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_debug_pc; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_iq_type; // @[core.scala:80:37]
wire [9:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_fu_code; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_iw_state; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_br; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_jalr; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_jal; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_sfb; // @[core.scala:80:37]
wire [7:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_br_mask; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_br_tag; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ftq_idx; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_edge_inst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_pc_lob; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_taken; // @[core.scala:80:37]
wire [19:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_imm_packed; // @[core.scala:80:37]
wire [11:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_csr_addr; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_rob_idx; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ldq_idx; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_stq_idx; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_rxq_idx; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_pdst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_prs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_prs2; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_prs3; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ppred; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_prs1_busy; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_prs2_busy; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_prs3_busy; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ppred_busy; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_stale_pdst; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_exception; // @[core.scala:80:37]
wire [63:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_exc_cause; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_bypassable; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_mem_cmd; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_mem_size; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_mem_signed; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_fence; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_fencei; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_amo; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_uses_ldq; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_uses_stq; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_unique; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ldst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs2; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs3; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ldst_val; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_dst_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_frs3_en; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_fp_val; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_fp_single; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_flags; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_valid; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_uopc; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_wakeups_0_bits_uop_inst; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_wakeups_0_bits_uop_debug_inst; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_is_rvc; // @[core.scala:80:37]
wire [39:0] _FpPipeline_io_wakeups_0_bits_uop_debug_pc; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_iq_type; // @[core.scala:80:37]
wire [9:0] _FpPipeline_io_wakeups_0_bits_uop_fu_code; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_br_type; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_op1_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_op2_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_imm_sel; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_op_fcn; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_ctrl_is_load; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_ctrl_is_sta; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_ctrl_is_std; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_iw_state; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_iw_p1_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_iw_p2_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_is_br; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_is_jalr; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_is_jal; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_is_sfb; // @[core.scala:80:37]
wire [7:0] _FpPipeline_io_wakeups_0_bits_uop_br_mask; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_br_tag; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_wakeups_0_bits_uop_ftq_idx; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_edge_inst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_pc_lob; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_taken; // @[core.scala:80:37]
wire [19:0] _FpPipeline_io_wakeups_0_bits_uop_imm_packed; // @[core.scala:80:37]
wire [11:0] _FpPipeline_io_wakeups_0_bits_uop_csr_addr; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_rob_idx; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_ldq_idx; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_stq_idx; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_rxq_idx; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_pdst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_prs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_prs2; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_prs3; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_wakeups_0_bits_uop_ppred; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_prs1_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_prs2_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_prs3_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_ppred_busy; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_stale_pdst; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_exception; // @[core.scala:80:37]
wire [63:0] _FpPipeline_io_wakeups_0_bits_uop_exc_cause; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_bypassable; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_mem_cmd; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_mem_size; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_mem_signed; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_is_fence; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_is_fencei; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_is_amo; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_uses_ldq; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_uses_stq; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_is_sys_pc2epc; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_is_unique; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_flush_on_commit; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_ldst_is_rs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_ldst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_lrs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_lrs2; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_lrs3; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_ldst_val; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_dst_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_lrs1_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_lrs2_rtype; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_frs3_en; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_fp_val; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_fp_single; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_xcpt_pf_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_xcpt_ae_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_xcpt_ma_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_bp_debug_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_bp_xcpt_if; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_debug_fsrc; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_debug_tsrc; // @[core.scala:80:37]
wire [64:0] _FpPipeline_io_wakeups_0_bits_data; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_predicated; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_valid; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_uopc; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_inst; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_debug_inst; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_rvc; // @[core.scala:80:37]
wire [39:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_debug_pc; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_iq_type; // @[core.scala:80:37]
wire [9:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_fu_code; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_iw_state; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_br; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_jalr; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_jal; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_sfb; // @[core.scala:80:37]
wire [7:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_br_mask; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_br_tag; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ftq_idx; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_edge_inst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_pc_lob; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_taken; // @[core.scala:80:37]
wire [19:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_imm_packed; // @[core.scala:80:37]
wire [11:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_csr_addr; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_rob_idx; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ldq_idx; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_stq_idx; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_rxq_idx; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_pdst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs2; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs3; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ppred; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs1_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs2_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs3_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ppred_busy; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_stale_pdst; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_exception; // @[core.scala:80:37]
wire [63:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_exc_cause; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_bypassable; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_mem_cmd; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_mem_size; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_mem_signed; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_fence; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_fencei; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_amo; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_uses_ldq; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_uses_stq; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_unique; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ldst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs2; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs3; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ldst_val; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_dst_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_frs3_en; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_fp_val; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_fp_single; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_flags; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_valid; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_uopc; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_wakeups_1_bits_uop_inst; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_wakeups_1_bits_uop_debug_inst; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_is_rvc; // @[core.scala:80:37]
wire [39:0] _FpPipeline_io_wakeups_1_bits_uop_debug_pc; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_iq_type; // @[core.scala:80:37]
wire [9:0] _FpPipeline_io_wakeups_1_bits_uop_fu_code; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_br_type; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_op1_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_op2_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_imm_sel; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_op_fcn; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_ctrl_is_load; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_ctrl_is_sta; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_ctrl_is_std; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_iw_state; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_iw_p1_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_iw_p2_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_is_br; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_is_jalr; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_is_jal; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_is_sfb; // @[core.scala:80:37]
wire [7:0] _FpPipeline_io_wakeups_1_bits_uop_br_mask; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_br_tag; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_wakeups_1_bits_uop_ftq_idx; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_edge_inst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_pc_lob; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_taken; // @[core.scala:80:37]
wire [19:0] _FpPipeline_io_wakeups_1_bits_uop_imm_packed; // @[core.scala:80:37]
wire [11:0] _FpPipeline_io_wakeups_1_bits_uop_csr_addr; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_rob_idx; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_ldq_idx; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_stq_idx; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_rxq_idx; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_pdst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_prs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_prs2; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_prs3; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_wakeups_1_bits_uop_ppred; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_prs1_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_prs2_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_prs3_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_ppred_busy; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_stale_pdst; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_exception; // @[core.scala:80:37]
wire [63:0] _FpPipeline_io_wakeups_1_bits_uop_exc_cause; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_bypassable; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_mem_cmd; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_mem_size; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_mem_signed; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_is_fence; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_is_fencei; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_is_amo; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_uses_ldq; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_uses_stq; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_is_sys_pc2epc; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_is_unique; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_flush_on_commit; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_ldst_is_rs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_ldst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_lrs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_lrs2; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_lrs3; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_ldst_val; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_dst_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_lrs1_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_lrs2_rtype; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_frs3_en; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_fp_val; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_fp_single; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_xcpt_pf_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_xcpt_ae_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_xcpt_ma_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_bp_debug_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_bp_xcpt_if; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_debug_fsrc; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_debug_tsrc; // @[core.scala:80:37]
wire [64:0] _FpPipeline_io_wakeups_1_bits_data; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_valid; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_uopc; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_inst; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_debug_inst; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_rvc; // @[core.scala:80:37]
wire [39:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_debug_pc; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_iq_type; // @[core.scala:80:37]
wire [9:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_fu_code; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_iw_state; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_br; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_jalr; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_jal; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_sfb; // @[core.scala:80:37]
wire [7:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_br_mask; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_br_tag; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ftq_idx; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_edge_inst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_pc_lob; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_taken; // @[core.scala:80:37]
wire [19:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_imm_packed; // @[core.scala:80:37]
wire [11:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_csr_addr; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_rob_idx; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ldq_idx; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_stq_idx; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_rxq_idx; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_pdst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs2; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs3; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ppred; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs1_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs2_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs3_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ppred_busy; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_stale_pdst; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_exception; // @[core.scala:80:37]
wire [63:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_exc_cause; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_bypassable; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_mem_cmd; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_mem_size; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_mem_signed; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_fence; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_fencei; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_amo; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_uses_ldq; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_uses_stq; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_unique; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ldst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs2; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs3; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ldst_val; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_dst_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_frs3_en; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_fp_val; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_fp_single; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_flags; // @[core.scala:80:37]
wire [64:0] _FpPipeline_io_debug_wb_wdata_0; // @[core.scala:80:37]
wire [64:0] _FpPipeline_io_debug_wb_wdata_1; // @[core.scala:80:37]
wire [9:0] _alu_exe_unit_io_fu_types; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_valid; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_iresp_bits_uop_uopc; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_io_iresp_bits_uop_inst; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_io_iresp_bits_uop_debug_inst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_is_rvc; // @[execution-units.scala:119:32]
wire [39:0] _alu_exe_unit_io_iresp_bits_uop_debug_pc; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_iresp_bits_uop_iq_type; // @[execution-units.scala:119:32]
wire [9:0] _alu_exe_unit_io_iresp_bits_uop_fu_code; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_iresp_bits_uop_iw_state; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_is_br; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_is_jalr; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_is_jal; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_is_sfb; // @[execution-units.scala:119:32]
wire [7:0] _alu_exe_unit_io_iresp_bits_uop_br_mask; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_iresp_bits_uop_br_tag; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_iresp_bits_uop_ftq_idx; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_edge_inst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_iresp_bits_uop_pc_lob; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_taken; // @[execution-units.scala:119:32]
wire [19:0] _alu_exe_unit_io_iresp_bits_uop_imm_packed; // @[execution-units.scala:119:32]
wire [11:0] _alu_exe_unit_io_iresp_bits_uop_csr_addr; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_iresp_bits_uop_rob_idx; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_iresp_bits_uop_ldq_idx; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_iresp_bits_uop_stq_idx; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_iresp_bits_uop_rxq_idx; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_iresp_bits_uop_pdst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_iresp_bits_uop_prs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_iresp_bits_uop_prs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_iresp_bits_uop_prs3; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_iresp_bits_uop_ppred; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_prs1_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_prs2_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_prs3_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_ppred_busy; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_iresp_bits_uop_stale_pdst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_exception; // @[execution-units.scala:119:32]
wire [63:0] _alu_exe_unit_io_iresp_bits_uop_exc_cause; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_bypassable; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_iresp_bits_uop_mem_cmd; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_iresp_bits_uop_mem_size; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_mem_signed; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_is_fence; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_is_fencei; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_is_amo; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_uses_ldq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_uses_stq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_is_unique; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_flush_on_commit; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_iresp_bits_uop_ldst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_iresp_bits_uop_lrs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_iresp_bits_uop_lrs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_iresp_bits_uop_lrs3; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_ldst_val; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_iresp_bits_uop_dst_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_iresp_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_iresp_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_frs3_en; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_fp_val; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_fp_single; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_bp_debug_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_iresp_bits_uop_debug_fsrc; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_iresp_bits_uop_debug_tsrc; // @[execution-units.scala:119:32]
wire [64:0] _alu_exe_unit_io_iresp_bits_data; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_valid; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_ll_fresp_bits_uop_uopc; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_io_ll_fresp_bits_uop_inst; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_io_ll_fresp_bits_uop_debug_inst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_is_rvc; // @[execution-units.scala:119:32]
wire [39:0] _alu_exe_unit_io_ll_fresp_bits_uop_debug_pc; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_ll_fresp_bits_uop_iq_type; // @[execution-units.scala:119:32]
wire [9:0] _alu_exe_unit_io_ll_fresp_bits_uop_fu_code; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_ll_fresp_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_ll_fresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_ll_fresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_ll_fresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_ll_fresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_ll_fresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_ll_fresp_bits_uop_iw_state; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_is_br; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_is_jalr; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_is_jal; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_is_sfb; // @[execution-units.scala:119:32]
wire [7:0] _alu_exe_unit_io_ll_fresp_bits_uop_br_mask; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_ll_fresp_bits_uop_br_tag; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_ll_fresp_bits_uop_ftq_idx; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_edge_inst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_ll_fresp_bits_uop_pc_lob; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_taken; // @[execution-units.scala:119:32]
wire [19:0] _alu_exe_unit_io_ll_fresp_bits_uop_imm_packed; // @[execution-units.scala:119:32]
wire [11:0] _alu_exe_unit_io_ll_fresp_bits_uop_csr_addr; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_ll_fresp_bits_uop_rob_idx; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_ll_fresp_bits_uop_ldq_idx; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_ll_fresp_bits_uop_stq_idx; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_ll_fresp_bits_uop_rxq_idx; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_ll_fresp_bits_uop_pdst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_ll_fresp_bits_uop_prs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_ll_fresp_bits_uop_prs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_ll_fresp_bits_uop_prs3; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_ll_fresp_bits_uop_ppred; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_prs1_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_prs2_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_prs3_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_ppred_busy; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_ll_fresp_bits_uop_stale_pdst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_exception; // @[execution-units.scala:119:32]
wire [63:0] _alu_exe_unit_io_ll_fresp_bits_uop_exc_cause; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_bypassable; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_ll_fresp_bits_uop_mem_cmd; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_ll_fresp_bits_uop_mem_size; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_mem_signed; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_is_fence; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_is_fencei; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_is_amo; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_uses_ldq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_uses_stq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_is_unique; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_flush_on_commit; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_ll_fresp_bits_uop_ldst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_ll_fresp_bits_uop_lrs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_ll_fresp_bits_uop_lrs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_ll_fresp_bits_uop_lrs3; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_ldst_val; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_ll_fresp_bits_uop_dst_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_ll_fresp_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_ll_fresp_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_frs3_en; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_fp_val; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_fp_single; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_bp_debug_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_ll_fresp_bits_uop_debug_fsrc; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_ll_fresp_bits_uop_debug_tsrc; // @[execution-units.scala:119:32]
wire [64:0] _alu_exe_unit_io_ll_fresp_bits_data; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_predicated; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_valid; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_uopc; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_inst; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_debug_inst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_is_rvc; // @[execution-units.scala:119:32]
wire [39:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_debug_pc; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_iq_type; // @[execution-units.scala:119:32]
wire [9:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_fu_code; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_iw_state; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_is_br; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_is_jalr; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_is_jal; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_is_sfb; // @[execution-units.scala:119:32]
wire [7:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_br_mask; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_br_tag; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_ftq_idx; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_edge_inst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_pc_lob; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_taken; // @[execution-units.scala:119:32]
wire [19:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_imm_packed; // @[execution-units.scala:119:32]
wire [11:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_csr_addr; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_rob_idx; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_ldq_idx; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_stq_idx; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_rxq_idx; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_pdst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_prs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_prs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_prs3; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_ppred; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_prs1_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_prs2_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_prs3_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_ppred_busy; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_stale_pdst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_exception; // @[execution-units.scala:119:32]
wire [63:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_exc_cause; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_bypassable; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_mem_cmd; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_mem_size; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_mem_signed; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_is_fence; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_is_fencei; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_is_amo; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_uses_ldq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_uses_stq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_is_unique; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_flush_on_commit; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_ldst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_lrs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_lrs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_lrs3; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_ldst_val; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_dst_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_frs3_en; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_fp_val; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_fp_single; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_bp_debug_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_debug_fsrc; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_uop_debug_tsrc; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_ll_fresp_bits_fflags_bits_flags; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_valid; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_uopc; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_io_bypass_0_bits_uop_inst; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_io_bypass_0_bits_uop_debug_inst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_is_rvc; // @[execution-units.scala:119:32]
wire [39:0] _alu_exe_unit_io_bypass_0_bits_uop_debug_pc; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_iq_type; // @[execution-units.scala:119:32]
wire [9:0] _alu_exe_unit_io_bypass_0_bits_uop_fu_code; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_iw_state; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_is_br; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_is_jalr; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_is_jal; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_is_sfb; // @[execution-units.scala:119:32]
wire [7:0] _alu_exe_unit_io_bypass_0_bits_uop_br_mask; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_br_tag; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_bypass_0_bits_uop_ftq_idx; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_edge_inst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_pc_lob; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_taken; // @[execution-units.scala:119:32]
wire [19:0] _alu_exe_unit_io_bypass_0_bits_uop_imm_packed; // @[execution-units.scala:119:32]
wire [11:0] _alu_exe_unit_io_bypass_0_bits_uop_csr_addr; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_rob_idx; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_ldq_idx; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_stq_idx; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_rxq_idx; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_pdst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_prs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_prs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_prs3; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_bypass_0_bits_uop_ppred; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_prs1_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_prs2_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_prs3_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_ppred_busy; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_stale_pdst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_exception; // @[execution-units.scala:119:32]
wire [63:0] _alu_exe_unit_io_bypass_0_bits_uop_exc_cause; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_bypassable; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_mem_cmd; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_mem_size; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_mem_signed; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_is_fence; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_is_fencei; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_is_amo; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_uses_ldq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_uses_stq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_is_unique; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_flush_on_commit; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_ldst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs3; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_ldst_val; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_dst_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_frs3_en; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_fp_val; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_fp_single; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_bp_debug_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_debug_fsrc; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_debug_tsrc; // @[execution-units.scala:119:32]
wire [64:0] _alu_exe_unit_io_bypass_0_bits_data; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_valid; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_bypass_1_bits_uop_uopc; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_io_bypass_1_bits_uop_inst; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_io_bypass_1_bits_uop_debug_inst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_is_rvc; // @[execution-units.scala:119:32]
wire [39:0] _alu_exe_unit_io_bypass_1_bits_uop_debug_pc; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_1_bits_uop_iq_type; // @[execution-units.scala:119:32]
wire [9:0] _alu_exe_unit_io_bypass_1_bits_uop_fu_code; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_bypass_1_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_1_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_1_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_1_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_bypass_1_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_1_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_1_bits_uop_iw_state; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_is_br; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_is_jalr; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_is_jal; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_is_sfb; // @[execution-units.scala:119:32]
wire [7:0] _alu_exe_unit_io_bypass_1_bits_uop_br_mask; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_1_bits_uop_br_tag; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_bypass_1_bits_uop_ftq_idx; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_edge_inst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_1_bits_uop_pc_lob; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_taken; // @[execution-units.scala:119:32]
wire [19:0] _alu_exe_unit_io_bypass_1_bits_uop_imm_packed; // @[execution-units.scala:119:32]
wire [11:0] _alu_exe_unit_io_bypass_1_bits_uop_csr_addr; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_bypass_1_bits_uop_rob_idx; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_1_bits_uop_ldq_idx; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_1_bits_uop_stq_idx; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_1_bits_uop_rxq_idx; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_1_bits_uop_pdst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_1_bits_uop_prs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_1_bits_uop_prs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_1_bits_uop_prs3; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_bypass_1_bits_uop_ppred; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_prs1_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_prs2_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_prs3_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_ppred_busy; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_1_bits_uop_stale_pdst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_exception; // @[execution-units.scala:119:32]
wire [63:0] _alu_exe_unit_io_bypass_1_bits_uop_exc_cause; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_bypassable; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_bypass_1_bits_uop_mem_cmd; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_1_bits_uop_mem_size; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_mem_signed; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_is_fence; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_is_fencei; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_is_amo; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_uses_ldq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_uses_stq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_is_unique; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_flush_on_commit; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_1_bits_uop_ldst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_1_bits_uop_lrs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_1_bits_uop_lrs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_1_bits_uop_lrs3; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_ldst_val; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_1_bits_uop_dst_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_1_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_1_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_frs3_en; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_fp_val; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_fp_single; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_bp_debug_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_1_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_1_bits_uop_debug_fsrc; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_1_bits_uop_debug_tsrc; // @[execution-units.scala:119:32]
wire [64:0] _alu_exe_unit_io_bypass_1_bits_data; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_valid; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_bypass_2_bits_uop_uopc; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_io_bypass_2_bits_uop_inst; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_io_bypass_2_bits_uop_debug_inst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_is_rvc; // @[execution-units.scala:119:32]
wire [39:0] _alu_exe_unit_io_bypass_2_bits_uop_debug_pc; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_2_bits_uop_iq_type; // @[execution-units.scala:119:32]
wire [9:0] _alu_exe_unit_io_bypass_2_bits_uop_fu_code; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_bypass_2_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_2_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_2_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_2_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_bypass_2_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_2_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_2_bits_uop_iw_state; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_is_br; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_is_jalr; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_is_jal; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_is_sfb; // @[execution-units.scala:119:32]
wire [7:0] _alu_exe_unit_io_bypass_2_bits_uop_br_mask; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_2_bits_uop_br_tag; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_bypass_2_bits_uop_ftq_idx; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_edge_inst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_2_bits_uop_pc_lob; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_taken; // @[execution-units.scala:119:32]
wire [19:0] _alu_exe_unit_io_bypass_2_bits_uop_imm_packed; // @[execution-units.scala:119:32]
wire [11:0] _alu_exe_unit_io_bypass_2_bits_uop_csr_addr; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_bypass_2_bits_uop_rob_idx; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_2_bits_uop_ldq_idx; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_2_bits_uop_stq_idx; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_2_bits_uop_rxq_idx; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_2_bits_uop_pdst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_2_bits_uop_prs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_2_bits_uop_prs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_2_bits_uop_prs3; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_bypass_2_bits_uop_ppred; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_prs1_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_prs2_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_prs3_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_ppred_busy; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_2_bits_uop_stale_pdst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_exception; // @[execution-units.scala:119:32]
wire [63:0] _alu_exe_unit_io_bypass_2_bits_uop_exc_cause; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_bypassable; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_bypass_2_bits_uop_mem_cmd; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_2_bits_uop_mem_size; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_mem_signed; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_is_fence; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_is_fencei; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_is_amo; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_uses_ldq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_uses_stq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_is_unique; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_flush_on_commit; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_2_bits_uop_ldst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_2_bits_uop_lrs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_2_bits_uop_lrs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_2_bits_uop_lrs3; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_ldst_val; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_2_bits_uop_dst_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_2_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_2_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_frs3_en; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_fp_val; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_fp_single; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_bp_debug_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_2_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_2_bits_uop_debug_fsrc; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_2_bits_uop_debug_tsrc; // @[execution-units.scala:119:32]
wire [64:0] _alu_exe_unit_io_bypass_2_bits_data; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_brinfo_uop_uopc; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_io_brinfo_uop_inst; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_io_brinfo_uop_debug_inst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_is_rvc; // @[execution-units.scala:119:32]
wire [39:0] _alu_exe_unit_io_brinfo_uop_debug_pc; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_brinfo_uop_iq_type; // @[execution-units.scala:119:32]
wire [9:0] _alu_exe_unit_io_brinfo_uop_fu_code; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_brinfo_uop_ctrl_br_type; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_brinfo_uop_ctrl_op1_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_brinfo_uop_ctrl_op2_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_brinfo_uop_ctrl_imm_sel; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_brinfo_uop_ctrl_op_fcn; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_brinfo_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_ctrl_is_load; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_ctrl_is_sta; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_ctrl_is_std; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_brinfo_uop_iw_state; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_iw_p1_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_iw_p2_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_is_br; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_is_jalr; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_is_jal; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_is_sfb; // @[execution-units.scala:119:32]
wire [7:0] _alu_exe_unit_io_brinfo_uop_br_mask; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_brinfo_uop_br_tag; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_brinfo_uop_ftq_idx; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_edge_inst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_brinfo_uop_pc_lob; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_taken; // @[execution-units.scala:119:32]
wire [19:0] _alu_exe_unit_io_brinfo_uop_imm_packed; // @[execution-units.scala:119:32]
wire [11:0] _alu_exe_unit_io_brinfo_uop_csr_addr; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_brinfo_uop_rob_idx; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_brinfo_uop_ldq_idx; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_brinfo_uop_stq_idx; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_brinfo_uop_rxq_idx; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_brinfo_uop_pdst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_brinfo_uop_prs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_brinfo_uop_prs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_brinfo_uop_prs3; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_brinfo_uop_ppred; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_prs1_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_prs2_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_prs3_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_ppred_busy; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_brinfo_uop_stale_pdst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_exception; // @[execution-units.scala:119:32]
wire [63:0] _alu_exe_unit_io_brinfo_uop_exc_cause; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_bypassable; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_brinfo_uop_mem_cmd; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_brinfo_uop_mem_size; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_mem_signed; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_is_fence; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_is_fencei; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_is_amo; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_uses_ldq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_uses_stq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_is_sys_pc2epc; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_is_unique; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_flush_on_commit; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_ldst_is_rs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_brinfo_uop_ldst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_brinfo_uop_lrs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_brinfo_uop_lrs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_brinfo_uop_lrs3; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_ldst_val; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_brinfo_uop_dst_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_brinfo_uop_lrs1_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_brinfo_uop_lrs2_rtype; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_frs3_en; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_fp_val; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_fp_single; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_xcpt_pf_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_xcpt_ae_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_xcpt_ma_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_bp_debug_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_bp_xcpt_if; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_brinfo_uop_debug_fsrc; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_brinfo_uop_debug_tsrc; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_valid; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_mispredict; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_taken; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_brinfo_cfi_type; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_brinfo_pc_sel; // @[execution-units.scala:119:32]
wire [39:0] _alu_exe_unit_io_brinfo_jalr_target; // @[execution-units.scala:119:32]
wire [20:0] _alu_exe_unit_io_brinfo_target_offset; // @[execution-units.scala:119:32]
wire _memExeUnit_io_ll_iresp_valid; // @[execution-units.scala:108:30]
wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_uopc; // @[execution-units.scala:108:30]
wire [31:0] _memExeUnit_io_ll_iresp_bits_uop_inst; // @[execution-units.scala:108:30]
wire [31:0] _memExeUnit_io_ll_iresp_bits_uop_debug_inst; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_is_rvc; // @[execution-units.scala:108:30]
wire [39:0] _memExeUnit_io_ll_iresp_bits_uop_debug_pc; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_iq_type; // @[execution-units.scala:108:30]
wire [9:0] _memExeUnit_io_ll_iresp_bits_uop_fu_code; // @[execution-units.scala:108:30]
wire [3:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_br_type; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:108:30]
wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_ctrl_is_load; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_ctrl_is_std; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_iw_state; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_is_br; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_is_jalr; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_is_jal; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_is_sfb; // @[execution-units.scala:108:30]
wire [7:0] _memExeUnit_io_ll_iresp_bits_uop_br_mask; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_br_tag; // @[execution-units.scala:108:30]
wire [3:0] _memExeUnit_io_ll_iresp_bits_uop_ftq_idx; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_edge_inst; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_pc_lob; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_taken; // @[execution-units.scala:108:30]
wire [19:0] _memExeUnit_io_ll_iresp_bits_uop_imm_packed; // @[execution-units.scala:108:30]
wire [11:0] _memExeUnit_io_ll_iresp_bits_uop_csr_addr; // @[execution-units.scala:108:30]
wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_rob_idx; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_ldq_idx; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_stq_idx; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_rxq_idx; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_pdst; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_prs1; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_prs2; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_prs3; // @[execution-units.scala:108:30]
wire [3:0] _memExeUnit_io_ll_iresp_bits_uop_ppred; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_prs1_busy; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_prs2_busy; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_prs3_busy; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_ppred_busy; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_stale_pdst; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_exception; // @[execution-units.scala:108:30]
wire [63:0] _memExeUnit_io_ll_iresp_bits_uop_exc_cause; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_bypassable; // @[execution-units.scala:108:30]
wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_mem_cmd; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_mem_size; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_mem_signed; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_is_fence; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_is_fencei; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_is_amo; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_uses_ldq; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_uses_stq; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_is_unique; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_flush_on_commit; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_ldst; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_lrs1; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_lrs2; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_lrs3; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_ldst_val; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_dst_rtype; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_lrs1_rtype; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_lrs2_rtype; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_frs3_en; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_fp_val; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_fp_single; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_bp_debug_if; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_debug_fsrc; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_debug_tsrc; // @[execution-units.scala:108:30]
wire [64:0] _memExeUnit_io_ll_iresp_bits_data; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_valid; // @[execution-units.scala:108:30]
wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_uopc; // @[execution-units.scala:108:30]
wire [31:0] _memExeUnit_io_ll_fresp_bits_uop_inst; // @[execution-units.scala:108:30]
wire [31:0] _memExeUnit_io_ll_fresp_bits_uop_debug_inst; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_is_rvc; // @[execution-units.scala:108:30]
wire [39:0] _memExeUnit_io_ll_fresp_bits_uop_debug_pc; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_iq_type; // @[execution-units.scala:108:30]
wire [9:0] _memExeUnit_io_ll_fresp_bits_uop_fu_code; // @[execution-units.scala:108:30]
wire [3:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_br_type; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:108:30]
wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_ctrl_is_load; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_ctrl_is_std; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_iw_state; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_is_br; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_is_jalr; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_is_jal; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_is_sfb; // @[execution-units.scala:108:30]
wire [7:0] _memExeUnit_io_ll_fresp_bits_uop_br_mask; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_br_tag; // @[execution-units.scala:108:30]
wire [3:0] _memExeUnit_io_ll_fresp_bits_uop_ftq_idx; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_edge_inst; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_pc_lob; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_taken; // @[execution-units.scala:108:30]
wire [19:0] _memExeUnit_io_ll_fresp_bits_uop_imm_packed; // @[execution-units.scala:108:30]
wire [11:0] _memExeUnit_io_ll_fresp_bits_uop_csr_addr; // @[execution-units.scala:108:30]
wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_rob_idx; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_ldq_idx; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_stq_idx; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_rxq_idx; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_pdst; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_prs1; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_prs2; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_prs3; // @[execution-units.scala:108:30]
wire [3:0] _memExeUnit_io_ll_fresp_bits_uop_ppred; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_prs1_busy; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_prs2_busy; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_prs3_busy; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_ppred_busy; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_stale_pdst; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_exception; // @[execution-units.scala:108:30]
wire [63:0] _memExeUnit_io_ll_fresp_bits_uop_exc_cause; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_bypassable; // @[execution-units.scala:108:30]
wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_mem_cmd; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_mem_size; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_mem_signed; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_is_fence; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_is_fencei; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_is_amo; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_uses_ldq; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_uses_stq; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_is_unique; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_flush_on_commit; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_ldst; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_lrs1; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_lrs2; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_lrs3; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_ldst_val; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_dst_rtype; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_lrs1_rtype; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_lrs2_rtype; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_frs3_en; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_fp_val; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_fp_single; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_bp_debug_if; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_debug_fsrc; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_debug_tsrc; // @[execution-units.scala:108:30]
wire [64:0] _memExeUnit_io_ll_fresp_bits_data; // @[execution-units.scala:108:30]
wire io_hartid_0 = io_hartid; // @[core.scala:51:7]
wire io_interrupts_debug_0 = io_interrupts_debug; // @[core.scala:51:7]
wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[core.scala:51:7]
wire io_interrupts_msip_0 = io_interrupts_msip; // @[core.scala:51:7]
wire io_interrupts_meip_0 = io_interrupts_meip; // @[core.scala:51:7]
wire io_interrupts_seip_0 = io_interrupts_seip; // @[core.scala:51:7]
wire io_ifu_fetchpacket_valid_0 = io_ifu_fetchpacket_valid; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_valid_0 = io_ifu_fetchpacket_bits_uops_0_valid; // @[core.scala:51:7]
wire [31:0] io_ifu_fetchpacket_bits_uops_0_bits_inst_0 = io_ifu_fetchpacket_bits_uops_0_bits_inst; // @[core.scala:51:7]
wire [31:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_inst_0 = io_ifu_fetchpacket_bits_uops_0_bits_debug_inst; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_is_rvc_0 = io_ifu_fetchpacket_bits_uops_0_bits_is_rvc; // @[core.scala:51:7]
wire [39:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_pc_0 = io_ifu_fetchpacket_bits_uops_0_bits_debug_pc; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_is_sfb_0 = io_ifu_fetchpacket_bits_uops_0_bits_is_sfb; // @[core.scala:51:7]
wire [3:0] io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx_0 = io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_edge_inst_0 = io_ifu_fetchpacket_bits_uops_0_bits_edge_inst; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_pc_lob_0 = io_ifu_fetchpacket_bits_uops_0_bits_pc_lob; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_taken_0 = io_ifu_fetchpacket_bits_uops_0_bits_taken; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc_0 = io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc; // @[core.scala:51:7]
wire io_ifu_get_pc_0_entry_cfi_idx_valid_0 = io_ifu_get_pc_0_entry_cfi_idx_valid; // @[core.scala:51:7]
wire [1:0] io_ifu_get_pc_0_entry_cfi_idx_bits_0 = io_ifu_get_pc_0_entry_cfi_idx_bits; // @[core.scala:51:7]
wire io_ifu_get_pc_0_entry_cfi_taken_0 = io_ifu_get_pc_0_entry_cfi_taken; // @[core.scala:51:7]
wire io_ifu_get_pc_0_entry_cfi_mispredicted_0 = io_ifu_get_pc_0_entry_cfi_mispredicted; // @[core.scala:51:7]
wire [2:0] io_ifu_get_pc_0_entry_cfi_type_0 = io_ifu_get_pc_0_entry_cfi_type; // @[core.scala:51:7]
wire [3:0] io_ifu_get_pc_0_entry_br_mask_0 = io_ifu_get_pc_0_entry_br_mask; // @[core.scala:51:7]
wire io_ifu_get_pc_0_entry_cfi_is_call_0 = io_ifu_get_pc_0_entry_cfi_is_call; // @[core.scala:51:7]
wire io_ifu_get_pc_0_entry_cfi_is_ret_0 = io_ifu_get_pc_0_entry_cfi_is_ret; // @[core.scala:51:7]
wire io_ifu_get_pc_0_entry_cfi_npc_plus4_0 = io_ifu_get_pc_0_entry_cfi_npc_plus4; // @[core.scala:51:7]
wire [39:0] io_ifu_get_pc_0_entry_ras_top_0 = io_ifu_get_pc_0_entry_ras_top; // @[core.scala:51:7]
wire [4:0] io_ifu_get_pc_0_entry_ras_idx_0 = io_ifu_get_pc_0_entry_ras_idx; // @[core.scala:51:7]
wire io_ifu_get_pc_0_entry_start_bank_0 = io_ifu_get_pc_0_entry_start_bank; // @[core.scala:51:7]
wire [39:0] io_ifu_get_pc_0_pc_0 = io_ifu_get_pc_0_pc; // @[core.scala:51:7]
wire [39:0] io_ifu_get_pc_0_com_pc_0 = io_ifu_get_pc_0_com_pc; // @[core.scala:51:7]
wire io_ifu_get_pc_0_next_val_0 = io_ifu_get_pc_0_next_val; // @[core.scala:51:7]
wire [39:0] io_ifu_get_pc_0_next_pc_0 = io_ifu_get_pc_0_next_pc; // @[core.scala:51:7]
wire io_ifu_get_pc_1_entry_cfi_idx_valid_0 = io_ifu_get_pc_1_entry_cfi_idx_valid; // @[core.scala:51:7]
wire [1:0] io_ifu_get_pc_1_entry_cfi_idx_bits_0 = io_ifu_get_pc_1_entry_cfi_idx_bits; // @[core.scala:51:7]
wire io_ifu_get_pc_1_entry_cfi_taken_0 = io_ifu_get_pc_1_entry_cfi_taken; // @[core.scala:51:7]
wire io_ifu_get_pc_1_entry_cfi_mispredicted_0 = io_ifu_get_pc_1_entry_cfi_mispredicted; // @[core.scala:51:7]
wire [2:0] io_ifu_get_pc_1_entry_cfi_type_0 = io_ifu_get_pc_1_entry_cfi_type; // @[core.scala:51:7]
wire [3:0] io_ifu_get_pc_1_entry_br_mask_0 = io_ifu_get_pc_1_entry_br_mask; // @[core.scala:51:7]
wire io_ifu_get_pc_1_entry_cfi_is_call_0 = io_ifu_get_pc_1_entry_cfi_is_call; // @[core.scala:51:7]
wire io_ifu_get_pc_1_entry_cfi_is_ret_0 = io_ifu_get_pc_1_entry_cfi_is_ret; // @[core.scala:51:7]
wire io_ifu_get_pc_1_entry_cfi_npc_plus4_0 = io_ifu_get_pc_1_entry_cfi_npc_plus4; // @[core.scala:51:7]
wire [39:0] io_ifu_get_pc_1_entry_ras_top_0 = io_ifu_get_pc_1_entry_ras_top; // @[core.scala:51:7]
wire [4:0] io_ifu_get_pc_1_entry_ras_idx_0 = io_ifu_get_pc_1_entry_ras_idx; // @[core.scala:51:7]
wire io_ifu_get_pc_1_entry_start_bank_0 = io_ifu_get_pc_1_entry_start_bank; // @[core.scala:51:7]
wire [63:0] io_ifu_get_pc_1_ghist_old_history_0 = io_ifu_get_pc_1_ghist_old_history; // @[core.scala:51:7]
wire io_ifu_get_pc_1_ghist_current_saw_branch_not_taken_0 = io_ifu_get_pc_1_ghist_current_saw_branch_not_taken; // @[core.scala:51:7]
wire io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken; // @[core.scala:51:7]
wire io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 = io_ifu_get_pc_1_ghist_new_saw_branch_taken; // @[core.scala:51:7]
wire [4:0] io_ifu_get_pc_1_ghist_ras_idx_0 = io_ifu_get_pc_1_ghist_ras_idx; // @[core.scala:51:7]
wire [39:0] io_ifu_get_pc_1_pc_0 = io_ifu_get_pc_1_pc; // @[core.scala:51:7]
wire [39:0] io_ifu_get_pc_1_com_pc_0 = io_ifu_get_pc_1_com_pc; // @[core.scala:51:7]
wire io_ifu_get_pc_1_next_val_0 = io_ifu_get_pc_1_next_val; // @[core.scala:51:7]
wire [39:0] io_ifu_get_pc_1_next_pc_0 = io_ifu_get_pc_1_next_pc; // @[core.scala:51:7]
wire [39:0] io_ifu_debug_fetch_pc_0_0 = io_ifu_debug_fetch_pc_0; // @[core.scala:51:7]
wire io_ifu_perf_acquire_0 = io_ifu_perf_acquire; // @[core.scala:51:7]
wire io_ifu_perf_tlbMiss_0 = io_ifu_perf_tlbMiss; // @[core.scala:51:7]
wire io_ptw_perf_l2miss_0 = io_ptw_perf_l2miss; // @[core.scala:51:7]
wire io_ptw_perf_l2hit_0 = io_ptw_perf_l2hit; // @[core.scala:51:7]
wire io_ptw_perf_pte_miss_0 = io_ptw_perf_pte_miss; // @[core.scala:51:7]
wire io_ptw_perf_pte_hit_0 = io_ptw_perf_pte_hit; // @[core.scala:51:7]
wire io_ptw_clock_enabled_0 = io_ptw_clock_enabled; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_valid_0 = io_lsu_exe_0_iresp_valid; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_iresp_bits_uop_uopc_0 = io_lsu_exe_0_iresp_bits_uop_uopc; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_iresp_bits_uop_inst_0 = io_lsu_exe_0_iresp_bits_uop_inst; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_iresp_bits_uop_debug_inst_0 = io_lsu_exe_0_iresp_bits_uop_debug_inst; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_is_rvc_0 = io_lsu_exe_0_iresp_bits_uop_is_rvc; // @[core.scala:51:7]
wire [39:0] io_lsu_exe_0_iresp_bits_uop_debug_pc_0 = io_lsu_exe_0_iresp_bits_uop_debug_pc; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_uop_iq_type_0 = io_lsu_exe_0_iresp_bits_uop_iq_type; // @[core.scala:51:7]
wire [9:0] io_lsu_exe_0_iresp_bits_uop_fu_code_0 = io_lsu_exe_0_iresp_bits_uop_fu_code; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_iresp_bits_uop_ctrl_br_type_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_br_type; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_load_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_load; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_std_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_std; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_iw_state_0 = io_lsu_exe_0_iresp_bits_uop_iw_state; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned_0 = io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned_0 = io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_is_br_0 = io_lsu_exe_0_iresp_bits_uop_is_br; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_is_jalr_0 = io_lsu_exe_0_iresp_bits_uop_is_jalr; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_is_jal_0 = io_lsu_exe_0_iresp_bits_uop_is_jal; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_is_sfb_0 = io_lsu_exe_0_iresp_bits_uop_is_sfb; // @[core.scala:51:7]
wire [7:0] io_lsu_exe_0_iresp_bits_uop_br_mask_0 = io_lsu_exe_0_iresp_bits_uop_br_mask; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_uop_br_tag_0 = io_lsu_exe_0_iresp_bits_uop_br_tag; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_iresp_bits_uop_ftq_idx_0 = io_lsu_exe_0_iresp_bits_uop_ftq_idx; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_edge_inst_0 = io_lsu_exe_0_iresp_bits_uop_edge_inst; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_pc_lob_0 = io_lsu_exe_0_iresp_bits_uop_pc_lob; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_taken_0 = io_lsu_exe_0_iresp_bits_uop_taken; // @[core.scala:51:7]
wire [19:0] io_lsu_exe_0_iresp_bits_uop_imm_packed_0 = io_lsu_exe_0_iresp_bits_uop_imm_packed; // @[core.scala:51:7]
wire [11:0] io_lsu_exe_0_iresp_bits_uop_csr_addr_0 = io_lsu_exe_0_iresp_bits_uop_csr_addr; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_iresp_bits_uop_rob_idx_0 = io_lsu_exe_0_iresp_bits_uop_rob_idx; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_uop_ldq_idx_0 = io_lsu_exe_0_iresp_bits_uop_ldq_idx; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_uop_stq_idx_0 = io_lsu_exe_0_iresp_bits_uop_stq_idx; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_rxq_idx_0 = io_lsu_exe_0_iresp_bits_uop_rxq_idx; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_pdst_0 = io_lsu_exe_0_iresp_bits_uop_pdst; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_prs1_0 = io_lsu_exe_0_iresp_bits_uop_prs1; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_prs2_0 = io_lsu_exe_0_iresp_bits_uop_prs2; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_prs3_0 = io_lsu_exe_0_iresp_bits_uop_prs3; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_iresp_bits_uop_ppred_0 = io_lsu_exe_0_iresp_bits_uop_ppred; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_prs1_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs1_busy; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_prs2_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs2_busy; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_prs3_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs3_busy; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_ppred_busy_0 = io_lsu_exe_0_iresp_bits_uop_ppred_busy; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_stale_pdst_0 = io_lsu_exe_0_iresp_bits_uop_stale_pdst; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_exception_0 = io_lsu_exe_0_iresp_bits_uop_exception; // @[core.scala:51:7]
wire [63:0] io_lsu_exe_0_iresp_bits_uop_exc_cause_0 = io_lsu_exe_0_iresp_bits_uop_exc_cause; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_bypassable_0 = io_lsu_exe_0_iresp_bits_uop_bypassable; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_iresp_bits_uop_mem_cmd_0 = io_lsu_exe_0_iresp_bits_uop_mem_cmd; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_mem_size_0 = io_lsu_exe_0_iresp_bits_uop_mem_size; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_mem_signed_0 = io_lsu_exe_0_iresp_bits_uop_mem_signed; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_is_fence_0 = io_lsu_exe_0_iresp_bits_uop_is_fence; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_is_fencei_0 = io_lsu_exe_0_iresp_bits_uop_is_fencei; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_is_amo_0 = io_lsu_exe_0_iresp_bits_uop_is_amo; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_uses_ldq_0 = io_lsu_exe_0_iresp_bits_uop_uses_ldq; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_uses_stq_0 = io_lsu_exe_0_iresp_bits_uop_uses_stq; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc_0 = io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_is_unique_0 = io_lsu_exe_0_iresp_bits_uop_is_unique; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_flush_on_commit_0 = io_lsu_exe_0_iresp_bits_uop_flush_on_commit; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1_0 = io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_ldst_0 = io_lsu_exe_0_iresp_bits_uop_ldst; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs1_0 = io_lsu_exe_0_iresp_bits_uop_lrs1; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs2_0 = io_lsu_exe_0_iresp_bits_uop_lrs2; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs3_0 = io_lsu_exe_0_iresp_bits_uop_lrs3; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_ldst_val_0 = io_lsu_exe_0_iresp_bits_uop_ldst_val; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_dst_rtype_0 = io_lsu_exe_0_iresp_bits_uop_dst_rtype; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_lrs1_rtype_0 = io_lsu_exe_0_iresp_bits_uop_lrs1_rtype; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_lrs2_rtype_0 = io_lsu_exe_0_iresp_bits_uop_lrs2_rtype; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_frs3_en_0 = io_lsu_exe_0_iresp_bits_uop_frs3_en; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_fp_val_0 = io_lsu_exe_0_iresp_bits_uop_fp_val; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_fp_single_0 = io_lsu_exe_0_iresp_bits_uop_fp_single; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_bp_debug_if_0 = io_lsu_exe_0_iresp_bits_uop_bp_debug_if; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if_0 = io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_debug_fsrc_0 = io_lsu_exe_0_iresp_bits_uop_debug_fsrc; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_debug_tsrc_0 = io_lsu_exe_0_iresp_bits_uop_debug_tsrc; // @[core.scala:51:7]
wire [63:0] io_lsu_exe_0_iresp_bits_data_0 = io_lsu_exe_0_iresp_bits_data; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_valid_0 = io_lsu_exe_0_fresp_valid; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_fresp_bits_uop_uopc_0 = io_lsu_exe_0_fresp_bits_uop_uopc; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_fresp_bits_uop_inst_0 = io_lsu_exe_0_fresp_bits_uop_inst; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_fresp_bits_uop_debug_inst_0 = io_lsu_exe_0_fresp_bits_uop_debug_inst; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_is_rvc_0 = io_lsu_exe_0_fresp_bits_uop_is_rvc; // @[core.scala:51:7]
wire [39:0] io_lsu_exe_0_fresp_bits_uop_debug_pc_0 = io_lsu_exe_0_fresp_bits_uop_debug_pc; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_uop_iq_type_0 = io_lsu_exe_0_fresp_bits_uop_iq_type; // @[core.scala:51:7]
wire [9:0] io_lsu_exe_0_fresp_bits_uop_fu_code_0 = io_lsu_exe_0_fresp_bits_uop_fu_code; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_fresp_bits_uop_ctrl_br_type_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_br_type; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_load_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_load; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_std_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_std; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_iw_state_0 = io_lsu_exe_0_fresp_bits_uop_iw_state; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned_0 = io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned_0 = io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_is_br_0 = io_lsu_exe_0_fresp_bits_uop_is_br; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_is_jalr_0 = io_lsu_exe_0_fresp_bits_uop_is_jalr; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_is_jal_0 = io_lsu_exe_0_fresp_bits_uop_is_jal; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_is_sfb_0 = io_lsu_exe_0_fresp_bits_uop_is_sfb; // @[core.scala:51:7]
wire [7:0] io_lsu_exe_0_fresp_bits_uop_br_mask_0 = io_lsu_exe_0_fresp_bits_uop_br_mask; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_uop_br_tag_0 = io_lsu_exe_0_fresp_bits_uop_br_tag; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_fresp_bits_uop_ftq_idx_0 = io_lsu_exe_0_fresp_bits_uop_ftq_idx; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_edge_inst_0 = io_lsu_exe_0_fresp_bits_uop_edge_inst; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_pc_lob_0 = io_lsu_exe_0_fresp_bits_uop_pc_lob; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_taken_0 = io_lsu_exe_0_fresp_bits_uop_taken; // @[core.scala:51:7]
wire [19:0] io_lsu_exe_0_fresp_bits_uop_imm_packed_0 = io_lsu_exe_0_fresp_bits_uop_imm_packed; // @[core.scala:51:7]
wire [11:0] io_lsu_exe_0_fresp_bits_uop_csr_addr_0 = io_lsu_exe_0_fresp_bits_uop_csr_addr; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_fresp_bits_uop_rob_idx_0 = io_lsu_exe_0_fresp_bits_uop_rob_idx; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_uop_ldq_idx_0 = io_lsu_exe_0_fresp_bits_uop_ldq_idx; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_uop_stq_idx_0 = io_lsu_exe_0_fresp_bits_uop_stq_idx; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_rxq_idx_0 = io_lsu_exe_0_fresp_bits_uop_rxq_idx; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_pdst_0 = io_lsu_exe_0_fresp_bits_uop_pdst; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_prs1_0 = io_lsu_exe_0_fresp_bits_uop_prs1; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_prs2_0 = io_lsu_exe_0_fresp_bits_uop_prs2; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_prs3_0 = io_lsu_exe_0_fresp_bits_uop_prs3; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_fresp_bits_uop_ppred_0 = io_lsu_exe_0_fresp_bits_uop_ppred; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_prs1_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs1_busy; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_prs2_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs2_busy; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_prs3_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs3_busy; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_ppred_busy_0 = io_lsu_exe_0_fresp_bits_uop_ppred_busy; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_stale_pdst_0 = io_lsu_exe_0_fresp_bits_uop_stale_pdst; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_exception_0 = io_lsu_exe_0_fresp_bits_uop_exception; // @[core.scala:51:7]
wire [63:0] io_lsu_exe_0_fresp_bits_uop_exc_cause_0 = io_lsu_exe_0_fresp_bits_uop_exc_cause; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_bypassable_0 = io_lsu_exe_0_fresp_bits_uop_bypassable; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_fresp_bits_uop_mem_cmd_0 = io_lsu_exe_0_fresp_bits_uop_mem_cmd; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_mem_size_0 = io_lsu_exe_0_fresp_bits_uop_mem_size; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_mem_signed_0 = io_lsu_exe_0_fresp_bits_uop_mem_signed; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_is_fence_0 = io_lsu_exe_0_fresp_bits_uop_is_fence; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_is_fencei_0 = io_lsu_exe_0_fresp_bits_uop_is_fencei; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_is_amo_0 = io_lsu_exe_0_fresp_bits_uop_is_amo; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_uses_ldq_0 = io_lsu_exe_0_fresp_bits_uop_uses_ldq; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_uses_stq_0 = io_lsu_exe_0_fresp_bits_uop_uses_stq; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc_0 = io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_is_unique_0 = io_lsu_exe_0_fresp_bits_uop_is_unique; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_flush_on_commit_0 = io_lsu_exe_0_fresp_bits_uop_flush_on_commit; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1_0 = io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_ldst_0 = io_lsu_exe_0_fresp_bits_uop_ldst; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs1_0 = io_lsu_exe_0_fresp_bits_uop_lrs1; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs2_0 = io_lsu_exe_0_fresp_bits_uop_lrs2; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs3_0 = io_lsu_exe_0_fresp_bits_uop_lrs3; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_ldst_val_0 = io_lsu_exe_0_fresp_bits_uop_ldst_val; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_dst_rtype_0 = io_lsu_exe_0_fresp_bits_uop_dst_rtype; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_lrs1_rtype_0 = io_lsu_exe_0_fresp_bits_uop_lrs1_rtype; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_lrs2_rtype_0 = io_lsu_exe_0_fresp_bits_uop_lrs2_rtype; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_frs3_en_0 = io_lsu_exe_0_fresp_bits_uop_frs3_en; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_fp_val_0 = io_lsu_exe_0_fresp_bits_uop_fp_val; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_fp_single_0 = io_lsu_exe_0_fresp_bits_uop_fp_single; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_bp_debug_if_0 = io_lsu_exe_0_fresp_bits_uop_bp_debug_if; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if_0 = io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_debug_fsrc_0 = io_lsu_exe_0_fresp_bits_uop_debug_fsrc; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_debug_tsrc_0 = io_lsu_exe_0_fresp_bits_uop_debug_tsrc; // @[core.scala:51:7]
wire [64:0] io_lsu_exe_0_fresp_bits_data_0 = io_lsu_exe_0_fresp_bits_data; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_ldq_idx_0_0 = io_lsu_dis_ldq_idx_0; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_stq_idx_0_0 = io_lsu_dis_stq_idx_0; // @[core.scala:51:7]
wire io_lsu_ldq_full_0_0 = io_lsu_ldq_full_0; // @[core.scala:51:7]
wire io_lsu_stq_full_0_0 = io_lsu_stq_full_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_ready_0 = io_lsu_fp_stdata_ready; // @[core.scala:51:7]
wire io_lsu_clr_bsy_0_valid_0 = io_lsu_clr_bsy_0_valid; // @[core.scala:51:7]
wire [4:0] io_lsu_clr_bsy_0_bits_0 = io_lsu_clr_bsy_0_bits; // @[core.scala:51:7]
wire io_lsu_clr_bsy_1_valid_0 = io_lsu_clr_bsy_1_valid; // @[core.scala:51:7]
wire [4:0] io_lsu_clr_bsy_1_bits_0 = io_lsu_clr_bsy_1_bits; // @[core.scala:51:7]
wire [4:0] io_lsu_clr_unsafe_0_bits_0 = io_lsu_clr_unsafe_0_bits; // @[core.scala:51:7]
wire io_lsu_spec_ld_wakeup_0_valid_0 = io_lsu_spec_ld_wakeup_0_valid; // @[core.scala:51:7]
wire [5:0] io_lsu_spec_ld_wakeup_0_bits_0 = io_lsu_spec_ld_wakeup_0_bits; // @[core.scala:51:7]
wire io_lsu_ld_miss_0 = io_lsu_ld_miss; // @[core.scala:51:7]
wire io_lsu_fencei_rdy_0 = io_lsu_fencei_rdy; // @[core.scala:51:7]
wire io_lsu_lxcpt_valid_0 = io_lsu_lxcpt_valid; // @[core.scala:51:7]
wire [6:0] io_lsu_lxcpt_bits_uop_uopc_0 = io_lsu_lxcpt_bits_uop_uopc; // @[core.scala:51:7]
wire [31:0] io_lsu_lxcpt_bits_uop_inst_0 = io_lsu_lxcpt_bits_uop_inst; // @[core.scala:51:7]
wire [31:0] io_lsu_lxcpt_bits_uop_debug_inst_0 = io_lsu_lxcpt_bits_uop_debug_inst; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_is_rvc_0 = io_lsu_lxcpt_bits_uop_is_rvc; // @[core.scala:51:7]
wire [39:0] io_lsu_lxcpt_bits_uop_debug_pc_0 = io_lsu_lxcpt_bits_uop_debug_pc; // @[core.scala:51:7]
wire [2:0] io_lsu_lxcpt_bits_uop_iq_type_0 = io_lsu_lxcpt_bits_uop_iq_type; // @[core.scala:51:7]
wire [9:0] io_lsu_lxcpt_bits_uop_fu_code_0 = io_lsu_lxcpt_bits_uop_fu_code; // @[core.scala:51:7]
wire [3:0] io_lsu_lxcpt_bits_uop_ctrl_br_type_0 = io_lsu_lxcpt_bits_uop_ctrl_br_type; // @[core.scala:51:7]
wire [1:0] io_lsu_lxcpt_bits_uop_ctrl_op1_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_op1_sel; // @[core.scala:51:7]
wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_op2_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_op2_sel; // @[core.scala:51:7]
wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_imm_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_imm_sel; // @[core.scala:51:7]
wire [4:0] io_lsu_lxcpt_bits_uop_ctrl_op_fcn_0 = io_lsu_lxcpt_bits_uop_ctrl_op_fcn; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_ctrl_fcn_dw_0 = io_lsu_lxcpt_bits_uop_ctrl_fcn_dw; // @[core.scala:51:7]
wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_csr_cmd_0 = io_lsu_lxcpt_bits_uop_ctrl_csr_cmd; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_ctrl_is_load_0 = io_lsu_lxcpt_bits_uop_ctrl_is_load; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_ctrl_is_sta_0 = io_lsu_lxcpt_bits_uop_ctrl_is_sta; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_ctrl_is_std_0 = io_lsu_lxcpt_bits_uop_ctrl_is_std; // @[core.scala:51:7]
wire [1:0] io_lsu_lxcpt_bits_uop_iw_state_0 = io_lsu_lxcpt_bits_uop_iw_state; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_iw_p1_poisoned_0 = io_lsu_lxcpt_bits_uop_iw_p1_poisoned; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_iw_p2_poisoned_0 = io_lsu_lxcpt_bits_uop_iw_p2_poisoned; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_is_br_0 = io_lsu_lxcpt_bits_uop_is_br; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_is_jalr_0 = io_lsu_lxcpt_bits_uop_is_jalr; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_is_jal_0 = io_lsu_lxcpt_bits_uop_is_jal; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_is_sfb_0 = io_lsu_lxcpt_bits_uop_is_sfb; // @[core.scala:51:7]
wire [7:0] io_lsu_lxcpt_bits_uop_br_mask_0 = io_lsu_lxcpt_bits_uop_br_mask; // @[core.scala:51:7]
wire [2:0] io_lsu_lxcpt_bits_uop_br_tag_0 = io_lsu_lxcpt_bits_uop_br_tag; // @[core.scala:51:7]
wire [3:0] io_lsu_lxcpt_bits_uop_ftq_idx_0 = io_lsu_lxcpt_bits_uop_ftq_idx; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_edge_inst_0 = io_lsu_lxcpt_bits_uop_edge_inst; // @[core.scala:51:7]
wire [5:0] io_lsu_lxcpt_bits_uop_pc_lob_0 = io_lsu_lxcpt_bits_uop_pc_lob; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_taken_0 = io_lsu_lxcpt_bits_uop_taken; // @[core.scala:51:7]
wire [19:0] io_lsu_lxcpt_bits_uop_imm_packed_0 = io_lsu_lxcpt_bits_uop_imm_packed; // @[core.scala:51:7]
wire [11:0] io_lsu_lxcpt_bits_uop_csr_addr_0 = io_lsu_lxcpt_bits_uop_csr_addr; // @[core.scala:51:7]
wire [4:0] io_lsu_lxcpt_bits_uop_rob_idx_0 = io_lsu_lxcpt_bits_uop_rob_idx; // @[core.scala:51:7]
wire [2:0] io_lsu_lxcpt_bits_uop_ldq_idx_0 = io_lsu_lxcpt_bits_uop_ldq_idx; // @[core.scala:51:7]
wire [2:0] io_lsu_lxcpt_bits_uop_stq_idx_0 = io_lsu_lxcpt_bits_uop_stq_idx; // @[core.scala:51:7]
wire [1:0] io_lsu_lxcpt_bits_uop_rxq_idx_0 = io_lsu_lxcpt_bits_uop_rxq_idx; // @[core.scala:51:7]
wire [5:0] io_lsu_lxcpt_bits_uop_pdst_0 = io_lsu_lxcpt_bits_uop_pdst; // @[core.scala:51:7]
wire [5:0] io_lsu_lxcpt_bits_uop_prs1_0 = io_lsu_lxcpt_bits_uop_prs1; // @[core.scala:51:7]
wire [5:0] io_lsu_lxcpt_bits_uop_prs2_0 = io_lsu_lxcpt_bits_uop_prs2; // @[core.scala:51:7]
wire [5:0] io_lsu_lxcpt_bits_uop_prs3_0 = io_lsu_lxcpt_bits_uop_prs3; // @[core.scala:51:7]
wire [3:0] io_lsu_lxcpt_bits_uop_ppred_0 = io_lsu_lxcpt_bits_uop_ppred; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_prs1_busy_0 = io_lsu_lxcpt_bits_uop_prs1_busy; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_prs2_busy_0 = io_lsu_lxcpt_bits_uop_prs2_busy; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_prs3_busy_0 = io_lsu_lxcpt_bits_uop_prs3_busy; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_ppred_busy_0 = io_lsu_lxcpt_bits_uop_ppred_busy; // @[core.scala:51:7]
wire [5:0] io_lsu_lxcpt_bits_uop_stale_pdst_0 = io_lsu_lxcpt_bits_uop_stale_pdst; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_exception_0 = io_lsu_lxcpt_bits_uop_exception; // @[core.scala:51:7]
wire [63:0] io_lsu_lxcpt_bits_uop_exc_cause_0 = io_lsu_lxcpt_bits_uop_exc_cause; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_bypassable_0 = io_lsu_lxcpt_bits_uop_bypassable; // @[core.scala:51:7]
wire [4:0] io_lsu_lxcpt_bits_uop_mem_cmd_0 = io_lsu_lxcpt_bits_uop_mem_cmd; // @[core.scala:51:7]
wire [1:0] io_lsu_lxcpt_bits_uop_mem_size_0 = io_lsu_lxcpt_bits_uop_mem_size; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_mem_signed_0 = io_lsu_lxcpt_bits_uop_mem_signed; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_is_fence_0 = io_lsu_lxcpt_bits_uop_is_fence; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_is_fencei_0 = io_lsu_lxcpt_bits_uop_is_fencei; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_is_amo_0 = io_lsu_lxcpt_bits_uop_is_amo; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_uses_ldq_0 = io_lsu_lxcpt_bits_uop_uses_ldq; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_uses_stq_0 = io_lsu_lxcpt_bits_uop_uses_stq; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_is_sys_pc2epc_0 = io_lsu_lxcpt_bits_uop_is_sys_pc2epc; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_is_unique_0 = io_lsu_lxcpt_bits_uop_is_unique; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_flush_on_commit_0 = io_lsu_lxcpt_bits_uop_flush_on_commit; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_ldst_is_rs1_0 = io_lsu_lxcpt_bits_uop_ldst_is_rs1; // @[core.scala:51:7]
wire [5:0] io_lsu_lxcpt_bits_uop_ldst_0 = io_lsu_lxcpt_bits_uop_ldst; // @[core.scala:51:7]
wire [5:0] io_lsu_lxcpt_bits_uop_lrs1_0 = io_lsu_lxcpt_bits_uop_lrs1; // @[core.scala:51:7]
wire [5:0] io_lsu_lxcpt_bits_uop_lrs2_0 = io_lsu_lxcpt_bits_uop_lrs2; // @[core.scala:51:7]
wire [5:0] io_lsu_lxcpt_bits_uop_lrs3_0 = io_lsu_lxcpt_bits_uop_lrs3; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_ldst_val_0 = io_lsu_lxcpt_bits_uop_ldst_val; // @[core.scala:51:7]
wire [1:0] io_lsu_lxcpt_bits_uop_dst_rtype_0 = io_lsu_lxcpt_bits_uop_dst_rtype; // @[core.scala:51:7]
wire [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype_0 = io_lsu_lxcpt_bits_uop_lrs1_rtype; // @[core.scala:51:7]
wire [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype_0 = io_lsu_lxcpt_bits_uop_lrs2_rtype; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_frs3_en_0 = io_lsu_lxcpt_bits_uop_frs3_en; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_fp_val_0 = io_lsu_lxcpt_bits_uop_fp_val; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_fp_single_0 = io_lsu_lxcpt_bits_uop_fp_single; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_xcpt_pf_if_0 = io_lsu_lxcpt_bits_uop_xcpt_pf_if; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_xcpt_ae_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ae_if; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_xcpt_ma_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ma_if; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_bp_debug_if_0 = io_lsu_lxcpt_bits_uop_bp_debug_if; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_bp_xcpt_if_0 = io_lsu_lxcpt_bits_uop_bp_xcpt_if; // @[core.scala:51:7]
wire [1:0] io_lsu_lxcpt_bits_uop_debug_fsrc_0 = io_lsu_lxcpt_bits_uop_debug_fsrc; // @[core.scala:51:7]
wire [1:0] io_lsu_lxcpt_bits_uop_debug_tsrc_0 = io_lsu_lxcpt_bits_uop_debug_tsrc; // @[core.scala:51:7]
wire [4:0] io_lsu_lxcpt_bits_cause_0 = io_lsu_lxcpt_bits_cause; // @[core.scala:51:7]
wire [39:0] io_lsu_lxcpt_bits_badvaddr_0 = io_lsu_lxcpt_bits_badvaddr; // @[core.scala:51:7]
wire io_lsu_perf_acquire_0 = io_lsu_perf_acquire; // @[core.scala:51:7]
wire io_lsu_perf_release_0 = io_lsu_perf_release; // @[core.scala:51:7]
wire io_lsu_perf_tlbMiss_0 = io_lsu_perf_tlbMiss; // @[core.scala:51:7]
wire io_ptw_tlb_req_ready_0 = io_ptw_tlb_req_ready; // @[core.scala:51:7]
wire io_ptw_tlb_resp_valid_0 = io_ptw_tlb_resp_valid; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_ae_ptw_0 = io_ptw_tlb_resp_bits_ae_ptw; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_ae_final_0 = io_ptw_tlb_resp_bits_ae_final; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_pf_0 = io_ptw_tlb_resp_bits_pf; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_gf_0 = io_ptw_tlb_resp_bits_gf; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_hr_0 = io_ptw_tlb_resp_bits_hr; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_hw_0 = io_ptw_tlb_resp_bits_hw; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_hx_0 = io_ptw_tlb_resp_bits_hx; // @[core.scala:51:7]
wire [9:0] io_ptw_tlb_resp_bits_pte_reserved_for_future_0 = io_ptw_tlb_resp_bits_pte_reserved_for_future; // @[core.scala:51:7]
wire [43:0] io_ptw_tlb_resp_bits_pte_ppn_0 = io_ptw_tlb_resp_bits_pte_ppn; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_resp_bits_pte_reserved_for_software_0 = io_ptw_tlb_resp_bits_pte_reserved_for_software; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_pte_d_0 = io_ptw_tlb_resp_bits_pte_d; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_pte_a_0 = io_ptw_tlb_resp_bits_pte_a; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_pte_g_0 = io_ptw_tlb_resp_bits_pte_g; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_pte_u_0 = io_ptw_tlb_resp_bits_pte_u; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_pte_x_0 = io_ptw_tlb_resp_bits_pte_x; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_pte_w_0 = io_ptw_tlb_resp_bits_pte_w; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_pte_r_0 = io_ptw_tlb_resp_bits_pte_r; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_pte_v_0 = io_ptw_tlb_resp_bits_pte_v; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_resp_bits_level_0 = io_ptw_tlb_resp_bits_level; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_homogeneous_0 = io_ptw_tlb_resp_bits_homogeneous; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_gpa_valid_0 = io_ptw_tlb_resp_bits_gpa_valid; // @[core.scala:51:7]
wire [38:0] io_ptw_tlb_resp_bits_gpa_bits_0 = io_ptw_tlb_resp_bits_gpa_bits; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_gpa_is_pte_0 = io_ptw_tlb_resp_bits_gpa_is_pte; // @[core.scala:51:7]
wire [3:0] io_ptw_tlb_ptbr_mode_0 = io_ptw_tlb_ptbr_mode; // @[core.scala:51:7]
wire [43:0] io_ptw_tlb_ptbr_ppn_0 = io_ptw_tlb_ptbr_ppn; // @[core.scala:51:7]
wire io_ptw_tlb_status_debug_0 = io_ptw_tlb_status_debug; // @[core.scala:51:7]
wire io_ptw_tlb_status_cease_0 = io_ptw_tlb_status_cease; // @[core.scala:51:7]
wire io_ptw_tlb_status_wfi_0 = io_ptw_tlb_status_wfi; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_status_dprv_0 = io_ptw_tlb_status_dprv; // @[core.scala:51:7]
wire io_ptw_tlb_status_dv_0 = io_ptw_tlb_status_dv; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_status_prv_0 = io_ptw_tlb_status_prv; // @[core.scala:51:7]
wire io_ptw_tlb_status_v_0 = io_ptw_tlb_status_v; // @[core.scala:51:7]
wire io_ptw_tlb_status_sd_0 = io_ptw_tlb_status_sd; // @[core.scala:51:7]
wire io_ptw_tlb_status_mpv_0 = io_ptw_tlb_status_mpv; // @[core.scala:51:7]
wire io_ptw_tlb_status_gva_0 = io_ptw_tlb_status_gva; // @[core.scala:51:7]
wire io_ptw_tlb_status_tsr_0 = io_ptw_tlb_status_tsr; // @[core.scala:51:7]
wire io_ptw_tlb_status_tw_0 = io_ptw_tlb_status_tw; // @[core.scala:51:7]
wire io_ptw_tlb_status_tvm_0 = io_ptw_tlb_status_tvm; // @[core.scala:51:7]
wire io_ptw_tlb_status_mxr_0 = io_ptw_tlb_status_mxr; // @[core.scala:51:7]
wire io_ptw_tlb_status_sum_0 = io_ptw_tlb_status_sum; // @[core.scala:51:7]
wire io_ptw_tlb_status_mprv_0 = io_ptw_tlb_status_mprv; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_status_fs_0 = io_ptw_tlb_status_fs; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_status_mpp_0 = io_ptw_tlb_status_mpp; // @[core.scala:51:7]
wire io_ptw_tlb_status_spp_0 = io_ptw_tlb_status_spp; // @[core.scala:51:7]
wire io_ptw_tlb_status_mpie_0 = io_ptw_tlb_status_mpie; // @[core.scala:51:7]
wire io_ptw_tlb_status_spie_0 = io_ptw_tlb_status_spie; // @[core.scala:51:7]
wire io_ptw_tlb_status_mie_0 = io_ptw_tlb_status_mie; // @[core.scala:51:7]
wire io_ptw_tlb_status_sie_0 = io_ptw_tlb_status_sie; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_0_cfg_l_0 = io_ptw_tlb_pmp_0_cfg_l; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_0_cfg_a_0 = io_ptw_tlb_pmp_0_cfg_a; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_0_cfg_x_0 = io_ptw_tlb_pmp_0_cfg_x; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_0_cfg_w_0 = io_ptw_tlb_pmp_0_cfg_w; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_0_cfg_r_0 = io_ptw_tlb_pmp_0_cfg_r; // @[core.scala:51:7]
wire [29:0] io_ptw_tlb_pmp_0_addr_0 = io_ptw_tlb_pmp_0_addr; // @[core.scala:51:7]
wire [31:0] io_ptw_tlb_pmp_0_mask_0 = io_ptw_tlb_pmp_0_mask; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_1_cfg_l_0 = io_ptw_tlb_pmp_1_cfg_l; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_1_cfg_a_0 = io_ptw_tlb_pmp_1_cfg_a; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_1_cfg_x_0 = io_ptw_tlb_pmp_1_cfg_x; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_1_cfg_w_0 = io_ptw_tlb_pmp_1_cfg_w; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_1_cfg_r_0 = io_ptw_tlb_pmp_1_cfg_r; // @[core.scala:51:7]
wire [29:0] io_ptw_tlb_pmp_1_addr_0 = io_ptw_tlb_pmp_1_addr; // @[core.scala:51:7]
wire [31:0] io_ptw_tlb_pmp_1_mask_0 = io_ptw_tlb_pmp_1_mask; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_2_cfg_l_0 = io_ptw_tlb_pmp_2_cfg_l; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_2_cfg_a_0 = io_ptw_tlb_pmp_2_cfg_a; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_2_cfg_x_0 = io_ptw_tlb_pmp_2_cfg_x; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_2_cfg_w_0 = io_ptw_tlb_pmp_2_cfg_w; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_2_cfg_r_0 = io_ptw_tlb_pmp_2_cfg_r; // @[core.scala:51:7]
wire [29:0] io_ptw_tlb_pmp_2_addr_0 = io_ptw_tlb_pmp_2_addr; // @[core.scala:51:7]
wire [31:0] io_ptw_tlb_pmp_2_mask_0 = io_ptw_tlb_pmp_2_mask; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_3_cfg_l_0 = io_ptw_tlb_pmp_3_cfg_l; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_3_cfg_a_0 = io_ptw_tlb_pmp_3_cfg_a; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_3_cfg_x_0 = io_ptw_tlb_pmp_3_cfg_x; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_3_cfg_w_0 = io_ptw_tlb_pmp_3_cfg_w; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_3_cfg_r_0 = io_ptw_tlb_pmp_3_cfg_r; // @[core.scala:51:7]
wire [29:0] io_ptw_tlb_pmp_3_addr_0 = io_ptw_tlb_pmp_3_addr; // @[core.scala:51:7]
wire [31:0] io_ptw_tlb_pmp_3_mask_0 = io_ptw_tlb_pmp_3_mask; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_4_cfg_l_0 = io_ptw_tlb_pmp_4_cfg_l; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_4_cfg_a_0 = io_ptw_tlb_pmp_4_cfg_a; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_4_cfg_x_0 = io_ptw_tlb_pmp_4_cfg_x; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_4_cfg_w_0 = io_ptw_tlb_pmp_4_cfg_w; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_4_cfg_r_0 = io_ptw_tlb_pmp_4_cfg_r; // @[core.scala:51:7]
wire [29:0] io_ptw_tlb_pmp_4_addr_0 = io_ptw_tlb_pmp_4_addr; // @[core.scala:51:7]
wire [31:0] io_ptw_tlb_pmp_4_mask_0 = io_ptw_tlb_pmp_4_mask; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_5_cfg_l_0 = io_ptw_tlb_pmp_5_cfg_l; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_5_cfg_a_0 = io_ptw_tlb_pmp_5_cfg_a; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_5_cfg_x_0 = io_ptw_tlb_pmp_5_cfg_x; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_5_cfg_w_0 = io_ptw_tlb_pmp_5_cfg_w; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_5_cfg_r_0 = io_ptw_tlb_pmp_5_cfg_r; // @[core.scala:51:7]
wire [29:0] io_ptw_tlb_pmp_5_addr_0 = io_ptw_tlb_pmp_5_addr; // @[core.scala:51:7]
wire [31:0] io_ptw_tlb_pmp_5_mask_0 = io_ptw_tlb_pmp_5_mask; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_6_cfg_l_0 = io_ptw_tlb_pmp_6_cfg_l; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_6_cfg_a_0 = io_ptw_tlb_pmp_6_cfg_a; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_6_cfg_x_0 = io_ptw_tlb_pmp_6_cfg_x; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_6_cfg_w_0 = io_ptw_tlb_pmp_6_cfg_w; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_6_cfg_r_0 = io_ptw_tlb_pmp_6_cfg_r; // @[core.scala:51:7]
wire [29:0] io_ptw_tlb_pmp_6_addr_0 = io_ptw_tlb_pmp_6_addr; // @[core.scala:51:7]
wire [31:0] io_ptw_tlb_pmp_6_mask_0 = io_ptw_tlb_pmp_6_mask; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_7_cfg_l_0 = io_ptw_tlb_pmp_7_cfg_l; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_7_cfg_a_0 = io_ptw_tlb_pmp_7_cfg_a; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_7_cfg_x_0 = io_ptw_tlb_pmp_7_cfg_x; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_7_cfg_w_0 = io_ptw_tlb_pmp_7_cfg_w; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_7_cfg_r_0 = io_ptw_tlb_pmp_7_cfg_r; // @[core.scala:51:7]
wire [29:0] io_ptw_tlb_pmp_7_addr_0 = io_ptw_tlb_pmp_7_addr; // @[core.scala:51:7]
wire [31:0] io_ptw_tlb_pmp_7_mask_0 = io_ptw_tlb_pmp_7_mask; // @[core.scala:51:7]
wire coreMonitorBundle_clock = clock; // @[core.scala:1405:31]
wire coreMonitorBundle_reset = reset; // @[core.scala:1405:31]
wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_uopc = 7'h0; // @[core.scala:51:7]
wire [6:0] io_rocc_cmd_bits_inst_funct = 7'h0; // @[core.scala:51:7]
wire [6:0] io_rocc_cmd_bits_inst_opcode = 7'h0; // @[core.scala:51:7]
wire [6:0] io_rocc_mem_req_bits_tag = 7'h0; // @[core.scala:51:7]
wire [6:0] io_rocc_mem_resp_bits_tag = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:51:7]
wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:147:30]
wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:148:30]
wire [6:0] pred_wakeup_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:149:26]
wire [6:0] bypasses_0_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_1_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_2_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:174:24]
wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:175:27]
wire [6:0] pred_bypasses_1_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:175:27]
wire [6:0] pred_bypasses_2_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:175:27]
wire [6:0] p_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] fast_wakeup_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:814:29]
wire [6:0] slow_wakeup_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:815:29]
wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_iq_type = 3'h0; // @[core.scala:51:7]
wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_op2_sel = 3'h0; // @[core.scala:51:7]
wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_imm_sel = 3'h0; // @[core.scala:51:7]
wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7]
wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_br_tag = 3'h0; // @[core.scala:51:7]
wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_ldq_idx = 3'h0; // @[core.scala:51:7]
wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_stq_idx = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_br_tag = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_stq_idx = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_br_tag = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_stq_idx = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_br_tag = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_stq_idx = 3'h0; // @[core.scala:51:7]
wire [2:0] io_trace_insns_0_priv = 3'h0; // @[core.scala:51:7]
wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_br_tag = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_stq_idx = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_br_tag = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_stq_idx = 3'h0; // @[core.scala:147:30]
wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_br_tag = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_stq_idx = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_br_tag = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_stq_idx = 3'h0; // @[core.scala:148:30]
wire [2:0] pred_wakeup_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:149:26]
wire [2:0] pred_wakeup_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:149:26]
wire [2:0] pred_wakeup_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:149:26]
wire [2:0] pred_wakeup_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:149:26]
wire [2:0] pred_wakeup_bits_fflags_bits_uop_br_tag = 3'h0; // @[core.scala:149:26]
wire [2:0] pred_wakeup_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[core.scala:149:26]
wire [2:0] pred_wakeup_bits_fflags_bits_uop_stq_idx = 3'h0; // @[core.scala:149:26]
wire [2:0] dec_uops_0_ctrl_op2_sel = 3'h0; // @[core.scala:158:24]
wire [2:0] dec_uops_0_ctrl_imm_sel = 3'h0; // @[core.scala:158:24]
wire [2:0] dec_uops_0_ctrl_csr_cmd = 3'h0; // @[core.scala:158:24]
wire [2:0] dec_uops_0_ldq_idx = 3'h0; // @[core.scala:158:24]
wire [2:0] dec_uops_0_stq_idx = 3'h0; // @[core.scala:158:24]
wire [2:0] bypasses_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_0_bits_fflags_bits_uop_br_tag = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_0_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_0_bits_fflags_bits_uop_stq_idx = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_fflags_bits_uop_br_tag = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_fflags_bits_uop_stq_idx = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_fflags_bits_uop_br_tag = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_fflags_bits_uop_stq_idx = 3'h0; // @[core.scala:174:24]
wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_br_tag = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_stq_idx = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_1_bits_fflags_bits_uop_br_tag = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_1_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_1_bits_fflags_bits_uop_stq_idx = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_2_bits_fflags_bits_uop_br_tag = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_2_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_2_bits_fflags_bits_uop_stq_idx = 3'h0; // @[core.scala:175:27]
wire [2:0] p_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] p_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] p_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] p_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] p_uop_br_tag = 3'h0; // @[consts.scala:269:19]
wire [2:0] p_uop_ldq_idx = 3'h0; // @[consts.scala:269:19]
wire [2:0] p_uop_stq_idx = 3'h0; // @[consts.scala:269:19]
wire [2:0] p_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] p_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] p_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] fast_wakeup_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:814:29]
wire [2:0] fast_wakeup_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:814:29]
wire [2:0] fast_wakeup_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:814:29]
wire [2:0] fast_wakeup_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:814:29]
wire [2:0] fast_wakeup_bits_fflags_bits_uop_br_tag = 3'h0; // @[core.scala:814:29]
wire [2:0] fast_wakeup_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[core.scala:814:29]
wire [2:0] fast_wakeup_bits_fflags_bits_uop_stq_idx = 3'h0; // @[core.scala:814:29]
wire [2:0] slow_wakeup_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:815:29]
wire [2:0] slow_wakeup_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:815:29]
wire [2:0] slow_wakeup_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:815:29]
wire [2:0] slow_wakeup_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:815:29]
wire [2:0] slow_wakeup_bits_fflags_bits_uop_br_tag = 3'h0; // @[core.scala:815:29]
wire [2:0] slow_wakeup_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[core.scala:815:29]
wire [2:0] slow_wakeup_bits_fflags_bits_uop_stq_idx = 3'h0; // @[core.scala:815:29]
wire [2:0] coreMonitorBundle_priv_mode = 3'h0; // @[core.scala:1405:31]
wire [9:0] io_ifu_fetchpacket_bits_uops_0_bits_fu_code = 10'h0; // @[core.scala:51:7]
wire [9:0] io_lsu_exe_0_req_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:51:7]
wire [9:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:51:7]
wire [9:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:51:7]
wire [9:0] int_iss_wakeups_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:147:30]
wire [9:0] int_iss_wakeups_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:147:30]
wire [9:0] int_ren_wakeups_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:148:30]
wire [9:0] int_ren_wakeups_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:148:30]
wire [9:0] pred_wakeup_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:149:26]
wire [9:0] bypasses_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:174:24]
wire [9:0] bypasses_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:174:24]
wire [9:0] bypasses_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:174:24]
wire [9:0] pred_bypasses_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:175:27]
wire [9:0] pred_bypasses_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:175:27]
wire [9:0] pred_bypasses_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:175:27]
wire [9:0] p_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] fast_wakeup_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:814:29]
wire [9:0] slow_wakeup_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:815:29]
wire [3:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_br_type = 4'h0; // @[core.scala:51:7]
wire [3:0] io_ifu_fetchpacket_bits_uops_0_bits_ppred = 4'h0; // @[core.scala:51:7]
wire [3:0] io_ifu_debug_ftq_idx_0 = 4'h0; // @[core.scala:51:7]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[core.scala:51:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ppred = 4'h0; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ppred = 4'h0; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ppred = 4'h0; // @[core.scala:51:7]
wire [3:0] io_lsu_dis_uops_0_bits_ppred = 4'h0; // @[core.scala:51:7]
wire [3:0] io_ptw_tlb_hgatp_mode = 4'h0; // @[core.scala:51:7]
wire [3:0] io_ptw_tlb_vsatp_mode = 4'h0; // @[core.scala:51:7]
wire [3:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_1_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_1_bits_fflags_bits_uop_ppred = 4'h0; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_2_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_2_bits_fflags_bits_uop_ppred = 4'h0; // @[core.scala:147:30]
wire [3:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_1_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_1_bits_fflags_bits_uop_ppred = 4'h0; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_2_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_2_bits_fflags_bits_uop_ppred = 4'h0; // @[core.scala:148:30]
wire [3:0] pred_wakeup_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:149:26]
wire [3:0] pred_wakeup_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[core.scala:149:26]
wire [3:0] pred_wakeup_bits_fflags_bits_uop_ppred = 4'h0; // @[core.scala:149:26]
wire [3:0] dec_uops_0_ctrl_br_type = 4'h0; // @[core.scala:158:24]
wire [3:0] dec_uops_0_ppred = 4'h0; // @[core.scala:158:24]
wire [3:0] dis_uops_0_ppred = 4'h0; // @[core.scala:167:24]
wire [3:0] bypasses_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:174:24]
wire [3:0] bypasses_0_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[core.scala:174:24]
wire [3:0] bypasses_0_bits_fflags_bits_uop_ppred = 4'h0; // @[core.scala:174:24]
wire [3:0] bypasses_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:174:24]
wire [3:0] bypasses_1_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[core.scala:174:24]
wire [3:0] bypasses_1_bits_fflags_bits_uop_ppred = 4'h0; // @[core.scala:174:24]
wire [3:0] bypasses_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:174:24]
wire [3:0] bypasses_2_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[core.scala:174:24]
wire [3:0] bypasses_2_bits_fflags_bits_uop_ppred = 4'h0; // @[core.scala:174:24]
wire [3:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:175:27]
wire [3:0] pred_bypasses_0_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[core.scala:175:27]
wire [3:0] pred_bypasses_0_bits_fflags_bits_uop_ppred = 4'h0; // @[core.scala:175:27]
wire [3:0] pred_bypasses_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:175:27]
wire [3:0] pred_bypasses_1_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[core.scala:175:27]
wire [3:0] pred_bypasses_1_bits_fflags_bits_uop_ppred = 4'h0; // @[core.scala:175:27]
wire [3:0] pred_bypasses_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:175:27]
wire [3:0] pred_bypasses_2_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[core.scala:175:27]
wire [3:0] pred_bypasses_2_bits_fflags_bits_uop_ppred = 4'h0; // @[core.scala:175:27]
wire [3:0] p_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] p_uop_ftq_idx = 4'h0; // @[consts.scala:269:19]
wire [3:0] p_uop_ppred = 4'h0; // @[consts.scala:269:19]
wire [3:0] p_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] fast_wakeup_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:814:29]
wire [3:0] fast_wakeup_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[core.scala:814:29]
wire [3:0] fast_wakeup_bits_fflags_bits_uop_ppred = 4'h0; // @[core.scala:814:29]
wire [3:0] slow_wakeup_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:815:29]
wire [3:0] slow_wakeup_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[core.scala:815:29]
wire [3:0] slow_wakeup_bits_fflags_bits_uop_ppred = 4'h0; // @[core.scala:815:29]
wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_op1_sel = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_iw_state = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_rxq_idx = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_mem_size = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_dst_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs1_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs2_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_tsrc = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_status_xs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_status_vs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_status_xs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_cmd_bits_status_dprv = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_cmd_bits_status_prv = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_cmd_bits_status_sxl = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_cmd_bits_status_uxl = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_cmd_bits_status_xs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_cmd_bits_status_fs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_cmd_bits_status_mpp = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_cmd_bits_status_vs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_mem_req_bits_size = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_mem_req_bits_dprv = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_mem_resp_bits_size = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_mem_resp_bits_dprv = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_status_xs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_status_vs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_hstatus_vsxl = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_hstatus_zero3 = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_hstatus_zero2 = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_gstatus_dprv = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_gstatus_prv = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_gstatus_sxl = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_gstatus_uxl = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_gstatus_xs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_gstatus_fs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_gstatus_mpp = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_gstatus_vs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_0_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_1_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_2_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_3_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_4_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_5_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_6_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_7_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:147:30]
wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:148:30]
wire [1:0] pred_wakeup_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:149:26]
wire [1:0] dec_uops_0_ctrl_op1_sel = 2'h0; // @[core.scala:158:24]
wire [1:0] dec_uops_0_iw_state = 2'h0; // @[core.scala:158:24]
wire [1:0] dec_uops_0_rxq_idx = 2'h0; // @[core.scala:158:24]
wire [1:0] dec_uops_0_debug_tsrc = 2'h0; // @[core.scala:158:24]
wire [1:0] bypasses_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:174:24]
wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:175:27]
wire [1:0] csr_io_counters_0_inc_sets_hi = 2'h0; // @[Events.scala:16:21]
wire [1:0] csr_io_counters_1_inc_sets_hi = 2'h0; // @[Events.scala:16:21]
wire [1:0] _youngest_com_idx_T = 2'h0; // @[core.scala:465:42]
wire [1:0] p_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] fast_wakeup_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:814:29]
wire [1:0] slow_wakeup_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:815:29]
wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_op_fcn = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_rob_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_mem_cmd = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_get_pc_0_ghist_ras_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[core.scala:51:7]
wire [4:0] io_rocc_cmd_bits_inst_rs2 = 5'h0; // @[core.scala:51:7]
wire [4:0] io_rocc_cmd_bits_inst_rs1 = 5'h0; // @[core.scala:51:7]
wire [4:0] io_rocc_cmd_bits_inst_rd = 5'h0; // @[core.scala:51:7]
wire [4:0] io_rocc_resp_bits_rd = 5'h0; // @[core.scala:51:7]
wire [4:0] io_rocc_mem_req_bits_cmd = 5'h0; // @[core.scala:51:7]
wire [4:0] io_rocc_mem_resp_bits_cmd = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_rob_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_flags = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_rob_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_flags = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_rob_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_flags = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ptw_tlb_hstatus_zero1 = 5'h0; // @[core.scala:51:7]
wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_rob_idx = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_1_bits_fflags_bits_flags = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_rob_idx = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_2_bits_fflags_bits_flags = 5'h0; // @[core.scala:147:30]
wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_rob_idx = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_1_bits_fflags_bits_flags = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_rob_idx = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_2_bits_fflags_bits_flags = 5'h0; // @[core.scala:148:30]
wire [4:0] pred_wakeup_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:149:26]
wire [4:0] pred_wakeup_bits_fflags_bits_uop_rob_idx = 5'h0; // @[core.scala:149:26]
wire [4:0] pred_wakeup_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:149:26]
wire [4:0] pred_wakeup_bits_fflags_bits_flags = 5'h0; // @[core.scala:149:26]
wire [4:0] dec_uops_0_ctrl_op_fcn = 5'h0; // @[core.scala:158:24]
wire [4:0] dec_uops_0_rob_idx = 5'h0; // @[core.scala:158:24]
wire [4:0] bypasses_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_0_bits_fflags_bits_uop_rob_idx = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_0_bits_fflags_bits_flags = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_1_bits_fflags_bits_uop_rob_idx = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_1_bits_fflags_bits_flags = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_2_bits_fflags_bits_uop_rob_idx = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_2_bits_fflags_bits_flags = 5'h0; // @[core.scala:174:24]
wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:175:27]
wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_rob_idx = 5'h0; // @[core.scala:175:27]
wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:175:27]
wire [4:0] pred_bypasses_0_bits_fflags_bits_flags = 5'h0; // @[core.scala:175:27]
wire [4:0] pred_bypasses_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:175:27]
wire [4:0] pred_bypasses_1_bits_fflags_bits_uop_rob_idx = 5'h0; // @[core.scala:175:27]
wire [4:0] pred_bypasses_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:175:27]
wire [4:0] pred_bypasses_1_bits_fflags_bits_flags = 5'h0; // @[core.scala:175:27]
wire [4:0] pred_bypasses_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:175:27]
wire [4:0] pred_bypasses_2_bits_fflags_bits_uop_rob_idx = 5'h0; // @[core.scala:175:27]
wire [4:0] pred_bypasses_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:175:27]
wire [4:0] pred_bypasses_2_bits_fflags_bits_flags = 5'h0; // @[core.scala:175:27]
wire [4:0] _new_ghist_WIRE_ras_idx = 5'h0; // @[core.scala:406:44]
wire [4:0] p_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_rob_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] fast_wakeup_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_bits_fflags_bits_uop_rob_idx = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_bits_fflags_bits_flags = 5'h0; // @[core.scala:814:29]
wire [4:0] slow_wakeup_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_bits_fflags_bits_uop_rob_idx = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_bits_fflags_bits_flags = 5'h0; // @[core.scala:815:29]
wire [4:0] coreMonitorBundle_wrdst = 5'h0; // @[core.scala:1405:31]
wire [4:0] coreMonitorBundle_rd0src = 5'h0; // @[core.scala:1405:31]
wire [4:0] coreMonitorBundle_rd1src = 5'h0; // @[core.scala:1405:31]
wire io_ifu_fetchpacket_bits_uops_0_bits_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_ctrl_is_load = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_ctrl_is_sta = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_ctrl_is_std = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_iw_p1_poisoned = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_iw_p2_poisoned = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_is_br = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_is_jalr = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_is_jal = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_prs1_busy = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_prs2_busy = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_prs3_busy = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_ppred_busy = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_exception = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_bypassable = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_mem_signed = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_is_fence = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_is_fencei = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_is_amo = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_uses_ldq = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_uses_stq = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_is_sys_pc2epc = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_is_unique = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_flush_on_commit = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_ldst_is_rs1 = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_ldst_val = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_frs3_en = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_fp_val = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_fp_single = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ma_if = 1'h0; // @[core.scala:51:7]
wire io_ifu_get_pc_0_ghist_current_saw_branch_not_taken = 1'h0; // @[core.scala:51:7]
wire io_ifu_get_pc_0_ghist_new_saw_branch_not_taken = 1'h0; // @[core.scala:51:7]
wire io_ifu_get_pc_0_ghist_new_saw_branch_taken = 1'h0; // @[core.scala:51:7]
wire io_ifu_status_mbe = 1'h0; // @[core.scala:51:7]
wire io_ifu_status_sbe = 1'h0; // @[core.scala:51:7]
wire io_ifu_status_sd_rv32 = 1'h0; // @[core.scala:51:7]
wire io_ifu_status_ube = 1'h0; // @[core.scala:51:7]
wire io_ifu_status_upie = 1'h0; // @[core.scala:51:7]
wire io_ifu_status_hie = 1'h0; // @[core.scala:51:7]
wire io_ifu_status_uie = 1'h0; // @[core.scala:51:7]
wire io_ifu_sfence_bits_hv = 1'h0; // @[core.scala:51:7]
wire io_ifu_sfence_bits_hg = 1'h0; // @[core.scala:51:7]
wire io_ptw_sfence_bits_hv = 1'h0; // @[core.scala:51:7]
wire io_ptw_sfence_bits_hg = 1'h0; // @[core.scala:51:7]
wire io_ptw_status_mbe = 1'h0; // @[core.scala:51:7]
wire io_ptw_status_sbe = 1'h0; // @[core.scala:51:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[core.scala:51:7]
wire io_ptw_status_ube = 1'h0; // @[core.scala:51:7]
wire io_ptw_status_upie = 1'h0; // @[core.scala:51:7]
wire io_ptw_status_hie = 1'h0; // @[core.scala:51:7]
wire io_ptw_status_uie = 1'h0; // @[core.scala:51:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[core.scala:51:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[core.scala:51:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[core.scala:51:7]
wire io_ptw_hstatus_hu = 1'h0; // @[core.scala:51:7]
wire io_ptw_hstatus_spvp = 1'h0; // @[core.scala:51:7]
wire io_ptw_hstatus_spv = 1'h0; // @[core.scala:51:7]
wire io_ptw_hstatus_gva = 1'h0; // @[core.scala:51:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_debug = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_cease = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_wfi = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_dv = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_v = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_sd = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_mpv = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_gva = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_mbe = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_sbe = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_tsr = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_tw = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_tvm = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_mxr = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_sum = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_mprv = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_spp = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_mpie = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_ube = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_spie = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_upie = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_mie = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_hie = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_sie = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_uie = 1'h0; // @[core.scala:51:7]
wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[core.scala:51:7]
wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[core.scala:51:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[core.scala:51:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[core.scala:51:7]
wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[core.scala:51:7]
wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[core.scala:51:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[core.scala:51:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_ready = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_valid = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_inst_xd = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_inst_xs1 = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_inst_xs2 = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_debug = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_cease = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_wfi = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_dv = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_v = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_sd = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_mpv = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_gva = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_mbe = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_sbe = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_sd_rv32 = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_tsr = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_tw = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_tvm = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_mxr = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_sum = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_mprv = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_spp = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_mpie = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_ube = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_spie = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_upie = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_mie = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_hie = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_sie = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_uie = 1'h0; // @[core.scala:51:7]
wire io_rocc_resp_ready = 1'h0; // @[core.scala:51:7]
wire io_rocc_resp_valid = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_req_ready = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_req_valid = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_req_bits_signed = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_req_bits_dv = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_req_bits_phys = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_req_bits_no_resp = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_req_bits_no_alloc = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_req_bits_no_xcpt = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s1_kill = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_nack = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_nack_cause_raw = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_kill = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_uncached = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_resp_valid = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_resp_bits_signed = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_resp_bits_dv = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_resp_bits_replay = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_resp_bits_has_data = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_replay_next = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_xcpt_ma_ld = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_xcpt_ma_st = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_xcpt_pf_ld = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_xcpt_pf_st = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_xcpt_gf_ld = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_xcpt_gf_st = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_xcpt_ae_ld = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_xcpt_ae_st = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_gpa_is_pte = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_ordered = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_store_pending = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_perf_acquire = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_perf_release = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_perf_grant = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_perf_tlbMiss = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_perf_blocked = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_keep_clock_enabled = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_clock_enabled = 1'h0; // @[core.scala:51:7]
wire io_rocc_busy = 1'h0; // @[core.scala:51:7]
wire io_rocc_interrupt = 1'h0; // @[core.scala:51:7]
wire io_rocc_exception = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_predicated = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_valid = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_sfence_bits_hv = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_sfence_bits_hg = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_predicated = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_valid = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_predicated = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_valid = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_ppred_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_clr_unsafe_0_valid = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_req_valid = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_req_bits_valid = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_req_bits_bits_need_gpa = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_req_bits_bits_vstage1 = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_req_bits_bits_stage2 = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_fragmented_superpage = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_status_mbe = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_status_sbe = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_status_sd_rv32 = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_status_ube = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_status_upie = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_status_hie = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_status_uie = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_hstatus_vtsr = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_hstatus_vtw = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_hstatus_vtvm = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_hstatus_hu = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_hstatus_spvp = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_hstatus_spv = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_hstatus_gva = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_hstatus_vsbe = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_debug = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_cease = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_wfi = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_dv = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_v = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_sd = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_mpv = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_gva = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_mbe = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_sbe = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_sd_rv32 = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_tsr = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_tw = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_tvm = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_mxr = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_sum = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_mprv = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_spp = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_mpie = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_ube = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_spie = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_upie = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_mie = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_hie = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_sie = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_uie = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_customCSRs_csrs_0_ren = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_customCSRs_csrs_0_wen = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_customCSRs_csrs_0_stall = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_customCSRs_csrs_0_set = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_customCSRs_csrs_1_ren = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_customCSRs_csrs_1_wen = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_customCSRs_csrs_1_stall = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_customCSRs_csrs_1_set = 1'h0; // @[core.scala:51:7]
wire io_trace_insns_0_valid = 1'h0; // @[core.scala:51:7]
wire io_trace_insns_0_exception = 1'h0; // @[core.scala:51:7]
wire io_trace_insns_0_interrupt = 1'h0; // @[core.scala:51:7]
wire int_iss_wakeups_1_bits_predicated = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_valid = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_predicated = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_valid = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:147:30]
wire int_ren_wakeups_1_bits_predicated = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_valid = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_predicated = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_valid = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:148:30]
wire pred_wakeup_valid = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_data = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_predicated = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_valid = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:149:26]
wire dec_uops_0_ctrl_fcn_dw = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_ctrl_is_load = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_ctrl_is_sta = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_ctrl_is_std = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_iw_p1_poisoned = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_iw_p2_poisoned = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_prs1_busy = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_prs2_busy = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_prs3_busy = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_ppred_busy = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_ldst_is_rs1 = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_xcpt_ma_if = 1'h0; // @[core.scala:158:24]
wire dis_uops_0_ppred_busy = 1'h0; // @[core.scala:167:24]
wire bypasses_0_bits_predicated = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_valid = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_predicated = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_valid = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_predicated = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_valid = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:174:24]
wire pred_bypasses_0_bits_predicated = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_valid = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_predicated = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_valid = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_predicated = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_valid = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:175:27]
wire brupdate_b2_valid = 1'h0; // @[core.scala:188:23]
wire _use_this_mispredict_T_2 = 1'h0; // @[util.scala:363:52]
wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_3 = 1'h0; // @[Events.scala:13:33]
wire hits_1 = 1'h0; // @[Events.scala:13:25]
wire hits_2 = 1'h0; // @[Events.scala:13:25]
wire hits_3 = 1'h0; // @[Events.scala:13:25]
wire _hits_WIRE_1_0 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_1 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_2 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_3 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_4 = 1'h0; // @[Events.scala:13:33]
wire hits_1_0 = 1'h0; // @[Events.scala:13:25]
wire hits_1_4 = 1'h0; // @[Events.scala:13:25]
wire _hits_WIRE_2_0 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2_1 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2_2 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2_3 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2_4 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2_5 = 1'h0; // @[Events.scala:13:33]
wire custom_csrs_csrs_0_stall = 1'h0; // @[core.scala:276:25]
wire custom_csrs_csrs_0_set = 1'h0; // @[core.scala:276:25]
wire custom_csrs_csrs_1_stall = 1'h0; // @[core.scala:276:25]
wire custom_csrs_csrs_1_set = 1'h0; // @[core.scala:276:25]
wire _new_ghist_WIRE_current_saw_branch_not_taken = 1'h0; // @[core.scala:406:44]
wire _new_ghist_WIRE_new_saw_branch_not_taken = 1'h0; // @[core.scala:406:44]
wire _new_ghist_WIRE_new_saw_branch_taken = 1'h0; // @[core.scala:406:44]
wire new_ghist_new_saw_branch_not_taken = 1'h0; // @[core.scala:406:29]
wire new_ghist_new_saw_branch_taken = 1'h0; // @[core.scala:406:29]
wire next_ghist_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:87:27]
wire next_ghist_new_saw_branch_not_taken = 1'h0; // @[frontend.scala:87:27]
wire next_ghist_new_saw_branch_taken = 1'h0; // @[frontend.scala:87:27]
wire youngest_com_idx = 1'h0; // @[core.scala:465:42]
wire _io_ifu_commit_bits_WIRE = 1'h0;
wire p_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire p_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire p_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire p_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire p_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire p_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire p_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire p_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire p_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire p_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire p_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire p_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire p_uop_taken = 1'h0; // @[consts.scala:269:19]
wire p_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire p_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire p_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire p_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire p_uop_exception = 1'h0; // @[consts.scala:269:19]
wire p_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire p_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire p_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire p_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire p_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire p_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire p_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire p_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire p_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire p_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire p_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire p_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire p_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire p_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire p_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire p_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire p_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire p_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire p_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire p_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire p_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire p_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire p_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire p_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire _dis_uops_0_ppred_busy_T_2 = 1'h0; // @[micro-op.scala:110:43]
wire _dis_uops_0_ppred_busy_T_3 = 1'h0; // @[core.scala:669:48]
wire _wait_for_rocc_T_1 = 1'h0; // @[core.scala:689:90]
wire wait_for_rocc_0 = 1'h0; // @[core.scala:689:73]
wire fast_wakeup_bits_predicated = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_valid = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:814:29]
wire slow_wakeup_bits_predicated = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_valid = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:815:29]
wire _pred_wakeup_valid_T_1 = 1'h0; // @[micro-op.scala:109:42]
wire _pred_wakeup_valid_T_2 = 1'h0; // @[core.scala:862:50]
wire _pred_wakeup_valid_T_6 = 1'h0; // @[core.scala:863:58]
wire _rob_io_csr_replay_valid_T = 1'h0; // @[core.scala:1008:58]
wire _large_T_3 = 1'h0; // @[Counters.scala:68:28]
wire coreMonitorBundle_excpt = 1'h0; // @[core.scala:1405:31]
wire coreMonitorBundle_valid = 1'h0; // @[core.scala:1405:31]
wire coreMonitorBundle_wrenx = 1'h0; // @[core.scala:1405:31]
wire coreMonitorBundle_wrenf = 1'h0; // @[core.scala:1405:31]
wire _io_rocc_exception_T = 1'h0; // @[core.scala:1424:61]
wire _io_rocc_exception_T_1 = 1'h0; // @[core.scala:1424:41]
wire [7:0] io_ifu_fetchpacket_bits_uops_0_bits_br_mask = 8'h0; // @[core.scala:51:7]
wire [7:0] io_ifu_status_zero1 = 8'h0; // @[core.scala:51:7]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[core.scala:51:7]
wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[core.scala:51:7]
wire [7:0] io_rocc_cmd_bits_status_zero1 = 8'h0; // @[core.scala:51:7]
wire [7:0] io_rocc_mem_req_bits_mask = 8'h0; // @[core.scala:51:7]
wire [7:0] io_rocc_mem_s1_data_mask = 8'h0; // @[core.scala:51:7]
wire [7:0] io_rocc_mem_resp_bits_mask = 8'h0; // @[core.scala:51:7]
wire [7:0] io_lsu_exe_0_req_bits_fflags_bits_uop_br_mask = 8'h0; // @[core.scala:51:7]
wire [7:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_br_mask = 8'h0; // @[core.scala:51:7]
wire [7:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_br_mask = 8'h0; // @[core.scala:51:7]
wire [7:0] io_ptw_tlb_status_zero1 = 8'h0; // @[core.scala:51:7]
wire [7:0] io_ptw_tlb_gstatus_zero1 = 8'h0; // @[core.scala:51:7]
wire [7:0] int_iss_wakeups_1_bits_fflags_bits_uop_br_mask = 8'h0; // @[core.scala:147:30]
wire [7:0] int_iss_wakeups_2_bits_fflags_bits_uop_br_mask = 8'h0; // @[core.scala:147:30]
wire [7:0] int_ren_wakeups_1_bits_fflags_bits_uop_br_mask = 8'h0; // @[core.scala:148:30]
wire [7:0] int_ren_wakeups_2_bits_fflags_bits_uop_br_mask = 8'h0; // @[core.scala:148:30]
wire [7:0] pred_wakeup_bits_fflags_bits_uop_br_mask = 8'h0; // @[core.scala:149:26]
wire [7:0] bypasses_0_bits_fflags_bits_uop_br_mask = 8'h0; // @[core.scala:174:24]
wire [7:0] bypasses_1_bits_fflags_bits_uop_br_mask = 8'h0; // @[core.scala:174:24]
wire [7:0] bypasses_2_bits_fflags_bits_uop_br_mask = 8'h0; // @[core.scala:174:24]
wire [7:0] pred_bypasses_0_bits_fflags_bits_uop_br_mask = 8'h0; // @[core.scala:175:27]
wire [7:0] pred_bypasses_1_bits_fflags_bits_uop_br_mask = 8'h0; // @[core.scala:175:27]
wire [7:0] pred_bypasses_2_bits_fflags_bits_uop_br_mask = 8'h0; // @[core.scala:175:27]
wire [7:0] p_uop_br_mask = 8'h0; // @[consts.scala:269:19]
wire [7:0] fast_wakeup_bits_fflags_bits_uop_br_mask = 8'h0; // @[core.scala:814:29]
wire [7:0] slow_wakeup_bits_fflags_bits_uop_br_mask = 8'h0; // @[core.scala:815:29]
wire [19:0] io_ifu_fetchpacket_bits_uops_0_bits_imm_packed = 20'h0; // @[core.scala:51:7]
wire [19:0] io_lsu_exe_0_req_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:51:7]
wire [19:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:51:7]
wire [19:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:51:7]
wire [19:0] int_iss_wakeups_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:147:30]
wire [19:0] int_iss_wakeups_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:147:30]
wire [19:0] int_ren_wakeups_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:148:30]
wire [19:0] int_ren_wakeups_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:148:30]
wire [19:0] pred_wakeup_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:149:26]
wire [19:0] bypasses_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:174:24]
wire [19:0] bypasses_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:174:24]
wire [19:0] bypasses_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:174:24]
wire [19:0] pred_bypasses_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:175:27]
wire [19:0] pred_bypasses_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:175:27]
wire [19:0] pred_bypasses_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:175:27]
wire [19:0] p_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] fast_wakeup_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:814:29]
wire [19:0] slow_wakeup_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:815:29]
wire [11:0] io_ifu_fetchpacket_bits_uops_0_bits_csr_addr = 12'h0; // @[core.scala:51:7]
wire [11:0] io_lsu_exe_0_req_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:51:7]
wire [11:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:51:7]
wire [11:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:51:7]
wire [11:0] int_iss_wakeups_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:147:30]
wire [11:0] int_iss_wakeups_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:147:30]
wire [11:0] int_ren_wakeups_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:148:30]
wire [11:0] int_ren_wakeups_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:148:30]
wire [11:0] pred_wakeup_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:149:26]
wire [11:0] dec_uops_0_csr_addr = 12'h0; // @[core.scala:158:24]
wire [11:0] bypasses_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:174:24]
wire [11:0] bypasses_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:174:24]
wire [11:0] bypasses_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:174:24]
wire [11:0] pred_bypasses_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:175:27]
wire [11:0] pred_bypasses_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:175:27]
wire [11:0] pred_bypasses_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:175:27]
wire [11:0] p_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] fast_wakeup_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:814:29]
wire [11:0] slow_wakeup_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:815:29]
wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_pdst = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_prs1 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_prs2 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_prs3 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_stale_pdst = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_ldst = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs1 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs2 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs3 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_pdst = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs1 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs2 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs3 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_pdst = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs1 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs2 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs3 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_pdst = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs1 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs2 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs3 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ptw_tlb_hstatus_vgein = 6'h0; // @[core.scala:51:7]
wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_pdst = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_prs1 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_prs2 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_prs3 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_pdst = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_prs1 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_prs2 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_prs3 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_pdst = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_prs1 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_prs2 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_prs3 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_pdst = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_prs1 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_prs2 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_prs3 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:148:30]
wire [5:0] pred_wakeup_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_fflags_bits_uop_pdst = 6'h0; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_fflags_bits_uop_prs1 = 6'h0; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_fflags_bits_uop_prs2 = 6'h0; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_fflags_bits_uop_prs3 = 6'h0; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:149:26]
wire [5:0] dec_uops_0_pdst = 6'h0; // @[core.scala:158:24]
wire [5:0] dec_uops_0_prs1 = 6'h0; // @[core.scala:158:24]
wire [5:0] dec_uops_0_prs2 = 6'h0; // @[core.scala:158:24]
wire [5:0] dec_uops_0_prs3 = 6'h0; // @[core.scala:158:24]
wire [5:0] dec_uops_0_stale_pdst = 6'h0; // @[core.scala:158:24]
wire [5:0] bypasses_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_fflags_bits_uop_pdst = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_fflags_bits_uop_prs1 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_fflags_bits_uop_prs2 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_fflags_bits_uop_prs3 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_fflags_bits_uop_pdst = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_fflags_bits_uop_prs1 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_fflags_bits_uop_prs2 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_fflags_bits_uop_prs3 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_fflags_bits_uop_pdst = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_fflags_bits_uop_prs1 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_fflags_bits_uop_prs2 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_fflags_bits_uop_prs3 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:174:24]
wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_pdst = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_prs1 = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_prs2 = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_prs3 = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_1_bits_fflags_bits_uop_pdst = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_1_bits_fflags_bits_uop_prs1 = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_1_bits_fflags_bits_uop_prs2 = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_1_bits_fflags_bits_uop_prs3 = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_1_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_1_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_2_bits_fflags_bits_uop_pdst = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_2_bits_fflags_bits_uop_prs1 = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_2_bits_fflags_bits_uop_prs2 = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_2_bits_fflags_bits_uop_prs3 = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_2_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_2_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:175:27]
wire [5:0] p_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_pdst = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_prs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_prs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_prs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_stale_pdst = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] fast_wakeup_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_fflags_bits_uop_pdst = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_fflags_bits_uop_prs1 = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_fflags_bits_uop_prs2 = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_fflags_bits_uop_prs3 = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:814:29]
wire [5:0] slow_wakeup_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_fflags_bits_uop_pdst = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_fflags_bits_uop_prs1 = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_fflags_bits_uop_prs2 = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_fflags_bits_uop_prs3 = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:815:29]
wire [63:0] io_ifu_fetchpacket_bits_uops_0_bits_exc_cause = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ifu_get_pc_0_ghist_old_history = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[core.scala:51:7]
wire [63:0] io_rocc_cmd_bits_rs1 = 64'h0; // @[core.scala:51:7]
wire [63:0] io_rocc_cmd_bits_rs2 = 64'h0; // @[core.scala:51:7]
wire [63:0] io_rocc_resp_bits_data = 64'h0; // @[core.scala:51:7]
wire [63:0] io_rocc_mem_req_bits_data = 64'h0; // @[core.scala:51:7]
wire [63:0] io_rocc_mem_s1_data_data = 64'h0; // @[core.scala:51:7]
wire [63:0] io_rocc_mem_resp_bits_data = 64'h0; // @[core.scala:51:7]
wire [63:0] io_rocc_mem_resp_bits_data_word_bypass = 64'h0; // @[core.scala:51:7]
wire [63:0] io_rocc_mem_resp_bits_data_raw = 64'h0; // @[core.scala:51:7]
wire [63:0] io_rocc_mem_resp_bits_store_data = 64'h0; // @[core.scala:51:7]
wire [63:0] io_lsu_exe_0_req_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:51:7]
wire [63:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:51:7]
wire [63:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_tlb_customCSRs_csrs_0_wdata = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_tlb_customCSRs_csrs_0_value = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_tlb_customCSRs_csrs_0_sdata = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_tlb_customCSRs_csrs_1_wdata = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_tlb_customCSRs_csrs_1_value = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_tlb_customCSRs_csrs_1_sdata = 64'h0; // @[core.scala:51:7]
wire [63:0] io_trace_insns_0_cause = 64'h0; // @[core.scala:51:7]
wire [63:0] int_iss_wakeups_1_bits_data = 64'h0; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_2_bits_data = 64'h0; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:147:30]
wire [63:0] int_ren_wakeups_1_bits_data = 64'h0; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_2_bits_data = 64'h0; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:148:30]
wire [63:0] pred_wakeup_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:149:26]
wire [63:0] bypasses_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:174:24]
wire [63:0] bypasses_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:174:24]
wire [63:0] bypasses_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:174:24]
wire [63:0] pred_bypasses_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:175:27]
wire [63:0] pred_bypasses_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:175:27]
wire [63:0] pred_bypasses_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:175:27]
wire [63:0] custom_csrs_csrs_0_sdata = 64'h0; // @[core.scala:276:25]
wire [63:0] custom_csrs_csrs_1_sdata = 64'h0; // @[core.scala:276:25]
wire [63:0] _new_ghist_WIRE_old_history = 64'h0; // @[core.scala:406:44]
wire [63:0] new_ghist_old_history = 64'h0; // @[core.scala:406:29]
wire [63:0] p_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] fast_wakeup_bits_data = 64'h0; // @[core.scala:814:29]
wire [63:0] fast_wakeup_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:814:29]
wire [63:0] slow_wakeup_bits_data = 64'h0; // @[core.scala:815:29]
wire [63:0] slow_wakeup_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:815:29]
wire [63:0] coreMonitorBundle_hartid = 64'h0; // @[core.scala:1405:31]
wire [63:0] coreMonitorBundle_pc = 64'h0; // @[core.scala:1405:31]
wire [63:0] coreMonitorBundle_wrdata = 64'h0; // @[core.scala:1405:31]
wire [63:0] coreMonitorBundle_rd0val = 64'h0; // @[core.scala:1405:31]
wire [63:0] coreMonitorBundle_rd1val = 64'h0; // @[core.scala:1405:31]
wire [31:0] io_ifu_status_isa = 32'h14112D; // @[core.scala:51:7]
wire [31:0] io_ptw_status_isa = 32'h14112D; // @[core.scala:51:7]
wire [31:0] io_ptw_tlb_status_isa = 32'h14112D; // @[core.scala:51:7]
wire [22:0] io_ifu_status_zero2 = 23'h0; // @[core.scala:51:7]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[core.scala:51:7]
wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[core.scala:51:7]
wire [22:0] io_rocc_cmd_bits_status_zero2 = 23'h0; // @[core.scala:51:7]
wire [22:0] io_ptw_tlb_status_zero2 = 23'h0; // @[core.scala:51:7]
wire [22:0] io_ptw_tlb_gstatus_zero2 = 23'h0; // @[core.scala:51:7]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[core.scala:51:7]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[core.scala:51:7]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[core.scala:51:7]
wire [15:0] io_ptw_tlb_ptbr_asid = 16'h0; // @[core.scala:51:7]
wire [15:0] io_ptw_tlb_hgatp_asid = 16'h0; // @[core.scala:51:7]
wire [15:0] io_ptw_tlb_vsatp_asid = 16'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_status_sxl = 2'h2; // @[core.scala:51:7]
wire [1:0] io_ifu_status_uxl = 2'h2; // @[core.scala:51:7]
wire [1:0] io_ptw_status_sxl = 2'h2; // @[core.scala:51:7]
wire [1:0] io_ptw_status_uxl = 2'h2; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_status_sxl = 2'h2; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_status_uxl = 2'h2; // @[core.scala:51:7]
wire [1:0] p_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[core.scala:51:7]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[core.scala:51:7]
wire [43:0] io_ptw_tlb_hgatp_ppn = 44'h0; // @[core.scala:51:7]
wire [43:0] io_ptw_tlb_vsatp_ppn = 44'h0; // @[core.scala:51:7]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[core.scala:51:7]
wire [29:0] io_ptw_tlb_hstatus_zero6 = 30'h0; // @[core.scala:51:7]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[core.scala:51:7]
wire [8:0] io_ptw_tlb_hstatus_zero5 = 9'h0; // @[core.scala:51:7]
wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[core.scala:51:7]
wire [31:0] io_rocc_cmd_bits_status_isa = 32'h0; // @[core.scala:51:7]
wire [31:0] io_rocc_mem_s2_paddr = 32'h0; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_req_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:51:7]
wire [31:0] io_ptw_tlb_gstatus_isa = 32'h0; // @[core.scala:51:7]
wire [31:0] io_trace_insns_0_insn = 32'h0; // @[core.scala:51:7]
wire [31:0] int_iss_wakeups_1_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_2_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:147:30]
wire [31:0] int_ren_wakeups_1_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_2_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:148:30]
wire [31:0] pred_wakeup_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:149:26]
wire [31:0] pred_wakeup_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:149:26]
wire [31:0] bypasses_0_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:174:24]
wire [31:0] bypasses_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:174:24]
wire [31:0] bypasses_1_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:174:24]
wire [31:0] bypasses_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:174:24]
wire [31:0] bypasses_2_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:174:24]
wire [31:0] bypasses_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:174:24]
wire [31:0] pred_bypasses_0_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:175:27]
wire [31:0] pred_bypasses_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:175:27]
wire [31:0] pred_bypasses_1_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:175:27]
wire [31:0] pred_bypasses_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:175:27]
wire [31:0] pred_bypasses_2_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:175:27]
wire [31:0] pred_bypasses_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:175:27]
wire [31:0] p_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] p_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] fast_wakeup_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:814:29]
wire [31:0] fast_wakeup_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:814:29]
wire [31:0] slow_wakeup_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:815:29]
wire [31:0] slow_wakeup_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:815:29]
wire [31:0] coreMonitorBundle_timer = 32'h0; // @[core.scala:1405:31]
wire [31:0] coreMonitorBundle_inst = 32'h0; // @[core.scala:1405:31]
wire [39:0] io_rocc_mem_req_bits_addr = 40'h0; // @[core.scala:51:7]
wire [39:0] io_rocc_mem_resp_bits_addr = 40'h0; // @[core.scala:51:7]
wire [39:0] io_rocc_mem_s2_gpa = 40'h0; // @[core.scala:51:7]
wire [39:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:51:7]
wire [39:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:51:7]
wire [39:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:51:7]
wire [39:0] io_trace_insns_0_iaddr = 40'h0; // @[core.scala:51:7]
wire [39:0] io_trace_insns_0_tval = 40'h0; // @[core.scala:51:7]
wire [39:0] int_iss_wakeups_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:147:30]
wire [39:0] int_iss_wakeups_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:147:30]
wire [39:0] int_ren_wakeups_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:148:30]
wire [39:0] int_ren_wakeups_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:148:30]
wire [39:0] pred_wakeup_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:149:26]
wire [39:0] bypasses_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:174:24]
wire [39:0] bypasses_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:174:24]
wire [39:0] bypasses_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:174:24]
wire [39:0] pred_bypasses_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:175:27]
wire [39:0] pred_bypasses_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:175:27]
wire [39:0] pred_bypasses_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:175:27]
wire [39:0] p_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] fast_wakeup_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:814:29]
wire [39:0] slow_wakeup_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:815:29]
wire io_lsu_exe_0_iresp_ready = 1'h1; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_ready = 1'h1; // @[core.scala:51:7]
wire _use_this_mispredict_T = 1'h1; // @[core.scala:206:31]
wire use_this_mispredict = 1'h1; // @[core.scala:206:47]
wire new_ghist_current_saw_branch_not_taken = 1'h1; // @[core.scala:406:29]
wire flush_pc_req_ready = 1'h1; // @[core.scala:524:26]
wire _large_T_1 = 1'h1; // @[Counters.scala:51:36]
wire [26:0] io_ptw_tlb_req_bits_bits_addr = 27'h0; // @[core.scala:51:7]
wire [4:0] _pause_mem_T = 5'h1F; // @[core.scala:912:77]
wire [3:0] _cfi_idx_T_1 = 4'h8; // @[core.scala:442:45]
wire [3:0] _next_ghist_not_taken_branches_T_11 = 4'hF; // @[frontend.scala:91:45]
wire dec_ready; // @[core.scala:161:24]
wire [4:0] new_ghist_ras_idx = io_ifu_get_pc_0_entry_ras_idx_0; // @[core.scala:51:7, :406:29]
wire _cfi_idx_T = io_ifu_get_pc_1_entry_start_bank_0; // @[core.scala:51:7, :442:32]
wire io_ptw_sfence_valid_0 = io_ifu_sfence_valid_0; // @[core.scala:51:7]
wire io_ptw_sfence_bits_rs1_0 = io_ifu_sfence_bits_rs1_0; // @[core.scala:51:7]
wire io_ptw_sfence_bits_rs2_0 = io_ifu_sfence_bits_rs2_0; // @[core.scala:51:7]
wire [38:0] io_ptw_sfence_bits_addr_0 = io_ifu_sfence_bits_addr_0; // @[core.scala:51:7]
wire io_ptw_sfence_bits_asid_0 = io_ifu_sfence_bits_asid_0; // @[core.scala:51:7]
wire [7:0] brupdate_b1_resolve_mask; // @[core.scala:188:23]
wire [7:0] brupdate_b1_mispredict_mask; // @[core.scala:188:23]
wire [6:0] brupdate_b2_uop_uopc; // @[core.scala:188:23]
wire [31:0] brupdate_b2_uop_inst; // @[core.scala:188:23]
wire [31:0] brupdate_b2_uop_debug_inst; // @[core.scala:188:23]
wire brupdate_b2_uop_is_rvc; // @[core.scala:188:23]
wire [39:0] brupdate_b2_uop_debug_pc; // @[core.scala:188:23]
wire [2:0] brupdate_b2_uop_iq_type; // @[core.scala:188:23]
wire [9:0] brupdate_b2_uop_fu_code; // @[core.scala:188:23]
wire [3:0] brupdate_b2_uop_ctrl_br_type; // @[core.scala:188:23]
wire [1:0] brupdate_b2_uop_ctrl_op1_sel; // @[core.scala:188:23]
wire [2:0] brupdate_b2_uop_ctrl_op2_sel; // @[core.scala:188:23]
wire [2:0] brupdate_b2_uop_ctrl_imm_sel; // @[core.scala:188:23]
wire [4:0] brupdate_b2_uop_ctrl_op_fcn; // @[core.scala:188:23]
wire brupdate_b2_uop_ctrl_fcn_dw; // @[core.scala:188:23]
wire [2:0] brupdate_b2_uop_ctrl_csr_cmd; // @[core.scala:188:23]
wire brupdate_b2_uop_ctrl_is_load; // @[core.scala:188:23]
wire brupdate_b2_uop_ctrl_is_sta; // @[core.scala:188:23]
wire brupdate_b2_uop_ctrl_is_std; // @[core.scala:188:23]
wire [1:0] brupdate_b2_uop_iw_state; // @[core.scala:188:23]
wire brupdate_b2_uop_iw_p1_poisoned; // @[core.scala:188:23]
wire brupdate_b2_uop_iw_p2_poisoned; // @[core.scala:188:23]
wire brupdate_b2_uop_is_br; // @[core.scala:188:23]
wire brupdate_b2_uop_is_jalr; // @[core.scala:188:23]
wire brupdate_b2_uop_is_jal; // @[core.scala:188:23]
wire brupdate_b2_uop_is_sfb; // @[core.scala:188:23]
wire [7:0] brupdate_b2_uop_br_mask; // @[core.scala:188:23]
wire [2:0] brupdate_b2_uop_br_tag; // @[core.scala:188:23]
wire [3:0] brupdate_b2_uop_ftq_idx; // @[core.scala:188:23]
wire brupdate_b2_uop_edge_inst; // @[core.scala:188:23]
wire [5:0] brupdate_b2_uop_pc_lob; // @[core.scala:188:23]
wire brupdate_b2_uop_taken; // @[core.scala:188:23]
wire [19:0] brupdate_b2_uop_imm_packed; // @[core.scala:188:23]
wire [11:0] brupdate_b2_uop_csr_addr; // @[core.scala:188:23]
wire [4:0] brupdate_b2_uop_rob_idx; // @[core.scala:188:23]
wire [2:0] brupdate_b2_uop_ldq_idx; // @[core.scala:188:23]
wire [2:0] brupdate_b2_uop_stq_idx; // @[core.scala:188:23]
wire [1:0] brupdate_b2_uop_rxq_idx; // @[core.scala:188:23]
wire [5:0] brupdate_b2_uop_pdst; // @[core.scala:188:23]
wire [5:0] brupdate_b2_uop_prs1; // @[core.scala:188:23]
wire [5:0] brupdate_b2_uop_prs2; // @[core.scala:188:23]
wire [5:0] brupdate_b2_uop_prs3; // @[core.scala:188:23]
wire [3:0] brupdate_b2_uop_ppred; // @[core.scala:188:23]
wire brupdate_b2_uop_prs1_busy; // @[core.scala:188:23]
wire brupdate_b2_uop_prs2_busy; // @[core.scala:188:23]
wire brupdate_b2_uop_prs3_busy; // @[core.scala:188:23]
wire brupdate_b2_uop_ppred_busy; // @[core.scala:188:23]
wire [5:0] brupdate_b2_uop_stale_pdst; // @[core.scala:188:23]
wire brupdate_b2_uop_exception; // @[core.scala:188:23]
wire [63:0] brupdate_b2_uop_exc_cause; // @[core.scala:188:23]
wire brupdate_b2_uop_bypassable; // @[core.scala:188:23]
wire [4:0] brupdate_b2_uop_mem_cmd; // @[core.scala:188:23]
wire [1:0] brupdate_b2_uop_mem_size; // @[core.scala:188:23]
wire brupdate_b2_uop_mem_signed; // @[core.scala:188:23]
wire brupdate_b2_uop_is_fence; // @[core.scala:188:23]
wire brupdate_b2_uop_is_fencei; // @[core.scala:188:23]
wire brupdate_b2_uop_is_amo; // @[core.scala:188:23]
wire brupdate_b2_uop_uses_ldq; // @[core.scala:188:23]
wire brupdate_b2_uop_uses_stq; // @[core.scala:188:23]
wire brupdate_b2_uop_is_sys_pc2epc; // @[core.scala:188:23]
wire brupdate_b2_uop_is_unique; // @[core.scala:188:23]
wire brupdate_b2_uop_flush_on_commit; // @[core.scala:188:23]
wire brupdate_b2_uop_ldst_is_rs1; // @[core.scala:188:23]
wire [5:0] brupdate_b2_uop_ldst; // @[core.scala:188:23]
wire [5:0] brupdate_b2_uop_lrs1; // @[core.scala:188:23]
wire [5:0] brupdate_b2_uop_lrs2; // @[core.scala:188:23]
wire [5:0] brupdate_b2_uop_lrs3; // @[core.scala:188:23]
wire brupdate_b2_uop_ldst_val; // @[core.scala:188:23]
wire [1:0] brupdate_b2_uop_dst_rtype; // @[core.scala:188:23]
wire [1:0] brupdate_b2_uop_lrs1_rtype; // @[core.scala:188:23]
wire [1:0] brupdate_b2_uop_lrs2_rtype; // @[core.scala:188:23]
wire brupdate_b2_uop_frs3_en; // @[core.scala:188:23]
wire brupdate_b2_uop_fp_val; // @[core.scala:188:23]
wire brupdate_b2_uop_fp_single; // @[core.scala:188:23]
wire brupdate_b2_uop_xcpt_pf_if; // @[core.scala:188:23]
wire brupdate_b2_uop_xcpt_ae_if; // @[core.scala:188:23]
wire brupdate_b2_uop_xcpt_ma_if; // @[core.scala:188:23]
wire brupdate_b2_uop_bp_debug_if; // @[core.scala:188:23]
wire brupdate_b2_uop_bp_xcpt_if; // @[core.scala:188:23]
wire [1:0] brupdate_b2_uop_debug_fsrc; // @[core.scala:188:23]
wire [1:0] brupdate_b2_uop_debug_tsrc; // @[core.scala:188:23]
wire brupdate_b2_mispredict; // @[core.scala:188:23]
wire brupdate_b2_taken; // @[core.scala:188:23]
wire [2:0] brupdate_b2_cfi_type; // @[core.scala:188:23]
wire [1:0] brupdate_b2_pc_sel; // @[core.scala:188:23]
wire [39:0] brupdate_b2_jalr_target; // @[core.scala:188:23]
wire [20:0] brupdate_b2_target_offset; // @[core.scala:188:23]
wire _io_ifu_flush_icache_T_3; // @[core.scala:388:71]
wire hits_2_0 = io_ifu_perf_acquire_0; // @[Events.scala:13:25]
wire hits_2_3 = io_ifu_perf_tlbMiss_0; // @[Events.scala:13:25]
wire hits_2_5 = io_ptw_perf_l2miss_0; // @[Events.scala:13:25]
wire dis_fire_0; // @[core.scala:168:24]
wire [6:0] dis_uops_0_uopc; // @[core.scala:167:24]
wire [31:0] dis_uops_0_inst; // @[core.scala:167:24]
wire [31:0] dis_uops_0_debug_inst; // @[core.scala:167:24]
wire dis_uops_0_is_rvc; // @[core.scala:167:24]
wire [39:0] dis_uops_0_debug_pc; // @[core.scala:167:24]
wire [2:0] dis_uops_0_iq_type; // @[core.scala:167:24]
wire [9:0] dis_uops_0_fu_code; // @[core.scala:167:24]
wire [3:0] dis_uops_0_ctrl_br_type; // @[core.scala:167:24]
wire [1:0] dis_uops_0_ctrl_op1_sel; // @[core.scala:167:24]
wire [2:0] dis_uops_0_ctrl_op2_sel; // @[core.scala:167:24]
wire [2:0] dis_uops_0_ctrl_imm_sel; // @[core.scala:167:24]
wire [4:0] dis_uops_0_ctrl_op_fcn; // @[core.scala:167:24]
wire dis_uops_0_ctrl_fcn_dw; // @[core.scala:167:24]
wire [2:0] dis_uops_0_ctrl_csr_cmd; // @[core.scala:167:24]
wire dis_uops_0_ctrl_is_load; // @[core.scala:167:24]
wire dis_uops_0_ctrl_is_sta; // @[core.scala:167:24]
wire dis_uops_0_ctrl_is_std; // @[core.scala:167:24]
wire [1:0] dis_uops_0_iw_state; // @[core.scala:167:24]
wire dis_uops_0_iw_p1_poisoned; // @[core.scala:167:24]
wire dis_uops_0_iw_p2_poisoned; // @[core.scala:167:24]
wire dis_uops_0_is_br; // @[core.scala:167:24]
wire dis_uops_0_is_jalr; // @[core.scala:167:24]
wire dis_uops_0_is_jal; // @[core.scala:167:24]
wire dis_uops_0_is_sfb; // @[core.scala:167:24]
wire [7:0] dis_uops_0_br_mask; // @[core.scala:167:24]
wire [2:0] dis_uops_0_br_tag; // @[core.scala:167:24]
wire [3:0] dis_uops_0_ftq_idx; // @[core.scala:167:24]
wire dis_uops_0_edge_inst; // @[core.scala:167:24]
wire [5:0] dis_uops_0_pc_lob; // @[core.scala:167:24]
wire dis_uops_0_taken; // @[core.scala:167:24]
wire [19:0] dis_uops_0_imm_packed; // @[core.scala:167:24]
wire [11:0] dis_uops_0_csr_addr; // @[core.scala:167:24]
wire [4:0] dis_uops_0_rob_idx; // @[core.scala:167:24]
wire [2:0] dis_uops_0_ldq_idx; // @[core.scala:167:24]
wire [2:0] dis_uops_0_stq_idx; // @[core.scala:167:24]
wire [1:0] dis_uops_0_rxq_idx; // @[core.scala:167:24]
wire [5:0] dis_uops_0_pdst; // @[core.scala:167:24]
wire [5:0] dis_uops_0_prs1; // @[core.scala:167:24]
wire [5:0] dis_uops_0_prs2; // @[core.scala:167:24]
wire [5:0] dis_uops_0_prs3; // @[core.scala:167:24]
wire dis_uops_0_prs1_busy; // @[core.scala:167:24]
wire dis_uops_0_prs2_busy; // @[core.scala:167:24]
wire dis_uops_0_prs3_busy; // @[core.scala:167:24]
wire [5:0] dis_uops_0_stale_pdst; // @[core.scala:167:24]
wire dis_uops_0_exception; // @[core.scala:167:24]
wire [63:0] dis_uops_0_exc_cause; // @[core.scala:167:24]
wire dis_uops_0_bypassable; // @[core.scala:167:24]
wire [4:0] dis_uops_0_mem_cmd; // @[core.scala:167:24]
wire [1:0] dis_uops_0_mem_size; // @[core.scala:167:24]
wire dis_uops_0_mem_signed; // @[core.scala:167:24]
wire dis_uops_0_is_fence; // @[core.scala:167:24]
wire dis_uops_0_is_fencei; // @[core.scala:167:24]
wire dis_uops_0_is_amo; // @[core.scala:167:24]
wire dis_uops_0_uses_ldq; // @[core.scala:167:24]
wire dis_uops_0_uses_stq; // @[core.scala:167:24]
wire dis_uops_0_is_sys_pc2epc; // @[core.scala:167:24]
wire dis_uops_0_is_unique; // @[core.scala:167:24]
wire dis_uops_0_flush_on_commit; // @[core.scala:167:24]
wire dis_uops_0_ldst_is_rs1; // @[core.scala:167:24]
wire [5:0] dis_uops_0_ldst; // @[core.scala:167:24]
wire [5:0] dis_uops_0_lrs1; // @[core.scala:167:24]
wire [5:0] dis_uops_0_lrs2; // @[core.scala:167:24]
wire [5:0] dis_uops_0_lrs3; // @[core.scala:167:24]
wire dis_uops_0_ldst_val; // @[core.scala:167:24]
wire [1:0] dis_uops_0_dst_rtype; // @[core.scala:167:24]
wire [1:0] dis_uops_0_lrs1_rtype; // @[core.scala:167:24]
wire [1:0] dis_uops_0_lrs2_rtype; // @[core.scala:167:24]
wire dis_uops_0_frs3_en; // @[core.scala:167:24]
wire dis_uops_0_fp_val; // @[core.scala:167:24]
wire dis_uops_0_fp_single; // @[core.scala:167:24]
wire dis_uops_0_xcpt_pf_if; // @[core.scala:167:24]
wire dis_uops_0_xcpt_ae_if; // @[core.scala:167:24]
wire dis_uops_0_xcpt_ma_if; // @[core.scala:167:24]
wire dis_uops_0_bp_debug_if; // @[core.scala:167:24]
wire dis_uops_0_bp_xcpt_if; // @[core.scala:167:24]
wire [1:0] dis_uops_0_debug_fsrc; // @[core.scala:167:24]
wire [1:0] dis_uops_0_debug_tsrc; // @[core.scala:167:24]
assign dis_uops_0_ldq_idx = io_lsu_dis_ldq_idx_0_0; // @[core.scala:51:7, :167:24]
assign dis_uops_0_stq_idx = io_lsu_dis_stq_idx_0_0; // @[core.scala:51:7, :167:24]
wire _io_lsu_fence_dmem_T; // @[core.scala:711:86]
wire hits_2_1 = io_lsu_perf_acquire_0; // @[Events.scala:13:25]
wire hits_2_2 = io_lsu_perf_release_0; // @[Events.scala:13:25]
wire hits_2_4 = io_lsu_perf_tlbMiss_0; // @[Events.scala:13:25]
wire io_ifu_fetchpacket_ready_0; // @[core.scala:51:7]
wire [3:0] io_ifu_get_pc_0_ftq_idx_0; // @[core.scala:51:7]
wire [3:0] io_ifu_get_pc_1_ftq_idx_0; // @[core.scala:51:7]
wire io_ifu_status_debug_0; // @[core.scala:51:7]
wire io_ifu_status_cease_0; // @[core.scala:51:7]
wire io_ifu_status_wfi_0; // @[core.scala:51:7]
wire [1:0] io_ifu_status_dprv_0; // @[core.scala:51:7]
wire io_ifu_status_dv_0; // @[core.scala:51:7]
wire [1:0] io_ifu_status_prv_0; // @[core.scala:51:7]
wire io_ifu_status_v_0; // @[core.scala:51:7]
wire io_ifu_status_sd_0; // @[core.scala:51:7]
wire io_ifu_status_mpv_0; // @[core.scala:51:7]
wire io_ifu_status_gva_0; // @[core.scala:51:7]
wire io_ifu_status_tsr_0; // @[core.scala:51:7]
wire io_ifu_status_tw_0; // @[core.scala:51:7]
wire io_ifu_status_tvm_0; // @[core.scala:51:7]
wire io_ifu_status_mxr_0; // @[core.scala:51:7]
wire io_ifu_status_sum_0; // @[core.scala:51:7]
wire io_ifu_status_mprv_0; // @[core.scala:51:7]
wire [1:0] io_ifu_status_fs_0; // @[core.scala:51:7]
wire [1:0] io_ifu_status_mpp_0; // @[core.scala:51:7]
wire io_ifu_status_spp_0; // @[core.scala:51:7]
wire io_ifu_status_mpie_0; // @[core.scala:51:7]
wire io_ifu_status_spie_0; // @[core.scala:51:7]
wire io_ifu_status_mie_0; // @[core.scala:51:7]
wire io_ifu_status_sie_0; // @[core.scala:51:7]
wire [7:0] io_ifu_brupdate_b1_resolve_mask_0; // @[core.scala:51:7]
wire [7:0] io_ifu_brupdate_b1_mispredict_mask_0; // @[core.scala:51:7]
wire [3:0] io_ifu_brupdate_b2_uop_ctrl_br_type_0; // @[core.scala:51:7]
wire [1:0] io_ifu_brupdate_b2_uop_ctrl_op1_sel_0; // @[core.scala:51:7]
wire [2:0] io_ifu_brupdate_b2_uop_ctrl_op2_sel_0; // @[core.scala:51:7]
wire [2:0] io_ifu_brupdate_b2_uop_ctrl_imm_sel_0; // @[core.scala:51:7]
wire [4:0] io_ifu_brupdate_b2_uop_ctrl_op_fcn_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_ctrl_fcn_dw_0; // @[core.scala:51:7]
wire [2:0] io_ifu_brupdate_b2_uop_ctrl_csr_cmd_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_ctrl_is_load_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_ctrl_is_sta_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_ctrl_is_std_0; // @[core.scala:51:7]
wire [6:0] io_ifu_brupdate_b2_uop_uopc_0; // @[core.scala:51:7]
wire [31:0] io_ifu_brupdate_b2_uop_inst_0; // @[core.scala:51:7]
wire [31:0] io_ifu_brupdate_b2_uop_debug_inst_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_is_rvc_0; // @[core.scala:51:7]
wire [39:0] io_ifu_brupdate_b2_uop_debug_pc_0; // @[core.scala:51:7]
wire [2:0] io_ifu_brupdate_b2_uop_iq_type_0; // @[core.scala:51:7]
wire [9:0] io_ifu_brupdate_b2_uop_fu_code_0; // @[core.scala:51:7]
wire [1:0] io_ifu_brupdate_b2_uop_iw_state_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_iw_p1_poisoned_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_iw_p2_poisoned_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_is_br_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_is_jalr_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_is_jal_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_is_sfb_0; // @[core.scala:51:7]
wire [7:0] io_ifu_brupdate_b2_uop_br_mask_0; // @[core.scala:51:7]
wire [2:0] io_ifu_brupdate_b2_uop_br_tag_0; // @[core.scala:51:7]
wire [3:0] io_ifu_brupdate_b2_uop_ftq_idx_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_edge_inst_0; // @[core.scala:51:7]
wire [5:0] io_ifu_brupdate_b2_uop_pc_lob_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_taken_0; // @[core.scala:51:7]
wire [19:0] io_ifu_brupdate_b2_uop_imm_packed_0; // @[core.scala:51:7]
wire [11:0] io_ifu_brupdate_b2_uop_csr_addr_0; // @[core.scala:51:7]
wire [4:0] io_ifu_brupdate_b2_uop_rob_idx_0; // @[core.scala:51:7]
wire [2:0] io_ifu_brupdate_b2_uop_ldq_idx_0; // @[core.scala:51:7]
wire [2:0] io_ifu_brupdate_b2_uop_stq_idx_0; // @[core.scala:51:7]
wire [1:0] io_ifu_brupdate_b2_uop_rxq_idx_0; // @[core.scala:51:7]
wire [5:0] io_ifu_brupdate_b2_uop_pdst_0; // @[core.scala:51:7]
wire [5:0] io_ifu_brupdate_b2_uop_prs1_0; // @[core.scala:51:7]
wire [5:0] io_ifu_brupdate_b2_uop_prs2_0; // @[core.scala:51:7]
wire [5:0] io_ifu_brupdate_b2_uop_prs3_0; // @[core.scala:51:7]
wire [3:0] io_ifu_brupdate_b2_uop_ppred_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_prs1_busy_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_prs2_busy_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_prs3_busy_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_ppred_busy_0; // @[core.scala:51:7]
wire [5:0] io_ifu_brupdate_b2_uop_stale_pdst_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_exception_0; // @[core.scala:51:7]
wire [63:0] io_ifu_brupdate_b2_uop_exc_cause_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_bypassable_0; // @[core.scala:51:7]
wire [4:0] io_ifu_brupdate_b2_uop_mem_cmd_0; // @[core.scala:51:7]
wire [1:0] io_ifu_brupdate_b2_uop_mem_size_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_mem_signed_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_is_fence_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_is_fencei_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_is_amo_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_uses_ldq_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_uses_stq_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_is_sys_pc2epc_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_is_unique_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_flush_on_commit_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_ldst_is_rs1_0; // @[core.scala:51:7]
wire [5:0] io_ifu_brupdate_b2_uop_ldst_0; // @[core.scala:51:7]
wire [5:0] io_ifu_brupdate_b2_uop_lrs1_0; // @[core.scala:51:7]
wire [5:0] io_ifu_brupdate_b2_uop_lrs2_0; // @[core.scala:51:7]
wire [5:0] io_ifu_brupdate_b2_uop_lrs3_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_ldst_val_0; // @[core.scala:51:7]
wire [1:0] io_ifu_brupdate_b2_uop_dst_rtype_0; // @[core.scala:51:7]
wire [1:0] io_ifu_brupdate_b2_uop_lrs1_rtype_0; // @[core.scala:51:7]
wire [1:0] io_ifu_brupdate_b2_uop_lrs2_rtype_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_frs3_en_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_fp_val_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_fp_single_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_xcpt_pf_if_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_xcpt_ae_if_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_xcpt_ma_if_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_bp_debug_if_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_bp_xcpt_if_0; // @[core.scala:51:7]
wire [1:0] io_ifu_brupdate_b2_uop_debug_fsrc_0; // @[core.scala:51:7]
wire [1:0] io_ifu_brupdate_b2_uop_debug_tsrc_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_valid_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_mispredict_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_taken_0; // @[core.scala:51:7]
wire [2:0] io_ifu_brupdate_b2_cfi_type_0; // @[core.scala:51:7]
wire [1:0] io_ifu_brupdate_b2_pc_sel_0; // @[core.scala:51:7]
wire [39:0] io_ifu_brupdate_b2_jalr_target_0; // @[core.scala:51:7]
wire [20:0] io_ifu_brupdate_b2_target_offset_0; // @[core.scala:51:7]
wire [63:0] io_ifu_redirect_ghist_old_history_0; // @[core.scala:51:7]
wire io_ifu_redirect_ghist_current_saw_branch_not_taken_0; // @[core.scala:51:7]
wire io_ifu_redirect_ghist_new_saw_branch_not_taken_0; // @[core.scala:51:7]
wire io_ifu_redirect_ghist_new_saw_branch_taken_0; // @[core.scala:51:7]
wire [4:0] io_ifu_redirect_ghist_ras_idx_0; // @[core.scala:51:7]
wire io_ifu_commit_valid_0; // @[core.scala:51:7]
wire [15:0] io_ifu_commit_bits_0; // @[core.scala:51:7]
wire io_ifu_redirect_flush_0; // @[core.scala:51:7]
wire io_ifu_redirect_val_0; // @[core.scala:51:7]
wire [39:0] io_ifu_redirect_pc_0; // @[core.scala:51:7]
wire [3:0] io_ifu_redirect_ftq_idx_0; // @[core.scala:51:7]
wire io_ifu_flush_icache_0; // @[core.scala:51:7]
wire [3:0] io_ptw_ptbr_mode_0; // @[core.scala:51:7]
wire [43:0] io_ptw_ptbr_ppn_0; // @[core.scala:51:7]
wire io_ptw_status_debug_0; // @[core.scala:51:7]
wire io_ptw_status_cease_0; // @[core.scala:51:7]
wire io_ptw_status_wfi_0; // @[core.scala:51:7]
wire [1:0] io_ptw_status_dprv_0; // @[core.scala:51:7]
wire io_ptw_status_dv_0; // @[core.scala:51:7]
wire [1:0] io_ptw_status_prv_0; // @[core.scala:51:7]
wire io_ptw_status_v_0; // @[core.scala:51:7]
wire io_ptw_status_sd_0; // @[core.scala:51:7]
wire io_ptw_status_mpv_0; // @[core.scala:51:7]
wire io_ptw_status_gva_0; // @[core.scala:51:7]
wire io_ptw_status_tsr_0; // @[core.scala:51:7]
wire io_ptw_status_tw_0; // @[core.scala:51:7]
wire io_ptw_status_tvm_0; // @[core.scala:51:7]
wire io_ptw_status_mxr_0; // @[core.scala:51:7]
wire io_ptw_status_sum_0; // @[core.scala:51:7]
wire io_ptw_status_mprv_0; // @[core.scala:51:7]
wire [1:0] io_ptw_status_fs_0; // @[core.scala:51:7]
wire [1:0] io_ptw_status_mpp_0; // @[core.scala:51:7]
wire io_ptw_status_spp_0; // @[core.scala:51:7]
wire io_ptw_status_mpie_0; // @[core.scala:51:7]
wire io_ptw_status_spie_0; // @[core.scala:51:7]
wire io_ptw_status_mie_0; // @[core.scala:51:7]
wire io_ptw_status_sie_0; // @[core.scala:51:7]
wire io_ptw_pmp_0_cfg_l_0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_0_cfg_a_0; // @[core.scala:51:7]
wire io_ptw_pmp_0_cfg_x_0; // @[core.scala:51:7]
wire io_ptw_pmp_0_cfg_w_0; // @[core.scala:51:7]
wire io_ptw_pmp_0_cfg_r_0; // @[core.scala:51:7]
wire [29:0] io_ptw_pmp_0_addr_0; // @[core.scala:51:7]
wire [31:0] io_ptw_pmp_0_mask_0; // @[core.scala:51:7]
wire io_ptw_pmp_1_cfg_l_0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_1_cfg_a_0; // @[core.scala:51:7]
wire io_ptw_pmp_1_cfg_x_0; // @[core.scala:51:7]
wire io_ptw_pmp_1_cfg_w_0; // @[core.scala:51:7]
wire io_ptw_pmp_1_cfg_r_0; // @[core.scala:51:7]
wire [29:0] io_ptw_pmp_1_addr_0; // @[core.scala:51:7]
wire [31:0] io_ptw_pmp_1_mask_0; // @[core.scala:51:7]
wire io_ptw_pmp_2_cfg_l_0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_2_cfg_a_0; // @[core.scala:51:7]
wire io_ptw_pmp_2_cfg_x_0; // @[core.scala:51:7]
wire io_ptw_pmp_2_cfg_w_0; // @[core.scala:51:7]
wire io_ptw_pmp_2_cfg_r_0; // @[core.scala:51:7]
wire [29:0] io_ptw_pmp_2_addr_0; // @[core.scala:51:7]
wire [31:0] io_ptw_pmp_2_mask_0; // @[core.scala:51:7]
wire io_ptw_pmp_3_cfg_l_0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_3_cfg_a_0; // @[core.scala:51:7]
wire io_ptw_pmp_3_cfg_x_0; // @[core.scala:51:7]
wire io_ptw_pmp_3_cfg_w_0; // @[core.scala:51:7]
wire io_ptw_pmp_3_cfg_r_0; // @[core.scala:51:7]
wire [29:0] io_ptw_pmp_3_addr_0; // @[core.scala:51:7]
wire [31:0] io_ptw_pmp_3_mask_0; // @[core.scala:51:7]
wire io_ptw_pmp_4_cfg_l_0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_4_cfg_a_0; // @[core.scala:51:7]
wire io_ptw_pmp_4_cfg_x_0; // @[core.scala:51:7]
wire io_ptw_pmp_4_cfg_w_0; // @[core.scala:51:7]
wire io_ptw_pmp_4_cfg_r_0; // @[core.scala:51:7]
wire [29:0] io_ptw_pmp_4_addr_0; // @[core.scala:51:7]
wire [31:0] io_ptw_pmp_4_mask_0; // @[core.scala:51:7]
wire io_ptw_pmp_5_cfg_l_0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_5_cfg_a_0; // @[core.scala:51:7]
wire io_ptw_pmp_5_cfg_x_0; // @[core.scala:51:7]
wire io_ptw_pmp_5_cfg_w_0; // @[core.scala:51:7]
wire io_ptw_pmp_5_cfg_r_0; // @[core.scala:51:7]
wire [29:0] io_ptw_pmp_5_addr_0; // @[core.scala:51:7]
wire [31:0] io_ptw_pmp_5_mask_0; // @[core.scala:51:7]
wire io_ptw_pmp_6_cfg_l_0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_6_cfg_a_0; // @[core.scala:51:7]
wire io_ptw_pmp_6_cfg_x_0; // @[core.scala:51:7]
wire io_ptw_pmp_6_cfg_w_0; // @[core.scala:51:7]
wire io_ptw_pmp_6_cfg_r_0; // @[core.scala:51:7]
wire [29:0] io_ptw_pmp_6_addr_0; // @[core.scala:51:7]
wire [31:0] io_ptw_pmp_6_mask_0; // @[core.scala:51:7]
wire io_ptw_pmp_7_cfg_l_0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_7_cfg_a_0; // @[core.scala:51:7]
wire io_ptw_pmp_7_cfg_x_0; // @[core.scala:51:7]
wire io_ptw_pmp_7_cfg_w_0; // @[core.scala:51:7]
wire io_ptw_pmp_7_cfg_r_0; // @[core.scala:51:7]
wire [29:0] io_ptw_pmp_7_addr_0; // @[core.scala:51:7]
wire [31:0] io_ptw_pmp_7_mask_0; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_req_bits_uop_ctrl_br_type_0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_ctrl_op1_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_op2_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_imm_sel_0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_req_bits_uop_ctrl_op_fcn_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw_0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_ctrl_is_load_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_ctrl_is_sta_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_ctrl_is_std_0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_req_bits_uop_uopc_0; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_req_bits_uop_inst_0; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_req_bits_uop_debug_inst_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_is_rvc_0; // @[core.scala:51:7]
wire [39:0] io_lsu_exe_0_req_bits_uop_debug_pc_0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_uop_iq_type_0; // @[core.scala:51:7]
wire [9:0] io_lsu_exe_0_req_bits_uop_fu_code_0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_iw_state_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_iw_p1_poisoned_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_iw_p2_poisoned_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_is_br_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_is_jalr_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_is_jal_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_is_sfb_0; // @[core.scala:51:7]
wire [7:0] io_lsu_exe_0_req_bits_uop_br_mask_0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_uop_br_tag_0; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_req_bits_uop_ftq_idx_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_edge_inst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_uop_pc_lob_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_taken_0; // @[core.scala:51:7]
wire [19:0] io_lsu_exe_0_req_bits_uop_imm_packed_0; // @[core.scala:51:7]
wire [11:0] io_lsu_exe_0_req_bits_uop_csr_addr_0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_req_bits_uop_rob_idx_0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_uop_ldq_idx_0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_uop_stq_idx_0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_rxq_idx_0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_uop_pdst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_uop_prs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_uop_prs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_uop_prs3_0; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_req_bits_uop_ppred_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_prs1_busy_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_prs2_busy_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_prs3_busy_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_ppred_busy_0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_uop_stale_pdst_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_exception_0; // @[core.scala:51:7]
wire [63:0] io_lsu_exe_0_req_bits_uop_exc_cause_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_bypassable_0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_req_bits_uop_mem_cmd_0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_mem_size_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_mem_signed_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_is_fence_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_is_fencei_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_is_amo_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_uses_ldq_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_uses_stq_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_is_sys_pc2epc_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_is_unique_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_flush_on_commit_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_ldst_is_rs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_uop_ldst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_uop_lrs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_uop_lrs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_uop_lrs3_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_ldst_val_0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_dst_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_lrs1_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_lrs2_rtype_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_frs3_en_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_fp_val_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_fp_single_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_xcpt_pf_if_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_xcpt_ae_if_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_xcpt_ma_if_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_bp_debug_if_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_bp_xcpt_if_0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_debug_fsrc_0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_debug_tsrc_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_mxcpt_valid_0; // @[core.scala:51:7]
wire [24:0] io_lsu_exe_0_req_bits_mxcpt_bits_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_sfence_bits_rs1_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_sfence_bits_rs2_0; // @[core.scala:51:7]
wire [38:0] io_lsu_exe_0_req_bits_sfence_bits_addr_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_sfence_bits_asid_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_sfence_valid_0; // @[core.scala:51:7]
wire [63:0] io_lsu_exe_0_req_bits_data_0; // @[core.scala:51:7]
wire [39:0] io_lsu_exe_0_req_bits_addr_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_valid_0; // @[core.scala:51:7]
wire [3:0] io_lsu_dis_uops_0_bits_ctrl_br_type_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_0_bits_ctrl_op1_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_uops_0_bits_ctrl_op2_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_uops_0_bits_ctrl_imm_sel_0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_0_bits_ctrl_op_fcn_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_ctrl_fcn_dw_0; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_uops_0_bits_ctrl_csr_cmd_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_ctrl_is_load_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_ctrl_is_sta_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_ctrl_is_std_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_0_bits_uopc_0; // @[core.scala:51:7]
wire [31:0] io_lsu_dis_uops_0_bits_inst_0; // @[core.scala:51:7]
wire [31:0] io_lsu_dis_uops_0_bits_debug_inst_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_is_rvc_0; // @[core.scala:51:7]
wire [39:0] io_lsu_dis_uops_0_bits_debug_pc_0; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_uops_0_bits_iq_type_0; // @[core.scala:51:7]
wire [9:0] io_lsu_dis_uops_0_bits_fu_code_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_0_bits_iw_state_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_iw_p1_poisoned_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_iw_p2_poisoned_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_is_br_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_is_jalr_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_is_jal_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_is_sfb_0; // @[core.scala:51:7]
wire [7:0] io_lsu_dis_uops_0_bits_br_mask_0; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_uops_0_bits_br_tag_0; // @[core.scala:51:7]
wire [3:0] io_lsu_dis_uops_0_bits_ftq_idx_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_edge_inst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_0_bits_pc_lob_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_taken_0; // @[core.scala:51:7]
wire [19:0] io_lsu_dis_uops_0_bits_imm_packed_0; // @[core.scala:51:7]
wire [11:0] io_lsu_dis_uops_0_bits_csr_addr_0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_0_bits_rob_idx_0; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_uops_0_bits_ldq_idx_0; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_uops_0_bits_stq_idx_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_0_bits_rxq_idx_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_0_bits_pdst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_0_bits_prs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_0_bits_prs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_0_bits_prs3_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_prs1_busy_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_prs2_busy_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_prs3_busy_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_0_bits_stale_pdst_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_exception_0; // @[core.scala:51:7]
wire [63:0] io_lsu_dis_uops_0_bits_exc_cause_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_bypassable_0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_0_bits_mem_cmd_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_0_bits_mem_size_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_mem_signed_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_is_fence_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_is_fencei_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_is_amo_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_uses_ldq_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_uses_stq_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_is_sys_pc2epc_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_is_unique_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_flush_on_commit_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_ldst_is_rs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_0_bits_ldst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_0_bits_lrs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_0_bits_lrs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_0_bits_lrs3_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_ldst_val_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_0_bits_dst_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_0_bits_lrs1_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_0_bits_lrs2_rtype_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_frs3_en_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_fp_val_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_fp_single_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_xcpt_pf_if_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_xcpt_ae_if_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_xcpt_ma_if_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_bp_debug_if_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_bp_xcpt_if_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_0_bits_debug_fsrc_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_0_bits_debug_tsrc_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_valid_0; // @[core.scala:51:7]
wire [3:0] io_lsu_fp_stdata_bits_uop_ctrl_br_type_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_ctrl_op1_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_op2_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_imm_sel_0; // @[core.scala:51:7]
wire [4:0] io_lsu_fp_stdata_bits_uop_ctrl_op_fcn_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_ctrl_is_load_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_ctrl_is_sta_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_ctrl_is_std_0; // @[core.scala:51:7]
wire [6:0] io_lsu_fp_stdata_bits_uop_uopc_0; // @[core.scala:51:7]
wire [31:0] io_lsu_fp_stdata_bits_uop_inst_0; // @[core.scala:51:7]
wire [31:0] io_lsu_fp_stdata_bits_uop_debug_inst_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_is_rvc_0; // @[core.scala:51:7]
wire [39:0] io_lsu_fp_stdata_bits_uop_debug_pc_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_uop_iq_type_0; // @[core.scala:51:7]
wire [9:0] io_lsu_fp_stdata_bits_uop_fu_code_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_iw_state_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_iw_p1_poisoned_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_iw_p2_poisoned_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_is_br_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_is_jalr_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_is_jal_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_is_sfb_0; // @[core.scala:51:7]
wire [7:0] io_lsu_fp_stdata_bits_uop_br_mask_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_uop_br_tag_0; // @[core.scala:51:7]
wire [3:0] io_lsu_fp_stdata_bits_uop_ftq_idx_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_edge_inst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_pc_lob_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_taken_0; // @[core.scala:51:7]
wire [19:0] io_lsu_fp_stdata_bits_uop_imm_packed_0; // @[core.scala:51:7]
wire [11:0] io_lsu_fp_stdata_bits_uop_csr_addr_0; // @[core.scala:51:7]
wire [4:0] io_lsu_fp_stdata_bits_uop_rob_idx_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_uop_ldq_idx_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_uop_stq_idx_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_rxq_idx_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_pdst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_prs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_prs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_prs3_0; // @[core.scala:51:7]
wire [3:0] io_lsu_fp_stdata_bits_uop_ppred_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_prs1_busy_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_prs2_busy_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_prs3_busy_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_ppred_busy_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_stale_pdst_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_exception_0; // @[core.scala:51:7]
wire [63:0] io_lsu_fp_stdata_bits_uop_exc_cause_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_bypassable_0; // @[core.scala:51:7]
wire [4:0] io_lsu_fp_stdata_bits_uop_mem_cmd_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_mem_size_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_mem_signed_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_is_fence_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_is_fencei_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_is_amo_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_uses_ldq_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_uses_stq_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_is_sys_pc2epc_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_is_unique_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_flush_on_commit_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_ldst_is_rs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_ldst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_lrs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_lrs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_lrs3_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_ldst_val_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_dst_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_lrs1_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_lrs2_rtype_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_frs3_en_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_fp_val_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_fp_single_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_xcpt_pf_if_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_xcpt_ae_if_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_xcpt_ma_if_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_bp_debug_if_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_bp_xcpt_if_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_debug_fsrc_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_debug_tsrc_0; // @[core.scala:51:7]
wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[core.scala:51:7]
wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std_0; // @[core.scala:51:7]
wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_uopc_0; // @[core.scala:51:7]
wire [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_inst_0; // @[core.scala:51:7]
wire [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc_0; // @[core.scala:51:7]
wire [39:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type_0; // @[core.scala:51:7]
wire [9:0] io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_br_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb_0; // @[core.scala:51:7]
wire [7:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag_0; // @[core.scala:51:7]
wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_taken_0; // @[core.scala:51:7]
wire [19:0] io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed_0; // @[core.scala:51:7]
wire [11:0] io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr_0; // @[core.scala:51:7]
wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pdst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_0; // @[core.scala:51:7]
wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_exception_0; // @[core.scala:51:7]
wire [63:0] io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable_0; // @[core.scala:51:7]
wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc_0; // @[core.scala:51:7]
wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_flags_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_valid_0; // @[core.scala:51:7]
wire [63:0] io_lsu_fp_stdata_bits_data_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_predicated_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_valid_0; // @[core.scala:51:7]
wire io_lsu_commit_valids_0_0; // @[core.scala:51:7]
wire io_lsu_commit_arch_valids_0_0; // @[core.scala:51:7]
wire [3:0] io_lsu_commit_uops_0_ctrl_br_type_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_0_ctrl_op1_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_commit_uops_0_ctrl_op2_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_commit_uops_0_ctrl_imm_sel_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_0_ctrl_op_fcn_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_ctrl_fcn_dw_0; // @[core.scala:51:7]
wire [2:0] io_lsu_commit_uops_0_ctrl_csr_cmd_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_ctrl_is_load_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_ctrl_is_sta_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_ctrl_is_std_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_0_uopc_0; // @[core.scala:51:7]
wire [31:0] io_lsu_commit_uops_0_inst_0; // @[core.scala:51:7]
wire [31:0] io_lsu_commit_uops_0_debug_inst_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_is_rvc_0; // @[core.scala:51:7]
wire [39:0] io_lsu_commit_uops_0_debug_pc_0; // @[core.scala:51:7]
wire [2:0] io_lsu_commit_uops_0_iq_type_0; // @[core.scala:51:7]
wire [9:0] io_lsu_commit_uops_0_fu_code_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_0_iw_state_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_iw_p1_poisoned_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_iw_p2_poisoned_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_is_br_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_is_jalr_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_is_jal_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_is_sfb_0; // @[core.scala:51:7]
wire [7:0] io_lsu_commit_uops_0_br_mask_0; // @[core.scala:51:7]
wire [2:0] io_lsu_commit_uops_0_br_tag_0; // @[core.scala:51:7]
wire [3:0] io_lsu_commit_uops_0_ftq_idx_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_edge_inst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_0_pc_lob_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_taken_0; // @[core.scala:51:7]
wire [19:0] io_lsu_commit_uops_0_imm_packed_0; // @[core.scala:51:7]
wire [11:0] io_lsu_commit_uops_0_csr_addr_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_0_rob_idx_0; // @[core.scala:51:7]
wire [2:0] io_lsu_commit_uops_0_ldq_idx_0; // @[core.scala:51:7]
wire [2:0] io_lsu_commit_uops_0_stq_idx_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_0_rxq_idx_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_0_pdst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_0_prs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_0_prs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_0_prs3_0; // @[core.scala:51:7]
wire [3:0] io_lsu_commit_uops_0_ppred_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_prs1_busy_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_prs2_busy_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_prs3_busy_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_ppred_busy_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_0_stale_pdst_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_exception_0; // @[core.scala:51:7]
wire [63:0] io_lsu_commit_uops_0_exc_cause_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_bypassable_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_0_mem_cmd_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_0_mem_size_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_mem_signed_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_is_fence_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_is_fencei_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_is_amo_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_uses_ldq_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_uses_stq_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_is_sys_pc2epc_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_is_unique_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_flush_on_commit_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_ldst_is_rs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_0_ldst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_0_lrs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_0_lrs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_0_lrs3_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_ldst_val_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_0_dst_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_0_lrs1_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_0_lrs2_rtype_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_frs3_en_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_fp_val_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_fp_single_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_xcpt_pf_if_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_xcpt_ae_if_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_xcpt_ma_if_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_bp_debug_if_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_bp_xcpt_if_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_0_debug_fsrc_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_0_debug_tsrc_0; // @[core.scala:51:7]
wire io_lsu_commit_fflags_valid_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_fflags_bits_0; // @[core.scala:51:7]
wire [31:0] io_lsu_commit_debug_insts_0_0; // @[core.scala:51:7]
wire io_lsu_commit_rbk_valids_0_0; // @[core.scala:51:7]
wire [63:0] io_lsu_commit_debug_wdata_0_0; // @[core.scala:51:7]
wire io_lsu_commit_rollback_0; // @[core.scala:51:7]
wire [7:0] io_lsu_brupdate_b1_resolve_mask_0; // @[core.scala:51:7]
wire [7:0] io_lsu_brupdate_b1_mispredict_mask_0; // @[core.scala:51:7]
wire [3:0] io_lsu_brupdate_b2_uop_ctrl_br_type_0; // @[core.scala:51:7]
wire [1:0] io_lsu_brupdate_b2_uop_ctrl_op1_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_brupdate_b2_uop_ctrl_op2_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_brupdate_b2_uop_ctrl_imm_sel_0; // @[core.scala:51:7]
wire [4:0] io_lsu_brupdate_b2_uop_ctrl_op_fcn_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_ctrl_fcn_dw_0; // @[core.scala:51:7]
wire [2:0] io_lsu_brupdate_b2_uop_ctrl_csr_cmd_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_ctrl_is_load_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_ctrl_is_sta_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_ctrl_is_std_0; // @[core.scala:51:7]
wire [6:0] io_lsu_brupdate_b2_uop_uopc_0; // @[core.scala:51:7]
wire [31:0] io_lsu_brupdate_b2_uop_inst_0; // @[core.scala:51:7]
wire [31:0] io_lsu_brupdate_b2_uop_debug_inst_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_is_rvc_0; // @[core.scala:51:7]
wire [39:0] io_lsu_brupdate_b2_uop_debug_pc_0; // @[core.scala:51:7]
wire [2:0] io_lsu_brupdate_b2_uop_iq_type_0; // @[core.scala:51:7]
wire [9:0] io_lsu_brupdate_b2_uop_fu_code_0; // @[core.scala:51:7]
wire [1:0] io_lsu_brupdate_b2_uop_iw_state_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_iw_p1_poisoned_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_iw_p2_poisoned_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_is_br_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_is_jalr_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_is_jal_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_is_sfb_0; // @[core.scala:51:7]
wire [7:0] io_lsu_brupdate_b2_uop_br_mask_0; // @[core.scala:51:7]
wire [2:0] io_lsu_brupdate_b2_uop_br_tag_0; // @[core.scala:51:7]
wire [3:0] io_lsu_brupdate_b2_uop_ftq_idx_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_edge_inst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_brupdate_b2_uop_pc_lob_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_taken_0; // @[core.scala:51:7]
wire [19:0] io_lsu_brupdate_b2_uop_imm_packed_0; // @[core.scala:51:7]
wire [11:0] io_lsu_brupdate_b2_uop_csr_addr_0; // @[core.scala:51:7]
wire [4:0] io_lsu_brupdate_b2_uop_rob_idx_0; // @[core.scala:51:7]
wire [2:0] io_lsu_brupdate_b2_uop_ldq_idx_0; // @[core.scala:51:7]
wire [2:0] io_lsu_brupdate_b2_uop_stq_idx_0; // @[core.scala:51:7]
wire [1:0] io_lsu_brupdate_b2_uop_rxq_idx_0; // @[core.scala:51:7]
wire [5:0] io_lsu_brupdate_b2_uop_pdst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_brupdate_b2_uop_prs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_brupdate_b2_uop_prs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_brupdate_b2_uop_prs3_0; // @[core.scala:51:7]
wire [3:0] io_lsu_brupdate_b2_uop_ppred_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_prs1_busy_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_prs2_busy_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_prs3_busy_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_ppred_busy_0; // @[core.scala:51:7]
wire [5:0] io_lsu_brupdate_b2_uop_stale_pdst_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_exception_0; // @[core.scala:51:7]
wire [63:0] io_lsu_brupdate_b2_uop_exc_cause_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_bypassable_0; // @[core.scala:51:7]
wire [4:0] io_lsu_brupdate_b2_uop_mem_cmd_0; // @[core.scala:51:7]
wire [1:0] io_lsu_brupdate_b2_uop_mem_size_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_mem_signed_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_is_fence_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_is_fencei_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_is_amo_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_uses_ldq_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_uses_stq_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_is_sys_pc2epc_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_is_unique_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_flush_on_commit_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_ldst_is_rs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_brupdate_b2_uop_ldst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs3_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_ldst_val_0; // @[core.scala:51:7]
wire [1:0] io_lsu_brupdate_b2_uop_dst_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_frs3_en_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_fp_val_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_fp_single_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_xcpt_pf_if_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_xcpt_ae_if_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_xcpt_ma_if_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_bp_debug_if_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_bp_xcpt_if_0; // @[core.scala:51:7]
wire [1:0] io_lsu_brupdate_b2_uop_debug_fsrc_0; // @[core.scala:51:7]
wire [1:0] io_lsu_brupdate_b2_uop_debug_tsrc_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_valid_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_mispredict_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_taken_0; // @[core.scala:51:7]
wire [2:0] io_lsu_brupdate_b2_cfi_type_0; // @[core.scala:51:7]
wire [1:0] io_lsu_brupdate_b2_pc_sel_0; // @[core.scala:51:7]
wire [39:0] io_lsu_brupdate_b2_jalr_target_0; // @[core.scala:51:7]
wire [20:0] io_lsu_brupdate_b2_target_offset_0; // @[core.scala:51:7]
wire io_lsu_commit_load_at_rob_head_0; // @[core.scala:51:7]
wire io_lsu_fence_dmem_0; // @[core.scala:51:7]
wire [4:0] io_lsu_rob_pnr_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_rob_head_idx_0; // @[core.scala:51:7]
wire io_lsu_exception_0; // @[core.scala:51:7]
wire [63:0] io_lsu_tsc_reg_0; // @[core.scala:51:7]
wire io_trace_custom_rob_empty_0; // @[core.scala:51:7]
wire [63:0] io_trace_time_0; // @[core.scala:51:7]
wire [2:0] io_fcsr_rm; // @[core.scala:51:7]
wire _int_iss_wakeups_0_valid_T_2; // @[core.scala:795:52]
wire fast_wakeup_valid; // @[core.scala:814:29]
wire [6:0] fast_wakeup_bits_uop_uopc; // @[core.scala:814:29]
wire [31:0] fast_wakeup_bits_uop_inst; // @[core.scala:814:29]
wire [31:0] fast_wakeup_bits_uop_debug_inst; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_is_rvc; // @[core.scala:814:29]
wire [39:0] fast_wakeup_bits_uop_debug_pc; // @[core.scala:814:29]
wire [2:0] fast_wakeup_bits_uop_iq_type; // @[core.scala:814:29]
wire [9:0] fast_wakeup_bits_uop_fu_code; // @[core.scala:814:29]
wire [3:0] fast_wakeup_bits_uop_ctrl_br_type; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:814:29]
wire [2:0] fast_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:814:29]
wire [2:0] fast_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:814:29]
wire [4:0] fast_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:814:29]
wire [2:0] fast_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_ctrl_is_load; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_ctrl_is_std; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_uop_iw_state; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_is_br; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_is_jalr; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_is_jal; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_is_sfb; // @[core.scala:814:29]
wire [7:0] fast_wakeup_bits_uop_br_mask; // @[core.scala:814:29]
wire [2:0] fast_wakeup_bits_uop_br_tag; // @[core.scala:814:29]
wire [3:0] fast_wakeup_bits_uop_ftq_idx; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_edge_inst; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_uop_pc_lob; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_taken; // @[core.scala:814:29]
wire [19:0] fast_wakeup_bits_uop_imm_packed; // @[core.scala:814:29]
wire [11:0] fast_wakeup_bits_uop_csr_addr; // @[core.scala:814:29]
wire [4:0] fast_wakeup_bits_uop_rob_idx; // @[core.scala:814:29]
wire [2:0] fast_wakeup_bits_uop_ldq_idx; // @[core.scala:814:29]
wire [2:0] fast_wakeup_bits_uop_stq_idx; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_uop_rxq_idx; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_uop_pdst; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_uop_prs1; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_uop_prs2; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_uop_prs3; // @[core.scala:814:29]
wire [3:0] fast_wakeup_bits_uop_ppred; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_prs1_busy; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_prs2_busy; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_prs3_busy; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_ppred_busy; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_uop_stale_pdst; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_exception; // @[core.scala:814:29]
wire [63:0] fast_wakeup_bits_uop_exc_cause; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_bypassable; // @[core.scala:814:29]
wire [4:0] fast_wakeup_bits_uop_mem_cmd; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_uop_mem_size; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_mem_signed; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_is_fence; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_is_fencei; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_is_amo; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_uses_ldq; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_uses_stq; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_is_unique; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_flush_on_commit; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_uop_ldst; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_uop_lrs1; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_uop_lrs2; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_uop_lrs3; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_ldst_val; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_uop_dst_rtype; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_uop_lrs1_rtype; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_uop_lrs2_rtype; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_frs3_en; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_fp_val; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_fp_single; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_bp_debug_if; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_uop_debug_fsrc; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_uop_debug_tsrc; // @[core.scala:814:29]
wire slow_wakeup_valid; // @[core.scala:815:29]
wire [6:0] slow_wakeup_bits_uop_uopc; // @[core.scala:815:29]
wire [31:0] slow_wakeup_bits_uop_inst; // @[core.scala:815:29]
wire [31:0] slow_wakeup_bits_uop_debug_inst; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_is_rvc; // @[core.scala:815:29]
wire [39:0] slow_wakeup_bits_uop_debug_pc; // @[core.scala:815:29]
wire [2:0] slow_wakeup_bits_uop_iq_type; // @[core.scala:815:29]
wire [9:0] slow_wakeup_bits_uop_fu_code; // @[core.scala:815:29]
wire [3:0] slow_wakeup_bits_uop_ctrl_br_type; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:815:29]
wire [2:0] slow_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:815:29]
wire [2:0] slow_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:815:29]
wire [4:0] slow_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:815:29]
wire [2:0] slow_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_ctrl_is_load; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_ctrl_is_std; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_uop_iw_state; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_is_br; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_is_jalr; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_is_jal; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_is_sfb; // @[core.scala:815:29]
wire [7:0] slow_wakeup_bits_uop_br_mask; // @[core.scala:815:29]
wire [2:0] slow_wakeup_bits_uop_br_tag; // @[core.scala:815:29]
wire [3:0] slow_wakeup_bits_uop_ftq_idx; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_edge_inst; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_uop_pc_lob; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_taken; // @[core.scala:815:29]
wire [19:0] slow_wakeup_bits_uop_imm_packed; // @[core.scala:815:29]
wire [11:0] slow_wakeup_bits_uop_csr_addr; // @[core.scala:815:29]
wire [4:0] slow_wakeup_bits_uop_rob_idx; // @[core.scala:815:29]
wire [2:0] slow_wakeup_bits_uop_ldq_idx; // @[core.scala:815:29]
wire [2:0] slow_wakeup_bits_uop_stq_idx; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_uop_rxq_idx; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_uop_pdst; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_uop_prs1; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_uop_prs2; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_uop_prs3; // @[core.scala:815:29]
wire [3:0] slow_wakeup_bits_uop_ppred; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_prs1_busy; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_prs2_busy; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_prs3_busy; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_ppred_busy; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_uop_stale_pdst; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_exception; // @[core.scala:815:29]
wire [63:0] slow_wakeup_bits_uop_exc_cause; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_bypassable; // @[core.scala:815:29]
wire [4:0] slow_wakeup_bits_uop_mem_cmd; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_uop_mem_size; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_mem_signed; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_is_fence; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_is_fencei; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_is_amo; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_uses_ldq; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_uses_stq; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_is_unique; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_flush_on_commit; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_uop_ldst; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_uop_lrs1; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_uop_lrs2; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_uop_lrs3; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_ldst_val; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_uop_dst_rtype; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_uop_lrs1_rtype; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_uop_lrs2_rtype; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_frs3_en; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_fp_val; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_fp_single; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_bp_debug_if; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_uop_debug_fsrc; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_uop_debug_tsrc; // @[core.scala:815:29]
wire [3:0] int_iss_wakeups_0_bits_uop_ctrl_br_type; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_uop_ctrl_op1_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_uop_ctrl_op2_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_uop_ctrl_imm_sel; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_0_bits_uop_ctrl_op_fcn; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_ctrl_is_load; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_ctrl_is_sta; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_ctrl_is_std; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_0_bits_uop_uopc; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_0_bits_uop_inst; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_0_bits_uop_debug_inst; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_is_rvc; // @[core.scala:147:30]
wire [39:0] int_iss_wakeups_0_bits_uop_debug_pc; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_uop_iq_type; // @[core.scala:147:30]
wire [9:0] int_iss_wakeups_0_bits_uop_fu_code; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_uop_iw_state; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_iw_p1_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_iw_p2_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_is_br; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_is_jalr; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_is_jal; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_is_sfb; // @[core.scala:147:30]
wire [7:0] int_iss_wakeups_0_bits_uop_br_mask; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_uop_br_tag; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_0_bits_uop_ftq_idx; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_edge_inst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_uop_pc_lob; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_taken; // @[core.scala:147:30]
wire [19:0] int_iss_wakeups_0_bits_uop_imm_packed; // @[core.scala:147:30]
wire [11:0] int_iss_wakeups_0_bits_uop_csr_addr; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_0_bits_uop_rob_idx; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_uop_ldq_idx; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_uop_stq_idx; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_uop_rxq_idx; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_uop_pdst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_uop_prs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_uop_prs2; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_uop_prs3; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_0_bits_uop_ppred; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_prs1_busy; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_prs2_busy; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_prs3_busy; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_ppred_busy; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_uop_stale_pdst; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_exception; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_0_bits_uop_exc_cause; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_bypassable; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_0_bits_uop_mem_cmd; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_uop_mem_size; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_mem_signed; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_is_fence; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_is_fencei; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_is_amo; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_uses_ldq; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_uses_stq; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_is_sys_pc2epc; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_is_unique; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_flush_on_commit; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_ldst_is_rs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_uop_ldst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_uop_lrs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_uop_lrs2; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_uop_lrs3; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_ldst_val; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_uop_dst_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_uop_lrs1_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_uop_lrs2_rtype; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_frs3_en; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_fp_val; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_fp_single; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_xcpt_pf_if; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_xcpt_ae_if; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_xcpt_ma_if; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_bp_debug_if; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_bp_xcpt_if; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_uop_debug_fsrc; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_uop_debug_tsrc; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_uopc; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_0_bits_fflags_bits_uop_inst; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_0_bits_fflags_bits_uop_debug_inst; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_is_rvc; // @[core.scala:147:30]
wire [39:0] int_iss_wakeups_0_bits_fflags_bits_uop_debug_pc; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_iq_type; // @[core.scala:147:30]
wire [9:0] int_iss_wakeups_0_bits_fflags_bits_uop_fu_code; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_iw_state; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_is_br; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_is_jalr; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_is_jal; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_is_sfb; // @[core.scala:147:30]
wire [7:0] int_iss_wakeups_0_bits_fflags_bits_uop_br_mask; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_br_tag; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_0_bits_fflags_bits_uop_ftq_idx; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_edge_inst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_pc_lob; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_taken; // @[core.scala:147:30]
wire [19:0] int_iss_wakeups_0_bits_fflags_bits_uop_imm_packed; // @[core.scala:147:30]
wire [11:0] int_iss_wakeups_0_bits_fflags_bits_uop_csr_addr; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_rob_idx; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_ldq_idx; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_stq_idx; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_rxq_idx; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_pdst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_prs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_prs2; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_prs3; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_0_bits_fflags_bits_uop_ppred; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_prs1_busy; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_prs2_busy; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_prs3_busy; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_ppred_busy; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_stale_pdst; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_exception; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_0_bits_fflags_bits_uop_exc_cause; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_bypassable; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_mem_cmd; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_mem_size; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_mem_signed; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_is_fence; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_is_fencei; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_is_amo; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_uses_ldq; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_uses_stq; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_is_unique; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_ldst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs2; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs3; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_ldst_val; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_dst_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_frs3_en; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_fp_val; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_fp_single; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_0_bits_fflags_bits_flags; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_valid; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_0_bits_data; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_predicated; // @[core.scala:147:30]
wire int_iss_wakeups_0_valid; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_1_bits_uop_ctrl_br_type; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_uop_ctrl_op1_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_1_bits_uop_ctrl_op2_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_1_bits_uop_ctrl_imm_sel; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_1_bits_uop_ctrl_op_fcn; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_1_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_ctrl_is_load; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_ctrl_is_sta; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_ctrl_is_std; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_1_bits_uop_uopc; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_1_bits_uop_inst; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_1_bits_uop_debug_inst; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_is_rvc; // @[core.scala:147:30]
wire [39:0] int_iss_wakeups_1_bits_uop_debug_pc; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_1_bits_uop_iq_type; // @[core.scala:147:30]
wire [9:0] int_iss_wakeups_1_bits_uop_fu_code; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_uop_iw_state; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_iw_p1_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_iw_p2_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_is_br; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_is_jalr; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_is_jal; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_is_sfb; // @[core.scala:147:30]
wire [7:0] int_iss_wakeups_1_bits_uop_br_mask; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_1_bits_uop_br_tag; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_1_bits_uop_ftq_idx; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_edge_inst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_uop_pc_lob; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_taken; // @[core.scala:147:30]
wire [19:0] int_iss_wakeups_1_bits_uop_imm_packed; // @[core.scala:147:30]
wire [11:0] int_iss_wakeups_1_bits_uop_csr_addr; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_1_bits_uop_rob_idx; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_1_bits_uop_ldq_idx; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_1_bits_uop_stq_idx; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_uop_rxq_idx; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_uop_pdst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_uop_prs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_uop_prs2; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_uop_prs3; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_1_bits_uop_ppred; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_prs1_busy; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_prs2_busy; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_prs3_busy; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_ppred_busy; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_uop_stale_pdst; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_exception; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_1_bits_uop_exc_cause; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_bypassable; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_1_bits_uop_mem_cmd; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_uop_mem_size; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_mem_signed; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_is_fence; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_is_fencei; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_is_amo; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_uses_ldq; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_uses_stq; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_is_sys_pc2epc; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_is_unique; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_flush_on_commit; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_ldst_is_rs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_uop_ldst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_uop_lrs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_uop_lrs2; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_uop_lrs3; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_ldst_val; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_uop_dst_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_uop_lrs1_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_uop_lrs2_rtype; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_frs3_en; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_fp_val; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_fp_single; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_xcpt_pf_if; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_xcpt_ae_if; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_xcpt_ma_if; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_bp_debug_if; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_bp_xcpt_if; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_uop_debug_fsrc; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_uop_debug_tsrc; // @[core.scala:147:30]
wire int_iss_wakeups_1_valid; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_2_bits_uop_ctrl_br_type; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_uop_ctrl_op1_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_uop_ctrl_op2_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_uop_ctrl_imm_sel; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_2_bits_uop_ctrl_op_fcn; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_ctrl_is_load; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_ctrl_is_sta; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_ctrl_is_std; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_2_bits_uop_uopc; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_2_bits_uop_inst; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_2_bits_uop_debug_inst; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_is_rvc; // @[core.scala:147:30]
wire [39:0] int_iss_wakeups_2_bits_uop_debug_pc; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_uop_iq_type; // @[core.scala:147:30]
wire [9:0] int_iss_wakeups_2_bits_uop_fu_code; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_uop_iw_state; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_iw_p1_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_iw_p2_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_is_br; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_is_jalr; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_is_jal; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_is_sfb; // @[core.scala:147:30]
wire [7:0] int_iss_wakeups_2_bits_uop_br_mask; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_uop_br_tag; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_2_bits_uop_ftq_idx; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_edge_inst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_uop_pc_lob; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_taken; // @[core.scala:147:30]
wire [19:0] int_iss_wakeups_2_bits_uop_imm_packed; // @[core.scala:147:30]
wire [11:0] int_iss_wakeups_2_bits_uop_csr_addr; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_2_bits_uop_rob_idx; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_uop_ldq_idx; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_uop_stq_idx; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_uop_rxq_idx; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_uop_pdst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_uop_prs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_uop_prs2; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_uop_prs3; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_2_bits_uop_ppred; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_prs1_busy; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_prs2_busy; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_prs3_busy; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_ppred_busy; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_uop_stale_pdst; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_exception; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_2_bits_uop_exc_cause; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_bypassable; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_2_bits_uop_mem_cmd; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_uop_mem_size; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_mem_signed; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_is_fence; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_is_fencei; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_is_amo; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_uses_ldq; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_uses_stq; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_is_sys_pc2epc; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_is_unique; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_flush_on_commit; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_ldst_is_rs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_uop_ldst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_uop_lrs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_uop_lrs2; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_uop_lrs3; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_ldst_val; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_uop_dst_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_uop_lrs1_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_uop_lrs2_rtype; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_frs3_en; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_fp_val; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_fp_single; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_xcpt_pf_if; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_xcpt_ae_if; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_xcpt_ma_if; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_bp_debug_if; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_bp_xcpt_if; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_uop_debug_fsrc; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_uop_debug_tsrc; // @[core.scala:147:30]
wire int_iss_wakeups_2_valid; // @[core.scala:147:30]
wire _int_ren_wakeups_0_valid_T_2; // @[core.scala:798:52]
wire [3:0] int_ren_wakeups_0_bits_uop_ctrl_br_type; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_uop_ctrl_op1_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_uop_ctrl_op2_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_uop_ctrl_imm_sel; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_0_bits_uop_ctrl_op_fcn; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_ctrl_is_load; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_ctrl_is_sta; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_ctrl_is_std; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_0_bits_uop_uopc; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_0_bits_uop_inst; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_0_bits_uop_debug_inst; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_is_rvc; // @[core.scala:148:30]
wire [39:0] int_ren_wakeups_0_bits_uop_debug_pc; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_uop_iq_type; // @[core.scala:148:30]
wire [9:0] int_ren_wakeups_0_bits_uop_fu_code; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_uop_iw_state; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_iw_p1_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_iw_p2_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_is_br; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_is_jalr; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_is_jal; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_is_sfb; // @[core.scala:148:30]
wire [7:0] int_ren_wakeups_0_bits_uop_br_mask; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_uop_br_tag; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_0_bits_uop_ftq_idx; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_edge_inst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_uop_pc_lob; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_taken; // @[core.scala:148:30]
wire [19:0] int_ren_wakeups_0_bits_uop_imm_packed; // @[core.scala:148:30]
wire [11:0] int_ren_wakeups_0_bits_uop_csr_addr; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_0_bits_uop_rob_idx; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_uop_ldq_idx; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_uop_stq_idx; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_uop_rxq_idx; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_uop_pdst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_uop_prs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_uop_prs2; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_uop_prs3; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_0_bits_uop_ppred; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_prs1_busy; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_prs2_busy; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_prs3_busy; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_ppred_busy; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_uop_stale_pdst; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_exception; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_0_bits_uop_exc_cause; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_bypassable; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_0_bits_uop_mem_cmd; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_uop_mem_size; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_mem_signed; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_is_fence; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_is_fencei; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_is_amo; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_uses_ldq; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_uses_stq; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_is_sys_pc2epc; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_is_unique; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_flush_on_commit; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_ldst_is_rs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_uop_ldst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_uop_lrs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_uop_lrs2; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_uop_lrs3; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_ldst_val; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_uop_dst_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_uop_lrs1_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_uop_lrs2_rtype; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_frs3_en; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_fp_val; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_fp_single; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_xcpt_pf_if; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_xcpt_ae_if; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_xcpt_ma_if; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_bp_debug_if; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_bp_xcpt_if; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_uop_debug_fsrc; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_uop_debug_tsrc; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_uopc; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_0_bits_fflags_bits_uop_inst; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_0_bits_fflags_bits_uop_debug_inst; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_is_rvc; // @[core.scala:148:30]
wire [39:0] int_ren_wakeups_0_bits_fflags_bits_uop_debug_pc; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_iq_type; // @[core.scala:148:30]
wire [9:0] int_ren_wakeups_0_bits_fflags_bits_uop_fu_code; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_iw_state; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_is_br; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_is_jalr; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_is_jal; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_is_sfb; // @[core.scala:148:30]
wire [7:0] int_ren_wakeups_0_bits_fflags_bits_uop_br_mask; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_br_tag; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_0_bits_fflags_bits_uop_ftq_idx; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_edge_inst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_pc_lob; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_taken; // @[core.scala:148:30]
wire [19:0] int_ren_wakeups_0_bits_fflags_bits_uop_imm_packed; // @[core.scala:148:30]
wire [11:0] int_ren_wakeups_0_bits_fflags_bits_uop_csr_addr; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_rob_idx; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_ldq_idx; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_stq_idx; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_rxq_idx; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_pdst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_prs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_prs2; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_prs3; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_0_bits_fflags_bits_uop_ppred; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_prs1_busy; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_prs2_busy; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_prs3_busy; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_ppred_busy; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_stale_pdst; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_exception; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_0_bits_fflags_bits_uop_exc_cause; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_bypassable; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_mem_cmd; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_mem_size; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_mem_signed; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_is_fence; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_is_fencei; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_is_amo; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_uses_ldq; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_uses_stq; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_is_unique; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_ldst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs2; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs3; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_ldst_val; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_dst_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_frs3_en; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_fp_val; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_fp_single; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_0_bits_fflags_bits_flags; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_valid; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_0_bits_data; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_predicated; // @[core.scala:148:30]
wire int_ren_wakeups_0_valid; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_1_bits_uop_ctrl_br_type; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_uop_ctrl_op1_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_1_bits_uop_ctrl_op2_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_1_bits_uop_ctrl_imm_sel; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_1_bits_uop_ctrl_op_fcn; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_1_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_ctrl_is_load; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_ctrl_is_sta; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_ctrl_is_std; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_1_bits_uop_uopc; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_1_bits_uop_inst; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_1_bits_uop_debug_inst; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_is_rvc; // @[core.scala:148:30]
wire [39:0] int_ren_wakeups_1_bits_uop_debug_pc; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_1_bits_uop_iq_type; // @[core.scala:148:30]
wire [9:0] int_ren_wakeups_1_bits_uop_fu_code; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_uop_iw_state; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_iw_p1_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_iw_p2_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_is_br; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_is_jalr; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_is_jal; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_is_sfb; // @[core.scala:148:30]
wire [7:0] int_ren_wakeups_1_bits_uop_br_mask; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_1_bits_uop_br_tag; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_1_bits_uop_ftq_idx; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_edge_inst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_uop_pc_lob; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_taken; // @[core.scala:148:30]
wire [19:0] int_ren_wakeups_1_bits_uop_imm_packed; // @[core.scala:148:30]
wire [11:0] int_ren_wakeups_1_bits_uop_csr_addr; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_1_bits_uop_rob_idx; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_1_bits_uop_ldq_idx; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_1_bits_uop_stq_idx; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_uop_rxq_idx; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_uop_pdst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_uop_prs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_uop_prs2; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_uop_prs3; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_1_bits_uop_ppred; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_prs1_busy; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_prs2_busy; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_prs3_busy; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_ppred_busy; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_uop_stale_pdst; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_exception; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_1_bits_uop_exc_cause; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_bypassable; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_1_bits_uop_mem_cmd; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_uop_mem_size; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_mem_signed; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_is_fence; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_is_fencei; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_is_amo; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_uses_ldq; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_uses_stq; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_is_sys_pc2epc; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_is_unique; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_flush_on_commit; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_ldst_is_rs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_uop_ldst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_uop_lrs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_uop_lrs2; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_uop_lrs3; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_ldst_val; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_uop_dst_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_uop_lrs1_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_uop_lrs2_rtype; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_frs3_en; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_fp_val; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_fp_single; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_xcpt_pf_if; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_xcpt_ae_if; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_xcpt_ma_if; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_bp_debug_if; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_bp_xcpt_if; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_uop_debug_fsrc; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_uop_debug_tsrc; // @[core.scala:148:30]
wire int_ren_wakeups_1_valid; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_2_bits_uop_ctrl_br_type; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_uop_ctrl_op1_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_uop_ctrl_op2_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_uop_ctrl_imm_sel; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_2_bits_uop_ctrl_op_fcn; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_ctrl_is_load; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_ctrl_is_sta; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_ctrl_is_std; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_2_bits_uop_uopc; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_2_bits_uop_inst; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_2_bits_uop_debug_inst; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_is_rvc; // @[core.scala:148:30]
wire [39:0] int_ren_wakeups_2_bits_uop_debug_pc; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_uop_iq_type; // @[core.scala:148:30]
wire [9:0] int_ren_wakeups_2_bits_uop_fu_code; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_uop_iw_state; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_iw_p1_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_iw_p2_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_is_br; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_is_jalr; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_is_jal; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_is_sfb; // @[core.scala:148:30]
wire [7:0] int_ren_wakeups_2_bits_uop_br_mask; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_uop_br_tag; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_2_bits_uop_ftq_idx; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_edge_inst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_uop_pc_lob; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_taken; // @[core.scala:148:30]
wire [19:0] int_ren_wakeups_2_bits_uop_imm_packed; // @[core.scala:148:30]
wire [11:0] int_ren_wakeups_2_bits_uop_csr_addr; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_2_bits_uop_rob_idx; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_uop_ldq_idx; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_uop_stq_idx; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_uop_rxq_idx; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_uop_pdst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_uop_prs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_uop_prs2; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_uop_prs3; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_2_bits_uop_ppred; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_prs1_busy; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_prs2_busy; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_prs3_busy; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_ppred_busy; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_uop_stale_pdst; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_exception; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_2_bits_uop_exc_cause; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_bypassable; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_2_bits_uop_mem_cmd; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_uop_mem_size; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_mem_signed; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_is_fence; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_is_fencei; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_is_amo; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_uses_ldq; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_uses_stq; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_is_sys_pc2epc; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_is_unique; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_flush_on_commit; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_ldst_is_rs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_uop_ldst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_uop_lrs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_uop_lrs2; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_uop_lrs3; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_ldst_val; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_uop_dst_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_uop_lrs1_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_uop_lrs2_rtype; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_frs3_en; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_fp_val; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_fp_single; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_xcpt_pf_if; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_xcpt_ae_if; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_xcpt_ma_if; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_bp_debug_if; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_bp_xcpt_if; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_uop_debug_fsrc; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_uop_debug_tsrc; // @[core.scala:148:30]
wire int_ren_wakeups_2_valid; // @[core.scala:148:30]
wire [6:0] iss_uops_1_uopc; // @[core.scala:173:24]
wire [31:0] iss_uops_1_inst; // @[core.scala:173:24]
wire [31:0] iss_uops_1_debug_inst; // @[core.scala:173:24]
wire iss_uops_1_is_rvc; // @[core.scala:173:24]
wire [39:0] iss_uops_1_debug_pc; // @[core.scala:173:24]
wire [2:0] iss_uops_1_iq_type; // @[core.scala:173:24]
wire [9:0] iss_uops_1_fu_code; // @[core.scala:173:24]
wire [3:0] iss_uops_1_ctrl_br_type; // @[core.scala:173:24]
wire [1:0] iss_uops_1_ctrl_op1_sel; // @[core.scala:173:24]
wire [2:0] iss_uops_1_ctrl_op2_sel; // @[core.scala:173:24]
wire [2:0] iss_uops_1_ctrl_imm_sel; // @[core.scala:173:24]
wire [4:0] iss_uops_1_ctrl_op_fcn; // @[core.scala:173:24]
wire iss_uops_1_ctrl_fcn_dw; // @[core.scala:173:24]
wire [2:0] iss_uops_1_ctrl_csr_cmd; // @[core.scala:173:24]
wire iss_uops_1_ctrl_is_load; // @[core.scala:173:24]
wire iss_uops_1_ctrl_is_sta; // @[core.scala:173:24]
wire iss_uops_1_ctrl_is_std; // @[core.scala:173:24]
wire [1:0] iss_uops_1_iw_state; // @[core.scala:173:24]
wire iss_uops_1_iw_p1_poisoned; // @[core.scala:173:24]
wire iss_uops_1_iw_p2_poisoned; // @[core.scala:173:24]
wire iss_uops_1_is_br; // @[core.scala:173:24]
wire iss_uops_1_is_jalr; // @[core.scala:173:24]
wire iss_uops_1_is_jal; // @[core.scala:173:24]
wire iss_uops_1_is_sfb; // @[core.scala:173:24]
wire [7:0] iss_uops_1_br_mask; // @[core.scala:173:24]
wire [2:0] iss_uops_1_br_tag; // @[core.scala:173:24]
wire [3:0] iss_uops_1_ftq_idx; // @[core.scala:173:24]
wire iss_uops_1_edge_inst; // @[core.scala:173:24]
wire [5:0] iss_uops_1_pc_lob; // @[core.scala:173:24]
wire iss_uops_1_taken; // @[core.scala:173:24]
wire [19:0] iss_uops_1_imm_packed; // @[core.scala:173:24]
wire [11:0] iss_uops_1_csr_addr; // @[core.scala:173:24]
wire [4:0] iss_uops_1_rob_idx; // @[core.scala:173:24]
wire [2:0] iss_uops_1_ldq_idx; // @[core.scala:173:24]
wire [2:0] iss_uops_1_stq_idx; // @[core.scala:173:24]
wire [1:0] iss_uops_1_rxq_idx; // @[core.scala:173:24]
wire [5:0] iss_uops_1_pdst; // @[core.scala:173:24]
wire [5:0] iss_uops_1_prs1; // @[core.scala:173:24]
wire [5:0] iss_uops_1_prs2; // @[core.scala:173:24]
wire [5:0] iss_uops_1_prs3; // @[core.scala:173:24]
wire [3:0] iss_uops_1_ppred; // @[core.scala:173:24]
wire iss_uops_1_prs1_busy; // @[core.scala:173:24]
wire iss_uops_1_prs2_busy; // @[core.scala:173:24]
wire iss_uops_1_prs3_busy; // @[core.scala:173:24]
wire iss_uops_1_ppred_busy; // @[core.scala:173:24]
wire [5:0] iss_uops_1_stale_pdst; // @[core.scala:173:24]
wire iss_uops_1_exception; // @[core.scala:173:24]
wire [63:0] iss_uops_1_exc_cause; // @[core.scala:173:24]
wire iss_uops_1_bypassable; // @[core.scala:173:24]
wire [4:0] iss_uops_1_mem_cmd; // @[core.scala:173:24]
wire [1:0] iss_uops_1_mem_size; // @[core.scala:173:24]
wire iss_uops_1_mem_signed; // @[core.scala:173:24]
wire iss_uops_1_is_fence; // @[core.scala:173:24]
wire iss_uops_1_is_fencei; // @[core.scala:173:24]
wire iss_uops_1_is_amo; // @[core.scala:173:24]
wire iss_uops_1_uses_ldq; // @[core.scala:173:24]
wire iss_uops_1_uses_stq; // @[core.scala:173:24]
wire iss_uops_1_is_sys_pc2epc; // @[core.scala:173:24]
wire iss_uops_1_is_unique; // @[core.scala:173:24]
wire iss_uops_1_flush_on_commit; // @[core.scala:173:24]
wire iss_uops_1_ldst_is_rs1; // @[core.scala:173:24]
wire [5:0] iss_uops_1_ldst; // @[core.scala:173:24]
wire [5:0] iss_uops_1_lrs1; // @[core.scala:173:24]
wire [5:0] iss_uops_1_lrs2; // @[core.scala:173:24]
wire [5:0] iss_uops_1_lrs3; // @[core.scala:173:24]
wire iss_uops_1_ldst_val; // @[core.scala:173:24]
wire [1:0] iss_uops_1_dst_rtype; // @[core.scala:173:24]
wire [1:0] iss_uops_1_lrs1_rtype; // @[core.scala:173:24]
wire [1:0] iss_uops_1_lrs2_rtype; // @[core.scala:173:24]
wire iss_uops_1_frs3_en; // @[core.scala:173:24]
wire iss_uops_1_fp_val; // @[core.scala:173:24]
wire iss_uops_1_fp_single; // @[core.scala:173:24]
wire iss_uops_1_xcpt_pf_if; // @[core.scala:173:24]
wire iss_uops_1_xcpt_ae_if; // @[core.scala:173:24]
wire iss_uops_1_xcpt_ma_if; // @[core.scala:173:24]
wire iss_uops_1_bp_debug_if; // @[core.scala:173:24]
wire iss_uops_1_bp_xcpt_if; // @[core.scala:173:24]
wire [1:0] iss_uops_1_debug_fsrc; // @[core.scala:173:24]
wire [1:0] iss_uops_1_debug_tsrc; // @[core.scala:173:24]
wire [3:0] pred_wakeup_bits_uop_ctrl_br_type; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:149:26]
wire [2:0] pred_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:149:26]
wire [2:0] pred_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:149:26]
wire [4:0] pred_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:149:26]
wire [2:0] pred_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_ctrl_is_load; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_ctrl_is_std; // @[core.scala:149:26]
wire [6:0] pred_wakeup_bits_uop_uopc; // @[core.scala:149:26]
wire [31:0] pred_wakeup_bits_uop_inst; // @[core.scala:149:26]
wire [31:0] pred_wakeup_bits_uop_debug_inst; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_is_rvc; // @[core.scala:149:26]
wire [39:0] pred_wakeup_bits_uop_debug_pc; // @[core.scala:149:26]
wire [2:0] pred_wakeup_bits_uop_iq_type; // @[core.scala:149:26]
wire [9:0] pred_wakeup_bits_uop_fu_code; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_uop_iw_state; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_is_br; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_is_jalr; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_is_jal; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_is_sfb; // @[core.scala:149:26]
wire [7:0] pred_wakeup_bits_uop_br_mask; // @[core.scala:149:26]
wire [2:0] pred_wakeup_bits_uop_br_tag; // @[core.scala:149:26]
wire [3:0] pred_wakeup_bits_uop_ftq_idx; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_edge_inst; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_uop_pc_lob; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_taken; // @[core.scala:149:26]
wire [19:0] pred_wakeup_bits_uop_imm_packed; // @[core.scala:149:26]
wire [11:0] pred_wakeup_bits_uop_csr_addr; // @[core.scala:149:26]
wire [4:0] pred_wakeup_bits_uop_rob_idx; // @[core.scala:149:26]
wire [2:0] pred_wakeup_bits_uop_ldq_idx; // @[core.scala:149:26]
wire [2:0] pred_wakeup_bits_uop_stq_idx; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_uop_rxq_idx; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_uop_pdst; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_uop_prs1; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_uop_prs2; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_uop_prs3; // @[core.scala:149:26]
wire [3:0] pred_wakeup_bits_uop_ppred; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_prs1_busy; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_prs2_busy; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_prs3_busy; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_ppred_busy; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_uop_stale_pdst; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_exception; // @[core.scala:149:26]
wire [63:0] pred_wakeup_bits_uop_exc_cause; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_bypassable; // @[core.scala:149:26]
wire [4:0] pred_wakeup_bits_uop_mem_cmd; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_uop_mem_size; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_mem_signed; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_is_fence; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_is_fencei; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_is_amo; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_uses_ldq; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_uses_stq; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_is_unique; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_flush_on_commit; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_uop_ldst; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_uop_lrs1; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_uop_lrs2; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_uop_lrs3; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_ldst_val; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_uop_dst_rtype; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_uop_lrs1_rtype; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_uop_lrs2_rtype; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_frs3_en; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_fp_val; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_fp_single; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_bp_debug_if; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_uop_debug_fsrc; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_uop_debug_tsrc; // @[core.scala:149:26]
wire _dec_valids_0_T_3; // @[core.scala:508:97]
wire dec_valids_0; // @[core.scala:157:24]
wire [3:0] xcpt_pc_req_bits = dec_uops_0_ftq_idx; // @[core.scala:158:24, :523:25]
wire [6:0] dec_uops_0_uopc; // @[core.scala:158:24]
wire [31:0] dec_uops_0_inst; // @[core.scala:158:24]
wire [31:0] dec_uops_0_debug_inst; // @[core.scala:158:24]
wire dec_uops_0_is_rvc; // @[core.scala:158:24]
wire [39:0] dec_uops_0_debug_pc; // @[core.scala:158:24]
wire [2:0] dec_uops_0_iq_type; // @[core.scala:158:24]
wire [9:0] dec_uops_0_fu_code; // @[core.scala:158:24]
wire dec_uops_0_is_br; // @[core.scala:158:24]
wire dec_uops_0_is_jalr; // @[core.scala:158:24]
wire dec_uops_0_is_jal; // @[core.scala:158:24]
wire dec_uops_0_is_sfb; // @[core.scala:158:24]
wire [7:0] dec_uops_0_br_mask; // @[core.scala:158:24]
wire [2:0] dec_uops_0_br_tag; // @[core.scala:158:24]
wire dec_uops_0_edge_inst; // @[core.scala:158:24]
wire [5:0] dec_uops_0_pc_lob; // @[core.scala:158:24]
wire dec_uops_0_taken; // @[core.scala:158:24]
wire [19:0] dec_uops_0_imm_packed; // @[core.scala:158:24]
wire dec_uops_0_exception; // @[core.scala:158:24]
wire [63:0] dec_uops_0_exc_cause; // @[core.scala:158:24]
wire dec_uops_0_bypassable; // @[core.scala:158:24]
wire [4:0] dec_uops_0_mem_cmd; // @[core.scala:158:24]
wire [1:0] dec_uops_0_mem_size; // @[core.scala:158:24]
wire dec_uops_0_mem_signed; // @[core.scala:158:24]
wire dec_uops_0_is_fence; // @[core.scala:158:24]
wire dec_uops_0_is_fencei; // @[core.scala:158:24]
wire dec_uops_0_is_amo; // @[core.scala:158:24]
wire dec_uops_0_uses_ldq; // @[core.scala:158:24]
wire dec_uops_0_uses_stq; // @[core.scala:158:24]
wire dec_uops_0_is_sys_pc2epc; // @[core.scala:158:24]
wire dec_uops_0_is_unique; // @[core.scala:158:24]
wire dec_uops_0_flush_on_commit; // @[core.scala:158:24]
wire [5:0] dec_uops_0_ldst; // @[core.scala:158:24]
wire [5:0] dec_uops_0_lrs1; // @[core.scala:158:24]
wire [5:0] dec_uops_0_lrs2; // @[core.scala:158:24]
wire [5:0] dec_uops_0_lrs3; // @[core.scala:158:24]
wire dec_uops_0_ldst_val; // @[core.scala:158:24]
wire [1:0] dec_uops_0_dst_rtype; // @[core.scala:158:24]
wire [1:0] dec_uops_0_lrs1_rtype; // @[core.scala:158:24]
wire [1:0] dec_uops_0_lrs2_rtype; // @[core.scala:158:24]
wire dec_uops_0_frs3_en; // @[core.scala:158:24]
wire dec_uops_0_fp_val; // @[core.scala:158:24]
wire dec_uops_0_fp_single; // @[core.scala:158:24]
wire dec_uops_0_xcpt_pf_if; // @[core.scala:158:24]
wire dec_uops_0_xcpt_ae_if; // @[core.scala:158:24]
wire dec_uops_0_bp_debug_if; // @[core.scala:158:24]
wire dec_uops_0_bp_xcpt_if; // @[core.scala:158:24]
wire [1:0] dec_uops_0_debug_fsrc; // @[core.scala:158:24]
wire dec_fire_0; // @[core.scala:159:24]
assign dec_ready = dec_fire_0; // @[core.scala:159:24, :161:24]
assign io_ifu_fetchpacket_ready_0 = dec_ready; // @[core.scala:51:7, :161:24]
wire dec_xcpts_0; // @[core.scala:162:24]
wire xcpt_pc_req_valid = dec_xcpts_0; // @[core.scala:162:24, :523:25]
wire _ren_stalls_0_T_1; // @[core.scala:671:63]
wire ren_stalls_0; // @[core.scala:163:24]
wire dis_valids_0; // @[core.scala:166:24]
wire dis_prior_slot_valid_1 = dis_valids_0; // @[core.scala:166:24, :683:71]
assign io_lsu_dis_uops_0_bits_uopc_0 = dis_uops_0_uopc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_inst_0 = dis_uops_0_inst; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_debug_inst_0 = dis_uops_0_debug_inst; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_is_rvc_0 = dis_uops_0_is_rvc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_debug_pc_0 = dis_uops_0_debug_pc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_iq_type_0 = dis_uops_0_iq_type; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_fu_code_0 = dis_uops_0_fu_code; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ctrl_br_type_0 = dis_uops_0_ctrl_br_type; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ctrl_op1_sel_0 = dis_uops_0_ctrl_op1_sel; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ctrl_op2_sel_0 = dis_uops_0_ctrl_op2_sel; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ctrl_imm_sel_0 = dis_uops_0_ctrl_imm_sel; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ctrl_op_fcn_0 = dis_uops_0_ctrl_op_fcn; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ctrl_fcn_dw_0 = dis_uops_0_ctrl_fcn_dw; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ctrl_csr_cmd_0 = dis_uops_0_ctrl_csr_cmd; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ctrl_is_load_0 = dis_uops_0_ctrl_is_load; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ctrl_is_sta_0 = dis_uops_0_ctrl_is_sta; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ctrl_is_std_0 = dis_uops_0_ctrl_is_std; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_iw_state_0 = dis_uops_0_iw_state; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_iw_p1_poisoned_0 = dis_uops_0_iw_p1_poisoned; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_iw_p2_poisoned_0 = dis_uops_0_iw_p2_poisoned; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_is_br_0 = dis_uops_0_is_br; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_is_jalr_0 = dis_uops_0_is_jalr; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_is_jal_0 = dis_uops_0_is_jal; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_is_sfb_0 = dis_uops_0_is_sfb; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_br_mask_0 = dis_uops_0_br_mask; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_br_tag_0 = dis_uops_0_br_tag; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ftq_idx_0 = dis_uops_0_ftq_idx; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_edge_inst_0 = dis_uops_0_edge_inst; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_pc_lob_0 = dis_uops_0_pc_lob; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_taken_0 = dis_uops_0_taken; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_imm_packed_0 = dis_uops_0_imm_packed; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_csr_addr_0 = dis_uops_0_csr_addr; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_rob_idx_0 = dis_uops_0_rob_idx; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ldq_idx_0 = dis_uops_0_ldq_idx; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_stq_idx_0 = dis_uops_0_stq_idx; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_rxq_idx_0 = dis_uops_0_rxq_idx; // @[core.scala:51:7, :167:24]
wire [5:0] _dis_uops_0_pdst_T_3; // @[core.scala:659:28]
assign io_lsu_dis_uops_0_bits_pdst_0 = dis_uops_0_pdst; // @[core.scala:51:7, :167:24]
wire [5:0] _dis_uops_0_prs1_T_3; // @[core.scala:654:28]
assign io_lsu_dis_uops_0_bits_prs1_0 = dis_uops_0_prs1; // @[core.scala:51:7, :167:24]
wire [5:0] _dis_uops_0_prs2_T_1; // @[core.scala:656:28]
assign io_lsu_dis_uops_0_bits_prs2_0 = dis_uops_0_prs2; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_prs3_0 = dis_uops_0_prs3; // @[core.scala:51:7, :167:24]
wire _dis_uops_0_prs1_busy_T_4; // @[core.scala:664:85]
assign io_lsu_dis_uops_0_bits_prs1_busy_0 = dis_uops_0_prs1_busy; // @[core.scala:51:7, :167:24]
wire _dis_uops_0_prs2_busy_T_4; // @[core.scala:666:85]
assign io_lsu_dis_uops_0_bits_prs2_busy_0 = dis_uops_0_prs2_busy; // @[core.scala:51:7, :167:24]
wire _dis_uops_0_prs3_busy_T; // @[core.scala:668:46]
assign io_lsu_dis_uops_0_bits_prs3_busy_0 = dis_uops_0_prs3_busy; // @[core.scala:51:7, :167:24]
wire [5:0] _dis_uops_0_stale_pdst_T_1; // @[core.scala:662:34]
assign io_lsu_dis_uops_0_bits_stale_pdst_0 = dis_uops_0_stale_pdst; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_exception_0 = dis_uops_0_exception; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_exc_cause_0 = dis_uops_0_exc_cause; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_bypassable_0 = dis_uops_0_bypassable; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_mem_cmd_0 = dis_uops_0_mem_cmd; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_mem_size_0 = dis_uops_0_mem_size; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_mem_signed_0 = dis_uops_0_mem_signed; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_is_fence_0 = dis_uops_0_is_fence; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_is_fencei_0 = dis_uops_0_is_fencei; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_is_amo_0 = dis_uops_0_is_amo; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_uses_ldq_0 = dis_uops_0_uses_ldq; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_uses_stq_0 = dis_uops_0_uses_stq; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_is_sys_pc2epc_0 = dis_uops_0_is_sys_pc2epc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_is_unique_0 = dis_uops_0_is_unique; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_flush_on_commit_0 = dis_uops_0_flush_on_commit; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ldst_is_rs1_0 = dis_uops_0_ldst_is_rs1; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ldst_0 = dis_uops_0_ldst; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_lrs1_0 = dis_uops_0_lrs1; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_lrs2_0 = dis_uops_0_lrs2; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_lrs3_0 = dis_uops_0_lrs3; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ldst_val_0 = dis_uops_0_ldst_val; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_dst_rtype_0 = dis_uops_0_dst_rtype; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_lrs1_rtype_0 = dis_uops_0_lrs1_rtype; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_lrs2_rtype_0 = dis_uops_0_lrs2_rtype; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_frs3_en_0 = dis_uops_0_frs3_en; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_fp_val_0 = dis_uops_0_fp_val; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_fp_single_0 = dis_uops_0_fp_single; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_xcpt_pf_if_0 = dis_uops_0_xcpt_pf_if; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_xcpt_ae_if_0 = dis_uops_0_xcpt_ae_if; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_xcpt_ma_if_0 = dis_uops_0_xcpt_ma_if; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_bp_debug_if_0 = dis_uops_0_bp_debug_if; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_bp_xcpt_if_0 = dis_uops_0_bp_xcpt_if; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_debug_fsrc_0 = dis_uops_0_debug_fsrc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_debug_tsrc_0 = dis_uops_0_debug_tsrc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_valid_0 = dis_fire_0; // @[core.scala:51:7, :168:24]
wire _dis_ready_T; // @[core.scala:715:16]
wire dis_ready; // @[core.scala:169:24]
wire iss_valids_0; // @[core.scala:172:24]
wire iss_valids_1; // @[core.scala:172:24]
assign pred_wakeup_bits_uop_uopc = iss_uops_1_uopc; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_uopc = iss_uops_1_uopc; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_inst = iss_uops_1_inst; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_inst = iss_uops_1_inst; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_debug_inst = iss_uops_1_debug_inst; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_debug_inst = iss_uops_1_debug_inst; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_is_rvc = iss_uops_1_is_rvc; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_is_rvc = iss_uops_1_is_rvc; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_debug_pc = iss_uops_1_debug_pc; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_debug_pc = iss_uops_1_debug_pc; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_iq_type = iss_uops_1_iq_type; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_iq_type = iss_uops_1_iq_type; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_fu_code = iss_uops_1_fu_code; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_fu_code = iss_uops_1_fu_code; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ctrl_br_type = iss_uops_1_ctrl_br_type; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ctrl_br_type = iss_uops_1_ctrl_br_type; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ctrl_op1_sel = iss_uops_1_ctrl_op1_sel; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ctrl_op1_sel = iss_uops_1_ctrl_op1_sel; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ctrl_op2_sel = iss_uops_1_ctrl_op2_sel; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ctrl_op2_sel = iss_uops_1_ctrl_op2_sel; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ctrl_imm_sel = iss_uops_1_ctrl_imm_sel; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ctrl_imm_sel = iss_uops_1_ctrl_imm_sel; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ctrl_op_fcn = iss_uops_1_ctrl_op_fcn; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ctrl_op_fcn = iss_uops_1_ctrl_op_fcn; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ctrl_fcn_dw = iss_uops_1_ctrl_fcn_dw; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ctrl_fcn_dw = iss_uops_1_ctrl_fcn_dw; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ctrl_csr_cmd = iss_uops_1_ctrl_csr_cmd; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ctrl_csr_cmd = iss_uops_1_ctrl_csr_cmd; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ctrl_is_load = iss_uops_1_ctrl_is_load; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ctrl_is_load = iss_uops_1_ctrl_is_load; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ctrl_is_sta = iss_uops_1_ctrl_is_sta; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ctrl_is_sta = iss_uops_1_ctrl_is_sta; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ctrl_is_std = iss_uops_1_ctrl_is_std; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ctrl_is_std = iss_uops_1_ctrl_is_std; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_iw_state = iss_uops_1_iw_state; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_iw_state = iss_uops_1_iw_state; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_iw_p1_poisoned = iss_uops_1_iw_p1_poisoned; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_iw_p1_poisoned = iss_uops_1_iw_p1_poisoned; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_iw_p2_poisoned = iss_uops_1_iw_p2_poisoned; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_iw_p2_poisoned = iss_uops_1_iw_p2_poisoned; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_is_br = iss_uops_1_is_br; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_is_br = iss_uops_1_is_br; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_is_jalr = iss_uops_1_is_jalr; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_is_jalr = iss_uops_1_is_jalr; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_is_jal = iss_uops_1_is_jal; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_is_jal = iss_uops_1_is_jal; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_is_sfb = iss_uops_1_is_sfb; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_is_sfb = iss_uops_1_is_sfb; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_br_mask = iss_uops_1_br_mask; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_br_mask = iss_uops_1_br_mask; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_br_tag = iss_uops_1_br_tag; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_br_tag = iss_uops_1_br_tag; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ftq_idx = iss_uops_1_ftq_idx; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ftq_idx = iss_uops_1_ftq_idx; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_edge_inst = iss_uops_1_edge_inst; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_edge_inst = iss_uops_1_edge_inst; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_pc_lob = iss_uops_1_pc_lob; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_pc_lob = iss_uops_1_pc_lob; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_taken = iss_uops_1_taken; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_taken = iss_uops_1_taken; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_imm_packed = iss_uops_1_imm_packed; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_imm_packed = iss_uops_1_imm_packed; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_csr_addr = iss_uops_1_csr_addr; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_csr_addr = iss_uops_1_csr_addr; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_rob_idx = iss_uops_1_rob_idx; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_rob_idx = iss_uops_1_rob_idx; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ldq_idx = iss_uops_1_ldq_idx; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ldq_idx = iss_uops_1_ldq_idx; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_stq_idx = iss_uops_1_stq_idx; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_stq_idx = iss_uops_1_stq_idx; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_rxq_idx = iss_uops_1_rxq_idx; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_rxq_idx = iss_uops_1_rxq_idx; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_pdst = iss_uops_1_pdst; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_pdst = iss_uops_1_pdst; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_prs1 = iss_uops_1_prs1; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_prs1 = iss_uops_1_prs1; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_prs2 = iss_uops_1_prs2; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_prs2 = iss_uops_1_prs2; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_prs3 = iss_uops_1_prs3; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_prs3 = iss_uops_1_prs3; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ppred = iss_uops_1_ppred; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ppred = iss_uops_1_ppred; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_prs1_busy = iss_uops_1_prs1_busy; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_prs1_busy = iss_uops_1_prs1_busy; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_prs2_busy = iss_uops_1_prs2_busy; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_prs2_busy = iss_uops_1_prs2_busy; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_prs3_busy = iss_uops_1_prs3_busy; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_prs3_busy = iss_uops_1_prs3_busy; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ppred_busy = iss_uops_1_ppred_busy; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ppred_busy = iss_uops_1_ppred_busy; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_stale_pdst = iss_uops_1_stale_pdst; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_stale_pdst = iss_uops_1_stale_pdst; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_exception = iss_uops_1_exception; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_exception = iss_uops_1_exception; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_exc_cause = iss_uops_1_exc_cause; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_exc_cause = iss_uops_1_exc_cause; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_bypassable = iss_uops_1_bypassable; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_bypassable = iss_uops_1_bypassable; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_mem_cmd = iss_uops_1_mem_cmd; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_mem_cmd = iss_uops_1_mem_cmd; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_mem_size = iss_uops_1_mem_size; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_mem_size = iss_uops_1_mem_size; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_mem_signed = iss_uops_1_mem_signed; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_mem_signed = iss_uops_1_mem_signed; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_is_fence = iss_uops_1_is_fence; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_is_fence = iss_uops_1_is_fence; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_is_fencei = iss_uops_1_is_fencei; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_is_fencei = iss_uops_1_is_fencei; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_is_amo = iss_uops_1_is_amo; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_is_amo = iss_uops_1_is_amo; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_uses_ldq = iss_uops_1_uses_ldq; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_uses_ldq = iss_uops_1_uses_ldq; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_uses_stq = iss_uops_1_uses_stq; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_uses_stq = iss_uops_1_uses_stq; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_is_sys_pc2epc = iss_uops_1_is_sys_pc2epc; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_is_sys_pc2epc = iss_uops_1_is_sys_pc2epc; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_is_unique = iss_uops_1_is_unique; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_is_unique = iss_uops_1_is_unique; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_flush_on_commit = iss_uops_1_flush_on_commit; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_flush_on_commit = iss_uops_1_flush_on_commit; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ldst_is_rs1 = iss_uops_1_ldst_is_rs1; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ldst_is_rs1 = iss_uops_1_ldst_is_rs1; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ldst = iss_uops_1_ldst; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ldst = iss_uops_1_ldst; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_lrs1 = iss_uops_1_lrs1; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_lrs1 = iss_uops_1_lrs1; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_lrs2 = iss_uops_1_lrs2; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_lrs2 = iss_uops_1_lrs2; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_lrs3 = iss_uops_1_lrs3; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_lrs3 = iss_uops_1_lrs3; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ldst_val = iss_uops_1_ldst_val; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ldst_val = iss_uops_1_ldst_val; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_dst_rtype = iss_uops_1_dst_rtype; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_dst_rtype = iss_uops_1_dst_rtype; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_lrs1_rtype = iss_uops_1_lrs1_rtype; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_lrs1_rtype = iss_uops_1_lrs1_rtype; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_lrs2_rtype = iss_uops_1_lrs2_rtype; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_lrs2_rtype = iss_uops_1_lrs2_rtype; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_frs3_en = iss_uops_1_frs3_en; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_frs3_en = iss_uops_1_frs3_en; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_fp_val = iss_uops_1_fp_val; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_fp_val = iss_uops_1_fp_val; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_fp_single = iss_uops_1_fp_single; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_fp_single = iss_uops_1_fp_single; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_xcpt_pf_if = iss_uops_1_xcpt_pf_if; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_xcpt_pf_if = iss_uops_1_xcpt_pf_if; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_xcpt_ae_if = iss_uops_1_xcpt_ae_if; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_xcpt_ae_if = iss_uops_1_xcpt_ae_if; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_xcpt_ma_if = iss_uops_1_xcpt_ma_if; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_xcpt_ma_if = iss_uops_1_xcpt_ma_if; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_bp_debug_if = iss_uops_1_bp_debug_if; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_bp_debug_if = iss_uops_1_bp_debug_if; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_bp_xcpt_if = iss_uops_1_bp_xcpt_if; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_bp_xcpt_if = iss_uops_1_bp_xcpt_if; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_debug_fsrc = iss_uops_1_debug_fsrc; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_debug_fsrc = iss_uops_1_debug_fsrc; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_debug_tsrc = iss_uops_1_debug_tsrc; // @[core.scala:149:26, :173:24]
wire [3:0] iss_uops_0_ctrl_br_type; // @[core.scala:173:24]
wire [1:0] iss_uops_0_ctrl_op1_sel; // @[core.scala:173:24]
wire [2:0] iss_uops_0_ctrl_op2_sel; // @[core.scala:173:24]
wire [2:0] iss_uops_0_ctrl_imm_sel; // @[core.scala:173:24]
wire [4:0] iss_uops_0_ctrl_op_fcn; // @[core.scala:173:24]
wire iss_uops_0_ctrl_fcn_dw; // @[core.scala:173:24]
wire [2:0] iss_uops_0_ctrl_csr_cmd; // @[core.scala:173:24]
wire iss_uops_0_ctrl_is_load; // @[core.scala:173:24]
wire iss_uops_0_ctrl_is_sta; // @[core.scala:173:24]
wire iss_uops_0_ctrl_is_std; // @[core.scala:173:24]
assign fast_wakeup_bits_uop_debug_tsrc = iss_uops_1_debug_tsrc; // @[core.scala:173:24, :814:29]
wire [6:0] iss_uops_0_uopc; // @[core.scala:173:24]
wire [31:0] iss_uops_0_inst; // @[core.scala:173:24]
wire [31:0] iss_uops_0_debug_inst; // @[core.scala:173:24]
wire iss_uops_0_is_rvc; // @[core.scala:173:24]
wire [39:0] iss_uops_0_debug_pc; // @[core.scala:173:24]
wire [2:0] iss_uops_0_iq_type; // @[core.scala:173:24]
wire [9:0] iss_uops_0_fu_code; // @[core.scala:173:24]
wire [1:0] iss_uops_0_iw_state; // @[core.scala:173:24]
wire iss_uops_0_iw_p1_poisoned; // @[core.scala:173:24]
wire iss_uops_0_iw_p2_poisoned; // @[core.scala:173:24]
wire iss_uops_0_is_br; // @[core.scala:173:24]
wire iss_uops_0_is_jalr; // @[core.scala:173:24]
wire iss_uops_0_is_jal; // @[core.scala:173:24]
wire iss_uops_0_is_sfb; // @[core.scala:173:24]
wire [7:0] iss_uops_0_br_mask; // @[core.scala:173:24]
wire [2:0] iss_uops_0_br_tag; // @[core.scala:173:24]
wire [3:0] iss_uops_0_ftq_idx; // @[core.scala:173:24]
wire iss_uops_0_edge_inst; // @[core.scala:173:24]
wire [5:0] iss_uops_0_pc_lob; // @[core.scala:173:24]
wire iss_uops_0_taken; // @[core.scala:173:24]
wire [19:0] iss_uops_0_imm_packed; // @[core.scala:173:24]
wire [11:0] iss_uops_0_csr_addr; // @[core.scala:173:24]
wire [4:0] iss_uops_0_rob_idx; // @[core.scala:173:24]
wire [2:0] iss_uops_0_ldq_idx; // @[core.scala:173:24]
wire [2:0] iss_uops_0_stq_idx; // @[core.scala:173:24]
wire [1:0] iss_uops_0_rxq_idx; // @[core.scala:173:24]
wire [5:0] iss_uops_0_pdst; // @[core.scala:173:24]
wire [5:0] iss_uops_0_prs1; // @[core.scala:173:24]
wire [5:0] iss_uops_0_prs2; // @[core.scala:173:24]
wire [5:0] iss_uops_0_prs3; // @[core.scala:173:24]
wire [3:0] iss_uops_0_ppred; // @[core.scala:173:24]
wire iss_uops_0_prs1_busy; // @[core.scala:173:24]
wire iss_uops_0_prs2_busy; // @[core.scala:173:24]
wire iss_uops_0_prs3_busy; // @[core.scala:173:24]
wire iss_uops_0_ppred_busy; // @[core.scala:173:24]
wire [5:0] iss_uops_0_stale_pdst; // @[core.scala:173:24]
wire iss_uops_0_exception; // @[core.scala:173:24]
wire [63:0] iss_uops_0_exc_cause; // @[core.scala:173:24]
wire iss_uops_0_bypassable; // @[core.scala:173:24]
wire [4:0] iss_uops_0_mem_cmd; // @[core.scala:173:24]
wire [1:0] iss_uops_0_mem_size; // @[core.scala:173:24]
wire iss_uops_0_mem_signed; // @[core.scala:173:24]
wire iss_uops_0_is_fence; // @[core.scala:173:24]
wire iss_uops_0_is_fencei; // @[core.scala:173:24]
wire iss_uops_0_is_amo; // @[core.scala:173:24]
wire iss_uops_0_uses_ldq; // @[core.scala:173:24]
wire iss_uops_0_uses_stq; // @[core.scala:173:24]
wire iss_uops_0_is_sys_pc2epc; // @[core.scala:173:24]
wire iss_uops_0_is_unique; // @[core.scala:173:24]
wire iss_uops_0_flush_on_commit; // @[core.scala:173:24]
wire iss_uops_0_ldst_is_rs1; // @[core.scala:173:24]
wire [5:0] iss_uops_0_ldst; // @[core.scala:173:24]
wire [5:0] iss_uops_0_lrs1; // @[core.scala:173:24]
wire [5:0] iss_uops_0_lrs2; // @[core.scala:173:24]
wire [5:0] iss_uops_0_lrs3; // @[core.scala:173:24]
wire iss_uops_0_ldst_val; // @[core.scala:173:24]
wire [1:0] iss_uops_0_dst_rtype; // @[core.scala:173:24]
wire [1:0] iss_uops_0_lrs1_rtype; // @[core.scala:173:24]
wire [1:0] iss_uops_0_lrs2_rtype; // @[core.scala:173:24]
wire iss_uops_0_frs3_en; // @[core.scala:173:24]
wire iss_uops_0_fp_val; // @[core.scala:173:24]
wire iss_uops_0_fp_single; // @[core.scala:173:24]
wire iss_uops_0_xcpt_pf_if; // @[core.scala:173:24]
wire iss_uops_0_xcpt_ae_if; // @[core.scala:173:24]
wire iss_uops_0_xcpt_ma_if; // @[core.scala:173:24]
wire iss_uops_0_bp_debug_if; // @[core.scala:173:24]
wire iss_uops_0_bp_xcpt_if; // @[core.scala:173:24]
wire [1:0] iss_uops_0_debug_fsrc; // @[core.scala:173:24]
wire [1:0] iss_uops_0_debug_tsrc; // @[core.scala:173:24]
wire [3:0] bypasses_0_bits_uop_ctrl_br_type; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_uop_ctrl_op1_sel; // @[core.scala:174:24]
wire [2:0] bypasses_0_bits_uop_ctrl_op2_sel; // @[core.scala:174:24]
wire [2:0] bypasses_0_bits_uop_ctrl_imm_sel; // @[core.scala:174:24]
wire [4:0] bypasses_0_bits_uop_ctrl_op_fcn; // @[core.scala:174:24]
wire bypasses_0_bits_uop_ctrl_fcn_dw; // @[core.scala:174:24]
wire [2:0] bypasses_0_bits_uop_ctrl_csr_cmd; // @[core.scala:174:24]
wire bypasses_0_bits_uop_ctrl_is_load; // @[core.scala:174:24]
wire bypasses_0_bits_uop_ctrl_is_sta; // @[core.scala:174:24]
wire bypasses_0_bits_uop_ctrl_is_std; // @[core.scala:174:24]
wire [6:0] bypasses_0_bits_uop_uopc; // @[core.scala:174:24]
wire [31:0] bypasses_0_bits_uop_inst; // @[core.scala:174:24]
wire [31:0] bypasses_0_bits_uop_debug_inst; // @[core.scala:174:24]
wire bypasses_0_bits_uop_is_rvc; // @[core.scala:174:24]
wire [39:0] bypasses_0_bits_uop_debug_pc; // @[core.scala:174:24]
wire [2:0] bypasses_0_bits_uop_iq_type; // @[core.scala:174:24]
wire [9:0] bypasses_0_bits_uop_fu_code; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_uop_iw_state; // @[core.scala:174:24]
wire bypasses_0_bits_uop_iw_p1_poisoned; // @[core.scala:174:24]
wire bypasses_0_bits_uop_iw_p2_poisoned; // @[core.scala:174:24]
wire bypasses_0_bits_uop_is_br; // @[core.scala:174:24]
wire bypasses_0_bits_uop_is_jalr; // @[core.scala:174:24]
wire bypasses_0_bits_uop_is_jal; // @[core.scala:174:24]
wire bypasses_0_bits_uop_is_sfb; // @[core.scala:174:24]
wire [7:0] bypasses_0_bits_uop_br_mask; // @[core.scala:174:24]
wire [2:0] bypasses_0_bits_uop_br_tag; // @[core.scala:174:24]
wire [3:0] bypasses_0_bits_uop_ftq_idx; // @[core.scala:174:24]
wire bypasses_0_bits_uop_edge_inst; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_uop_pc_lob; // @[core.scala:174:24]
wire bypasses_0_bits_uop_taken; // @[core.scala:174:24]
wire [19:0] bypasses_0_bits_uop_imm_packed; // @[core.scala:174:24]
wire [11:0] bypasses_0_bits_uop_csr_addr; // @[core.scala:174:24]
wire [4:0] bypasses_0_bits_uop_rob_idx; // @[core.scala:174:24]
wire [2:0] bypasses_0_bits_uop_ldq_idx; // @[core.scala:174:24]
wire [2:0] bypasses_0_bits_uop_stq_idx; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_uop_rxq_idx; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_uop_pdst; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_uop_prs1; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_uop_prs2; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_uop_prs3; // @[core.scala:174:24]
wire [3:0] bypasses_0_bits_uop_ppred; // @[core.scala:174:24]
wire bypasses_0_bits_uop_prs1_busy; // @[core.scala:174:24]
wire bypasses_0_bits_uop_prs2_busy; // @[core.scala:174:24]
wire bypasses_0_bits_uop_prs3_busy; // @[core.scala:174:24]
wire bypasses_0_bits_uop_ppred_busy; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_uop_stale_pdst; // @[core.scala:174:24]
wire bypasses_0_bits_uop_exception; // @[core.scala:174:24]
wire [63:0] bypasses_0_bits_uop_exc_cause; // @[core.scala:174:24]
wire bypasses_0_bits_uop_bypassable; // @[core.scala:174:24]
wire [4:0] bypasses_0_bits_uop_mem_cmd; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_uop_mem_size; // @[core.scala:174:24]
wire bypasses_0_bits_uop_mem_signed; // @[core.scala:174:24]
wire bypasses_0_bits_uop_is_fence; // @[core.scala:174:24]
wire bypasses_0_bits_uop_is_fencei; // @[core.scala:174:24]
wire bypasses_0_bits_uop_is_amo; // @[core.scala:174:24]
wire bypasses_0_bits_uop_uses_ldq; // @[core.scala:174:24]
wire bypasses_0_bits_uop_uses_stq; // @[core.scala:174:24]
wire bypasses_0_bits_uop_is_sys_pc2epc; // @[core.scala:174:24]
wire bypasses_0_bits_uop_is_unique; // @[core.scala:174:24]
wire bypasses_0_bits_uop_flush_on_commit; // @[core.scala:174:24]
wire bypasses_0_bits_uop_ldst_is_rs1; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_uop_ldst; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_uop_lrs1; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_uop_lrs2; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_uop_lrs3; // @[core.scala:174:24]
wire bypasses_0_bits_uop_ldst_val; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_uop_dst_rtype; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_uop_lrs1_rtype; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_uop_lrs2_rtype; // @[core.scala:174:24]
wire bypasses_0_bits_uop_frs3_en; // @[core.scala:174:24]
wire bypasses_0_bits_uop_fp_val; // @[core.scala:174:24]
wire bypasses_0_bits_uop_fp_single; // @[core.scala:174:24]
wire bypasses_0_bits_uop_xcpt_pf_if; // @[core.scala:174:24]
wire bypasses_0_bits_uop_xcpt_ae_if; // @[core.scala:174:24]
wire bypasses_0_bits_uop_xcpt_ma_if; // @[core.scala:174:24]
wire bypasses_0_bits_uop_bp_debug_if; // @[core.scala:174:24]
wire bypasses_0_bits_uop_bp_xcpt_if; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_uop_debug_fsrc; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_uop_debug_tsrc; // @[core.scala:174:24]
wire [63:0] bypasses_0_bits_data; // @[core.scala:174:24]
wire bypasses_0_valid; // @[core.scala:174:24]
wire [3:0] bypasses_1_bits_uop_ctrl_br_type; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_uop_ctrl_op1_sel; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_uop_ctrl_op2_sel; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_uop_ctrl_imm_sel; // @[core.scala:174:24]
wire [4:0] bypasses_1_bits_uop_ctrl_op_fcn; // @[core.scala:174:24]
wire bypasses_1_bits_uop_ctrl_fcn_dw; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_uop_ctrl_csr_cmd; // @[core.scala:174:24]
wire bypasses_1_bits_uop_ctrl_is_load; // @[core.scala:174:24]
wire bypasses_1_bits_uop_ctrl_is_sta; // @[core.scala:174:24]
wire bypasses_1_bits_uop_ctrl_is_std; // @[core.scala:174:24]
wire [6:0] bypasses_1_bits_uop_uopc; // @[core.scala:174:24]
wire [31:0] bypasses_1_bits_uop_inst; // @[core.scala:174:24]
wire [31:0] bypasses_1_bits_uop_debug_inst; // @[core.scala:174:24]
wire bypasses_1_bits_uop_is_rvc; // @[core.scala:174:24]
wire [39:0] bypasses_1_bits_uop_debug_pc; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_uop_iq_type; // @[core.scala:174:24]
wire [9:0] bypasses_1_bits_uop_fu_code; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_uop_iw_state; // @[core.scala:174:24]
wire bypasses_1_bits_uop_iw_p1_poisoned; // @[core.scala:174:24]
wire bypasses_1_bits_uop_iw_p2_poisoned; // @[core.scala:174:24]
wire bypasses_1_bits_uop_is_br; // @[core.scala:174:24]
wire bypasses_1_bits_uop_is_jalr; // @[core.scala:174:24]
wire bypasses_1_bits_uop_is_jal; // @[core.scala:174:24]
wire bypasses_1_bits_uop_is_sfb; // @[core.scala:174:24]
wire [7:0] bypasses_1_bits_uop_br_mask; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_uop_br_tag; // @[core.scala:174:24]
wire [3:0] bypasses_1_bits_uop_ftq_idx; // @[core.scala:174:24]
wire bypasses_1_bits_uop_edge_inst; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_uop_pc_lob; // @[core.scala:174:24]
wire bypasses_1_bits_uop_taken; // @[core.scala:174:24]
wire [19:0] bypasses_1_bits_uop_imm_packed; // @[core.scala:174:24]
wire [11:0] bypasses_1_bits_uop_csr_addr; // @[core.scala:174:24]
wire [4:0] bypasses_1_bits_uop_rob_idx; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_uop_ldq_idx; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_uop_stq_idx; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_uop_rxq_idx; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_uop_pdst; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_uop_prs1; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_uop_prs2; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_uop_prs3; // @[core.scala:174:24]
wire [3:0] bypasses_1_bits_uop_ppred; // @[core.scala:174:24]
wire bypasses_1_bits_uop_prs1_busy; // @[core.scala:174:24]
wire bypasses_1_bits_uop_prs2_busy; // @[core.scala:174:24]
wire bypasses_1_bits_uop_prs3_busy; // @[core.scala:174:24]
wire bypasses_1_bits_uop_ppred_busy; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_uop_stale_pdst; // @[core.scala:174:24]
wire bypasses_1_bits_uop_exception; // @[core.scala:174:24]
wire [63:0] bypasses_1_bits_uop_exc_cause; // @[core.scala:174:24]
wire bypasses_1_bits_uop_bypassable; // @[core.scala:174:24]
wire [4:0] bypasses_1_bits_uop_mem_cmd; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_uop_mem_size; // @[core.scala:174:24]
wire bypasses_1_bits_uop_mem_signed; // @[core.scala:174:24]
wire bypasses_1_bits_uop_is_fence; // @[core.scala:174:24]
wire bypasses_1_bits_uop_is_fencei; // @[core.scala:174:24]
wire bypasses_1_bits_uop_is_amo; // @[core.scala:174:24]
wire bypasses_1_bits_uop_uses_ldq; // @[core.scala:174:24]
wire bypasses_1_bits_uop_uses_stq; // @[core.scala:174:24]
wire bypasses_1_bits_uop_is_sys_pc2epc; // @[core.scala:174:24]
wire bypasses_1_bits_uop_is_unique; // @[core.scala:174:24]
wire bypasses_1_bits_uop_flush_on_commit; // @[core.scala:174:24]
wire bypasses_1_bits_uop_ldst_is_rs1; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_uop_ldst; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_uop_lrs1; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_uop_lrs2; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_uop_lrs3; // @[core.scala:174:24]
wire bypasses_1_bits_uop_ldst_val; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_uop_dst_rtype; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_uop_lrs1_rtype; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_uop_lrs2_rtype; // @[core.scala:174:24]
wire bypasses_1_bits_uop_frs3_en; // @[core.scala:174:24]
wire bypasses_1_bits_uop_fp_val; // @[core.scala:174:24]
wire bypasses_1_bits_uop_fp_single; // @[core.scala:174:24]
wire bypasses_1_bits_uop_xcpt_pf_if; // @[core.scala:174:24]
wire bypasses_1_bits_uop_xcpt_ae_if; // @[core.scala:174:24]
wire bypasses_1_bits_uop_xcpt_ma_if; // @[core.scala:174:24]
wire bypasses_1_bits_uop_bp_debug_if; // @[core.scala:174:24]
wire bypasses_1_bits_uop_bp_xcpt_if; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_uop_debug_fsrc; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_uop_debug_tsrc; // @[core.scala:174:24]
wire [63:0] bypasses_1_bits_data; // @[core.scala:174:24]
wire bypasses_1_valid; // @[core.scala:174:24]
wire [3:0] bypasses_2_bits_uop_ctrl_br_type; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_uop_ctrl_op1_sel; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_uop_ctrl_op2_sel; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_uop_ctrl_imm_sel; // @[core.scala:174:24]
wire [4:0] bypasses_2_bits_uop_ctrl_op_fcn; // @[core.scala:174:24]
wire bypasses_2_bits_uop_ctrl_fcn_dw; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_uop_ctrl_csr_cmd; // @[core.scala:174:24]
wire bypasses_2_bits_uop_ctrl_is_load; // @[core.scala:174:24]
wire bypasses_2_bits_uop_ctrl_is_sta; // @[core.scala:174:24]
wire bypasses_2_bits_uop_ctrl_is_std; // @[core.scala:174:24]
wire [6:0] bypasses_2_bits_uop_uopc; // @[core.scala:174:24]
wire [31:0] bypasses_2_bits_uop_inst; // @[core.scala:174:24]
wire [31:0] bypasses_2_bits_uop_debug_inst; // @[core.scala:174:24]
wire bypasses_2_bits_uop_is_rvc; // @[core.scala:174:24]
wire [39:0] bypasses_2_bits_uop_debug_pc; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_uop_iq_type; // @[core.scala:174:24]
wire [9:0] bypasses_2_bits_uop_fu_code; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_uop_iw_state; // @[core.scala:174:24]
wire bypasses_2_bits_uop_iw_p1_poisoned; // @[core.scala:174:24]
wire bypasses_2_bits_uop_iw_p2_poisoned; // @[core.scala:174:24]
wire bypasses_2_bits_uop_is_br; // @[core.scala:174:24]
wire bypasses_2_bits_uop_is_jalr; // @[core.scala:174:24]
wire bypasses_2_bits_uop_is_jal; // @[core.scala:174:24]
wire bypasses_2_bits_uop_is_sfb; // @[core.scala:174:24]
wire [7:0] bypasses_2_bits_uop_br_mask; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_uop_br_tag; // @[core.scala:174:24]
wire [3:0] bypasses_2_bits_uop_ftq_idx; // @[core.scala:174:24]
wire bypasses_2_bits_uop_edge_inst; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_uop_pc_lob; // @[core.scala:174:24]
wire bypasses_2_bits_uop_taken; // @[core.scala:174:24]
wire [19:0] bypasses_2_bits_uop_imm_packed; // @[core.scala:174:24]
wire [11:0] bypasses_2_bits_uop_csr_addr; // @[core.scala:174:24]
wire [4:0] bypasses_2_bits_uop_rob_idx; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_uop_ldq_idx; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_uop_stq_idx; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_uop_rxq_idx; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_uop_pdst; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_uop_prs1; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_uop_prs2; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_uop_prs3; // @[core.scala:174:24]
wire [3:0] bypasses_2_bits_uop_ppred; // @[core.scala:174:24]
wire bypasses_2_bits_uop_prs1_busy; // @[core.scala:174:24]
wire bypasses_2_bits_uop_prs2_busy; // @[core.scala:174:24]
wire bypasses_2_bits_uop_prs3_busy; // @[core.scala:174:24]
wire bypasses_2_bits_uop_ppred_busy; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_uop_stale_pdst; // @[core.scala:174:24]
wire bypasses_2_bits_uop_exception; // @[core.scala:174:24]
wire [63:0] bypasses_2_bits_uop_exc_cause; // @[core.scala:174:24]
wire bypasses_2_bits_uop_bypassable; // @[core.scala:174:24]
wire [4:0] bypasses_2_bits_uop_mem_cmd; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_uop_mem_size; // @[core.scala:174:24]
wire bypasses_2_bits_uop_mem_signed; // @[core.scala:174:24]
wire bypasses_2_bits_uop_is_fence; // @[core.scala:174:24]
wire bypasses_2_bits_uop_is_fencei; // @[core.scala:174:24]
wire bypasses_2_bits_uop_is_amo; // @[core.scala:174:24]
wire bypasses_2_bits_uop_uses_ldq; // @[core.scala:174:24]
wire bypasses_2_bits_uop_uses_stq; // @[core.scala:174:24]
wire bypasses_2_bits_uop_is_sys_pc2epc; // @[core.scala:174:24]
wire bypasses_2_bits_uop_is_unique; // @[core.scala:174:24]
wire bypasses_2_bits_uop_flush_on_commit; // @[core.scala:174:24]
wire bypasses_2_bits_uop_ldst_is_rs1; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_uop_ldst; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_uop_lrs1; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_uop_lrs2; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_uop_lrs3; // @[core.scala:174:24]
wire bypasses_2_bits_uop_ldst_val; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_uop_dst_rtype; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_uop_lrs1_rtype; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_uop_lrs2_rtype; // @[core.scala:174:24]
wire bypasses_2_bits_uop_frs3_en; // @[core.scala:174:24]
wire bypasses_2_bits_uop_fp_val; // @[core.scala:174:24]
wire bypasses_2_bits_uop_fp_single; // @[core.scala:174:24]
wire bypasses_2_bits_uop_xcpt_pf_if; // @[core.scala:174:24]
wire bypasses_2_bits_uop_xcpt_ae_if; // @[core.scala:174:24]
wire bypasses_2_bits_uop_xcpt_ma_if; // @[core.scala:174:24]
wire bypasses_2_bits_uop_bp_debug_if; // @[core.scala:174:24]
wire bypasses_2_bits_uop_bp_xcpt_if; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_uop_debug_fsrc; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_uop_debug_tsrc; // @[core.scala:174:24]
wire [63:0] bypasses_2_bits_data; // @[core.scala:174:24]
wire bypasses_2_valid; // @[core.scala:174:24]
wire [3:0] pred_bypasses_0_bits_uop_ctrl_br_type; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_uop_ctrl_op1_sel; // @[core.scala:175:27]
wire [2:0] pred_bypasses_0_bits_uop_ctrl_op2_sel; // @[core.scala:175:27]
wire [2:0] pred_bypasses_0_bits_uop_ctrl_imm_sel; // @[core.scala:175:27]
wire [4:0] pred_bypasses_0_bits_uop_ctrl_op_fcn; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_ctrl_fcn_dw; // @[core.scala:175:27]
wire [2:0] pred_bypasses_0_bits_uop_ctrl_csr_cmd; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_ctrl_is_load; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_ctrl_is_sta; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_ctrl_is_std; // @[core.scala:175:27]
wire [6:0] pred_bypasses_0_bits_uop_uopc; // @[core.scala:175:27]
wire [31:0] pred_bypasses_0_bits_uop_inst; // @[core.scala:175:27]
wire [31:0] pred_bypasses_0_bits_uop_debug_inst; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_is_rvc; // @[core.scala:175:27]
wire [39:0] pred_bypasses_0_bits_uop_debug_pc; // @[core.scala:175:27]
wire [2:0] pred_bypasses_0_bits_uop_iq_type; // @[core.scala:175:27]
wire [9:0] pred_bypasses_0_bits_uop_fu_code; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_uop_iw_state; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_iw_p1_poisoned; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_iw_p2_poisoned; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_is_br; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_is_jalr; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_is_jal; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_is_sfb; // @[core.scala:175:27]
wire [7:0] pred_bypasses_0_bits_uop_br_mask; // @[core.scala:175:27]
wire [2:0] pred_bypasses_0_bits_uop_br_tag; // @[core.scala:175:27]
wire [3:0] pred_bypasses_0_bits_uop_ftq_idx; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_edge_inst; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_uop_pc_lob; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_taken; // @[core.scala:175:27]
wire [19:0] pred_bypasses_0_bits_uop_imm_packed; // @[core.scala:175:27]
wire [11:0] pred_bypasses_0_bits_uop_csr_addr; // @[core.scala:175:27]
wire [4:0] pred_bypasses_0_bits_uop_rob_idx; // @[core.scala:175:27]
wire [2:0] pred_bypasses_0_bits_uop_ldq_idx; // @[core.scala:175:27]
wire [2:0] pred_bypasses_0_bits_uop_stq_idx; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_uop_rxq_idx; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_uop_pdst; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_uop_prs1; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_uop_prs2; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_uop_prs3; // @[core.scala:175:27]
wire [3:0] pred_bypasses_0_bits_uop_ppred; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_prs1_busy; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_prs2_busy; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_prs3_busy; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_ppred_busy; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_uop_stale_pdst; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_exception; // @[core.scala:175:27]
wire [63:0] pred_bypasses_0_bits_uop_exc_cause; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_bypassable; // @[core.scala:175:27]
wire [4:0] pred_bypasses_0_bits_uop_mem_cmd; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_uop_mem_size; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_mem_signed; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_is_fence; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_is_fencei; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_is_amo; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_uses_ldq; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_uses_stq; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_is_sys_pc2epc; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_is_unique; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_flush_on_commit; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_ldst_is_rs1; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_uop_ldst; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_uop_lrs1; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_uop_lrs2; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_uop_lrs3; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_ldst_val; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_uop_dst_rtype; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_uop_lrs1_rtype; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_uop_lrs2_rtype; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_frs3_en; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_fp_val; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_fp_single; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_xcpt_pf_if; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_xcpt_ae_if; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_xcpt_ma_if; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_bp_debug_if; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_bp_xcpt_if; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_uop_debug_fsrc; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_uop_debug_tsrc; // @[core.scala:175:27]
wire pred_bypasses_0_bits_data; // @[core.scala:175:27]
wire pred_bypasses_0_valid; // @[core.scala:175:27]
wire [3:0] pred_bypasses_1_bits_uop_ctrl_br_type; // @[core.scala:175:27]
wire [1:0] pred_bypasses_1_bits_uop_ctrl_op1_sel; // @[core.scala:175:27]
wire [2:0] pred_bypasses_1_bits_uop_ctrl_op2_sel; // @[core.scala:175:27]
wire [2:0] pred_bypasses_1_bits_uop_ctrl_imm_sel; // @[core.scala:175:27]
wire [4:0] pred_bypasses_1_bits_uop_ctrl_op_fcn; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_ctrl_fcn_dw; // @[core.scala:175:27]
wire [2:0] pred_bypasses_1_bits_uop_ctrl_csr_cmd; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_ctrl_is_load; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_ctrl_is_sta; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_ctrl_is_std; // @[core.scala:175:27]
wire [6:0] pred_bypasses_1_bits_uop_uopc; // @[core.scala:175:27]
wire [31:0] pred_bypasses_1_bits_uop_inst; // @[core.scala:175:27]
wire [31:0] pred_bypasses_1_bits_uop_debug_inst; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_is_rvc; // @[core.scala:175:27]
wire [39:0] pred_bypasses_1_bits_uop_debug_pc; // @[core.scala:175:27]
wire [2:0] pred_bypasses_1_bits_uop_iq_type; // @[core.scala:175:27]
wire [9:0] pred_bypasses_1_bits_uop_fu_code; // @[core.scala:175:27]
wire [1:0] pred_bypasses_1_bits_uop_iw_state; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_iw_p1_poisoned; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_iw_p2_poisoned; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_is_br; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_is_jalr; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_is_jal; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_is_sfb; // @[core.scala:175:27]
wire [7:0] pred_bypasses_1_bits_uop_br_mask; // @[core.scala:175:27]
wire [2:0] pred_bypasses_1_bits_uop_br_tag; // @[core.scala:175:27]
wire [3:0] pred_bypasses_1_bits_uop_ftq_idx; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_edge_inst; // @[core.scala:175:27]
wire [5:0] pred_bypasses_1_bits_uop_pc_lob; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_taken; // @[core.scala:175:27]
wire [19:0] pred_bypasses_1_bits_uop_imm_packed; // @[core.scala:175:27]
wire [11:0] pred_bypasses_1_bits_uop_csr_addr; // @[core.scala:175:27]
wire [4:0] pred_bypasses_1_bits_uop_rob_idx; // @[core.scala:175:27]
wire [2:0] pred_bypasses_1_bits_uop_ldq_idx; // @[core.scala:175:27]
wire [2:0] pred_bypasses_1_bits_uop_stq_idx; // @[core.scala:175:27]
wire [1:0] pred_bypasses_1_bits_uop_rxq_idx; // @[core.scala:175:27]
wire [5:0] pred_bypasses_1_bits_uop_pdst; // @[core.scala:175:27]
wire [5:0] pred_bypasses_1_bits_uop_prs1; // @[core.scala:175:27]
wire [5:0] pred_bypasses_1_bits_uop_prs2; // @[core.scala:175:27]
wire [5:0] pred_bypasses_1_bits_uop_prs3; // @[core.scala:175:27]
wire [3:0] pred_bypasses_1_bits_uop_ppred; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_prs1_busy; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_prs2_busy; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_prs3_busy; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_ppred_busy; // @[core.scala:175:27]
wire [5:0] pred_bypasses_1_bits_uop_stale_pdst; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_exception; // @[core.scala:175:27]
wire [63:0] pred_bypasses_1_bits_uop_exc_cause; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_bypassable; // @[core.scala:175:27]
wire [4:0] pred_bypasses_1_bits_uop_mem_cmd; // @[core.scala:175:27]
wire [1:0] pred_bypasses_1_bits_uop_mem_size; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_mem_signed; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_is_fence; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_is_fencei; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_is_amo; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_uses_ldq; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_uses_stq; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_is_sys_pc2epc; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_is_unique; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_flush_on_commit; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_ldst_is_rs1; // @[core.scala:175:27]
wire [5:0] pred_bypasses_1_bits_uop_ldst; // @[core.scala:175:27]
wire [5:0] pred_bypasses_1_bits_uop_lrs1; // @[core.scala:175:27]
wire [5:0] pred_bypasses_1_bits_uop_lrs2; // @[core.scala:175:27]
wire [5:0] pred_bypasses_1_bits_uop_lrs3; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_ldst_val; // @[core.scala:175:27]
wire [1:0] pred_bypasses_1_bits_uop_dst_rtype; // @[core.scala:175:27]
wire [1:0] pred_bypasses_1_bits_uop_lrs1_rtype; // @[core.scala:175:27]
wire [1:0] pred_bypasses_1_bits_uop_lrs2_rtype; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_frs3_en; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_fp_val; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_fp_single; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_xcpt_pf_if; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_xcpt_ae_if; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_xcpt_ma_if; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_bp_debug_if; // @[core.scala:175:27]
wire pred_bypasses_1_bits_uop_bp_xcpt_if; // @[core.scala:175:27]
wire [1:0] pred_bypasses_1_bits_uop_debug_fsrc; // @[core.scala:175:27]
wire [1:0] pred_bypasses_1_bits_uop_debug_tsrc; // @[core.scala:175:27]
wire pred_bypasses_1_bits_data; // @[core.scala:175:27]
wire pred_bypasses_1_valid; // @[core.scala:175:27]
wire [3:0] pred_bypasses_2_bits_uop_ctrl_br_type; // @[core.scala:175:27]
wire [1:0] pred_bypasses_2_bits_uop_ctrl_op1_sel; // @[core.scala:175:27]
wire [2:0] pred_bypasses_2_bits_uop_ctrl_op2_sel; // @[core.scala:175:27]
wire [2:0] pred_bypasses_2_bits_uop_ctrl_imm_sel; // @[core.scala:175:27]
wire [4:0] pred_bypasses_2_bits_uop_ctrl_op_fcn; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_ctrl_fcn_dw; // @[core.scala:175:27]
wire [2:0] pred_bypasses_2_bits_uop_ctrl_csr_cmd; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_ctrl_is_load; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_ctrl_is_sta; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_ctrl_is_std; // @[core.scala:175:27]
wire [6:0] pred_bypasses_2_bits_uop_uopc; // @[core.scala:175:27]
wire [31:0] pred_bypasses_2_bits_uop_inst; // @[core.scala:175:27]
wire [31:0] pred_bypasses_2_bits_uop_debug_inst; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_is_rvc; // @[core.scala:175:27]
wire [39:0] pred_bypasses_2_bits_uop_debug_pc; // @[core.scala:175:27]
wire [2:0] pred_bypasses_2_bits_uop_iq_type; // @[core.scala:175:27]
wire [9:0] pred_bypasses_2_bits_uop_fu_code; // @[core.scala:175:27]
wire [1:0] pred_bypasses_2_bits_uop_iw_state; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_iw_p1_poisoned; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_iw_p2_poisoned; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_is_br; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_is_jalr; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_is_jal; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_is_sfb; // @[core.scala:175:27]
wire [7:0] pred_bypasses_2_bits_uop_br_mask; // @[core.scala:175:27]
wire [2:0] pred_bypasses_2_bits_uop_br_tag; // @[core.scala:175:27]
wire [3:0] pred_bypasses_2_bits_uop_ftq_idx; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_edge_inst; // @[core.scala:175:27]
wire [5:0] pred_bypasses_2_bits_uop_pc_lob; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_taken; // @[core.scala:175:27]
wire [19:0] pred_bypasses_2_bits_uop_imm_packed; // @[core.scala:175:27]
wire [11:0] pred_bypasses_2_bits_uop_csr_addr; // @[core.scala:175:27]
wire [4:0] pred_bypasses_2_bits_uop_rob_idx; // @[core.scala:175:27]
wire [2:0] pred_bypasses_2_bits_uop_ldq_idx; // @[core.scala:175:27]
wire [2:0] pred_bypasses_2_bits_uop_stq_idx; // @[core.scala:175:27]
wire [1:0] pred_bypasses_2_bits_uop_rxq_idx; // @[core.scala:175:27]
wire [5:0] pred_bypasses_2_bits_uop_pdst; // @[core.scala:175:27]
wire [5:0] pred_bypasses_2_bits_uop_prs1; // @[core.scala:175:27]
wire [5:0] pred_bypasses_2_bits_uop_prs2; // @[core.scala:175:27]
wire [5:0] pred_bypasses_2_bits_uop_prs3; // @[core.scala:175:27]
wire [3:0] pred_bypasses_2_bits_uop_ppred; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_prs1_busy; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_prs2_busy; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_prs3_busy; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_ppred_busy; // @[core.scala:175:27]
wire [5:0] pred_bypasses_2_bits_uop_stale_pdst; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_exception; // @[core.scala:175:27]
wire [63:0] pred_bypasses_2_bits_uop_exc_cause; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_bypassable; // @[core.scala:175:27]
wire [4:0] pred_bypasses_2_bits_uop_mem_cmd; // @[core.scala:175:27]
wire [1:0] pred_bypasses_2_bits_uop_mem_size; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_mem_signed; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_is_fence; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_is_fencei; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_is_amo; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_uses_ldq; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_uses_stq; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_is_sys_pc2epc; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_is_unique; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_flush_on_commit; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_ldst_is_rs1; // @[core.scala:175:27]
wire [5:0] pred_bypasses_2_bits_uop_ldst; // @[core.scala:175:27]
wire [5:0] pred_bypasses_2_bits_uop_lrs1; // @[core.scala:175:27]
wire [5:0] pred_bypasses_2_bits_uop_lrs2; // @[core.scala:175:27]
wire [5:0] pred_bypasses_2_bits_uop_lrs3; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_ldst_val; // @[core.scala:175:27]
wire [1:0] pred_bypasses_2_bits_uop_dst_rtype; // @[core.scala:175:27]
wire [1:0] pred_bypasses_2_bits_uop_lrs1_rtype; // @[core.scala:175:27]
wire [1:0] pred_bypasses_2_bits_uop_lrs2_rtype; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_frs3_en; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_fp_val; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_fp_single; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_xcpt_pf_if; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_xcpt_ae_if; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_xcpt_ma_if; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_bp_debug_if; // @[core.scala:175:27]
wire pred_bypasses_2_bits_uop_bp_xcpt_if; // @[core.scala:175:27]
wire [1:0] pred_bypasses_2_bits_uop_debug_fsrc; // @[core.scala:175:27]
wire [1:0] pred_bypasses_2_bits_uop_debug_tsrc; // @[core.scala:175:27]
wire pred_bypasses_2_bits_data; // @[core.scala:175:27]
wire pred_bypasses_2_valid; // @[core.scala:175:27]
reg [6:0] brinfos_0_uop_uopc; // @[core.scala:182:20]
wire [6:0] b2_uop_out_uopc = brinfos_0_uop_uopc; // @[util.scala:96:23]
reg [31:0] brinfos_0_uop_inst; // @[core.scala:182:20]
wire [31:0] b2_uop_out_inst = brinfos_0_uop_inst; // @[util.scala:96:23]
reg [31:0] brinfos_0_uop_debug_inst; // @[core.scala:182:20]
wire [31:0] b2_uop_out_debug_inst = brinfos_0_uop_debug_inst; // @[util.scala:96:23]
reg brinfos_0_uop_is_rvc; // @[core.scala:182:20]
wire b2_uop_out_is_rvc = brinfos_0_uop_is_rvc; // @[util.scala:96:23]
reg [39:0] brinfos_0_uop_debug_pc; // @[core.scala:182:20]
wire [39:0] b2_uop_out_debug_pc = brinfos_0_uop_debug_pc; // @[util.scala:96:23]
reg [2:0] brinfos_0_uop_iq_type; // @[core.scala:182:20]
wire [2:0] b2_uop_out_iq_type = brinfos_0_uop_iq_type; // @[util.scala:96:23]
reg [9:0] brinfos_0_uop_fu_code; // @[core.scala:182:20]
wire [9:0] b2_uop_out_fu_code = brinfos_0_uop_fu_code; // @[util.scala:96:23]
reg [3:0] brinfos_0_uop_ctrl_br_type; // @[core.scala:182:20]
wire [3:0] b2_uop_out_ctrl_br_type = brinfos_0_uop_ctrl_br_type; // @[util.scala:96:23]
reg [1:0] brinfos_0_uop_ctrl_op1_sel; // @[core.scala:182:20]
wire [1:0] b2_uop_out_ctrl_op1_sel = brinfos_0_uop_ctrl_op1_sel; // @[util.scala:96:23]
reg [2:0] brinfos_0_uop_ctrl_op2_sel; // @[core.scala:182:20]
wire [2:0] b2_uop_out_ctrl_op2_sel = brinfos_0_uop_ctrl_op2_sel; // @[util.scala:96:23]
reg [2:0] brinfos_0_uop_ctrl_imm_sel; // @[core.scala:182:20]
wire [2:0] b2_uop_out_ctrl_imm_sel = brinfos_0_uop_ctrl_imm_sel; // @[util.scala:96:23]
reg [4:0] brinfos_0_uop_ctrl_op_fcn; // @[core.scala:182:20]
wire [4:0] b2_uop_out_ctrl_op_fcn = brinfos_0_uop_ctrl_op_fcn; // @[util.scala:96:23]
reg brinfos_0_uop_ctrl_fcn_dw; // @[core.scala:182:20]
wire b2_uop_out_ctrl_fcn_dw = brinfos_0_uop_ctrl_fcn_dw; // @[util.scala:96:23]
reg [2:0] brinfos_0_uop_ctrl_csr_cmd; // @[core.scala:182:20]
wire [2:0] b2_uop_out_ctrl_csr_cmd = brinfos_0_uop_ctrl_csr_cmd; // @[util.scala:96:23]
reg brinfos_0_uop_ctrl_is_load; // @[core.scala:182:20]
wire b2_uop_out_ctrl_is_load = brinfos_0_uop_ctrl_is_load; // @[util.scala:96:23]
reg brinfos_0_uop_ctrl_is_sta; // @[core.scala:182:20]
wire b2_uop_out_ctrl_is_sta = brinfos_0_uop_ctrl_is_sta; // @[util.scala:96:23]
reg brinfos_0_uop_ctrl_is_std; // @[core.scala:182:20]
wire b2_uop_out_ctrl_is_std = brinfos_0_uop_ctrl_is_std; // @[util.scala:96:23]
reg [1:0] brinfos_0_uop_iw_state; // @[core.scala:182:20]
wire [1:0] b2_uop_out_iw_state = brinfos_0_uop_iw_state; // @[util.scala:96:23]
reg brinfos_0_uop_iw_p1_poisoned; // @[core.scala:182:20]
wire b2_uop_out_iw_p1_poisoned = brinfos_0_uop_iw_p1_poisoned; // @[util.scala:96:23]
reg brinfos_0_uop_iw_p2_poisoned; // @[core.scala:182:20]
wire b2_uop_out_iw_p2_poisoned = brinfos_0_uop_iw_p2_poisoned; // @[util.scala:96:23]
reg brinfos_0_uop_is_br; // @[core.scala:182:20]
wire b2_uop_out_is_br = brinfos_0_uop_is_br; // @[util.scala:96:23]
reg brinfos_0_uop_is_jalr; // @[core.scala:182:20]
wire b2_uop_out_is_jalr = brinfos_0_uop_is_jalr; // @[util.scala:96:23]
reg brinfos_0_uop_is_jal; // @[core.scala:182:20]
wire b2_uop_out_is_jal = brinfos_0_uop_is_jal; // @[util.scala:96:23]
reg brinfos_0_uop_is_sfb; // @[core.scala:182:20]
wire b2_uop_out_is_sfb = brinfos_0_uop_is_sfb; // @[util.scala:96:23]
reg [7:0] brinfos_0_uop_br_mask; // @[core.scala:182:20]
reg [2:0] brinfos_0_uop_br_tag; // @[core.scala:182:20]
wire [2:0] b2_uop_out_br_tag = brinfos_0_uop_br_tag; // @[util.scala:96:23]
reg [3:0] brinfos_0_uop_ftq_idx; // @[core.scala:182:20]
assign io_ifu_get_pc_1_ftq_idx_0 = brinfos_0_uop_ftq_idx; // @[core.scala:51:7, :182:20]
wire [3:0] b2_uop_out_ftq_idx = brinfos_0_uop_ftq_idx; // @[util.scala:96:23]
reg brinfos_0_uop_edge_inst; // @[core.scala:182:20]
wire b2_uop_out_edge_inst = brinfos_0_uop_edge_inst; // @[util.scala:96:23]
reg [5:0] brinfos_0_uop_pc_lob; // @[core.scala:182:20]
wire [5:0] b2_uop_out_pc_lob = brinfos_0_uop_pc_lob; // @[util.scala:96:23]
reg brinfos_0_uop_taken; // @[core.scala:182:20]
wire b2_uop_out_taken = brinfos_0_uop_taken; // @[util.scala:96:23]
reg [19:0] brinfos_0_uop_imm_packed; // @[core.scala:182:20]
wire [19:0] b2_uop_out_imm_packed = brinfos_0_uop_imm_packed; // @[util.scala:96:23]
reg [11:0] brinfos_0_uop_csr_addr; // @[core.scala:182:20]
wire [11:0] b2_uop_out_csr_addr = brinfos_0_uop_csr_addr; // @[util.scala:96:23]
reg [4:0] brinfos_0_uop_rob_idx; // @[core.scala:182:20]
wire [4:0] b2_uop_out_rob_idx = brinfos_0_uop_rob_idx; // @[util.scala:96:23]
reg [2:0] brinfos_0_uop_ldq_idx; // @[core.scala:182:20]
wire [2:0] b2_uop_out_ldq_idx = brinfos_0_uop_ldq_idx; // @[util.scala:96:23]
reg [2:0] brinfos_0_uop_stq_idx; // @[core.scala:182:20]
wire [2:0] b2_uop_out_stq_idx = brinfos_0_uop_stq_idx; // @[util.scala:96:23]
reg [1:0] brinfos_0_uop_rxq_idx; // @[core.scala:182:20]
wire [1:0] b2_uop_out_rxq_idx = brinfos_0_uop_rxq_idx; // @[util.scala:96:23]
reg [5:0] brinfos_0_uop_pdst; // @[core.scala:182:20]
wire [5:0] b2_uop_out_pdst = brinfos_0_uop_pdst; // @[util.scala:96:23]
reg [5:0] brinfos_0_uop_prs1; // @[core.scala:182:20]
wire [5:0] b2_uop_out_prs1 = brinfos_0_uop_prs1; // @[util.scala:96:23]
reg [5:0] brinfos_0_uop_prs2; // @[core.scala:182:20]
wire [5:0] b2_uop_out_prs2 = brinfos_0_uop_prs2; // @[util.scala:96:23]
reg [5:0] brinfos_0_uop_prs3; // @[core.scala:182:20]
wire [5:0] b2_uop_out_prs3 = brinfos_0_uop_prs3; // @[util.scala:96:23]
reg [3:0] brinfos_0_uop_ppred; // @[core.scala:182:20]
wire [3:0] b2_uop_out_ppred = brinfos_0_uop_ppred; // @[util.scala:96:23]
reg brinfos_0_uop_prs1_busy; // @[core.scala:182:20]
wire b2_uop_out_prs1_busy = brinfos_0_uop_prs1_busy; // @[util.scala:96:23]
reg brinfos_0_uop_prs2_busy; // @[core.scala:182:20]
wire b2_uop_out_prs2_busy = brinfos_0_uop_prs2_busy; // @[util.scala:96:23]
reg brinfos_0_uop_prs3_busy; // @[core.scala:182:20]
wire b2_uop_out_prs3_busy = brinfos_0_uop_prs3_busy; // @[util.scala:96:23]
reg brinfos_0_uop_ppred_busy; // @[core.scala:182:20]
wire b2_uop_out_ppred_busy = brinfos_0_uop_ppred_busy; // @[util.scala:96:23]
reg [5:0] brinfos_0_uop_stale_pdst; // @[core.scala:182:20]
wire [5:0] b2_uop_out_stale_pdst = brinfos_0_uop_stale_pdst; // @[util.scala:96:23]
reg brinfos_0_uop_exception; // @[core.scala:182:20]
wire b2_uop_out_exception = brinfos_0_uop_exception; // @[util.scala:96:23]
reg [63:0] brinfos_0_uop_exc_cause; // @[core.scala:182:20]
wire [63:0] b2_uop_out_exc_cause = brinfos_0_uop_exc_cause; // @[util.scala:96:23]
reg brinfos_0_uop_bypassable; // @[core.scala:182:20]
wire b2_uop_out_bypassable = brinfos_0_uop_bypassable; // @[util.scala:96:23]
reg [4:0] brinfos_0_uop_mem_cmd; // @[core.scala:182:20]
wire [4:0] b2_uop_out_mem_cmd = brinfos_0_uop_mem_cmd; // @[util.scala:96:23]
reg [1:0] brinfos_0_uop_mem_size; // @[core.scala:182:20]
wire [1:0] b2_uop_out_mem_size = brinfos_0_uop_mem_size; // @[util.scala:96:23]
reg brinfos_0_uop_mem_signed; // @[core.scala:182:20]
wire b2_uop_out_mem_signed = brinfos_0_uop_mem_signed; // @[util.scala:96:23]
reg brinfos_0_uop_is_fence; // @[core.scala:182:20]
wire b2_uop_out_is_fence = brinfos_0_uop_is_fence; // @[util.scala:96:23]
reg brinfos_0_uop_is_fencei; // @[core.scala:182:20]
wire b2_uop_out_is_fencei = brinfos_0_uop_is_fencei; // @[util.scala:96:23]
reg brinfos_0_uop_is_amo; // @[core.scala:182:20]
wire b2_uop_out_is_amo = brinfos_0_uop_is_amo; // @[util.scala:96:23]
reg brinfos_0_uop_uses_ldq; // @[core.scala:182:20]
wire b2_uop_out_uses_ldq = brinfos_0_uop_uses_ldq; // @[util.scala:96:23]
reg brinfos_0_uop_uses_stq; // @[core.scala:182:20]
wire b2_uop_out_uses_stq = brinfos_0_uop_uses_stq; // @[util.scala:96:23]
reg brinfos_0_uop_is_sys_pc2epc; // @[core.scala:182:20]
wire b2_uop_out_is_sys_pc2epc = brinfos_0_uop_is_sys_pc2epc; // @[util.scala:96:23]
reg brinfos_0_uop_is_unique; // @[core.scala:182:20]
wire b2_uop_out_is_unique = brinfos_0_uop_is_unique; // @[util.scala:96:23]
reg brinfos_0_uop_flush_on_commit; // @[core.scala:182:20]
wire b2_uop_out_flush_on_commit = brinfos_0_uop_flush_on_commit; // @[util.scala:96:23]
reg brinfos_0_uop_ldst_is_rs1; // @[core.scala:182:20]
wire b2_uop_out_ldst_is_rs1 = brinfos_0_uop_ldst_is_rs1; // @[util.scala:96:23]
reg [5:0] brinfos_0_uop_ldst; // @[core.scala:182:20]
wire [5:0] b2_uop_out_ldst = brinfos_0_uop_ldst; // @[util.scala:96:23]
reg [5:0] brinfos_0_uop_lrs1; // @[core.scala:182:20]
wire [5:0] b2_uop_out_lrs1 = brinfos_0_uop_lrs1; // @[util.scala:96:23]
reg [5:0] brinfos_0_uop_lrs2; // @[core.scala:182:20]
wire [5:0] b2_uop_out_lrs2 = brinfos_0_uop_lrs2; // @[util.scala:96:23]
reg [5:0] brinfos_0_uop_lrs3; // @[core.scala:182:20]
wire [5:0] b2_uop_out_lrs3 = brinfos_0_uop_lrs3; // @[util.scala:96:23]
reg brinfos_0_uop_ldst_val; // @[core.scala:182:20]
wire b2_uop_out_ldst_val = brinfos_0_uop_ldst_val; // @[util.scala:96:23]
reg [1:0] brinfos_0_uop_dst_rtype; // @[core.scala:182:20]
wire [1:0] b2_uop_out_dst_rtype = brinfos_0_uop_dst_rtype; // @[util.scala:96:23]
reg [1:0] brinfos_0_uop_lrs1_rtype; // @[core.scala:182:20]
wire [1:0] b2_uop_out_lrs1_rtype = brinfos_0_uop_lrs1_rtype; // @[util.scala:96:23]
reg [1:0] brinfos_0_uop_lrs2_rtype; // @[core.scala:182:20]
wire [1:0] b2_uop_out_lrs2_rtype = brinfos_0_uop_lrs2_rtype; // @[util.scala:96:23]
reg brinfos_0_uop_frs3_en; // @[core.scala:182:20]
wire b2_uop_out_frs3_en = brinfos_0_uop_frs3_en; // @[util.scala:96:23]
reg brinfos_0_uop_fp_val; // @[core.scala:182:20]
wire b2_uop_out_fp_val = brinfos_0_uop_fp_val; // @[util.scala:96:23]
reg brinfos_0_uop_fp_single; // @[core.scala:182:20]
wire b2_uop_out_fp_single = brinfos_0_uop_fp_single; // @[util.scala:96:23]
reg brinfos_0_uop_xcpt_pf_if; // @[core.scala:182:20]
wire b2_uop_out_xcpt_pf_if = brinfos_0_uop_xcpt_pf_if; // @[util.scala:96:23]
reg brinfos_0_uop_xcpt_ae_if; // @[core.scala:182:20]
wire b2_uop_out_xcpt_ae_if = brinfos_0_uop_xcpt_ae_if; // @[util.scala:96:23]
reg brinfos_0_uop_xcpt_ma_if; // @[core.scala:182:20]
wire b2_uop_out_xcpt_ma_if = brinfos_0_uop_xcpt_ma_if; // @[util.scala:96:23]
reg brinfos_0_uop_bp_debug_if; // @[core.scala:182:20]
wire b2_uop_out_bp_debug_if = brinfos_0_uop_bp_debug_if; // @[util.scala:96:23]
reg brinfos_0_uop_bp_xcpt_if; // @[core.scala:182:20]
wire b2_uop_out_bp_xcpt_if = brinfos_0_uop_bp_xcpt_if; // @[util.scala:96:23]
reg [1:0] brinfos_0_uop_debug_fsrc; // @[core.scala:182:20]
wire [1:0] b2_uop_out_debug_fsrc = brinfos_0_uop_debug_fsrc; // @[util.scala:96:23]
reg [1:0] brinfos_0_uop_debug_tsrc; // @[core.scala:182:20]
wire [1:0] b2_uop_out_debug_tsrc = brinfos_0_uop_debug_tsrc; // @[util.scala:96:23]
reg brinfos_0_valid; // @[core.scala:182:20]
reg brinfos_0_mispredict; // @[core.scala:182:20]
reg brinfos_0_taken; // @[core.scala:182:20]
reg [2:0] brinfos_0_cfi_type; // @[core.scala:182:20]
reg [1:0] brinfos_0_pc_sel; // @[core.scala:182:20]
reg [39:0] brinfos_0_jalr_target; // @[core.scala:182:20]
reg [20:0] brinfos_0_target_offset; // @[core.scala:182:20]
wire [7:0] b1_resolve_mask; // @[core.scala:189:19]
assign io_ifu_brupdate_b1_resolve_mask_0 = brupdate_b1_resolve_mask; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b1_resolve_mask_0 = brupdate_b1_resolve_mask; // @[core.scala:51:7, :188:23]
wire [7:0] b1_mispredict_mask; // @[core.scala:189:19]
assign io_ifu_brupdate_b1_mispredict_mask_0 = brupdate_b1_mispredict_mask; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b1_mispredict_mask_0 = brupdate_b1_mispredict_mask; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_uopc_0 = brupdate_b2_uop_uopc; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_uopc_0 = brupdate_b2_uop_uopc; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_inst_0 = brupdate_b2_uop_inst; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_inst_0 = brupdate_b2_uop_inst; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_debug_inst_0 = brupdate_b2_uop_debug_inst; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_debug_inst_0 = brupdate_b2_uop_debug_inst; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_is_rvc_0 = brupdate_b2_uop_is_rvc; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_is_rvc_0 = brupdate_b2_uop_is_rvc; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_debug_pc_0 = brupdate_b2_uop_debug_pc; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_debug_pc_0 = brupdate_b2_uop_debug_pc; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_iq_type_0 = brupdate_b2_uop_iq_type; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_iq_type_0 = brupdate_b2_uop_iq_type; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_fu_code_0 = brupdate_b2_uop_fu_code; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_fu_code_0 = brupdate_b2_uop_fu_code; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ctrl_br_type_0 = brupdate_b2_uop_ctrl_br_type; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ctrl_br_type_0 = brupdate_b2_uop_ctrl_br_type; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ctrl_op1_sel_0 = brupdate_b2_uop_ctrl_op1_sel; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ctrl_op1_sel_0 = brupdate_b2_uop_ctrl_op1_sel; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ctrl_op2_sel_0 = brupdate_b2_uop_ctrl_op2_sel; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ctrl_op2_sel_0 = brupdate_b2_uop_ctrl_op2_sel; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ctrl_imm_sel_0 = brupdate_b2_uop_ctrl_imm_sel; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ctrl_imm_sel_0 = brupdate_b2_uop_ctrl_imm_sel; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ctrl_op_fcn_0 = brupdate_b2_uop_ctrl_op_fcn; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ctrl_op_fcn_0 = brupdate_b2_uop_ctrl_op_fcn; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ctrl_fcn_dw_0 = brupdate_b2_uop_ctrl_fcn_dw; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ctrl_fcn_dw_0 = brupdate_b2_uop_ctrl_fcn_dw; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ctrl_csr_cmd_0 = brupdate_b2_uop_ctrl_csr_cmd; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ctrl_csr_cmd_0 = brupdate_b2_uop_ctrl_csr_cmd; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ctrl_is_load_0 = brupdate_b2_uop_ctrl_is_load; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ctrl_is_load_0 = brupdate_b2_uop_ctrl_is_load; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ctrl_is_sta_0 = brupdate_b2_uop_ctrl_is_sta; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ctrl_is_sta_0 = brupdate_b2_uop_ctrl_is_sta; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ctrl_is_std_0 = brupdate_b2_uop_ctrl_is_std; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ctrl_is_std_0 = brupdate_b2_uop_ctrl_is_std; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_iw_state_0 = brupdate_b2_uop_iw_state; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_iw_state_0 = brupdate_b2_uop_iw_state; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_iw_p1_poisoned_0 = brupdate_b2_uop_iw_p1_poisoned; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_iw_p1_poisoned_0 = brupdate_b2_uop_iw_p1_poisoned; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_iw_p2_poisoned_0 = brupdate_b2_uop_iw_p2_poisoned; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_iw_p2_poisoned_0 = brupdate_b2_uop_iw_p2_poisoned; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_is_br_0 = brupdate_b2_uop_is_br; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_is_br_0 = brupdate_b2_uop_is_br; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_is_jalr_0 = brupdate_b2_uop_is_jalr; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_is_jalr_0 = brupdate_b2_uop_is_jalr; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_is_jal_0 = brupdate_b2_uop_is_jal; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_is_jal_0 = brupdate_b2_uop_is_jal; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_is_sfb_0 = brupdate_b2_uop_is_sfb; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_is_sfb_0 = brupdate_b2_uop_is_sfb; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_br_mask_0 = brupdate_b2_uop_br_mask; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_br_mask_0 = brupdate_b2_uop_br_mask; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_br_tag_0 = brupdate_b2_uop_br_tag; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_br_tag_0 = brupdate_b2_uop_br_tag; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ftq_idx_0 = brupdate_b2_uop_ftq_idx; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ftq_idx_0 = brupdate_b2_uop_ftq_idx; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_edge_inst_0 = brupdate_b2_uop_edge_inst; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_edge_inst_0 = brupdate_b2_uop_edge_inst; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_pc_lob_0 = brupdate_b2_uop_pc_lob; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_pc_lob_0 = brupdate_b2_uop_pc_lob; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_taken_0 = brupdate_b2_uop_taken; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_taken_0 = brupdate_b2_uop_taken; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_imm_packed_0 = brupdate_b2_uop_imm_packed; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_imm_packed_0 = brupdate_b2_uop_imm_packed; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_csr_addr_0 = brupdate_b2_uop_csr_addr; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_csr_addr_0 = brupdate_b2_uop_csr_addr; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_rob_idx_0 = brupdate_b2_uop_rob_idx; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_rob_idx_0 = brupdate_b2_uop_rob_idx; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ldq_idx_0 = brupdate_b2_uop_ldq_idx; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ldq_idx_0 = brupdate_b2_uop_ldq_idx; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_stq_idx_0 = brupdate_b2_uop_stq_idx; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_stq_idx_0 = brupdate_b2_uop_stq_idx; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_rxq_idx_0 = brupdate_b2_uop_rxq_idx; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_rxq_idx_0 = brupdate_b2_uop_rxq_idx; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_pdst_0 = brupdate_b2_uop_pdst; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_pdst_0 = brupdate_b2_uop_pdst; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_prs1_0 = brupdate_b2_uop_prs1; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_prs1_0 = brupdate_b2_uop_prs1; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_prs2_0 = brupdate_b2_uop_prs2; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_prs2_0 = brupdate_b2_uop_prs2; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_prs3_0 = brupdate_b2_uop_prs3; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_prs3_0 = brupdate_b2_uop_prs3; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ppred_0 = brupdate_b2_uop_ppred; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ppred_0 = brupdate_b2_uop_ppred; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_prs1_busy_0 = brupdate_b2_uop_prs1_busy; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_prs1_busy_0 = brupdate_b2_uop_prs1_busy; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_prs2_busy_0 = brupdate_b2_uop_prs2_busy; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_prs2_busy_0 = brupdate_b2_uop_prs2_busy; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_prs3_busy_0 = brupdate_b2_uop_prs3_busy; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_prs3_busy_0 = brupdate_b2_uop_prs3_busy; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ppred_busy_0 = brupdate_b2_uop_ppred_busy; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ppred_busy_0 = brupdate_b2_uop_ppred_busy; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_stale_pdst_0 = brupdate_b2_uop_stale_pdst; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_stale_pdst_0 = brupdate_b2_uop_stale_pdst; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_exception_0 = brupdate_b2_uop_exception; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_exception_0 = brupdate_b2_uop_exception; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_exc_cause_0 = brupdate_b2_uop_exc_cause; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_exc_cause_0 = brupdate_b2_uop_exc_cause; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_bypassable_0 = brupdate_b2_uop_bypassable; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_bypassable_0 = brupdate_b2_uop_bypassable; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_mem_cmd_0 = brupdate_b2_uop_mem_cmd; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_mem_cmd_0 = brupdate_b2_uop_mem_cmd; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_mem_size_0 = brupdate_b2_uop_mem_size; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_mem_size_0 = brupdate_b2_uop_mem_size; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_mem_signed_0 = brupdate_b2_uop_mem_signed; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_mem_signed_0 = brupdate_b2_uop_mem_signed; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_is_fence_0 = brupdate_b2_uop_is_fence; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_is_fence_0 = brupdate_b2_uop_is_fence; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_is_fencei_0 = brupdate_b2_uop_is_fencei; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_is_fencei_0 = brupdate_b2_uop_is_fencei; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_is_amo_0 = brupdate_b2_uop_is_amo; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_is_amo_0 = brupdate_b2_uop_is_amo; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_uses_ldq_0 = brupdate_b2_uop_uses_ldq; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_uses_ldq_0 = brupdate_b2_uop_uses_ldq; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_uses_stq_0 = brupdate_b2_uop_uses_stq; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_uses_stq_0 = brupdate_b2_uop_uses_stq; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_is_sys_pc2epc_0 = brupdate_b2_uop_is_sys_pc2epc; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_is_sys_pc2epc_0 = brupdate_b2_uop_is_sys_pc2epc; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_is_unique_0 = brupdate_b2_uop_is_unique; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_is_unique_0 = brupdate_b2_uop_is_unique; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_flush_on_commit_0 = brupdate_b2_uop_flush_on_commit; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_flush_on_commit_0 = brupdate_b2_uop_flush_on_commit; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ldst_is_rs1_0 = brupdate_b2_uop_ldst_is_rs1; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ldst_is_rs1_0 = brupdate_b2_uop_ldst_is_rs1; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ldst_0 = brupdate_b2_uop_ldst; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ldst_0 = brupdate_b2_uop_ldst; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_lrs1_0 = brupdate_b2_uop_lrs1; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_lrs1_0 = brupdate_b2_uop_lrs1; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_lrs2_0 = brupdate_b2_uop_lrs2; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_lrs2_0 = brupdate_b2_uop_lrs2; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_lrs3_0 = brupdate_b2_uop_lrs3; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_lrs3_0 = brupdate_b2_uop_lrs3; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ldst_val_0 = brupdate_b2_uop_ldst_val; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ldst_val_0 = brupdate_b2_uop_ldst_val; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_dst_rtype_0 = brupdate_b2_uop_dst_rtype; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_dst_rtype_0 = brupdate_b2_uop_dst_rtype; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_lrs1_rtype_0 = brupdate_b2_uop_lrs1_rtype; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_lrs1_rtype_0 = brupdate_b2_uop_lrs1_rtype; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_lrs2_rtype_0 = brupdate_b2_uop_lrs2_rtype; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_lrs2_rtype_0 = brupdate_b2_uop_lrs2_rtype; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_frs3_en_0 = brupdate_b2_uop_frs3_en; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_frs3_en_0 = brupdate_b2_uop_frs3_en; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_fp_val_0 = brupdate_b2_uop_fp_val; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_fp_val_0 = brupdate_b2_uop_fp_val; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_fp_single_0 = brupdate_b2_uop_fp_single; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_fp_single_0 = brupdate_b2_uop_fp_single; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_xcpt_pf_if_0 = brupdate_b2_uop_xcpt_pf_if; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_xcpt_pf_if_0 = brupdate_b2_uop_xcpt_pf_if; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_xcpt_ae_if_0 = brupdate_b2_uop_xcpt_ae_if; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_xcpt_ae_if_0 = brupdate_b2_uop_xcpt_ae_if; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_xcpt_ma_if_0 = brupdate_b2_uop_xcpt_ma_if; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_xcpt_ma_if_0 = brupdate_b2_uop_xcpt_ma_if; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_bp_debug_if_0 = brupdate_b2_uop_bp_debug_if; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_bp_debug_if_0 = brupdate_b2_uop_bp_debug_if; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_bp_xcpt_if_0 = brupdate_b2_uop_bp_xcpt_if; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_bp_xcpt_if_0 = brupdate_b2_uop_bp_xcpt_if; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_debug_fsrc_0 = brupdate_b2_uop_debug_fsrc; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_debug_fsrc_0 = brupdate_b2_uop_debug_fsrc; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_debug_tsrc_0 = brupdate_b2_uop_debug_tsrc; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_debug_tsrc_0 = brupdate_b2_uop_debug_tsrc; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_valid_0 = brupdate_b2_valid; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_valid_0 = brupdate_b2_valid; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_mispredict_0 = brupdate_b2_mispredict; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_mispredict_0 = brupdate_b2_mispredict; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_taken_0 = brupdate_b2_taken; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_taken_0 = brupdate_b2_taken; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_cfi_type_0 = brupdate_b2_cfi_type; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_cfi_type_0 = brupdate_b2_cfi_type; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_pc_sel_0 = brupdate_b2_pc_sel; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_pc_sel_0 = brupdate_b2_pc_sel; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_jalr_target_0 = brupdate_b2_jalr_target; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_jalr_target_0 = brupdate_b2_jalr_target; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_target_offset_0 = brupdate_b2_target_offset; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_target_offset_0 = brupdate_b2_target_offset; // @[core.scala:51:7, :188:23]
wire [7:0] _b1_resolve_mask_T; // @[core.scala:199:47]
assign brupdate_b1_resolve_mask = b1_resolve_mask; // @[core.scala:188:23, :189:19]
wire [7:0] _b1_mispredict_mask_T_1; // @[core.scala:200:68]
assign brupdate_b1_mispredict_mask = b1_mispredict_mask; // @[core.scala:188:23, :189:19]
reg [6:0] b2_uop_uopc; // @[core.scala:190:18]
assign brupdate_b2_uop_uopc = b2_uop_uopc; // @[core.scala:188:23, :190:18]
reg [31:0] b2_uop_inst; // @[core.scala:190:18]
assign brupdate_b2_uop_inst = b2_uop_inst; // @[core.scala:188:23, :190:18]
reg [31:0] b2_uop_debug_inst; // @[core.scala:190:18]
assign brupdate_b2_uop_debug_inst = b2_uop_debug_inst; // @[core.scala:188:23, :190:18]
reg b2_uop_is_rvc; // @[core.scala:190:18]
assign brupdate_b2_uop_is_rvc = b2_uop_is_rvc; // @[core.scala:188:23, :190:18]
reg [39:0] b2_uop_debug_pc; // @[core.scala:190:18]
assign brupdate_b2_uop_debug_pc = b2_uop_debug_pc; // @[core.scala:188:23, :190:18]
reg [2:0] b2_uop_iq_type; // @[core.scala:190:18]
assign brupdate_b2_uop_iq_type = b2_uop_iq_type; // @[core.scala:188:23, :190:18]
reg [9:0] b2_uop_fu_code; // @[core.scala:190:18]
assign brupdate_b2_uop_fu_code = b2_uop_fu_code; // @[core.scala:188:23, :190:18]
reg [3:0] b2_uop_ctrl_br_type; // @[core.scala:190:18]
assign brupdate_b2_uop_ctrl_br_type = b2_uop_ctrl_br_type; // @[core.scala:188:23, :190:18]
reg [1:0] b2_uop_ctrl_op1_sel; // @[core.scala:190:18]
assign brupdate_b2_uop_ctrl_op1_sel = b2_uop_ctrl_op1_sel; // @[core.scala:188:23, :190:18]
reg [2:0] b2_uop_ctrl_op2_sel; // @[core.scala:190:18]
assign brupdate_b2_uop_ctrl_op2_sel = b2_uop_ctrl_op2_sel; // @[core.scala:188:23, :190:18]
reg [2:0] b2_uop_ctrl_imm_sel; // @[core.scala:190:18]
assign brupdate_b2_uop_ctrl_imm_sel = b2_uop_ctrl_imm_sel; // @[core.scala:188:23, :190:18]
reg [4:0] b2_uop_ctrl_op_fcn; // @[core.scala:190:18]
assign brupdate_b2_uop_ctrl_op_fcn = b2_uop_ctrl_op_fcn; // @[core.scala:188:23, :190:18]
reg b2_uop_ctrl_fcn_dw; // @[core.scala:190:18]
assign brupdate_b2_uop_ctrl_fcn_dw = b2_uop_ctrl_fcn_dw; // @[core.scala:188:23, :190:18]
reg [2:0] b2_uop_ctrl_csr_cmd; // @[core.scala:190:18]
assign brupdate_b2_uop_ctrl_csr_cmd = b2_uop_ctrl_csr_cmd; // @[core.scala:188:23, :190:18]
reg b2_uop_ctrl_is_load; // @[core.scala:190:18]
assign brupdate_b2_uop_ctrl_is_load = b2_uop_ctrl_is_load; // @[core.scala:188:23, :190:18]
reg b2_uop_ctrl_is_sta; // @[core.scala:190:18]
assign brupdate_b2_uop_ctrl_is_sta = b2_uop_ctrl_is_sta; // @[core.scala:188:23, :190:18]
reg b2_uop_ctrl_is_std; // @[core.scala:190:18]
assign brupdate_b2_uop_ctrl_is_std = b2_uop_ctrl_is_std; // @[core.scala:188:23, :190:18]
reg [1:0] b2_uop_iw_state; // @[core.scala:190:18]
assign brupdate_b2_uop_iw_state = b2_uop_iw_state; // @[core.scala:188:23, :190:18]
reg b2_uop_iw_p1_poisoned; // @[core.scala:190:18]
assign brupdate_b2_uop_iw_p1_poisoned = b2_uop_iw_p1_poisoned; // @[core.scala:188:23, :190:18]
reg b2_uop_iw_p2_poisoned; // @[core.scala:190:18]
assign brupdate_b2_uop_iw_p2_poisoned = b2_uop_iw_p2_poisoned; // @[core.scala:188:23, :190:18]
reg b2_uop_is_br; // @[core.scala:190:18]
assign brupdate_b2_uop_is_br = b2_uop_is_br; // @[core.scala:188:23, :190:18]
reg b2_uop_is_jalr; // @[core.scala:190:18]
assign brupdate_b2_uop_is_jalr = b2_uop_is_jalr; // @[core.scala:188:23, :190:18]
reg b2_uop_is_jal; // @[core.scala:190:18]
assign brupdate_b2_uop_is_jal = b2_uop_is_jal; // @[core.scala:188:23, :190:18]
reg b2_uop_is_sfb; // @[core.scala:190:18]
assign brupdate_b2_uop_is_sfb = b2_uop_is_sfb; // @[core.scala:188:23, :190:18]
reg [7:0] b2_uop_br_mask; // @[core.scala:190:18]
assign brupdate_b2_uop_br_mask = b2_uop_br_mask; // @[core.scala:188:23, :190:18]
reg [2:0] b2_uop_br_tag; // @[core.scala:190:18]
assign brupdate_b2_uop_br_tag = b2_uop_br_tag; // @[core.scala:188:23, :190:18]
reg [3:0] b2_uop_ftq_idx; // @[core.scala:190:18]
assign brupdate_b2_uop_ftq_idx = b2_uop_ftq_idx; // @[core.scala:188:23, :190:18]
reg b2_uop_edge_inst; // @[core.scala:190:18]
assign brupdate_b2_uop_edge_inst = b2_uop_edge_inst; // @[core.scala:188:23, :190:18]
reg [5:0] b2_uop_pc_lob; // @[core.scala:190:18]
assign brupdate_b2_uop_pc_lob = b2_uop_pc_lob; // @[core.scala:188:23, :190:18]
reg b2_uop_taken; // @[core.scala:190:18]
assign brupdate_b2_uop_taken = b2_uop_taken; // @[core.scala:188:23, :190:18]
reg [19:0] b2_uop_imm_packed; // @[core.scala:190:18]
assign brupdate_b2_uop_imm_packed = b2_uop_imm_packed; // @[core.scala:188:23, :190:18]
reg [11:0] b2_uop_csr_addr; // @[core.scala:190:18]
assign brupdate_b2_uop_csr_addr = b2_uop_csr_addr; // @[core.scala:188:23, :190:18]
reg [4:0] b2_uop_rob_idx; // @[core.scala:190:18]
assign brupdate_b2_uop_rob_idx = b2_uop_rob_idx; // @[core.scala:188:23, :190:18]
reg [2:0] b2_uop_ldq_idx; // @[core.scala:190:18]
assign brupdate_b2_uop_ldq_idx = b2_uop_ldq_idx; // @[core.scala:188:23, :190:18]
reg [2:0] b2_uop_stq_idx; // @[core.scala:190:18]
assign brupdate_b2_uop_stq_idx = b2_uop_stq_idx; // @[core.scala:188:23, :190:18]
reg [1:0] b2_uop_rxq_idx; // @[core.scala:190:18]
assign brupdate_b2_uop_rxq_idx = b2_uop_rxq_idx; // @[core.scala:188:23, :190:18]
reg [5:0] b2_uop_pdst; // @[core.scala:190:18]
assign brupdate_b2_uop_pdst = b2_uop_pdst; // @[core.scala:188:23, :190:18]
reg [5:0] b2_uop_prs1; // @[core.scala:190:18]
assign brupdate_b2_uop_prs1 = b2_uop_prs1; // @[core.scala:188:23, :190:18]
reg [5:0] b2_uop_prs2; // @[core.scala:190:18]
assign brupdate_b2_uop_prs2 = b2_uop_prs2; // @[core.scala:188:23, :190:18]
reg [5:0] b2_uop_prs3; // @[core.scala:190:18]
assign brupdate_b2_uop_prs3 = b2_uop_prs3; // @[core.scala:188:23, :190:18]
reg [3:0] b2_uop_ppred; // @[core.scala:190:18]
assign brupdate_b2_uop_ppred = b2_uop_ppred; // @[core.scala:188:23, :190:18]
reg b2_uop_prs1_busy; // @[core.scala:190:18]
assign brupdate_b2_uop_prs1_busy = b2_uop_prs1_busy; // @[core.scala:188:23, :190:18]
reg b2_uop_prs2_busy; // @[core.scala:190:18]
assign brupdate_b2_uop_prs2_busy = b2_uop_prs2_busy; // @[core.scala:188:23, :190:18]
reg b2_uop_prs3_busy; // @[core.scala:190:18]
assign brupdate_b2_uop_prs3_busy = b2_uop_prs3_busy; // @[core.scala:188:23, :190:18]
reg b2_uop_ppred_busy; // @[core.scala:190:18]
assign brupdate_b2_uop_ppred_busy = b2_uop_ppred_busy; // @[core.scala:188:23, :190:18]
reg [5:0] b2_uop_stale_pdst; // @[core.scala:190:18]
assign brupdate_b2_uop_stale_pdst = b2_uop_stale_pdst; // @[core.scala:188:23, :190:18]
reg b2_uop_exception; // @[core.scala:190:18]
assign brupdate_b2_uop_exception = b2_uop_exception; // @[core.scala:188:23, :190:18]
reg [63:0] b2_uop_exc_cause; // @[core.scala:190:18]
assign brupdate_b2_uop_exc_cause = b2_uop_exc_cause; // @[core.scala:188:23, :190:18]
reg b2_uop_bypassable; // @[core.scala:190:18]
assign brupdate_b2_uop_bypassable = b2_uop_bypassable; // @[core.scala:188:23, :190:18]
reg [4:0] b2_uop_mem_cmd; // @[core.scala:190:18]
assign brupdate_b2_uop_mem_cmd = b2_uop_mem_cmd; // @[core.scala:188:23, :190:18]
reg [1:0] b2_uop_mem_size; // @[core.scala:190:18]
assign brupdate_b2_uop_mem_size = b2_uop_mem_size; // @[core.scala:188:23, :190:18]
reg b2_uop_mem_signed; // @[core.scala:190:18]
assign brupdate_b2_uop_mem_signed = b2_uop_mem_signed; // @[core.scala:188:23, :190:18]
reg b2_uop_is_fence; // @[core.scala:190:18]
assign brupdate_b2_uop_is_fence = b2_uop_is_fence; // @[core.scala:188:23, :190:18]
reg b2_uop_is_fencei; // @[core.scala:190:18]
assign brupdate_b2_uop_is_fencei = b2_uop_is_fencei; // @[core.scala:188:23, :190:18]
reg b2_uop_is_amo; // @[core.scala:190:18]
assign brupdate_b2_uop_is_amo = b2_uop_is_amo; // @[core.scala:188:23, :190:18]
reg b2_uop_uses_ldq; // @[core.scala:190:18]
assign brupdate_b2_uop_uses_ldq = b2_uop_uses_ldq; // @[core.scala:188:23, :190:18]
reg b2_uop_uses_stq; // @[core.scala:190:18]
assign brupdate_b2_uop_uses_stq = b2_uop_uses_stq; // @[core.scala:188:23, :190:18]
reg b2_uop_is_sys_pc2epc; // @[core.scala:190:18]
assign brupdate_b2_uop_is_sys_pc2epc = b2_uop_is_sys_pc2epc; // @[core.scala:188:23, :190:18]
reg b2_uop_is_unique; // @[core.scala:190:18]
assign brupdate_b2_uop_is_unique = b2_uop_is_unique; // @[core.scala:188:23, :190:18]
reg b2_uop_flush_on_commit; // @[core.scala:190:18]
assign brupdate_b2_uop_flush_on_commit = b2_uop_flush_on_commit; // @[core.scala:188:23, :190:18]
reg b2_uop_ldst_is_rs1; // @[core.scala:190:18]
assign brupdate_b2_uop_ldst_is_rs1 = b2_uop_ldst_is_rs1; // @[core.scala:188:23, :190:18]
reg [5:0] b2_uop_ldst; // @[core.scala:190:18]
assign brupdate_b2_uop_ldst = b2_uop_ldst; // @[core.scala:188:23, :190:18]
reg [5:0] b2_uop_lrs1; // @[core.scala:190:18]
assign brupdate_b2_uop_lrs1 = b2_uop_lrs1; // @[core.scala:188:23, :190:18]
reg [5:0] b2_uop_lrs2; // @[core.scala:190:18]
assign brupdate_b2_uop_lrs2 = b2_uop_lrs2; // @[core.scala:188:23, :190:18]
reg [5:0] b2_uop_lrs3; // @[core.scala:190:18]
assign brupdate_b2_uop_lrs3 = b2_uop_lrs3; // @[core.scala:188:23, :190:18]
reg b2_uop_ldst_val; // @[core.scala:190:18]
assign brupdate_b2_uop_ldst_val = b2_uop_ldst_val; // @[core.scala:188:23, :190:18]
reg [1:0] b2_uop_dst_rtype; // @[core.scala:190:18]
assign brupdate_b2_uop_dst_rtype = b2_uop_dst_rtype; // @[core.scala:188:23, :190:18]
reg [1:0] b2_uop_lrs1_rtype; // @[core.scala:190:18]
assign brupdate_b2_uop_lrs1_rtype = b2_uop_lrs1_rtype; // @[core.scala:188:23, :190:18]
reg [1:0] b2_uop_lrs2_rtype; // @[core.scala:190:18]
assign brupdate_b2_uop_lrs2_rtype = b2_uop_lrs2_rtype; // @[core.scala:188:23, :190:18]
reg b2_uop_frs3_en; // @[core.scala:190:18]
assign brupdate_b2_uop_frs3_en = b2_uop_frs3_en; // @[core.scala:188:23, :190:18]
reg b2_uop_fp_val; // @[core.scala:190:18]
assign brupdate_b2_uop_fp_val = b2_uop_fp_val; // @[core.scala:188:23, :190:18]
reg b2_uop_fp_single; // @[core.scala:190:18]
assign brupdate_b2_uop_fp_single = b2_uop_fp_single; // @[core.scala:188:23, :190:18]
reg b2_uop_xcpt_pf_if; // @[core.scala:190:18]
assign brupdate_b2_uop_xcpt_pf_if = b2_uop_xcpt_pf_if; // @[core.scala:188:23, :190:18]
reg b2_uop_xcpt_ae_if; // @[core.scala:190:18]
assign brupdate_b2_uop_xcpt_ae_if = b2_uop_xcpt_ae_if; // @[core.scala:188:23, :190:18]
reg b2_uop_xcpt_ma_if; // @[core.scala:190:18]
assign brupdate_b2_uop_xcpt_ma_if = b2_uop_xcpt_ma_if; // @[core.scala:188:23, :190:18]
reg b2_uop_bp_debug_if; // @[core.scala:190:18]
assign brupdate_b2_uop_bp_debug_if = b2_uop_bp_debug_if; // @[core.scala:188:23, :190:18]
reg b2_uop_bp_xcpt_if; // @[core.scala:190:18]
assign brupdate_b2_uop_bp_xcpt_if = b2_uop_bp_xcpt_if; // @[core.scala:188:23, :190:18]
reg [1:0] b2_uop_debug_fsrc; // @[core.scala:190:18]
assign brupdate_b2_uop_debug_fsrc = b2_uop_debug_fsrc; // @[core.scala:188:23, :190:18]
reg [1:0] b2_uop_debug_tsrc; // @[core.scala:190:18]
assign brupdate_b2_uop_debug_tsrc = b2_uop_debug_tsrc; // @[core.scala:188:23, :190:18]
reg b2_mispredict; // @[core.scala:190:18]
assign brupdate_b2_mispredict = b2_mispredict; // @[core.scala:188:23, :190:18]
wire hits_1_1 = b2_mispredict; // @[Events.scala:13:25]
reg b2_taken; // @[core.scala:190:18]
assign brupdate_b2_taken = b2_taken; // @[core.scala:188:23, :190:18]
reg [2:0] b2_cfi_type; // @[core.scala:190:18]
assign brupdate_b2_cfi_type = b2_cfi_type; // @[core.scala:188:23, :190:18]
reg [1:0] b2_pc_sel; // @[core.scala:190:18]
assign brupdate_b2_pc_sel = b2_pc_sel; // @[core.scala:188:23, :190:18]
reg [39:0] b2_jalr_target; // @[core.scala:190:18]
assign brupdate_b2_jalr_target = b2_jalr_target; // @[core.scala:188:23, :190:18]
reg [20:0] b2_target_offset; // @[core.scala:190:18]
assign brupdate_b2_target_offset = b2_target_offset; // @[core.scala:188:23, :190:18]
wire _brinfos_0_valid_T = ~_rob_io_flush_valid; // @[core.scala:143:32, :197:37]
wire _brinfos_0_valid_T_1 = _alu_exe_unit_io_brinfo_valid & _brinfos_0_valid_T; // @[execution-units.scala:119:32]
wire [7:0] _GEN = {5'h0, brinfos_0_uop_br_tag}; // @[core.scala:182:20, :199:47]
assign _b1_resolve_mask_T = {7'h0, brinfos_0_valid} << _GEN; // @[core.scala:182:20, :199:47]
assign b1_resolve_mask = _b1_resolve_mask_T; // @[core.scala:189:19, :199:47]
wire _T_1 = brinfos_0_valid & brinfos_0_mispredict; // @[core.scala:182:20, :200:51]
wire _b1_mispredict_mask_T; // @[core.scala:200:51]
assign _b1_mispredict_mask_T = _T_1; // @[core.scala:200:51]
wire _use_this_mispredict_T_1; // @[core.scala:207:13]
assign _use_this_mispredict_T_1 = _T_1; // @[core.scala:200:51, :207:13]
assign _b1_mispredict_mask_T_1 = {7'h0, _b1_mispredict_mask_T} << _GEN; // @[core.scala:199:47, :200:{51,68}]
assign b1_mispredict_mask = _b1_mispredict_mask_T_1; // @[core.scala:189:19, :200:68]
wire _GEN_0 = brinfos_0_uop_rob_idx < _rob_io_rob_head_idx; // @[util.scala:363:64]
wire _use_this_mispredict_T_3; // @[util.scala:363:64]
assign _use_this_mispredict_T_3 = _GEN_0; // @[util.scala:363:64]
wire _use_this_mispredict_T_5; // @[util.scala:363:78]
assign _use_this_mispredict_T_5 = _GEN_0; // @[util.scala:363:{64,78}]
wire _use_this_mispredict_T_4 = _use_this_mispredict_T_3; // @[util.scala:363:{58,64}]
wire _use_this_mispredict_T_6 = _use_this_mispredict_T_4 ^ _use_this_mispredict_T_5; // @[util.scala:363:{58,72,78}]
wire _use_this_mispredict_T_7 = _use_this_mispredict_T_1 & _use_this_mispredict_T_6; // @[util.scala:363:72]
wire [7:0] _b2_uop_out_br_mask_T_1; // @[util.scala:85:25]
wire [7:0] b2_uop_out_br_mask; // @[util.scala:96:23]
wire [7:0] _b2_uop_out_br_mask_T = ~brupdate_b1_resolve_mask; // @[util.scala:85:27]
assign _b2_uop_out_br_mask_T_1 = brinfos_0_uop_br_mask & _b2_uop_out_br_mask_T; // @[util.scala:85:{25,27}]
assign b2_uop_out_br_mask = _b2_uop_out_br_mask_T_1; // @[util.scala:85:25, :96:23]
reg [39:0] b2_jalr_target_REG; // @[core.scala:218:28]
wire hits_0; // @[Events.scala:13:25]
wire _csr_io_counters_1_inc_sets_T_3; // @[core.scala:258:65]
wire hits_1_2; // @[Events.scala:13:25]
wire hits_1_3; // @[Events.scala:13:25]
wire custom_csrs_csrs_0_ren; // @[core.scala:276:25]
wire custom_csrs_csrs_0_wen; // @[core.scala:276:25]
wire [63:0] custom_csrs_csrs_0_wdata; // @[core.scala:276:25]
wire [63:0] custom_csrs_csrs_0_value; // @[core.scala:276:25]
wire custom_csrs_csrs_1_ren; // @[core.scala:276:25]
wire custom_csrs_csrs_1_wen; // @[core.scala:276:25]
wire [63:0] custom_csrs_csrs_1_wdata; // @[core.scala:276:25]
wire [63:0] custom_csrs_csrs_1_value; // @[core.scala:276:25]
wire [1:0] csr_io_counters_0_inc_set = _csr_io_counters_0_eventSel[1:0]; // @[Events.scala:40:13]
wire [55:0] csr_io_counters_0_inc_mask = _csr_io_counters_0_eventSel[63:8]; // @[Events.scala:40:44]
wire [1:0] _GEN_1 = {1'h0, hits_0}; // @[Events.scala:13:25, :16:21]
wire [1:0] csr_io_counters_0_inc_sets_lo; // @[Events.scala:16:21]
assign csr_io_counters_0_inc_sets_lo = _GEN_1; // @[Events.scala:16:21]
wire [1:0] csr_io_counters_1_inc_sets_lo; // @[Events.scala:16:21]
assign csr_io_counters_1_inc_sets_lo = _GEN_1; // @[Events.scala:16:21]
wire [3:0] _csr_io_counters_0_inc_sets_T = {2'h0, csr_io_counters_0_inc_sets_lo}; // @[Events.scala:16:21]
wire [55:0] _csr_io_counters_0_inc_sets_T_1 = {52'h0, csr_io_counters_0_inc_mask[3:0] & _csr_io_counters_0_inc_sets_T}; // @[Events.scala:16:21, :40:44]
wire csr_io_counters_0_inc_sets_0 = |_csr_io_counters_0_inc_sets_T_1; // @[core.scala:248:{68,76}]
wire _GEN_2 = b2_cfi_type == 3'h3; // @[core.scala:190:18, :259:63]
wire _csr_io_counters_0_inc_sets_T_2; // @[core.scala:259:63]
assign _csr_io_counters_0_inc_sets_T_2 = _GEN_2; // @[core.scala:259:63]
wire _csr_io_counters_1_inc_sets_T_2; // @[core.scala:259:63]
assign _csr_io_counters_1_inc_sets_T_2 = _GEN_2; // @[core.scala:259:63]
wire _csr_io_counters_0_inc_sets_T_3 = b2_mispredict & _csr_io_counters_0_inc_sets_T_2; // @[core.scala:190:18, :258:65, :259:63]
wire [1:0] _GEN_3 = {hits_1_1, 1'h0}; // @[Events.scala:13:25, :16:21]
wire [1:0] csr_io_counters_0_inc_sets_lo_1; // @[Events.scala:16:21]
assign csr_io_counters_0_inc_sets_lo_1 = _GEN_3; // @[Events.scala:16:21]
wire [1:0] csr_io_counters_1_inc_sets_lo_1; // @[Events.scala:16:21]
assign csr_io_counters_1_inc_sets_lo_1 = _GEN_3; // @[Events.scala:16:21]
wire [1:0] _GEN_4 = {hits_1_4, hits_1_3}; // @[Events.scala:13:25, :16:21]
wire [1:0] csr_io_counters_0_inc_sets_hi_hi; // @[Events.scala:16:21]
assign csr_io_counters_0_inc_sets_hi_hi = _GEN_4; // @[Events.scala:16:21]
wire [1:0] csr_io_counters_1_inc_sets_hi_hi; // @[Events.scala:16:21]
assign csr_io_counters_1_inc_sets_hi_hi = _GEN_4; // @[Events.scala:16:21]
wire [2:0] csr_io_counters_0_inc_sets_hi_1 = {csr_io_counters_0_inc_sets_hi_hi, hits_1_2}; // @[Events.scala:13:25, :16:21]
wire [4:0] _csr_io_counters_0_inc_sets_T_4 = {csr_io_counters_0_inc_sets_hi_1, csr_io_counters_0_inc_sets_lo_1}; // @[Events.scala:16:21]
wire [55:0] _csr_io_counters_0_inc_sets_T_5 = {51'h0, csr_io_counters_0_inc_mask[4:0] & _csr_io_counters_0_inc_sets_T_4}; // @[Events.scala:16:21, :40:44]
wire csr_io_counters_0_inc_sets_1 = |_csr_io_counters_0_inc_sets_T_5; // @[core.scala:254:{68,76}]
wire [1:0] _GEN_5 = {hits_2_2, hits_2_1}; // @[Events.scala:13:25, :16:21]
wire [1:0] csr_io_counters_0_inc_sets_lo_hi; // @[Events.scala:16:21]
assign csr_io_counters_0_inc_sets_lo_hi = _GEN_5; // @[Events.scala:16:21]
wire [1:0] csr_io_counters_1_inc_sets_lo_hi; // @[Events.scala:16:21]
assign csr_io_counters_1_inc_sets_lo_hi = _GEN_5; // @[Events.scala:16:21]
wire [2:0] csr_io_counters_0_inc_sets_lo_2 = {csr_io_counters_0_inc_sets_lo_hi, hits_2_0}; // @[Events.scala:13:25, :16:21]
wire [1:0] _GEN_6 = {hits_2_5, hits_2_4}; // @[Events.scala:13:25, :16:21]
wire [1:0] csr_io_counters_0_inc_sets_hi_hi_1; // @[Events.scala:16:21]
assign csr_io_counters_0_inc_sets_hi_hi_1 = _GEN_6; // @[Events.scala:16:21]
wire [1:0] csr_io_counters_1_inc_sets_hi_hi_1; // @[Events.scala:16:21]
assign csr_io_counters_1_inc_sets_hi_hi_1 = _GEN_6; // @[Events.scala:16:21]
wire [2:0] csr_io_counters_0_inc_sets_hi_2 = {csr_io_counters_0_inc_sets_hi_hi_1, hits_2_3}; // @[Events.scala:13:25, :16:21]
wire [5:0] _csr_io_counters_0_inc_sets_T_6 = {csr_io_counters_0_inc_sets_hi_2, csr_io_counters_0_inc_sets_lo_2}; // @[Events.scala:16:21]
wire [55:0] _csr_io_counters_0_inc_sets_T_7 = {50'h0, csr_io_counters_0_inc_mask[5:0] & _csr_io_counters_0_inc_sets_T_6}; // @[Events.scala:16:21, :40:44]
wire csr_io_counters_0_inc_sets_2 = |_csr_io_counters_0_inc_sets_T_7; // @[core.scala:264:{68,76}]
wire _csr_io_counters_0_inc_T = csr_io_counters_0_inc_set == 2'h1; // @[package.scala:39:86]
wire _csr_io_counters_0_inc_T_1 = _csr_io_counters_0_inc_T ? csr_io_counters_0_inc_sets_1 : csr_io_counters_0_inc_sets_0; // @[package.scala:39:{76,86}]
wire _csr_io_counters_0_inc_T_2 = csr_io_counters_0_inc_set == 2'h2; // @[package.scala:39:86]
wire _csr_io_counters_0_inc_T_3 = _csr_io_counters_0_inc_T_2 ? csr_io_counters_0_inc_sets_2 : _csr_io_counters_0_inc_T_1; // @[package.scala:39:{76,86}]
wire _csr_io_counters_0_inc_T_4 = &csr_io_counters_0_inc_set; // @[package.scala:39:86]
wire _csr_io_counters_0_inc_T_5 = _csr_io_counters_0_inc_T_4 ? csr_io_counters_0_inc_sets_2 : _csr_io_counters_0_inc_T_3; // @[package.scala:39:{76,86}]
reg csr_io_counters_0_inc_REG; // @[core.scala:283:50]
wire [1:0] csr_io_counters_1_inc_set = _csr_io_counters_1_eventSel[1:0]; // @[Events.scala:40:13]
wire [55:0] csr_io_counters_1_inc_mask = _csr_io_counters_1_eventSel[63:8]; // @[Events.scala:40:44]
wire [3:0] _csr_io_counters_1_inc_sets_T = {2'h0, csr_io_counters_1_inc_sets_lo}; // @[Events.scala:16:21]
wire [55:0] _csr_io_counters_1_inc_sets_T_1 = {52'h0, csr_io_counters_1_inc_mask[3:0] & _csr_io_counters_1_inc_sets_T}; // @[Events.scala:16:21, :40:44]
wire csr_io_counters_1_inc_sets_0 = |_csr_io_counters_1_inc_sets_T_1; // @[core.scala:248:{68,76}]
assign _csr_io_counters_1_inc_sets_T_3 = b2_mispredict & _csr_io_counters_1_inc_sets_T_2; // @[core.scala:190:18, :258:65, :259:63]
assign hits_1_2 = _csr_io_counters_1_inc_sets_T_3; // @[Events.scala:13:25]
wire [2:0] csr_io_counters_1_inc_sets_hi_1 = {csr_io_counters_1_inc_sets_hi_hi, hits_1_2}; // @[Events.scala:13:25, :16:21]
wire [4:0] _csr_io_counters_1_inc_sets_T_4 = {csr_io_counters_1_inc_sets_hi_1, csr_io_counters_1_inc_sets_lo_1}; // @[Events.scala:16:21]
wire [55:0] _csr_io_counters_1_inc_sets_T_5 = {51'h0, csr_io_counters_1_inc_mask[4:0] & _csr_io_counters_1_inc_sets_T_4}; // @[Events.scala:16:21, :40:44]
wire csr_io_counters_1_inc_sets_1 = |_csr_io_counters_1_inc_sets_T_5; // @[core.scala:254:{68,76}]
wire [2:0] csr_io_counters_1_inc_sets_lo_2 = {csr_io_counters_1_inc_sets_lo_hi, hits_2_0}; // @[Events.scala:13:25, :16:21]
wire [2:0] csr_io_counters_1_inc_sets_hi_2 = {csr_io_counters_1_inc_sets_hi_hi_1, hits_2_3}; // @[Events.scala:13:25, :16:21]
wire [5:0] _csr_io_counters_1_inc_sets_T_6 = {csr_io_counters_1_inc_sets_hi_2, csr_io_counters_1_inc_sets_lo_2}; // @[Events.scala:16:21]
wire [55:0] _csr_io_counters_1_inc_sets_T_7 = {50'h0, csr_io_counters_1_inc_mask[5:0] & _csr_io_counters_1_inc_sets_T_6}; // @[Events.scala:16:21, :40:44]
wire csr_io_counters_1_inc_sets_2 = |_csr_io_counters_1_inc_sets_T_7; // @[core.scala:264:{68,76}]
wire _csr_io_counters_1_inc_T = csr_io_counters_1_inc_set == 2'h1; // @[package.scala:39:86]
wire _csr_io_counters_1_inc_T_1 = _csr_io_counters_1_inc_T ? csr_io_counters_1_inc_sets_1 : csr_io_counters_1_inc_sets_0; // @[package.scala:39:{76,86}]
wire _csr_io_counters_1_inc_T_2 = csr_io_counters_1_inc_set == 2'h2; // @[package.scala:39:86]
wire _csr_io_counters_1_inc_T_3 = _csr_io_counters_1_inc_T_2 ? csr_io_counters_1_inc_sets_2 : _csr_io_counters_1_inc_T_1; // @[package.scala:39:{76,86}]
wire _csr_io_counters_1_inc_T_4 = &csr_io_counters_1_inc_set; // @[package.scala:39:86]
wire _csr_io_counters_1_inc_T_5 = _csr_io_counters_1_inc_T_4 ? csr_io_counters_1_inc_sets_2 : _csr_io_counters_1_inc_T_3; // @[package.scala:39:{76,86}]
reg csr_io_counters_1_inc_REG; // @[core.scala:283:50]
reg [63:0] debug_tsc_reg; // @[core.scala:288:30]
assign io_lsu_tsc_reg_0 = debug_tsc_reg; // @[core.scala:51:7, :288:30]
reg [63:0] debug_irt_reg; // @[core.scala:289:30]
reg [63:0] debug_brs_0; // @[core.scala:290:26]
reg [63:0] debug_brs_1; // @[core.scala:290:26]
reg [63:0] debug_brs_2; // @[core.scala:290:26]
reg [63:0] debug_brs_3; // @[core.scala:290:26]
reg [63:0] debug_jals_0; // @[core.scala:291:26]
reg [63:0] debug_jals_1; // @[core.scala:291:26]
reg [63:0] debug_jals_2; // @[core.scala:291:26]
reg [63:0] debug_jals_3; // @[core.scala:291:26]
reg [63:0] debug_jalrs_0; // @[core.scala:292:26]
reg [63:0] debug_jalrs_1; // @[core.scala:292:26]
reg [63:0] debug_jalrs_2; // @[core.scala:292:26]
reg [63:0] debug_jalrs_3; // @[core.scala:292:26]
wire _GEN_7 = _rob_io_commit_uops_0_debug_fsrc == 2'h0; // @[core.scala:143:32, :297:41]
wire _debug_brs_0_T; // @[core.scala:297:41]
assign _debug_brs_0_T = _GEN_7; // @[core.scala:297:41]
wire _debug_jals_0_T; // @[core.scala:302:41]
assign _debug_jals_0_T = _GEN_7; // @[core.scala:297:41, :302:41]
wire _debug_jalrs_0_T; // @[core.scala:307:41]
assign _debug_jalrs_0_T = _GEN_7; // @[core.scala:297:41, :307:41]
wire _debug_brs_0_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_0_T; // @[core.scala:143:32, :296:36, :297:41]
wire _debug_brs_0_T_2 = _debug_brs_0_T_1 & _rob_io_commit_uops_0_is_br; // @[core.scala:143:32, :296:36, :297:50]
wire _debug_brs_0_WIRE_0 = _debug_brs_0_T_2; // @[core.scala:295:52, :297:50]
wire [64:0] _debug_brs_0_T_3 = {1'h0, debug_brs_0} + {64'h0, _debug_brs_0_WIRE_0}; // @[core.scala:290:26, :295:{34,52}]
wire [63:0] _debug_brs_0_T_4 = _debug_brs_0_T_3[63:0]; // @[core.scala:295:34]
wire _debug_jals_0_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_0_T; // @[core.scala:143:32, :301:36, :302:41]
wire _debug_jals_0_T_2 = _debug_jals_0_T_1 & _rob_io_commit_uops_0_is_jal; // @[core.scala:143:32, :301:36, :302:50]
wire _debug_jals_0_WIRE_0 = _debug_jals_0_T_2; // @[core.scala:300:54, :302:50]
wire [64:0] _debug_jals_0_T_3 = {1'h0, debug_jals_0} + {64'h0, _debug_jals_0_WIRE_0}; // @[core.scala:291:26, :300:{36,54}]
wire [63:0] _debug_jals_0_T_4 = _debug_jals_0_T_3[63:0]; // @[core.scala:300:36]
wire _debug_jalrs_0_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_0_T; // @[core.scala:143:32, :306:36, :307:41]
wire _debug_jalrs_0_T_2 = _debug_jalrs_0_T_1 & _rob_io_commit_uops_0_is_jalr; // @[core.scala:143:32, :306:36, :307:50]
wire _debug_jalrs_0_WIRE_0 = _debug_jalrs_0_T_2; // @[core.scala:305:56, :307:50]
wire [64:0] _debug_jalrs_0_T_3 = {1'h0, debug_jalrs_0} + {64'h0, _debug_jalrs_0_WIRE_0}; // @[core.scala:292:26, :305:{38,56}]
wire [63:0] _debug_jalrs_0_T_4 = _debug_jalrs_0_T_3[63:0]; // @[core.scala:305:38]
wire _GEN_8 = _rob_io_commit_uops_0_debug_fsrc == 2'h1; // @[core.scala:143:32, :297:41]
wire _debug_brs_1_T; // @[core.scala:297:41]
assign _debug_brs_1_T = _GEN_8; // @[core.scala:297:41]
wire _debug_jals_1_T; // @[core.scala:302:41]
assign _debug_jals_1_T = _GEN_8; // @[core.scala:297:41, :302:41]
wire _debug_jalrs_1_T; // @[core.scala:307:41]
assign _debug_jalrs_1_T = _GEN_8; // @[core.scala:297:41, :307:41]
wire _debug_brs_1_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_1_T; // @[core.scala:143:32, :296:36, :297:41]
wire _debug_brs_1_T_2 = _debug_brs_1_T_1 & _rob_io_commit_uops_0_is_br; // @[core.scala:143:32, :296:36, :297:50]
wire _debug_brs_1_WIRE_0 = _debug_brs_1_T_2; // @[core.scala:295:52, :297:50]
wire [64:0] _debug_brs_1_T_3 = {1'h0, debug_brs_1} + {64'h0, _debug_brs_1_WIRE_0}; // @[core.scala:290:26, :295:{34,52}]
wire [63:0] _debug_brs_1_T_4 = _debug_brs_1_T_3[63:0]; // @[core.scala:295:34]
wire _debug_jals_1_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_1_T; // @[core.scala:143:32, :301:36, :302:41]
wire _debug_jals_1_T_2 = _debug_jals_1_T_1 & _rob_io_commit_uops_0_is_jal; // @[core.scala:143:32, :301:36, :302:50]
wire _debug_jals_1_WIRE_0 = _debug_jals_1_T_2; // @[core.scala:300:54, :302:50]
wire [64:0] _debug_jals_1_T_3 = {1'h0, debug_jals_1} + {64'h0, _debug_jals_1_WIRE_0}; // @[core.scala:291:26, :300:{36,54}]
wire [63:0] _debug_jals_1_T_4 = _debug_jals_1_T_3[63:0]; // @[core.scala:300:36]
wire _debug_jalrs_1_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_1_T; // @[core.scala:143:32, :306:36, :307:41]
wire _debug_jalrs_1_T_2 = _debug_jalrs_1_T_1 & _rob_io_commit_uops_0_is_jalr; // @[core.scala:143:32, :306:36, :307:50]
wire _debug_jalrs_1_WIRE_0 = _debug_jalrs_1_T_2; // @[core.scala:305:56, :307:50]
wire [64:0] _debug_jalrs_1_T_3 = {1'h0, debug_jalrs_1} + {64'h0, _debug_jalrs_1_WIRE_0}; // @[core.scala:292:26, :305:{38,56}]
wire [63:0] _debug_jalrs_1_T_4 = _debug_jalrs_1_T_3[63:0]; // @[core.scala:305:38]
wire _GEN_9 = _rob_io_commit_uops_0_debug_fsrc == 2'h2; // @[core.scala:143:32, :297:41]
wire _debug_brs_2_T; // @[core.scala:297:41]
assign _debug_brs_2_T = _GEN_9; // @[core.scala:297:41]
wire _debug_jals_2_T; // @[core.scala:302:41]
assign _debug_jals_2_T = _GEN_9; // @[core.scala:297:41, :302:41]
wire _debug_jalrs_2_T; // @[core.scala:307:41]
assign _debug_jalrs_2_T = _GEN_9; // @[core.scala:297:41, :307:41]
wire _debug_brs_2_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_2_T; // @[core.scala:143:32, :296:36, :297:41]
wire _debug_brs_2_T_2 = _debug_brs_2_T_1 & _rob_io_commit_uops_0_is_br; // @[core.scala:143:32, :296:36, :297:50]
wire _debug_brs_2_WIRE_0 = _debug_brs_2_T_2; // @[core.scala:295:52, :297:50]
wire [64:0] _debug_brs_2_T_3 = {1'h0, debug_brs_2} + {64'h0, _debug_brs_2_WIRE_0}; // @[core.scala:290:26, :295:{34,52}]
wire [63:0] _debug_brs_2_T_4 = _debug_brs_2_T_3[63:0]; // @[core.scala:295:34]
wire _debug_jals_2_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_2_T; // @[core.scala:143:32, :301:36, :302:41]
wire _debug_jals_2_T_2 = _debug_jals_2_T_1 & _rob_io_commit_uops_0_is_jal; // @[core.scala:143:32, :301:36, :302:50]
wire _debug_jals_2_WIRE_0 = _debug_jals_2_T_2; // @[core.scala:300:54, :302:50]
wire [64:0] _debug_jals_2_T_3 = {1'h0, debug_jals_2} + {64'h0, _debug_jals_2_WIRE_0}; // @[core.scala:291:26, :300:{36,54}]
wire [63:0] _debug_jals_2_T_4 = _debug_jals_2_T_3[63:0]; // @[core.scala:300:36]
wire _debug_jalrs_2_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_2_T; // @[core.scala:143:32, :306:36, :307:41]
wire _debug_jalrs_2_T_2 = _debug_jalrs_2_T_1 & _rob_io_commit_uops_0_is_jalr; // @[core.scala:143:32, :306:36, :307:50]
wire _debug_jalrs_2_WIRE_0 = _debug_jalrs_2_T_2; // @[core.scala:305:56, :307:50]
wire [64:0] _debug_jalrs_2_T_3 = {1'h0, debug_jalrs_2} + {64'h0, _debug_jalrs_2_WIRE_0}; // @[core.scala:292:26, :305:{38,56}]
wire [63:0] _debug_jalrs_2_T_4 = _debug_jalrs_2_T_3[63:0]; // @[core.scala:305:38]
wire _debug_brs_3_T = &_rob_io_commit_uops_0_debug_fsrc; // @[core.scala:143:32, :297:41]
wire _debug_brs_3_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_3_T; // @[core.scala:143:32, :296:36, :297:41]
wire _debug_brs_3_T_2 = _debug_brs_3_T_1 & _rob_io_commit_uops_0_is_br; // @[core.scala:143:32, :296:36, :297:50]
wire _debug_brs_3_WIRE_0 = _debug_brs_3_T_2; // @[core.scala:295:52, :297:50]
wire [64:0] _debug_brs_3_T_3 = {1'h0, debug_brs_3} + {64'h0, _debug_brs_3_WIRE_0}; // @[core.scala:290:26, :295:{34,52}]
wire [63:0] _debug_brs_3_T_4 = _debug_brs_3_T_3[63:0]; // @[core.scala:295:34]
wire _debug_jals_3_T = &_rob_io_commit_uops_0_debug_fsrc; // @[core.scala:143:32, :297:41, :302:41]
wire _debug_jals_3_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_3_T; // @[core.scala:143:32, :301:36, :302:41]
wire _debug_jals_3_T_2 = _debug_jals_3_T_1 & _rob_io_commit_uops_0_is_jal; // @[core.scala:143:32, :301:36, :302:50]
wire _debug_jals_3_WIRE_0 = _debug_jals_3_T_2; // @[core.scala:300:54, :302:50]
wire [64:0] _debug_jals_3_T_3 = {1'h0, debug_jals_3} + {64'h0, _debug_jals_3_WIRE_0}; // @[core.scala:291:26, :300:{36,54}]
wire [63:0] _debug_jals_3_T_4 = _debug_jals_3_T_3[63:0]; // @[core.scala:300:36]
wire _debug_jalrs_3_T = &_rob_io_commit_uops_0_debug_fsrc; // @[core.scala:143:32, :297:41, :307:41]
wire _debug_jalrs_3_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_3_T; // @[core.scala:143:32, :306:36, :307:41]
wire _debug_jalrs_3_T_2 = _debug_jalrs_3_T_1 & _rob_io_commit_uops_0_is_jalr; // @[core.scala:143:32, :306:36, :307:50]
wire _debug_jalrs_3_WIRE_0 = _debug_jalrs_3_T_2; // @[core.scala:305:56, :307:50]
wire [64:0] _debug_jalrs_3_T_3 = {1'h0, debug_jalrs_3} + {64'h0, _debug_jalrs_3_WIRE_0}; // @[core.scala:292:26, :305:{38,56}]
wire [63:0] _debug_jalrs_3_T_4 = _debug_jalrs_3_T_3[63:0]; // @[core.scala:305:38]
wire [64:0] _debug_tsc_reg_T = {1'h0, debug_tsc_reg} + 65'h1; // @[core.scala:288:30, :316:34]
wire [63:0] _debug_tsc_reg_T_1 = _debug_tsc_reg_T[63:0]; // @[core.scala:316:34]
wire _debug_irt_reg_T; // @[core.scala:317:44]
wire [64:0] _debug_irt_reg_T_1 = {1'h0, debug_irt_reg} + {64'h0, _debug_irt_reg_T}; // @[core.scala:289:30, :317:{34,44}]
wire [63:0] _debug_irt_reg_T_2 = _debug_irt_reg_T_1[63:0]; // @[core.scala:317:34]
wire _io_ifu_flush_icache_T = _rob_io_commit_arch_valids_0 & _rob_io_commit_uops_0_is_fencei; // @[core.scala:143:32, :388:35]
wire _io_ifu_flush_icache_T_1 = dec_valids_0 & dec_uops_0_is_jalr; // @[core.scala:157:24, :158:24, :389:28]
wire _io_ifu_flush_icache_T_2 = _io_ifu_flush_icache_T_1 & _csr_io_status_debug; // @[core.scala:271:19, :389:{28,51}]
reg io_ifu_flush_icache_REG; // @[core.scala:389:13]
assign _io_ifu_flush_icache_T_3 = _io_ifu_flush_icache_T | io_ifu_flush_icache_REG; // @[core.scala:388:{35,71}, :389:13]
assign io_ifu_flush_icache_0 = _io_ifu_flush_icache_T_3; // @[core.scala:51:7, :388:71]
reg REG; // @[core.scala:401:16]
reg [2:0] flush_typ; // @[core.scala:404:28]
wire _io_ifu_redirect_pc_T = flush_typ == 3'h3; // @[core.scala:404:28, :411:44]
reg [39:0] io_ifu_redirect_pc_REG; // @[core.scala:412:49]
reg [39:0] io_ifu_redirect_pc_REG_1; // @[core.scala:412:41]
wire [39:0] _io_ifu_redirect_pc_T_1 = _io_ifu_redirect_pc_T ? io_ifu_redirect_pc_REG_1 : _csr_io_evec; // @[core.scala:271:19, :411:{33,44}, :412:41]
wire [39:0] _flush_pc_T = ~io_ifu_get_pc_0_pc_0; // @[util.scala:237:7]
wire [39:0] _flush_pc_T_1 = {_flush_pc_T[39:6], 6'h3F}; // @[util.scala:237:{7,11}]
wire [39:0] _flush_pc_T_2 = ~_flush_pc_T_1; // @[util.scala:237:{5,11}]
reg [5:0] flush_pc_REG; // @[core.scala:416:32]
wire [40:0] _flush_pc_T_3 = {1'h0, _flush_pc_T_2} + {35'h0, flush_pc_REG}; // @[util.scala:237:5]
wire [39:0] _flush_pc_T_4 = _flush_pc_T_3[39:0]; // @[core.scala:416:23]
reg flush_pc_REG_1; // @[core.scala:417:36]
wire [1:0] _flush_pc_T_5 = {flush_pc_REG_1, 1'h0}; // @[core.scala:417:{28,36}]
wire [40:0] _flush_pc_T_6 = {1'h0, _flush_pc_T_4} - {39'h0, _flush_pc_T_5}; // @[core.scala:416:23, :417:{23,28}]
wire [39:0] flush_pc = _flush_pc_T_6[39:0]; // @[core.scala:417:23]
reg flush_pc_next_REG; // @[core.scala:418:49]
wire [2:0] _flush_pc_next_T = flush_pc_next_REG ? 3'h2 : 3'h4; // @[core.scala:418:{41,49}]
wire [40:0] _flush_pc_next_T_1 = {1'h0, flush_pc} + {38'h0, _flush_pc_next_T}; // @[core.scala:417:23, :418:{36,41}]
wire [39:0] flush_pc_next = _flush_pc_next_T_1[39:0]; // @[core.scala:418:36]
wire _io_ifu_redirect_pc_T_2 = flush_typ == 3'h2; // @[rob.scala:167:40]
wire [39:0] _io_ifu_redirect_pc_T_3 = _io_ifu_redirect_pc_T_2 ? flush_pc : flush_pc_next; // @[rob.scala:167:40]
reg [3:0] io_ifu_redirect_ftq_idx_REG; // @[core.scala:423:39]
reg REG_1; // @[core.scala:424:50]
wire _T_12 = brupdate_b2_mispredict & ~REG_1; // @[core.scala:188:23, :424:{39,42,50}]
wire [39:0] _block_pc_T = ~io_ifu_get_pc_1_pc_0; // @[util.scala:237:7]
wire [39:0] _block_pc_T_1 = {_block_pc_T[39:6], 6'h3F}; // @[util.scala:237:{7,11}]
wire [39:0] block_pc = ~_block_pc_T_1; // @[util.scala:237:{5,11}]
wire [39:0] uop_maybe_pc = {block_pc[39:6], block_pc[5:0] | brupdate_b2_uop_pc_lob}; // @[util.scala:237:5]
wire [39:0] _jal_br_target_T = uop_maybe_pc; // @[core.scala:426:33, :429:36]
wire _npc_T = brupdate_b2_uop_is_rvc | brupdate_b2_uop_edge_inst; // @[core.scala:188:23, :427:57]
wire [2:0] _npc_T_1 = _npc_T ? 3'h2 : 3'h4; // @[core.scala:427:{33,57}]
wire [40:0] _npc_T_2 = {1'h0, uop_maybe_pc} + {38'h0, _npc_T_1}; // @[core.scala:418:36, :426:33, :427:{28,33}]
wire [39:0] npc = _npc_T_2[39:0]; // @[core.scala:427:28]
wire [39:0] _jal_br_target_T_10; // @[core.scala:430:75]
wire [39:0] jal_br_target; // @[core.scala:428:29]
wire [40:0] _jal_br_target_T_1 = {_jal_br_target_T[39], _jal_br_target_T} + {{20{brupdate_b2_target_offset[20]}}, brupdate_b2_target_offset}; // @[core.scala:188:23, :429:{36,43}]
wire [39:0] _jal_br_target_T_2 = _jal_br_target_T_1[39:0]; // @[core.scala:429:43]
wire [39:0] _jal_br_target_T_3 = _jal_br_target_T_2; // @[core.scala:429:43]
wire [38:0] _jal_br_target_T_4 = {39{brupdate_b2_uop_edge_inst}}; // @[core.scala:188:23, :430:12]
wire [39:0] _jal_br_target_T_5 = {_jal_br_target_T_4, 1'h0}; // @[core.scala:430:{12,61}]
wire [39:0] _jal_br_target_T_6 = _jal_br_target_T_5; // @[core.scala:430:{61,67}]
wire [40:0] _jal_br_target_T_7 = {_jal_br_target_T_3[39], _jal_br_target_T_3} + {_jal_br_target_T_6[39], _jal_br_target_T_6}; // @[core.scala:429:{43,71}, :430:67]
wire [39:0] _jal_br_target_T_8 = _jal_br_target_T_7[39:0]; // @[core.scala:429:71]
wire [39:0] _jal_br_target_T_9 = _jal_br_target_T_8; // @[core.scala:429:71]
assign _jal_br_target_T_10 = _jal_br_target_T_9; // @[core.scala:429:71, :430:75]
assign jal_br_target = _jal_br_target_T_10; // @[core.scala:428:29, :430:75]
wire _bj_addr_T = brupdate_b2_cfi_type == 3'h3; // @[core.scala:188:23, :431:44]
wire [39:0] bj_addr = _bj_addr_T ? brupdate_b2_jalr_target : jal_br_target; // @[core.scala:188:23, :428:29, :431:{22,44}]
wire _mispredict_target_T = brupdate_b2_pc_sel == 2'h0; // @[core.scala:188:23, :432:52]
wire [39:0] mispredict_target = _mispredict_target_T ? npc : bj_addr; // @[core.scala:427:28, :431:22, :432:{32,52}]
assign io_ifu_redirect_val_0 = REG | _T_12; // @[core.scala:51:7, :401:{16,38}, :402:27, :424:{39,72}]
assign io_ifu_redirect_pc_0 = REG ? (flush_typ[0] ? _io_ifu_redirect_pc_T_1 : _io_ifu_redirect_pc_T_3) : mispredict_target; // @[rob.scala:166:40]
assign io_ifu_redirect_ftq_idx_0 = REG ? io_ifu_redirect_ftq_idx_REG : brupdate_b2_uop_ftq_idx; // @[core.scala:51:7, :188:23, :401:{16,38}, :423:{29,39}, :424:72]
wire _GEN_10 = brupdate_b2_cfi_type == 3'h1; // @[core.scala:188:23, :437:48]
wire _use_same_ghist_T; // @[core.scala:437:48]
assign _use_same_ghist_T = _GEN_10; // @[core.scala:437:48]
wire _next_ghist_T; // @[core.scala:447:28]
assign _next_ghist_T = _GEN_10; // @[core.scala:437:48, :447:28]
wire _use_same_ghist_T_1 = ~brupdate_b2_taken; // @[core.scala:188:23, :438:27]
wire _use_same_ghist_T_2 = _use_same_ghist_T & _use_same_ghist_T_1; // @[core.scala:437:{48,59}, :438:27]
wire [39:0] _use_same_ghist_T_3 = ~block_pc; // @[util.scala:237:5]
wire [39:0] _use_same_ghist_T_4 = {_use_same_ghist_T_3[39:3], 3'h7}; // @[frontend.scala:160:{33,39}]
wire [39:0] _use_same_ghist_T_5 = ~_use_same_ghist_T_4; // @[frontend.scala:160:{31,39}]
wire [39:0] _use_same_ghist_T_6 = ~npc; // @[frontend.scala:160:33]
wire [39:0] _use_same_ghist_T_7 = {_use_same_ghist_T_6[39:3], 3'h7}; // @[frontend.scala:160:{33,39}]
wire [39:0] _use_same_ghist_T_8 = ~_use_same_ghist_T_7; // @[frontend.scala:160:{31,39}]
wire _use_same_ghist_T_9 = _use_same_ghist_T_5 == _use_same_ghist_T_8; // @[frontend.scala:160:31]
wire use_same_ghist = _use_same_ghist_T_2 & _use_same_ghist_T_9; // @[core.scala:437:59, :438:46, :439:47]
wire [3:0] _cfi_idx_T_2 = {_cfi_idx_T, 3'h0}; // @[core.scala:442:{10,32}]
wire [5:0] _cfi_idx_T_3 = {brupdate_b2_uop_pc_lob[5:4], brupdate_b2_uop_pc_lob[3:0] ^ _cfi_idx_T_2}; // @[core.scala:188:23, :441:43, :442:10]
wire [1:0] cfi_idx = _cfi_idx_T_3[2:1]; // @[core.scala:441:43, :442:74]
wire [1:0] next_ghist_cfi_idx_fixed = cfi_idx; // @[frontend.scala:85:32]
wire _GEN_11 = io_ifu_get_pc_1_entry_cfi_idx_bits_0 == cfi_idx; // @[core.scala:51:7, :442:74, :451:55]
wire _next_ghist_T_1; // @[core.scala:451:55]
assign _next_ghist_T_1 = _GEN_11; // @[core.scala:451:55]
wire _next_ghist_T_3; // @[core.scala:452:55]
assign _next_ghist_T_3 = _GEN_11; // @[core.scala:451:55, :452:55]
wire _next_ghist_T_2 = io_ifu_get_pc_1_entry_cfi_is_call_0 & _next_ghist_T_1; // @[core.scala:51:7, :451:{29,55}]
wire _next_ghist_new_history_ras_idx_T = _next_ghist_T_2; // @[frontend.scala:123:42]
wire _next_ghist_T_4 = io_ifu_get_pc_1_entry_cfi_is_ret_0 & _next_ghist_T_3; // @[core.scala:51:7, :452:{29,55}]
wire _next_ghist_new_history_ras_idx_T_4 = _next_ghist_T_4; // @[frontend.scala:124:42]
wire [3:0] next_ghist_cfi_idx_oh = 4'h1 << next_ghist_cfi_idx_fixed; // @[OneHot.scala:58:35]
wire [3:0] _next_ghist_not_taken_branches_T = next_ghist_cfi_idx_oh; // @[OneHot.scala:58:35]
wire [4:0] _next_ghist_new_history_ras_idx_T_9; // @[frontend.scala:123:31]
wire [63:0] next_ghist_old_history; // @[frontend.scala:87:27]
wire [4:0] next_ghist_ras_idx; // @[frontend.scala:87:27]
wire [3:0] _next_ghist_not_taken_branches_T_1 = {1'h0, next_ghist_cfi_idx_oh[3:1]}; // @[OneHot.scala:58:35]
wire [3:0] _next_ghist_not_taken_branches_T_2 = {2'h0, next_ghist_cfi_idx_oh[3:2]}; // @[OneHot.scala:58:35]
wire [3:0] _next_ghist_not_taken_branches_T_3 = {3'h0, next_ghist_cfi_idx_oh[3]}; // @[OneHot.scala:58:35]
wire [3:0] _next_ghist_not_taken_branches_T_4 = _next_ghist_not_taken_branches_T | _next_ghist_not_taken_branches_T_1; // @[util.scala:373:{29,45}]
wire [3:0] _next_ghist_not_taken_branches_T_5 = _next_ghist_not_taken_branches_T_4 | _next_ghist_not_taken_branches_T_2; // @[util.scala:373:{29,45}]
wire [3:0] _next_ghist_not_taken_branches_T_6 = _next_ghist_not_taken_branches_T_5 | _next_ghist_not_taken_branches_T_3; // @[util.scala:373:{29,45}]
wire _GEN_12 = _next_ghist_T & brupdate_b2_taken; // @[frontend.scala:90:84]
wire _next_ghist_not_taken_branches_T_7; // @[frontend.scala:90:84]
assign _next_ghist_not_taken_branches_T_7 = _GEN_12; // @[frontend.scala:90:84]
wire _next_ghist_new_history_old_history_T; // @[frontend.scala:98:48]
assign _next_ghist_new_history_old_history_T = _GEN_12; // @[frontend.scala:90:84, :98:48]
wire [3:0] _next_ghist_not_taken_branches_T_8 = _next_ghist_not_taken_branches_T_7 ? next_ghist_cfi_idx_oh : 4'h0; // @[OneHot.scala:58:35]
wire [3:0] _next_ghist_not_taken_branches_T_9 = ~_next_ghist_not_taken_branches_T_8; // @[frontend.scala:90:{69,73}]
wire [3:0] _next_ghist_not_taken_branches_T_10 = _next_ghist_not_taken_branches_T_6 & _next_ghist_not_taken_branches_T_9; // @[util.scala:373:45]
wire [3:0] _next_ghist_not_taken_branches_T_12 = _next_ghist_not_taken_branches_T_10; // @[frontend.scala:89:44, :90:67]
wire [3:0] next_ghist_not_taken_branches = io_ifu_get_pc_1_entry_br_mask_0 & _next_ghist_not_taken_branches_T_12; // @[frontend.scala:89:{39,44}]
wire _next_ghist_saw_not_taken_branch_T = |next_ghist_not_taken_branches; // @[frontend.scala:89:39, :97:53]
wire next_ghist_saw_not_taken_branch = _next_ghist_saw_not_taken_branch_T | io_ifu_get_pc_1_ghist_current_saw_branch_not_taken_0; // @[frontend.scala:97:{53,61}]
wire _next_ghist_new_history_old_history_T_1 = _next_ghist_new_history_old_history_T; // @[frontend.scala:98:{48,61}]
wire [64:0] _GEN_13 = {io_ifu_get_pc_1_ghist_old_history_0, 1'h0}; // @[frontend.scala:98:91]
wire [64:0] _next_ghist_new_history_old_history_T_2; // @[frontend.scala:98:91]
assign _next_ghist_new_history_old_history_T_2 = _GEN_13; // @[frontend.scala:98:91]
wire [64:0] _next_ghist_new_history_old_history_T_4; // @[frontend.scala:99:91]
assign _next_ghist_new_history_old_history_T_4 = _GEN_13; // @[frontend.scala:98:91, :99:91]
wire [64:0] _next_ghist_new_history_old_history_T_3 = {_next_ghist_new_history_old_history_T_2[64:1], 1'h1}; // @[frontend.scala:98:{91,96}]
wire [64:0] _next_ghist_new_history_old_history_T_5 = next_ghist_saw_not_taken_branch ? _next_ghist_new_history_old_history_T_4 : {1'h0, io_ifu_get_pc_1_ghist_old_history_0}; // @[frontend.scala:97:61, :99:{37,91}]
wire [64:0] _next_ghist_new_history_old_history_T_6 = _next_ghist_new_history_old_history_T_1 ? _next_ghist_new_history_old_history_T_3 : _next_ghist_new_history_old_history_T_5; // @[frontend.scala:98:{37,61,96}, :99:37]
assign next_ghist_old_history = _next_ghist_new_history_old_history_T_6[63:0]; // @[frontend.scala:87:27, :98:{31,37}]
wire [5:0] _GEN_14 = {1'h0, io_ifu_get_pc_1_ghist_ras_idx_0}; // @[util.scala:203:14]
wire [5:0] _next_ghist_new_history_ras_idx_T_1 = _GEN_14 + 6'h1; // @[util.scala:203:14]
wire [4:0] _next_ghist_new_history_ras_idx_T_2 = _next_ghist_new_history_ras_idx_T_1[4:0]; // @[util.scala:203:14]
wire [4:0] _next_ghist_new_history_ras_idx_T_3 = _next_ghist_new_history_ras_idx_T_2; // @[util.scala:203:{14,20}]
wire [5:0] _next_ghist_new_history_ras_idx_T_5 = _GEN_14 - 6'h1; // @[util.scala:203:14, :220:14]
wire [4:0] _next_ghist_new_history_ras_idx_T_6 = _next_ghist_new_history_ras_idx_T_5[4:0]; // @[util.scala:220:14]
wire [4:0] _next_ghist_new_history_ras_idx_T_7 = _next_ghist_new_history_ras_idx_T_6; // @[util.scala:220:{14,20}]
wire [4:0] _next_ghist_new_history_ras_idx_T_8 = _next_ghist_new_history_ras_idx_T_4 ? _next_ghist_new_history_ras_idx_T_7 : io_ifu_get_pc_1_ghist_ras_idx_0; // @[util.scala:220:20]
assign _next_ghist_new_history_ras_idx_T_9 = _next_ghist_new_history_ras_idx_T ? _next_ghist_new_history_ras_idx_T_3 : _next_ghist_new_history_ras_idx_T_8; // @[util.scala:203:20]
assign next_ghist_ras_idx = _next_ghist_new_history_ras_idx_T_9; // @[frontend.scala:87:27, :123:31]
wire [63:0] _io_ifu_redirect_ghist_T_old_history = use_same_ghist ? io_ifu_get_pc_1_ghist_old_history_0 : next_ghist_old_history; // @[frontend.scala:87:27]
wire _io_ifu_redirect_ghist_T_current_saw_branch_not_taken = use_same_ghist & io_ifu_get_pc_1_ghist_current_saw_branch_not_taken_0; // @[core.scala:51:7, :438:46, :455:35]
wire _io_ifu_redirect_ghist_T_new_saw_branch_not_taken = use_same_ghist & io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0; // @[core.scala:51:7, :438:46, :455:35]
wire _io_ifu_redirect_ghist_T_new_saw_branch_taken = use_same_ghist & io_ifu_get_pc_1_ghist_new_saw_branch_taken_0; // @[core.scala:51:7, :438:46, :455:35]
wire [4:0] _io_ifu_redirect_ghist_T_ras_idx = use_same_ghist ? io_ifu_get_pc_1_ghist_ras_idx_0 : next_ghist_ras_idx; // @[frontend.scala:87:27]
assign io_ifu_redirect_ghist_old_history_0 = REG ? 64'h0 : _io_ifu_redirect_ghist_T_old_history; // @[core.scala:51:7, :401:{16,38}, :409:27, :424:72, :455:35]
assign io_ifu_redirect_ghist_new_saw_branch_not_taken_0 = ~REG & _io_ifu_redirect_ghist_T_new_saw_branch_not_taken; // @[core.scala:51:7, :401:{16,38}, :409:27, :424:72, :455:35]
assign io_ifu_redirect_ghist_new_saw_branch_taken_0 = ~REG & _io_ifu_redirect_ghist_T_new_saw_branch_taken; // @[core.scala:51:7, :401:{16,38}, :409:27, :424:72, :455:35]
assign io_ifu_redirect_ghist_ras_idx_0 = REG ? new_ghist_ras_idx : _io_ifu_redirect_ghist_T_ras_idx; // @[core.scala:51:7, :401:{16,38}, :406:29, :409:27, :424:72, :455:35]
assign io_ifu_redirect_ghist_current_saw_branch_not_taken_0 = REG | use_same_ghist; // @[core.scala:51:7, :401:{16,38}, :409:27, :424:72, :438:46]
assign io_ifu_redirect_flush_0 = REG | _T_12 | (|{_rob_io_flush_frontend, brupdate_b1_mispredict_mask}); // @[core.scala:51:7, :143:32, :188:23, :224:42, :401:{16,38}, :403:27, :424:{39,72}, :435:29, :460:{38,78}]
wire _io_ifu_commit_valid_T = _rob_io_commit_valids_0 | _rob_io_com_xcpt_valid; // @[core.scala:143:32, :466:59]
wire [3:0] _io_ifu_commit_bits_T = _rob_io_com_xcpt_valid ? _rob_io_com_xcpt_bits_ftq_idx : _rob_io_commit_uops_0_ftq_idx; // @[core.scala:143:32, :467:29]
reg REG_2; // @[core.scala:475:18]
reg io_ifu_sfence_REG_valid; // @[core.scala:476:31]
assign io_ifu_sfence_valid_0 = io_ifu_sfence_REG_valid; // @[core.scala:51:7, :476:31]
reg io_ifu_sfence_REG_bits_rs1; // @[core.scala:476:31]
assign io_ifu_sfence_bits_rs1_0 = io_ifu_sfence_REG_bits_rs1; // @[core.scala:51:7, :476:31]
reg io_ifu_sfence_REG_bits_rs2; // @[core.scala:476:31]
assign io_ifu_sfence_bits_rs2_0 = io_ifu_sfence_REG_bits_rs2; // @[core.scala:51:7, :476:31]
reg [38:0] io_ifu_sfence_REG_bits_addr; // @[core.scala:476:31]
assign io_ifu_sfence_bits_addr_0 = io_ifu_sfence_REG_bits_addr; // @[core.scala:51:7, :476:31]
reg io_ifu_sfence_REG_bits_asid; // @[core.scala:476:31]
assign io_ifu_sfence_bits_asid_0 = io_ifu_sfence_REG_bits_asid; // @[core.scala:51:7, :476:31]
reg dec_finished_mask; // @[core.scala:496:34]
wire _dec_valids_0_T_1 = dec_finished_mask; // @[core.scala:496:34, :509:61]
wire _dec_brmask_logic_io_is_branch_0_T = dec_finished_mask; // @[core.scala:496:34, :600:59]
wire _dec_valids_0_T = io_ifu_fetchpacket_valid_0 & io_ifu_fetchpacket_bits_uops_0_valid_0; // @[core.scala:51:7, :508:68]
wire _dec_valids_0_T_2 = ~_dec_valids_0_T_1; // @[core.scala:509:{43,61}]
assign _dec_valids_0_T_3 = _dec_valids_0_T & _dec_valids_0_T_2; // @[core.scala:508:{68,97}, :509:43]
assign dec_valids_0 = _dec_valids_0_T_3; // @[core.scala:157:24, :508:97]
wire jmp_pc_req_ready; // @[core.scala:522:25]
wire jmp_pc_req_valid; // @[core.scala:522:25]
wire [3:0] jmp_pc_req_bits; // @[core.scala:522:25]
wire xcpt_pc_req_ready; // @[core.scala:523:25]
wire flush_pc_req_valid; // @[core.scala:524:26]
wire [3:0] flush_pc_req_bits; // @[core.scala:524:26]
wire _jmp_pc_req_valid_T = iss_uops_1_fu_code == 10'h2; // @[core.scala:173:24, :539:90]
wire _jmp_pc_req_valid_T_1 = iss_valids_1 & _jmp_pc_req_valid_T; // @[core.scala:172:24, :539:{56,90}]
reg jmp_pc_req_valid_REG; // @[core.scala:539:30]
assign jmp_pc_req_valid = jmp_pc_req_valid_REG; // @[core.scala:522:25, :539:30]
reg [3:0] jmp_pc_req_bits_REG; // @[core.scala:540:30]
assign jmp_pc_req_bits = jmp_pc_req_bits_REG; // @[core.scala:522:25, :540:30]
assign dec_xcpts_0 = dec_uops_0_exception & dec_valids_0; // @[core.scala:157:24, :158:24, :162:24, :566:71]
wire _dec_xcpt_stall_T = ~xcpt_pc_req_ready; // @[core.scala:523:25, :567:50]
wire dec_xcpt_stall = dec_xcpts_0 & _dec_xcpt_stall_T; // @[core.scala:162:24, :567:{47,50}]
wire branch_mask_full_0; // @[core.scala:569:30]
wire _dec_hazards_T = ~dis_ready; // @[core.scala:169:24, :573:26]
wire _dec_hazards_T_1 = _dec_hazards_T | _rob_io_commit_rollback; // @[core.scala:143:32, :573:26, :574:23]
wire _dec_hazards_T_2 = _dec_hazards_T_1 | dec_xcpt_stall; // @[core.scala:567:47, :574:23, :575:23]
wire _dec_hazards_T_3 = _dec_hazards_T_2 | branch_mask_full_0; // @[core.scala:569:30, :575:23, :576:23]
wire _dec_hazards_T_4 = |brupdate_b1_mispredict_mask; // @[core.scala:188:23, :224:42, :577:54]
wire _dec_hazards_T_5 = _dec_hazards_T_3 | _dec_hazards_T_4; // @[core.scala:576:23, :577:{23,54}]
wire _dec_hazards_T_6 = _dec_hazards_T_5 | brupdate_b2_mispredict; // @[core.scala:188:23, :577:23, :578:23]
wire _dec_hazards_T_7 = _dec_hazards_T_6 | io_ifu_redirect_flush_0; // @[core.scala:51:7, :578:23, :579:23]
wire dec_hazards_0 = dec_valids_0 & _dec_hazards_T_7; // @[core.scala:157:24, :572:37, :579:23]
wire dec_stalls_0 = dec_hazards_0; // @[core.scala:572:37, :581:62]
assign dec_fire_0 = dec_valids_0 & ~dec_stalls_0; // @[core.scala:157:24, :159:24, :581:62, :582:{58,61}]
wire _dec_finished_mask_T = dec_fire_0 | dec_finished_mask; // @[core.scala:159:24, :496:34, :590:42]
reg dec_brmask_logic_io_flush_pipeline_REG; // @[core.scala:597:48]
wire _dec_brmask_logic_io_is_branch_0_T_1 = ~_dec_brmask_logic_io_is_branch_0_T; // @[core.scala:600:{41,59}]
wire _dec_brmask_logic_io_is_branch_0_T_2 = ~dec_uops_0_is_sfb; // @[core.scala:158:24]
wire _dec_brmask_logic_io_is_branch_0_T_3 = dec_uops_0_is_br & _dec_brmask_logic_io_is_branch_0_T_2; // @[core.scala:158:24]
wire _dec_brmask_logic_io_is_branch_0_T_4 = _dec_brmask_logic_io_is_branch_0_T_3 | dec_uops_0_is_jalr; // @[core.scala:158:24]
wire _dec_brmask_logic_io_is_branch_0_T_5 = _dec_brmask_logic_io_is_branch_0_T_1 & _dec_brmask_logic_io_is_branch_0_T_4; // @[core.scala:600:{41,63}]
wire _dec_brmask_logic_io_will_fire_0_T = ~dec_uops_0_is_sfb; // @[core.scala:158:24]
wire _dec_brmask_logic_io_will_fire_0_T_1 = dec_uops_0_is_br & _dec_brmask_logic_io_will_fire_0_T; // @[core.scala:158:24]
wire _dec_brmask_logic_io_will_fire_0_T_2 = _dec_brmask_logic_io_will_fire_0_T_1 | dec_uops_0_is_jalr; // @[core.scala:158:24]
wire _dec_brmask_logic_io_will_fire_0_T_3 = dec_fire_0 & _dec_brmask_logic_io_will_fire_0_T_2; // @[core.scala:159:24, :601:54]
wire _GEN_15 = dis_uops_0_lrs1_rtype == 2'h1; // @[core.scala:167:24, :654:52]
wire _dis_uops_0_prs1_T; // @[core.scala:654:52]
assign _dis_uops_0_prs1_T = _GEN_15; // @[core.scala:654:52]
wire _dis_uops_0_prs1_busy_T_2; // @[core.scala:665:73]
assign _dis_uops_0_prs1_busy_T_2 = _GEN_15; // @[core.scala:654:52, :665:73]
wire _GEN_16 = dis_uops_0_lrs1_rtype == 2'h0; // @[core.scala:167:24, :655:52]
wire _dis_uops_0_prs1_T_1; // @[core.scala:655:52]
assign _dis_uops_0_prs1_T_1 = _GEN_16; // @[core.scala:655:52]
wire _dis_uops_0_prs1_busy_T; // @[core.scala:664:73]
assign _dis_uops_0_prs1_busy_T = _GEN_16; // @[core.scala:655:52, :664:73]
wire [5:0] _dis_uops_0_prs1_T_2 = _dis_uops_0_prs1_T_1 ? _rename_stage_io_ren2_uops_0_prs1 : dis_uops_0_lrs1; // @[core.scala:103:32, :167:24, :655:{28,52}]
assign _dis_uops_0_prs1_T_3 = _dis_uops_0_prs1_T ? _fp_rename_stage_io_ren2_uops_0_prs1 : _dis_uops_0_prs1_T_2; // @[core.scala:104:46, :654:{28,52}, :655:28]
assign dis_uops_0_prs1 = _dis_uops_0_prs1_T_3; // @[core.scala:167:24, :654:28]
wire _GEN_17 = dis_uops_0_lrs2_rtype == 2'h1; // @[core.scala:167:24, :656:52]
wire _dis_uops_0_prs2_T; // @[core.scala:656:52]
assign _dis_uops_0_prs2_T = _GEN_17; // @[core.scala:656:52]
wire _dis_uops_0_prs2_busy_T_2; // @[core.scala:667:73]
assign _dis_uops_0_prs2_busy_T_2 = _GEN_17; // @[core.scala:656:52, :667:73]
assign _dis_uops_0_prs2_T_1 = _dis_uops_0_prs2_T ? _fp_rename_stage_io_ren2_uops_0_prs2 : _rename_stage_io_ren2_uops_0_prs2; // @[core.scala:103:32, :104:46, :656:{28,52}]
assign dis_uops_0_prs2 = _dis_uops_0_prs2_T_1; // @[core.scala:167:24, :656:28]
wire _GEN_18 = dis_uops_0_dst_rtype == 2'h1; // @[core.scala:167:24, :659:52]
wire _dis_uops_0_pdst_T; // @[core.scala:659:52]
assign _dis_uops_0_pdst_T = _GEN_18; // @[core.scala:659:52]
wire _dis_uops_0_stale_pdst_T; // @[core.scala:662:57]
assign _dis_uops_0_stale_pdst_T = _GEN_18; // @[core.scala:659:52, :662:57]
wire _dis_uops_0_pdst_T_1 = dis_uops_0_dst_rtype == 2'h0; // @[core.scala:167:24, :660:52]
wire [5:0] _dis_uops_0_pdst_T_2 = _dis_uops_0_pdst_T_1 ? _rename_stage_io_ren2_uops_0_pdst : 6'h0; // @[core.scala:103:32, :660:{28,52}]
assign _dis_uops_0_pdst_T_3 = _dis_uops_0_pdst_T ? _fp_rename_stage_io_ren2_uops_0_pdst : _dis_uops_0_pdst_T_2; // @[core.scala:104:46, :659:{28,52}, :660:28]
assign dis_uops_0_pdst = _dis_uops_0_pdst_T_3; // @[core.scala:167:24, :659:28]
assign _dis_uops_0_stale_pdst_T_1 = _dis_uops_0_stale_pdst_T ? _fp_rename_stage_io_ren2_uops_0_stale_pdst : _rename_stage_io_ren2_uops_0_stale_pdst; // @[core.scala:103:32, :104:46, :662:{34,57}]
assign dis_uops_0_stale_pdst = _dis_uops_0_stale_pdst_T_1; // @[core.scala:167:24, :662:34]
wire _dis_uops_0_prs1_busy_T_1 = _rename_stage_io_ren2_uops_0_prs1_busy & _dis_uops_0_prs1_busy_T; // @[core.scala:103:32, :664:{46,73}]
wire _dis_uops_0_prs1_busy_T_3 = _fp_rename_stage_io_ren2_uops_0_prs1_busy & _dis_uops_0_prs1_busy_T_2; // @[core.scala:104:46, :665:{46,73}]
assign _dis_uops_0_prs1_busy_T_4 = _dis_uops_0_prs1_busy_T_1 | _dis_uops_0_prs1_busy_T_3; // @[core.scala:664:{46,85}, :665:46]
assign dis_uops_0_prs1_busy = _dis_uops_0_prs1_busy_T_4; // @[core.scala:167:24, :664:85]
wire _dis_uops_0_prs2_busy_T = dis_uops_0_lrs2_rtype == 2'h0; // @[core.scala:167:24, :666:73]
wire _dis_uops_0_prs2_busy_T_1 = _rename_stage_io_ren2_uops_0_prs2_busy & _dis_uops_0_prs2_busy_T; // @[core.scala:103:32, :666:{46,73}]
wire _dis_uops_0_prs2_busy_T_3 = _fp_rename_stage_io_ren2_uops_0_prs2_busy & _dis_uops_0_prs2_busy_T_2; // @[core.scala:104:46, :667:{46,73}]
assign _dis_uops_0_prs2_busy_T_4 = _dis_uops_0_prs2_busy_T_1 | _dis_uops_0_prs2_busy_T_3; // @[core.scala:666:{46,85}, :667:46]
assign dis_uops_0_prs2_busy = _dis_uops_0_prs2_busy_T_4; // @[core.scala:167:24, :666:85]
assign _dis_uops_0_prs3_busy_T = _fp_rename_stage_io_ren2_uops_0_prs3_busy & dis_uops_0_frs3_en; // @[core.scala:104:46, :167:24, :668:46]
assign dis_uops_0_prs3_busy = _dis_uops_0_prs3_busy_T; // @[core.scala:167:24, :668:46]
wire _dis_uops_0_ppred_busy_T = ~dis_uops_0_is_br; // @[core.scala:167:24]
wire _dis_uops_0_ppred_busy_T_1 = _dis_uops_0_ppred_busy_T & dis_uops_0_is_sfb; // @[core.scala:167:24]
wire _ren_stalls_0_T = _rename_stage_io_ren_stalls_0 | _fp_rename_stage_io_ren_stalls_0; // @[core.scala:103:32, :104:46, :671:52]
assign _ren_stalls_0_T_1 = _ren_stalls_0_T; // @[core.scala:671:{52,63}]
assign ren_stalls_0 = _ren_stalls_0_T_1; // @[core.scala:163:24, :671:63]
wire _dis_prior_slot_unique_T = dis_valids_0 & dis_uops_0_is_unique; // @[core.scala:166:24, :167:24, :684:101]
wire dis_prior_slot_unique_1 = _dis_prior_slot_unique_T; // @[core.scala:684:{96,101}]
wire _wait_for_empty_pipeline_T = custom_csrs_csrs_0_value[3]; // @[core.scala:276:25]
wire _wait_for_empty_pipeline_T_1 = dis_uops_0_is_unique | _wait_for_empty_pipeline_T; // @[core.scala:167:24, :685:85]
wire _wait_for_empty_pipeline_T_2 = ~_rob_io_empty; // @[core.scala:143:32, :686:36]
wire _wait_for_empty_pipeline_T_3 = ~io_lsu_fencei_rdy_0; // @[core.scala:51:7, :686:53]
wire _wait_for_empty_pipeline_T_4 = _wait_for_empty_pipeline_T_2 | _wait_for_empty_pipeline_T_3; // @[core.scala:686:{36,50,53}]
wire _wait_for_empty_pipeline_T_5 = _wait_for_empty_pipeline_T_4; // @[core.scala:686:{50,72}]
wire wait_for_empty_pipeline_0 = _wait_for_empty_pipeline_T_1 & _wait_for_empty_pipeline_T_5; // @[core.scala:685:{85,112}, :686:72]
wire _wait_for_rocc_T = dis_uops_0_is_fence | dis_uops_0_is_fencei; // @[core.scala:167:24, :689:47]
wire _GEN_19 = dis_uops_0_uopc == 7'h6C; // @[core.scala:167:24, :691:76]
wire _block_rocc_T; // @[core.scala:691:76]
assign _block_rocc_T = _GEN_19; // @[core.scala:691:76]
wire _dis_rocc_alloc_stall_T; // @[core.scala:692:51]
assign _dis_rocc_alloc_stall_T = _GEN_19; // @[core.scala:691:76, :692:51]
wire _block_rocc_T_1 = dis_valids_0 & _block_rocc_T; // @[core.scala:166:24, :691:{66,76}]
wire block_rocc_1 = _block_rocc_T_1; // @[core.scala:691:{66,109}]
wire _dis_hazards_T = ~_rob_io_ready; // @[core.scala:143:32, :697:26]
wire _dis_hazards_T_1 = _dis_hazards_T | ren_stalls_0; // @[core.scala:163:24, :697:26, :698:23]
wire _dis_hazards_T_2 = io_lsu_ldq_full_0_0 & dis_uops_0_uses_ldq; // @[core.scala:51:7, :167:24, :699:45]
wire _dis_hazards_T_3 = _dis_hazards_T_1 | _dis_hazards_T_2; // @[core.scala:698:23, :699:{23,45}]
wire _dis_hazards_T_4 = io_lsu_stq_full_0_0 & dis_uops_0_uses_stq; // @[core.scala:51:7, :167:24, :700:45]
wire _dis_hazards_T_5 = _dis_hazards_T_3 | _dis_hazards_T_4; // @[core.scala:699:23, :700:{23,45}]
wire _dis_hazards_T_6 = ~_dispatcher_io_ren_uops_0_ready; // @[core.scala:114:32, :701:26]
wire _dis_hazards_T_7 = _dis_hazards_T_5 | _dis_hazards_T_6; // @[core.scala:700:23, :701:{23,26}]
wire _dis_hazards_T_8 = _dis_hazards_T_7 | wait_for_empty_pipeline_0; // @[core.scala:685:112, :701:23, :702:23]
wire _dis_hazards_T_9 = _dis_hazards_T_8; // @[core.scala:702:23, :703:23]
wire _dis_hazards_T_10 = _dis_hazards_T_9; // @[core.scala:703:23, :704:23]
wire _dis_hazards_T_11 = _dis_hazards_T_10; // @[core.scala:704:23, :705:23]
wire _dis_hazards_T_12 = |brupdate_b1_mispredict_mask; // @[core.scala:188:23, :224:42, :706:54]
wire _dis_hazards_T_13 = _dis_hazards_T_11 | _dis_hazards_T_12; // @[core.scala:705:23, :706:{23,54}]
wire _dis_hazards_T_14 = _dis_hazards_T_13 | brupdate_b2_mispredict; // @[core.scala:188:23, :706:23, :707:23]
wire _dis_hazards_T_15 = _dis_hazards_T_14 | io_ifu_redirect_flush_0; // @[core.scala:51:7, :707:23, :708:23]
wire dis_hazards_0 = dis_valids_0 & _dis_hazards_T_15; // @[core.scala:166:24, :696:37, :708:23]
wire dis_stalls_0 = dis_hazards_0; // @[core.scala:696:37, :713:62]
assign _io_lsu_fence_dmem_T = dis_valids_0 & wait_for_empty_pipeline_0; // @[core.scala:166:24, :685:112, :711:86]
assign io_lsu_fence_dmem_0 = _io_lsu_fence_dmem_T; // @[core.scala:51:7, :711:86]
assign dis_fire_0 = dis_valids_0 & ~dis_stalls_0; // @[core.scala:166:24, :168:24, :713:62, :714:{62,65}]
assign _dis_ready_T = ~dis_stalls_0; // @[core.scala:713:62, :714:65, :715:16]
assign dis_ready = _dis_ready_T; // @[core.scala:169:24, :715:16]
reg REG_3; // @[core.scala:738:16]
assign io_ifu_commit_valid_0 = REG_3 | _io_ifu_commit_valid_T; // @[core.scala:51:7, :466:{23,59}, :738:{16,94}, :739:25]
reg [3:0] io_ifu_commit_bits_REG; // @[core.scala:740:35]
assign io_ifu_commit_bits_0 = {12'h0, REG_3 ? io_ifu_commit_bits_REG : _io_ifu_commit_bits_T}; // @[core.scala:51:7, :467:{23,29}, :738:{16,94}, :740:{25,35}]
wire _GEN_20 = _ll_wbarb_io_out_bits_uop_dst_rtype == 2'h0; // @[core.scala:132:32, :795:90]
wire _int_iss_wakeups_0_valid_T_1; // @[core.scala:795:90]
assign _int_iss_wakeups_0_valid_T_1 = _GEN_20; // @[core.scala:795:90]
wire _int_ren_wakeups_0_valid_T_1; // @[core.scala:798:90]
assign _int_ren_wakeups_0_valid_T_1 = _GEN_20; // @[core.scala:795:90, :798:90]
wire _iregfile_io_write_ports_0_wport_valid_T; // @[regfile.scala:57:61]
assign _iregfile_io_write_ports_0_wport_valid_T = _GEN_20; // @[regfile.scala:57:61]
wire _int_iss_wakeups_0_valid_T; // @[Decoupled.scala:51:35]
assign _int_iss_wakeups_0_valid_T_2 = _int_iss_wakeups_0_valid_T & _int_iss_wakeups_0_valid_T_1; // @[Decoupled.scala:51:35]
assign int_iss_wakeups_0_valid = _int_iss_wakeups_0_valid_T_2; // @[core.scala:147:30, :795:52]
wire _int_ren_wakeups_0_valid_T; // @[Decoupled.scala:51:35]
assign _int_ren_wakeups_0_valid_T_2 = _int_ren_wakeups_0_valid_T & _int_ren_wakeups_0_valid_T_1; // @[Decoupled.scala:51:35]
assign int_ren_wakeups_0_valid = _int_ren_wakeups_0_valid_T_2; // @[core.scala:148:30, :798:52]
wire _fast_wakeup_valid_T_7; // @[core.scala:827:52]
assign int_iss_wakeups_1_valid = fast_wakeup_valid; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_valid = fast_wakeup_valid; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_uopc = fast_wakeup_bits_uop_uopc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_uopc = fast_wakeup_bits_uop_uopc; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_inst = fast_wakeup_bits_uop_inst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_inst = fast_wakeup_bits_uop_inst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_debug_inst = fast_wakeup_bits_uop_debug_inst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_debug_inst = fast_wakeup_bits_uop_debug_inst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_is_rvc = fast_wakeup_bits_uop_is_rvc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_is_rvc = fast_wakeup_bits_uop_is_rvc; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_debug_pc = fast_wakeup_bits_uop_debug_pc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_debug_pc = fast_wakeup_bits_uop_debug_pc; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_iq_type = fast_wakeup_bits_uop_iq_type; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_iq_type = fast_wakeup_bits_uop_iq_type; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_fu_code = fast_wakeup_bits_uop_fu_code; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_fu_code = fast_wakeup_bits_uop_fu_code; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ctrl_br_type = fast_wakeup_bits_uop_ctrl_br_type; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ctrl_br_type = fast_wakeup_bits_uop_ctrl_br_type; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ctrl_op1_sel = fast_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ctrl_op1_sel = fast_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ctrl_op2_sel = fast_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ctrl_op2_sel = fast_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ctrl_imm_sel = fast_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ctrl_imm_sel = fast_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ctrl_op_fcn = fast_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ctrl_op_fcn = fast_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ctrl_fcn_dw = fast_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ctrl_fcn_dw = fast_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ctrl_csr_cmd = fast_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ctrl_csr_cmd = fast_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ctrl_is_load = fast_wakeup_bits_uop_ctrl_is_load; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ctrl_is_load = fast_wakeup_bits_uop_ctrl_is_load; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ctrl_is_sta = fast_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ctrl_is_sta = fast_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ctrl_is_std = fast_wakeup_bits_uop_ctrl_is_std; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ctrl_is_std = fast_wakeup_bits_uop_ctrl_is_std; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_iw_state = fast_wakeup_bits_uop_iw_state; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_iw_state = fast_wakeup_bits_uop_iw_state; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_iw_p1_poisoned = fast_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_iw_p1_poisoned = fast_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_iw_p2_poisoned = fast_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_iw_p2_poisoned = fast_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_is_br = fast_wakeup_bits_uop_is_br; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_is_br = fast_wakeup_bits_uop_is_br; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_is_jalr = fast_wakeup_bits_uop_is_jalr; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_is_jalr = fast_wakeup_bits_uop_is_jalr; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_is_jal = fast_wakeup_bits_uop_is_jal; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_is_jal = fast_wakeup_bits_uop_is_jal; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_is_sfb = fast_wakeup_bits_uop_is_sfb; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_is_sfb = fast_wakeup_bits_uop_is_sfb; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_br_mask = fast_wakeup_bits_uop_br_mask; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_br_mask = fast_wakeup_bits_uop_br_mask; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_br_tag = fast_wakeup_bits_uop_br_tag; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_br_tag = fast_wakeup_bits_uop_br_tag; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ftq_idx = fast_wakeup_bits_uop_ftq_idx; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ftq_idx = fast_wakeup_bits_uop_ftq_idx; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_edge_inst = fast_wakeup_bits_uop_edge_inst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_edge_inst = fast_wakeup_bits_uop_edge_inst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_pc_lob = fast_wakeup_bits_uop_pc_lob; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_pc_lob = fast_wakeup_bits_uop_pc_lob; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_taken = fast_wakeup_bits_uop_taken; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_taken = fast_wakeup_bits_uop_taken; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_imm_packed = fast_wakeup_bits_uop_imm_packed; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_imm_packed = fast_wakeup_bits_uop_imm_packed; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_csr_addr = fast_wakeup_bits_uop_csr_addr; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_csr_addr = fast_wakeup_bits_uop_csr_addr; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_rob_idx = fast_wakeup_bits_uop_rob_idx; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_rob_idx = fast_wakeup_bits_uop_rob_idx; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ldq_idx = fast_wakeup_bits_uop_ldq_idx; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ldq_idx = fast_wakeup_bits_uop_ldq_idx; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_stq_idx = fast_wakeup_bits_uop_stq_idx; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_stq_idx = fast_wakeup_bits_uop_stq_idx; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_rxq_idx = fast_wakeup_bits_uop_rxq_idx; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_rxq_idx = fast_wakeup_bits_uop_rxq_idx; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_pdst = fast_wakeup_bits_uop_pdst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_pdst = fast_wakeup_bits_uop_pdst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_prs1 = fast_wakeup_bits_uop_prs1; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_prs1 = fast_wakeup_bits_uop_prs1; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_prs2 = fast_wakeup_bits_uop_prs2; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_prs2 = fast_wakeup_bits_uop_prs2; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_prs3 = fast_wakeup_bits_uop_prs3; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_prs3 = fast_wakeup_bits_uop_prs3; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ppred = fast_wakeup_bits_uop_ppred; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ppred = fast_wakeup_bits_uop_ppred; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_prs1_busy = fast_wakeup_bits_uop_prs1_busy; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_prs1_busy = fast_wakeup_bits_uop_prs1_busy; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_prs2_busy = fast_wakeup_bits_uop_prs2_busy; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_prs2_busy = fast_wakeup_bits_uop_prs2_busy; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_prs3_busy = fast_wakeup_bits_uop_prs3_busy; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_prs3_busy = fast_wakeup_bits_uop_prs3_busy; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ppred_busy = fast_wakeup_bits_uop_ppred_busy; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ppred_busy = fast_wakeup_bits_uop_ppred_busy; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_stale_pdst = fast_wakeup_bits_uop_stale_pdst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_stale_pdst = fast_wakeup_bits_uop_stale_pdst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_exception = fast_wakeup_bits_uop_exception; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_exception = fast_wakeup_bits_uop_exception; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_exc_cause = fast_wakeup_bits_uop_exc_cause; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_exc_cause = fast_wakeup_bits_uop_exc_cause; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_bypassable = fast_wakeup_bits_uop_bypassable; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_bypassable = fast_wakeup_bits_uop_bypassable; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_mem_cmd = fast_wakeup_bits_uop_mem_cmd; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_mem_cmd = fast_wakeup_bits_uop_mem_cmd; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_mem_size = fast_wakeup_bits_uop_mem_size; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_mem_size = fast_wakeup_bits_uop_mem_size; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_mem_signed = fast_wakeup_bits_uop_mem_signed; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_mem_signed = fast_wakeup_bits_uop_mem_signed; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_is_fence = fast_wakeup_bits_uop_is_fence; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_is_fence = fast_wakeup_bits_uop_is_fence; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_is_fencei = fast_wakeup_bits_uop_is_fencei; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_is_fencei = fast_wakeup_bits_uop_is_fencei; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_is_amo = fast_wakeup_bits_uop_is_amo; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_is_amo = fast_wakeup_bits_uop_is_amo; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_uses_ldq = fast_wakeup_bits_uop_uses_ldq; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_uses_ldq = fast_wakeup_bits_uop_uses_ldq; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_uses_stq = fast_wakeup_bits_uop_uses_stq; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_uses_stq = fast_wakeup_bits_uop_uses_stq; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_is_sys_pc2epc = fast_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_is_sys_pc2epc = fast_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_is_unique = fast_wakeup_bits_uop_is_unique; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_is_unique = fast_wakeup_bits_uop_is_unique; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_flush_on_commit = fast_wakeup_bits_uop_flush_on_commit; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_flush_on_commit = fast_wakeup_bits_uop_flush_on_commit; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ldst_is_rs1 = fast_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ldst_is_rs1 = fast_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ldst = fast_wakeup_bits_uop_ldst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ldst = fast_wakeup_bits_uop_ldst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_lrs1 = fast_wakeup_bits_uop_lrs1; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_lrs1 = fast_wakeup_bits_uop_lrs1; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_lrs2 = fast_wakeup_bits_uop_lrs2; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_lrs2 = fast_wakeup_bits_uop_lrs2; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_lrs3 = fast_wakeup_bits_uop_lrs3; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_lrs3 = fast_wakeup_bits_uop_lrs3; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ldst_val = fast_wakeup_bits_uop_ldst_val; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ldst_val = fast_wakeup_bits_uop_ldst_val; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_dst_rtype = fast_wakeup_bits_uop_dst_rtype; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_dst_rtype = fast_wakeup_bits_uop_dst_rtype; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_lrs1_rtype = fast_wakeup_bits_uop_lrs1_rtype; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_lrs1_rtype = fast_wakeup_bits_uop_lrs1_rtype; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_lrs2_rtype = fast_wakeup_bits_uop_lrs2_rtype; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_lrs2_rtype = fast_wakeup_bits_uop_lrs2_rtype; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_frs3_en = fast_wakeup_bits_uop_frs3_en; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_frs3_en = fast_wakeup_bits_uop_frs3_en; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_fp_val = fast_wakeup_bits_uop_fp_val; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_fp_val = fast_wakeup_bits_uop_fp_val; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_fp_single = fast_wakeup_bits_uop_fp_single; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_fp_single = fast_wakeup_bits_uop_fp_single; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_xcpt_pf_if = fast_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_xcpt_pf_if = fast_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_xcpt_ae_if = fast_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_xcpt_ae_if = fast_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_xcpt_ma_if = fast_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_xcpt_ma_if = fast_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_bp_debug_if = fast_wakeup_bits_uop_bp_debug_if; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_bp_debug_if = fast_wakeup_bits_uop_bp_debug_if; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_bp_xcpt_if = fast_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_bp_xcpt_if = fast_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_debug_fsrc = fast_wakeup_bits_uop_debug_fsrc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_debug_fsrc = fast_wakeup_bits_uop_debug_fsrc; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_debug_tsrc = fast_wakeup_bits_uop_debug_tsrc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_debug_tsrc = fast_wakeup_bits_uop_debug_tsrc; // @[core.scala:148:30, :814:29]
wire _slow_wakeup_valid_T_5; // @[core.scala:834:59]
assign int_iss_wakeups_2_valid = slow_wakeup_valid; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_valid = slow_wakeup_valid; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_uopc = slow_wakeup_bits_uop_uopc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_uopc = slow_wakeup_bits_uop_uopc; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_inst = slow_wakeup_bits_uop_inst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_inst = slow_wakeup_bits_uop_inst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_debug_inst = slow_wakeup_bits_uop_debug_inst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_debug_inst = slow_wakeup_bits_uop_debug_inst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_is_rvc = slow_wakeup_bits_uop_is_rvc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_is_rvc = slow_wakeup_bits_uop_is_rvc; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_debug_pc = slow_wakeup_bits_uop_debug_pc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_debug_pc = slow_wakeup_bits_uop_debug_pc; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_iq_type = slow_wakeup_bits_uop_iq_type; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_iq_type = slow_wakeup_bits_uop_iq_type; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_fu_code = slow_wakeup_bits_uop_fu_code; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_fu_code = slow_wakeup_bits_uop_fu_code; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ctrl_br_type = slow_wakeup_bits_uop_ctrl_br_type; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ctrl_br_type = slow_wakeup_bits_uop_ctrl_br_type; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ctrl_op1_sel = slow_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ctrl_op1_sel = slow_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ctrl_op2_sel = slow_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ctrl_op2_sel = slow_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ctrl_imm_sel = slow_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ctrl_imm_sel = slow_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ctrl_op_fcn = slow_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ctrl_op_fcn = slow_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ctrl_fcn_dw = slow_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ctrl_fcn_dw = slow_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ctrl_csr_cmd = slow_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ctrl_csr_cmd = slow_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ctrl_is_load = slow_wakeup_bits_uop_ctrl_is_load; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ctrl_is_load = slow_wakeup_bits_uop_ctrl_is_load; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ctrl_is_sta = slow_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ctrl_is_sta = slow_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ctrl_is_std = slow_wakeup_bits_uop_ctrl_is_std; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ctrl_is_std = slow_wakeup_bits_uop_ctrl_is_std; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_iw_state = slow_wakeup_bits_uop_iw_state; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_iw_state = slow_wakeup_bits_uop_iw_state; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_iw_p1_poisoned = slow_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_iw_p1_poisoned = slow_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_iw_p2_poisoned = slow_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_iw_p2_poisoned = slow_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_is_br = slow_wakeup_bits_uop_is_br; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_is_br = slow_wakeup_bits_uop_is_br; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_is_jalr = slow_wakeup_bits_uop_is_jalr; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_is_jalr = slow_wakeup_bits_uop_is_jalr; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_is_jal = slow_wakeup_bits_uop_is_jal; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_is_jal = slow_wakeup_bits_uop_is_jal; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_is_sfb = slow_wakeup_bits_uop_is_sfb; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_is_sfb = slow_wakeup_bits_uop_is_sfb; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_br_mask = slow_wakeup_bits_uop_br_mask; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_br_mask = slow_wakeup_bits_uop_br_mask; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_br_tag = slow_wakeup_bits_uop_br_tag; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_br_tag = slow_wakeup_bits_uop_br_tag; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ftq_idx = slow_wakeup_bits_uop_ftq_idx; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ftq_idx = slow_wakeup_bits_uop_ftq_idx; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_edge_inst = slow_wakeup_bits_uop_edge_inst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_edge_inst = slow_wakeup_bits_uop_edge_inst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_pc_lob = slow_wakeup_bits_uop_pc_lob; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_pc_lob = slow_wakeup_bits_uop_pc_lob; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_taken = slow_wakeup_bits_uop_taken; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_taken = slow_wakeup_bits_uop_taken; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_imm_packed = slow_wakeup_bits_uop_imm_packed; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_imm_packed = slow_wakeup_bits_uop_imm_packed; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_csr_addr = slow_wakeup_bits_uop_csr_addr; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_csr_addr = slow_wakeup_bits_uop_csr_addr; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_rob_idx = slow_wakeup_bits_uop_rob_idx; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_rob_idx = slow_wakeup_bits_uop_rob_idx; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ldq_idx = slow_wakeup_bits_uop_ldq_idx; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ldq_idx = slow_wakeup_bits_uop_ldq_idx; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_stq_idx = slow_wakeup_bits_uop_stq_idx; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_stq_idx = slow_wakeup_bits_uop_stq_idx; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_rxq_idx = slow_wakeup_bits_uop_rxq_idx; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_rxq_idx = slow_wakeup_bits_uop_rxq_idx; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_pdst = slow_wakeup_bits_uop_pdst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_pdst = slow_wakeup_bits_uop_pdst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_prs1 = slow_wakeup_bits_uop_prs1; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_prs1 = slow_wakeup_bits_uop_prs1; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_prs2 = slow_wakeup_bits_uop_prs2; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_prs2 = slow_wakeup_bits_uop_prs2; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_prs3 = slow_wakeup_bits_uop_prs3; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_prs3 = slow_wakeup_bits_uop_prs3; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ppred = slow_wakeup_bits_uop_ppred; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ppred = slow_wakeup_bits_uop_ppred; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_prs1_busy = slow_wakeup_bits_uop_prs1_busy; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_prs1_busy = slow_wakeup_bits_uop_prs1_busy; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_prs2_busy = slow_wakeup_bits_uop_prs2_busy; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_prs2_busy = slow_wakeup_bits_uop_prs2_busy; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_prs3_busy = slow_wakeup_bits_uop_prs3_busy; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_prs3_busy = slow_wakeup_bits_uop_prs3_busy; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ppred_busy = slow_wakeup_bits_uop_ppred_busy; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ppred_busy = slow_wakeup_bits_uop_ppred_busy; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_stale_pdst = slow_wakeup_bits_uop_stale_pdst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_stale_pdst = slow_wakeup_bits_uop_stale_pdst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_exception = slow_wakeup_bits_uop_exception; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_exception = slow_wakeup_bits_uop_exception; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_exc_cause = slow_wakeup_bits_uop_exc_cause; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_exc_cause = slow_wakeup_bits_uop_exc_cause; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_bypassable = slow_wakeup_bits_uop_bypassable; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_bypassable = slow_wakeup_bits_uop_bypassable; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_mem_cmd = slow_wakeup_bits_uop_mem_cmd; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_mem_cmd = slow_wakeup_bits_uop_mem_cmd; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_mem_size = slow_wakeup_bits_uop_mem_size; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_mem_size = slow_wakeup_bits_uop_mem_size; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_mem_signed = slow_wakeup_bits_uop_mem_signed; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_mem_signed = slow_wakeup_bits_uop_mem_signed; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_is_fence = slow_wakeup_bits_uop_is_fence; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_is_fence = slow_wakeup_bits_uop_is_fence; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_is_fencei = slow_wakeup_bits_uop_is_fencei; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_is_fencei = slow_wakeup_bits_uop_is_fencei; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_is_amo = slow_wakeup_bits_uop_is_amo; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_is_amo = slow_wakeup_bits_uop_is_amo; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_uses_ldq = slow_wakeup_bits_uop_uses_ldq; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_uses_ldq = slow_wakeup_bits_uop_uses_ldq; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_uses_stq = slow_wakeup_bits_uop_uses_stq; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_uses_stq = slow_wakeup_bits_uop_uses_stq; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_is_sys_pc2epc = slow_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_is_sys_pc2epc = slow_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_is_unique = slow_wakeup_bits_uop_is_unique; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_is_unique = slow_wakeup_bits_uop_is_unique; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_flush_on_commit = slow_wakeup_bits_uop_flush_on_commit; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_flush_on_commit = slow_wakeup_bits_uop_flush_on_commit; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ldst_is_rs1 = slow_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ldst_is_rs1 = slow_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ldst = slow_wakeup_bits_uop_ldst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ldst = slow_wakeup_bits_uop_ldst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_lrs1 = slow_wakeup_bits_uop_lrs1; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_lrs1 = slow_wakeup_bits_uop_lrs1; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_lrs2 = slow_wakeup_bits_uop_lrs2; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_lrs2 = slow_wakeup_bits_uop_lrs2; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_lrs3 = slow_wakeup_bits_uop_lrs3; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_lrs3 = slow_wakeup_bits_uop_lrs3; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ldst_val = slow_wakeup_bits_uop_ldst_val; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ldst_val = slow_wakeup_bits_uop_ldst_val; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_dst_rtype = slow_wakeup_bits_uop_dst_rtype; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_dst_rtype = slow_wakeup_bits_uop_dst_rtype; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_lrs1_rtype = slow_wakeup_bits_uop_lrs1_rtype; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_lrs1_rtype = slow_wakeup_bits_uop_lrs1_rtype; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_lrs2_rtype = slow_wakeup_bits_uop_lrs2_rtype; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_lrs2_rtype = slow_wakeup_bits_uop_lrs2_rtype; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_frs3_en = slow_wakeup_bits_uop_frs3_en; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_frs3_en = slow_wakeup_bits_uop_frs3_en; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_fp_val = slow_wakeup_bits_uop_fp_val; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_fp_val = slow_wakeup_bits_uop_fp_val; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_fp_single = slow_wakeup_bits_uop_fp_single; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_fp_single = slow_wakeup_bits_uop_fp_single; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_xcpt_pf_if = slow_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_xcpt_pf_if = slow_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_xcpt_ae_if = slow_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_xcpt_ae_if = slow_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_xcpt_ma_if = slow_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_xcpt_ma_if = slow_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_bp_debug_if = slow_wakeup_bits_uop_bp_debug_if; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_bp_debug_if = slow_wakeup_bits_uop_bp_debug_if; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_bp_xcpt_if = slow_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_bp_xcpt_if = slow_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_debug_fsrc = slow_wakeup_bits_uop_debug_fsrc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_debug_fsrc = slow_wakeup_bits_uop_debug_fsrc; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_debug_tsrc = slow_wakeup_bits_uop_debug_tsrc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_debug_tsrc = slow_wakeup_bits_uop_debug_tsrc; // @[core.scala:148:30, :815:29]
wire _T_58 = _alu_exe_unit_io_iresp_bits_uop_dst_rtype != 2'h2; // @[execution-units.scala:119:32]
wire _slow_wakeup_valid_T; // @[micro-op.scala:149:36]
assign _slow_wakeup_valid_T = _T_58; // @[micro-op.scala:149:36]
wire _iregfile_io_write_ports_1_valid_T; // @[micro-op.scala:149:36]
assign _iregfile_io_write_ports_1_valid_T = _T_58; // @[micro-op.scala:149:36]
wire _rob_io_debug_wb_valids_1_T; // @[micro-op.scala:149:36]
assign _rob_io_debug_wb_valids_1_T = _T_58; // @[micro-op.scala:149:36]
wire _fast_wakeup_valid_T = iss_valids_1 & iss_uops_1_bypassable; // @[core.scala:172:24, :173:24, :824:45]
wire _fast_wakeup_valid_T_1 = iss_uops_1_dst_rtype == 2'h0; // @[core.scala:173:24, :826:53]
wire _fast_wakeup_valid_T_2 = _fast_wakeup_valid_T & _fast_wakeup_valid_T_1; // @[core.scala:824:45, :825:54, :826:53]
wire _fast_wakeup_valid_T_3 = _fast_wakeup_valid_T_2 & iss_uops_1_ldst_val; // @[core.scala:173:24, :825:54, :826:64]
wire _GEN_21 = iss_uops_1_iw_p1_poisoned | iss_uops_1_iw_p2_poisoned; // @[core.scala:173:24, :828:79]
wire _fast_wakeup_valid_T_4; // @[core.scala:828:79]
assign _fast_wakeup_valid_T_4 = _GEN_21; // @[core.scala:828:79]
wire _pred_wakeup_valid_T_3; // @[core.scala:864:84]
assign _pred_wakeup_valid_T_3 = _GEN_21; // @[core.scala:828:79, :864:84]
wire _iregister_read_io_iss_valids_1_T; // @[core.scala:981:72]
assign _iregister_read_io_iss_valids_1_T = _GEN_21; // @[core.scala:828:79, :981:72]
wire _fast_wakeup_valid_T_5 = io_lsu_ld_miss_0 & _fast_wakeup_valid_T_4; // @[core.scala:51:7, :828:{48,79}]
wire _fast_wakeup_valid_T_6 = ~_fast_wakeup_valid_T_5; // @[core.scala:828:{31,48}]
assign _fast_wakeup_valid_T_7 = _fast_wakeup_valid_T_3 & _fast_wakeup_valid_T_6; // @[core.scala:826:64, :827:52, :828:31]
assign fast_wakeup_valid = _fast_wakeup_valid_T_7; // @[core.scala:814:29, :827:52]
wire _slow_wakeup_valid_T_1 = _alu_exe_unit_io_iresp_valid & _slow_wakeup_valid_T; // @[execution-units.scala:119:32]
wire _slow_wakeup_valid_T_2 = ~_alu_exe_unit_io_iresp_bits_uop_bypassable; // @[execution-units.scala:119:32]
wire _slow_wakeup_valid_T_3 = _slow_wakeup_valid_T_1 & _slow_wakeup_valid_T_2; // @[core.scala:832:42, :833:54, :834:33]
wire _T_52 = _alu_exe_unit_io_iresp_bits_uop_dst_rtype == 2'h0; // @[execution-units.scala:119:32]
wire _slow_wakeup_valid_T_4; // @[core.scala:835:57]
assign _slow_wakeup_valid_T_4 = _T_52; // @[core.scala:835:57]
wire _iregfile_io_write_ports_1_valid_T_2; // @[core.scala:1160:77]
assign _iregfile_io_write_ports_1_valid_T_2 = _T_52; // @[core.scala:835:57, :1160:77]
wire _rob_io_debug_wb_valids_1_T_2; // @[core.scala:1240:86]
assign _rob_io_debug_wb_valids_1_T_2 = _T_52; // @[core.scala:835:57, :1240:86]
assign _slow_wakeup_valid_T_5 = _slow_wakeup_valid_T_3 & _slow_wakeup_valid_T_4; // @[core.scala:833:54, :834:59, :835:57]
assign slow_wakeup_valid = _slow_wakeup_valid_T_5; // @[core.scala:815:29, :834:59]
wire _pred_wakeup_valid_T = iss_uops_1_is_br & iss_uops_1_is_sfb; // @[core.scala:173:24]
wire _pred_wakeup_valid_T_4 = io_lsu_ld_miss_0 & _pred_wakeup_valid_T_3; // @[core.scala:51:7, :864:{42,84}]
wire _pred_wakeup_valid_T_5 = ~_pred_wakeup_valid_T_4; // @[core.scala:864:{25,42}]
wire loads_saturating = _mem_issue_unit_io_iss_valids_0 & _mem_issue_unit_io_iss_uops_0_uses_ldq; // @[core.scala:108:32, :908:57]
reg [4:0] saturating_loads_counter; // @[core.scala:909:41]
wire [5:0] _saturating_loads_counter_T = {1'h0, saturating_loads_counter} + 6'h1; // @[core.scala:909:41, :910:82]
wire [4:0] _saturating_loads_counter_T_1 = _saturating_loads_counter_T[4:0]; // @[core.scala:910:82]
reg pause_mem_REG; // @[core.scala:912:26]
wire _pause_mem_T_1 = &saturating_loads_counter; // @[core.scala:909:41, :912:73]
wire pause_mem = pause_mem_REG & _pause_mem_T_1; // @[core.scala:912:{26,45,73}]
wire [9:0] _mem_issue_unit_io_fu_types_0_T = {7'h0, ~pause_mem, 2'h0}; // @[core.scala:912:45, :931:53]
wire [9:0] _idiv_issued_T = iss_uops_1_fu_code & 10'h10; // @[core.scala:173:24]
wire _idiv_issued_T_1 = |_idiv_issued_T; // @[micro-op.scala:154:{40,47}]
wire idiv_issued = iss_valids_1 & _idiv_issued_T_1; // @[core.scala:172:24, :924:47]
reg [9:0] REG_4; // @[core.scala:925:38]
reg mem_issue_unit_io_flush_pipeline_REG; // @[core.scala:946:49]
reg int_issue_unit_io_flush_pipeline_REG; // @[core.scala:946:49]
reg memExeUnit_io_com_exception_REG; // @[core.scala:952:51]
wire _GEN_22 = int_iss_wakeups_0_bits_uop_iw_p1_poisoned | int_iss_wakeups_0_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61]
wire _mem_issue_unit_io_wakeup_ports_0_bits_poisoned_T; // @[core.scala:961:61]
assign _mem_issue_unit_io_wakeup_ports_0_bits_poisoned_T = _GEN_22; // @[core.scala:961:61]
wire _int_issue_unit_io_wakeup_ports_0_bits_poisoned_T; // @[core.scala:961:61]
assign _int_issue_unit_io_wakeup_ports_0_bits_poisoned_T = _GEN_22; // @[core.scala:961:61]
wire _GEN_23 = int_iss_wakeups_1_bits_uop_iw_p1_poisoned | int_iss_wakeups_1_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61]
wire _mem_issue_unit_io_wakeup_ports_1_bits_poisoned_T; // @[core.scala:961:61]
assign _mem_issue_unit_io_wakeup_ports_1_bits_poisoned_T = _GEN_23; // @[core.scala:961:61]
wire _int_issue_unit_io_wakeup_ports_1_bits_poisoned_T; // @[core.scala:961:61]
assign _int_issue_unit_io_wakeup_ports_1_bits_poisoned_T = _GEN_23; // @[core.scala:961:61]
wire _GEN_24 = int_iss_wakeups_2_bits_uop_iw_p1_poisoned | int_iss_wakeups_2_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61]
wire _mem_issue_unit_io_wakeup_ports_2_bits_poisoned_T; // @[core.scala:961:61]
assign _mem_issue_unit_io_wakeup_ports_2_bits_poisoned_T = _GEN_24; // @[core.scala:961:61]
wire _int_issue_unit_io_wakeup_ports_2_bits_poisoned_T; // @[core.scala:961:61]
assign _int_issue_unit_io_wakeup_ports_2_bits_poisoned_T = _GEN_24; // @[core.scala:961:61]
wire _iregister_read_io_iss_valids_0_T = iss_uops_0_iw_p1_poisoned | iss_uops_0_iw_p2_poisoned; // @[core.scala:173:24, :981:72]
wire _iregister_read_io_iss_valids_0_T_1 = io_lsu_ld_miss_0 & _iregister_read_io_iss_valids_0_T; // @[core.scala:51:7, :981:{41,72}]
wire _iregister_read_io_iss_valids_0_T_2 = ~_iregister_read_io_iss_valids_0_T_1; // @[core.scala:981:{24,41}]
wire _iregister_read_io_iss_valids_0_T_3 = iss_valids_0 & _iregister_read_io_iss_valids_0_T_2; // @[core.scala:172:24, :981:{21,24}]
wire _iregister_read_io_iss_valids_1_T_1 = io_lsu_ld_miss_0 & _iregister_read_io_iss_valids_1_T; // @[core.scala:51:7, :981:{41,72}]
wire _iregister_read_io_iss_valids_1_T_2 = ~_iregister_read_io_iss_valids_1_T_1; // @[core.scala:981:{24,41}]
wire _iregister_read_io_iss_valids_1_T_3 = iss_valids_1 & _iregister_read_io_iss_valids_1_T_2; // @[core.scala:172:24, :981:{21,24}]
reg iregister_read_io_kill_REG; // @[core.scala:987:38]
wire [2:0] _csr_io_rw_cmd_T = {~_alu_exe_unit_io_iresp_valid, 2'h0}; // @[CSR.scala:183:15]
wire [2:0] _csr_io_rw_cmd_T_1 = ~_csr_io_rw_cmd_T; // @[CSR.scala:183:{11,15}]
wire [2:0] _csr_io_rw_cmd_T_2 = _alu_exe_unit_io_iresp_bits_uop_ctrl_csr_cmd & _csr_io_rw_cmd_T_1; // @[CSR.scala:183:{9,11}]
reg csr_io_retire_REG; // @[core.scala:1015:30]
reg csr_io_exception_REG; // @[core.scala:1016:30]
wire [39:0] _csr_io_pc_T = ~io_ifu_get_pc_0_com_pc_0; // @[util.scala:237:7]
wire [39:0] _csr_io_pc_T_1 = {_csr_io_pc_T[39:6], 6'h3F}; // @[util.scala:237:{7,11}]
wire [39:0] _csr_io_pc_T_2 = ~_csr_io_pc_T_1; // @[util.scala:237:{5,11}]
reg [5:0] csr_io_pc_REG; // @[core.scala:1020:31]
wire [40:0] _csr_io_pc_T_3 = {1'h0, _csr_io_pc_T_2} + {35'h0, csr_io_pc_REG}; // @[util.scala:237:5]
wire [39:0] _csr_io_pc_T_4 = _csr_io_pc_T_3[39:0]; // @[core.scala:1020:22]
reg csr_io_pc_REG_1; // @[core.scala:1021:35]
wire [1:0] _csr_io_pc_T_5 = {csr_io_pc_REG_1, 1'h0}; // @[core.scala:1021:{27,35}]
wire [40:0] _csr_io_pc_T_6 = {1'h0, _csr_io_pc_T_4} - {39'h0, _csr_io_pc_T_5}; // @[core.scala:1020:22, :1021:{22,27}]
wire [39:0] _csr_io_pc_T_7 = _csr_io_pc_T_6[39:0]; // @[core.scala:1021:22]
reg [63:0] csr_io_cause_REG; // @[core.scala:1023:30]
wire _tval_valid_T = csr_io_cause_REG == 64'h3; // @[package.scala:16:47]
wire _tval_valid_T_1 = csr_io_cause_REG == 64'h4; // @[package.scala:16:47]
wire _tval_valid_T_2 = csr_io_cause_REG == 64'h6; // @[package.scala:16:47]
wire _tval_valid_T_3 = csr_io_cause_REG == 64'h5; // @[package.scala:16:47]
wire _tval_valid_T_4 = csr_io_cause_REG == 64'h7; // @[package.scala:16:47]
wire _tval_valid_T_5 = csr_io_cause_REG == 64'h1; // @[package.scala:16:47]
wire _tval_valid_T_6 = csr_io_cause_REG == 64'hD; // @[package.scala:16:47]
wire _tval_valid_T_7 = csr_io_cause_REG == 64'hF; // @[package.scala:16:47]
wire _tval_valid_T_8 = csr_io_cause_REG == 64'hC; // @[package.scala:16:47]
wire _tval_valid_T_9 = _tval_valid_T | _tval_valid_T_1; // @[package.scala:16:47, :81:59]
wire _tval_valid_T_10 = _tval_valid_T_9 | _tval_valid_T_2; // @[package.scala:16:47, :81:59]
wire _tval_valid_T_11 = _tval_valid_T_10 | _tval_valid_T_3; // @[package.scala:16:47, :81:59]
wire _tval_valid_T_12 = _tval_valid_T_11 | _tval_valid_T_4; // @[package.scala:16:47, :81:59]
wire _tval_valid_T_13 = _tval_valid_T_12 | _tval_valid_T_5; // @[package.scala:16:47, :81:59]
wire _tval_valid_T_14 = _tval_valid_T_13 | _tval_valid_T_6; // @[package.scala:16:47, :81:59]
wire _tval_valid_T_15 = _tval_valid_T_14 | _tval_valid_T_7; // @[package.scala:16:47, :81:59]
wire _tval_valid_T_16 = _tval_valid_T_15 | _tval_valid_T_8; // @[package.scala:16:47, :81:59]
wire tval_valid = csr_io_exception_REG & _tval_valid_T_16; // @[package.scala:81:59]
wire [63:0] _csr_io_tval_a_T; // @[core.scala:1049:18]
wire [24:0] csr_io_tval_a = _csr_io_tval_a_T[63:39]; // @[core.scala:1049:{18,25}]
wire _csr_io_tval_msb_T = csr_io_tval_a == 25'h0; // @[core.scala:1049:25, :1050:23]
wire _csr_io_tval_msb_T_1 = &csr_io_tval_a; // @[core.scala:1049:25, :1050:36]
wire _csr_io_tval_msb_T_2 = _csr_io_tval_msb_T | _csr_io_tval_msb_T_1; // @[core.scala:1050:{23,31,36}]
wire _csr_io_tval_msb_T_3 = _rob_io_com_xcpt_bits_badvaddr[39]; // @[core.scala:143:32, :1050:48]
wire _csr_io_tval_msb_T_4 = _rob_io_com_xcpt_bits_badvaddr[38]; // @[core.scala:143:32, :1050:64]
wire _csr_io_tval_msb_T_5 = ~_csr_io_tval_msb_T_4; // @[core.scala:1050:{61,64}]
wire csr_io_tval_msb = _csr_io_tval_msb_T_2 ? _csr_io_tval_msb_T_3 : _csr_io_tval_msb_T_5; // @[core.scala:1050:{20,31,48,61}]
wire [38:0] _csr_io_tval_T = _rob_io_com_xcpt_bits_badvaddr[38:0]; // @[core.scala:143:32, :1051:18]
wire [39:0] _csr_io_tval_T_1 = {csr_io_tval_msb, _csr_io_tval_T}; // @[core.scala:1050:20, :1051:{10,18}]
reg [39:0] csr_io_tval_REG; // @[core.scala:1040:12]
wire [39:0] _csr_io_tval_T_2 = tval_valid ? csr_io_tval_REG : 40'h0; // @[core.scala:1026:37, :1039:21, :1040:12]
assign bypasses_0_bits_data = _alu_exe_unit_io_bypass_0_bits_data[63:0]; // @[execution-units.scala:119:32]
assign bypasses_1_bits_data = _alu_exe_unit_io_bypass_1_bits_data[63:0]; // @[execution-units.scala:119:32]
assign bypasses_2_bits_data = _alu_exe_unit_io_bypass_2_bits_data[63:0]; // @[execution-units.scala:119:32]
assign pred_bypasses_0_bits_data = _alu_exe_unit_io_bypass_0_bits_data[0]; // @[execution-units.scala:119:32]
assign pred_bypasses_1_bits_data = _alu_exe_unit_io_bypass_1_bits_data[0]; // @[execution-units.scala:119:32]
assign pred_bypasses_2_bits_data = _alu_exe_unit_io_bypass_2_bits_data[0]; // @[execution-units.scala:119:32]
reg io_lsu_exception_REG; // @[core.scala:1124:30]
assign io_lsu_exception_0 = io_lsu_exception_REG; // @[core.scala:51:7, :1124:30]
wire _iregfile_io_write_ports_0_wport_valid_T_1; // @[regfile.scala:57:35]
wire [5:0] iregfile_io_write_ports_0_wport_bits_addr; // @[regfile.scala:55:22]
wire [63:0] iregfile_io_write_ports_0_wport_bits_data; // @[regfile.scala:55:22]
wire iregfile_io_write_ports_0_wport_valid; // @[regfile.scala:55:22]
assign _iregfile_io_write_ports_0_wport_valid_T_1 = _ll_wbarb_io_out_valid & _iregfile_io_write_ports_0_wport_valid_T; // @[regfile.scala:57:{35,61}]
assign iregfile_io_write_ports_0_wport_valid = _iregfile_io_write_ports_0_wport_valid_T_1; // @[regfile.scala:55:22, :57:35]
wire wbReadsCSR = |_alu_exe_unit_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire _iregfile_io_write_ports_1_valid_T_1 = _alu_exe_unit_io_iresp_valid & _iregfile_io_write_ports_1_valid_T; // @[execution-units.scala:119:32]
wire _iregfile_io_write_ports_1_valid_T_3 = _iregfile_io_write_ports_1_valid_T_1 & _iregfile_io_write_ports_1_valid_T_2; // @[core.scala:1160:{22,48,77}]
wire [64:0] _GEN_25 = {1'h0, _csr_io_rw_rdata}; // @[core.scala:271:19, :1167:56]
wire [64:0] _iregfile_io_write_ports_1_bits_data_T = wbReadsCSR ? _GEN_25 : _alu_exe_unit_io_iresp_bits_data; // @[execution-units.scala:119:32]
wire _rob_io_wb_resps_0_valid_T = ~_ll_wbarb_io_out_bits_uop_is_amo; // @[core.scala:132:32, :1217:78]
wire _rob_io_wb_resps_0_valid_T_1 = _ll_wbarb_io_out_bits_uop_uses_stq & _rob_io_wb_resps_0_valid_T; // @[core.scala:132:32, :1217:{75,78}]
wire _rob_io_wb_resps_0_valid_T_2 = ~_rob_io_wb_resps_0_valid_T_1; // @[core.scala:1217:{57,75}]
wire _rob_io_wb_resps_0_valid_T_3 = _ll_wbarb_io_out_valid & _rob_io_wb_resps_0_valid_T_2; // @[core.scala:132:32, :1217:{54,57}]
wire _rob_io_debug_wb_valids_0_T = _ll_wbarb_io_out_bits_uop_dst_rtype != 2'h2; // @[core.scala:132:32, :1219:74]
wire _rob_io_debug_wb_valids_0_T_1 = _ll_wbarb_io_out_valid & _rob_io_debug_wb_valids_0_T; // @[core.scala:132:32, :1219:{54,74}]
wire _rob_io_wb_resps_1_valid_T = ~_alu_exe_unit_io_iresp_bits_uop_is_amo; // @[execution-units.scala:119:32]
wire _rob_io_wb_resps_1_valid_T_1 = _alu_exe_unit_io_iresp_bits_uop_uses_stq & _rob_io_wb_resps_1_valid_T; // @[execution-units.scala:119:32]
wire _rob_io_wb_resps_1_valid_T_2 = ~_rob_io_wb_resps_1_valid_T_1; // @[core.scala:1238:{51,69}]
wire _rob_io_wb_resps_1_valid_T_3 = _alu_exe_unit_io_iresp_valid & _rob_io_wb_resps_1_valid_T_2; // @[execution-units.scala:119:32]
wire _rob_io_debug_wb_valids_1_T_1 = _alu_exe_unit_io_iresp_valid & _rob_io_debug_wb_valids_1_T; // @[execution-units.scala:119:32]
wire _rob_io_debug_wb_valids_1_T_3 = _rob_io_debug_wb_valids_1_T_1 & _rob_io_debug_wb_valids_1_T_2; // @[core.scala:1240:{49,66,86}]
wire _rob_io_debug_wb_wdata_1_T = |_alu_exe_unit_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire [64:0] _rob_io_debug_wb_wdata_1_T_1 = _rob_io_debug_wb_wdata_1_T ? _GEN_25 : _alu_exe_unit_io_iresp_bits_data; // @[execution-units.scala:119:32]
reg REG_5; // @[core.scala:1306:45]
reg memExeUnit_io_req_bits_kill_REG; // @[core.scala:1310:45]
reg alu_exe_unit_io_req_bits_kill_REG; // @[core.scala:1310:45]
reg [4:0] small_0; // @[Counters.scala:45:41]
wire [5:0] nextSmall = {1'h0, small_0} + 6'h1; // @[Counters.scala:45:41, :46:33]
reg [26:0] large_0; // @[Counters.scala:50:31]
wire _large_T = nextSmall[5]; // @[Counters.scala:46:33, :51:20]
wire _large_T_2 = _large_T; // @[Counters.scala:51:{20,33}]
wire [27:0] _large_r_T = {1'h0, large_0} + 28'h1; // @[Counters.scala:50:31, :51:55]
wire [26:0] _large_r_T_1 = _large_r_T[26:0]; // @[Counters.scala:51:55]
wire [31:0] value = {large_0, small_0}; // @[Counters.scala:45:41, :50:31, :55:30]
|
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
|
module PE_374( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_118 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
|
module PE_300( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_44 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util._
import FUConstants._
/**
* IO bundle to interact with Issue slot
*
* @param numWakeupPorts number of wakeup ports for the slot
*/
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val request_hp = Output(Bool())
val grant = Input(Bool())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted.
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz))))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W))))
val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue.
val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued.
val debug = {
val result = new Bundle {
val p1 = Bool()
val p2 = Bool()
val p3 = Bool()
val ppred = Bool()
val state = UInt(width=2.W)
}
Output(result)
}
}
/**
* Single issue slot. Holds a uop within the issue queue
*
* @param numWakeupPorts number of wakeup ports
*/
class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters)
extends BoomModule
with IssueUnitConstants
{
val io = IO(new IssueSlotIO(numWakeupPorts))
// slot invalid?
// slot is valid, holding 1 uop
// slot is valid, holds 2 uops (like a store)
def is_invalid = state === s_invalid
def is_valid = state =/= s_invalid
val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot)
val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot)
val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val state = RegInit(s_invalid)
val p1 = RegInit(false.B)
val p2 = RegInit(false.B)
val p3 = RegInit(false.B)
val ppred = RegInit(false.B)
// Poison if woken up by speculative load.
// Poison lasts 1 cycle (as ldMiss will come on the next cycle).
// SO if poisoned is true, set it to false!
val p1_poisoned = RegInit(false.B)
val p2_poisoned = RegInit(false.B)
p1_poisoned := false.B
p2_poisoned := false.B
val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
val slot_uop = RegInit(NullMicroOp)
val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
//-----------------------------------------------------------------------------
// next slot state computation
// compute the next state for THIS entry slot (in a collasping queue, the
// current uop may get moved elsewhere, and a new uop can enter
when (io.kill) {
state := s_invalid
} .elsewhen (io.in_uop.valid) {
state := io.in_uop.bits.iw_state
} .elsewhen (io.clear) {
state := s_invalid
} .otherwise {
state := next_state
}
//-----------------------------------------------------------------------------
// "update" state
// compute the next state for the micro-op in this slot. This micro-op may
// be moved elsewhere, so the "next_state" travels with it.
// defaults
next_state := state
next_uopc := slot_uop.uopc
next_lrs1_rtype := slot_uop.lrs1_rtype
next_lrs2_rtype := slot_uop.lrs2_rtype
when (io.kill) {
next_state := s_invalid
} .elsewhen ((io.grant && (state === s_valid_1)) ||
(io.grant && (state === s_valid_2) && p1 && p2 && ppred)) {
// try to issue this uop.
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_invalid
}
} .elsewhen (io.grant && (state === s_valid_2)) {
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_valid_1
when (p1) {
slot_uop.uopc := uopSTD
next_uopc := uopSTD
slot_uop.lrs1_rtype := RT_X
next_lrs1_rtype := RT_X
} .otherwise {
slot_uop.lrs2_rtype := RT_X
next_lrs2_rtype := RT_X
}
}
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.")
}
// Wakeup Compare Logic
// these signals are the "next_p*" for the current slot's micro-op.
// they are important for shifting the current slot_uop up to an other entry.
val next_p1 = WireInit(p1)
val next_p2 = WireInit(p2)
val next_p3 = WireInit(p3)
val next_ppred = WireInit(ppred)
when (io.in_uop.valid) {
p1 := !(io.in_uop.bits.prs1_busy)
p2 := !(io.in_uop.bits.prs2_busy)
p3 := !(io.in_uop.bits.prs3_busy)
ppred := !(io.in_uop.bits.ppred_busy)
}
when (io.ldspec_miss && next_p1_poisoned) {
assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!")
p1 := false.B
}
when (io.ldspec_miss && next_p2_poisoned) {
assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!")
p2 := false.B
}
for (i <- 0 until numWakeupPorts) {
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs1)) {
p1 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs2)) {
p2 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs3)) {
p3 := true.B
}
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) {
ppred := true.B
}
for (w <- 0 until memWidth) {
assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),
"Loads to x0 should never speculatively wakeup other instructions")
}
// TODO disable if FP IQ.
for (w <- 0 until memWidth) {
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs1 &&
next_uop.lrs1_rtype === RT_FIX) {
p1 := true.B
p1_poisoned := true.B
assert (!next_p1_poisoned)
}
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs2 &&
next_uop.lrs2_rtype === RT_FIX) {
p2 := true.B
p2_poisoned := true.B
assert (!next_p2_poisoned)
}
}
// Handle branch misspeculations
val next_br_mask = GetNewBrMask(io.brupdate, slot_uop)
// was this micro-op killed by a branch? if yes, we can't let it be valid if
// we compact it into an other entry
when (IsKilledByBranch(io.brupdate, slot_uop)) {
next_state := s_invalid
}
when (!io.in_uop.valid) {
slot_uop.br_mask := next_br_mask
}
//-------------------------------------------------------------
// Request Logic
io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill
val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr
io.request_hp := io.request && high_priority
when (state === s_valid_1) {
io.request := p1 && p2 && p3 && ppred && !io.kill
} .elsewhen (state === s_valid_2) {
io.request := (p1 || p2) && ppred && !io.kill
} .otherwise {
io.request := false.B
}
//assign outputs
io.valid := is_valid
io.uop := slot_uop
io.uop.iw_p1_poisoned := p1_poisoned
io.uop.iw_p2_poisoned := p2_poisoned
// micro-op will vacate due to grant.
val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred)
val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned)
io.will_be_valid := is_valid && !(may_vacate && !squash_grant)
io.out_uop := slot_uop
io.out_uop.iw_state := next_state
io.out_uop.uopc := next_uopc
io.out_uop.lrs1_rtype := next_lrs1_rtype
io.out_uop.lrs2_rtype := next_lrs2_rtype
io.out_uop.br_mask := next_br_mask
io.out_uop.prs1_busy := !p1
io.out_uop.prs2_busy := !p2
io.out_uop.prs3_busy := !p3
io.out_uop.ppred_busy := !ppred
io.out_uop.iw_p1_poisoned := p1_poisoned
io.out_uop.iw_p2_poisoned := p2_poisoned
when (state === s_valid_2) {
when (p1 && p2 && ppred) {
; // send out the entire instruction as one uop
} .elsewhen (p1 && ppred) {
io.uop.uopc := slot_uop.uopc
io.uop.lrs2_rtype := RT_X
} .elsewhen (p2 && ppred) {
io.uop.uopc := uopSTD
io.uop.lrs1_rtype := RT_X
}
}
// debug outputs
io.debug.p1 := p1
io.debug.p2 := p2
io.debug.p3 := p3
io.debug.ppred := ppred
io.debug.state := state
}
|
module IssueSlot_131( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11]
wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File INToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val signedIn = Input(Bool())
val in = Input(Bits(intWidth.W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val intAsRawFloat = rawFloatFromIN(io.signedIn, io.in);
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
intAsRawFloat.expWidth,
intWidth,
expWidth,
sigWidth,
flRoundOpt_sigMSBitAlwaysZero | flRoundOpt_neverUnderflows
))
roundAnyRawFNToRecFN.io.invalidExc := false.B
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := intAsRawFloat
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
File rawFloatFromIN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
object rawFloatFromIN
{
def apply(signedIn: Bool, in: Bits): RawFloat =
{
val expWidth = log2Up(in.getWidth) + 1
//*** CHANGE THIS; CAN BE VERY LARGE:
val extIntWidth = 1<<(expWidth - 1)
val sign = signedIn && in(in.getWidth - 1)
val absIn = Mux(sign, -in.asUInt, in.asUInt)
val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0)
val adjustedNormDist = countLeadingZeros(extAbsIn)
val sig =
(extAbsIn<<adjustedNormDist)(
extIntWidth - 1, extIntWidth - in.getWidth)
val out = Wire(new RawFloat(expWidth, in.getWidth))
out.isNaN := false.B
out.isInf := false.B
out.isZero := ! sig(in.getWidth - 1)
out.sign := sign
out.sExp := (2.U(2.W) ## ~adjustedNormDist(expWidth - 2, 0)).zext
out.sig := sig
out
}
}
|
module INToRecFN_i64_e5_s11_7( // @[INToRecFN.scala:43:7]
input io_signedIn, // @[INToRecFN.scala:46:16]
input [63:0] io_in, // @[INToRecFN.scala:46:16]
input [2:0] io_roundingMode, // @[INToRecFN.scala:46:16]
output [16:0] io_out, // @[INToRecFN.scala:46:16]
output [4:0] io_exceptionFlags // @[INToRecFN.scala:46:16]
);
wire io_signedIn_0 = io_signedIn; // @[INToRecFN.scala:43:7]
wire [63:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[INToRecFN.scala:43:7]
wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7]
wire [16:0] io_out_0; // @[INToRecFN.scala:43:7]
wire [4:0] io_exceptionFlags_0; // @[INToRecFN.scala:43:7]
wire _intAsRawFloat_sign_T = io_in_0[63]; // @[rawFloatFromIN.scala:51:34]
wire intAsRawFloat_sign = io_signedIn_0 & _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}]
wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23]
wire [64:0] _intAsRawFloat_absIn_T = 65'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31]
wire [63:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[63:0]; // @[rawFloatFromIN.scala:52:31]
wire [63:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}]
wire [127:0] _intAsRawFloat_extAbsIn_T = {64'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44]
wire [63:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[63:0]; // @[rawFloatFromIN.scala:53:{44,53}]
wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_32 = intAsRawFloat_extAbsIn[32]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_33 = intAsRawFloat_extAbsIn[33]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_34 = intAsRawFloat_extAbsIn[34]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_35 = intAsRawFloat_extAbsIn[35]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_36 = intAsRawFloat_extAbsIn[36]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_37 = intAsRawFloat_extAbsIn[37]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_38 = intAsRawFloat_extAbsIn[38]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_39 = intAsRawFloat_extAbsIn[39]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_40 = intAsRawFloat_extAbsIn[40]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_41 = intAsRawFloat_extAbsIn[41]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_42 = intAsRawFloat_extAbsIn[42]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_43 = intAsRawFloat_extAbsIn[43]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_44 = intAsRawFloat_extAbsIn[44]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_45 = intAsRawFloat_extAbsIn[45]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_46 = intAsRawFloat_extAbsIn[46]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_47 = intAsRawFloat_extAbsIn[47]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_48 = intAsRawFloat_extAbsIn[48]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_49 = intAsRawFloat_extAbsIn[49]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_50 = intAsRawFloat_extAbsIn[50]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_51 = intAsRawFloat_extAbsIn[51]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_52 = intAsRawFloat_extAbsIn[52]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_53 = intAsRawFloat_extAbsIn[53]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_54 = intAsRawFloat_extAbsIn[54]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_55 = intAsRawFloat_extAbsIn[55]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_56 = intAsRawFloat_extAbsIn[56]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_57 = intAsRawFloat_extAbsIn[57]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_58 = intAsRawFloat_extAbsIn[58]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_59 = intAsRawFloat_extAbsIn[59]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_60 = intAsRawFloat_extAbsIn[60]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_61 = intAsRawFloat_extAbsIn[61]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_62 = intAsRawFloat_extAbsIn[62]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_63 = intAsRawFloat_extAbsIn[63]; // @[rawFloatFromIN.scala:53:53]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_64 = {5'h1F, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_65 = _intAsRawFloat_adjustedNormDist_T_2 ? 6'h3D : _intAsRawFloat_adjustedNormDist_T_64; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_66 = _intAsRawFloat_adjustedNormDist_T_3 ? 6'h3C : _intAsRawFloat_adjustedNormDist_T_65; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_67 = _intAsRawFloat_adjustedNormDist_T_4 ? 6'h3B : _intAsRawFloat_adjustedNormDist_T_66; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_68 = _intAsRawFloat_adjustedNormDist_T_5 ? 6'h3A : _intAsRawFloat_adjustedNormDist_T_67; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_69 = _intAsRawFloat_adjustedNormDist_T_6 ? 6'h39 : _intAsRawFloat_adjustedNormDist_T_68; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_70 = _intAsRawFloat_adjustedNormDist_T_7 ? 6'h38 : _intAsRawFloat_adjustedNormDist_T_69; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_71 = _intAsRawFloat_adjustedNormDist_T_8 ? 6'h37 : _intAsRawFloat_adjustedNormDist_T_70; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_72 = _intAsRawFloat_adjustedNormDist_T_9 ? 6'h36 : _intAsRawFloat_adjustedNormDist_T_71; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_73 = _intAsRawFloat_adjustedNormDist_T_10 ? 6'h35 : _intAsRawFloat_adjustedNormDist_T_72; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_74 = _intAsRawFloat_adjustedNormDist_T_11 ? 6'h34 : _intAsRawFloat_adjustedNormDist_T_73; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_75 = _intAsRawFloat_adjustedNormDist_T_12 ? 6'h33 : _intAsRawFloat_adjustedNormDist_T_74; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_76 = _intAsRawFloat_adjustedNormDist_T_13 ? 6'h32 : _intAsRawFloat_adjustedNormDist_T_75; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_77 = _intAsRawFloat_adjustedNormDist_T_14 ? 6'h31 : _intAsRawFloat_adjustedNormDist_T_76; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_78 = _intAsRawFloat_adjustedNormDist_T_15 ? 6'h30 : _intAsRawFloat_adjustedNormDist_T_77; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_79 = _intAsRawFloat_adjustedNormDist_T_16 ? 6'h2F : _intAsRawFloat_adjustedNormDist_T_78; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_80 = _intAsRawFloat_adjustedNormDist_T_17 ? 6'h2E : _intAsRawFloat_adjustedNormDist_T_79; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_81 = _intAsRawFloat_adjustedNormDist_T_18 ? 6'h2D : _intAsRawFloat_adjustedNormDist_T_80; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_82 = _intAsRawFloat_adjustedNormDist_T_19 ? 6'h2C : _intAsRawFloat_adjustedNormDist_T_81; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_83 = _intAsRawFloat_adjustedNormDist_T_20 ? 6'h2B : _intAsRawFloat_adjustedNormDist_T_82; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_84 = _intAsRawFloat_adjustedNormDist_T_21 ? 6'h2A : _intAsRawFloat_adjustedNormDist_T_83; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_85 = _intAsRawFloat_adjustedNormDist_T_22 ? 6'h29 : _intAsRawFloat_adjustedNormDist_T_84; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_86 = _intAsRawFloat_adjustedNormDist_T_23 ? 6'h28 : _intAsRawFloat_adjustedNormDist_T_85; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_87 = _intAsRawFloat_adjustedNormDist_T_24 ? 6'h27 : _intAsRawFloat_adjustedNormDist_T_86; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_88 = _intAsRawFloat_adjustedNormDist_T_25 ? 6'h26 : _intAsRawFloat_adjustedNormDist_T_87; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_89 = _intAsRawFloat_adjustedNormDist_T_26 ? 6'h25 : _intAsRawFloat_adjustedNormDist_T_88; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_90 = _intAsRawFloat_adjustedNormDist_T_27 ? 6'h24 : _intAsRawFloat_adjustedNormDist_T_89; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_91 = _intAsRawFloat_adjustedNormDist_T_28 ? 6'h23 : _intAsRawFloat_adjustedNormDist_T_90; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_92 = _intAsRawFloat_adjustedNormDist_T_29 ? 6'h22 : _intAsRawFloat_adjustedNormDist_T_91; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_93 = _intAsRawFloat_adjustedNormDist_T_30 ? 6'h21 : _intAsRawFloat_adjustedNormDist_T_92; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_94 = _intAsRawFloat_adjustedNormDist_T_31 ? 6'h20 : _intAsRawFloat_adjustedNormDist_T_93; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_95 = _intAsRawFloat_adjustedNormDist_T_32 ? 6'h1F : _intAsRawFloat_adjustedNormDist_T_94; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_96 = _intAsRawFloat_adjustedNormDist_T_33 ? 6'h1E : _intAsRawFloat_adjustedNormDist_T_95; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_97 = _intAsRawFloat_adjustedNormDist_T_34 ? 6'h1D : _intAsRawFloat_adjustedNormDist_T_96; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_98 = _intAsRawFloat_adjustedNormDist_T_35 ? 6'h1C : _intAsRawFloat_adjustedNormDist_T_97; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_99 = _intAsRawFloat_adjustedNormDist_T_36 ? 6'h1B : _intAsRawFloat_adjustedNormDist_T_98; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_100 = _intAsRawFloat_adjustedNormDist_T_37 ? 6'h1A : _intAsRawFloat_adjustedNormDist_T_99; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_101 = _intAsRawFloat_adjustedNormDist_T_38 ? 6'h19 : _intAsRawFloat_adjustedNormDist_T_100; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_102 = _intAsRawFloat_adjustedNormDist_T_39 ? 6'h18 : _intAsRawFloat_adjustedNormDist_T_101; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_103 = _intAsRawFloat_adjustedNormDist_T_40 ? 6'h17 : _intAsRawFloat_adjustedNormDist_T_102; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_104 = _intAsRawFloat_adjustedNormDist_T_41 ? 6'h16 : _intAsRawFloat_adjustedNormDist_T_103; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_105 = _intAsRawFloat_adjustedNormDist_T_42 ? 6'h15 : _intAsRawFloat_adjustedNormDist_T_104; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_106 = _intAsRawFloat_adjustedNormDist_T_43 ? 6'h14 : _intAsRawFloat_adjustedNormDist_T_105; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_107 = _intAsRawFloat_adjustedNormDist_T_44 ? 6'h13 : _intAsRawFloat_adjustedNormDist_T_106; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_108 = _intAsRawFloat_adjustedNormDist_T_45 ? 6'h12 : _intAsRawFloat_adjustedNormDist_T_107; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_109 = _intAsRawFloat_adjustedNormDist_T_46 ? 6'h11 : _intAsRawFloat_adjustedNormDist_T_108; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_110 = _intAsRawFloat_adjustedNormDist_T_47 ? 6'h10 : _intAsRawFloat_adjustedNormDist_T_109; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_111 = _intAsRawFloat_adjustedNormDist_T_48 ? 6'hF : _intAsRawFloat_adjustedNormDist_T_110; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_112 = _intAsRawFloat_adjustedNormDist_T_49 ? 6'hE : _intAsRawFloat_adjustedNormDist_T_111; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_113 = _intAsRawFloat_adjustedNormDist_T_50 ? 6'hD : _intAsRawFloat_adjustedNormDist_T_112; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_114 = _intAsRawFloat_adjustedNormDist_T_51 ? 6'hC : _intAsRawFloat_adjustedNormDist_T_113; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_115 = _intAsRawFloat_adjustedNormDist_T_52 ? 6'hB : _intAsRawFloat_adjustedNormDist_T_114; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_116 = _intAsRawFloat_adjustedNormDist_T_53 ? 6'hA : _intAsRawFloat_adjustedNormDist_T_115; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_117 = _intAsRawFloat_adjustedNormDist_T_54 ? 6'h9 : _intAsRawFloat_adjustedNormDist_T_116; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_118 = _intAsRawFloat_adjustedNormDist_T_55 ? 6'h8 : _intAsRawFloat_adjustedNormDist_T_117; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_119 = _intAsRawFloat_adjustedNormDist_T_56 ? 6'h7 : _intAsRawFloat_adjustedNormDist_T_118; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_120 = _intAsRawFloat_adjustedNormDist_T_57 ? 6'h6 : _intAsRawFloat_adjustedNormDist_T_119; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_121 = _intAsRawFloat_adjustedNormDist_T_58 ? 6'h5 : _intAsRawFloat_adjustedNormDist_T_120; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_122 = _intAsRawFloat_adjustedNormDist_T_59 ? 6'h4 : _intAsRawFloat_adjustedNormDist_T_121; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_123 = _intAsRawFloat_adjustedNormDist_T_60 ? 6'h3 : _intAsRawFloat_adjustedNormDist_T_122; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_124 = _intAsRawFloat_adjustedNormDist_T_61 ? 6'h2 : _intAsRawFloat_adjustedNormDist_T_123; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_125 = _intAsRawFloat_adjustedNormDist_T_62 ? 6'h1 : _intAsRawFloat_adjustedNormDist_T_124; // @[Mux.scala:50:70]
wire [5:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_63 ? 6'h0 : _intAsRawFloat_adjustedNormDist_T_125; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
wire [126:0] _intAsRawFloat_sig_T = {63'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
wire [63:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[63:0]; // @[rawFloatFromIN.scala:56:{22,41}]
wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23]
wire [8:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72]
wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23]
wire [8:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23]
wire [64:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23]
wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[63]; // @[rawFloatFromIN.scala:56:41, :62:28]
assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}]
assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23]
wire [5:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}]
wire [7:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}]
assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}]
assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72]
assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20]
RoundAnyRawFNToRecFN_ie7_is64_oe5_os11_7 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15]
.io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23]
.io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23]
.io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23]
.io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23]
.io_roundingMode (io_roundingMode_0), // @[INToRecFN.scala:43:7]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[INToRecFN.scala:60:15]
assign io_out = io_out_0; // @[INToRecFN.scala:43:7]
assign io_exceptionFlags = io_exceptionFlags_0; // @[INToRecFN.scala:43:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
|
module AsyncResetSynchronizerShiftReg_w4_d3_i0_26( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_246 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_247 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_248 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_249 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLMonitor_64( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File SwitchAllocator.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])
(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val tail = Bool()
}
class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module {
val io = IO(new Bundle {
val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams))))
val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val chosen_oh = Vec(outN, Output(UInt(inN.W)))
})
val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) }
val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_|_))
val mask = RegInit(0.U(inN.W))
val choices = Wire(Vec(outN, UInt(inN.W)))
var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask))
for (i <- 0 until outN) {
choices(i) := sel | (sel >> inN)
sel = PriorityEncoderOH(unassigned & ~choices(i))
}
io.in.foreach(_.ready := false.B)
var chosens = 0.U(inN.W)
val in_tails = Cat(io.in.map(_.bits.tail).reverse)
for (i <- 0 until outN) {
val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse)
val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i))
io.chosen_oh(i) := chosen
io.out(i).valid := (in_valids & chosen).orR
io.out(i).bits := Mux1H(chosen, io.in.map(_.bits))
for (j <- 0 until inN) {
when (chosen(j) && io.out(i).ready) {
io.in(j).ready := true.B
}
}
chosens = chosens | chosen
when (io.out(i).fire) {
lock(i) := chosen & ~in_tails
}
}
when (io.out(0).fire) {
mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_|_)
} .otherwise {
mask := Mux(~mask === 0.U, 0.U, (mask << 1) | 1.U(1.W))
}
}
class SwitchAllocator(
val routerParams: RouterParams,
val inParams: Seq[ChannelParams],
val outParams: Seq[ChannelParams],
val ingressParams: Seq[IngressChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module
with HasRouterParams
with HasRouterInputParams
with HasRouterOutputParams {
val io = IO(new Bundle {
val req = MixedVec(allInParams.map(u =>
Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams))))))
val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))})
val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup,
MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) })
})
val nInputChannels = allInParams.map(_.nVirtualChannels).sum
val arbs = allOutParams.map { oP => Module(new SwitchArbiter(
allInParams.map(_.destSpeedup).reduce(_+_),
oP.srcSpeedup,
outParams,
egressParams
))}
arbs.foreach(_.io.out.foreach(_.ready := true.B))
var idx = 0
io.req.foreach(_.foreach { o =>
val fires = Wire(Vec(arbs.size, Bool()))
arbs.zipWithIndex.foreach { case (a,i) =>
a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_||_)
a.io.in(idx).bits := o.bits
fires(i) := a.io.in(idx).fire
}
o.ready := fires.reduce(_||_)
idx += 1
})
for (i <- 0 until nAllOutputs) {
for (j <- 0 until allOutParams(i).srcSpeedup) {
idx = 0
for (m <- 0 until nAllInputs) {
for (n <- 0 until allInParams(m).destSpeedup) {
io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid
idx += 1
}
}
}
}
io.credit_alloc.foreach(_.foreach(_.alloc := false.B))
io.credit_alloc.foreach(_.foreach(_.tail := false.B))
(arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) =>
for (j <- 0 until i.size) {
for (k <- 0 until a.io.out.size) {
when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) {
i(j).alloc := true.B
i(j).tail := a.io.out(k).bits.tail
}
}
}
}
}
|
module SwitchArbiter_1( // @[SwitchAllocator.scala:17:7]
input clock, // @[SwitchAllocator.scala:17:7]
input reset, // @[SwitchAllocator.scala:17:7]
output io_in_0_ready, // @[SwitchAllocator.scala:18:14]
input io_in_0_valid, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_1_ready, // @[SwitchAllocator.scala:18:14]
input io_in_1_valid, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_2_ready, // @[SwitchAllocator.scala:18:14]
input io_in_2_valid, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_3_ready, // @[SwitchAllocator.scala:18:14]
input io_in_3_valid, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_out_0_valid, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14]
output [3:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14]
);
reg [3:0] lock_0; // @[SwitchAllocator.scala:24:38]
wire [3:0] unassigned = {io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}]
reg [3:0] mask; // @[SwitchAllocator.scala:27:21]
wire [3:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}]
wire [7:0] sel = _sel_T_1[0] ? 8'h1 : _sel_T_1[1] ? 8'h2 : _sel_T_1[2] ? 8'h4 : _sel_T_1[3] ? 8'h8 : unassigned[0] ? 8'h10 : unassigned[1] ? 8'h20 : unassigned[2] ? 8'h40 : {unassigned[3], 7'h0}; // @[OneHot.scala:85:71]
wire [3:0] in_valids = {io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24]
wire [3:0] chosen = (|(in_valids & lock_0)) ? lock_0 : sel[3:0] | sel[7:4]; // @[Mux.scala:50:70]
wire [3:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35]
wire [2:0] _GEN = chosen[2:0] | chosen[3:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [1:0] _GEN_0 = _GEN[1:0] | chosen[3:2]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
always @(posedge clock) begin // @[SwitchAllocator.scala:17:7]
if (reset) begin // @[SwitchAllocator.scala:17:7]
lock_0 <= 4'h0; // @[SwitchAllocator.scala:24:38]
mask <= 4'h0; // @[SwitchAllocator.scala:27:21]
end
else begin // @[SwitchAllocator.scala:17:7]
if (|_io_out_0_valid_T) // @[SwitchAllocator.scala:44:{35,45}]
lock_0 <= chosen & ~{io_in_3_bits_tail, io_in_2_bits_tail, io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}]
mask <= (|_io_out_0_valid_T) ? {chosen[3], _GEN[2], _GEN_0[1], _GEN_0[0] | chosen[3]} : (&mask) ? 4'h0 : {mask[2:0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:{35,45}, :57:25, :58:{10,55,71}, :60:{10,16,23,49}]
end
always @(posedge)
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
package constellation.channel
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.util._
import constellation.noc.{HasNoCParams}
class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams {
val io = IO(new Bundle {
val in = Input(new Channel(cParam))
})
val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B }))
for (i <- 0 until cParam.srcSpeedup) {
val flit = io.in.flit(i)
when (flit.valid) {
when (flit.bits.head) {
in_flight(flit.bits.virt_channel_id) := true.B
assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken")
}
when (flit.bits.tail) {
in_flight(flit.bits.virt_channel_id) := false.B
}
}
val possibleFlows = cParam.possibleFlows
when (flit.valid && flit.bits.head) {
cParam match {
case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) =>
assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
}
}
}
File Types.scala:
package constellation.routing
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import constellation.noc.{HasNoCParams}
import constellation.channel.{Flit}
/** A representation for 1 specific virtual channel in wormhole routing
*
* @param src the source node
* @param vc ID for the virtual channel
* @param dst the destination node
* @param n_vc the number of virtual channels
*/
// BEGIN: ChannelRoutingInfo
case class ChannelRoutingInfo(
src: Int,
dst: Int,
vc: Int,
n_vc: Int
) {
// END: ChannelRoutingInfo
require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this")
require (!(src == -1 && dst == -1), s"Illegal $this")
require (vc < n_vc, s"Illegal $this")
val isIngress = src == -1
val isEgress = dst == -1
}
/** Represents the properties of a packet that are relevant for routing
* ingressId and egressId uniquely identify a flow, but vnet and dst are used here
* to simplify the implementation of routingrelations
*
* @param ingressId packet's source ingress point
* @param egressId packet's destination egress point
* @param vNet virtual subnetwork identifier
* @param dst packet's destination node ID
*/
// BEGIN: FlowRoutingInfo
case class FlowRoutingInfo(
ingressId: Int,
egressId: Int,
vNetId: Int,
ingressNode: Int,
ingressNodeId: Int,
egressNode: Int,
egressNodeId: Int,
fifo: Boolean
) {
// END: FlowRoutingInfo
def isFlow(f: FlowRoutingBundle): Bool = {
(f.ingress_node === ingressNode.U &&
f.egress_node === egressNode.U &&
f.ingress_node_id === ingressNodeId.U &&
f.egress_node_id === egressNodeId.U)
}
def asLiteral(b: FlowRoutingBundle): BigInt = {
Seq(
(vNetId , b.vnet_id),
(ingressNode , b.ingress_node),
(ingressNodeId , b.ingress_node_id),
(egressNode , b.egress_node),
(egressNodeId , b.egress_node_id)
).foldLeft(0)((l, t) => {
(l << t._2.getWidth) | t._1
})
}
}
class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams {
// Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination
// This simplifies the routing tables
val vnet_id = UInt(log2Ceil(nVirtualNetworks).W)
val ingress_node = UInt(log2Ceil(nNodes).W)
val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W)
val egress_node = UInt(log2Ceil(nNodes).W)
val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W)
}
|
module NoCMonitor_29( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [5:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [5:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26]
reg in_flight_8; // @[Monitor.scala:16:26]
reg in_flight_9; // @[Monitor.scala:16:26]
reg in_flight_10; // @[Monitor.scala:16:26]
reg in_flight_11; // @[Monitor.scala:16:26]
reg in_flight_12; // @[Monitor.scala:16:26]
reg in_flight_13; // @[Monitor.scala:16:26]
reg in_flight_14; // @[Monitor.scala:16:26]
reg in_flight_15; // @[Monitor.scala:16:26]
reg in_flight_16; // @[Monitor.scala:16:26]
reg in_flight_17; // @[Monitor.scala:16:26]
reg in_flight_18; // @[Monitor.scala:16:26]
reg in_flight_19; // @[Monitor.scala:16:26]
reg in_flight_20; // @[Monitor.scala:16:26]
reg in_flight_21; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 5'h0; // @[Monitor.scala:21:46]
wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 5'h1; // @[Monitor.scala:21:46]
wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 5'h4; // @[Monitor.scala:21:46]
wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 5'h5; // @[Monitor.scala:21:46]
wire _GEN_3 = io_in_flit_0_bits_virt_channel_id == 5'h6; // @[Monitor.scala:21:46]
wire _GEN_4 = io_in_flit_0_bits_virt_channel_id == 5'h7; // @[Monitor.scala:21:46]
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
|
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_282( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge)
|
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
|
module Tile_117( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_373 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
|
module AsyncResetSynchronizerShiftReg_w1_d3_i0_91( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_147 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File Logger.scala:
// See LICENSE for license details
package roccaccutils.logger
import chisel3._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.diplomacy.{ValName}
trait Logger {
// --------------------------
// MUST BE DEFINED BY CHILD
// --------------------------
def logInfoImplPrintWrapper(printf: chisel3.printf.Printf)(implicit p: Parameters = Parameters.empty): chisel3.printf.Printf
def logCriticalImplPrintWrapper(printf: chisel3.printf.Printf)(implicit p: Parameters = Parameters.empty): chisel3.printf.Printf
// --------------------------
def trimValName()(implicit valName: ValName): String = {
// TODO: For now don't trim since it can have different pre/post-fixes
//val trimAmt = if (valName.value.startsWith("<local")) 6 else 1
//println(s"Got this: ${valName.value}")
//"<" + valName.value.substring(trimAmt, valName.value.length)
valName.value
}
def createPrefix(typ: String)(implicit valName: ValName, withMod: Boolean, prefix: String): String = {
val s = Seq(s"${typ}", "%d") ++ (if (withMod) Seq(trimValName()) else Seq.empty) ++ (if (prefix != "") Seq(prefix) else Seq.empty)
":" + s.mkString(":") + ": "
}
def createFmtAndArgs(typ: String, format: String, args: Bits*)(implicit valName: ValName, withMod: Boolean, prefix: String): (String, Seq[Bits]) = {
val loginfo_cycles = RegInit(0.U(64.W))
loginfo_cycles := loginfo_cycles + 1.U
val allargs = Seq(loginfo_cycles) ++ args
val allfmt = createPrefix(typ) + format
(allfmt, allargs)
}
def logInfoImpl(format: String, args: Bits*)(implicit p: Parameters = Parameters.empty, valName: ValName, withMod: Boolean, prefix: String): Unit = {
val (allfmt, allargs) = createFmtAndArgs("INFO", format, args:_*)
logInfoImplPrintWrapper(printf(Printable.pack(allfmt, allargs:_*)))
}
def logCriticalImpl(format: String, args: Bits*)(implicit p: Parameters = Parameters.empty, valName: ValName, withMod: Boolean, prefix: String): Unit = {
val (allfmt, allargs) = createFmtAndArgs("CRIT", format, args:_*)
logCriticalImplPrintWrapper(printf(Printable.pack(allfmt, allargs:_*)))
}
// ---- USE THE FUNCTIONS BELOW ----
def logInfo(format: String, args: Bits*)(implicit p: Parameters = Parameters.empty, valName: ValName = ValName("<UnknownMod>"), prefix: String = ""): Unit = {
implicit val withMod = true
logInfoImpl(format, args:_*)
}
def logCritical(format: String, args: Bits*)(implicit p: Parameters = Parameters.empty, valName: ValName = ValName("<UnknownMod>"), prefix: String = ""): Unit = {
implicit val withMod = true
logCriticalImpl(format, args:_*)
}
def logInfoNoMod(format: String, args: Bits*)(implicit p: Parameters = Parameters.empty, valName: ValName = ValName("<UnknownMod>"), prefix: String = ""): Unit = {
implicit val withMod = false
logInfoImpl(format, args:_*)
}
def logCriticalNoMod(format: String, args: Bits*)(implicit p: Parameters = Parameters.empty, valName: ValName = ValName("<UnknownMod>"), prefix: String = ""): Unit = {
implicit val withMod = false
logCriticalImpl(format, args:_*)
}
}
// An example of a custom logger (that optionally only synthesizes critical messages):
//
// object MyLogger extends Logger {
// // just print info msgs
// def logInfoImplPrintWrapper(printf: chisel3.printf.Printf)(implicit p: Parameters = Parameters.empty): chisel3.printf.Printf = {
// printf
// }
//
// // optionally synthesize critical msgs
// def logCriticalImplPrintWrapper(printf: chisel3.printf.Printf)(implicit p: Parameters = Parameters.empty): chisel3.printf.Printf = {
// if (p(EnablePrintfSynthesis)) {
// SynthesizePrintf(printf) // function comes from midas.targetutils
// } else {
// printf
// }
// }
// }
object DefaultLogger extends Logger {
// just print info msgs
def logInfoImplPrintWrapper(printf: chisel3.printf.Printf)(implicit p: Parameters = Parameters.empty): chisel3.printf.Printf = {
printf
}
// just print critical msgs
def logCriticalImplPrintWrapper(printf: chisel3.printf.Printf)(implicit p: Parameters = Parameters.empty): chisel3.printf.Printf = {
printf
}
}
File MemWriter32.scala:
// See LICENSE for license details
package roccaccutils
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.rocket.{TLBConfig}
import freechips.rocketchip.util.{DecoupledHelper}
import freechips.rocketchip.rocket.constants.{MemoryOpConstants}
import roccaccutils.logger._
class MemWriter32(val cmd_que_depth: Int = 4, val write_cmp_flag:Boolean = true, val logger: Logger = DefaultLogger)(implicit p: Parameters, val hp: L2MemHelperParams)
extends Module
with MemoryOpConstants
with HasL2MemHelperParams {
val io = IO(new Bundle {
val memwrites_in = Flipped(Decoupled(new WriterBundle))
val l2io = new L2MemHelperBundle
val decompress_dest_info = Flipped(Decoupled(new DstInfo))
val bufs_completed = Output(UInt(64.W))
val no_writes_inflight = Output(Bool())
})
val incoming_writes_Q = Module(new Queue(new WriterBundle, cmd_que_depth))
incoming_writes_Q.io.enq <> io.memwrites_in
val decompress_dest_info_Q = Module(new Queue(new DstInfo, cmd_que_depth))
decompress_dest_info_Q.io.enq <> io.decompress_dest_info
val decompress_dest_last_fire = RegNext(decompress_dest_info_Q.io.deq.fire)
val decompress_dest_last_valid = RegNext(decompress_dest_info_Q.io.deq.valid)
val decompress_dest_printhelp = decompress_dest_info_Q.io.deq.valid && (decompress_dest_last_fire || (!decompress_dest_last_valid))
when (decompress_dest_printhelp) {
logger.logInfo("[config-memwriter] got dest info op: 0x%x, cmpflag 0x%x\n",
decompress_dest_info_Q.io.deq.bits.op,
decompress_dest_info_Q.io.deq.bits.cmpflag)
}
val buf_lens_Q = Module(new Queue(UInt(64.W), 10))
when (buf_lens_Q.io.enq.fire) {
logger.logInfo("[memwriter-serializer] enqueued buf len: %d\n", buf_lens_Q.io.enq.bits)
}
val buf_len_tracker = RegInit(0.U(64.W))
when (incoming_writes_Q.io.deq.fire) {
when (incoming_writes_Q.io.deq.bits.end_of_message) {
buf_len_tracker := 0.U
} .otherwise {
buf_len_tracker := buf_len_tracker +& incoming_writes_Q.io.deq.bits.validbytes
}
}
when (incoming_writes_Q.io.deq.fire) {
logger.logInfo("[memwriter-serializer] dat: 0x%x, bytes: 0x%x, EOM: %d\n",
incoming_writes_Q.io.deq.bits.data,
incoming_writes_Q.io.deq.bits.validbytes,
incoming_writes_Q.io.deq.bits.end_of_message
)
}
val NUM_QUEUES = 32
val QUEUE_DEPTHS = 16
val write_start_index = RegInit(0.U(log2Up(NUM_QUEUES+1).W))
val mem_resp_queues = VecInit.fill(NUM_QUEUES)(Module(new Queue(UInt(8.W), QUEUE_DEPTHS)).io)
// overridden below
for (queueno <- 0 until NUM_QUEUES) {
val q = mem_resp_queues(queueno)
q.enq.valid := false.B
q.enq.bits := 0.U
q.deq.ready := false.B
}
val len_to_write = incoming_writes_Q.io.deq.bits.validbytes
for (queueno <- 0 until NUM_QUEUES) {
mem_resp_queues((write_start_index +& queueno.U) % NUM_QUEUES.U).enq.bits := incoming_writes_Q.io.deq.bits.data >> ((len_to_write - (queueno+1).U) << 3)
}
val wrap_len_index_wide = write_start_index +& len_to_write
val wrap_len_index_end = wrap_len_index_wide % NUM_QUEUES.U
val wrapped = wrap_len_index_wide >= NUM_QUEUES.U
val all_queues_ready = mem_resp_queues.map(_.enq.ready).reduce(_ && _)
val end_of_buf = incoming_writes_Q.io.deq.bits.end_of_message
val account_for_buf_lens_Q = (!end_of_buf) || (end_of_buf && buf_lens_Q.io.enq.ready)
val input_fire_allqueues = DecoupledHelper(
incoming_writes_Q.io.deq.valid,
all_queues_ready,
account_for_buf_lens_Q
)
buf_lens_Q.io.enq.valid := input_fire_allqueues.fire(account_for_buf_lens_Q) && end_of_buf
buf_lens_Q.io.enq.bits := buf_len_tracker +& incoming_writes_Q.io.deq.bits.validbytes
incoming_writes_Q.io.deq.ready := input_fire_allqueues.fire(incoming_writes_Q.io.deq.valid)
when (input_fire_allqueues.fire()) {
write_start_index := wrap_len_index_end
}
for ( queueno <- 0 until NUM_QUEUES ) {
val use_this_queue = Mux(wrapped,
(queueno.U >= write_start_index) || (queueno.U < wrap_len_index_end),
(queueno.U >= write_start_index) && (queueno.U < wrap_len_index_end)
)
mem_resp_queues(queueno).enq.valid := input_fire_allqueues.fire() && use_this_queue
}
for ( queueno <- 0 until NUM_QUEUES ) {
when (mem_resp_queues(queueno).deq.valid) {
logger.logInfo("qi%d,0x%x\n", queueno.U, mem_resp_queues(queueno).deq.bits)
}
}
val read_start_index = RegInit(0.U(log2Up(NUM_QUEUES+1).W))
val remapVecData = Wire(Vec(NUM_QUEUES, UInt(8.W)))
val remapVecValids = Wire(Vec(NUM_QUEUES, Bool()))
val remapVecReadys = Wire(Vec(NUM_QUEUES, Bool()))
for (queueno <- 0 until NUM_QUEUES) {
val remapindex = (queueno.U +& read_start_index) % NUM_QUEUES.U
remapVecData(queueno) := mem_resp_queues(remapindex).deq.bits
remapVecValids(queueno) := mem_resp_queues(remapindex).deq.valid
mem_resp_queues(remapindex).deq.ready := remapVecReadys(queueno)
}
val count_valids = remapVecValids.map(_.asUInt).reduce(_ +& _)
val backend_bytes_written = RegInit(0.U(64.W))
val backend_next_write_addr = decompress_dest_info_Q.io.deq.bits.op + backend_bytes_written
val throttle_end = Mux(buf_lens_Q.io.deq.valid,
buf_lens_Q.io.deq.bits - backend_bytes_written,
32.U)
val throttle_end_writeable = Mux(throttle_end >= 32.U, 32.U,
Mux(throttle_end(4), 16.U,
Mux(throttle_end(3), 8.U,
Mux(throttle_end(2), 4.U,
Mux(throttle_end(1), 2.U,
Mux(throttle_end(0), 1.U,
0.U))))))
val throttle_end_writeable_log2 = Mux(throttle_end >= 32.U, 5.U,
Mux(throttle_end(4), 4.U,
Mux(throttle_end(3), 3.U,
Mux(throttle_end(2), 2.U,
Mux(throttle_end(1), 1.U,
Mux(throttle_end(0), 0.U,
0.U))))))
val ptr_align_max_bytes_writeable = Mux(backend_next_write_addr(0), 1.U,
Mux(backend_next_write_addr(1), 2.U,
Mux(backend_next_write_addr(2), 4.U,
Mux(backend_next_write_addr(3), 8.U,
Mux(backend_next_write_addr(4), 16.U,
32.U)))))
val ptr_align_max_bytes_writeable_log2 = Mux(backend_next_write_addr(0), 0.U,
Mux(backend_next_write_addr(1), 1.U,
Mux(backend_next_write_addr(2), 2.U,
Mux(backend_next_write_addr(3), 3.U,
Mux(backend_next_write_addr(4), 4.U,
5.U)))))
val count_valids_largest_aligned = Mux(count_valids(5), 32.U,
Mux(count_valids(4), 16.U,
Mux(count_valids(3), 8.U,
Mux(count_valids(2), 4.U,
Mux(count_valids(1), 2.U,
Mux(count_valids(0), 1.U,
0.U))))))
val count_valids_largest_aligned_log2 = Mux(count_valids(5), 5.U,
Mux(count_valids(4), 4.U,
Mux(count_valids(3), 3.U,
Mux(count_valids(2), 2.U,
Mux(count_valids(1), 1.U,
Mux(count_valids(0), 0.U,
0.U))))))
val bytes_to_write = Mux(
ptr_align_max_bytes_writeable < count_valids_largest_aligned,
Mux(ptr_align_max_bytes_writeable < throttle_end_writeable,
ptr_align_max_bytes_writeable,
throttle_end_writeable),
Mux(count_valids_largest_aligned < throttle_end_writeable,
count_valids_largest_aligned,
throttle_end_writeable)
)
val remapped_write_data = Cat(remapVecData.reverse) // >> ((NUM_QUEUES.U - bytes_to_write) << 3)
val enough_data = bytes_to_write =/= 0.U
val bytes_to_write_log2 = Mux(
ptr_align_max_bytes_writeable_log2 < count_valids_largest_aligned_log2,
Mux(ptr_align_max_bytes_writeable_log2 < throttle_end_writeable_log2,
ptr_align_max_bytes_writeable_log2,
throttle_end_writeable_log2),
Mux(count_valids_largest_aligned_log2 < throttle_end_writeable_log2,
count_valids_largest_aligned_log2,
throttle_end_writeable_log2)
)
val write_ptr_override = buf_lens_Q.io.deq.valid && (buf_lens_Q.io.deq.bits === backend_bytes_written)
val mem_write_fire = DecoupledHelper(
io.l2io.req.ready,
enough_data,
!write_ptr_override,
decompress_dest_info_Q.io.deq.valid
)
val bool_ptr_write_fire = DecoupledHelper(
io.l2io.req.ready,
buf_lens_Q.io.deq.valid,
buf_lens_Q.io.deq.bits === backend_bytes_written,
decompress_dest_info_Q.io.deq.valid
)
for (queueno <- 0 until NUM_QUEUES) {
remapVecReadys(queueno) := (queueno.U < bytes_to_write) && mem_write_fire.fire()
}
when (mem_write_fire.fire()) {
read_start_index := (read_start_index +& bytes_to_write) % NUM_QUEUES.U
backend_bytes_written := backend_bytes_written + bytes_to_write
logger.logInfo("[memwriter-serializer] writefire: addr: 0x%x, data 0x%x, size %d\n",
io.l2io.req.bits.addr,
io.l2io.req.bits.data,
io.l2io.req.bits.size
)
}
val bool_val = 1.U
if (write_cmp_flag) {
io.l2io.req.valid := mem_write_fire.fire(io.l2io.req.ready) || bool_ptr_write_fire.fire(io.l2io.req.ready)
} else {
io.l2io.req.valid := mem_write_fire.fire(io.l2io.req.ready)
}
io.l2io.req.bits.size := Mux(write_ptr_override, 0.U, bytes_to_write_log2)
io.l2io.req.bits.addr := Mux(write_ptr_override, decompress_dest_info_Q.io.deq.bits.cmpflag, backend_next_write_addr)
io.l2io.req.bits.data := Mux(write_ptr_override, bool_val, remapped_write_data)
io.l2io.req.bits.cmd := M_XWR
buf_lens_Q.io.deq.ready := bool_ptr_write_fire.fire(buf_lens_Q.io.deq.valid)
decompress_dest_info_Q.io.deq.ready := bool_ptr_write_fire.fire(decompress_dest_info_Q.io.deq.valid)
val bufs_completed = RegInit(0.U(64.W))
io.bufs_completed := bufs_completed
io.l2io.resp.ready := true.B
io.no_writes_inflight := io.l2io.no_memops_inflight
when (bool_ptr_write_fire.fire()) {
bufs_completed := bufs_completed + 1.U
backend_bytes_written := 0.U
logger.logInfo("[memwriter-serializer] write cmpflag addr: 0x%x, write ptr val 0x%x\n", decompress_dest_info_Q.io.deq.bits.cmpflag, bool_val)
}
when (count_valids =/= 0.U) {
logger.logInfo("[memwriter-serializer] write_start_index %d, backend_bytes_written %d, count_valids %d, ptr_align_max_bytes_writeable %d, bytes_to_write %d, bytes_to_write_log2 %d\n",
read_start_index,
backend_bytes_written,
count_valids,
ptr_align_max_bytes_writeable,
bytes_to_write,
bytes_to_write_log2
)
}
}
|
module MemWriter32( // @[MemWriter32.scala:14:7]
input clock, // @[MemWriter32.scala:14:7]
input reset, // @[MemWriter32.scala:14:7]
output io_memwrites_in_ready, // @[MemWriter32.scala:19:14]
input io_memwrites_in_valid, // @[MemWriter32.scala:19:14]
input [255:0] io_memwrites_in_bits_data, // @[MemWriter32.scala:19:14]
input [5:0] io_memwrites_in_bits_validbytes, // @[MemWriter32.scala:19:14]
input io_memwrites_in_bits_end_of_message, // @[MemWriter32.scala:19:14]
input io_l2io_req_ready, // @[MemWriter32.scala:19:14]
output io_l2io_req_valid, // @[MemWriter32.scala:19:14]
output [63:0] io_l2io_req_bits_addr, // @[MemWriter32.scala:19:14]
output [2:0] io_l2io_req_bits_size, // @[MemWriter32.scala:19:14]
output [255:0] io_l2io_req_bits_data, // @[MemWriter32.scala:19:14]
input io_l2io_resp_valid, // @[MemWriter32.scala:19:14]
input [255:0] io_l2io_resp_bits_data, // @[MemWriter32.scala:19:14]
input io_l2io_no_memops_inflight, // @[MemWriter32.scala:19:14]
output io_decompress_dest_info_ready, // @[MemWriter32.scala:19:14]
input io_decompress_dest_info_valid, // @[MemWriter32.scala:19:14]
input [63:0] io_decompress_dest_info_bits_op, // @[MemWriter32.scala:19:14]
input [63:0] io_decompress_dest_info_bits_cmpflag, // @[MemWriter32.scala:19:14]
output [63:0] io_bufs_completed, // @[MemWriter32.scala:19:14]
output io_no_writes_inflight // @[MemWriter32.scala:19:14]
);
wire _buf_lens_Q_io_enq_ready; // @[MemWriter32.scala:45:26]
wire _buf_lens_Q_io_deq_valid; // @[MemWriter32.scala:45:26]
wire [63:0] _buf_lens_Q_io_deq_bits; // @[MemWriter32.scala:45:26]
wire _decompress_dest_info_Q_io_deq_valid; // @[MemWriter32.scala:32:38]
wire [63:0] _decompress_dest_info_Q_io_deq_bits_op; // @[MemWriter32.scala:32:38]
wire [63:0] _decompress_dest_info_Q_io_deq_bits_cmpflag; // @[MemWriter32.scala:32:38]
wire _incoming_writes_Q_io_deq_valid; // @[MemWriter32.scala:28:33]
wire [255:0] _incoming_writes_Q_io_deq_bits_data; // @[MemWriter32.scala:28:33]
wire [5:0] _incoming_writes_Q_io_deq_bits_validbytes; // @[MemWriter32.scala:28:33]
wire _incoming_writes_Q_io_deq_bits_end_of_message; // @[MemWriter32.scala:28:33]
wire io_memwrites_in_valid_0 = io_memwrites_in_valid; // @[MemWriter32.scala:14:7]
wire [255:0] io_memwrites_in_bits_data_0 = io_memwrites_in_bits_data; // @[MemWriter32.scala:14:7]
wire [5:0] io_memwrites_in_bits_validbytes_0 = io_memwrites_in_bits_validbytes; // @[MemWriter32.scala:14:7]
wire io_memwrites_in_bits_end_of_message_0 = io_memwrites_in_bits_end_of_message; // @[MemWriter32.scala:14:7]
wire io_l2io_req_ready_0 = io_l2io_req_ready; // @[MemWriter32.scala:14:7]
wire io_l2io_resp_valid_0 = io_l2io_resp_valid; // @[MemWriter32.scala:14:7]
wire [255:0] io_l2io_resp_bits_data_0 = io_l2io_resp_bits_data; // @[MemWriter32.scala:14:7]
wire io_l2io_no_memops_inflight_0 = io_l2io_no_memops_inflight; // @[MemWriter32.scala:14:7]
wire io_decompress_dest_info_valid_0 = io_decompress_dest_info_valid; // @[MemWriter32.scala:14:7]
wire [63:0] io_decompress_dest_info_bits_op_0 = io_decompress_dest_info_bits_op; // @[MemWriter32.scala:14:7]
wire [63:0] io_decompress_dest_info_bits_cmpflag_0 = io_decompress_dest_info_bits_cmpflag; // @[MemWriter32.scala:14:7]
wire io_l2io_req_bits_cmd = 1'h1; // @[MemWriter32.scala:14:7]
wire io_l2io_resp_ready = 1'h1; // @[MemWriter32.scala:14:7]
wire _throttle_end_writeable_log2_T_6 = 1'h0; // @[MemWriter32.scala:160:50]
wire _count_valids_largest_aligned_log2_T_6 = 1'h0; // @[MemWriter32.scala:190:56]
wire _io_l2io_req_valid_T_4; // @[MemWriter32.scala:248:65]
wire [63:0] _io_l2io_req_bits_addr_T; // @[MemWriter32.scala:253:31]
wire [2:0] _io_l2io_req_bits_size_T; // @[MemWriter32.scala:252:31]
wire [255:0] _io_l2io_req_bits_data_T; // @[MemWriter32.scala:254:31]
wire io_no_writes_inflight_0 = io_l2io_no_memops_inflight_0; // @[MemWriter32.scala:14:7]
wire io_memwrites_in_ready_0; // @[MemWriter32.scala:14:7]
wire [63:0] io_l2io_req_bits_addr_0; // @[MemWriter32.scala:14:7]
wire [2:0] io_l2io_req_bits_size_0; // @[MemWriter32.scala:14:7]
wire [255:0] io_l2io_req_bits_data_0; // @[MemWriter32.scala:14:7]
wire io_l2io_req_valid_0; // @[MemWriter32.scala:14:7]
wire io_decompress_dest_info_ready_0; // @[MemWriter32.scala:14:7]
wire [63:0] io_bufs_completed_0; // @[MemWriter32.scala:14:7]
wire _decompress_dest_info_Q_io_deq_ready_T_1; // @[Misc.scala:26:53]
wire _decompress_dest_last_fire_T = _decompress_dest_info_Q_io_deq_ready_T_1 & _decompress_dest_info_Q_io_deq_valid; // @[Decoupled.scala:51:35]
reg decompress_dest_last_fire; // @[MemWriter32.scala:35:42]
reg decompress_dest_last_valid; // @[MemWriter32.scala:36:43]
wire _decompress_dest_printhelp_T = ~decompress_dest_last_valid; // @[MemWriter32.scala:36:43, :37:105]
wire _decompress_dest_printhelp_T_1 = decompress_dest_last_fire | _decompress_dest_printhelp_T; // @[MemWriter32.scala:35:42, :37:{101,105}]
wire decompress_dest_printhelp = _decompress_dest_info_Q_io_deq_valid & _decompress_dest_printhelp_T_1; // @[MemWriter32.scala:32:38, :37:{71,101}]
reg [63:0] allargs_0; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T = {1'h0, allargs_0} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_1; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_2 = {1'h0, allargs_0_1} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Logger.scala:38:38]
reg [63:0] buf_len_tracker; // @[MemWriter32.scala:50:32]
wire _incoming_writes_Q_io_deq_ready_T; // @[Misc.scala:26:53]
wire _T_6 = _incoming_writes_Q_io_deq_ready_T & _incoming_writes_Q_io_deq_valid; // @[Decoupled.scala:51:35]
wire [64:0] _GEN = {1'h0, buf_len_tracker} + {59'h0, _incoming_writes_Q_io_deq_bits_validbytes}; // @[MemWriter32.scala:28:33, :50:32, :55:42]
wire [64:0] _buf_len_tracker_T; // @[MemWriter32.scala:55:42]
assign _buf_len_tracker_T = _GEN; // @[MemWriter32.scala:55:42]
wire [64:0] _buf_lens_Q_io_enq_bits_T; // @[MemWriter32.scala:103:45]
assign _buf_lens_Q_io_enq_bits_T = _GEN; // @[MemWriter32.scala:55:42, :103:45]
reg [63:0] allargs_0_2; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_4 = {1'h0, allargs_0_2} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Logger.scala:38:38]
reg [5:0] write_start_index; // @[MemWriter32.scala:69:34]
wire _mem_resp_queues_0_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_1_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_2_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_3_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_4_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_5_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_6_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_7_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_8_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_9_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_10_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_11_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_12_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_13_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_14_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_15_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_16_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_17_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_18_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_19_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_20_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_21_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_22_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_23_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_24_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_25_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_26_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_27_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_28_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_29_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_30_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire _mem_resp_queues_31_enq_valid_T_2; // @[MemWriter32.scala:116:71]
wire mem_resp_queues_0_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_0_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_0_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_0_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_0_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_0_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_0_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_1_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_1_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_1_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_1_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_1_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_1_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_1_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_2_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_2_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_2_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_2_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_2_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_2_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_2_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_3_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_3_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_3_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_3_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_3_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_3_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_3_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_4_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_4_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_4_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_4_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_4_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_4_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_4_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_5_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_5_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_5_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_5_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_5_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_5_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_5_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_6_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_6_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_6_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_6_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_6_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_6_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_6_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_7_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_7_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_7_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_7_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_7_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_7_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_7_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_8_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_8_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_8_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_8_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_8_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_8_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_8_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_9_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_9_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_9_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_9_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_9_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_9_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_9_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_10_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_10_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_10_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_10_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_10_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_10_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_10_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_11_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_11_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_11_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_11_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_11_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_11_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_11_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_12_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_12_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_12_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_12_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_12_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_12_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_12_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_13_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_13_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_13_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_13_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_13_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_13_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_13_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_14_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_14_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_14_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_14_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_14_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_14_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_14_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_15_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_15_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_15_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_15_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_15_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_15_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_15_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_16_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_16_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_16_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_16_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_16_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_16_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_16_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_17_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_17_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_17_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_17_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_17_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_17_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_17_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_18_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_18_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_18_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_18_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_18_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_18_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_18_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_19_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_19_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_19_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_19_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_19_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_19_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_19_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_20_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_20_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_20_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_20_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_20_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_20_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_20_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_21_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_21_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_21_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_21_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_21_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_21_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_21_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_22_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_22_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_22_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_22_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_22_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_22_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_22_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_23_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_23_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_23_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_23_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_23_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_23_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_23_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_24_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_24_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_24_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_24_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_24_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_24_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_24_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_25_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_25_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_25_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_25_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_25_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_25_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_25_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_26_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_26_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_26_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_26_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_26_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_26_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_26_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_27_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_27_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_27_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_27_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_27_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_27_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_27_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_28_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_28_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_28_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_28_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_28_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_28_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_28_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_29_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_29_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_29_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_29_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_29_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_29_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_29_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_30_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_30_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_30_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_30_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_30_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_30_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_30_count; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_31_enq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_31_enq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_31_enq_bits; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_31_deq_ready; // @[MemWriter32.scala:70:49]
wire mem_resp_queues_31_deq_valid; // @[MemWriter32.scala:70:49]
wire [7:0] mem_resp_queues_31_deq_bits; // @[MemWriter32.scala:70:49]
wire [4:0] mem_resp_queues_31_count; // @[MemWriter32.scala:70:49]
wire [6:0] _GEN_0 = {1'h0, write_start_index}; // @[MemWriter32.scala:69:34, :82:40]
wire [6:0] _T_10 = _GEN_0 % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _GEN_1 = {1'h0, _incoming_writes_Q_io_deq_bits_validbytes}; // @[MemWriter32.scala:28:33, :82:135]
wire [6:0] _mem_resp_queues_enq_bits_T = _GEN_1 - 7'h1; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_1 = _mem_resp_queues_enq_bits_T[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_2 = {_mem_resp_queues_enq_bits_T_1, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_3 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_2; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_13 = (_GEN_0 + 7'h1) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_4 = _GEN_1 - 7'h2; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_5 = _mem_resp_queues_enq_bits_T_4[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_6 = {_mem_resp_queues_enq_bits_T_5, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_7 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_6; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_16 = (_GEN_0 + 7'h2) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_8 = _GEN_1 - 7'h3; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_9 = _mem_resp_queues_enq_bits_T_8[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_10 = {_mem_resp_queues_enq_bits_T_9, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_11 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_10; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_19 = (_GEN_0 + 7'h3) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_12 = _GEN_1 - 7'h4; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_13 = _mem_resp_queues_enq_bits_T_12[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_14 = {_mem_resp_queues_enq_bits_T_13, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_15 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_14; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_22 = (_GEN_0 + 7'h4) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_16 = _GEN_1 - 7'h5; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_17 = _mem_resp_queues_enq_bits_T_16[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_18 = {_mem_resp_queues_enq_bits_T_17, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_19 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_18; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_25 = (_GEN_0 + 7'h5) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_20 = _GEN_1 - 7'h6; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_21 = _mem_resp_queues_enq_bits_T_20[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_22 = {_mem_resp_queues_enq_bits_T_21, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_23 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_22; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_28 = (_GEN_0 + 7'h6) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_24 = _GEN_1 - 7'h7; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_25 = _mem_resp_queues_enq_bits_T_24[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_26 = {_mem_resp_queues_enq_bits_T_25, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_27 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_26; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_31 = (_GEN_0 + 7'h7) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_28 = _GEN_1 - 7'h8; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_29 = _mem_resp_queues_enq_bits_T_28[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_30 = {_mem_resp_queues_enq_bits_T_29, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_31 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_30; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_34 = (_GEN_0 + 7'h8) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_32 = _GEN_1 - 7'h9; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_33 = _mem_resp_queues_enq_bits_T_32[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_34 = {_mem_resp_queues_enq_bits_T_33, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_35 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_34; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_37 = (_GEN_0 + 7'h9) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_36 = _GEN_1 - 7'hA; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_37 = _mem_resp_queues_enq_bits_T_36[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_38 = {_mem_resp_queues_enq_bits_T_37, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_39 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_38; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_40 = (_GEN_0 + 7'hA) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_40 = _GEN_1 - 7'hB; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_41 = _mem_resp_queues_enq_bits_T_40[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_42 = {_mem_resp_queues_enq_bits_T_41, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_43 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_42; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_43 = (_GEN_0 + 7'hB) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_44 = _GEN_1 - 7'hC; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_45 = _mem_resp_queues_enq_bits_T_44[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_46 = {_mem_resp_queues_enq_bits_T_45, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_47 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_46; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_46 = (_GEN_0 + 7'hC) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_48 = _GEN_1 - 7'hD; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_49 = _mem_resp_queues_enq_bits_T_48[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_50 = {_mem_resp_queues_enq_bits_T_49, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_51 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_50; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_49 = (_GEN_0 + 7'hD) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_52 = _GEN_1 - 7'hE; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_53 = _mem_resp_queues_enq_bits_T_52[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_54 = {_mem_resp_queues_enq_bits_T_53, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_55 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_54; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_52 = (_GEN_0 + 7'hE) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_56 = _GEN_1 - 7'hF; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_57 = _mem_resp_queues_enq_bits_T_56[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_58 = {_mem_resp_queues_enq_bits_T_57, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_59 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_58; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_55 = (_GEN_0 + 7'hF) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_60 = _GEN_1 - 7'h10; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_61 = _mem_resp_queues_enq_bits_T_60[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_62 = {_mem_resp_queues_enq_bits_T_61, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_63 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_62; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_58 = (_GEN_0 + 7'h10) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_64 = _GEN_1 - 7'h11; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_65 = _mem_resp_queues_enq_bits_T_64[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_66 = {_mem_resp_queues_enq_bits_T_65, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_67 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_66; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_61 = (_GEN_0 + 7'h11) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_68 = _GEN_1 - 7'h12; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_69 = _mem_resp_queues_enq_bits_T_68[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_70 = {_mem_resp_queues_enq_bits_T_69, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_71 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_70; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_64 = (_GEN_0 + 7'h12) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_72 = _GEN_1 - 7'h13; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_73 = _mem_resp_queues_enq_bits_T_72[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_74 = {_mem_resp_queues_enq_bits_T_73, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_75 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_74; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_67 = (_GEN_0 + 7'h13) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_76 = _GEN_1 - 7'h14; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_77 = _mem_resp_queues_enq_bits_T_76[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_78 = {_mem_resp_queues_enq_bits_T_77, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_79 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_78; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_70 = (_GEN_0 + 7'h14) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_80 = _GEN_1 - 7'h15; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_81 = _mem_resp_queues_enq_bits_T_80[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_82 = {_mem_resp_queues_enq_bits_T_81, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_83 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_82; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_73 = (_GEN_0 + 7'h15) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_84 = _GEN_1 - 7'h16; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_85 = _mem_resp_queues_enq_bits_T_84[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_86 = {_mem_resp_queues_enq_bits_T_85, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_87 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_86; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_76 = (_GEN_0 + 7'h16) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_88 = _GEN_1 - 7'h17; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_89 = _mem_resp_queues_enq_bits_T_88[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_90 = {_mem_resp_queues_enq_bits_T_89, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_91 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_90; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_79 = (_GEN_0 + 7'h17) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_92 = _GEN_1 - 7'h18; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_93 = _mem_resp_queues_enq_bits_T_92[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_94 = {_mem_resp_queues_enq_bits_T_93, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_95 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_94; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_82 = (_GEN_0 + 7'h18) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_96 = _GEN_1 - 7'h19; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_97 = _mem_resp_queues_enq_bits_T_96[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_98 = {_mem_resp_queues_enq_bits_T_97, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_99 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_98; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_85 = (_GEN_0 + 7'h19) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_100 = _GEN_1 - 7'h1A; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_101 = _mem_resp_queues_enq_bits_T_100[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_102 = {_mem_resp_queues_enq_bits_T_101, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_103 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_102; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_88 = (_GEN_0 + 7'h1A) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_104 = _GEN_1 - 7'h1B; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_105 = _mem_resp_queues_enq_bits_T_104[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_106 = {_mem_resp_queues_enq_bits_T_105, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_107 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_106; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_91 = (_GEN_0 + 7'h1B) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_108 = _GEN_1 - 7'h1C; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_109 = _mem_resp_queues_enq_bits_T_108[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_110 = {_mem_resp_queues_enq_bits_T_109, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_111 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_110; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_94 = (_GEN_0 + 7'h1C) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_112 = _GEN_1 - 7'h1D; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_113 = _mem_resp_queues_enq_bits_T_112[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_114 = {_mem_resp_queues_enq_bits_T_113, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_115 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_114; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_97 = (_GEN_0 + 7'h1D) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_116 = _GEN_1 - 7'h1E; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_117 = _mem_resp_queues_enq_bits_T_116[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_118 = {_mem_resp_queues_enq_bits_T_117, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_119 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_118; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_100 = (_GEN_0 + 7'h1E) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_120 = _GEN_1 - 7'h1F; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_121 = _mem_resp_queues_enq_bits_T_120[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_122 = {_mem_resp_queues_enq_bits_T_121, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_123 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_122; // @[MemWriter32.scala:28:33, :82:{117,152}]
wire [6:0] _T_103 = (_GEN_0 + 7'h1F) % 7'h20; // @[MemWriter32.scala:82:{40,54}]
wire [6:0] _mem_resp_queues_enq_bits_T_124 = _GEN_1 - 7'h20; // @[MemWriter32.scala:82:135]
wire [5:0] _mem_resp_queues_enq_bits_T_125 = _mem_resp_queues_enq_bits_T_124[5:0]; // @[MemWriter32.scala:82:135]
wire [8:0] _mem_resp_queues_enq_bits_T_126 = {_mem_resp_queues_enq_bits_T_125, 3'h0}; // @[MemWriter32.scala:82:{135,152}]
wire [255:0] _mem_resp_queues_enq_bits_T_127 = _incoming_writes_Q_io_deq_bits_data >> _mem_resp_queues_enq_bits_T_126; // @[MemWriter32.scala:28:33, :82:{117,152}]
assign mem_resp_queues_0_enq_bits = _T_103[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h0 ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_1_enq_bits = _T_103[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h1 ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_2_enq_bits = _T_103[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h2 ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_3_enq_bits = _T_103[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h3 ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_4_enq_bits = _T_103[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h4 ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_5_enq_bits = _T_103[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h5 ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_6_enq_bits = _T_103[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h6 ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_7_enq_bits = _T_103[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h7 ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_8_enq_bits = _T_103[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h8 ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_9_enq_bits = _T_103[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h9 ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_10_enq_bits = _T_103[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'hA ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_11_enq_bits = _T_103[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'hB ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_12_enq_bits = _T_103[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'hC ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_13_enq_bits = _T_103[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'hD ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_14_enq_bits = _T_103[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'hE ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_15_enq_bits = _T_103[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'hF ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_16_enq_bits = _T_103[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h10 ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_17_enq_bits = _T_103[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h11 ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_18_enq_bits = _T_103[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h12 ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_19_enq_bits = _T_103[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h13 ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_20_enq_bits = _T_103[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h14 ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_21_enq_bits = _T_103[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h15 ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_22_enq_bits = _T_103[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h16 ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_23_enq_bits = _T_103[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h17 ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_24_enq_bits = _T_103[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h18 ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_25_enq_bits = _T_103[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h19 ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_26_enq_bits = _T_103[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h1A ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_27_enq_bits = _T_103[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h1B ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_28_enq_bits = _T_103[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h1C ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_29_enq_bits = _T_103[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h1D ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_30_enq_bits = _T_103[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_127[7:0] : _T_100[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_123[7:0] : _T_97[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_119[7:0] : _T_94[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_115[7:0] : _T_91[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_111[7:0] : _T_88[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_107[7:0] : _T_85[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_103[7:0] : _T_82[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_99[7:0] : _T_79[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_95[7:0] : _T_76[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_91[7:0] : _T_73[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_87[7:0] : _T_70[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_83[7:0] : _T_67[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_79[7:0] : _T_64[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_75[7:0] : _T_61[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_71[7:0] : _T_58[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_67[7:0] : _T_55[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_63[7:0] : _T_52[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_59[7:0] : _T_49[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_55[7:0] : _T_46[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_51[7:0] : _T_43[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_47[7:0] : _T_40[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_43[7:0] : _T_37[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_39[7:0] : _T_34[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_35[7:0] : _T_31[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_31[7:0] : _T_28[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_27[7:0] : _T_25[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_23[7:0] : _T_22[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_19[7:0] : _T_19[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_15[7:0] : _T_16[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_11[7:0] : _T_13[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_7[7:0] : _T_10[4:0] == 5'h1E ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
assign mem_resp_queues_31_enq_bits = (&(_T_103[4:0])) ? _mem_resp_queues_enq_bits_T_127[7:0] : (&(_T_100[4:0])) ? _mem_resp_queues_enq_bits_T_123[7:0] : (&(_T_97[4:0])) ? _mem_resp_queues_enq_bits_T_119[7:0] : (&(_T_94[4:0])) ? _mem_resp_queues_enq_bits_T_115[7:0] : (&(_T_91[4:0])) ? _mem_resp_queues_enq_bits_T_111[7:0] : (&(_T_88[4:0])) ? _mem_resp_queues_enq_bits_T_107[7:0] : (&(_T_85[4:0])) ? _mem_resp_queues_enq_bits_T_103[7:0] : (&(_T_82[4:0])) ? _mem_resp_queues_enq_bits_T_99[7:0] : (&(_T_79[4:0])) ? _mem_resp_queues_enq_bits_T_95[7:0] : (&(_T_76[4:0])) ? _mem_resp_queues_enq_bits_T_91[7:0] : (&(_T_73[4:0])) ? _mem_resp_queues_enq_bits_T_87[7:0] : (&(_T_70[4:0])) ? _mem_resp_queues_enq_bits_T_83[7:0] : (&(_T_67[4:0])) ? _mem_resp_queues_enq_bits_T_79[7:0] : (&(_T_64[4:0])) ? _mem_resp_queues_enq_bits_T_75[7:0] : (&(_T_61[4:0])) ? _mem_resp_queues_enq_bits_T_71[7:0] : (&(_T_58[4:0])) ? _mem_resp_queues_enq_bits_T_67[7:0] : (&(_T_55[4:0])) ? _mem_resp_queues_enq_bits_T_63[7:0] : (&(_T_52[4:0])) ? _mem_resp_queues_enq_bits_T_59[7:0] : (&(_T_49[4:0])) ? _mem_resp_queues_enq_bits_T_55[7:0] : (&(_T_46[4:0])) ? _mem_resp_queues_enq_bits_T_51[7:0] : (&(_T_43[4:0])) ? _mem_resp_queues_enq_bits_T_47[7:0] : (&(_T_40[4:0])) ? _mem_resp_queues_enq_bits_T_43[7:0] : (&(_T_37[4:0])) ? _mem_resp_queues_enq_bits_T_39[7:0] : (&(_T_34[4:0])) ? _mem_resp_queues_enq_bits_T_35[7:0] : (&(_T_31[4:0])) ? _mem_resp_queues_enq_bits_T_31[7:0] : (&(_T_28[4:0])) ? _mem_resp_queues_enq_bits_T_27[7:0] : (&(_T_25[4:0])) ? _mem_resp_queues_enq_bits_T_23[7:0] : (&(_T_22[4:0])) ? _mem_resp_queues_enq_bits_T_19[7:0] : (&(_T_19[4:0])) ? _mem_resp_queues_enq_bits_T_15[7:0] : (&(_T_16[4:0])) ? _mem_resp_queues_enq_bits_T_11[7:0] : (&(_T_13[4:0])) ? _mem_resp_queues_enq_bits_T_7[7:0] : (&(_T_10[4:0])) ? _mem_resp_queues_enq_bits_T_3[7:0] : 8'h0; // @[MemWriter32.scala:70:49, :75:16, :82:{54,79,117}]
wire [6:0] wrap_len_index_wide = _GEN_0 + _GEN_1; // @[MemWriter32.scala:82:{40,135}, :86:47]
wire [6:0] _GEN_2 = wrap_len_index_wide % 7'h20; // @[MemWriter32.scala:86:47, :87:48]
wire [5:0] wrap_len_index_end = _GEN_2[5:0]; // @[MemWriter32.scala:87:48]
wire wrapped = |(wrap_len_index_wide[6:5]); // @[MemWriter32.scala:86:47, :88:37]
wire _all_queues_ready_T = mem_resp_queues_0_enq_ready & mem_resp_queues_1_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_1 = _all_queues_ready_T & mem_resp_queues_2_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_2 = _all_queues_ready_T_1 & mem_resp_queues_3_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_3 = _all_queues_ready_T_2 & mem_resp_queues_4_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_4 = _all_queues_ready_T_3 & mem_resp_queues_5_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_5 = _all_queues_ready_T_4 & mem_resp_queues_6_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_6 = _all_queues_ready_T_5 & mem_resp_queues_7_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_7 = _all_queues_ready_T_6 & mem_resp_queues_8_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_8 = _all_queues_ready_T_7 & mem_resp_queues_9_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_9 = _all_queues_ready_T_8 & mem_resp_queues_10_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_10 = _all_queues_ready_T_9 & mem_resp_queues_11_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_11 = _all_queues_ready_T_10 & mem_resp_queues_12_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_12 = _all_queues_ready_T_11 & mem_resp_queues_13_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_13 = _all_queues_ready_T_12 & mem_resp_queues_14_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_14 = _all_queues_ready_T_13 & mem_resp_queues_15_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_15 = _all_queues_ready_T_14 & mem_resp_queues_16_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_16 = _all_queues_ready_T_15 & mem_resp_queues_17_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_17 = _all_queues_ready_T_16 & mem_resp_queues_18_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_18 = _all_queues_ready_T_17 & mem_resp_queues_19_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_19 = _all_queues_ready_T_18 & mem_resp_queues_20_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_20 = _all_queues_ready_T_19 & mem_resp_queues_21_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_21 = _all_queues_ready_T_20 & mem_resp_queues_22_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_22 = _all_queues_ready_T_21 & mem_resp_queues_23_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_23 = _all_queues_ready_T_22 & mem_resp_queues_24_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_24 = _all_queues_ready_T_23 & mem_resp_queues_25_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_25 = _all_queues_ready_T_24 & mem_resp_queues_26_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_26 = _all_queues_ready_T_25 & mem_resp_queues_27_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_27 = _all_queues_ready_T_26 & mem_resp_queues_28_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_28 = _all_queues_ready_T_27 & mem_resp_queues_29_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _all_queues_ready_T_29 = _all_queues_ready_T_28 & mem_resp_queues_30_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire all_queues_ready = _all_queues_ready_T_29 & mem_resp_queues_31_enq_ready; // @[MemWriter32.scala:70:49, :90:68]
wire _account_for_buf_lens_Q_T = ~_incoming_writes_Q_io_deq_bits_end_of_message; // @[MemWriter32.scala:28:33, :94:33]
wire _account_for_buf_lens_Q_T_1 = _incoming_writes_Q_io_deq_bits_end_of_message & _buf_lens_Q_io_enq_ready; // @[MemWriter32.scala:28:33, :45:26, :94:61]
wire account_for_buf_lens_Q = _account_for_buf_lens_Q_T | _account_for_buf_lens_Q_T_1; // @[MemWriter32.scala:94:{33,46,61}]
wire _T_105 = _incoming_writes_Q_io_deq_valid & all_queues_ready; // @[Misc.scala:26:53]
wire _buf_lens_Q_io_enq_valid_T; // @[Misc.scala:26:53]
assign _buf_lens_Q_io_enq_valid_T = _T_105; // @[Misc.scala:26:53]
wire _mem_resp_queues_0_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_0_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_1_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_1_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_2_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_2_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_3_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_3_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_4_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_4_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_5_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_5_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_6_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_6_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_7_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_7_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_8_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_8_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_9_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_9_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_10_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_10_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_11_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_11_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_12_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_12_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_13_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_13_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_14_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_14_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_15_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_15_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_16_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_16_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_17_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_17_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_18_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_18_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_19_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_19_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_20_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_20_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_21_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_21_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_22_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_22_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_23_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_23_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_24_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_24_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_25_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_25_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_26_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_26_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_27_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_27_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_28_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_28_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_29_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_29_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_30_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_30_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _mem_resp_queues_31_enq_valid_T; // @[Misc.scala:29:18]
assign _mem_resp_queues_31_enq_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
wire _buf_lens_Q_io_enq_valid_T_1 = _buf_lens_Q_io_enq_valid_T & _incoming_writes_Q_io_deq_bits_end_of_message; // @[Misc.scala:26:53]
assign _incoming_writes_Q_io_deq_ready_T = all_queues_ready & account_for_buf_lens_Q; // @[Misc.scala:26:53]
wire _GEN_3 = write_start_index == 6'h0; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T = _GEN_3; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_3; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_3 = _GEN_3; // @[MemWriter32.scala:113:41, :114:41]
wire _use_this_queue_T_1 = |wrap_len_index_end; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_2 = _use_this_queue_T | _use_this_queue_T_1; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_4 = |wrap_len_index_end; // @[MemWriter32.scala:87:48, :113:77, :114:77]
wire _use_this_queue_T_5 = _use_this_queue_T_3 & _use_this_queue_T_4; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue = wrapped ? _use_this_queue_T_2 : _use_this_queue_T_5; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_0_enq_valid_T_1 = _mem_resp_queues_0_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_0_enq_valid_T_2 = _mem_resp_queues_0_enq_valid_T_1 & use_this_queue; // @[Misc.scala:29:18]
assign mem_resp_queues_0_enq_valid = _mem_resp_queues_0_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_4 = write_start_index < 6'h2; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_6; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_6 = _GEN_4; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_9; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_9 = _GEN_4; // @[MemWriter32.scala:113:41, :114:41]
wire _use_this_queue_T_7 = |(wrap_len_index_end[5:1]); // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_8 = _use_this_queue_T_6 | _use_this_queue_T_7; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_10 = |(wrap_len_index_end[5:1]); // @[MemWriter32.scala:87:48, :113:77, :114:77]
wire _use_this_queue_T_11 = _use_this_queue_T_9 & _use_this_queue_T_10; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_1 = wrapped ? _use_this_queue_T_8 : _use_this_queue_T_11; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_1_enq_valid_T_1 = _mem_resp_queues_1_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_1_enq_valid_T_2 = _mem_resp_queues_1_enq_valid_T_1 & use_this_queue_1; // @[Misc.scala:29:18]
assign mem_resp_queues_1_enq_valid = _mem_resp_queues_1_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_5 = write_start_index < 6'h3; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_12; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_12 = _GEN_5; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_15; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_15 = _GEN_5; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_6 = wrap_len_index_end > 6'h2; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_13; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_13 = _GEN_6; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_16; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_16 = _GEN_6; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_14 = _use_this_queue_T_12 | _use_this_queue_T_13; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_17 = _use_this_queue_T_15 & _use_this_queue_T_16; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_2 = wrapped ? _use_this_queue_T_14 : _use_this_queue_T_17; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_2_enq_valid_T_1 = _mem_resp_queues_2_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_2_enq_valid_T_2 = _mem_resp_queues_2_enq_valid_T_1 & use_this_queue_2; // @[Misc.scala:29:18]
assign mem_resp_queues_2_enq_valid = _mem_resp_queues_2_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_7 = write_start_index < 6'h4; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_18; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_18 = _GEN_7; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_21; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_21 = _GEN_7; // @[MemWriter32.scala:113:41, :114:41]
wire _use_this_queue_T_19 = |(wrap_len_index_end[5:2]); // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_20 = _use_this_queue_T_18 | _use_this_queue_T_19; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_22 = |(wrap_len_index_end[5:2]); // @[MemWriter32.scala:87:48, :113:77, :114:77]
wire _use_this_queue_T_23 = _use_this_queue_T_21 & _use_this_queue_T_22; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_3 = wrapped ? _use_this_queue_T_20 : _use_this_queue_T_23; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_3_enq_valid_T_1 = _mem_resp_queues_3_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_3_enq_valid_T_2 = _mem_resp_queues_3_enq_valid_T_1 & use_this_queue_3; // @[Misc.scala:29:18]
assign mem_resp_queues_3_enq_valid = _mem_resp_queues_3_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_8 = write_start_index < 6'h5; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_24; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_24 = _GEN_8; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_27; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_27 = _GEN_8; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_9 = wrap_len_index_end > 6'h4; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_25; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_25 = _GEN_9; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_28; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_28 = _GEN_9; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_26 = _use_this_queue_T_24 | _use_this_queue_T_25; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_29 = _use_this_queue_T_27 & _use_this_queue_T_28; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_4 = wrapped ? _use_this_queue_T_26 : _use_this_queue_T_29; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_4_enq_valid_T_1 = _mem_resp_queues_4_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_4_enq_valid_T_2 = _mem_resp_queues_4_enq_valid_T_1 & use_this_queue_4; // @[Misc.scala:29:18]
assign mem_resp_queues_4_enq_valid = _mem_resp_queues_4_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_10 = write_start_index < 6'h6; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_30; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_30 = _GEN_10; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_33; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_33 = _GEN_10; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_11 = wrap_len_index_end > 6'h5; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_31; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_31 = _GEN_11; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_34; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_34 = _GEN_11; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_32 = _use_this_queue_T_30 | _use_this_queue_T_31; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_35 = _use_this_queue_T_33 & _use_this_queue_T_34; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_5 = wrapped ? _use_this_queue_T_32 : _use_this_queue_T_35; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_5_enq_valid_T_1 = _mem_resp_queues_5_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_5_enq_valid_T_2 = _mem_resp_queues_5_enq_valid_T_1 & use_this_queue_5; // @[Misc.scala:29:18]
assign mem_resp_queues_5_enq_valid = _mem_resp_queues_5_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_12 = write_start_index < 6'h7; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_36; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_36 = _GEN_12; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_39; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_39 = _GEN_12; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_13 = wrap_len_index_end > 6'h6; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_37; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_37 = _GEN_13; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_40; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_40 = _GEN_13; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_38 = _use_this_queue_T_36 | _use_this_queue_T_37; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_41 = _use_this_queue_T_39 & _use_this_queue_T_40; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_6 = wrapped ? _use_this_queue_T_38 : _use_this_queue_T_41; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_6_enq_valid_T_1 = _mem_resp_queues_6_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_6_enq_valid_T_2 = _mem_resp_queues_6_enq_valid_T_1 & use_this_queue_6; // @[Misc.scala:29:18]
assign mem_resp_queues_6_enq_valid = _mem_resp_queues_6_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_14 = write_start_index < 6'h8; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_42; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_42 = _GEN_14; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_45; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_45 = _GEN_14; // @[MemWriter32.scala:113:41, :114:41]
wire _use_this_queue_T_43 = |(wrap_len_index_end[5:3]); // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_44 = _use_this_queue_T_42 | _use_this_queue_T_43; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_46 = |(wrap_len_index_end[5:3]); // @[MemWriter32.scala:87:48, :113:77, :114:77]
wire _use_this_queue_T_47 = _use_this_queue_T_45 & _use_this_queue_T_46; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_7 = wrapped ? _use_this_queue_T_44 : _use_this_queue_T_47; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_7_enq_valid_T_1 = _mem_resp_queues_7_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_7_enq_valid_T_2 = _mem_resp_queues_7_enq_valid_T_1 & use_this_queue_7; // @[Misc.scala:29:18]
assign mem_resp_queues_7_enq_valid = _mem_resp_queues_7_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_15 = write_start_index < 6'h9; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_48; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_48 = _GEN_15; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_51; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_51 = _GEN_15; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_16 = wrap_len_index_end > 6'h8; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_49; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_49 = _GEN_16; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_52; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_52 = _GEN_16; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_50 = _use_this_queue_T_48 | _use_this_queue_T_49; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_53 = _use_this_queue_T_51 & _use_this_queue_T_52; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_8 = wrapped ? _use_this_queue_T_50 : _use_this_queue_T_53; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_8_enq_valid_T_1 = _mem_resp_queues_8_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_8_enq_valid_T_2 = _mem_resp_queues_8_enq_valid_T_1 & use_this_queue_8; // @[Misc.scala:29:18]
assign mem_resp_queues_8_enq_valid = _mem_resp_queues_8_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_17 = write_start_index < 6'hA; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_54; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_54 = _GEN_17; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_57; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_57 = _GEN_17; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_18 = wrap_len_index_end > 6'h9; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_55; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_55 = _GEN_18; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_58; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_58 = _GEN_18; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_56 = _use_this_queue_T_54 | _use_this_queue_T_55; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_59 = _use_this_queue_T_57 & _use_this_queue_T_58; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_9 = wrapped ? _use_this_queue_T_56 : _use_this_queue_T_59; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_9_enq_valid_T_1 = _mem_resp_queues_9_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_9_enq_valid_T_2 = _mem_resp_queues_9_enq_valid_T_1 & use_this_queue_9; // @[Misc.scala:29:18]
assign mem_resp_queues_9_enq_valid = _mem_resp_queues_9_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_19 = write_start_index < 6'hB; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_60; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_60 = _GEN_19; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_63; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_63 = _GEN_19; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_20 = wrap_len_index_end > 6'hA; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_61; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_61 = _GEN_20; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_64; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_64 = _GEN_20; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_62 = _use_this_queue_T_60 | _use_this_queue_T_61; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_65 = _use_this_queue_T_63 & _use_this_queue_T_64; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_10 = wrapped ? _use_this_queue_T_62 : _use_this_queue_T_65; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_10_enq_valid_T_1 = _mem_resp_queues_10_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_10_enq_valid_T_2 = _mem_resp_queues_10_enq_valid_T_1 & use_this_queue_10; // @[Misc.scala:29:18]
assign mem_resp_queues_10_enq_valid = _mem_resp_queues_10_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_21 = write_start_index < 6'hC; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_66; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_66 = _GEN_21; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_69; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_69 = _GEN_21; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_22 = wrap_len_index_end > 6'hB; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_67; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_67 = _GEN_22; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_70; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_70 = _GEN_22; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_68 = _use_this_queue_T_66 | _use_this_queue_T_67; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_71 = _use_this_queue_T_69 & _use_this_queue_T_70; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_11 = wrapped ? _use_this_queue_T_68 : _use_this_queue_T_71; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_11_enq_valid_T_1 = _mem_resp_queues_11_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_11_enq_valid_T_2 = _mem_resp_queues_11_enq_valid_T_1 & use_this_queue_11; // @[Misc.scala:29:18]
assign mem_resp_queues_11_enq_valid = _mem_resp_queues_11_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_23 = write_start_index < 6'hD; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_72; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_72 = _GEN_23; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_75; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_75 = _GEN_23; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_24 = wrap_len_index_end > 6'hC; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_73; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_73 = _GEN_24; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_76; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_76 = _GEN_24; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_74 = _use_this_queue_T_72 | _use_this_queue_T_73; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_77 = _use_this_queue_T_75 & _use_this_queue_T_76; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_12 = wrapped ? _use_this_queue_T_74 : _use_this_queue_T_77; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_12_enq_valid_T_1 = _mem_resp_queues_12_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_12_enq_valid_T_2 = _mem_resp_queues_12_enq_valid_T_1 & use_this_queue_12; // @[Misc.scala:29:18]
assign mem_resp_queues_12_enq_valid = _mem_resp_queues_12_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_25 = write_start_index < 6'hE; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_78; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_78 = _GEN_25; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_81; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_81 = _GEN_25; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_26 = wrap_len_index_end > 6'hD; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_79; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_79 = _GEN_26; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_82; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_82 = _GEN_26; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_80 = _use_this_queue_T_78 | _use_this_queue_T_79; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_83 = _use_this_queue_T_81 & _use_this_queue_T_82; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_13 = wrapped ? _use_this_queue_T_80 : _use_this_queue_T_83; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_13_enq_valid_T_1 = _mem_resp_queues_13_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_13_enq_valid_T_2 = _mem_resp_queues_13_enq_valid_T_1 & use_this_queue_13; // @[Misc.scala:29:18]
assign mem_resp_queues_13_enq_valid = _mem_resp_queues_13_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_27 = write_start_index < 6'hF; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_84; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_84 = _GEN_27; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_87; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_87 = _GEN_27; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_28 = wrap_len_index_end > 6'hE; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_85; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_85 = _GEN_28; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_88; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_88 = _GEN_28; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_86 = _use_this_queue_T_84 | _use_this_queue_T_85; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_89 = _use_this_queue_T_87 & _use_this_queue_T_88; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_14 = wrapped ? _use_this_queue_T_86 : _use_this_queue_T_89; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_14_enq_valid_T_1 = _mem_resp_queues_14_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_14_enq_valid_T_2 = _mem_resp_queues_14_enq_valid_T_1 & use_this_queue_14; // @[Misc.scala:29:18]
assign mem_resp_queues_14_enq_valid = _mem_resp_queues_14_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_29 = write_start_index < 6'h10; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_90; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_90 = _GEN_29; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_93; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_93 = _GEN_29; // @[MemWriter32.scala:113:41, :114:41]
wire _use_this_queue_T_91 = |(wrap_len_index_end[5:4]); // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_92 = _use_this_queue_T_90 | _use_this_queue_T_91; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_94 = |(wrap_len_index_end[5:4]); // @[MemWriter32.scala:87:48, :113:77, :114:77]
wire _use_this_queue_T_95 = _use_this_queue_T_93 & _use_this_queue_T_94; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_15 = wrapped ? _use_this_queue_T_92 : _use_this_queue_T_95; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_15_enq_valid_T_1 = _mem_resp_queues_15_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_15_enq_valid_T_2 = _mem_resp_queues_15_enq_valid_T_1 & use_this_queue_15; // @[Misc.scala:29:18]
assign mem_resp_queues_15_enq_valid = _mem_resp_queues_15_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_30 = write_start_index < 6'h11; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_96; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_96 = _GEN_30; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_99; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_99 = _GEN_30; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_31 = wrap_len_index_end > 6'h10; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_97; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_97 = _GEN_31; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_100; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_100 = _GEN_31; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_98 = _use_this_queue_T_96 | _use_this_queue_T_97; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_101 = _use_this_queue_T_99 & _use_this_queue_T_100; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_16 = wrapped ? _use_this_queue_T_98 : _use_this_queue_T_101; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_16_enq_valid_T_1 = _mem_resp_queues_16_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_16_enq_valid_T_2 = _mem_resp_queues_16_enq_valid_T_1 & use_this_queue_16; // @[Misc.scala:29:18]
assign mem_resp_queues_16_enq_valid = _mem_resp_queues_16_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_32 = write_start_index < 6'h12; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_102; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_102 = _GEN_32; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_105; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_105 = _GEN_32; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_33 = wrap_len_index_end > 6'h11; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_103; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_103 = _GEN_33; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_106; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_106 = _GEN_33; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_104 = _use_this_queue_T_102 | _use_this_queue_T_103; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_107 = _use_this_queue_T_105 & _use_this_queue_T_106; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_17 = wrapped ? _use_this_queue_T_104 : _use_this_queue_T_107; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_17_enq_valid_T_1 = _mem_resp_queues_17_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_17_enq_valid_T_2 = _mem_resp_queues_17_enq_valid_T_1 & use_this_queue_17; // @[Misc.scala:29:18]
assign mem_resp_queues_17_enq_valid = _mem_resp_queues_17_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_34 = write_start_index < 6'h13; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_108; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_108 = _GEN_34; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_111; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_111 = _GEN_34; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_35 = wrap_len_index_end > 6'h12; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_109; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_109 = _GEN_35; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_112; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_112 = _GEN_35; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_110 = _use_this_queue_T_108 | _use_this_queue_T_109; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_113 = _use_this_queue_T_111 & _use_this_queue_T_112; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_18 = wrapped ? _use_this_queue_T_110 : _use_this_queue_T_113; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_18_enq_valid_T_1 = _mem_resp_queues_18_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_18_enq_valid_T_2 = _mem_resp_queues_18_enq_valid_T_1 & use_this_queue_18; // @[Misc.scala:29:18]
assign mem_resp_queues_18_enq_valid = _mem_resp_queues_18_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_36 = write_start_index < 6'h14; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_114; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_114 = _GEN_36; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_117; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_117 = _GEN_36; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_37 = wrap_len_index_end > 6'h13; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_115; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_115 = _GEN_37; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_118; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_118 = _GEN_37; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_116 = _use_this_queue_T_114 | _use_this_queue_T_115; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_119 = _use_this_queue_T_117 & _use_this_queue_T_118; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_19 = wrapped ? _use_this_queue_T_116 : _use_this_queue_T_119; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_19_enq_valid_T_1 = _mem_resp_queues_19_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_19_enq_valid_T_2 = _mem_resp_queues_19_enq_valid_T_1 & use_this_queue_19; // @[Misc.scala:29:18]
assign mem_resp_queues_19_enq_valid = _mem_resp_queues_19_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_38 = write_start_index < 6'h15; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_120; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_120 = _GEN_38; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_123; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_123 = _GEN_38; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_39 = wrap_len_index_end > 6'h14; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_121; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_121 = _GEN_39; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_124; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_124 = _GEN_39; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_122 = _use_this_queue_T_120 | _use_this_queue_T_121; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_125 = _use_this_queue_T_123 & _use_this_queue_T_124; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_20 = wrapped ? _use_this_queue_T_122 : _use_this_queue_T_125; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_20_enq_valid_T_1 = _mem_resp_queues_20_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_20_enq_valid_T_2 = _mem_resp_queues_20_enq_valid_T_1 & use_this_queue_20; // @[Misc.scala:29:18]
assign mem_resp_queues_20_enq_valid = _mem_resp_queues_20_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_40 = write_start_index < 6'h16; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_126; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_126 = _GEN_40; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_129; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_129 = _GEN_40; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_41 = wrap_len_index_end > 6'h15; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_127; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_127 = _GEN_41; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_130; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_130 = _GEN_41; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_128 = _use_this_queue_T_126 | _use_this_queue_T_127; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_131 = _use_this_queue_T_129 & _use_this_queue_T_130; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_21 = wrapped ? _use_this_queue_T_128 : _use_this_queue_T_131; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_21_enq_valid_T_1 = _mem_resp_queues_21_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_21_enq_valid_T_2 = _mem_resp_queues_21_enq_valid_T_1 & use_this_queue_21; // @[Misc.scala:29:18]
assign mem_resp_queues_21_enq_valid = _mem_resp_queues_21_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_42 = write_start_index < 6'h17; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_132; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_132 = _GEN_42; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_135; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_135 = _GEN_42; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_43 = wrap_len_index_end > 6'h16; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_133; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_133 = _GEN_43; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_136; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_136 = _GEN_43; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_134 = _use_this_queue_T_132 | _use_this_queue_T_133; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_137 = _use_this_queue_T_135 & _use_this_queue_T_136; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_22 = wrapped ? _use_this_queue_T_134 : _use_this_queue_T_137; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_22_enq_valid_T_1 = _mem_resp_queues_22_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_22_enq_valid_T_2 = _mem_resp_queues_22_enq_valid_T_1 & use_this_queue_22; // @[Misc.scala:29:18]
assign mem_resp_queues_22_enq_valid = _mem_resp_queues_22_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_44 = write_start_index < 6'h18; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_138; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_138 = _GEN_44; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_141; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_141 = _GEN_44; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_45 = wrap_len_index_end > 6'h17; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_139; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_139 = _GEN_45; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_142; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_142 = _GEN_45; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_140 = _use_this_queue_T_138 | _use_this_queue_T_139; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_143 = _use_this_queue_T_141 & _use_this_queue_T_142; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_23 = wrapped ? _use_this_queue_T_140 : _use_this_queue_T_143; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_23_enq_valid_T_1 = _mem_resp_queues_23_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_23_enq_valid_T_2 = _mem_resp_queues_23_enq_valid_T_1 & use_this_queue_23; // @[Misc.scala:29:18]
assign mem_resp_queues_23_enq_valid = _mem_resp_queues_23_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_46 = write_start_index < 6'h19; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_144; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_144 = _GEN_46; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_147; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_147 = _GEN_46; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_47 = wrap_len_index_end > 6'h18; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_145; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_145 = _GEN_47; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_148; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_148 = _GEN_47; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_146 = _use_this_queue_T_144 | _use_this_queue_T_145; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_149 = _use_this_queue_T_147 & _use_this_queue_T_148; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_24 = wrapped ? _use_this_queue_T_146 : _use_this_queue_T_149; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_24_enq_valid_T_1 = _mem_resp_queues_24_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_24_enq_valid_T_2 = _mem_resp_queues_24_enq_valid_T_1 & use_this_queue_24; // @[Misc.scala:29:18]
assign mem_resp_queues_24_enq_valid = _mem_resp_queues_24_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_48 = write_start_index < 6'h1A; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_150; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_150 = _GEN_48; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_153; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_153 = _GEN_48; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_49 = wrap_len_index_end > 6'h19; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_151; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_151 = _GEN_49; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_154; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_154 = _GEN_49; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_152 = _use_this_queue_T_150 | _use_this_queue_T_151; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_155 = _use_this_queue_T_153 & _use_this_queue_T_154; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_25 = wrapped ? _use_this_queue_T_152 : _use_this_queue_T_155; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_25_enq_valid_T_1 = _mem_resp_queues_25_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_25_enq_valid_T_2 = _mem_resp_queues_25_enq_valid_T_1 & use_this_queue_25; // @[Misc.scala:29:18]
assign mem_resp_queues_25_enq_valid = _mem_resp_queues_25_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_50 = write_start_index < 6'h1B; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_156; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_156 = _GEN_50; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_159; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_159 = _GEN_50; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_51 = wrap_len_index_end > 6'h1A; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_157; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_157 = _GEN_51; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_160; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_160 = _GEN_51; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_158 = _use_this_queue_T_156 | _use_this_queue_T_157; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_161 = _use_this_queue_T_159 & _use_this_queue_T_160; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_26 = wrapped ? _use_this_queue_T_158 : _use_this_queue_T_161; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_26_enq_valid_T_1 = _mem_resp_queues_26_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_26_enq_valid_T_2 = _mem_resp_queues_26_enq_valid_T_1 & use_this_queue_26; // @[Misc.scala:29:18]
assign mem_resp_queues_26_enq_valid = _mem_resp_queues_26_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_52 = write_start_index < 6'h1C; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_162; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_162 = _GEN_52; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_165; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_165 = _GEN_52; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_53 = wrap_len_index_end > 6'h1B; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_163; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_163 = _GEN_53; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_166; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_166 = _GEN_53; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_164 = _use_this_queue_T_162 | _use_this_queue_T_163; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_167 = _use_this_queue_T_165 & _use_this_queue_T_166; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_27 = wrapped ? _use_this_queue_T_164 : _use_this_queue_T_167; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_27_enq_valid_T_1 = _mem_resp_queues_27_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_27_enq_valid_T_2 = _mem_resp_queues_27_enq_valid_T_1 & use_this_queue_27; // @[Misc.scala:29:18]
assign mem_resp_queues_27_enq_valid = _mem_resp_queues_27_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_54 = write_start_index < 6'h1D; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_168; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_168 = _GEN_54; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_171; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_171 = _GEN_54; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_55 = wrap_len_index_end > 6'h1C; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_169; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_169 = _GEN_55; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_172; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_172 = _GEN_55; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_170 = _use_this_queue_T_168 | _use_this_queue_T_169; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_173 = _use_this_queue_T_171 & _use_this_queue_T_172; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_28 = wrapped ? _use_this_queue_T_170 : _use_this_queue_T_173; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_28_enq_valid_T_1 = _mem_resp_queues_28_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_28_enq_valid_T_2 = _mem_resp_queues_28_enq_valid_T_1 & use_this_queue_28; // @[Misc.scala:29:18]
assign mem_resp_queues_28_enq_valid = _mem_resp_queues_28_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_56 = write_start_index < 6'h1E; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_174; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_174 = _GEN_56; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_177; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_177 = _GEN_56; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_57 = wrap_len_index_end > 6'h1D; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_175; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_175 = _GEN_57; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_178; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_178 = _GEN_57; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_176 = _use_this_queue_T_174 | _use_this_queue_T_175; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_179 = _use_this_queue_T_177 & _use_this_queue_T_178; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_29 = wrapped ? _use_this_queue_T_176 : _use_this_queue_T_179; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_29_enq_valid_T_1 = _mem_resp_queues_29_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_29_enq_valid_T_2 = _mem_resp_queues_29_enq_valid_T_1 & use_this_queue_29; // @[Misc.scala:29:18]
assign mem_resp_queues_29_enq_valid = _mem_resp_queues_29_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _GEN_58 = write_start_index < 6'h1F; // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_180; // @[MemWriter32.scala:113:41]
assign _use_this_queue_T_180 = _GEN_58; // @[MemWriter32.scala:113:41]
wire _use_this_queue_T_183; // @[MemWriter32.scala:114:41]
assign _use_this_queue_T_183 = _GEN_58; // @[MemWriter32.scala:113:41, :114:41]
wire _GEN_59 = wrap_len_index_end > 6'h1E; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_181; // @[MemWriter32.scala:113:77]
assign _use_this_queue_T_181 = _GEN_59; // @[MemWriter32.scala:113:77]
wire _use_this_queue_T_184; // @[MemWriter32.scala:114:77]
assign _use_this_queue_T_184 = _GEN_59; // @[MemWriter32.scala:113:77, :114:77]
wire _use_this_queue_T_182 = _use_this_queue_T_180 | _use_this_queue_T_181; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_185 = _use_this_queue_T_183 & _use_this_queue_T_184; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_30 = wrapped ? _use_this_queue_T_182 : _use_this_queue_T_185; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_30_enq_valid_T_1 = _mem_resp_queues_30_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_30_enq_valid_T_2 = _mem_resp_queues_30_enq_valid_T_1 & use_this_queue_30; // @[Misc.scala:29:18]
assign mem_resp_queues_30_enq_valid = _mem_resp_queues_30_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
wire _use_this_queue_T_186 = ~(write_start_index[5]); // @[MemWriter32.scala:69:34, :113:41]
wire _use_this_queue_T_187 = wrap_len_index_end[5]; // @[MemWriter32.scala:87:48, :113:77]
wire _use_this_queue_T_190 = wrap_len_index_end[5]; // @[MemWriter32.scala:87:48, :113:77, :114:77]
wire _use_this_queue_T_188 = _use_this_queue_T_186 | _use_this_queue_T_187; // @[MemWriter32.scala:113:{41,63,77}]
wire _use_this_queue_T_189 = ~(write_start_index[5]); // @[MemWriter32.scala:69:34, :113:41, :114:41]
wire _use_this_queue_T_191 = _use_this_queue_T_189 & _use_this_queue_T_190; // @[MemWriter32.scala:114:{41,63,77}]
wire use_this_queue_31 = wrapped ? _use_this_queue_T_188 : _use_this_queue_T_191; // @[MemWriter32.scala:88:37, :112:29, :113:63, :114:63]
wire _mem_resp_queues_31_enq_valid_T_1 = _mem_resp_queues_31_enq_valid_T & account_for_buf_lens_Q; // @[Misc.scala:29:18]
assign _mem_resp_queues_31_enq_valid_T_2 = _mem_resp_queues_31_enq_valid_T_1 & use_this_queue_31; // @[Misc.scala:29:18]
assign mem_resp_queues_31_enq_valid = _mem_resp_queues_31_enq_valid_T_2; // @[MemWriter32.scala:70:49, :116:71]
reg [63:0] allargs_0_3; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_6 = {1'h0, allargs_0_3} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_4; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_8 = {1'h0, allargs_0_4} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_5; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_10 = {1'h0, allargs_0_5} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_6; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_12 = {1'h0, allargs_0_6} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_7; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_14 = {1'h0, allargs_0_7} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_8; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_16 = {1'h0, allargs_0_8} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_9; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_18 = {1'h0, allargs_0_9} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_10; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_20 = {1'h0, allargs_0_10} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_11; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_22 = {1'h0, allargs_0_11} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_12; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_24 = {1'h0, allargs_0_12} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_13; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_26 = {1'h0, allargs_0_13} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_14; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_28 = {1'h0, allargs_0_14} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_15; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_30 = {1'h0, allargs_0_15} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_16; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_32 = {1'h0, allargs_0_16} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_17; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_34 = {1'h0, allargs_0_17} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_18; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_36 = {1'h0, allargs_0_18} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_19; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_38 = {1'h0, allargs_0_19} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_20; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_40 = {1'h0, allargs_0_20} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_21; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_42 = {1'h0, allargs_0_21} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_22; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_44 = {1'h0, allargs_0_22} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_23; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_46 = {1'h0, allargs_0_23} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_24; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_48 = {1'h0, allargs_0_24} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_25; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_50 = {1'h0, allargs_0_25} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_26; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_52 = {1'h0, allargs_0_26} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_27; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_54 = {1'h0, allargs_0_27} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_28; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_56 = {1'h0, allargs_0_28} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_29; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_58 = {1'h0, allargs_0_29} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_30; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_60 = {1'h0, allargs_0_30} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_31; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_62 = {1'h0, allargs_0_31} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_32; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_64 = {1'h0, allargs_0_32} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_33; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_66 = {1'h0, allargs_0_33} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_34; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_68 = {1'h0, allargs_0_34} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Logger.scala:38:38]
reg [5:0] read_start_index; // @[MemWriter32.scala:125:33]
wire [7:0] remapVecData_0; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_1; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_2; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_3; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_4; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_5; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_6; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_7; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_8; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_9; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_10; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_11; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_12; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_13; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_14; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_15; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_16; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_17; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_18; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_19; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_20; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_21; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_22; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_23; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_24; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_25; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_26; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_27; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_28; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_29; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_30; // @[MemWriter32.scala:127:26]
wire [7:0] remapVecData_31; // @[MemWriter32.scala:127:26]
wire remapVecValids_0; // @[MemWriter32.scala:128:28]
wire remapVecValids_1; // @[MemWriter32.scala:128:28]
wire remapVecValids_2; // @[MemWriter32.scala:128:28]
wire remapVecValids_3; // @[MemWriter32.scala:128:28]
wire remapVecValids_4; // @[MemWriter32.scala:128:28]
wire remapVecValids_5; // @[MemWriter32.scala:128:28]
wire remapVecValids_6; // @[MemWriter32.scala:128:28]
wire remapVecValids_7; // @[MemWriter32.scala:128:28]
wire remapVecValids_8; // @[MemWriter32.scala:128:28]
wire remapVecValids_9; // @[MemWriter32.scala:128:28]
wire remapVecValids_10; // @[MemWriter32.scala:128:28]
wire remapVecValids_11; // @[MemWriter32.scala:128:28]
wire remapVecValids_12; // @[MemWriter32.scala:128:28]
wire remapVecValids_13; // @[MemWriter32.scala:128:28]
wire remapVecValids_14; // @[MemWriter32.scala:128:28]
wire remapVecValids_15; // @[MemWriter32.scala:128:28]
wire remapVecValids_16; // @[MemWriter32.scala:128:28]
wire remapVecValids_17; // @[MemWriter32.scala:128:28]
wire remapVecValids_18; // @[MemWriter32.scala:128:28]
wire remapVecValids_19; // @[MemWriter32.scala:128:28]
wire remapVecValids_20; // @[MemWriter32.scala:128:28]
wire remapVecValids_21; // @[MemWriter32.scala:128:28]
wire remapVecValids_22; // @[MemWriter32.scala:128:28]
wire remapVecValids_23; // @[MemWriter32.scala:128:28]
wire remapVecValids_24; // @[MemWriter32.scala:128:28]
wire remapVecValids_25; // @[MemWriter32.scala:128:28]
wire remapVecValids_26; // @[MemWriter32.scala:128:28]
wire remapVecValids_27; // @[MemWriter32.scala:128:28]
wire remapVecValids_28; // @[MemWriter32.scala:128:28]
wire remapVecValids_29; // @[MemWriter32.scala:128:28]
wire remapVecValids_30; // @[MemWriter32.scala:128:28]
wire remapVecValids_31; // @[MemWriter32.scala:128:28]
wire _remapVecReadys_0_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_1_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_2_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_3_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_4_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_5_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_6_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_7_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_8_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_9_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_10_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_11_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_12_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_13_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_14_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_15_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_16_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_17_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_18_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_19_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_20_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_21_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_22_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_23_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_24_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_25_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_26_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_27_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_28_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_29_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_30_T_4; // @[MemWriter32.scala:233:61]
wire _remapVecReadys_31_T_4; // @[MemWriter32.scala:233:61]
wire remapVecReadys_0; // @[MemWriter32.scala:129:28]
wire remapVecReadys_1; // @[MemWriter32.scala:129:28]
wire remapVecReadys_2; // @[MemWriter32.scala:129:28]
wire remapVecReadys_3; // @[MemWriter32.scala:129:28]
wire remapVecReadys_4; // @[MemWriter32.scala:129:28]
wire remapVecReadys_5; // @[MemWriter32.scala:129:28]
wire remapVecReadys_6; // @[MemWriter32.scala:129:28]
wire remapVecReadys_7; // @[MemWriter32.scala:129:28]
wire remapVecReadys_8; // @[MemWriter32.scala:129:28]
wire remapVecReadys_9; // @[MemWriter32.scala:129:28]
wire remapVecReadys_10; // @[MemWriter32.scala:129:28]
wire remapVecReadys_11; // @[MemWriter32.scala:129:28]
wire remapVecReadys_12; // @[MemWriter32.scala:129:28]
wire remapVecReadys_13; // @[MemWriter32.scala:129:28]
wire remapVecReadys_14; // @[MemWriter32.scala:129:28]
wire remapVecReadys_15; // @[MemWriter32.scala:129:28]
wire remapVecReadys_16; // @[MemWriter32.scala:129:28]
wire remapVecReadys_17; // @[MemWriter32.scala:129:28]
wire remapVecReadys_18; // @[MemWriter32.scala:129:28]
wire remapVecReadys_19; // @[MemWriter32.scala:129:28]
wire remapVecReadys_20; // @[MemWriter32.scala:129:28]
wire remapVecReadys_21; // @[MemWriter32.scala:129:28]
wire remapVecReadys_22; // @[MemWriter32.scala:129:28]
wire remapVecReadys_23; // @[MemWriter32.scala:129:28]
wire remapVecReadys_24; // @[MemWriter32.scala:129:28]
wire remapVecReadys_25; // @[MemWriter32.scala:129:28]
wire remapVecReadys_26; // @[MemWriter32.scala:129:28]
wire remapVecReadys_27; // @[MemWriter32.scala:129:28]
wire remapVecReadys_28; // @[MemWriter32.scala:129:28]
wire remapVecReadys_29; // @[MemWriter32.scala:129:28]
wire remapVecReadys_30; // @[MemWriter32.scala:129:28]
wire remapVecReadys_31; // @[MemWriter32.scala:129:28]
wire [6:0] _remapindex_T = {1'h0, read_start_index}; // @[MemWriter32.scala:125:33, :132:33]
wire [6:0] _GEN_60 = _remapindex_T % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex = _GEN_60[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_0_T = remapindex[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_0_T = remapindex[4:0]; // @[MemWriter32.scala:132:54]
wire [31:0][7:0] _GEN_61 = {{mem_resp_queues_31_deq_bits}, {mem_resp_queues_30_deq_bits}, {mem_resp_queues_29_deq_bits}, {mem_resp_queues_28_deq_bits}, {mem_resp_queues_27_deq_bits}, {mem_resp_queues_26_deq_bits}, {mem_resp_queues_25_deq_bits}, {mem_resp_queues_24_deq_bits}, {mem_resp_queues_23_deq_bits}, {mem_resp_queues_22_deq_bits}, {mem_resp_queues_21_deq_bits}, {mem_resp_queues_20_deq_bits}, {mem_resp_queues_19_deq_bits}, {mem_resp_queues_18_deq_bits}, {mem_resp_queues_17_deq_bits}, {mem_resp_queues_16_deq_bits}, {mem_resp_queues_15_deq_bits}, {mem_resp_queues_14_deq_bits}, {mem_resp_queues_13_deq_bits}, {mem_resp_queues_12_deq_bits}, {mem_resp_queues_11_deq_bits}, {mem_resp_queues_10_deq_bits}, {mem_resp_queues_9_deq_bits}, {mem_resp_queues_8_deq_bits}, {mem_resp_queues_7_deq_bits}, {mem_resp_queues_6_deq_bits}, {mem_resp_queues_5_deq_bits}, {mem_resp_queues_4_deq_bits}, {mem_resp_queues_3_deq_bits}, {mem_resp_queues_2_deq_bits}, {mem_resp_queues_1_deq_bits}, {mem_resp_queues_0_deq_bits}}; // @[MemWriter32.scala:70:49, :133:27]
assign remapVecData_0 = _GEN_61[_remapVecData_0_T]; // @[MemWriter32.scala:127:26, :133:27]
wire [31:0] _GEN_62 = {{mem_resp_queues_31_deq_valid}, {mem_resp_queues_30_deq_valid}, {mem_resp_queues_29_deq_valid}, {mem_resp_queues_28_deq_valid}, {mem_resp_queues_27_deq_valid}, {mem_resp_queues_26_deq_valid}, {mem_resp_queues_25_deq_valid}, {mem_resp_queues_24_deq_valid}, {mem_resp_queues_23_deq_valid}, {mem_resp_queues_22_deq_valid}, {mem_resp_queues_21_deq_valid}, {mem_resp_queues_20_deq_valid}, {mem_resp_queues_19_deq_valid}, {mem_resp_queues_18_deq_valid}, {mem_resp_queues_17_deq_valid}, {mem_resp_queues_16_deq_valid}, {mem_resp_queues_15_deq_valid}, {mem_resp_queues_14_deq_valid}, {mem_resp_queues_13_deq_valid}, {mem_resp_queues_12_deq_valid}, {mem_resp_queues_11_deq_valid}, {mem_resp_queues_10_deq_valid}, {mem_resp_queues_9_deq_valid}, {mem_resp_queues_8_deq_valid}, {mem_resp_queues_7_deq_valid}, {mem_resp_queues_6_deq_valid}, {mem_resp_queues_5_deq_valid}, {mem_resp_queues_4_deq_valid}, {mem_resp_queues_3_deq_valid}, {mem_resp_queues_2_deq_valid}, {mem_resp_queues_1_deq_valid}, {mem_resp_queues_0_deq_valid}}; // @[MemWriter32.scala:70:49, :134:29]
assign remapVecValids_0 = _GEN_62[_remapVecValids_0_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_1 = _remapindex_T + 7'h1; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_63 = _remapindex_T_1 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_1 = _GEN_63[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_1_T = remapindex_1[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_1_T = remapindex_1[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_1 = _GEN_61[_remapVecData_1_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_1 = _GEN_62[_remapVecValids_1_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_2 = _remapindex_T + 7'h2; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_64 = _remapindex_T_2 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_2 = _GEN_64[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_2_T = remapindex_2[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_2_T = remapindex_2[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_2 = _GEN_61[_remapVecData_2_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_2 = _GEN_62[_remapVecValids_2_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_3 = _remapindex_T + 7'h3; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_65 = _remapindex_T_3 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_3 = _GEN_65[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_3_T = remapindex_3[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_3_T = remapindex_3[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_3 = _GEN_61[_remapVecData_3_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_3 = _GEN_62[_remapVecValids_3_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_4 = _remapindex_T + 7'h4; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_66 = _remapindex_T_4 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_4 = _GEN_66[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_4_T = remapindex_4[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_4_T = remapindex_4[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_4 = _GEN_61[_remapVecData_4_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_4 = _GEN_62[_remapVecValids_4_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_5 = _remapindex_T + 7'h5; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_67 = _remapindex_T_5 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_5 = _GEN_67[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_5_T = remapindex_5[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_5_T = remapindex_5[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_5 = _GEN_61[_remapVecData_5_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_5 = _GEN_62[_remapVecValids_5_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_6 = _remapindex_T + 7'h6; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_68 = _remapindex_T_6 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_6 = _GEN_68[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_6_T = remapindex_6[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_6_T = remapindex_6[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_6 = _GEN_61[_remapVecData_6_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_6 = _GEN_62[_remapVecValids_6_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_7 = _remapindex_T + 7'h7; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_69 = _remapindex_T_7 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_7 = _GEN_69[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_7_T = remapindex_7[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_7_T = remapindex_7[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_7 = _GEN_61[_remapVecData_7_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_7 = _GEN_62[_remapVecValids_7_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_8 = _remapindex_T + 7'h8; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_70 = _remapindex_T_8 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_8 = _GEN_70[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_8_T = remapindex_8[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_8_T = remapindex_8[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_8 = _GEN_61[_remapVecData_8_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_8 = _GEN_62[_remapVecValids_8_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_9 = _remapindex_T + 7'h9; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_71 = _remapindex_T_9 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_9 = _GEN_71[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_9_T = remapindex_9[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_9_T = remapindex_9[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_9 = _GEN_61[_remapVecData_9_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_9 = _GEN_62[_remapVecValids_9_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_10 = _remapindex_T + 7'hA; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_72 = _remapindex_T_10 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_10 = _GEN_72[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_10_T = remapindex_10[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_10_T = remapindex_10[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_10 = _GEN_61[_remapVecData_10_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_10 = _GEN_62[_remapVecValids_10_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_11 = _remapindex_T + 7'hB; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_73 = _remapindex_T_11 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_11 = _GEN_73[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_11_T = remapindex_11[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_11_T = remapindex_11[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_11 = _GEN_61[_remapVecData_11_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_11 = _GEN_62[_remapVecValids_11_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_12 = _remapindex_T + 7'hC; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_74 = _remapindex_T_12 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_12 = _GEN_74[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_12_T = remapindex_12[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_12_T = remapindex_12[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_12 = _GEN_61[_remapVecData_12_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_12 = _GEN_62[_remapVecValids_12_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_13 = _remapindex_T + 7'hD; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_75 = _remapindex_T_13 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_13 = _GEN_75[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_13_T = remapindex_13[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_13_T = remapindex_13[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_13 = _GEN_61[_remapVecData_13_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_13 = _GEN_62[_remapVecValids_13_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_14 = _remapindex_T + 7'hE; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_76 = _remapindex_T_14 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_14 = _GEN_76[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_14_T = remapindex_14[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_14_T = remapindex_14[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_14 = _GEN_61[_remapVecData_14_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_14 = _GEN_62[_remapVecValids_14_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_15 = _remapindex_T + 7'hF; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_77 = _remapindex_T_15 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_15 = _GEN_77[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_15_T = remapindex_15[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_15_T = remapindex_15[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_15 = _GEN_61[_remapVecData_15_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_15 = _GEN_62[_remapVecValids_15_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_16 = _remapindex_T + 7'h10; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_78 = _remapindex_T_16 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_16 = _GEN_78[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_16_T = remapindex_16[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_16_T = remapindex_16[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_16 = _GEN_61[_remapVecData_16_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_16 = _GEN_62[_remapVecValids_16_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_17 = _remapindex_T + 7'h11; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_79 = _remapindex_T_17 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_17 = _GEN_79[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_17_T = remapindex_17[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_17_T = remapindex_17[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_17 = _GEN_61[_remapVecData_17_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_17 = _GEN_62[_remapVecValids_17_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_18 = _remapindex_T + 7'h12; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_80 = _remapindex_T_18 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_18 = _GEN_80[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_18_T = remapindex_18[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_18_T = remapindex_18[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_18 = _GEN_61[_remapVecData_18_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_18 = _GEN_62[_remapVecValids_18_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_19 = _remapindex_T + 7'h13; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_81 = _remapindex_T_19 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_19 = _GEN_81[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_19_T = remapindex_19[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_19_T = remapindex_19[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_19 = _GEN_61[_remapVecData_19_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_19 = _GEN_62[_remapVecValids_19_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_20 = _remapindex_T + 7'h14; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_82 = _remapindex_T_20 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_20 = _GEN_82[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_20_T = remapindex_20[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_20_T = remapindex_20[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_20 = _GEN_61[_remapVecData_20_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_20 = _GEN_62[_remapVecValids_20_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_21 = _remapindex_T + 7'h15; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_83 = _remapindex_T_21 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_21 = _GEN_83[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_21_T = remapindex_21[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_21_T = remapindex_21[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_21 = _GEN_61[_remapVecData_21_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_21 = _GEN_62[_remapVecValids_21_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_22 = _remapindex_T + 7'h16; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_84 = _remapindex_T_22 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_22 = _GEN_84[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_22_T = remapindex_22[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_22_T = remapindex_22[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_22 = _GEN_61[_remapVecData_22_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_22 = _GEN_62[_remapVecValids_22_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_23 = _remapindex_T + 7'h17; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_85 = _remapindex_T_23 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_23 = _GEN_85[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_23_T = remapindex_23[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_23_T = remapindex_23[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_23 = _GEN_61[_remapVecData_23_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_23 = _GEN_62[_remapVecValids_23_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_24 = _remapindex_T + 7'h18; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_86 = _remapindex_T_24 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_24 = _GEN_86[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_24_T = remapindex_24[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_24_T = remapindex_24[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_24 = _GEN_61[_remapVecData_24_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_24 = _GEN_62[_remapVecValids_24_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_25 = _remapindex_T + 7'h19; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_87 = _remapindex_T_25 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_25 = _GEN_87[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_25_T = remapindex_25[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_25_T = remapindex_25[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_25 = _GEN_61[_remapVecData_25_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_25 = _GEN_62[_remapVecValids_25_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_26 = _remapindex_T + 7'h1A; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_88 = _remapindex_T_26 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_26 = _GEN_88[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_26_T = remapindex_26[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_26_T = remapindex_26[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_26 = _GEN_61[_remapVecData_26_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_26 = _GEN_62[_remapVecValids_26_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_27 = _remapindex_T + 7'h1B; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_89 = _remapindex_T_27 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_27 = _GEN_89[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_27_T = remapindex_27[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_27_T = remapindex_27[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_27 = _GEN_61[_remapVecData_27_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_27 = _GEN_62[_remapVecValids_27_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_28 = _remapindex_T + 7'h1C; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_90 = _remapindex_T_28 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_28 = _GEN_90[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_28_T = remapindex_28[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_28_T = remapindex_28[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_28 = _GEN_61[_remapVecData_28_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_28 = _GEN_62[_remapVecValids_28_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_29 = _remapindex_T + 7'h1D; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_91 = _remapindex_T_29 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_29 = _GEN_91[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_29_T = remapindex_29[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_29_T = remapindex_29[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_29 = _GEN_61[_remapVecData_29_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_29 = _GEN_62[_remapVecValids_29_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_30 = _remapindex_T + 7'h1E; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_92 = _remapindex_T_30 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_30 = _GEN_92[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_30_T = remapindex_30[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_30_T = remapindex_30[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_30 = _GEN_61[_remapVecData_30_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_30 = _GEN_62[_remapVecValids_30_T]; // @[MemWriter32.scala:128:28, :134:29]
wire [6:0] _remapindex_T_31 = _remapindex_T + 7'h1F; // @[MemWriter32.scala:132:33]
wire [6:0] _GEN_93 = _remapindex_T_31 % 7'h20; // @[MemWriter32.scala:132:{33,54}]
wire [5:0] remapindex_31 = _GEN_93[5:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecData_31_T = remapindex_31[4:0]; // @[MemWriter32.scala:132:54]
wire [4:0] _remapVecValids_31_T = remapindex_31[4:0]; // @[MemWriter32.scala:132:54]
assign remapVecData_31 = _GEN_61[_remapVecData_31_T]; // @[MemWriter32.scala:127:26, :133:27]
assign remapVecValids_31 = _GEN_62[_remapVecValids_31_T]; // @[MemWriter32.scala:128:28, :134:29]
assign mem_resp_queues_0_deq_ready = remapindex_31[4:0] == 5'h0 ? remapVecReadys_31 : remapindex_30[4:0] == 5'h0 ? remapVecReadys_30 : remapindex_29[4:0] == 5'h0 ? remapVecReadys_29 : remapindex_28[4:0] == 5'h0 ? remapVecReadys_28 : remapindex_27[4:0] == 5'h0 ? remapVecReadys_27 : remapindex_26[4:0] == 5'h0 ? remapVecReadys_26 : remapindex_25[4:0] == 5'h0 ? remapVecReadys_25 : remapindex_24[4:0] == 5'h0 ? remapVecReadys_24 : remapindex_23[4:0] == 5'h0 ? remapVecReadys_23 : remapindex_22[4:0] == 5'h0 ? remapVecReadys_22 : remapindex_21[4:0] == 5'h0 ? remapVecReadys_21 : remapindex_20[4:0] == 5'h0 ? remapVecReadys_20 : remapindex_19[4:0] == 5'h0 ? remapVecReadys_19 : remapindex_18[4:0] == 5'h0 ? remapVecReadys_18 : remapindex_17[4:0] == 5'h0 ? remapVecReadys_17 : remapindex_16[4:0] == 5'h0 ? remapVecReadys_16 : remapindex_15[4:0] == 5'h0 ? remapVecReadys_15 : remapindex_14[4:0] == 5'h0 ? remapVecReadys_14 : remapindex_13[4:0] == 5'h0 ? remapVecReadys_13 : remapindex_12[4:0] == 5'h0 ? remapVecReadys_12 : remapindex_11[4:0] == 5'h0 ? remapVecReadys_11 : remapindex_10[4:0] == 5'h0 ? remapVecReadys_10 : remapindex_9[4:0] == 5'h0 ? remapVecReadys_9 : remapindex_8[4:0] == 5'h0 ? remapVecReadys_8 : remapindex_7[4:0] == 5'h0 ? remapVecReadys_7 : remapindex_6[4:0] == 5'h0 ? remapVecReadys_6 : remapindex_5[4:0] == 5'h0 ? remapVecReadys_5 : remapindex_4[4:0] == 5'h0 ? remapVecReadys_4 : remapindex_3[4:0] == 5'h0 ? remapVecReadys_3 : remapindex_2[4:0] == 5'h0 ? remapVecReadys_2 : remapindex_1[4:0] == 5'h0 ? remapVecReadys_1 : remapindex[4:0] == 5'h0 & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_1_deq_ready = remapindex_31[4:0] == 5'h1 ? remapVecReadys_31 : remapindex_30[4:0] == 5'h1 ? remapVecReadys_30 : remapindex_29[4:0] == 5'h1 ? remapVecReadys_29 : remapindex_28[4:0] == 5'h1 ? remapVecReadys_28 : remapindex_27[4:0] == 5'h1 ? remapVecReadys_27 : remapindex_26[4:0] == 5'h1 ? remapVecReadys_26 : remapindex_25[4:0] == 5'h1 ? remapVecReadys_25 : remapindex_24[4:0] == 5'h1 ? remapVecReadys_24 : remapindex_23[4:0] == 5'h1 ? remapVecReadys_23 : remapindex_22[4:0] == 5'h1 ? remapVecReadys_22 : remapindex_21[4:0] == 5'h1 ? remapVecReadys_21 : remapindex_20[4:0] == 5'h1 ? remapVecReadys_20 : remapindex_19[4:0] == 5'h1 ? remapVecReadys_19 : remapindex_18[4:0] == 5'h1 ? remapVecReadys_18 : remapindex_17[4:0] == 5'h1 ? remapVecReadys_17 : remapindex_16[4:0] == 5'h1 ? remapVecReadys_16 : remapindex_15[4:0] == 5'h1 ? remapVecReadys_15 : remapindex_14[4:0] == 5'h1 ? remapVecReadys_14 : remapindex_13[4:0] == 5'h1 ? remapVecReadys_13 : remapindex_12[4:0] == 5'h1 ? remapVecReadys_12 : remapindex_11[4:0] == 5'h1 ? remapVecReadys_11 : remapindex_10[4:0] == 5'h1 ? remapVecReadys_10 : remapindex_9[4:0] == 5'h1 ? remapVecReadys_9 : remapindex_8[4:0] == 5'h1 ? remapVecReadys_8 : remapindex_7[4:0] == 5'h1 ? remapVecReadys_7 : remapindex_6[4:0] == 5'h1 ? remapVecReadys_6 : remapindex_5[4:0] == 5'h1 ? remapVecReadys_5 : remapindex_4[4:0] == 5'h1 ? remapVecReadys_4 : remapindex_3[4:0] == 5'h1 ? remapVecReadys_3 : remapindex_2[4:0] == 5'h1 ? remapVecReadys_2 : remapindex_1[4:0] == 5'h1 ? remapVecReadys_1 : remapindex[4:0] == 5'h1 & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_2_deq_ready = remapindex_31[4:0] == 5'h2 ? remapVecReadys_31 : remapindex_30[4:0] == 5'h2 ? remapVecReadys_30 : remapindex_29[4:0] == 5'h2 ? remapVecReadys_29 : remapindex_28[4:0] == 5'h2 ? remapVecReadys_28 : remapindex_27[4:0] == 5'h2 ? remapVecReadys_27 : remapindex_26[4:0] == 5'h2 ? remapVecReadys_26 : remapindex_25[4:0] == 5'h2 ? remapVecReadys_25 : remapindex_24[4:0] == 5'h2 ? remapVecReadys_24 : remapindex_23[4:0] == 5'h2 ? remapVecReadys_23 : remapindex_22[4:0] == 5'h2 ? remapVecReadys_22 : remapindex_21[4:0] == 5'h2 ? remapVecReadys_21 : remapindex_20[4:0] == 5'h2 ? remapVecReadys_20 : remapindex_19[4:0] == 5'h2 ? remapVecReadys_19 : remapindex_18[4:0] == 5'h2 ? remapVecReadys_18 : remapindex_17[4:0] == 5'h2 ? remapVecReadys_17 : remapindex_16[4:0] == 5'h2 ? remapVecReadys_16 : remapindex_15[4:0] == 5'h2 ? remapVecReadys_15 : remapindex_14[4:0] == 5'h2 ? remapVecReadys_14 : remapindex_13[4:0] == 5'h2 ? remapVecReadys_13 : remapindex_12[4:0] == 5'h2 ? remapVecReadys_12 : remapindex_11[4:0] == 5'h2 ? remapVecReadys_11 : remapindex_10[4:0] == 5'h2 ? remapVecReadys_10 : remapindex_9[4:0] == 5'h2 ? remapVecReadys_9 : remapindex_8[4:0] == 5'h2 ? remapVecReadys_8 : remapindex_7[4:0] == 5'h2 ? remapVecReadys_7 : remapindex_6[4:0] == 5'h2 ? remapVecReadys_6 : remapindex_5[4:0] == 5'h2 ? remapVecReadys_5 : remapindex_4[4:0] == 5'h2 ? remapVecReadys_4 : remapindex_3[4:0] == 5'h2 ? remapVecReadys_3 : remapindex_2[4:0] == 5'h2 ? remapVecReadys_2 : remapindex_1[4:0] == 5'h2 ? remapVecReadys_1 : remapindex[4:0] == 5'h2 & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_3_deq_ready = remapindex_31[4:0] == 5'h3 ? remapVecReadys_31 : remapindex_30[4:0] == 5'h3 ? remapVecReadys_30 : remapindex_29[4:0] == 5'h3 ? remapVecReadys_29 : remapindex_28[4:0] == 5'h3 ? remapVecReadys_28 : remapindex_27[4:0] == 5'h3 ? remapVecReadys_27 : remapindex_26[4:0] == 5'h3 ? remapVecReadys_26 : remapindex_25[4:0] == 5'h3 ? remapVecReadys_25 : remapindex_24[4:0] == 5'h3 ? remapVecReadys_24 : remapindex_23[4:0] == 5'h3 ? remapVecReadys_23 : remapindex_22[4:0] == 5'h3 ? remapVecReadys_22 : remapindex_21[4:0] == 5'h3 ? remapVecReadys_21 : remapindex_20[4:0] == 5'h3 ? remapVecReadys_20 : remapindex_19[4:0] == 5'h3 ? remapVecReadys_19 : remapindex_18[4:0] == 5'h3 ? remapVecReadys_18 : remapindex_17[4:0] == 5'h3 ? remapVecReadys_17 : remapindex_16[4:0] == 5'h3 ? remapVecReadys_16 : remapindex_15[4:0] == 5'h3 ? remapVecReadys_15 : remapindex_14[4:0] == 5'h3 ? remapVecReadys_14 : remapindex_13[4:0] == 5'h3 ? remapVecReadys_13 : remapindex_12[4:0] == 5'h3 ? remapVecReadys_12 : remapindex_11[4:0] == 5'h3 ? remapVecReadys_11 : remapindex_10[4:0] == 5'h3 ? remapVecReadys_10 : remapindex_9[4:0] == 5'h3 ? remapVecReadys_9 : remapindex_8[4:0] == 5'h3 ? remapVecReadys_8 : remapindex_7[4:0] == 5'h3 ? remapVecReadys_7 : remapindex_6[4:0] == 5'h3 ? remapVecReadys_6 : remapindex_5[4:0] == 5'h3 ? remapVecReadys_5 : remapindex_4[4:0] == 5'h3 ? remapVecReadys_4 : remapindex_3[4:0] == 5'h3 ? remapVecReadys_3 : remapindex_2[4:0] == 5'h3 ? remapVecReadys_2 : remapindex_1[4:0] == 5'h3 ? remapVecReadys_1 : remapindex[4:0] == 5'h3 & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_4_deq_ready = remapindex_31[4:0] == 5'h4 ? remapVecReadys_31 : remapindex_30[4:0] == 5'h4 ? remapVecReadys_30 : remapindex_29[4:0] == 5'h4 ? remapVecReadys_29 : remapindex_28[4:0] == 5'h4 ? remapVecReadys_28 : remapindex_27[4:0] == 5'h4 ? remapVecReadys_27 : remapindex_26[4:0] == 5'h4 ? remapVecReadys_26 : remapindex_25[4:0] == 5'h4 ? remapVecReadys_25 : remapindex_24[4:0] == 5'h4 ? remapVecReadys_24 : remapindex_23[4:0] == 5'h4 ? remapVecReadys_23 : remapindex_22[4:0] == 5'h4 ? remapVecReadys_22 : remapindex_21[4:0] == 5'h4 ? remapVecReadys_21 : remapindex_20[4:0] == 5'h4 ? remapVecReadys_20 : remapindex_19[4:0] == 5'h4 ? remapVecReadys_19 : remapindex_18[4:0] == 5'h4 ? remapVecReadys_18 : remapindex_17[4:0] == 5'h4 ? remapVecReadys_17 : remapindex_16[4:0] == 5'h4 ? remapVecReadys_16 : remapindex_15[4:0] == 5'h4 ? remapVecReadys_15 : remapindex_14[4:0] == 5'h4 ? remapVecReadys_14 : remapindex_13[4:0] == 5'h4 ? remapVecReadys_13 : remapindex_12[4:0] == 5'h4 ? remapVecReadys_12 : remapindex_11[4:0] == 5'h4 ? remapVecReadys_11 : remapindex_10[4:0] == 5'h4 ? remapVecReadys_10 : remapindex_9[4:0] == 5'h4 ? remapVecReadys_9 : remapindex_8[4:0] == 5'h4 ? remapVecReadys_8 : remapindex_7[4:0] == 5'h4 ? remapVecReadys_7 : remapindex_6[4:0] == 5'h4 ? remapVecReadys_6 : remapindex_5[4:0] == 5'h4 ? remapVecReadys_5 : remapindex_4[4:0] == 5'h4 ? remapVecReadys_4 : remapindex_3[4:0] == 5'h4 ? remapVecReadys_3 : remapindex_2[4:0] == 5'h4 ? remapVecReadys_2 : remapindex_1[4:0] == 5'h4 ? remapVecReadys_1 : remapindex[4:0] == 5'h4 & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_5_deq_ready = remapindex_31[4:0] == 5'h5 ? remapVecReadys_31 : remapindex_30[4:0] == 5'h5 ? remapVecReadys_30 : remapindex_29[4:0] == 5'h5 ? remapVecReadys_29 : remapindex_28[4:0] == 5'h5 ? remapVecReadys_28 : remapindex_27[4:0] == 5'h5 ? remapVecReadys_27 : remapindex_26[4:0] == 5'h5 ? remapVecReadys_26 : remapindex_25[4:0] == 5'h5 ? remapVecReadys_25 : remapindex_24[4:0] == 5'h5 ? remapVecReadys_24 : remapindex_23[4:0] == 5'h5 ? remapVecReadys_23 : remapindex_22[4:0] == 5'h5 ? remapVecReadys_22 : remapindex_21[4:0] == 5'h5 ? remapVecReadys_21 : remapindex_20[4:0] == 5'h5 ? remapVecReadys_20 : remapindex_19[4:0] == 5'h5 ? remapVecReadys_19 : remapindex_18[4:0] == 5'h5 ? remapVecReadys_18 : remapindex_17[4:0] == 5'h5 ? remapVecReadys_17 : remapindex_16[4:0] == 5'h5 ? remapVecReadys_16 : remapindex_15[4:0] == 5'h5 ? remapVecReadys_15 : remapindex_14[4:0] == 5'h5 ? remapVecReadys_14 : remapindex_13[4:0] == 5'h5 ? remapVecReadys_13 : remapindex_12[4:0] == 5'h5 ? remapVecReadys_12 : remapindex_11[4:0] == 5'h5 ? remapVecReadys_11 : remapindex_10[4:0] == 5'h5 ? remapVecReadys_10 : remapindex_9[4:0] == 5'h5 ? remapVecReadys_9 : remapindex_8[4:0] == 5'h5 ? remapVecReadys_8 : remapindex_7[4:0] == 5'h5 ? remapVecReadys_7 : remapindex_6[4:0] == 5'h5 ? remapVecReadys_6 : remapindex_5[4:0] == 5'h5 ? remapVecReadys_5 : remapindex_4[4:0] == 5'h5 ? remapVecReadys_4 : remapindex_3[4:0] == 5'h5 ? remapVecReadys_3 : remapindex_2[4:0] == 5'h5 ? remapVecReadys_2 : remapindex_1[4:0] == 5'h5 ? remapVecReadys_1 : remapindex[4:0] == 5'h5 & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_6_deq_ready = remapindex_31[4:0] == 5'h6 ? remapVecReadys_31 : remapindex_30[4:0] == 5'h6 ? remapVecReadys_30 : remapindex_29[4:0] == 5'h6 ? remapVecReadys_29 : remapindex_28[4:0] == 5'h6 ? remapVecReadys_28 : remapindex_27[4:0] == 5'h6 ? remapVecReadys_27 : remapindex_26[4:0] == 5'h6 ? remapVecReadys_26 : remapindex_25[4:0] == 5'h6 ? remapVecReadys_25 : remapindex_24[4:0] == 5'h6 ? remapVecReadys_24 : remapindex_23[4:0] == 5'h6 ? remapVecReadys_23 : remapindex_22[4:0] == 5'h6 ? remapVecReadys_22 : remapindex_21[4:0] == 5'h6 ? remapVecReadys_21 : remapindex_20[4:0] == 5'h6 ? remapVecReadys_20 : remapindex_19[4:0] == 5'h6 ? remapVecReadys_19 : remapindex_18[4:0] == 5'h6 ? remapVecReadys_18 : remapindex_17[4:0] == 5'h6 ? remapVecReadys_17 : remapindex_16[4:0] == 5'h6 ? remapVecReadys_16 : remapindex_15[4:0] == 5'h6 ? remapVecReadys_15 : remapindex_14[4:0] == 5'h6 ? remapVecReadys_14 : remapindex_13[4:0] == 5'h6 ? remapVecReadys_13 : remapindex_12[4:0] == 5'h6 ? remapVecReadys_12 : remapindex_11[4:0] == 5'h6 ? remapVecReadys_11 : remapindex_10[4:0] == 5'h6 ? remapVecReadys_10 : remapindex_9[4:0] == 5'h6 ? remapVecReadys_9 : remapindex_8[4:0] == 5'h6 ? remapVecReadys_8 : remapindex_7[4:0] == 5'h6 ? remapVecReadys_7 : remapindex_6[4:0] == 5'h6 ? remapVecReadys_6 : remapindex_5[4:0] == 5'h6 ? remapVecReadys_5 : remapindex_4[4:0] == 5'h6 ? remapVecReadys_4 : remapindex_3[4:0] == 5'h6 ? remapVecReadys_3 : remapindex_2[4:0] == 5'h6 ? remapVecReadys_2 : remapindex_1[4:0] == 5'h6 ? remapVecReadys_1 : remapindex[4:0] == 5'h6 & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_7_deq_ready = remapindex_31[4:0] == 5'h7 ? remapVecReadys_31 : remapindex_30[4:0] == 5'h7 ? remapVecReadys_30 : remapindex_29[4:0] == 5'h7 ? remapVecReadys_29 : remapindex_28[4:0] == 5'h7 ? remapVecReadys_28 : remapindex_27[4:0] == 5'h7 ? remapVecReadys_27 : remapindex_26[4:0] == 5'h7 ? remapVecReadys_26 : remapindex_25[4:0] == 5'h7 ? remapVecReadys_25 : remapindex_24[4:0] == 5'h7 ? remapVecReadys_24 : remapindex_23[4:0] == 5'h7 ? remapVecReadys_23 : remapindex_22[4:0] == 5'h7 ? remapVecReadys_22 : remapindex_21[4:0] == 5'h7 ? remapVecReadys_21 : remapindex_20[4:0] == 5'h7 ? remapVecReadys_20 : remapindex_19[4:0] == 5'h7 ? remapVecReadys_19 : remapindex_18[4:0] == 5'h7 ? remapVecReadys_18 : remapindex_17[4:0] == 5'h7 ? remapVecReadys_17 : remapindex_16[4:0] == 5'h7 ? remapVecReadys_16 : remapindex_15[4:0] == 5'h7 ? remapVecReadys_15 : remapindex_14[4:0] == 5'h7 ? remapVecReadys_14 : remapindex_13[4:0] == 5'h7 ? remapVecReadys_13 : remapindex_12[4:0] == 5'h7 ? remapVecReadys_12 : remapindex_11[4:0] == 5'h7 ? remapVecReadys_11 : remapindex_10[4:0] == 5'h7 ? remapVecReadys_10 : remapindex_9[4:0] == 5'h7 ? remapVecReadys_9 : remapindex_8[4:0] == 5'h7 ? remapVecReadys_8 : remapindex_7[4:0] == 5'h7 ? remapVecReadys_7 : remapindex_6[4:0] == 5'h7 ? remapVecReadys_6 : remapindex_5[4:0] == 5'h7 ? remapVecReadys_5 : remapindex_4[4:0] == 5'h7 ? remapVecReadys_4 : remapindex_3[4:0] == 5'h7 ? remapVecReadys_3 : remapindex_2[4:0] == 5'h7 ? remapVecReadys_2 : remapindex_1[4:0] == 5'h7 ? remapVecReadys_1 : remapindex[4:0] == 5'h7 & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_8_deq_ready = remapindex_31[4:0] == 5'h8 ? remapVecReadys_31 : remapindex_30[4:0] == 5'h8 ? remapVecReadys_30 : remapindex_29[4:0] == 5'h8 ? remapVecReadys_29 : remapindex_28[4:0] == 5'h8 ? remapVecReadys_28 : remapindex_27[4:0] == 5'h8 ? remapVecReadys_27 : remapindex_26[4:0] == 5'h8 ? remapVecReadys_26 : remapindex_25[4:0] == 5'h8 ? remapVecReadys_25 : remapindex_24[4:0] == 5'h8 ? remapVecReadys_24 : remapindex_23[4:0] == 5'h8 ? remapVecReadys_23 : remapindex_22[4:0] == 5'h8 ? remapVecReadys_22 : remapindex_21[4:0] == 5'h8 ? remapVecReadys_21 : remapindex_20[4:0] == 5'h8 ? remapVecReadys_20 : remapindex_19[4:0] == 5'h8 ? remapVecReadys_19 : remapindex_18[4:0] == 5'h8 ? remapVecReadys_18 : remapindex_17[4:0] == 5'h8 ? remapVecReadys_17 : remapindex_16[4:0] == 5'h8 ? remapVecReadys_16 : remapindex_15[4:0] == 5'h8 ? remapVecReadys_15 : remapindex_14[4:0] == 5'h8 ? remapVecReadys_14 : remapindex_13[4:0] == 5'h8 ? remapVecReadys_13 : remapindex_12[4:0] == 5'h8 ? remapVecReadys_12 : remapindex_11[4:0] == 5'h8 ? remapVecReadys_11 : remapindex_10[4:0] == 5'h8 ? remapVecReadys_10 : remapindex_9[4:0] == 5'h8 ? remapVecReadys_9 : remapindex_8[4:0] == 5'h8 ? remapVecReadys_8 : remapindex_7[4:0] == 5'h8 ? remapVecReadys_7 : remapindex_6[4:0] == 5'h8 ? remapVecReadys_6 : remapindex_5[4:0] == 5'h8 ? remapVecReadys_5 : remapindex_4[4:0] == 5'h8 ? remapVecReadys_4 : remapindex_3[4:0] == 5'h8 ? remapVecReadys_3 : remapindex_2[4:0] == 5'h8 ? remapVecReadys_2 : remapindex_1[4:0] == 5'h8 ? remapVecReadys_1 : remapindex[4:0] == 5'h8 & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_9_deq_ready = remapindex_31[4:0] == 5'h9 ? remapVecReadys_31 : remapindex_30[4:0] == 5'h9 ? remapVecReadys_30 : remapindex_29[4:0] == 5'h9 ? remapVecReadys_29 : remapindex_28[4:0] == 5'h9 ? remapVecReadys_28 : remapindex_27[4:0] == 5'h9 ? remapVecReadys_27 : remapindex_26[4:0] == 5'h9 ? remapVecReadys_26 : remapindex_25[4:0] == 5'h9 ? remapVecReadys_25 : remapindex_24[4:0] == 5'h9 ? remapVecReadys_24 : remapindex_23[4:0] == 5'h9 ? remapVecReadys_23 : remapindex_22[4:0] == 5'h9 ? remapVecReadys_22 : remapindex_21[4:0] == 5'h9 ? remapVecReadys_21 : remapindex_20[4:0] == 5'h9 ? remapVecReadys_20 : remapindex_19[4:0] == 5'h9 ? remapVecReadys_19 : remapindex_18[4:0] == 5'h9 ? remapVecReadys_18 : remapindex_17[4:0] == 5'h9 ? remapVecReadys_17 : remapindex_16[4:0] == 5'h9 ? remapVecReadys_16 : remapindex_15[4:0] == 5'h9 ? remapVecReadys_15 : remapindex_14[4:0] == 5'h9 ? remapVecReadys_14 : remapindex_13[4:0] == 5'h9 ? remapVecReadys_13 : remapindex_12[4:0] == 5'h9 ? remapVecReadys_12 : remapindex_11[4:0] == 5'h9 ? remapVecReadys_11 : remapindex_10[4:0] == 5'h9 ? remapVecReadys_10 : remapindex_9[4:0] == 5'h9 ? remapVecReadys_9 : remapindex_8[4:0] == 5'h9 ? remapVecReadys_8 : remapindex_7[4:0] == 5'h9 ? remapVecReadys_7 : remapindex_6[4:0] == 5'h9 ? remapVecReadys_6 : remapindex_5[4:0] == 5'h9 ? remapVecReadys_5 : remapindex_4[4:0] == 5'h9 ? remapVecReadys_4 : remapindex_3[4:0] == 5'h9 ? remapVecReadys_3 : remapindex_2[4:0] == 5'h9 ? remapVecReadys_2 : remapindex_1[4:0] == 5'h9 ? remapVecReadys_1 : remapindex[4:0] == 5'h9 & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_10_deq_ready = remapindex_31[4:0] == 5'hA ? remapVecReadys_31 : remapindex_30[4:0] == 5'hA ? remapVecReadys_30 : remapindex_29[4:0] == 5'hA ? remapVecReadys_29 : remapindex_28[4:0] == 5'hA ? remapVecReadys_28 : remapindex_27[4:0] == 5'hA ? remapVecReadys_27 : remapindex_26[4:0] == 5'hA ? remapVecReadys_26 : remapindex_25[4:0] == 5'hA ? remapVecReadys_25 : remapindex_24[4:0] == 5'hA ? remapVecReadys_24 : remapindex_23[4:0] == 5'hA ? remapVecReadys_23 : remapindex_22[4:0] == 5'hA ? remapVecReadys_22 : remapindex_21[4:0] == 5'hA ? remapVecReadys_21 : remapindex_20[4:0] == 5'hA ? remapVecReadys_20 : remapindex_19[4:0] == 5'hA ? remapVecReadys_19 : remapindex_18[4:0] == 5'hA ? remapVecReadys_18 : remapindex_17[4:0] == 5'hA ? remapVecReadys_17 : remapindex_16[4:0] == 5'hA ? remapVecReadys_16 : remapindex_15[4:0] == 5'hA ? remapVecReadys_15 : remapindex_14[4:0] == 5'hA ? remapVecReadys_14 : remapindex_13[4:0] == 5'hA ? remapVecReadys_13 : remapindex_12[4:0] == 5'hA ? remapVecReadys_12 : remapindex_11[4:0] == 5'hA ? remapVecReadys_11 : remapindex_10[4:0] == 5'hA ? remapVecReadys_10 : remapindex_9[4:0] == 5'hA ? remapVecReadys_9 : remapindex_8[4:0] == 5'hA ? remapVecReadys_8 : remapindex_7[4:0] == 5'hA ? remapVecReadys_7 : remapindex_6[4:0] == 5'hA ? remapVecReadys_6 : remapindex_5[4:0] == 5'hA ? remapVecReadys_5 : remapindex_4[4:0] == 5'hA ? remapVecReadys_4 : remapindex_3[4:0] == 5'hA ? remapVecReadys_3 : remapindex_2[4:0] == 5'hA ? remapVecReadys_2 : remapindex_1[4:0] == 5'hA ? remapVecReadys_1 : remapindex[4:0] == 5'hA & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_11_deq_ready = remapindex_31[4:0] == 5'hB ? remapVecReadys_31 : remapindex_30[4:0] == 5'hB ? remapVecReadys_30 : remapindex_29[4:0] == 5'hB ? remapVecReadys_29 : remapindex_28[4:0] == 5'hB ? remapVecReadys_28 : remapindex_27[4:0] == 5'hB ? remapVecReadys_27 : remapindex_26[4:0] == 5'hB ? remapVecReadys_26 : remapindex_25[4:0] == 5'hB ? remapVecReadys_25 : remapindex_24[4:0] == 5'hB ? remapVecReadys_24 : remapindex_23[4:0] == 5'hB ? remapVecReadys_23 : remapindex_22[4:0] == 5'hB ? remapVecReadys_22 : remapindex_21[4:0] == 5'hB ? remapVecReadys_21 : remapindex_20[4:0] == 5'hB ? remapVecReadys_20 : remapindex_19[4:0] == 5'hB ? remapVecReadys_19 : remapindex_18[4:0] == 5'hB ? remapVecReadys_18 : remapindex_17[4:0] == 5'hB ? remapVecReadys_17 : remapindex_16[4:0] == 5'hB ? remapVecReadys_16 : remapindex_15[4:0] == 5'hB ? remapVecReadys_15 : remapindex_14[4:0] == 5'hB ? remapVecReadys_14 : remapindex_13[4:0] == 5'hB ? remapVecReadys_13 : remapindex_12[4:0] == 5'hB ? remapVecReadys_12 : remapindex_11[4:0] == 5'hB ? remapVecReadys_11 : remapindex_10[4:0] == 5'hB ? remapVecReadys_10 : remapindex_9[4:0] == 5'hB ? remapVecReadys_9 : remapindex_8[4:0] == 5'hB ? remapVecReadys_8 : remapindex_7[4:0] == 5'hB ? remapVecReadys_7 : remapindex_6[4:0] == 5'hB ? remapVecReadys_6 : remapindex_5[4:0] == 5'hB ? remapVecReadys_5 : remapindex_4[4:0] == 5'hB ? remapVecReadys_4 : remapindex_3[4:0] == 5'hB ? remapVecReadys_3 : remapindex_2[4:0] == 5'hB ? remapVecReadys_2 : remapindex_1[4:0] == 5'hB ? remapVecReadys_1 : remapindex[4:0] == 5'hB & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_12_deq_ready = remapindex_31[4:0] == 5'hC ? remapVecReadys_31 : remapindex_30[4:0] == 5'hC ? remapVecReadys_30 : remapindex_29[4:0] == 5'hC ? remapVecReadys_29 : remapindex_28[4:0] == 5'hC ? remapVecReadys_28 : remapindex_27[4:0] == 5'hC ? remapVecReadys_27 : remapindex_26[4:0] == 5'hC ? remapVecReadys_26 : remapindex_25[4:0] == 5'hC ? remapVecReadys_25 : remapindex_24[4:0] == 5'hC ? remapVecReadys_24 : remapindex_23[4:0] == 5'hC ? remapVecReadys_23 : remapindex_22[4:0] == 5'hC ? remapVecReadys_22 : remapindex_21[4:0] == 5'hC ? remapVecReadys_21 : remapindex_20[4:0] == 5'hC ? remapVecReadys_20 : remapindex_19[4:0] == 5'hC ? remapVecReadys_19 : remapindex_18[4:0] == 5'hC ? remapVecReadys_18 : remapindex_17[4:0] == 5'hC ? remapVecReadys_17 : remapindex_16[4:0] == 5'hC ? remapVecReadys_16 : remapindex_15[4:0] == 5'hC ? remapVecReadys_15 : remapindex_14[4:0] == 5'hC ? remapVecReadys_14 : remapindex_13[4:0] == 5'hC ? remapVecReadys_13 : remapindex_12[4:0] == 5'hC ? remapVecReadys_12 : remapindex_11[4:0] == 5'hC ? remapVecReadys_11 : remapindex_10[4:0] == 5'hC ? remapVecReadys_10 : remapindex_9[4:0] == 5'hC ? remapVecReadys_9 : remapindex_8[4:0] == 5'hC ? remapVecReadys_8 : remapindex_7[4:0] == 5'hC ? remapVecReadys_7 : remapindex_6[4:0] == 5'hC ? remapVecReadys_6 : remapindex_5[4:0] == 5'hC ? remapVecReadys_5 : remapindex_4[4:0] == 5'hC ? remapVecReadys_4 : remapindex_3[4:0] == 5'hC ? remapVecReadys_3 : remapindex_2[4:0] == 5'hC ? remapVecReadys_2 : remapindex_1[4:0] == 5'hC ? remapVecReadys_1 : remapindex[4:0] == 5'hC & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_13_deq_ready = remapindex_31[4:0] == 5'hD ? remapVecReadys_31 : remapindex_30[4:0] == 5'hD ? remapVecReadys_30 : remapindex_29[4:0] == 5'hD ? remapVecReadys_29 : remapindex_28[4:0] == 5'hD ? remapVecReadys_28 : remapindex_27[4:0] == 5'hD ? remapVecReadys_27 : remapindex_26[4:0] == 5'hD ? remapVecReadys_26 : remapindex_25[4:0] == 5'hD ? remapVecReadys_25 : remapindex_24[4:0] == 5'hD ? remapVecReadys_24 : remapindex_23[4:0] == 5'hD ? remapVecReadys_23 : remapindex_22[4:0] == 5'hD ? remapVecReadys_22 : remapindex_21[4:0] == 5'hD ? remapVecReadys_21 : remapindex_20[4:0] == 5'hD ? remapVecReadys_20 : remapindex_19[4:0] == 5'hD ? remapVecReadys_19 : remapindex_18[4:0] == 5'hD ? remapVecReadys_18 : remapindex_17[4:0] == 5'hD ? remapVecReadys_17 : remapindex_16[4:0] == 5'hD ? remapVecReadys_16 : remapindex_15[4:0] == 5'hD ? remapVecReadys_15 : remapindex_14[4:0] == 5'hD ? remapVecReadys_14 : remapindex_13[4:0] == 5'hD ? remapVecReadys_13 : remapindex_12[4:0] == 5'hD ? remapVecReadys_12 : remapindex_11[4:0] == 5'hD ? remapVecReadys_11 : remapindex_10[4:0] == 5'hD ? remapVecReadys_10 : remapindex_9[4:0] == 5'hD ? remapVecReadys_9 : remapindex_8[4:0] == 5'hD ? remapVecReadys_8 : remapindex_7[4:0] == 5'hD ? remapVecReadys_7 : remapindex_6[4:0] == 5'hD ? remapVecReadys_6 : remapindex_5[4:0] == 5'hD ? remapVecReadys_5 : remapindex_4[4:0] == 5'hD ? remapVecReadys_4 : remapindex_3[4:0] == 5'hD ? remapVecReadys_3 : remapindex_2[4:0] == 5'hD ? remapVecReadys_2 : remapindex_1[4:0] == 5'hD ? remapVecReadys_1 : remapindex[4:0] == 5'hD & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_14_deq_ready = remapindex_31[4:0] == 5'hE ? remapVecReadys_31 : remapindex_30[4:0] == 5'hE ? remapVecReadys_30 : remapindex_29[4:0] == 5'hE ? remapVecReadys_29 : remapindex_28[4:0] == 5'hE ? remapVecReadys_28 : remapindex_27[4:0] == 5'hE ? remapVecReadys_27 : remapindex_26[4:0] == 5'hE ? remapVecReadys_26 : remapindex_25[4:0] == 5'hE ? remapVecReadys_25 : remapindex_24[4:0] == 5'hE ? remapVecReadys_24 : remapindex_23[4:0] == 5'hE ? remapVecReadys_23 : remapindex_22[4:0] == 5'hE ? remapVecReadys_22 : remapindex_21[4:0] == 5'hE ? remapVecReadys_21 : remapindex_20[4:0] == 5'hE ? remapVecReadys_20 : remapindex_19[4:0] == 5'hE ? remapVecReadys_19 : remapindex_18[4:0] == 5'hE ? remapVecReadys_18 : remapindex_17[4:0] == 5'hE ? remapVecReadys_17 : remapindex_16[4:0] == 5'hE ? remapVecReadys_16 : remapindex_15[4:0] == 5'hE ? remapVecReadys_15 : remapindex_14[4:0] == 5'hE ? remapVecReadys_14 : remapindex_13[4:0] == 5'hE ? remapVecReadys_13 : remapindex_12[4:0] == 5'hE ? remapVecReadys_12 : remapindex_11[4:0] == 5'hE ? remapVecReadys_11 : remapindex_10[4:0] == 5'hE ? remapVecReadys_10 : remapindex_9[4:0] == 5'hE ? remapVecReadys_9 : remapindex_8[4:0] == 5'hE ? remapVecReadys_8 : remapindex_7[4:0] == 5'hE ? remapVecReadys_7 : remapindex_6[4:0] == 5'hE ? remapVecReadys_6 : remapindex_5[4:0] == 5'hE ? remapVecReadys_5 : remapindex_4[4:0] == 5'hE ? remapVecReadys_4 : remapindex_3[4:0] == 5'hE ? remapVecReadys_3 : remapindex_2[4:0] == 5'hE ? remapVecReadys_2 : remapindex_1[4:0] == 5'hE ? remapVecReadys_1 : remapindex[4:0] == 5'hE & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_15_deq_ready = remapindex_31[4:0] == 5'hF ? remapVecReadys_31 : remapindex_30[4:0] == 5'hF ? remapVecReadys_30 : remapindex_29[4:0] == 5'hF ? remapVecReadys_29 : remapindex_28[4:0] == 5'hF ? remapVecReadys_28 : remapindex_27[4:0] == 5'hF ? remapVecReadys_27 : remapindex_26[4:0] == 5'hF ? remapVecReadys_26 : remapindex_25[4:0] == 5'hF ? remapVecReadys_25 : remapindex_24[4:0] == 5'hF ? remapVecReadys_24 : remapindex_23[4:0] == 5'hF ? remapVecReadys_23 : remapindex_22[4:0] == 5'hF ? remapVecReadys_22 : remapindex_21[4:0] == 5'hF ? remapVecReadys_21 : remapindex_20[4:0] == 5'hF ? remapVecReadys_20 : remapindex_19[4:0] == 5'hF ? remapVecReadys_19 : remapindex_18[4:0] == 5'hF ? remapVecReadys_18 : remapindex_17[4:0] == 5'hF ? remapVecReadys_17 : remapindex_16[4:0] == 5'hF ? remapVecReadys_16 : remapindex_15[4:0] == 5'hF ? remapVecReadys_15 : remapindex_14[4:0] == 5'hF ? remapVecReadys_14 : remapindex_13[4:0] == 5'hF ? remapVecReadys_13 : remapindex_12[4:0] == 5'hF ? remapVecReadys_12 : remapindex_11[4:0] == 5'hF ? remapVecReadys_11 : remapindex_10[4:0] == 5'hF ? remapVecReadys_10 : remapindex_9[4:0] == 5'hF ? remapVecReadys_9 : remapindex_8[4:0] == 5'hF ? remapVecReadys_8 : remapindex_7[4:0] == 5'hF ? remapVecReadys_7 : remapindex_6[4:0] == 5'hF ? remapVecReadys_6 : remapindex_5[4:0] == 5'hF ? remapVecReadys_5 : remapindex_4[4:0] == 5'hF ? remapVecReadys_4 : remapindex_3[4:0] == 5'hF ? remapVecReadys_3 : remapindex_2[4:0] == 5'hF ? remapVecReadys_2 : remapindex_1[4:0] == 5'hF ? remapVecReadys_1 : remapindex[4:0] == 5'hF & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_16_deq_ready = remapindex_31[4:0] == 5'h10 ? remapVecReadys_31 : remapindex_30[4:0] == 5'h10 ? remapVecReadys_30 : remapindex_29[4:0] == 5'h10 ? remapVecReadys_29 : remapindex_28[4:0] == 5'h10 ? remapVecReadys_28 : remapindex_27[4:0] == 5'h10 ? remapVecReadys_27 : remapindex_26[4:0] == 5'h10 ? remapVecReadys_26 : remapindex_25[4:0] == 5'h10 ? remapVecReadys_25 : remapindex_24[4:0] == 5'h10 ? remapVecReadys_24 : remapindex_23[4:0] == 5'h10 ? remapVecReadys_23 : remapindex_22[4:0] == 5'h10 ? remapVecReadys_22 : remapindex_21[4:0] == 5'h10 ? remapVecReadys_21 : remapindex_20[4:0] == 5'h10 ? remapVecReadys_20 : remapindex_19[4:0] == 5'h10 ? remapVecReadys_19 : remapindex_18[4:0] == 5'h10 ? remapVecReadys_18 : remapindex_17[4:0] == 5'h10 ? remapVecReadys_17 : remapindex_16[4:0] == 5'h10 ? remapVecReadys_16 : remapindex_15[4:0] == 5'h10 ? remapVecReadys_15 : remapindex_14[4:0] == 5'h10 ? remapVecReadys_14 : remapindex_13[4:0] == 5'h10 ? remapVecReadys_13 : remapindex_12[4:0] == 5'h10 ? remapVecReadys_12 : remapindex_11[4:0] == 5'h10 ? remapVecReadys_11 : remapindex_10[4:0] == 5'h10 ? remapVecReadys_10 : remapindex_9[4:0] == 5'h10 ? remapVecReadys_9 : remapindex_8[4:0] == 5'h10 ? remapVecReadys_8 : remapindex_7[4:0] == 5'h10 ? remapVecReadys_7 : remapindex_6[4:0] == 5'h10 ? remapVecReadys_6 : remapindex_5[4:0] == 5'h10 ? remapVecReadys_5 : remapindex_4[4:0] == 5'h10 ? remapVecReadys_4 : remapindex_3[4:0] == 5'h10 ? remapVecReadys_3 : remapindex_2[4:0] == 5'h10 ? remapVecReadys_2 : remapindex_1[4:0] == 5'h10 ? remapVecReadys_1 : remapindex[4:0] == 5'h10 & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_17_deq_ready = remapindex_31[4:0] == 5'h11 ? remapVecReadys_31 : remapindex_30[4:0] == 5'h11 ? remapVecReadys_30 : remapindex_29[4:0] == 5'h11 ? remapVecReadys_29 : remapindex_28[4:0] == 5'h11 ? remapVecReadys_28 : remapindex_27[4:0] == 5'h11 ? remapVecReadys_27 : remapindex_26[4:0] == 5'h11 ? remapVecReadys_26 : remapindex_25[4:0] == 5'h11 ? remapVecReadys_25 : remapindex_24[4:0] == 5'h11 ? remapVecReadys_24 : remapindex_23[4:0] == 5'h11 ? remapVecReadys_23 : remapindex_22[4:0] == 5'h11 ? remapVecReadys_22 : remapindex_21[4:0] == 5'h11 ? remapVecReadys_21 : remapindex_20[4:0] == 5'h11 ? remapVecReadys_20 : remapindex_19[4:0] == 5'h11 ? remapVecReadys_19 : remapindex_18[4:0] == 5'h11 ? remapVecReadys_18 : remapindex_17[4:0] == 5'h11 ? remapVecReadys_17 : remapindex_16[4:0] == 5'h11 ? remapVecReadys_16 : remapindex_15[4:0] == 5'h11 ? remapVecReadys_15 : remapindex_14[4:0] == 5'h11 ? remapVecReadys_14 : remapindex_13[4:0] == 5'h11 ? remapVecReadys_13 : remapindex_12[4:0] == 5'h11 ? remapVecReadys_12 : remapindex_11[4:0] == 5'h11 ? remapVecReadys_11 : remapindex_10[4:0] == 5'h11 ? remapVecReadys_10 : remapindex_9[4:0] == 5'h11 ? remapVecReadys_9 : remapindex_8[4:0] == 5'h11 ? remapVecReadys_8 : remapindex_7[4:0] == 5'h11 ? remapVecReadys_7 : remapindex_6[4:0] == 5'h11 ? remapVecReadys_6 : remapindex_5[4:0] == 5'h11 ? remapVecReadys_5 : remapindex_4[4:0] == 5'h11 ? remapVecReadys_4 : remapindex_3[4:0] == 5'h11 ? remapVecReadys_3 : remapindex_2[4:0] == 5'h11 ? remapVecReadys_2 : remapindex_1[4:0] == 5'h11 ? remapVecReadys_1 : remapindex[4:0] == 5'h11 & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_18_deq_ready = remapindex_31[4:0] == 5'h12 ? remapVecReadys_31 : remapindex_30[4:0] == 5'h12 ? remapVecReadys_30 : remapindex_29[4:0] == 5'h12 ? remapVecReadys_29 : remapindex_28[4:0] == 5'h12 ? remapVecReadys_28 : remapindex_27[4:0] == 5'h12 ? remapVecReadys_27 : remapindex_26[4:0] == 5'h12 ? remapVecReadys_26 : remapindex_25[4:0] == 5'h12 ? remapVecReadys_25 : remapindex_24[4:0] == 5'h12 ? remapVecReadys_24 : remapindex_23[4:0] == 5'h12 ? remapVecReadys_23 : remapindex_22[4:0] == 5'h12 ? remapVecReadys_22 : remapindex_21[4:0] == 5'h12 ? remapVecReadys_21 : remapindex_20[4:0] == 5'h12 ? remapVecReadys_20 : remapindex_19[4:0] == 5'h12 ? remapVecReadys_19 : remapindex_18[4:0] == 5'h12 ? remapVecReadys_18 : remapindex_17[4:0] == 5'h12 ? remapVecReadys_17 : remapindex_16[4:0] == 5'h12 ? remapVecReadys_16 : remapindex_15[4:0] == 5'h12 ? remapVecReadys_15 : remapindex_14[4:0] == 5'h12 ? remapVecReadys_14 : remapindex_13[4:0] == 5'h12 ? remapVecReadys_13 : remapindex_12[4:0] == 5'h12 ? remapVecReadys_12 : remapindex_11[4:0] == 5'h12 ? remapVecReadys_11 : remapindex_10[4:0] == 5'h12 ? remapVecReadys_10 : remapindex_9[4:0] == 5'h12 ? remapVecReadys_9 : remapindex_8[4:0] == 5'h12 ? remapVecReadys_8 : remapindex_7[4:0] == 5'h12 ? remapVecReadys_7 : remapindex_6[4:0] == 5'h12 ? remapVecReadys_6 : remapindex_5[4:0] == 5'h12 ? remapVecReadys_5 : remapindex_4[4:0] == 5'h12 ? remapVecReadys_4 : remapindex_3[4:0] == 5'h12 ? remapVecReadys_3 : remapindex_2[4:0] == 5'h12 ? remapVecReadys_2 : remapindex_1[4:0] == 5'h12 ? remapVecReadys_1 : remapindex[4:0] == 5'h12 & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_19_deq_ready = remapindex_31[4:0] == 5'h13 ? remapVecReadys_31 : remapindex_30[4:0] == 5'h13 ? remapVecReadys_30 : remapindex_29[4:0] == 5'h13 ? remapVecReadys_29 : remapindex_28[4:0] == 5'h13 ? remapVecReadys_28 : remapindex_27[4:0] == 5'h13 ? remapVecReadys_27 : remapindex_26[4:0] == 5'h13 ? remapVecReadys_26 : remapindex_25[4:0] == 5'h13 ? remapVecReadys_25 : remapindex_24[4:0] == 5'h13 ? remapVecReadys_24 : remapindex_23[4:0] == 5'h13 ? remapVecReadys_23 : remapindex_22[4:0] == 5'h13 ? remapVecReadys_22 : remapindex_21[4:0] == 5'h13 ? remapVecReadys_21 : remapindex_20[4:0] == 5'h13 ? remapVecReadys_20 : remapindex_19[4:0] == 5'h13 ? remapVecReadys_19 : remapindex_18[4:0] == 5'h13 ? remapVecReadys_18 : remapindex_17[4:0] == 5'h13 ? remapVecReadys_17 : remapindex_16[4:0] == 5'h13 ? remapVecReadys_16 : remapindex_15[4:0] == 5'h13 ? remapVecReadys_15 : remapindex_14[4:0] == 5'h13 ? remapVecReadys_14 : remapindex_13[4:0] == 5'h13 ? remapVecReadys_13 : remapindex_12[4:0] == 5'h13 ? remapVecReadys_12 : remapindex_11[4:0] == 5'h13 ? remapVecReadys_11 : remapindex_10[4:0] == 5'h13 ? remapVecReadys_10 : remapindex_9[4:0] == 5'h13 ? remapVecReadys_9 : remapindex_8[4:0] == 5'h13 ? remapVecReadys_8 : remapindex_7[4:0] == 5'h13 ? remapVecReadys_7 : remapindex_6[4:0] == 5'h13 ? remapVecReadys_6 : remapindex_5[4:0] == 5'h13 ? remapVecReadys_5 : remapindex_4[4:0] == 5'h13 ? remapVecReadys_4 : remapindex_3[4:0] == 5'h13 ? remapVecReadys_3 : remapindex_2[4:0] == 5'h13 ? remapVecReadys_2 : remapindex_1[4:0] == 5'h13 ? remapVecReadys_1 : remapindex[4:0] == 5'h13 & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_20_deq_ready = remapindex_31[4:0] == 5'h14 ? remapVecReadys_31 : remapindex_30[4:0] == 5'h14 ? remapVecReadys_30 : remapindex_29[4:0] == 5'h14 ? remapVecReadys_29 : remapindex_28[4:0] == 5'h14 ? remapVecReadys_28 : remapindex_27[4:0] == 5'h14 ? remapVecReadys_27 : remapindex_26[4:0] == 5'h14 ? remapVecReadys_26 : remapindex_25[4:0] == 5'h14 ? remapVecReadys_25 : remapindex_24[4:0] == 5'h14 ? remapVecReadys_24 : remapindex_23[4:0] == 5'h14 ? remapVecReadys_23 : remapindex_22[4:0] == 5'h14 ? remapVecReadys_22 : remapindex_21[4:0] == 5'h14 ? remapVecReadys_21 : remapindex_20[4:0] == 5'h14 ? remapVecReadys_20 : remapindex_19[4:0] == 5'h14 ? remapVecReadys_19 : remapindex_18[4:0] == 5'h14 ? remapVecReadys_18 : remapindex_17[4:0] == 5'h14 ? remapVecReadys_17 : remapindex_16[4:0] == 5'h14 ? remapVecReadys_16 : remapindex_15[4:0] == 5'h14 ? remapVecReadys_15 : remapindex_14[4:0] == 5'h14 ? remapVecReadys_14 : remapindex_13[4:0] == 5'h14 ? remapVecReadys_13 : remapindex_12[4:0] == 5'h14 ? remapVecReadys_12 : remapindex_11[4:0] == 5'h14 ? remapVecReadys_11 : remapindex_10[4:0] == 5'h14 ? remapVecReadys_10 : remapindex_9[4:0] == 5'h14 ? remapVecReadys_9 : remapindex_8[4:0] == 5'h14 ? remapVecReadys_8 : remapindex_7[4:0] == 5'h14 ? remapVecReadys_7 : remapindex_6[4:0] == 5'h14 ? remapVecReadys_6 : remapindex_5[4:0] == 5'h14 ? remapVecReadys_5 : remapindex_4[4:0] == 5'h14 ? remapVecReadys_4 : remapindex_3[4:0] == 5'h14 ? remapVecReadys_3 : remapindex_2[4:0] == 5'h14 ? remapVecReadys_2 : remapindex_1[4:0] == 5'h14 ? remapVecReadys_1 : remapindex[4:0] == 5'h14 & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_21_deq_ready = remapindex_31[4:0] == 5'h15 ? remapVecReadys_31 : remapindex_30[4:0] == 5'h15 ? remapVecReadys_30 : remapindex_29[4:0] == 5'h15 ? remapVecReadys_29 : remapindex_28[4:0] == 5'h15 ? remapVecReadys_28 : remapindex_27[4:0] == 5'h15 ? remapVecReadys_27 : remapindex_26[4:0] == 5'h15 ? remapVecReadys_26 : remapindex_25[4:0] == 5'h15 ? remapVecReadys_25 : remapindex_24[4:0] == 5'h15 ? remapVecReadys_24 : remapindex_23[4:0] == 5'h15 ? remapVecReadys_23 : remapindex_22[4:0] == 5'h15 ? remapVecReadys_22 : remapindex_21[4:0] == 5'h15 ? remapVecReadys_21 : remapindex_20[4:0] == 5'h15 ? remapVecReadys_20 : remapindex_19[4:0] == 5'h15 ? remapVecReadys_19 : remapindex_18[4:0] == 5'h15 ? remapVecReadys_18 : remapindex_17[4:0] == 5'h15 ? remapVecReadys_17 : remapindex_16[4:0] == 5'h15 ? remapVecReadys_16 : remapindex_15[4:0] == 5'h15 ? remapVecReadys_15 : remapindex_14[4:0] == 5'h15 ? remapVecReadys_14 : remapindex_13[4:0] == 5'h15 ? remapVecReadys_13 : remapindex_12[4:0] == 5'h15 ? remapVecReadys_12 : remapindex_11[4:0] == 5'h15 ? remapVecReadys_11 : remapindex_10[4:0] == 5'h15 ? remapVecReadys_10 : remapindex_9[4:0] == 5'h15 ? remapVecReadys_9 : remapindex_8[4:0] == 5'h15 ? remapVecReadys_8 : remapindex_7[4:0] == 5'h15 ? remapVecReadys_7 : remapindex_6[4:0] == 5'h15 ? remapVecReadys_6 : remapindex_5[4:0] == 5'h15 ? remapVecReadys_5 : remapindex_4[4:0] == 5'h15 ? remapVecReadys_4 : remapindex_3[4:0] == 5'h15 ? remapVecReadys_3 : remapindex_2[4:0] == 5'h15 ? remapVecReadys_2 : remapindex_1[4:0] == 5'h15 ? remapVecReadys_1 : remapindex[4:0] == 5'h15 & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_22_deq_ready = remapindex_31[4:0] == 5'h16 ? remapVecReadys_31 : remapindex_30[4:0] == 5'h16 ? remapVecReadys_30 : remapindex_29[4:0] == 5'h16 ? remapVecReadys_29 : remapindex_28[4:0] == 5'h16 ? remapVecReadys_28 : remapindex_27[4:0] == 5'h16 ? remapVecReadys_27 : remapindex_26[4:0] == 5'h16 ? remapVecReadys_26 : remapindex_25[4:0] == 5'h16 ? remapVecReadys_25 : remapindex_24[4:0] == 5'h16 ? remapVecReadys_24 : remapindex_23[4:0] == 5'h16 ? remapVecReadys_23 : remapindex_22[4:0] == 5'h16 ? remapVecReadys_22 : remapindex_21[4:0] == 5'h16 ? remapVecReadys_21 : remapindex_20[4:0] == 5'h16 ? remapVecReadys_20 : remapindex_19[4:0] == 5'h16 ? remapVecReadys_19 : remapindex_18[4:0] == 5'h16 ? remapVecReadys_18 : remapindex_17[4:0] == 5'h16 ? remapVecReadys_17 : remapindex_16[4:0] == 5'h16 ? remapVecReadys_16 : remapindex_15[4:0] == 5'h16 ? remapVecReadys_15 : remapindex_14[4:0] == 5'h16 ? remapVecReadys_14 : remapindex_13[4:0] == 5'h16 ? remapVecReadys_13 : remapindex_12[4:0] == 5'h16 ? remapVecReadys_12 : remapindex_11[4:0] == 5'h16 ? remapVecReadys_11 : remapindex_10[4:0] == 5'h16 ? remapVecReadys_10 : remapindex_9[4:0] == 5'h16 ? remapVecReadys_9 : remapindex_8[4:0] == 5'h16 ? remapVecReadys_8 : remapindex_7[4:0] == 5'h16 ? remapVecReadys_7 : remapindex_6[4:0] == 5'h16 ? remapVecReadys_6 : remapindex_5[4:0] == 5'h16 ? remapVecReadys_5 : remapindex_4[4:0] == 5'h16 ? remapVecReadys_4 : remapindex_3[4:0] == 5'h16 ? remapVecReadys_3 : remapindex_2[4:0] == 5'h16 ? remapVecReadys_2 : remapindex_1[4:0] == 5'h16 ? remapVecReadys_1 : remapindex[4:0] == 5'h16 & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_23_deq_ready = remapindex_31[4:0] == 5'h17 ? remapVecReadys_31 : remapindex_30[4:0] == 5'h17 ? remapVecReadys_30 : remapindex_29[4:0] == 5'h17 ? remapVecReadys_29 : remapindex_28[4:0] == 5'h17 ? remapVecReadys_28 : remapindex_27[4:0] == 5'h17 ? remapVecReadys_27 : remapindex_26[4:0] == 5'h17 ? remapVecReadys_26 : remapindex_25[4:0] == 5'h17 ? remapVecReadys_25 : remapindex_24[4:0] == 5'h17 ? remapVecReadys_24 : remapindex_23[4:0] == 5'h17 ? remapVecReadys_23 : remapindex_22[4:0] == 5'h17 ? remapVecReadys_22 : remapindex_21[4:0] == 5'h17 ? remapVecReadys_21 : remapindex_20[4:0] == 5'h17 ? remapVecReadys_20 : remapindex_19[4:0] == 5'h17 ? remapVecReadys_19 : remapindex_18[4:0] == 5'h17 ? remapVecReadys_18 : remapindex_17[4:0] == 5'h17 ? remapVecReadys_17 : remapindex_16[4:0] == 5'h17 ? remapVecReadys_16 : remapindex_15[4:0] == 5'h17 ? remapVecReadys_15 : remapindex_14[4:0] == 5'h17 ? remapVecReadys_14 : remapindex_13[4:0] == 5'h17 ? remapVecReadys_13 : remapindex_12[4:0] == 5'h17 ? remapVecReadys_12 : remapindex_11[4:0] == 5'h17 ? remapVecReadys_11 : remapindex_10[4:0] == 5'h17 ? remapVecReadys_10 : remapindex_9[4:0] == 5'h17 ? remapVecReadys_9 : remapindex_8[4:0] == 5'h17 ? remapVecReadys_8 : remapindex_7[4:0] == 5'h17 ? remapVecReadys_7 : remapindex_6[4:0] == 5'h17 ? remapVecReadys_6 : remapindex_5[4:0] == 5'h17 ? remapVecReadys_5 : remapindex_4[4:0] == 5'h17 ? remapVecReadys_4 : remapindex_3[4:0] == 5'h17 ? remapVecReadys_3 : remapindex_2[4:0] == 5'h17 ? remapVecReadys_2 : remapindex_1[4:0] == 5'h17 ? remapVecReadys_1 : remapindex[4:0] == 5'h17 & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_24_deq_ready = remapindex_31[4:0] == 5'h18 ? remapVecReadys_31 : remapindex_30[4:0] == 5'h18 ? remapVecReadys_30 : remapindex_29[4:0] == 5'h18 ? remapVecReadys_29 : remapindex_28[4:0] == 5'h18 ? remapVecReadys_28 : remapindex_27[4:0] == 5'h18 ? remapVecReadys_27 : remapindex_26[4:0] == 5'h18 ? remapVecReadys_26 : remapindex_25[4:0] == 5'h18 ? remapVecReadys_25 : remapindex_24[4:0] == 5'h18 ? remapVecReadys_24 : remapindex_23[4:0] == 5'h18 ? remapVecReadys_23 : remapindex_22[4:0] == 5'h18 ? remapVecReadys_22 : remapindex_21[4:0] == 5'h18 ? remapVecReadys_21 : remapindex_20[4:0] == 5'h18 ? remapVecReadys_20 : remapindex_19[4:0] == 5'h18 ? remapVecReadys_19 : remapindex_18[4:0] == 5'h18 ? remapVecReadys_18 : remapindex_17[4:0] == 5'h18 ? remapVecReadys_17 : remapindex_16[4:0] == 5'h18 ? remapVecReadys_16 : remapindex_15[4:0] == 5'h18 ? remapVecReadys_15 : remapindex_14[4:0] == 5'h18 ? remapVecReadys_14 : remapindex_13[4:0] == 5'h18 ? remapVecReadys_13 : remapindex_12[4:0] == 5'h18 ? remapVecReadys_12 : remapindex_11[4:0] == 5'h18 ? remapVecReadys_11 : remapindex_10[4:0] == 5'h18 ? remapVecReadys_10 : remapindex_9[4:0] == 5'h18 ? remapVecReadys_9 : remapindex_8[4:0] == 5'h18 ? remapVecReadys_8 : remapindex_7[4:0] == 5'h18 ? remapVecReadys_7 : remapindex_6[4:0] == 5'h18 ? remapVecReadys_6 : remapindex_5[4:0] == 5'h18 ? remapVecReadys_5 : remapindex_4[4:0] == 5'h18 ? remapVecReadys_4 : remapindex_3[4:0] == 5'h18 ? remapVecReadys_3 : remapindex_2[4:0] == 5'h18 ? remapVecReadys_2 : remapindex_1[4:0] == 5'h18 ? remapVecReadys_1 : remapindex[4:0] == 5'h18 & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_25_deq_ready = remapindex_31[4:0] == 5'h19 ? remapVecReadys_31 : remapindex_30[4:0] == 5'h19 ? remapVecReadys_30 : remapindex_29[4:0] == 5'h19 ? remapVecReadys_29 : remapindex_28[4:0] == 5'h19 ? remapVecReadys_28 : remapindex_27[4:0] == 5'h19 ? remapVecReadys_27 : remapindex_26[4:0] == 5'h19 ? remapVecReadys_26 : remapindex_25[4:0] == 5'h19 ? remapVecReadys_25 : remapindex_24[4:0] == 5'h19 ? remapVecReadys_24 : remapindex_23[4:0] == 5'h19 ? remapVecReadys_23 : remapindex_22[4:0] == 5'h19 ? remapVecReadys_22 : remapindex_21[4:0] == 5'h19 ? remapVecReadys_21 : remapindex_20[4:0] == 5'h19 ? remapVecReadys_20 : remapindex_19[4:0] == 5'h19 ? remapVecReadys_19 : remapindex_18[4:0] == 5'h19 ? remapVecReadys_18 : remapindex_17[4:0] == 5'h19 ? remapVecReadys_17 : remapindex_16[4:0] == 5'h19 ? remapVecReadys_16 : remapindex_15[4:0] == 5'h19 ? remapVecReadys_15 : remapindex_14[4:0] == 5'h19 ? remapVecReadys_14 : remapindex_13[4:0] == 5'h19 ? remapVecReadys_13 : remapindex_12[4:0] == 5'h19 ? remapVecReadys_12 : remapindex_11[4:0] == 5'h19 ? remapVecReadys_11 : remapindex_10[4:0] == 5'h19 ? remapVecReadys_10 : remapindex_9[4:0] == 5'h19 ? remapVecReadys_9 : remapindex_8[4:0] == 5'h19 ? remapVecReadys_8 : remapindex_7[4:0] == 5'h19 ? remapVecReadys_7 : remapindex_6[4:0] == 5'h19 ? remapVecReadys_6 : remapindex_5[4:0] == 5'h19 ? remapVecReadys_5 : remapindex_4[4:0] == 5'h19 ? remapVecReadys_4 : remapindex_3[4:0] == 5'h19 ? remapVecReadys_3 : remapindex_2[4:0] == 5'h19 ? remapVecReadys_2 : remapindex_1[4:0] == 5'h19 ? remapVecReadys_1 : remapindex[4:0] == 5'h19 & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_26_deq_ready = remapindex_31[4:0] == 5'h1A ? remapVecReadys_31 : remapindex_30[4:0] == 5'h1A ? remapVecReadys_30 : remapindex_29[4:0] == 5'h1A ? remapVecReadys_29 : remapindex_28[4:0] == 5'h1A ? remapVecReadys_28 : remapindex_27[4:0] == 5'h1A ? remapVecReadys_27 : remapindex_26[4:0] == 5'h1A ? remapVecReadys_26 : remapindex_25[4:0] == 5'h1A ? remapVecReadys_25 : remapindex_24[4:0] == 5'h1A ? remapVecReadys_24 : remapindex_23[4:0] == 5'h1A ? remapVecReadys_23 : remapindex_22[4:0] == 5'h1A ? remapVecReadys_22 : remapindex_21[4:0] == 5'h1A ? remapVecReadys_21 : remapindex_20[4:0] == 5'h1A ? remapVecReadys_20 : remapindex_19[4:0] == 5'h1A ? remapVecReadys_19 : remapindex_18[4:0] == 5'h1A ? remapVecReadys_18 : remapindex_17[4:0] == 5'h1A ? remapVecReadys_17 : remapindex_16[4:0] == 5'h1A ? remapVecReadys_16 : remapindex_15[4:0] == 5'h1A ? remapVecReadys_15 : remapindex_14[4:0] == 5'h1A ? remapVecReadys_14 : remapindex_13[4:0] == 5'h1A ? remapVecReadys_13 : remapindex_12[4:0] == 5'h1A ? remapVecReadys_12 : remapindex_11[4:0] == 5'h1A ? remapVecReadys_11 : remapindex_10[4:0] == 5'h1A ? remapVecReadys_10 : remapindex_9[4:0] == 5'h1A ? remapVecReadys_9 : remapindex_8[4:0] == 5'h1A ? remapVecReadys_8 : remapindex_7[4:0] == 5'h1A ? remapVecReadys_7 : remapindex_6[4:0] == 5'h1A ? remapVecReadys_6 : remapindex_5[4:0] == 5'h1A ? remapVecReadys_5 : remapindex_4[4:0] == 5'h1A ? remapVecReadys_4 : remapindex_3[4:0] == 5'h1A ? remapVecReadys_3 : remapindex_2[4:0] == 5'h1A ? remapVecReadys_2 : remapindex_1[4:0] == 5'h1A ? remapVecReadys_1 : remapindex[4:0] == 5'h1A & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_27_deq_ready = remapindex_31[4:0] == 5'h1B ? remapVecReadys_31 : remapindex_30[4:0] == 5'h1B ? remapVecReadys_30 : remapindex_29[4:0] == 5'h1B ? remapVecReadys_29 : remapindex_28[4:0] == 5'h1B ? remapVecReadys_28 : remapindex_27[4:0] == 5'h1B ? remapVecReadys_27 : remapindex_26[4:0] == 5'h1B ? remapVecReadys_26 : remapindex_25[4:0] == 5'h1B ? remapVecReadys_25 : remapindex_24[4:0] == 5'h1B ? remapVecReadys_24 : remapindex_23[4:0] == 5'h1B ? remapVecReadys_23 : remapindex_22[4:0] == 5'h1B ? remapVecReadys_22 : remapindex_21[4:0] == 5'h1B ? remapVecReadys_21 : remapindex_20[4:0] == 5'h1B ? remapVecReadys_20 : remapindex_19[4:0] == 5'h1B ? remapVecReadys_19 : remapindex_18[4:0] == 5'h1B ? remapVecReadys_18 : remapindex_17[4:0] == 5'h1B ? remapVecReadys_17 : remapindex_16[4:0] == 5'h1B ? remapVecReadys_16 : remapindex_15[4:0] == 5'h1B ? remapVecReadys_15 : remapindex_14[4:0] == 5'h1B ? remapVecReadys_14 : remapindex_13[4:0] == 5'h1B ? remapVecReadys_13 : remapindex_12[4:0] == 5'h1B ? remapVecReadys_12 : remapindex_11[4:0] == 5'h1B ? remapVecReadys_11 : remapindex_10[4:0] == 5'h1B ? remapVecReadys_10 : remapindex_9[4:0] == 5'h1B ? remapVecReadys_9 : remapindex_8[4:0] == 5'h1B ? remapVecReadys_8 : remapindex_7[4:0] == 5'h1B ? remapVecReadys_7 : remapindex_6[4:0] == 5'h1B ? remapVecReadys_6 : remapindex_5[4:0] == 5'h1B ? remapVecReadys_5 : remapindex_4[4:0] == 5'h1B ? remapVecReadys_4 : remapindex_3[4:0] == 5'h1B ? remapVecReadys_3 : remapindex_2[4:0] == 5'h1B ? remapVecReadys_2 : remapindex_1[4:0] == 5'h1B ? remapVecReadys_1 : remapindex[4:0] == 5'h1B & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_28_deq_ready = remapindex_31[4:0] == 5'h1C ? remapVecReadys_31 : remapindex_30[4:0] == 5'h1C ? remapVecReadys_30 : remapindex_29[4:0] == 5'h1C ? remapVecReadys_29 : remapindex_28[4:0] == 5'h1C ? remapVecReadys_28 : remapindex_27[4:0] == 5'h1C ? remapVecReadys_27 : remapindex_26[4:0] == 5'h1C ? remapVecReadys_26 : remapindex_25[4:0] == 5'h1C ? remapVecReadys_25 : remapindex_24[4:0] == 5'h1C ? remapVecReadys_24 : remapindex_23[4:0] == 5'h1C ? remapVecReadys_23 : remapindex_22[4:0] == 5'h1C ? remapVecReadys_22 : remapindex_21[4:0] == 5'h1C ? remapVecReadys_21 : remapindex_20[4:0] == 5'h1C ? remapVecReadys_20 : remapindex_19[4:0] == 5'h1C ? remapVecReadys_19 : remapindex_18[4:0] == 5'h1C ? remapVecReadys_18 : remapindex_17[4:0] == 5'h1C ? remapVecReadys_17 : remapindex_16[4:0] == 5'h1C ? remapVecReadys_16 : remapindex_15[4:0] == 5'h1C ? remapVecReadys_15 : remapindex_14[4:0] == 5'h1C ? remapVecReadys_14 : remapindex_13[4:0] == 5'h1C ? remapVecReadys_13 : remapindex_12[4:0] == 5'h1C ? remapVecReadys_12 : remapindex_11[4:0] == 5'h1C ? remapVecReadys_11 : remapindex_10[4:0] == 5'h1C ? remapVecReadys_10 : remapindex_9[4:0] == 5'h1C ? remapVecReadys_9 : remapindex_8[4:0] == 5'h1C ? remapVecReadys_8 : remapindex_7[4:0] == 5'h1C ? remapVecReadys_7 : remapindex_6[4:0] == 5'h1C ? remapVecReadys_6 : remapindex_5[4:0] == 5'h1C ? remapVecReadys_5 : remapindex_4[4:0] == 5'h1C ? remapVecReadys_4 : remapindex_3[4:0] == 5'h1C ? remapVecReadys_3 : remapindex_2[4:0] == 5'h1C ? remapVecReadys_2 : remapindex_1[4:0] == 5'h1C ? remapVecReadys_1 : remapindex[4:0] == 5'h1C & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_29_deq_ready = remapindex_31[4:0] == 5'h1D ? remapVecReadys_31 : remapindex_30[4:0] == 5'h1D ? remapVecReadys_30 : remapindex_29[4:0] == 5'h1D ? remapVecReadys_29 : remapindex_28[4:0] == 5'h1D ? remapVecReadys_28 : remapindex_27[4:0] == 5'h1D ? remapVecReadys_27 : remapindex_26[4:0] == 5'h1D ? remapVecReadys_26 : remapindex_25[4:0] == 5'h1D ? remapVecReadys_25 : remapindex_24[4:0] == 5'h1D ? remapVecReadys_24 : remapindex_23[4:0] == 5'h1D ? remapVecReadys_23 : remapindex_22[4:0] == 5'h1D ? remapVecReadys_22 : remapindex_21[4:0] == 5'h1D ? remapVecReadys_21 : remapindex_20[4:0] == 5'h1D ? remapVecReadys_20 : remapindex_19[4:0] == 5'h1D ? remapVecReadys_19 : remapindex_18[4:0] == 5'h1D ? remapVecReadys_18 : remapindex_17[4:0] == 5'h1D ? remapVecReadys_17 : remapindex_16[4:0] == 5'h1D ? remapVecReadys_16 : remapindex_15[4:0] == 5'h1D ? remapVecReadys_15 : remapindex_14[4:0] == 5'h1D ? remapVecReadys_14 : remapindex_13[4:0] == 5'h1D ? remapVecReadys_13 : remapindex_12[4:0] == 5'h1D ? remapVecReadys_12 : remapindex_11[4:0] == 5'h1D ? remapVecReadys_11 : remapindex_10[4:0] == 5'h1D ? remapVecReadys_10 : remapindex_9[4:0] == 5'h1D ? remapVecReadys_9 : remapindex_8[4:0] == 5'h1D ? remapVecReadys_8 : remapindex_7[4:0] == 5'h1D ? remapVecReadys_7 : remapindex_6[4:0] == 5'h1D ? remapVecReadys_6 : remapindex_5[4:0] == 5'h1D ? remapVecReadys_5 : remapindex_4[4:0] == 5'h1D ? remapVecReadys_4 : remapindex_3[4:0] == 5'h1D ? remapVecReadys_3 : remapindex_2[4:0] == 5'h1D ? remapVecReadys_2 : remapindex_1[4:0] == 5'h1D ? remapVecReadys_1 : remapindex[4:0] == 5'h1D & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_30_deq_ready = remapindex_31[4:0] == 5'h1E ? remapVecReadys_31 : remapindex_30[4:0] == 5'h1E ? remapVecReadys_30 : remapindex_29[4:0] == 5'h1E ? remapVecReadys_29 : remapindex_28[4:0] == 5'h1E ? remapVecReadys_28 : remapindex_27[4:0] == 5'h1E ? remapVecReadys_27 : remapindex_26[4:0] == 5'h1E ? remapVecReadys_26 : remapindex_25[4:0] == 5'h1E ? remapVecReadys_25 : remapindex_24[4:0] == 5'h1E ? remapVecReadys_24 : remapindex_23[4:0] == 5'h1E ? remapVecReadys_23 : remapindex_22[4:0] == 5'h1E ? remapVecReadys_22 : remapindex_21[4:0] == 5'h1E ? remapVecReadys_21 : remapindex_20[4:0] == 5'h1E ? remapVecReadys_20 : remapindex_19[4:0] == 5'h1E ? remapVecReadys_19 : remapindex_18[4:0] == 5'h1E ? remapVecReadys_18 : remapindex_17[4:0] == 5'h1E ? remapVecReadys_17 : remapindex_16[4:0] == 5'h1E ? remapVecReadys_16 : remapindex_15[4:0] == 5'h1E ? remapVecReadys_15 : remapindex_14[4:0] == 5'h1E ? remapVecReadys_14 : remapindex_13[4:0] == 5'h1E ? remapVecReadys_13 : remapindex_12[4:0] == 5'h1E ? remapVecReadys_12 : remapindex_11[4:0] == 5'h1E ? remapVecReadys_11 : remapindex_10[4:0] == 5'h1E ? remapVecReadys_10 : remapindex_9[4:0] == 5'h1E ? remapVecReadys_9 : remapindex_8[4:0] == 5'h1E ? remapVecReadys_8 : remapindex_7[4:0] == 5'h1E ? remapVecReadys_7 : remapindex_6[4:0] == 5'h1E ? remapVecReadys_6 : remapindex_5[4:0] == 5'h1E ? remapVecReadys_5 : remapindex_4[4:0] == 5'h1E ? remapVecReadys_4 : remapindex_3[4:0] == 5'h1E ? remapVecReadys_3 : remapindex_2[4:0] == 5'h1E ? remapVecReadys_2 : remapindex_1[4:0] == 5'h1E ? remapVecReadys_1 : remapindex[4:0] == 5'h1E & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
assign mem_resp_queues_31_deq_ready = (&(remapindex_31[4:0])) ? remapVecReadys_31 : (&(remapindex_30[4:0])) ? remapVecReadys_30 : (&(remapindex_29[4:0])) ? remapVecReadys_29 : (&(remapindex_28[4:0])) ? remapVecReadys_28 : (&(remapindex_27[4:0])) ? remapVecReadys_27 : (&(remapindex_26[4:0])) ? remapVecReadys_26 : (&(remapindex_25[4:0])) ? remapVecReadys_25 : (&(remapindex_24[4:0])) ? remapVecReadys_24 : (&(remapindex_23[4:0])) ? remapVecReadys_23 : (&(remapindex_22[4:0])) ? remapVecReadys_22 : (&(remapindex_21[4:0])) ? remapVecReadys_21 : (&(remapindex_20[4:0])) ? remapVecReadys_20 : (&(remapindex_19[4:0])) ? remapVecReadys_19 : (&(remapindex_18[4:0])) ? remapVecReadys_18 : (&(remapindex_17[4:0])) ? remapVecReadys_17 : (&(remapindex_16[4:0])) ? remapVecReadys_16 : (&(remapindex_15[4:0])) ? remapVecReadys_15 : (&(remapindex_14[4:0])) ? remapVecReadys_14 : (&(remapindex_13[4:0])) ? remapVecReadys_13 : (&(remapindex_12[4:0])) ? remapVecReadys_12 : (&(remapindex_11[4:0])) ? remapVecReadys_11 : (&(remapindex_10[4:0])) ? remapVecReadys_10 : (&(remapindex_9[4:0])) ? remapVecReadys_9 : (&(remapindex_8[4:0])) ? remapVecReadys_8 : (&(remapindex_7[4:0])) ? remapVecReadys_7 : (&(remapindex_6[4:0])) ? remapVecReadys_6 : (&(remapindex_5[4:0])) ? remapVecReadys_5 : (&(remapindex_4[4:0])) ? remapVecReadys_4 : (&(remapindex_3[4:0])) ? remapVecReadys_3 : (&(remapindex_2[4:0])) ? remapVecReadys_2 : (&(remapindex_1[4:0])) ? remapVecReadys_1 : (&(remapindex[4:0])) & remapVecReadys_0; // @[MemWriter32.scala:70:49, :76:17, :129:28, :132:54, :135:43]
wire [1:0] _count_valids_T = {1'h0, remapVecValids_0} + {1'h0, remapVecValids_1}; // @[MemWriter32.scala:128:28, :138:60]
wire [2:0] _count_valids_T_1 = {1'h0, _count_valids_T} + {2'h0, remapVecValids_2}; // @[MemWriter32.scala:128:28, :138:60]
wire [3:0] _count_valids_T_2 = {1'h0, _count_valids_T_1} + {3'h0, remapVecValids_3}; // @[MemWriter32.scala:128:28, :138:60]
wire [4:0] _count_valids_T_3 = {1'h0, _count_valids_T_2} + {4'h0, remapVecValids_4}; // @[MemWriter32.scala:128:28, :138:60]
wire [5:0] _count_valids_T_4 = {1'h0, _count_valids_T_3} + {5'h0, remapVecValids_5}; // @[MemWriter32.scala:128:28, :138:60]
wire [6:0] _count_valids_T_5 = {1'h0, _count_valids_T_4} + {6'h0, remapVecValids_6}; // @[MemWriter32.scala:128:28, :138:60]
wire [7:0] _count_valids_T_6 = {1'h0, _count_valids_T_5} + {7'h0, remapVecValids_7}; // @[MemWriter32.scala:128:28, :138:60]
wire [8:0] _count_valids_T_7 = {1'h0, _count_valids_T_6} + {8'h0, remapVecValids_8}; // @[MemWriter32.scala:128:28, :138:60]
wire [9:0] _count_valids_T_8 = {1'h0, _count_valids_T_7} + {9'h0, remapVecValids_9}; // @[MemWriter32.scala:128:28, :138:60]
wire [10:0] _count_valids_T_9 = {1'h0, _count_valids_T_8} + {10'h0, remapVecValids_10}; // @[MemWriter32.scala:128:28, :138:60]
wire [11:0] _count_valids_T_10 = {1'h0, _count_valids_T_9} + {11'h0, remapVecValids_11}; // @[MemWriter32.scala:128:28, :138:60]
wire [12:0] _count_valids_T_11 = {1'h0, _count_valids_T_10} + {12'h0, remapVecValids_12}; // @[MemWriter32.scala:128:28, :138:60]
wire [13:0] _count_valids_T_12 = {1'h0, _count_valids_T_11} + {13'h0, remapVecValids_13}; // @[MemWriter32.scala:128:28, :138:60]
wire [14:0] _count_valids_T_13 = {1'h0, _count_valids_T_12} + {14'h0, remapVecValids_14}; // @[MemWriter32.scala:128:28, :138:60]
wire [15:0] _count_valids_T_14 = {1'h0, _count_valids_T_13} + {15'h0, remapVecValids_15}; // @[MemWriter32.scala:128:28, :138:60]
wire [16:0] _count_valids_T_15 = {1'h0, _count_valids_T_14} + {16'h0, remapVecValids_16}; // @[MemWriter32.scala:128:28, :138:60]
wire [17:0] _count_valids_T_16 = {1'h0, _count_valids_T_15} + {17'h0, remapVecValids_17}; // @[MemWriter32.scala:128:28, :138:60]
wire [18:0] _count_valids_T_17 = {1'h0, _count_valids_T_16} + {18'h0, remapVecValids_18}; // @[MemWriter32.scala:128:28, :138:60]
wire [19:0] _count_valids_T_18 = {1'h0, _count_valids_T_17} + {19'h0, remapVecValids_19}; // @[MemWriter32.scala:128:28, :138:60]
wire [20:0] _count_valids_T_19 = {1'h0, _count_valids_T_18} + {20'h0, remapVecValids_20}; // @[MemWriter32.scala:128:28, :138:60]
wire [21:0] _count_valids_T_20 = {1'h0, _count_valids_T_19} + {21'h0, remapVecValids_21}; // @[MemWriter32.scala:128:28, :138:60]
wire [22:0] _count_valids_T_21 = {1'h0, _count_valids_T_20} + {22'h0, remapVecValids_22}; // @[MemWriter32.scala:128:28, :138:60]
wire [23:0] _count_valids_T_22 = {1'h0, _count_valids_T_21} + {23'h0, remapVecValids_23}; // @[MemWriter32.scala:128:28, :138:60]
wire [24:0] _count_valids_T_23 = {1'h0, _count_valids_T_22} + {24'h0, remapVecValids_24}; // @[MemWriter32.scala:128:28, :138:60]
wire [25:0] _count_valids_T_24 = {1'h0, _count_valids_T_23} + {25'h0, remapVecValids_25}; // @[MemWriter32.scala:128:28, :138:60]
wire [26:0] _count_valids_T_25 = {1'h0, _count_valids_T_24} + {26'h0, remapVecValids_26}; // @[MemWriter32.scala:128:28, :138:60]
wire [27:0] _count_valids_T_26 = {1'h0, _count_valids_T_25} + {27'h0, remapVecValids_27}; // @[MemWriter32.scala:128:28, :138:60]
wire [28:0] _count_valids_T_27 = {1'h0, _count_valids_T_26} + {28'h0, remapVecValids_28}; // @[MemWriter32.scala:128:28, :138:60]
wire [29:0] _count_valids_T_28 = {1'h0, _count_valids_T_27} + {29'h0, remapVecValids_29}; // @[MemWriter32.scala:128:28, :138:60]
wire [30:0] _count_valids_T_29 = {1'h0, _count_valids_T_28} + {30'h0, remapVecValids_30}; // @[MemWriter32.scala:128:28, :138:60]
wire [31:0] count_valids = {1'h0, _count_valids_T_29} + {31'h0, remapVecValids_31}; // @[MemWriter32.scala:128:28, :138:60]
reg [63:0] backend_bytes_written; // @[MemWriter32.scala:140:38]
wire [64:0] _GEN_94 = {1'h0, backend_bytes_written}; // @[MemWriter32.scala:140:38, :141:71]
wire [64:0] _backend_next_write_addr_T = {1'h0, _decompress_dest_info_Q_io_deq_bits_op} + _GEN_94; // @[MemWriter32.scala:32:38, :141:71]
wire [63:0] backend_next_write_addr = _backend_next_write_addr_T[63:0]; // @[MemWriter32.scala:141:71]
wire [64:0] _throttle_end_T = {1'h0, _buf_lens_Q_io_deq_bits} - _GEN_94; // @[MemWriter32.scala:45:26, :141:71, :144:28]
wire [63:0] _throttle_end_T_1 = _throttle_end_T[63:0]; // @[MemWriter32.scala:144:28]
wire [63:0] throttle_end = _buf_lens_Q_io_deq_valid ? _throttle_end_T_1 : 64'h20; // @[MemWriter32.scala:45:26, :143:25, :144:28]
wire _throttle_end_writeable_T = |(throttle_end[63:5]); // @[MemWriter32.scala:143:25, :147:49]
wire _throttle_end_writeable_T_1 = throttle_end[4]; // @[MemWriter32.scala:143:25, :148:53]
wire _throttle_end_writeable_log2_T_1 = throttle_end[4]; // @[MemWriter32.scala:143:25, :148:53, :156:55]
wire _throttle_end_writeable_T_2 = throttle_end[3]; // @[MemWriter32.scala:143:25, :149:55]
wire _throttle_end_writeable_log2_T_2 = throttle_end[3]; // @[MemWriter32.scala:143:25, :149:55, :157:57]
wire _throttle_end_writeable_T_3 = throttle_end[2]; // @[MemWriter32.scala:143:25, :150:57]
wire _throttle_end_writeable_log2_T_3 = throttle_end[2]; // @[MemWriter32.scala:143:25, :150:57, :158:59]
wire _throttle_end_writeable_T_4 = throttle_end[1]; // @[MemWriter32.scala:143:25, :151:59]
wire _throttle_end_writeable_log2_T_4 = throttle_end[1]; // @[MemWriter32.scala:143:25, :151:59, :159:61]
wire _throttle_end_writeable_T_5 = throttle_end[0]; // @[MemWriter32.scala:143:25, :152:61]
wire _throttle_end_writeable_log2_T_5 = throttle_end[0]; // @[MemWriter32.scala:143:25, :152:61, :160:63]
wire _throttle_end_writeable_T_6 = _throttle_end_writeable_T_5; // @[MemWriter32.scala:152:{48,61}]
wire [1:0] _throttle_end_writeable_T_7 = _throttle_end_writeable_T_4 ? 2'h2 : {1'h0, _throttle_end_writeable_T_6}; // @[MemWriter32.scala:151:{46,59}, :152:48]
wire [2:0] _throttle_end_writeable_T_8 = _throttle_end_writeable_T_3 ? 3'h4 : {1'h0, _throttle_end_writeable_T_7}; // @[MemWriter32.scala:150:{44,57}, :151:46]
wire [3:0] _throttle_end_writeable_T_9 = _throttle_end_writeable_T_2 ? 4'h8 : {1'h0, _throttle_end_writeable_T_8}; // @[MemWriter32.scala:149:{42,55}, :150:44]
wire [4:0] _throttle_end_writeable_T_10 = _throttle_end_writeable_T_1 ? 5'h10 : {1'h0, _throttle_end_writeable_T_9}; // @[MemWriter32.scala:148:{40,53}, :149:42]
wire [5:0] throttle_end_writeable = _throttle_end_writeable_T ? 6'h20 : {1'h0, _throttle_end_writeable_T_10}; // @[MemWriter32.scala:147:{35,49}, :148:40]
wire _throttle_end_writeable_log2_T = |(throttle_end[63:5]); // @[MemWriter32.scala:143:25, :147:49, :155:54]
wire _throttle_end_writeable_log2_T_7 = _throttle_end_writeable_log2_T_4; // @[MemWriter32.scala:159:{48,61}]
wire [1:0] _throttle_end_writeable_log2_T_8 = _throttle_end_writeable_log2_T_3 ? 2'h2 : {1'h0, _throttle_end_writeable_log2_T_7}; // @[MemWriter32.scala:158:{46,59}, :159:48]
wire [1:0] _throttle_end_writeable_log2_T_9 = _throttle_end_writeable_log2_T_2 ? 2'h3 : _throttle_end_writeable_log2_T_8; // @[MemWriter32.scala:157:{44,57}, :158:46]
wire [2:0] _throttle_end_writeable_log2_T_10 = _throttle_end_writeable_log2_T_1 ? 3'h4 : {1'h0, _throttle_end_writeable_log2_T_9}; // @[MemWriter32.scala:156:{42,55}, :157:44]
wire [2:0] throttle_end_writeable_log2 = _throttle_end_writeable_log2_T ? 3'h5 : _throttle_end_writeable_log2_T_10; // @[MemWriter32.scala:155:{40,54}, :156:42]
wire _ptr_align_max_bytes_writeable_T = backend_next_write_addr[0]; // @[MemWriter32.scala:141:71, :163:66]
wire _ptr_align_max_bytes_writeable_log2_T = backend_next_write_addr[0]; // @[MemWriter32.scala:141:71, :163:66, :170:71]
wire _ptr_align_max_bytes_writeable_T_1 = backend_next_write_addr[1]; // @[MemWriter32.scala:141:71, :164:68]
wire _ptr_align_max_bytes_writeable_log2_T_1 = backend_next_write_addr[1]; // @[MemWriter32.scala:141:71, :164:68, :171:72]
wire _ptr_align_max_bytes_writeable_T_2 = backend_next_write_addr[2]; // @[MemWriter32.scala:141:71, :165:70]
wire _ptr_align_max_bytes_writeable_log2_T_2 = backend_next_write_addr[2]; // @[MemWriter32.scala:141:71, :165:70, :172:74]
wire _ptr_align_max_bytes_writeable_T_3 = backend_next_write_addr[3]; // @[MemWriter32.scala:141:71, :166:72]
wire _ptr_align_max_bytes_writeable_log2_T_3 = backend_next_write_addr[3]; // @[MemWriter32.scala:141:71, :166:72, :173:76]
wire _ptr_align_max_bytes_writeable_T_4 = backend_next_write_addr[4]; // @[MemWriter32.scala:141:71, :167:74]
wire _ptr_align_max_bytes_writeable_log2_T_4 = backend_next_write_addr[4]; // @[MemWriter32.scala:141:71, :167:74, :174:78]
wire [5:0] _ptr_align_max_bytes_writeable_T_5 = _ptr_align_max_bytes_writeable_T_4 ? 6'h10 : 6'h20; // @[MemWriter32.scala:167:{50,74}]
wire [5:0] _ptr_align_max_bytes_writeable_T_6 = _ptr_align_max_bytes_writeable_T_3 ? 6'h8 : _ptr_align_max_bytes_writeable_T_5; // @[MemWriter32.scala:166:{48,72}, :167:50]
wire [5:0] _ptr_align_max_bytes_writeable_T_7 = _ptr_align_max_bytes_writeable_T_2 ? 6'h4 : _ptr_align_max_bytes_writeable_T_6; // @[MemWriter32.scala:165:{46,70}, :166:48]
wire [5:0] _ptr_align_max_bytes_writeable_T_8 = _ptr_align_max_bytes_writeable_T_1 ? 6'h2 : _ptr_align_max_bytes_writeable_T_7; // @[MemWriter32.scala:164:{44,68}, :165:46]
wire [5:0] ptr_align_max_bytes_writeable = _ptr_align_max_bytes_writeable_T ? 6'h1 : _ptr_align_max_bytes_writeable_T_8; // @[MemWriter32.scala:163:{42,66}, :164:44]
wire [2:0] _ptr_align_max_bytes_writeable_log2_T_5 = {2'h2, ~_ptr_align_max_bytes_writeable_log2_T_4}; // @[MemWriter32.scala:174:{54,78}]
wire [2:0] _ptr_align_max_bytes_writeable_log2_T_6 = _ptr_align_max_bytes_writeable_log2_T_3 ? 3'h3 : _ptr_align_max_bytes_writeable_log2_T_5; // @[MemWriter32.scala:173:{52,76}, :174:54]
wire [2:0] _ptr_align_max_bytes_writeable_log2_T_7 = _ptr_align_max_bytes_writeable_log2_T_2 ? 3'h2 : _ptr_align_max_bytes_writeable_log2_T_6; // @[MemWriter32.scala:172:{50,74}, :173:52]
wire [2:0] _ptr_align_max_bytes_writeable_log2_T_8 = _ptr_align_max_bytes_writeable_log2_T_1 ? 3'h1 : _ptr_align_max_bytes_writeable_log2_T_7; // @[MemWriter32.scala:171:{48,72}, :172:50]
wire [2:0] ptr_align_max_bytes_writeable_log2 = _ptr_align_max_bytes_writeable_log2_T ? 3'h0 : _ptr_align_max_bytes_writeable_log2_T_8; // @[MemWriter32.scala:170:{47,71}, :171:48]
wire _count_valids_largest_aligned_T = count_valids[5]; // @[MemWriter32.scala:138:60, :177:54]
wire _count_valids_largest_aligned_log2_T = count_valids[5]; // @[MemWriter32.scala:138:60, :177:54, :185:59]
wire _count_valids_largest_aligned_T_1 = count_valids[4]; // @[MemWriter32.scala:138:60, :178:55]
wire _count_valids_largest_aligned_log2_T_1 = count_valids[4]; // @[MemWriter32.scala:138:60, :178:55, :186:61]
wire _count_valids_largest_aligned_T_2 = count_valids[3]; // @[MemWriter32.scala:138:60, :179:57]
wire _count_valids_largest_aligned_log2_T_2 = count_valids[3]; // @[MemWriter32.scala:138:60, :179:57, :187:63]
wire _count_valids_largest_aligned_T_3 = count_valids[2]; // @[MemWriter32.scala:138:60, :180:59]
wire _count_valids_largest_aligned_log2_T_3 = count_valids[2]; // @[MemWriter32.scala:138:60, :180:59, :188:65]
wire _count_valids_largest_aligned_T_4 = count_valids[1]; // @[MemWriter32.scala:138:60, :181:61]
wire _count_valids_largest_aligned_log2_T_4 = count_valids[1]; // @[MemWriter32.scala:138:60, :181:61, :189:67]
wire _count_valids_largest_aligned_T_5 = count_valids[0]; // @[MemWriter32.scala:138:60, :182:63]
wire _count_valids_largest_aligned_log2_T_5 = count_valids[0]; // @[MemWriter32.scala:138:60, :182:63, :190:69]
wire _count_valids_largest_aligned_T_6 = _count_valids_largest_aligned_T_5; // @[MemWriter32.scala:182:{50,63}]
wire [1:0] _count_valids_largest_aligned_T_7 = _count_valids_largest_aligned_T_4 ? 2'h2 : {1'h0, _count_valids_largest_aligned_T_6}; // @[MemWriter32.scala:181:{48,61}, :182:50]
wire [2:0] _count_valids_largest_aligned_T_8 = _count_valids_largest_aligned_T_3 ? 3'h4 : {1'h0, _count_valids_largest_aligned_T_7}; // @[MemWriter32.scala:180:{46,59}, :181:48]
wire [3:0] _count_valids_largest_aligned_T_9 = _count_valids_largest_aligned_T_2 ? 4'h8 : {1'h0, _count_valids_largest_aligned_T_8}; // @[MemWriter32.scala:179:{44,57}, :180:46]
wire [4:0] _count_valids_largest_aligned_T_10 = _count_valids_largest_aligned_T_1 ? 5'h10 : {1'h0, _count_valids_largest_aligned_T_9}; // @[MemWriter32.scala:178:{42,55}, :179:44]
wire [5:0] count_valids_largest_aligned = _count_valids_largest_aligned_T ? 6'h20 : {1'h0, _count_valids_largest_aligned_T_10}; // @[MemWriter32.scala:177:{41,54}, :178:42]
wire _count_valids_largest_aligned_log2_T_7 = _count_valids_largest_aligned_log2_T_4; // @[MemWriter32.scala:189:{54,67}]
wire [1:0] _count_valids_largest_aligned_log2_T_8 = _count_valids_largest_aligned_log2_T_3 ? 2'h2 : {1'h0, _count_valids_largest_aligned_log2_T_7}; // @[MemWriter32.scala:188:{52,65}, :189:54]
wire [1:0] _count_valids_largest_aligned_log2_T_9 = _count_valids_largest_aligned_log2_T_2 ? 2'h3 : _count_valids_largest_aligned_log2_T_8; // @[MemWriter32.scala:187:{50,63}, :188:52]
wire [2:0] _count_valids_largest_aligned_log2_T_10 = _count_valids_largest_aligned_log2_T_1 ? 3'h4 : {1'h0, _count_valids_largest_aligned_log2_T_9}; // @[MemWriter32.scala:186:{48,61}, :187:50]
wire [2:0] count_valids_largest_aligned_log2 = _count_valids_largest_aligned_log2_T ? 3'h5 : _count_valids_largest_aligned_log2_T_10; // @[MemWriter32.scala:185:{46,59}, :186:48]
wire _bytes_to_write_T = ptr_align_max_bytes_writeable < count_valids_largest_aligned; // @[MemWriter32.scala:163:42, :177:41, :194:35]
wire _bytes_to_write_T_1 = ptr_align_max_bytes_writeable < throttle_end_writeable; // @[MemWriter32.scala:147:35, :163:42, :195:39]
wire [5:0] _bytes_to_write_T_2 = _bytes_to_write_T_1 ? ptr_align_max_bytes_writeable : throttle_end_writeable; // @[MemWriter32.scala:147:35, :163:42, :195:{8,39}]
wire _bytes_to_write_T_3 = count_valids_largest_aligned < throttle_end_writeable; // @[MemWriter32.scala:147:35, :177:41, :198:38]
wire [5:0] _bytes_to_write_T_4 = _bytes_to_write_T_3 ? count_valids_largest_aligned : throttle_end_writeable; // @[MemWriter32.scala:147:35, :177:41, :198:{8,38}]
wire [5:0] bytes_to_write = _bytes_to_write_T ? _bytes_to_write_T_2 : _bytes_to_write_T_4; // @[MemWriter32.scala:193:27, :194:35, :195:8, :198:8]
wire [15:0] remapped_write_data_lo_lo_lo_lo = {remapVecData_1, remapVecData_0}; // @[MemWriter32.scala:127:26, :202:32]
wire [15:0] remapped_write_data_lo_lo_lo_hi = {remapVecData_3, remapVecData_2}; // @[MemWriter32.scala:127:26, :202:32]
wire [31:0] remapped_write_data_lo_lo_lo = {remapped_write_data_lo_lo_lo_hi, remapped_write_data_lo_lo_lo_lo}; // @[MemWriter32.scala:202:32]
wire [15:0] remapped_write_data_lo_lo_hi_lo = {remapVecData_5, remapVecData_4}; // @[MemWriter32.scala:127:26, :202:32]
wire [15:0] remapped_write_data_lo_lo_hi_hi = {remapVecData_7, remapVecData_6}; // @[MemWriter32.scala:127:26, :202:32]
wire [31:0] remapped_write_data_lo_lo_hi = {remapped_write_data_lo_lo_hi_hi, remapped_write_data_lo_lo_hi_lo}; // @[MemWriter32.scala:202:32]
wire [63:0] remapped_write_data_lo_lo = {remapped_write_data_lo_lo_hi, remapped_write_data_lo_lo_lo}; // @[MemWriter32.scala:202:32]
wire [15:0] remapped_write_data_lo_hi_lo_lo = {remapVecData_9, remapVecData_8}; // @[MemWriter32.scala:127:26, :202:32]
wire [15:0] remapped_write_data_lo_hi_lo_hi = {remapVecData_11, remapVecData_10}; // @[MemWriter32.scala:127:26, :202:32]
wire [31:0] remapped_write_data_lo_hi_lo = {remapped_write_data_lo_hi_lo_hi, remapped_write_data_lo_hi_lo_lo}; // @[MemWriter32.scala:202:32]
wire [15:0] remapped_write_data_lo_hi_hi_lo = {remapVecData_13, remapVecData_12}; // @[MemWriter32.scala:127:26, :202:32]
wire [15:0] remapped_write_data_lo_hi_hi_hi = {remapVecData_15, remapVecData_14}; // @[MemWriter32.scala:127:26, :202:32]
wire [31:0] remapped_write_data_lo_hi_hi = {remapped_write_data_lo_hi_hi_hi, remapped_write_data_lo_hi_hi_lo}; // @[MemWriter32.scala:202:32]
wire [63:0] remapped_write_data_lo_hi = {remapped_write_data_lo_hi_hi, remapped_write_data_lo_hi_lo}; // @[MemWriter32.scala:202:32]
wire [127:0] remapped_write_data_lo = {remapped_write_data_lo_hi, remapped_write_data_lo_lo}; // @[MemWriter32.scala:202:32]
wire [15:0] remapped_write_data_hi_lo_lo_lo = {remapVecData_17, remapVecData_16}; // @[MemWriter32.scala:127:26, :202:32]
wire [15:0] remapped_write_data_hi_lo_lo_hi = {remapVecData_19, remapVecData_18}; // @[MemWriter32.scala:127:26, :202:32]
wire [31:0] remapped_write_data_hi_lo_lo = {remapped_write_data_hi_lo_lo_hi, remapped_write_data_hi_lo_lo_lo}; // @[MemWriter32.scala:202:32]
wire [15:0] remapped_write_data_hi_lo_hi_lo = {remapVecData_21, remapVecData_20}; // @[MemWriter32.scala:127:26, :202:32]
wire [15:0] remapped_write_data_hi_lo_hi_hi = {remapVecData_23, remapVecData_22}; // @[MemWriter32.scala:127:26, :202:32]
wire [31:0] remapped_write_data_hi_lo_hi = {remapped_write_data_hi_lo_hi_hi, remapped_write_data_hi_lo_hi_lo}; // @[MemWriter32.scala:202:32]
wire [63:0] remapped_write_data_hi_lo = {remapped_write_data_hi_lo_hi, remapped_write_data_hi_lo_lo}; // @[MemWriter32.scala:202:32]
wire [15:0] remapped_write_data_hi_hi_lo_lo = {remapVecData_25, remapVecData_24}; // @[MemWriter32.scala:127:26, :202:32]
wire [15:0] remapped_write_data_hi_hi_lo_hi = {remapVecData_27, remapVecData_26}; // @[MemWriter32.scala:127:26, :202:32]
wire [31:0] remapped_write_data_hi_hi_lo = {remapped_write_data_hi_hi_lo_hi, remapped_write_data_hi_hi_lo_lo}; // @[MemWriter32.scala:202:32]
wire [15:0] remapped_write_data_hi_hi_hi_lo = {remapVecData_29, remapVecData_28}; // @[MemWriter32.scala:127:26, :202:32]
wire [15:0] remapped_write_data_hi_hi_hi_hi = {remapVecData_31, remapVecData_30}; // @[MemWriter32.scala:127:26, :202:32]
wire [31:0] remapped_write_data_hi_hi_hi = {remapped_write_data_hi_hi_hi_hi, remapped_write_data_hi_hi_hi_lo}; // @[MemWriter32.scala:202:32]
wire [63:0] remapped_write_data_hi_hi = {remapped_write_data_hi_hi_hi, remapped_write_data_hi_hi_lo}; // @[MemWriter32.scala:202:32]
wire [127:0] remapped_write_data_hi = {remapped_write_data_hi_hi, remapped_write_data_hi_lo}; // @[MemWriter32.scala:202:32]
wire [255:0] remapped_write_data = {remapped_write_data_hi, remapped_write_data_lo}; // @[MemWriter32.scala:202:32]
wire enough_data = |bytes_to_write; // @[MemWriter32.scala:193:27, :204:36]
wire _bytes_to_write_log2_T = ptr_align_max_bytes_writeable_log2 < count_valids_largest_aligned_log2; // @[MemWriter32.scala:170:47, :185:46, :207:40]
wire _bytes_to_write_log2_T_1 = ptr_align_max_bytes_writeable_log2 < throttle_end_writeable_log2; // @[MemWriter32.scala:155:40, :170:47, :208:44]
wire [2:0] _bytes_to_write_log2_T_2 = _bytes_to_write_log2_T_1 ? ptr_align_max_bytes_writeable_log2 : throttle_end_writeable_log2; // @[MemWriter32.scala:155:40, :170:47, :208:{8,44}]
wire _bytes_to_write_log2_T_3 = count_valids_largest_aligned_log2 < throttle_end_writeable_log2; // @[MemWriter32.scala:155:40, :185:46, :211:43]
wire [2:0] _bytes_to_write_log2_T_4 = _bytes_to_write_log2_T_3 ? count_valids_largest_aligned_log2 : throttle_end_writeable_log2; // @[MemWriter32.scala:155:40, :185:46, :211:{8,43}]
wire [2:0] bytes_to_write_log2 = _bytes_to_write_log2_T ? _bytes_to_write_log2_T_2 : _bytes_to_write_log2_T_4; // @[MemWriter32.scala:206:32, :207:40, :208:8, :211:8]
wire _write_ptr_override_T = _buf_lens_Q_io_deq_bits == backend_bytes_written; // @[MemWriter32.scala:45:26, :140:38, :216:79]
wire write_ptr_override = _buf_lens_Q_io_deq_valid & _write_ptr_override_T; // @[MemWriter32.scala:45:26, :216:{52,79}]
wire _remapVecReadys_0_T = |bytes_to_write; // @[MemWriter32.scala:193:27, :204:36, :233:43]
wire _T_205 = io_l2io_req_ready_0 & enough_data; // @[Misc.scala:29:18]
wire _remapVecReadys_0_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_0_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_1_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_1_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_2_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_2_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_3_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_3_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_4_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_4_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_5_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_5_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_6_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_6_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_7_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_7_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_8_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_8_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_9_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_9_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_10_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_10_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_11_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_11_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_12_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_12_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_13_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_13_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_14_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_14_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_15_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_15_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_16_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_16_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_17_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_17_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_18_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_18_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_19_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_19_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_20_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_20_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_21_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_21_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_22_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_22_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_23_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_23_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_24_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_24_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_25_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_25_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_26_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_26_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_27_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_27_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_28_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_28_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_29_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_29_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_30_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_30_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_31_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_31_T_1 = _T_205; // @[Misc.scala:29:18]
wire _remapVecReadys_0_T_2 = _remapVecReadys_0_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_0_T_3 = _remapVecReadys_0_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_0_T_4 = _remapVecReadys_0_T & _remapVecReadys_0_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_0 = _remapVecReadys_0_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_1_T = |(bytes_to_write[5:1]); // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_1_T_2 = _remapVecReadys_1_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_1_T_3 = _remapVecReadys_1_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_1_T_4 = _remapVecReadys_1_T & _remapVecReadys_1_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_1 = _remapVecReadys_1_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_2_T = bytes_to_write > 6'h2; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_2_T_2 = _remapVecReadys_2_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_2_T_3 = _remapVecReadys_2_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_2_T_4 = _remapVecReadys_2_T & _remapVecReadys_2_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_2 = _remapVecReadys_2_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_3_T = |(bytes_to_write[5:2]); // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_3_T_2 = _remapVecReadys_3_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_3_T_3 = _remapVecReadys_3_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_3_T_4 = _remapVecReadys_3_T & _remapVecReadys_3_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_3 = _remapVecReadys_3_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_4_T = bytes_to_write > 6'h4; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_4_T_2 = _remapVecReadys_4_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_4_T_3 = _remapVecReadys_4_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_4_T_4 = _remapVecReadys_4_T & _remapVecReadys_4_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_4 = _remapVecReadys_4_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_5_T = bytes_to_write > 6'h5; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_5_T_2 = _remapVecReadys_5_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_5_T_3 = _remapVecReadys_5_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_5_T_4 = _remapVecReadys_5_T & _remapVecReadys_5_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_5 = _remapVecReadys_5_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_6_T = bytes_to_write > 6'h6; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_6_T_2 = _remapVecReadys_6_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_6_T_3 = _remapVecReadys_6_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_6_T_4 = _remapVecReadys_6_T & _remapVecReadys_6_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_6 = _remapVecReadys_6_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_7_T = |(bytes_to_write[5:3]); // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_7_T_2 = _remapVecReadys_7_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_7_T_3 = _remapVecReadys_7_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_7_T_4 = _remapVecReadys_7_T & _remapVecReadys_7_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_7 = _remapVecReadys_7_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_8_T = bytes_to_write > 6'h8; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_8_T_2 = _remapVecReadys_8_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_8_T_3 = _remapVecReadys_8_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_8_T_4 = _remapVecReadys_8_T & _remapVecReadys_8_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_8 = _remapVecReadys_8_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_9_T = bytes_to_write > 6'h9; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_9_T_2 = _remapVecReadys_9_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_9_T_3 = _remapVecReadys_9_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_9_T_4 = _remapVecReadys_9_T & _remapVecReadys_9_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_9 = _remapVecReadys_9_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_10_T = bytes_to_write > 6'hA; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_10_T_2 = _remapVecReadys_10_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_10_T_3 = _remapVecReadys_10_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_10_T_4 = _remapVecReadys_10_T & _remapVecReadys_10_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_10 = _remapVecReadys_10_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_11_T = bytes_to_write > 6'hB; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_11_T_2 = _remapVecReadys_11_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_11_T_3 = _remapVecReadys_11_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_11_T_4 = _remapVecReadys_11_T & _remapVecReadys_11_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_11 = _remapVecReadys_11_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_12_T = bytes_to_write > 6'hC; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_12_T_2 = _remapVecReadys_12_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_12_T_3 = _remapVecReadys_12_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_12_T_4 = _remapVecReadys_12_T & _remapVecReadys_12_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_12 = _remapVecReadys_12_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_13_T = bytes_to_write > 6'hD; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_13_T_2 = _remapVecReadys_13_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_13_T_3 = _remapVecReadys_13_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_13_T_4 = _remapVecReadys_13_T & _remapVecReadys_13_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_13 = _remapVecReadys_13_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_14_T = bytes_to_write > 6'hE; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_14_T_2 = _remapVecReadys_14_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_14_T_3 = _remapVecReadys_14_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_14_T_4 = _remapVecReadys_14_T & _remapVecReadys_14_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_14 = _remapVecReadys_14_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_15_T = |(bytes_to_write[5:4]); // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_15_T_2 = _remapVecReadys_15_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_15_T_3 = _remapVecReadys_15_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_15_T_4 = _remapVecReadys_15_T & _remapVecReadys_15_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_15 = _remapVecReadys_15_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_16_T = bytes_to_write > 6'h10; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_16_T_2 = _remapVecReadys_16_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_16_T_3 = _remapVecReadys_16_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_16_T_4 = _remapVecReadys_16_T & _remapVecReadys_16_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_16 = _remapVecReadys_16_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_17_T = bytes_to_write > 6'h11; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_17_T_2 = _remapVecReadys_17_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_17_T_3 = _remapVecReadys_17_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_17_T_4 = _remapVecReadys_17_T & _remapVecReadys_17_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_17 = _remapVecReadys_17_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_18_T = bytes_to_write > 6'h12; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_18_T_2 = _remapVecReadys_18_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_18_T_3 = _remapVecReadys_18_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_18_T_4 = _remapVecReadys_18_T & _remapVecReadys_18_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_18 = _remapVecReadys_18_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_19_T = bytes_to_write > 6'h13; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_19_T_2 = _remapVecReadys_19_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_19_T_3 = _remapVecReadys_19_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_19_T_4 = _remapVecReadys_19_T & _remapVecReadys_19_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_19 = _remapVecReadys_19_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_20_T = bytes_to_write > 6'h14; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_20_T_2 = _remapVecReadys_20_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_20_T_3 = _remapVecReadys_20_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_20_T_4 = _remapVecReadys_20_T & _remapVecReadys_20_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_20 = _remapVecReadys_20_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_21_T = bytes_to_write > 6'h15; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_21_T_2 = _remapVecReadys_21_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_21_T_3 = _remapVecReadys_21_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_21_T_4 = _remapVecReadys_21_T & _remapVecReadys_21_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_21 = _remapVecReadys_21_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_22_T = bytes_to_write > 6'h16; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_22_T_2 = _remapVecReadys_22_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_22_T_3 = _remapVecReadys_22_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_22_T_4 = _remapVecReadys_22_T & _remapVecReadys_22_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_22 = _remapVecReadys_22_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_23_T = bytes_to_write > 6'h17; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_23_T_2 = _remapVecReadys_23_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_23_T_3 = _remapVecReadys_23_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_23_T_4 = _remapVecReadys_23_T & _remapVecReadys_23_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_23 = _remapVecReadys_23_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_24_T = bytes_to_write > 6'h18; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_24_T_2 = _remapVecReadys_24_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_24_T_3 = _remapVecReadys_24_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_24_T_4 = _remapVecReadys_24_T & _remapVecReadys_24_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_24 = _remapVecReadys_24_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_25_T = bytes_to_write > 6'h19; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_25_T_2 = _remapVecReadys_25_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_25_T_3 = _remapVecReadys_25_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_25_T_4 = _remapVecReadys_25_T & _remapVecReadys_25_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_25 = _remapVecReadys_25_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_26_T = bytes_to_write > 6'h1A; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_26_T_2 = _remapVecReadys_26_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_26_T_3 = _remapVecReadys_26_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_26_T_4 = _remapVecReadys_26_T & _remapVecReadys_26_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_26 = _remapVecReadys_26_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_27_T = bytes_to_write > 6'h1B; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_27_T_2 = _remapVecReadys_27_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_27_T_3 = _remapVecReadys_27_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_27_T_4 = _remapVecReadys_27_T & _remapVecReadys_27_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_27 = _remapVecReadys_27_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_28_T = bytes_to_write > 6'h1C; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_28_T_2 = _remapVecReadys_28_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_28_T_3 = _remapVecReadys_28_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_28_T_4 = _remapVecReadys_28_T & _remapVecReadys_28_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_28 = _remapVecReadys_28_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_29_T = bytes_to_write > 6'h1D; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_29_T_2 = _remapVecReadys_29_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_29_T_3 = _remapVecReadys_29_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_29_T_4 = _remapVecReadys_29_T & _remapVecReadys_29_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_29 = _remapVecReadys_29_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_30_T = bytes_to_write > 6'h1E; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_30_T_2 = _remapVecReadys_30_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_30_T_3 = _remapVecReadys_30_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_30_T_4 = _remapVecReadys_30_T & _remapVecReadys_30_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_30 = _remapVecReadys_30_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _remapVecReadys_31_T = bytes_to_write[5]; // @[MemWriter32.scala:193:27, :233:43]
wire _remapVecReadys_31_T_2 = _remapVecReadys_31_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_31_T_3 = _remapVecReadys_31_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_31_T_4 = _remapVecReadys_31_T & _remapVecReadys_31_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_31 = _remapVecReadys_31_T_4; // @[MemWriter32.scala:129:28, :233:61]
wire _T_207 = _T_205 & ~write_ptr_override & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
wire [6:0] _read_start_index_T = _remapindex_T + {1'h0, bytes_to_write}; // @[MemWriter32.scala:132:33, :193:27, :237:43]
wire [6:0] _GEN_95 = _read_start_index_T % 7'h20; // @[MemWriter32.scala:237:{43,62}]
wire [5:0] _read_start_index_T_1 = _GEN_95[5:0]; // @[MemWriter32.scala:237:62]
wire [64:0] _backend_bytes_written_T = _GEN_94 + {59'h0, bytes_to_write}; // @[MemWriter32.scala:141:71, :193:27, :238:52]
wire [63:0] _backend_bytes_written_T_1 = _backend_bytes_written_T[63:0]; // @[MemWriter32.scala:238:52]
reg [63:0] allargs_0_35; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_70 = {1'h0, allargs_0_35} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Logger.scala:38:38]
wire _io_l2io_req_valid_T = enough_data & ~write_ptr_override; // @[Misc.scala:26:53]
wire _io_l2io_req_valid_T_1 = _io_l2io_req_valid_T & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:26:53]
wire _io_l2io_req_valid_T_2 = _buf_lens_Q_io_deq_valid & _write_ptr_override_T; // @[Misc.scala:26:53]
wire _io_l2io_req_valid_T_3 = _io_l2io_req_valid_T_2 & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:26:53]
assign _io_l2io_req_valid_T_4 = _io_l2io_req_valid_T_1 | _io_l2io_req_valid_T_3; // @[Misc.scala:26:53]
assign io_l2io_req_valid_0 = _io_l2io_req_valid_T_4; // @[MemWriter32.scala:14:7, :248:65]
assign _io_l2io_req_bits_size_T = write_ptr_override ? 3'h0 : bytes_to_write_log2; // @[MemWriter32.scala:206:32, :216:52, :252:31]
assign io_l2io_req_bits_size_0 = _io_l2io_req_bits_size_T; // @[MemWriter32.scala:14:7, :252:31]
assign _io_l2io_req_bits_addr_T = write_ptr_override ? _decompress_dest_info_Q_io_deq_bits_cmpflag : backend_next_write_addr; // @[MemWriter32.scala:32:38, :141:71, :216:52, :253:31]
assign io_l2io_req_bits_addr_0 = _io_l2io_req_bits_addr_T; // @[MemWriter32.scala:14:7, :253:31]
assign _io_l2io_req_bits_data_T = write_ptr_override ? 256'h1 : remapped_write_data; // @[MemWriter32.scala:202:32, :216:52, :254:31]
assign io_l2io_req_bits_data_0 = _io_l2io_req_bits_data_T; // @[MemWriter32.scala:14:7, :254:31]
wire _buf_lens_Q_io_deq_ready_T = io_l2io_req_ready_0 & _write_ptr_override_T; // @[Misc.scala:26:53]
wire _buf_lens_Q_io_deq_ready_T_1 = _buf_lens_Q_io_deq_ready_T & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:26:53]
wire _decompress_dest_info_Q_io_deq_ready_T = io_l2io_req_ready_0 & _buf_lens_Q_io_deq_valid; // @[Misc.scala:26:53]
assign _decompress_dest_info_Q_io_deq_ready_T_1 = _decompress_dest_info_Q_io_deq_ready_T & _write_ptr_override_T; // @[Misc.scala:26:53]
reg [63:0] bufs_completed; // @[MemWriter32.scala:260:31]
assign io_bufs_completed_0 = bufs_completed; // @[MemWriter32.scala:14:7, :260:31]
wire _T_212 = _decompress_dest_info_Q_io_deq_ready_T & _write_ptr_override_T & _decompress_dest_info_Q_io_deq_valid; // @[Misc.scala:26:53, :29:18]
wire [64:0] _bufs_completed_T = {1'h0, bufs_completed} + 65'h1; // @[MemWriter32.scala:260:31, :268:38]
wire [63:0] _bufs_completed_T_1 = _bufs_completed_T[63:0]; // @[MemWriter32.scala:268:38]
reg [63:0] allargs_0_36; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_72 = {1'h0, allargs_0_36} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_37; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_74 = {1'h0, allargs_0_37} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Logger.scala:38:38]
|
Generate the Verilog code corresponding to the following Chisel files.
File DivSqrtRecFN_small.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2017 SiFive, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of SiFive nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY SIFIVE AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL SIFIVE OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*
s = sigWidth
c_i = newBit
Division:
width of a is (s+2)
Normal
------
(qi + ci * 2^(-i))*b <= a
q0 = 0
r0 = a
q(i+1) = qi + ci*2^(-i)
ri = a - qi*b
r(i+1) = a - q(i+1)*b
= a - qi*b - ci*2^(-i)*b
r(i+1) = ri - ci*2^(-i)*b
ci = ri >= 2^(-i)*b
summary_i = ri != 0
i = 0 to s+1
(s+1)th bit plus summary_(i+1) gives enough information for rounding
If (a < b), then we need to calculate (s+2)th bit and summary_(i+1)
because we need s bits ignoring the leading zero. (This is skipCycle2
part of Hauser's code.)
Hauser
------
sig_i = qi
rem_i = 2^(i-2)*ri
cycle_i = s+3-i
sig_0 = 0
rem_0 = a/4
cycle_0 = s+3
bit_0 = 2^0 (= 2^(s+1), since we represent a, b and q with (s+2) bits)
sig(i+1) = sig(i) + ci*bit_i
rem(i+1) = 2rem_i - ci*b/2
ci = 2rem_i >= b/2
bit_i = 2^-i (=2^(cycle_i-2), since we represent a, b and q with (s+2) bits)
cycle(i+1) = cycle_i-1
summary_1 = a <> b
summary(i+1) = if ci then 2rem_i-b/2 <> 0 else summary_i, i <> 0
Proof:
2^i*r(i+1) = 2^i*ri - ci*b. Qed
ci = 2^i*ri >= b. Qed
summary(i+1) = if ci then rem(i+1) else summary_i, i <> 0
Now, note that all of ck's cannot be 0, since that means
a is 0. So when you traverse through a chain of 0 ck's,
from the end,
eventually, you reach a non-zero cj. That is exactly the
value of ri as the reminder remains the same. When all ck's
are 0 except c0 (which must be 1) then summary_1 is set
correctly according
to r1 = a-b != 0. So summary(i+1) is always set correctly
according to r(i+1)
Square root:
width of a is (s+1)
Normal
------
(xi + ci*2^(-i))^2 <= a
xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)) <= a
x0 = 0
x(i+1) = xi + ci*2^(-i)
ri = a - xi^2
r(i+1) = a - x(i+1)^2
= a - (xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)))
= ri - ci*2^(-i)*(2xi+ci*2^(-i))
= ri - ci*2^(-i)*(2xi+2^(-i)) // ci is always 0 or 1
ci = ri >= 2^(-i)*(2xi + 2^(-i))
summary_i = ri != 0
i = 0 to s+1
For odd expression, do 2 steps initially.
(s+1)th bit plus summary_(i+1) gives enough information for rounding.
Hauser
------
sig_i = xi
rem_i = ri*2^(i-1)
cycle_i = s+2-i
bit_i = 2^(-i) (= 2^(s-i) = 2^(cycle_i-2) in terms of bit representation)
sig_0 = 0
rem_0 = a/2
cycle_0 = s+2
bit_0 = 1 (= 2^s in terms of bit representation)
sig(i+1) = sig_i + ci * bit_i
rem(i+1) = 2rem_i - ci*(2sig_i + bit_i)
ci = 2*sig_i + bit_i <= 2*rem_i
bit_i = 2^(cycle_i-2) (in terms of bit representation)
cycle(i+1) = cycle_i-1
summary_1 = a - (2^s) (in terms of bit representation)
summary(i+1) = if ci then rem(i+1) <> 0 else summary_i, i <> 0
Proof:
ci = 2*sig_i + bit_i <= 2*rem_i
ci = 2xi + 2^(-i) <= ri*2^i. Qed
sig(i+1) = sig_i + ci * bit_i
x(i+1) = xi + ci*2^(-i). Qed
rem(i+1) = 2rem_i - ci*(2sig_i + bit_i)
r(i+1)*2^i = ri*2^i - ci*(2xi + 2^(-i))
r(i+1) = ri - ci*2^(-i)*(2xi + 2^(-i)). Qed
Same argument as before for summary.
------------------------------
Note that all registers are updated normally until cycle == 2.
At cycle == 2, rem is not updated, but all other registers are updated normally.
But, cycle == 1 does not read rem to calculate anything (note that final summary
is calculated using the values at cycle = 2).
*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
/*----------------------------------------------------------------------------
| Computes a division or square root for floating-point in recoded form.
| Multiple clock cycles are needed for each division or square-root operation,
| except possibly in special cases.
*----------------------------------------------------------------------------*/
class
DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(new RawFloat(expWidth, sigWidth))
val b = Input(new RawFloat(expWidth, sigWidth))
val roundingMode = Input(UInt(3.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val rawOutValid_div = Output(Bool())
val rawOutValid_sqrt = Output(Bool())
val roundingModeOut = Output(UInt(3.W))
val invalidExc = Output(Bool())
val infiniteExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val cycleNum = RegInit(0.U(log2Ceil(sigWidth + 3).W))
val inReady = RegInit(true.B) // <-> (cycleNum <= 1)
val rawOutValid = RegInit(false.B) // <-> (cycleNum === 1)
val sqrtOp_Z = Reg(Bool())
val majorExc_Z = Reg(Bool())
//*** REDUCE 3 BITS TO 2-BIT CODE:
val isNaN_Z = Reg(Bool())
val isInf_Z = Reg(Bool())
val isZero_Z = Reg(Bool())
val sign_Z = Reg(Bool())
val sExp_Z = Reg(SInt((expWidth + 2).W))
val fractB_Z = Reg(UInt(sigWidth.W))
val roundingMode_Z = Reg(UInt(3.W))
/*------------------------------------------------------------------------
| (The most-significant and least-significant bits of 'rem_Z' are needed
| only for square roots.)
*------------------------------------------------------------------------*/
val rem_Z = Reg(UInt((sigWidth + 2).W))
val notZeroRem_Z = Reg(Bool())
val sigX_Z = Reg(UInt((sigWidth + 2).W))
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val rawA_S = io.a
val rawB_S = io.b
//*** IMPROVE THESE:
val notSigNaNIn_invalidExc_S_div =
(rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf)
val notSigNaNIn_invalidExc_S_sqrt =
! rawA_S.isNaN && ! rawA_S.isZero && rawA_S.sign
val majorExc_S =
Mux(io.sqrtOp,
isSigNaNRawFloat(rawA_S) || notSigNaNIn_invalidExc_S_sqrt,
isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) ||
notSigNaNIn_invalidExc_S_div ||
(! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero)
)
val isNaN_S =
Mux(io.sqrtOp,
rawA_S.isNaN || notSigNaNIn_invalidExc_S_sqrt,
rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div
)
val isInf_S = Mux(io.sqrtOp, rawA_S.isInf, rawA_S.isInf || rawB_S.isZero)
val isZero_S = Mux(io.sqrtOp, rawA_S.isZero, rawA_S.isZero || rawB_S.isInf)
val sign_S = rawA_S.sign ^ (! io.sqrtOp && rawB_S.sign)
val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero
val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero
val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S
val normalCase_S_sqrt = ! specialCaseA_S && ! rawA_S.sign
val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)
val sExpQuot_S_div =
rawA_S.sExp +&
Cat(rawB_S.sExp(expWidth), ~rawB_S.sExp(expWidth - 1, 0)).asSInt
//*** IS THIS OPTIMAL?:
val sSatExpQuot_S_div =
Cat(Mux(((BigInt(7)<<(expWidth - 2)).S <= sExpQuot_S_div),
6.U,
sExpQuot_S_div(expWidth + 1, expWidth - 2)
),
sExpQuot_S_div(expWidth - 3, 0)
).asSInt
val evenSqrt_S = io.sqrtOp && ! rawA_S.sExp(0)
val oddSqrt_S = io.sqrtOp && rawA_S.sExp(0)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val idle = cycleNum === 0.U
val entering = inReady && io.inValid
val entering_normalCase = entering && normalCase_S
val processTwoBits = cycleNum >= 3.U && ((options & divSqrtOpt_twoBitsPerCycle) != 0).B
val skipCycle2 = cycleNum === 3.U && sigX_Z(sigWidth + 1) && ((options & divSqrtOpt_twoBitsPerCycle) == 0).B
when (! idle || entering) {
def computeCycleNum(f: UInt => UInt): UInt = {
Mux(entering & ! normalCase_S, f(1.U), 0.U) |
Mux(entering_normalCase,
Mux(io.sqrtOp,
Mux(rawA_S.sExp(0), f(sigWidth.U), f((sigWidth + 1).U)),
f((sigWidth + 2).U)
),
0.U
) |
Mux(! entering && ! skipCycle2, f(cycleNum - Mux(processTwoBits, 2.U, 1.U)), 0.U) |
Mux(skipCycle2, f(1.U), 0.U)
}
inReady := computeCycleNum(_ <= 1.U).asBool
rawOutValid := computeCycleNum(_ === 1.U).asBool
cycleNum := computeCycleNum(x => x)
}
io.inReady := inReady
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
when (entering) {
sqrtOp_Z := io.sqrtOp
majorExc_Z := majorExc_S
isNaN_Z := isNaN_S
isInf_Z := isInf_S
isZero_Z := isZero_S
sign_Z := sign_S
sExp_Z :=
Mux(io.sqrtOp,
(rawA_S.sExp>>1) +& (BigInt(1)<<(expWidth - 1)).S,
sSatExpQuot_S_div
)
roundingMode_Z := io.roundingMode
}
when (entering || ! inReady && sqrtOp_Z) {
fractB_Z :=
Mux(inReady && ! io.sqrtOp, rawB_S.sig(sigWidth - 2, 0)<<1, 0.U) |
Mux(inReady && io.sqrtOp && rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 2)).U, 0.U) |
Mux(inReady && io.sqrtOp && ! rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 1)).U, 0.U) |
Mux(! inReady /* sqrtOp_Z */ && processTwoBits, fractB_Z>>2, 0.U) |
Mux(! inReady /* sqrtOp_Z */ && ! processTwoBits, fractB_Z>>1, 0.U)
}
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val rem =
Mux(inReady && ! oddSqrt_S, rawA_S.sig<<1, 0.U) |
Mux(inReady && oddSqrt_S,
Cat(rawA_S.sig(sigWidth - 1, sigWidth - 2) - 1.U,
rawA_S.sig(sigWidth - 3, 0)<<3
),
0.U
) |
Mux(! inReady, rem_Z<<1, 0.U)
val bitMask = (1.U<<cycleNum)>>2
val trialTerm =
Mux(inReady && ! io.sqrtOp, rawB_S.sig<<1, 0.U) |
Mux(inReady && evenSqrt_S, (BigInt(1)<<sigWidth).U, 0.U) |
Mux(inReady && oddSqrt_S, (BigInt(5)<<(sigWidth - 1)).U, 0.U) |
Mux(! inReady, fractB_Z, 0.U) |
Mux(! inReady && ! sqrtOp_Z, 1.U << sigWidth, 0.U) |
Mux(! inReady && sqrtOp_Z, sigX_Z<<1, 0.U)
val trialRem = rem.zext -& trialTerm.zext
val newBit = (0.S <= trialRem)
val nextRem_Z = Mux(newBit, trialRem.asUInt, rem)(sigWidth + 1, 0)
val rem2 = nextRem_Z<<1
val trialTerm2_newBit0 = Mux(sqrtOp_Z, fractB_Z>>1 | sigX_Z<<1, fractB_Z | (1.U << sigWidth))
val trialTerm2_newBit1 = trialTerm2_newBit0 | Mux(sqrtOp_Z, fractB_Z<<1, 0.U)
val trialRem2 =
Mux(newBit,
(trialRem<<1) - trialTerm2_newBit1.zext,
(rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext)
val newBit2 = (0.S <= trialRem2)
val nextNotZeroRem_Z = Mux(inReady || newBit, trialRem =/= 0.S, notZeroRem_Z)
val nextNotZeroRem_Z_2 = // <-> Mux(newBit2, trialRem2 =/= 0.S, nextNotZeroRem_Z)
processTwoBits && newBit && (0.S < (trialRem<<1) - trialTerm2_newBit1.zext) ||
processTwoBits && !newBit && (0.S < (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) ||
!(processTwoBits && newBit2) && nextNotZeroRem_Z
val nextRem_Z_2 =
Mux(processTwoBits && newBit2, trialRem2.asUInt(sigWidth + 1, 0), 0.U) |
Mux(processTwoBits && !newBit2, rem2(sigWidth + 1, 0), 0.U) |
Mux(!processTwoBits, nextRem_Z, 0.U)
when (entering || ! inReady) {
notZeroRem_Z := nextNotZeroRem_Z_2
rem_Z := nextRem_Z_2
sigX_Z :=
Mux(inReady && ! io.sqrtOp, newBit<<(sigWidth + 1), 0.U) |
Mux(inReady && io.sqrtOp, (BigInt(1)<<sigWidth).U, 0.U) |
Mux(inReady && oddSqrt_S, newBit<<(sigWidth - 1), 0.U) |
Mux(! inReady, sigX_Z, 0.U) |
Mux(! inReady && newBit, bitMask, 0.U) |
Mux(processTwoBits && newBit2, bitMask>>1, 0.U)
}
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
io.rawOutValid_div := rawOutValid && ! sqrtOp_Z
io.rawOutValid_sqrt := rawOutValid && sqrtOp_Z
io.roundingModeOut := roundingMode_Z
io.invalidExc := majorExc_Z && isNaN_Z
io.infiniteExc := majorExc_Z && ! isNaN_Z
io.rawOut.isNaN := isNaN_Z
io.rawOut.isInf := isInf_Z
io.rawOut.isZero := isZero_Z
io.rawOut.sign := sign_Z
io.rawOut.sExp := sExp_Z
io.rawOut.sig := sigX_Z<<1 | notZeroRem_Z
}
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
class
DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val rawOutValid_div = Output(Bool())
val rawOutValid_sqrt = Output(Bool())
val roundingModeOut = Output(UInt(3.W))
val invalidExc = Output(Bool())
val infiniteExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
val divSqrtRawFN =
Module(new DivSqrtRawFN_small(expWidth, sigWidth, options))
io.inReady := divSqrtRawFN.io.inReady
divSqrtRawFN.io.inValid := io.inValid
divSqrtRawFN.io.sqrtOp := io.sqrtOp
divSqrtRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)
divSqrtRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)
divSqrtRawFN.io.roundingMode := io.roundingMode
io.rawOutValid_div := divSqrtRawFN.io.rawOutValid_div
io.rawOutValid_sqrt := divSqrtRawFN.io.rawOutValid_sqrt
io.roundingModeOut := divSqrtRawFN.io.roundingModeOut
io.invalidExc := divSqrtRawFN.io.invalidExc
io.infiniteExc := divSqrtRawFN.io.infiniteExc
io.rawOut := divSqrtRawFN.io.rawOut
}
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
class
DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val outValid_div = Output(Bool())
val outValid_sqrt = Output(Bool())
val out = Output(UInt((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(UInt(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val divSqrtRecFNToRaw =
Module(new DivSqrtRecFNToRaw_small(expWidth, sigWidth, options))
io.inReady := divSqrtRecFNToRaw.io.inReady
divSqrtRecFNToRaw.io.inValid := io.inValid
divSqrtRecFNToRaw.io.sqrtOp := io.sqrtOp
divSqrtRecFNToRaw.io.a := io.a
divSqrtRecFNToRaw.io.b := io.b
divSqrtRecFNToRaw.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.outValid_div := divSqrtRecFNToRaw.io.rawOutValid_div
io.outValid_sqrt := divSqrtRecFNToRaw.io.rawOutValid_sqrt
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := divSqrtRecFNToRaw.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := divSqrtRecFNToRaw.io.infiniteExc
roundRawFNToRecFN.io.in := divSqrtRecFNToRaw.io.rawOut
roundRawFNToRecFN.io.roundingMode := divSqrtRecFNToRaw.io.roundingModeOut
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
|
module DivSqrtRawFN_small_e11_s53_2( // @[DivSqrtRecFN_small.scala:199:5]
input clock, // @[DivSqrtRecFN_small.scala:199:5]
input reset, // @[DivSqrtRecFN_small.scala:199:5]
output io_inReady, // @[DivSqrtRecFN_small.scala:203:16]
input io_inValid, // @[DivSqrtRecFN_small.scala:203:16]
input io_sqrtOp, // @[DivSqrtRecFN_small.scala:203:16]
input io_a_isNaN, // @[DivSqrtRecFN_small.scala:203:16]
input io_a_isInf, // @[DivSqrtRecFN_small.scala:203:16]
input io_a_isZero, // @[DivSqrtRecFN_small.scala:203:16]
input io_a_sign, // @[DivSqrtRecFN_small.scala:203:16]
input [12:0] io_a_sExp, // @[DivSqrtRecFN_small.scala:203:16]
input [53:0] io_a_sig, // @[DivSqrtRecFN_small.scala:203:16]
input io_b_isNaN, // @[DivSqrtRecFN_small.scala:203:16]
input io_b_isInf, // @[DivSqrtRecFN_small.scala:203:16]
input io_b_isZero, // @[DivSqrtRecFN_small.scala:203:16]
input io_b_sign, // @[DivSqrtRecFN_small.scala:203:16]
input [12:0] io_b_sExp, // @[DivSqrtRecFN_small.scala:203:16]
input [53:0] io_b_sig, // @[DivSqrtRecFN_small.scala:203:16]
input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:203:16]
output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:203:16]
output io_invalidExc, // @[DivSqrtRecFN_small.scala:203:16]
output io_infiniteExc, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:203:16]
output [12:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:203:16]
output [55:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:203:16]
);
wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:199:5]
wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:199:5]
wire io_a_isNaN_0 = io_a_isNaN; // @[DivSqrtRecFN_small.scala:199:5]
wire io_a_isInf_0 = io_a_isInf; // @[DivSqrtRecFN_small.scala:199:5]
wire io_a_isZero_0 = io_a_isZero; // @[DivSqrtRecFN_small.scala:199:5]
wire io_a_sign_0 = io_a_sign; // @[DivSqrtRecFN_small.scala:199:5]
wire [12:0] io_a_sExp_0 = io_a_sExp; // @[DivSqrtRecFN_small.scala:199:5]
wire [53:0] io_a_sig_0 = io_a_sig; // @[DivSqrtRecFN_small.scala:199:5]
wire io_b_isNaN_0 = io_b_isNaN; // @[DivSqrtRecFN_small.scala:199:5]
wire io_b_isInf_0 = io_b_isInf; // @[DivSqrtRecFN_small.scala:199:5]
wire io_b_isZero_0 = io_b_isZero; // @[DivSqrtRecFN_small.scala:199:5]
wire io_b_sign_0 = io_b_sign; // @[DivSqrtRecFN_small.scala:199:5]
wire [12:0] io_b_sExp_0 = io_b_sExp; // @[DivSqrtRecFN_small.scala:199:5]
wire [53:0] io_b_sig_0 = io_b_sig; // @[DivSqrtRecFN_small.scala:199:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:199:5]
wire [1:0] _inReady_T_15 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61]
wire [1:0] _rawOutValid_T_15 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61]
wire [1:0] _cycleNum_T_11 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61]
wire [50:0] _fractB_Z_T_19 = 51'h0; // @[DivSqrtRecFN_small.scala:345:16]
wire [53:0] _trialTerm_T_16 = 54'h20000000000000; // @[DivSqrtRecFN_small.scala:366:42]
wire [53:0] _trialTerm2_newBit0_T_3 = 54'h20000000000000; // @[DivSqrtRecFN_small.scala:373:85]
wire [54:0] _nextRem_Z_2_T_3 = 55'h0; // @[DivSqrtRecFN_small.scala:386:12]
wire [54:0] _nextRem_Z_2_T_7 = 55'h0; // @[DivSqrtRecFN_small.scala:387:12]
wire [54:0] _nextRem_Z_2_T_8 = 55'h0; // @[DivSqrtRecFN_small.scala:386:81]
wire _inReady_T_2 = 1'h1; // @[DivSqrtRecFN_small.scala:317:38]
wire _inReady_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:317:38]
wire _rawOutValid_T_2 = 1'h1; // @[DivSqrtRecFN_small.scala:318:42]
wire _rawOutValid_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:318:42]
wire _fractB_Z_T_22 = 1'h1; // @[DivSqrtRecFN_small.scala:346:45]
wire _nextNotZeroRem_Z_2_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:384:9]
wire _nextRem_Z_2_T_9 = 1'h1; // @[DivSqrtRecFN_small.scala:388:13]
wire processTwoBits = 1'h0; // @[DivSqrtRecFN_small.scala:300:42]
wire _inReady_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38]
wire _inReady_T_6 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38]
wire _inReady_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:308:24]
wire _inReady_T_8 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38]
wire _inReady_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:307:20]
wire _inReady_T_10 = 1'h0; // @[DivSqrtRecFN_small.scala:306:16]
wire _rawOutValid_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42]
wire _rawOutValid_T_6 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42]
wire _rawOutValid_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:308:24]
wire _rawOutValid_T_8 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42]
wire _rawOutValid_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:307:20]
wire _rawOutValid_T_10 = 1'h0; // @[DivSqrtRecFN_small.scala:306:16]
wire _fractB_Z_T_17 = 1'h0; // @[DivSqrtRecFN_small.scala:345:42]
wire _nextNotZeroRem_Z_2_T = 1'h0; // @[DivSqrtRecFN_small.scala:382:24]
wire _nextNotZeroRem_Z_2_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:382:34]
wire _nextNotZeroRem_Z_2_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:383:24]
wire _nextNotZeroRem_Z_2_T_18 = 1'h0; // @[DivSqrtRecFN_small.scala:383:35]
wire _nextNotZeroRem_Z_2_T_19 = 1'h0; // @[DivSqrtRecFN_small.scala:382:85]
wire _nextNotZeroRem_Z_2_T_20 = 1'h0; // @[DivSqrtRecFN_small.scala:384:26]
wire _nextRem_Z_2_T = 1'h0; // @[DivSqrtRecFN_small.scala:386:28]
wire _nextRem_Z_2_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:387:28]
wire _sigX_Z_T_18 = 1'h0; // @[DivSqrtRecFN_small.scala:399:32]
wire [60:0] _sigX_Z_T_20 = 61'h0; // @[DivSqrtRecFN_small.scala:399:16]
wire _io_rawOutValid_div_T_1; // @[DivSqrtRecFN_small.scala:404:40]
wire _io_rawOutValid_sqrt_T; // @[DivSqrtRecFN_small.scala:405:40]
wire _io_invalidExc_T; // @[DivSqrtRecFN_small.scala:407:36]
wire _io_infiniteExc_T_1; // @[DivSqrtRecFN_small.scala:408:36]
wire [55:0] _io_rawOut_sig_T_1; // @[DivSqrtRecFN_small.scala:414:35]
wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:199:5]
wire [12:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:199:5]
wire [55:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_inReady_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:199:5]
wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:199:5]
reg [5:0] cycleNum; // @[DivSqrtRecFN_small.scala:224:33]
reg inReady; // @[DivSqrtRecFN_small.scala:225:33]
assign io_inReady_0 = inReady; // @[DivSqrtRecFN_small.scala:199:5, :225:33]
reg rawOutValid; // @[DivSqrtRecFN_small.scala:226:33]
reg sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29]
reg majorExc_Z; // @[DivSqrtRecFN_small.scala:229:29]
reg isNaN_Z; // @[DivSqrtRecFN_small.scala:231:29]
assign io_rawOut_isNaN_0 = isNaN_Z; // @[DivSqrtRecFN_small.scala:199:5, :231:29]
reg isInf_Z; // @[DivSqrtRecFN_small.scala:232:29]
assign io_rawOut_isInf_0 = isInf_Z; // @[DivSqrtRecFN_small.scala:199:5, :232:29]
reg isZero_Z; // @[DivSqrtRecFN_small.scala:233:29]
assign io_rawOut_isZero_0 = isZero_Z; // @[DivSqrtRecFN_small.scala:199:5, :233:29]
reg sign_Z; // @[DivSqrtRecFN_small.scala:234:29]
assign io_rawOut_sign_0 = sign_Z; // @[DivSqrtRecFN_small.scala:199:5, :234:29]
reg [12:0] sExp_Z; // @[DivSqrtRecFN_small.scala:235:29]
assign io_rawOut_sExp_0 = sExp_Z; // @[DivSqrtRecFN_small.scala:199:5, :235:29]
reg [52:0] fractB_Z; // @[DivSqrtRecFN_small.scala:236:29]
reg [2:0] roundingMode_Z; // @[DivSqrtRecFN_small.scala:237:29]
assign io_roundingModeOut_0 = roundingMode_Z; // @[DivSqrtRecFN_small.scala:199:5, :237:29]
reg [54:0] rem_Z; // @[DivSqrtRecFN_small.scala:243:29]
reg notZeroRem_Z; // @[DivSqrtRecFN_small.scala:244:29]
reg [54:0] sigX_Z; // @[DivSqrtRecFN_small.scala:245:29]
wire _notSigNaNIn_invalidExc_S_div_T = io_a_isZero_0 & io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :254:24]
wire _notSigNaNIn_invalidExc_S_div_T_1 = io_a_isInf_0 & io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :254:59]
wire notSigNaNIn_invalidExc_S_div = _notSigNaNIn_invalidExc_S_div_T | _notSigNaNIn_invalidExc_S_div_T_1; // @[DivSqrtRecFN_small.scala:254:{24,42,59}]
wire _notSigNaNIn_invalidExc_S_sqrt_T = ~io_a_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :256:9]
wire _notSigNaNIn_invalidExc_S_sqrt_T_1 = ~io_a_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :256:27]
wire _notSigNaNIn_invalidExc_S_sqrt_T_2 = _notSigNaNIn_invalidExc_S_sqrt_T & _notSigNaNIn_invalidExc_S_sqrt_T_1; // @[DivSqrtRecFN_small.scala:256:{9,24,27}]
wire notSigNaNIn_invalidExc_S_sqrt = _notSigNaNIn_invalidExc_S_sqrt_T_2 & io_a_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :256:{24,43}]
wire _majorExc_S_T = io_a_sig_0[51]; // @[common.scala:82:56]
wire _majorExc_S_T_4 = io_a_sig_0[51]; // @[common.scala:82:56]
wire _majorExc_S_T_1 = ~_majorExc_S_T; // @[common.scala:82:{49,56}]
wire _majorExc_S_T_2 = io_a_isNaN_0 & _majorExc_S_T_1; // @[common.scala:82:{46,49}]
wire _majorExc_S_T_3 = _majorExc_S_T_2 | notSigNaNIn_invalidExc_S_sqrt; // @[common.scala:82:46]
wire _majorExc_S_T_5 = ~_majorExc_S_T_4; // @[common.scala:82:{49,56}]
wire _majorExc_S_T_6 = io_a_isNaN_0 & _majorExc_S_T_5; // @[common.scala:82:{46,49}]
wire _majorExc_S_T_7 = io_b_sig_0[51]; // @[common.scala:82:56]
wire _majorExc_S_T_8 = ~_majorExc_S_T_7; // @[common.scala:82:{49,56}]
wire _majorExc_S_T_9 = io_b_isNaN_0 & _majorExc_S_T_8; // @[common.scala:82:{46,49}]
wire _majorExc_S_T_10 = _majorExc_S_T_6 | _majorExc_S_T_9; // @[common.scala:82:46]
wire _majorExc_S_T_11 = _majorExc_S_T_10 | notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecFN_small.scala:254:42, :260:{38,66}]
wire _majorExc_S_T_12 = ~io_a_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :256:9, :262:18]
wire _majorExc_S_T_13 = ~io_a_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :262:36]
wire _majorExc_S_T_14 = _majorExc_S_T_12 & _majorExc_S_T_13; // @[DivSqrtRecFN_small.scala:262:{18,33,36}]
wire _majorExc_S_T_15 = _majorExc_S_T_14 & io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :262:{33,51}]
wire _majorExc_S_T_16 = _majorExc_S_T_11 | _majorExc_S_T_15; // @[DivSqrtRecFN_small.scala:260:66, :261:46, :262:51]
wire majorExc_S = io_sqrtOp_0 ? _majorExc_S_T_3 : _majorExc_S_T_16; // @[DivSqrtRecFN_small.scala:199:5, :258:12, :259:38, :261:46]
wire _isNaN_S_T = io_a_isNaN_0 | notSigNaNIn_invalidExc_S_sqrt; // @[DivSqrtRecFN_small.scala:199:5, :256:43, :266:26]
wire _isNaN_S_T_1 = io_a_isNaN_0 | io_b_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :267:26]
wire _isNaN_S_T_2 = _isNaN_S_T_1 | notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecFN_small.scala:254:42, :267:{26,42}]
wire isNaN_S = io_sqrtOp_0 ? _isNaN_S_T : _isNaN_S_T_2; // @[DivSqrtRecFN_small.scala:199:5, :265:12, :266:26, :267:42]
wire _isInf_S_T = io_a_isInf_0 | io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :269:63]
wire isInf_S = io_sqrtOp_0 ? io_a_isInf_0 : _isInf_S_T; // @[DivSqrtRecFN_small.scala:199:5, :269:{23,63}]
wire _isZero_S_T = io_a_isZero_0 | io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :270:64]
wire isZero_S = io_sqrtOp_0 ? io_a_isZero_0 : _isZero_S_T; // @[DivSqrtRecFN_small.scala:199:5, :270:{23,64}]
wire _sign_S_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33]
wire _sign_S_T_1 = _sign_S_T & io_b_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :271:{33,45}]
wire sign_S = io_a_sign_0 ^ _sign_S_T_1; // @[DivSqrtRecFN_small.scala:199:5, :271:{30,45}]
wire _specialCaseA_S_T = io_a_isNaN_0 | io_a_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :273:39]
wire specialCaseA_S = _specialCaseA_S_T | io_a_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :273:{39,55}]
wire _specialCaseB_S_T = io_b_isNaN_0 | io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :274:39]
wire specialCaseB_S = _specialCaseB_S_T | io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :274:{39,55}]
wire _normalCase_S_div_T = ~specialCaseA_S; // @[DivSqrtRecFN_small.scala:273:55, :275:28]
wire _normalCase_S_div_T_1 = ~specialCaseB_S; // @[DivSqrtRecFN_small.scala:274:55, :275:48]
wire normalCase_S_div = _normalCase_S_div_T & _normalCase_S_div_T_1; // @[DivSqrtRecFN_small.scala:275:{28,45,48}]
wire _normalCase_S_sqrt_T = ~specialCaseA_S; // @[DivSqrtRecFN_small.scala:273:55, :275:28, :276:29]
wire _normalCase_S_sqrt_T_1 = ~io_a_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :276:49]
wire normalCase_S_sqrt = _normalCase_S_sqrt_T & _normalCase_S_sqrt_T_1; // @[DivSqrtRecFN_small.scala:276:{29,46,49}]
wire normalCase_S = io_sqrtOp_0 ? normalCase_S_sqrt : normalCase_S_div; // @[DivSqrtRecFN_small.scala:199:5, :275:45, :276:46, :277:27]
wire _sExpQuot_S_div_T = io_b_sExp_0[11]; // @[DivSqrtRecFN_small.scala:199:5, :281:28]
wire [10:0] _sExpQuot_S_div_T_1 = io_b_sExp_0[10:0]; // @[DivSqrtRecFN_small.scala:199:5, :281:52]
wire [10:0] _sExpQuot_S_div_T_2 = ~_sExpQuot_S_div_T_1; // @[DivSqrtRecFN_small.scala:281:{40,52}]
wire [11:0] _sExpQuot_S_div_T_3 = {_sExpQuot_S_div_T, _sExpQuot_S_div_T_2}; // @[DivSqrtRecFN_small.scala:281:{16,28,40}]
wire [11:0] _sExpQuot_S_div_T_4 = _sExpQuot_S_div_T_3; // @[DivSqrtRecFN_small.scala:281:{16,71}]
wire [13:0] sExpQuot_S_div = {io_a_sExp_0[12], io_a_sExp_0} + {{2{_sExpQuot_S_div_T_4[11]}}, _sExpQuot_S_div_T_4}; // @[DivSqrtRecFN_small.scala:199:5, :280:21, :281:71]
wire _sSatExpQuot_S_div_T = $signed(sExpQuot_S_div) > 14'shDFF; // @[DivSqrtRecFN_small.scala:280:21, :284:48]
wire [3:0] _sSatExpQuot_S_div_T_1 = sExpQuot_S_div[12:9]; // @[DivSqrtRecFN_small.scala:280:21, :286:31]
wire [3:0] _sSatExpQuot_S_div_T_2 = _sSatExpQuot_S_div_T ? 4'h6 : _sSatExpQuot_S_div_T_1; // @[DivSqrtRecFN_small.scala:284:{16,48}, :286:31]
wire [8:0] _sSatExpQuot_S_div_T_3 = sExpQuot_S_div[8:0]; // @[DivSqrtRecFN_small.scala:280:21, :288:27]
wire [12:0] _sSatExpQuot_S_div_T_4 = {_sSatExpQuot_S_div_T_2, _sSatExpQuot_S_div_T_3}; // @[DivSqrtRecFN_small.scala:284:{12,16}, :288:27]
wire [12:0] sSatExpQuot_S_div = _sSatExpQuot_S_div_T_4; // @[DivSqrtRecFN_small.scala:284:12, :289:11]
wire _evenSqrt_S_T = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48]
wire _oddSqrt_S_T = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :292:48]
wire _inReady_T_4 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36]
wire _rawOutValid_T_4 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36]
wire _cycleNum_T_3 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36]
wire _fractB_Z_T_6 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :343:52]
wire _fractB_Z_T_11 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :344:54]
wire _evenSqrt_S_T_1 = ~_evenSqrt_S_T; // @[DivSqrtRecFN_small.scala:291:{35,48}]
wire evenSqrt_S = io_sqrtOp_0 & _evenSqrt_S_T_1; // @[DivSqrtRecFN_small.scala:199:5, :291:{32,35}]
wire oddSqrt_S = io_sqrtOp_0 & _oddSqrt_S_T; // @[DivSqrtRecFN_small.scala:199:5, :292:{32,48}]
wire idle = cycleNum == 6'h0; // @[DivSqrtRecFN_small.scala:224:33, :296:25]
wire entering = inReady & io_inValid_0; // @[DivSqrtRecFN_small.scala:199:5, :225:33, :297:28]
wire entering_normalCase = entering & normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :297:28, :298:40]
wire _processTwoBits_T = cycleNum > 6'h2; // @[DivSqrtRecFN_small.scala:224:33, :300:35]
wire _skipCycle2_T = cycleNum == 6'h3; // @[DivSqrtRecFN_small.scala:224:33, :301:31]
wire _skipCycle2_T_1 = sigX_Z[54]; // @[DivSqrtRecFN_small.scala:245:29, :301:48]
wire _skipCycle2_T_2 = _skipCycle2_T & _skipCycle2_T_1; // @[DivSqrtRecFN_small.scala:301:{31,39,48}]
wire skipCycle2 = _skipCycle2_T_2; // @[DivSqrtRecFN_small.scala:301:{39,63}]
wire _inReady_T_22 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16]
wire _rawOutValid_T_22 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16]
wire _cycleNum_T_16 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16]
wire _inReady_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28]
wire _inReady_T_1 = entering & _inReady_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}]
wire _inReady_T_3 = _inReady_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}]
wire _inReady_T_11 = _inReady_T_3; // @[DivSqrtRecFN_small.scala:305:{16,57}]
wire _inReady_T_12 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17]
wire _inReady_T_13 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31]
wire _inReady_T_14 = _inReady_T_12 & _inReady_T_13; // @[DivSqrtRecFN_small.scala:313:{17,28,31}]
wire [6:0] _GEN = {1'h0, cycleNum} - 7'h1; // @[DivSqrtRecFN_small.scala:224:33, :313:56]
wire [6:0] _inReady_T_16; // @[DivSqrtRecFN_small.scala:313:56]
assign _inReady_T_16 = _GEN; // @[DivSqrtRecFN_small.scala:313:56]
wire [6:0] _rawOutValid_T_16; // @[DivSqrtRecFN_small.scala:313:56]
assign _rawOutValid_T_16 = _GEN; // @[DivSqrtRecFN_small.scala:313:56]
wire [6:0] _cycleNum_T_12; // @[DivSqrtRecFN_small.scala:313:56]
assign _cycleNum_T_12 = _GEN; // @[DivSqrtRecFN_small.scala:313:56]
wire [5:0] _inReady_T_17 = _inReady_T_16[5:0]; // @[DivSqrtRecFN_small.scala:313:56]
wire _inReady_T_18 = _inReady_T_17 < 6'h2; // @[DivSqrtRecFN_small.scala:313:56, :317:38]
wire _inReady_T_19 = _inReady_T_14 & _inReady_T_18; // @[DivSqrtRecFN_small.scala:313:{16,28}, :317:38]
wire _inReady_T_20 = _inReady_T_11 | _inReady_T_19; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16]
wire _inReady_T_23 = _inReady_T_20 | _inReady_T_22; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16]
wire _inReady_T_24 = _inReady_T_23; // @[DivSqrtRecFN_small.scala:313:95, :317:46]
wire _rawOutValid_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28]
wire _rawOutValid_T_1 = entering & _rawOutValid_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}]
wire _rawOutValid_T_3 = _rawOutValid_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}]
wire _rawOutValid_T_11 = _rawOutValid_T_3; // @[DivSqrtRecFN_small.scala:305:{16,57}]
wire _rawOutValid_T_12 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17]
wire _rawOutValid_T_13 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31]
wire _rawOutValid_T_14 = _rawOutValid_T_12 & _rawOutValid_T_13; // @[DivSqrtRecFN_small.scala:313:{17,28,31}]
wire [5:0] _rawOutValid_T_17 = _rawOutValid_T_16[5:0]; // @[DivSqrtRecFN_small.scala:313:56]
wire _rawOutValid_T_18 = _rawOutValid_T_17 == 6'h1; // @[DivSqrtRecFN_small.scala:313:56, :318:42]
wire _rawOutValid_T_19 = _rawOutValid_T_14 & _rawOutValid_T_18; // @[DivSqrtRecFN_small.scala:313:{16,28}, :318:42]
wire _rawOutValid_T_20 = _rawOutValid_T_11 | _rawOutValid_T_19; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16]
wire _rawOutValid_T_23 = _rawOutValid_T_20 | _rawOutValid_T_22; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16]
wire _rawOutValid_T_24 = _rawOutValid_T_23; // @[DivSqrtRecFN_small.scala:313:95, :318:51]
wire _cycleNum_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28]
wire _cycleNum_T_1 = entering & _cycleNum_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}]
wire _cycleNum_T_2 = _cycleNum_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}]
wire [5:0] _cycleNum_T_4 = _cycleNum_T_3 ? 6'h35 : 6'h36; // @[DivSqrtRecFN_small.scala:308:{24,36}]
wire [5:0] _cycleNum_T_5 = io_sqrtOp_0 ? _cycleNum_T_4 : 6'h37; // @[DivSqrtRecFN_small.scala:199:5, :307:20, :308:24]
wire [5:0] _cycleNum_T_6 = entering_normalCase ? _cycleNum_T_5 : 6'h0; // @[DivSqrtRecFN_small.scala:298:40, :306:16, :307:20]
wire [5:0] _cycleNum_T_7 = {5'h0, _cycleNum_T_2} | _cycleNum_T_6; // @[DivSqrtRecFN_small.scala:305:{16,57}, :306:16, :313:56]
wire _cycleNum_T_8 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17]
wire _cycleNum_T_9 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31]
wire _cycleNum_T_10 = _cycleNum_T_8 & _cycleNum_T_9; // @[DivSqrtRecFN_small.scala:313:{17,28,31}]
wire [5:0] _cycleNum_T_13 = _cycleNum_T_12[5:0]; // @[DivSqrtRecFN_small.scala:313:56]
wire [5:0] _cycleNum_T_14 = _cycleNum_T_10 ? _cycleNum_T_13 : 6'h0; // @[DivSqrtRecFN_small.scala:313:{16,28,56}]
wire [5:0] _cycleNum_T_15 = _cycleNum_T_7 | _cycleNum_T_14; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16]
wire [5:0] _cycleNum_T_17 = {_cycleNum_T_15[5:1], _cycleNum_T_15[0] | _cycleNum_T_16}; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16]
wire [11:0] _sExp_Z_T = io_a_sExp_0[12:1]; // @[DivSqrtRecFN_small.scala:199:5, :335:29]
wire [12:0] _sExp_Z_T_1 = {_sExp_Z_T[11], _sExp_Z_T} + 13'h400; // @[DivSqrtRecFN_small.scala:335:{29,34}]
wire [12:0] _sExp_Z_T_2 = io_sqrtOp_0 ? _sExp_Z_T_1 : sSatExpQuot_S_div; // @[DivSqrtRecFN_small.scala:199:5, :289:11, :334:16, :335:34]
wire _fractB_Z_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :342:28]
wire _fractB_Z_T_1 = inReady & _fractB_Z_T; // @[DivSqrtRecFN_small.scala:225:33, :342:{25,28}]
wire [51:0] _fractB_Z_T_2 = io_b_sig_0[51:0]; // @[DivSqrtRecFN_small.scala:199:5, :342:73]
wire [52:0] _fractB_Z_T_3 = {_fractB_Z_T_2, 1'h0}; // @[DivSqrtRecFN_small.scala:342:{73,90}]
wire [52:0] _fractB_Z_T_4 = _fractB_Z_T_1 ? _fractB_Z_T_3 : 53'h0; // @[DivSqrtRecFN_small.scala:342:{16,25,90}]
wire _GEN_0 = inReady & io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :225:33, :343:25]
wire _fractB_Z_T_5; // @[DivSqrtRecFN_small.scala:343:25]
assign _fractB_Z_T_5 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25]
wire _fractB_Z_T_10; // @[DivSqrtRecFN_small.scala:344:25]
assign _fractB_Z_T_10 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25, :344:25]
wire _sigX_Z_T_4; // @[DivSqrtRecFN_small.scala:395:25]
assign _sigX_Z_T_4 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25, :395:25]
wire _fractB_Z_T_7 = _fractB_Z_T_5 & _fractB_Z_T_6; // @[DivSqrtRecFN_small.scala:343:{25,38,52}]
wire [51:0] _fractB_Z_T_8 = {_fractB_Z_T_7, 51'h0}; // @[DivSqrtRecFN_small.scala:343:{16,38}]
wire [52:0] _fractB_Z_T_9 = {_fractB_Z_T_4[52], _fractB_Z_T_4[51:0] | _fractB_Z_T_8}; // @[DivSqrtRecFN_small.scala:342:{16,100}, :343:16]
wire _fractB_Z_T_12 = ~_fractB_Z_T_11; // @[DivSqrtRecFN_small.scala:344:{41,54}]
wire _fractB_Z_T_13 = _fractB_Z_T_10 & _fractB_Z_T_12; // @[DivSqrtRecFN_small.scala:344:{25,38,41}]
wire [52:0] _fractB_Z_T_14 = {_fractB_Z_T_13, 52'h0}; // @[DivSqrtRecFN_small.scala:344:{16,38}]
wire [52:0] _fractB_Z_T_15 = _fractB_Z_T_9 | _fractB_Z_T_14; // @[DivSqrtRecFN_small.scala:342:100, :343:100, :344:16]
wire [52:0] _fractB_Z_T_20 = _fractB_Z_T_15; // @[DivSqrtRecFN_small.scala:343:100, :344:100]
wire _fractB_Z_T_16 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :345:17]
wire [50:0] _fractB_Z_T_18 = fractB_Z[52:2]; // @[DivSqrtRecFN_small.scala:236:29, :345:71]
wire _fractB_Z_T_21 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :346:17]
wire _fractB_Z_T_23 = _fractB_Z_T_21; // @[DivSqrtRecFN_small.scala:346:{17,42}]
wire [51:0] _fractB_Z_T_24 = fractB_Z[52:1]; // @[DivSqrtRecFN_small.scala:236:29, :346:71]
wire [51:0] _trialTerm2_newBit0_T = fractB_Z[52:1]; // @[DivSqrtRecFN_small.scala:236:29, :346:71, :373:52]
wire [51:0] _fractB_Z_T_25 = _fractB_Z_T_23 ? _fractB_Z_T_24 : 52'h0; // @[DivSqrtRecFN_small.scala:346:{16,42,71}]
wire [52:0] _fractB_Z_T_26 = {_fractB_Z_T_20[52], _fractB_Z_T_20[51:0] | _fractB_Z_T_25}; // @[DivSqrtRecFN_small.scala:344:100, :345:100, :346:16]
wire _rem_T = ~oddSqrt_S; // @[DivSqrtRecFN_small.scala:292:32, :352:24]
wire _rem_T_1 = inReady & _rem_T; // @[DivSqrtRecFN_small.scala:225:33, :352:{21,24}]
wire [54:0] _rem_T_2 = {io_a_sig_0, 1'h0}; // @[DivSqrtRecFN_small.scala:199:5, :352:47]
wire [54:0] _rem_T_3 = _rem_T_1 ? _rem_T_2 : 55'h0; // @[DivSqrtRecFN_small.scala:352:{12,21,47}]
wire _GEN_1 = inReady & oddSqrt_S; // @[DivSqrtRecFN_small.scala:225:33, :292:32, :353:21]
wire _rem_T_4; // @[DivSqrtRecFN_small.scala:353:21]
assign _rem_T_4 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21]
wire _trialTerm_T_7; // @[DivSqrtRecFN_small.scala:364:21]
assign _trialTerm_T_7 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21, :364:21]
wire _sigX_Z_T_7; // @[DivSqrtRecFN_small.scala:396:25]
assign _sigX_Z_T_7 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21, :396:25]
wire [1:0] _rem_T_5 = io_a_sig_0[52:51]; // @[DivSqrtRecFN_small.scala:199:5, :354:27]
wire [2:0] _rem_T_6 = {1'h0, _rem_T_5} - 3'h1; // @[DivSqrtRecFN_small.scala:354:{27,56}]
wire [1:0] _rem_T_7 = _rem_T_6[1:0]; // @[DivSqrtRecFN_small.scala:354:56]
wire [50:0] _rem_T_8 = io_a_sig_0[50:0]; // @[DivSqrtRecFN_small.scala:199:5, :355:27]
wire [53:0] _rem_T_9 = {_rem_T_8, 3'h0}; // @[DivSqrtRecFN_small.scala:355:{27,44}]
wire [55:0] _rem_T_10 = {_rem_T_7, _rem_T_9}; // @[DivSqrtRecFN_small.scala:354:{16,56}, :355:44]
wire [55:0] _rem_T_11 = _rem_T_4 ? _rem_T_10 : 56'h0; // @[DivSqrtRecFN_small.scala:353:{12,21}, :354:16]
wire [55:0] _rem_T_12 = {1'h0, _rem_T_3} | _rem_T_11; // @[DivSqrtRecFN_small.scala:352:{12,57}, :353:12]
wire _rem_T_13 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :359:13]
wire [55:0] _rem_T_14 = {rem_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:243:29, :359:29]
wire [55:0] _rem_T_15 = _rem_T_13 ? _rem_T_14 : 56'h0; // @[DivSqrtRecFN_small.scala:359:{12,13,29}]
wire [55:0] rem = _rem_T_12 | _rem_T_15; // @[DivSqrtRecFN_small.scala:352:57, :358:11, :359:12]
wire [63:0] _bitMask_T = 64'h1 << cycleNum; // @[DivSqrtRecFN_small.scala:224:33, :360:23]
wire [61:0] bitMask = _bitMask_T[63:2]; // @[DivSqrtRecFN_small.scala:360:{23,34}]
wire _trialTerm_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :362:24]
wire _trialTerm_T_1 = inReady & _trialTerm_T; // @[DivSqrtRecFN_small.scala:225:33, :362:{21,24}]
wire [54:0] _trialTerm_T_2 = {io_b_sig_0, 1'h0}; // @[DivSqrtRecFN_small.scala:199:5, :362:48]
wire [54:0] _trialTerm_T_3 = _trialTerm_T_1 ? _trialTerm_T_2 : 55'h0; // @[DivSqrtRecFN_small.scala:362:{12,21,48}]
wire _trialTerm_T_4 = inReady & evenSqrt_S; // @[DivSqrtRecFN_small.scala:225:33, :291:32, :363:21]
wire [53:0] _trialTerm_T_5 = {_trialTerm_T_4, 53'h0}; // @[DivSqrtRecFN_small.scala:363:{12,21}]
wire [54:0] _trialTerm_T_6 = {_trialTerm_T_3[54], _trialTerm_T_3[53:0] | _trialTerm_T_5}; // @[DivSqrtRecFN_small.scala:362:{12,74}, :363:12]
wire [54:0] _trialTerm_T_8 = _trialTerm_T_7 ? 55'h50000000000000 : 55'h0; // @[DivSqrtRecFN_small.scala:364:{12,21}]
wire [54:0] _trialTerm_T_9 = _trialTerm_T_6 | _trialTerm_T_8; // @[DivSqrtRecFN_small.scala:362:74, :363:74, :364:12]
wire _trialTerm_T_10 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :365:13]
wire [52:0] _trialTerm_T_11 = _trialTerm_T_10 ? fractB_Z : 53'h0; // @[DivSqrtRecFN_small.scala:236:29, :365:{12,13}]
wire [54:0] _trialTerm_T_12 = {_trialTerm_T_9[54:53], _trialTerm_T_9[52:0] | _trialTerm_T_11}; // @[DivSqrtRecFN_small.scala:363:74, :364:74, :365:12]
wire _trialTerm_T_13 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :366:13]
wire _trialTerm_T_14 = ~sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :366:26]
wire _trialTerm_T_15 = _trialTerm_T_13 & _trialTerm_T_14; // @[DivSqrtRecFN_small.scala:366:{13,23,26}]
wire [53:0] _trialTerm_T_17 = {_trialTerm_T_15, 53'h0}; // @[DivSqrtRecFN_small.scala:366:{12,23}]
wire [54:0] _trialTerm_T_18 = {_trialTerm_T_12[54], _trialTerm_T_12[53:0] | _trialTerm_T_17}; // @[DivSqrtRecFN_small.scala:364:74, :365:74, :366:12]
wire _trialTerm_T_19 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :367:13]
wire _trialTerm_T_20 = _trialTerm_T_19 & sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :367:{13,23}]
wire [55:0] _GEN_2 = {sigX_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:245:29, :367:44]
wire [55:0] _trialTerm_T_21; // @[DivSqrtRecFN_small.scala:367:44]
assign _trialTerm_T_21 = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44]
wire [55:0] _trialTerm2_newBit0_T_1; // @[DivSqrtRecFN_small.scala:373:64]
assign _trialTerm2_newBit0_T_1 = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44, :373:64]
wire [55:0] _io_rawOut_sig_T; // @[DivSqrtRecFN_small.scala:414:31]
assign _io_rawOut_sig_T = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44, :414:31]
wire [55:0] _trialTerm_T_22 = _trialTerm_T_20 ? _trialTerm_T_21 : 56'h0; // @[DivSqrtRecFN_small.scala:367:{12,23,44}]
wire [55:0] trialTerm = {1'h0, _trialTerm_T_18} | _trialTerm_T_22; // @[DivSqrtRecFN_small.scala:365:74, :366:74, :367:12]
wire [56:0] _trialRem_T = {1'h0, rem}; // @[DivSqrtRecFN_small.scala:358:11, :368:24]
wire [56:0] _trialRem_T_1 = {1'h0, trialTerm}; // @[DivSqrtRecFN_small.scala:366:74, :368:42]
wire [57:0] trialRem = {_trialRem_T[56], _trialRem_T} - {_trialRem_T_1[56], _trialRem_T_1}; // @[DivSqrtRecFN_small.scala:368:{24,29,42}]
wire [57:0] _nextRem_Z_T = trialRem; // @[DivSqrtRecFN_small.scala:368:29, :371:42]
wire newBit = $signed(trialRem) > -58'sh1; // @[DivSqrtRecFN_small.scala:368:29, :369:23]
wire [57:0] _nextRem_Z_T_1 = newBit ? _nextRem_Z_T : {2'h0, rem}; // @[DivSqrtRecFN_small.scala:354:56, :358:11, :369:23, :371:{24,42}]
wire [54:0] nextRem_Z = _nextRem_Z_T_1[54:0]; // @[DivSqrtRecFN_small.scala:371:{24,54}]
wire [54:0] _nextRem_Z_2_T_10 = nextRem_Z; // @[DivSqrtRecFN_small.scala:371:54, :388:12]
wire [55:0] rem2 = {nextRem_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:371:54, :372:25]
wire [55:0] _trialTerm2_newBit0_T_2 = {4'h0, _trialTerm2_newBit0_T} | _trialTerm2_newBit0_T_1; // @[DivSqrtRecFN_small.scala:300:35, :373:{52,56,64}]
wire [53:0] _trialTerm2_newBit0_T_4 = {1'h1, fractB_Z}; // @[DivSqrtRecFN_small.scala:236:29, :373:78]
wire [55:0] trialTerm2_newBit0 = sqrtOp_Z ? _trialTerm2_newBit0_T_2 : {2'h0, _trialTerm2_newBit0_T_4}; // @[DivSqrtRecFN_small.scala:228:29, :354:56, :373:{33,56,78}]
wire [53:0] _trialTerm2_newBit1_T = {fractB_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:236:29, :374:73]
wire [53:0] _trialTerm2_newBit1_T_1 = sqrtOp_Z ? _trialTerm2_newBit1_T : 54'h0; // @[DivSqrtRecFN_small.scala:228:29, :374:{54,73}]
wire [55:0] trialTerm2_newBit1 = {trialTerm2_newBit0[55:54], trialTerm2_newBit0[53:0] | _trialTerm2_newBit1_T_1}; // @[DivSqrtRecFN_small.scala:373:33, :374:{49,54}]
wire [58:0] _GEN_3 = {trialRem, 1'h0}; // @[DivSqrtRecFN_small.scala:368:29, :377:22]
wire [58:0] _trialRem2_T; // @[DivSqrtRecFN_small.scala:377:22]
assign _trialRem2_T = _GEN_3; // @[DivSqrtRecFN_small.scala:377:22]
wire [58:0] _nextNotZeroRem_Z_2_T_1; // @[DivSqrtRecFN_small.scala:382:53]
assign _nextNotZeroRem_Z_2_T_1 = _GEN_3; // @[DivSqrtRecFN_small.scala:377:22, :382:53]
wire [56:0] _GEN_4 = {1'h0, trialTerm2_newBit1}; // @[DivSqrtRecFN_small.scala:374:49, :377:48]
wire [56:0] _trialRem2_T_1; // @[DivSqrtRecFN_small.scala:377:48]
assign _trialRem2_T_1 = _GEN_4; // @[DivSqrtRecFN_small.scala:377:48]
wire [56:0] _nextNotZeroRem_Z_2_T_2; // @[DivSqrtRecFN_small.scala:382:79]
assign _nextNotZeroRem_Z_2_T_2 = _GEN_4; // @[DivSqrtRecFN_small.scala:377:48, :382:79]
wire [59:0] _trialRem2_T_2 = {_trialRem2_T[58], _trialRem2_T} - {{3{_trialRem2_T_1[56]}}, _trialRem2_T_1}; // @[DivSqrtRecFN_small.scala:377:{22,27,48}]
wire [58:0] _trialRem2_T_3 = _trialRem2_T_2[58:0]; // @[DivSqrtRecFN_small.scala:377:27]
wire [58:0] _trialRem2_T_4 = _trialRem2_T_3; // @[DivSqrtRecFN_small.scala:377:27]
wire [56:0] _GEN_5 = {rem_Z, 2'h0}; // @[DivSqrtRecFN_small.scala:243:29, :354:56, :378:19]
wire [56:0] _trialRem2_T_5; // @[DivSqrtRecFN_small.scala:378:19]
assign _trialRem2_T_5 = _GEN_5; // @[DivSqrtRecFN_small.scala:378:19]
wire [56:0] _nextNotZeroRem_Z_2_T_10; // @[DivSqrtRecFN_small.scala:383:51]
assign _nextNotZeroRem_Z_2_T_10 = _GEN_5; // @[DivSqrtRecFN_small.scala:378:19, :383:51]
wire [55:0] _trialRem2_T_6 = _trialRem2_T_5[55:0]; // @[DivSqrtRecFN_small.scala:378:{19,23}]
wire [56:0] _trialRem2_T_7 = {1'h0, _trialRem2_T_6}; // @[DivSqrtRecFN_small.scala:378:{23,39}]
wire [56:0] _GEN_6 = {1'h0, trialTerm2_newBit0}; // @[DivSqrtRecFN_small.scala:373:33, :378:65]
wire [56:0] _trialRem2_T_8; // @[DivSqrtRecFN_small.scala:378:65]
assign _trialRem2_T_8 = _GEN_6; // @[DivSqrtRecFN_small.scala:378:65]
wire [56:0] _nextNotZeroRem_Z_2_T_13; // @[DivSqrtRecFN_small.scala:383:97]
assign _nextNotZeroRem_Z_2_T_13 = _GEN_6; // @[DivSqrtRecFN_small.scala:378:65, :383:97]
wire [57:0] _trialRem2_T_9 = {_trialRem2_T_7[56], _trialRem2_T_7} - {_trialRem2_T_8[56], _trialRem2_T_8}; // @[DivSqrtRecFN_small.scala:378:{39,44,65}]
wire [56:0] _trialRem2_T_10 = _trialRem2_T_9[56:0]; // @[DivSqrtRecFN_small.scala:378:44]
wire [56:0] _trialRem2_T_11 = _trialRem2_T_10; // @[DivSqrtRecFN_small.scala:378:44]
wire [58:0] trialRem2 = newBit ? _trialRem2_T_4 : {{2{_trialRem2_T_11[56]}}, _trialRem2_T_11}; // @[DivSqrtRecFN_small.scala:369:23, :376:12, :377:27, :378:44]
wire [58:0] _nextRem_Z_2_T_1 = trialRem2; // @[DivSqrtRecFN_small.scala:376:12, :386:51]
wire newBit2 = $signed(trialRem2) > -59'sh1; // @[DivSqrtRecFN_small.scala:376:12, :379:24]
wire _nextNotZeroRem_Z_T = inReady | newBit; // @[DivSqrtRecFN_small.scala:225:33, :369:23, :380:40]
wire _nextNotZeroRem_Z_T_1 = |trialRem; // @[DivSqrtRecFN_small.scala:368:29, :380:60]
wire nextNotZeroRem_Z = _nextNotZeroRem_Z_T ? _nextNotZeroRem_Z_T_1 : notZeroRem_Z; // @[DivSqrtRecFN_small.scala:244:29, :380:{31,40,60}]
wire _nextNotZeroRem_Z_2_T_22 = nextNotZeroRem_Z; // @[DivSqrtRecFN_small.scala:380:31, :384:38]
wire [59:0] _nextNotZeroRem_Z_2_T_3 = {_nextNotZeroRem_Z_2_T_1[58], _nextNotZeroRem_Z_2_T_1} - {{3{_nextNotZeroRem_Z_2_T_2[56]}}, _nextNotZeroRem_Z_2_T_2}; // @[DivSqrtRecFN_small.scala:382:{53,58,79}]
wire [58:0] _nextNotZeroRem_Z_2_T_4 = _nextNotZeroRem_Z_2_T_3[58:0]; // @[DivSqrtRecFN_small.scala:382:58]
wire [58:0] _nextNotZeroRem_Z_2_T_5 = _nextNotZeroRem_Z_2_T_4; // @[DivSqrtRecFN_small.scala:382:58]
wire _nextNotZeroRem_Z_2_T_6 = $signed(_nextNotZeroRem_Z_2_T_5) > 59'sh0; // @[DivSqrtRecFN_small.scala:382:{42,58}]
wire _nextNotZeroRem_Z_2_T_8 = ~newBit; // @[DivSqrtRecFN_small.scala:369:23, :383:27]
wire [55:0] _nextNotZeroRem_Z_2_T_11 = _nextNotZeroRem_Z_2_T_10[55:0]; // @[DivSqrtRecFN_small.scala:383:{51,55}]
wire [56:0] _nextNotZeroRem_Z_2_T_12 = {1'h0, _nextNotZeroRem_Z_2_T_11}; // @[DivSqrtRecFN_small.scala:383:{55,71}]
wire [57:0] _nextNotZeroRem_Z_2_T_14 = {_nextNotZeroRem_Z_2_T_12[56], _nextNotZeroRem_Z_2_T_12} - {_nextNotZeroRem_Z_2_T_13[56], _nextNotZeroRem_Z_2_T_13}; // @[DivSqrtRecFN_small.scala:383:{71,76,97}]
wire [56:0] _nextNotZeroRem_Z_2_T_15 = _nextNotZeroRem_Z_2_T_14[56:0]; // @[DivSqrtRecFN_small.scala:383:76]
wire [56:0] _nextNotZeroRem_Z_2_T_16 = _nextNotZeroRem_Z_2_T_15; // @[DivSqrtRecFN_small.scala:383:76]
wire _nextNotZeroRem_Z_2_T_17 = $signed(_nextNotZeroRem_Z_2_T_16) > 57'sh0; // @[DivSqrtRecFN_small.scala:383:{43,76}]
wire nextNotZeroRem_Z_2 = _nextNotZeroRem_Z_2_T_22; // @[DivSqrtRecFN_small.scala:383:103, :384:38]
wire [54:0] _nextRem_Z_2_T_2 = _nextRem_Z_2_T_1[54:0]; // @[DivSqrtRecFN_small.scala:386:{51,57}]
wire _nextRem_Z_2_T_4 = ~newBit2; // @[DivSqrtRecFN_small.scala:379:24, :387:31]
wire [54:0] _nextRem_Z_2_T_6 = rem2[54:0]; // @[DivSqrtRecFN_small.scala:372:25, :387:45]
wire [54:0] nextRem_Z_2 = _nextRem_Z_2_T_10; // @[DivSqrtRecFN_small.scala:387:83, :388:12]
wire _sigX_Z_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :394:28]
wire _sigX_Z_T_1 = inReady & _sigX_Z_T; // @[DivSqrtRecFN_small.scala:225:33, :394:{25,28}]
wire [54:0] _sigX_Z_T_2 = {newBit, 54'h0}; // @[DivSqrtRecFN_small.scala:369:23, :394:50]
wire [54:0] _sigX_Z_T_3 = _sigX_Z_T_1 ? _sigX_Z_T_2 : 55'h0; // @[DivSqrtRecFN_small.scala:394:{16,25,50}]
wire [53:0] _sigX_Z_T_5 = {_sigX_Z_T_4, 53'h0}; // @[DivSqrtRecFN_small.scala:395:{16,25}]
wire [54:0] _sigX_Z_T_6 = {_sigX_Z_T_3[54], _sigX_Z_T_3[53:0] | _sigX_Z_T_5}; // @[DivSqrtRecFN_small.scala:394:{16,74}, :395:16]
wire [52:0] _sigX_Z_T_8 = {newBit, 52'h0}; // @[DivSqrtRecFN_small.scala:369:23, :396:50]
wire [52:0] _sigX_Z_T_9 = _sigX_Z_T_7 ? _sigX_Z_T_8 : 53'h0; // @[DivSqrtRecFN_small.scala:396:{16,25,50}]
wire [54:0] _sigX_Z_T_10 = {_sigX_Z_T_6[54:53], _sigX_Z_T_6[52:0] | _sigX_Z_T_9}; // @[DivSqrtRecFN_small.scala:394:74, :395:74, :396:16]
wire _sigX_Z_T_11 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :397:17]
wire [54:0] _sigX_Z_T_12 = _sigX_Z_T_11 ? sigX_Z : 55'h0; // @[DivSqrtRecFN_small.scala:245:29, :397:{16,17}]
wire [54:0] _sigX_Z_T_13 = _sigX_Z_T_10 | _sigX_Z_T_12; // @[DivSqrtRecFN_small.scala:395:74, :396:74, :397:16]
wire _sigX_Z_T_14 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :398:17]
wire _sigX_Z_T_15 = _sigX_Z_T_14 & newBit; // @[DivSqrtRecFN_small.scala:369:23, :398:{17,27}]
wire [61:0] _sigX_Z_T_16 = _sigX_Z_T_15 ? bitMask : 62'h0; // @[DivSqrtRecFN_small.scala:360:34, :398:{16,27}]
wire [61:0] _sigX_Z_T_17 = {7'h0, _sigX_Z_T_13} | _sigX_Z_T_16; // @[DivSqrtRecFN_small.scala:396:74, :397:74, :398:16]
wire [61:0] _sigX_Z_T_21 = _sigX_Z_T_17; // @[DivSqrtRecFN_small.scala:397:74, :398:74]
wire [60:0] _sigX_Z_T_19 = bitMask[61:1]; // @[DivSqrtRecFN_small.scala:360:34, :399:51]
wire _io_rawOutValid_div_T = ~sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :366:26, :404:43]
assign _io_rawOutValid_div_T_1 = rawOutValid & _io_rawOutValid_div_T; // @[DivSqrtRecFN_small.scala:226:33, :404:{40,43}]
assign io_rawOutValid_div_0 = _io_rawOutValid_div_T_1; // @[DivSqrtRecFN_small.scala:199:5, :404:40]
assign _io_rawOutValid_sqrt_T = rawOutValid & sqrtOp_Z; // @[DivSqrtRecFN_small.scala:226:33, :228:29, :405:40]
assign io_rawOutValid_sqrt_0 = _io_rawOutValid_sqrt_T; // @[DivSqrtRecFN_small.scala:199:5, :405:40]
assign _io_invalidExc_T = majorExc_Z & isNaN_Z; // @[DivSqrtRecFN_small.scala:229:29, :231:29, :407:36]
assign io_invalidExc_0 = _io_invalidExc_T; // @[DivSqrtRecFN_small.scala:199:5, :407:36]
wire _io_infiniteExc_T = ~isNaN_Z; // @[DivSqrtRecFN_small.scala:231:29, :408:39]
assign _io_infiniteExc_T_1 = majorExc_Z & _io_infiniteExc_T; // @[DivSqrtRecFN_small.scala:229:29, :408:{36,39}]
assign io_infiniteExc_0 = _io_infiniteExc_T_1; // @[DivSqrtRecFN_small.scala:199:5, :408:36]
assign _io_rawOut_sig_T_1 = {_io_rawOut_sig_T[55:1], _io_rawOut_sig_T[0] | notZeroRem_Z}; // @[DivSqrtRecFN_small.scala:244:29, :414:{31,35}]
assign io_rawOut_sig_0 = _io_rawOut_sig_T_1; // @[DivSqrtRecFN_small.scala:199:5, :414:35]
always @(posedge clock) begin // @[DivSqrtRecFN_small.scala:199:5]
if (reset) begin // @[DivSqrtRecFN_small.scala:199:5]
cycleNum <= 6'h0; // @[DivSqrtRecFN_small.scala:224:33]
inReady <= 1'h1; // @[DivSqrtRecFN_small.scala:225:33]
rawOutValid <= 1'h0; // @[DivSqrtRecFN_small.scala:226:33]
end
else if (~idle | entering) begin // @[DivSqrtRecFN_small.scala:296:25, :297:28, :303:{11,18}]
cycleNum <= _cycleNum_T_17; // @[DivSqrtRecFN_small.scala:224:33, :313:95]
inReady <= _inReady_T_24; // @[DivSqrtRecFN_small.scala:225:33, :317:46]
rawOutValid <= _rawOutValid_T_24; // @[DivSqrtRecFN_small.scala:226:33, :318:51]
end
if (entering) begin // @[DivSqrtRecFN_small.scala:297:28]
sqrtOp_Z <= io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :228:29]
majorExc_Z <= majorExc_S; // @[DivSqrtRecFN_small.scala:229:29, :258:12]
isNaN_Z <= isNaN_S; // @[DivSqrtRecFN_small.scala:231:29, :265:12]
isInf_Z <= isInf_S; // @[DivSqrtRecFN_small.scala:232:29, :269:23]
isZero_Z <= isZero_S; // @[DivSqrtRecFN_small.scala:233:29, :270:23]
sign_Z <= sign_S; // @[DivSqrtRecFN_small.scala:234:29, :271:30]
sExp_Z <= _sExp_Z_T_2; // @[DivSqrtRecFN_small.scala:235:29, :334:16]
roundingMode_Z <= io_roundingMode_0; // @[DivSqrtRecFN_small.scala:199:5, :237:29]
end
if (entering | ~inReady & sqrtOp_Z) // @[DivSqrtRecFN_small.scala:225:33, :228:29, :297:28, :340:{20,23,33}]
fractB_Z <= _fractB_Z_T_26; // @[DivSqrtRecFN_small.scala:236:29, :345:100]
if (entering | ~inReady) begin // @[DivSqrtRecFN_small.scala:225:33, :297:28, :340:23, :390:20]
rem_Z <= nextRem_Z_2; // @[DivSqrtRecFN_small.scala:243:29, :387:83]
notZeroRem_Z <= nextNotZeroRem_Z_2; // @[DivSqrtRecFN_small.scala:244:29, :383:103]
sigX_Z <= _sigX_Z_T_21[54:0]; // @[DivSqrtRecFN_small.scala:245:29, :393:16, :398:74]
end
always @(posedge)
assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:199:5]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File Nodes.scala:
package constellation.channel
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.diplomacy._
case class EmptyParams()
case class ChannelEdgeParams(cp: ChannelParams, p: Parameters)
object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] {
def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
ChannelEdgeParams(pu, p)
}
def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p)
def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString)
}
override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = {
val monitor = Module(new NoCMonitor(edge.cp)(edge.p))
monitor.io.in := bundle
}
// TODO: Add nodepath stuff? override def mixO, override def mixI
}
case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams()))
case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams))
case class ChannelAdapterNode(
slaveFn: ChannelParams => ChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn)
case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)()
case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)()
case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters)
case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters)
object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] {
def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
IngressChannelEdgeParams(pu, p)
}
def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p)
def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString)
}
}
object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] {
def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
EgressChannelEdgeParams(pu, p)
}
def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p)
def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString)
}
}
case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams()))
case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams))
case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams()))
case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams))
case class IngressChannelAdapterNode(
slaveFn: IngressChannelParams => IngressChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn)
case class EgressChannelAdapterNode(
slaveFn: EgressChannelParams => EgressChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn)
case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)()
case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)()
case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)()
case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)()
File Router.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{RoutingRelation}
import constellation.noc.{HasNoCParams}
case class UserRouterParams(
// Payload width. Must match payload width on all channels attached to this routing node
payloadBits: Int = 64,
// Combines SA and ST stages (removes pipeline register)
combineSAST: Boolean = false,
// Combines RC and VA stages (removes pipeline register)
combineRCVA: Boolean = false,
// Adds combinational path from SA to VA
coupleSAVA: Boolean = false,
vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p)
)
case class RouterParams(
nodeId: Int,
nIngress: Int,
nEgress: Int,
user: UserRouterParams
)
trait HasRouterOutputParams {
def outParams: Seq[ChannelParams]
def egressParams: Seq[EgressChannelParams]
def allOutParams = outParams ++ egressParams
def nOutputs = outParams.size
def nEgress = egressParams.size
def nAllOutputs = allOutParams.size
}
trait HasRouterInputParams {
def inParams: Seq[ChannelParams]
def ingressParams: Seq[IngressChannelParams]
def allInParams = inParams ++ ingressParams
def nInputs = inParams.size
def nIngress = ingressParams.size
def nAllInputs = allInParams.size
}
trait HasRouterParams
{
def routerParams: RouterParams
def nodeId = routerParams.nodeId
def payloadBits = routerParams.user.payloadBits
}
class DebugBundle(val nIn: Int) extends Bundle {
val va_stall = Vec(nIn, UInt())
val sa_stall = Vec(nIn, UInt())
}
class Router(
val routerParams: RouterParams,
preDiplomaticInParams: Seq[ChannelParams],
preDiplomaticIngressParams: Seq[IngressChannelParams],
outDests: Seq[Int],
egressIds: Seq[Int]
)(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams {
val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams
val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u))
val sourceNodes = outDests.map(u => ChannelSourceNode(u))
val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u))
val egressNodes = egressIds.map(u => EgressChannelSourceNode(u))
val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size))
val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None
def inParams = module.inParams
def outParams = module.outParams
def ingressParams = module.ingressParams
def egressParams = module.egressParams
lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams {
val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip
val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip
val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip
val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip
val io_debug = debugNode.out(0)._1
val inParams = edgesIn.map(_.cp)
val outParams = edgesOut.map(_.cp)
val ingressParams = edgesIngress.map(_.cp)
val egressParams = edgesEgress.map(_.cp)
allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits))
allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits))
require(nIngress == routerParams.nIngress)
require(nEgress == routerParams.nEgress)
require(nAllInputs >= 1)
require(nAllOutputs >= 1)
require(nodeId < (1 << nodeIdBits))
val input_units = inParams.zipWithIndex.map { case (u,i) =>
Module(new InputUnit(u, outParams, egressParams,
routerParams.user.combineRCVA, routerParams.user.combineSAST))
.suggestName(s"input_unit_${i}_from_${u.srcId}") }
val ingress_units = ingressParams.zipWithIndex.map { case (u,i) =>
Module(new IngressUnit(i, u, outParams, egressParams,
routerParams.user.combineRCVA, routerParams.user.combineSAST))
.suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") }
val all_input_units = input_units ++ ingress_units
val output_units = outParams.zipWithIndex.map { case (u,i) =>
Module(new OutputUnit(inParams, ingressParams, u))
.suggestName(s"output_unit_${i}_to_${u.destId}")}
val egress_units = egressParams.zipWithIndex.map { case (u,i) =>
Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1,
routerParams.user.combineSAST,
inParams, ingressParams, u))
.suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")}
val all_output_units = output_units ++ egress_units
val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams))
val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams))
val vc_allocator = Module(routerParams.user.vcAllocator(
VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams)
)(p))
val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams))
val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire)))
dontTouch(fires_count)
(io_in zip input_units ).foreach { case (i,u) => u.io.in <> i }
(io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit }
(output_units zip io_out ).foreach { case (u,o) => o <> u.io.out }
(egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out }
(route_computer.io.req zip all_input_units).foreach {
case (i,u) => i <> u.io.router_req }
(all_input_units zip route_computer.io.resp).foreach {
case (u,o) => u.io.router_resp <> o }
(vc_allocator.io.req zip all_input_units).foreach {
case (i,u) => i <> u.io.vcalloc_req }
(all_input_units zip vc_allocator.io.resp).foreach {
case (u,o) => u.io.vcalloc_resp <> o }
(all_output_units zip vc_allocator.io.out_allocs).foreach {
case (u,a) => u.io.allocs <> a }
(vc_allocator.io.channel_status zip all_output_units).foreach {
case (a,u) => a := u.io.channel_status }
all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) =>
in.io.out_credit_available(outIdx) := out.io.credit_available
})
(all_input_units zip switch_allocator.io.req).foreach {
case (u,r) => r <> u.io.salloc_req }
(all_output_units zip switch_allocator.io.credit_alloc).foreach {
case (u,a) => u.io.credit_alloc := a }
(switch.io.in zip all_input_units).foreach {
case (i,u) => i <> u.io.out }
(all_output_units zip switch.io.out).foreach {
case (u,o) => u.io.in <> o }
switch.io.sel := (if (routerParams.user.combineSAST) {
switch_allocator.io.switch_sel
} else {
RegNext(switch_allocator.io.switch_sel)
})
if (hasCtrl) {
val io_ctrl = ctrlNode.get.out(0)._1
val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams))
io_ctrl <> ctrl.io.ctrl
(all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r }
(all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) }
} else {
input_units.foreach(_.io.block := false.B)
ingress_units.foreach(_.io.block := false.B)
}
(io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r }
(io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r }
val debug_tsc = RegInit(0.U(64.W))
debug_tsc := debug_tsc + 1.U
val debug_sample = RegInit(0.U(64.W))
debug_sample := debug_sample + 1.U
val sample_rate = PlusArg("noc_util_sample_rate", width=20)
when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U }
def sample(fire: Bool, s: String) = {
val util_ctr = RegInit(0.U(64.W))
val fired = RegInit(false.B)
util_ctr := util_ctr + fire
fired := fired || fire
when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) {
val fmtStr = s"nocsample %d $s %d\n"
printf(fmtStr, debug_tsc, util_ctr);
fired := fire
}
}
destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f =>
sample(f.fire, s"${edge.cp.srcId} $nodeId")
} }
ingressNodes.map(_.in(0)).foreach { case (in, edge) =>
sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId")
}
egressNodes.map(_.out(0)).foreach { case (out, edge) =>
sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}")
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
|
module Router_2( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_2_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_ingress_nodes_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_io_out_2_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _egress_unit_2_to_5_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_2_to_5_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_2_to_5_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_1_to_4_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_1_to_4_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_1_to_4_io_out_valid; // @[Router.scala:125:13]
wire _output_unit_0_to_18_io_credit_available_0; // @[Router.scala:122:13]
wire _output_unit_0_to_18_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_0_to_18_io_credit_available_2; // @[Router.scala:122:13]
wire _output_unit_0_to_18_io_credit_available_3; // @[Router.scala:122:13]
wire _output_unit_0_to_18_io_credit_available_4; // @[Router.scala:122:13]
wire _output_unit_0_to_18_io_credit_available_5; // @[Router.scala:122:13]
wire _output_unit_0_to_18_io_credit_available_6; // @[Router.scala:122:13]
wire _output_unit_0_to_18_io_credit_available_7; // @[Router.scala:122:13]
wire _output_unit_0_to_18_io_channel_status_0_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_18_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_18_io_channel_status_2_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_18_io_channel_status_3_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_18_io_channel_status_4_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_18_io_channel_status_5_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_18_io_channel_status_6_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_18_io_channel_status_7_occupied; // @[Router.scala:122:13]
wire _ingress_unit_3_from_8_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_3_from_8_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_3_from_8_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [4:0] _ingress_unit_3_from_8_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_3_from_8_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [4:0] _ingress_unit_3_from_8_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_3_from_8_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_3_from_8_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_3_from_8_io_in_ready; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_2_from_7_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_7_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [4:0] _ingress_unit_2_from_7_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_2_from_7_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [4:0] _ingress_unit_2_from_7_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_2_from_7_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_7_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_2_from_7_io_in_ready; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_1_from_6_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_1_from_6_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [4:0] _ingress_unit_1_from_6_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_1_from_6_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [4:0] _ingress_unit_1_from_6_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_1_from_6_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_1_from_6_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_1_from_6_io_in_ready; // @[Router.scala:116:13]
wire _input_unit_0_from_18_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_18_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_18_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_18_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_18_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_18_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_18_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_18_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_18_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_18_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_0_from_18_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_18_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_18_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_18_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_18_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_18_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_18_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_6_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_7_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _ingress_unit_3_from_8_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35]
reg REG_2_0_3_0; // @[Router.scala:178:14]
reg REG_2_0_2_0; // @[Router.scala:178:14]
reg REG_2_0_1_0; // @[Router.scala:178:14]
reg REG_2_0_0_0; // @[Router.scala:178:14]
reg REG_1_0_3_0; // @[Router.scala:178:14]
reg REG_1_0_2_0; // @[Router.scala:178:14]
reg REG_1_0_1_0; // @[Router.scala:178:14]
reg REG_1_0_0_0; // @[Router.scala:178:14]
reg REG_0_0_3_0; // @[Router.scala:178:14]
reg REG_0_0_2_0; // @[Router.scala:178:14]
reg REG_0_0_1_0; // @[Router.scala:178:14]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_3; // @[Router.scala:203:29]
reg fired_3; // @[Router.scala:204:26]
wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_4; // @[Router.scala:203:29]
reg fired_4; // @[Router.scala:204:26]
wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_5; // @[Router.scala:203:29]
reg fired_5; // @[Router.scala:204:26]
wire _GEN_6 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}]
|
Generate the Verilog code corresponding to the following Chisel files.
File tage.scala:
package boom.v4.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v4.common._
import boom.v4.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int, val singlePorted: Boolean)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f2_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val us = SyncReadMem(nRows, Vec(bankWidth*2, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
us.suggestName(s"tage_u_${histLength}")
table.suggestName(s"tage_table_${histLength}")
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = Wire(Vec(bankWidth, new TageEntry))
val s2_req_rus = Wire(Vec(bankWidth*2, Bool()))
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f2_resp(w).valid := s2_req_rhits(w)
io.f2_resp(w).bits.u := Cat(s2_req_rus(w*2+1), s2_req_rus(w*2))
io.f2_resp(w).bits.ctr := s2_req_rtage(w).ctr
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val clear_u_hi = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val clear_u_lo = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val clear_u_mask = VecInit((0 until bankWidth*2) map { i => if (i % 2 == 0) clear_u_lo else clear_u_hi }).asUInt
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
val wen = WireInit(doing_reset || io.update_mask.reduce(_||_))
val rdata = if (singlePorted) table.read(s1_hashed_idx, !wen && io.f1_req_valid) else table.read(s1_hashed_idx, io.f1_req_valid)
when (RegNext(wen) && singlePorted.B) {
s2_req_rtage := 0.U.asTypeOf(Vec(bankWidth, new TageEntry))
} .otherwise {
s2_req_rtage := VecInit(rdata.map(_.asTypeOf(new TageEntry)))
}
when (wen) {
val widx = Mux(doing_reset, reset_idx, update_idx)
val wdata = Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt)))
val wmask = Mux(doing_reset, ~(0.U(bankWidth.W)), io.update_mask.asUInt)
table.write(widx, wdata, wmask.asBools)
}
val update_u_mask = VecInit((0 until bankWidth*2) map {i => io.update_u_mask(i / 2)})
val update_u_wen = WireInit(doing_reset || doing_clear_u || update_u_mask.reduce(_||_))
val u_rdata = if (singlePorted) {
us.read(s1_hashed_idx, !update_u_wen && io.f1_req_valid)
} else {
us.read(s1_hashed_idx, io.f1_req_valid)
}
s2_req_rus := u_rdata
when (update_u_wen) {
val widx = Mux(doing_reset, reset_idx, Mux(doing_clear_u, clear_u_idx, update_idx))
val wdata = Mux(doing_reset || doing_clear_u, VecInit(0.U((bankWidth*2).W).asBools), VecInit(io.update_u.asUInt.asBools))
val wmask = Mux(doing_reset, ~(0.U((bankWidth*2).W)), Mux(doing_clear_u, clear_u_mask, update_u_mask.asUInt))
us.write(widx, wdata, wmask.asBools)
}
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048,
singlePorted: Boolean = false
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod, params.singlePorted))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(bankAlign(io.f0_pc))
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f2_resps = VecInit(tables.map(_.io.f2_resp))
val f3_resps = RegNext(f2_resps)
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var s2_provided = false.B
var s2_provider = 0.U
var s2_alt_provided = false.B
var s2_alt_provider = 0.U
for (i <- 0 until tageNTables) {
val hit = f2_resps(i)(w).valid
s2_alt_provided = s2_alt_provided || (s2_provided && hit)
s2_provided = s2_provided || hit
s2_alt_provider = Mux(hit, s2_provider, s2_alt_provider)
s2_provider = Mux(hit, i.U, s2_provider)
}
val s3_provided = RegNext(s2_provided)
val s3_provider = RegNext(s2_provider)
val s3_alt_provided = RegNext(s2_alt_provided)
val s3_alt_provider = RegNext(s2_alt_provider)
val prov = RegNext(f2_resps(s2_provider)(w).bits)
val alt = RegNext(f2_resps(s2_alt_provider)(w).bits)
io.resp.f3(w).taken := Mux(s3_provided,
Mux(prov.ctr === 3.U || prov.ctr === 4.U,
Mux(s3_alt_provided, alt.ctr(2), io.resp_in(0).f3(w).taken),
prov.ctr(2)),
io.resp_in(0).f3(w).taken
)
f3_meta.provider(w).valid := s3_provided
f3_meta.provider(w).bits := s3_provider
f3_meta.alt_differs(w) := s3_alt_provided && alt.ctr(2) =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := prov.u
f3_meta.provider_ctr(w) := prov.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(f3_meta.provider(w).bits)) & Fill(tageNTables, f3_meta.provider(w).valid))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
}
|
module tage_table_32_0( // @[tage.scala:90:27]
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [51:0] R0_data,
input [6:0] W0_addr,
input W0_en,
input W0_clk,
input [51:0] W0_data,
input [3:0] W0_mask
);
tage_table_32_ext tage_table_32_ext ( // @[tage.scala:90:27]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
); // @[tage.scala:90:27]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Switch.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel.{ChannelParams, IngressChannelParams, EgressChannelParams, Flit}
class SwitchBundle(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle with HasRouterOutputParams{
val flit = new Flit(allOutParams(0).payloadBits)
val out_virt_channel = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W)
}
class Switch(
val routerParams: RouterParams,
val inParams: Seq[ChannelParams],
val outParams: Seq[ChannelParams],
val ingressParams: Seq[IngressChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module
with HasRouterParams
with HasRouterInputParams
with HasRouterOutputParams {
val io = IO(new Bundle {
val in = MixedVec(allInParams.map { u => Vec(u.destSpeedup,
Input(Valid(new SwitchBundle(outParams, egressParams)))) })
val out = MixedVec(allOutParams.map { u => Vec(u.srcSpeedup,
Output(Valid(new Flit(u.payloadBits)))) })
val sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup,
MixedVec(allInParams.map { i => Vec(i.destSpeedup, Input(Bool())) })) })
})
val in_flat = Wire(Vec(allInParams.map(_.destSpeedup).reduce(_+_),
Valid(new SwitchBundle(outParams, egressParams))))
var idx = 0
io.in.foreach(_.foreach { i =>
in_flat(idx) := i
idx += 1
})
for (i <- 0 until nAllOutputs) {
for (j <- 0 until allOutParams(i).srcSpeedup) {
val sel_flat = io.sel(i)(j).asUInt
assert(PopCount(sel_flat) <= 1.U)
io.out(i)(j).valid := Mux1H(sel_flat, in_flat.map(_.valid)) && sel_flat =/= 0.U
io.out(i)(j).bits := Mux1H(sel_flat, in_flat.map(_.bits.flit))
io.out(i)(j).bits.virt_channel_id := Mux1H(sel_flat, in_flat.map(_.bits.out_virt_channel))
}
}
}
|
module Switch_28( // @[Switch.scala:16:7]
input clock, // @[Switch.scala:16:7]
input reset, // @[Switch.scala:16:7]
input io_in_1_0_valid, // @[Switch.scala:27:14]
input io_in_1_0_bits_flit_head, // @[Switch.scala:27:14]
input io_in_1_0_bits_flit_tail, // @[Switch.scala:27:14]
input [72:0] io_in_1_0_bits_flit_payload, // @[Switch.scala:27:14]
input [2:0] io_in_1_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14]
input [4:0] io_in_1_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14]
input [1:0] io_in_1_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14]
input [4:0] io_in_1_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14]
input [1:0] io_in_1_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14]
input [2:0] io_in_1_0_bits_out_virt_channel, // @[Switch.scala:27:14]
input io_in_0_0_valid, // @[Switch.scala:27:14]
input io_in_0_0_bits_flit_head, // @[Switch.scala:27:14]
input io_in_0_0_bits_flit_tail, // @[Switch.scala:27:14]
input [72:0] io_in_0_0_bits_flit_payload, // @[Switch.scala:27:14]
input [2:0] io_in_0_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14]
input [4:0] io_in_0_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14]
input [1:0] io_in_0_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14]
input [4:0] io_in_0_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14]
input [1:0] io_in_0_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14]
input [2:0] io_in_0_0_bits_out_virt_channel, // @[Switch.scala:27:14]
output io_out_1_0_valid, // @[Switch.scala:27:14]
output io_out_1_0_bits_head, // @[Switch.scala:27:14]
output io_out_1_0_bits_tail, // @[Switch.scala:27:14]
output [72:0] io_out_1_0_bits_payload, // @[Switch.scala:27:14]
output [2:0] io_out_1_0_bits_flow_vnet_id, // @[Switch.scala:27:14]
output [4:0] io_out_1_0_bits_flow_ingress_node, // @[Switch.scala:27:14]
output [1:0] io_out_1_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14]
output [4:0] io_out_1_0_bits_flow_egress_node, // @[Switch.scala:27:14]
output [1:0] io_out_1_0_bits_flow_egress_node_id, // @[Switch.scala:27:14]
output [2:0] io_out_1_0_bits_virt_channel_id, // @[Switch.scala:27:14]
output io_out_0_0_valid, // @[Switch.scala:27:14]
output io_out_0_0_bits_head, // @[Switch.scala:27:14]
output io_out_0_0_bits_tail, // @[Switch.scala:27:14]
output [72:0] io_out_0_0_bits_payload, // @[Switch.scala:27:14]
output [2:0] io_out_0_0_bits_flow_vnet_id, // @[Switch.scala:27:14]
output [4:0] io_out_0_0_bits_flow_ingress_node, // @[Switch.scala:27:14]
output [1:0] io_out_0_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14]
output [4:0] io_out_0_0_bits_flow_egress_node, // @[Switch.scala:27:14]
output [1:0] io_out_0_0_bits_flow_egress_node_id, // @[Switch.scala:27:14]
output [2:0] io_out_0_0_bits_virt_channel_id, // @[Switch.scala:27:14]
input io_sel_1_0_1_0, // @[Switch.scala:27:14]
input io_sel_1_0_0_0, // @[Switch.scala:27:14]
input io_sel_0_0_1_0, // @[Switch.scala:27:14]
input io_sel_0_0_0_0 // @[Switch.scala:27:14]
);
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
|
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_115( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge)
|
Generate the Verilog code corresponding to the following Chisel files.
File IngressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
class IngressUnit(
ingressNodeId: Int,
cParam: IngressChannelParams,
outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean,
combineSAST: Boolean,
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits)))
}
val io = IO(new IngressUnitIO)
val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2,
flow=combineRCVA))
assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))
route_buffer.io.enq.bits.head := io.in.bits.head
route_buffer.io.enq.bits.tail := io.in.bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
route_buffer.io.enq.bits.flow := DontCare
} else {
route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U
route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U
route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U
route_buffer.io.enq.bits.flow.egress_node := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNode.U)
)
route_buffer.io.enq.bits.flow.egress_node_id := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNodeId.U)
)
}
route_buffer.io.enq.bits.payload := io.in.bits.payload
route_buffer.io.enq.bits.virt_channel_id := DontCare
io.router_req.bits.src_virt_id := 0.U
io.router_req.bits.flow := route_buffer.io.enq.bits.flow
val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U
route_buffer.io.enq.valid := io.in.valid && (
io.router_req.ready || !io.in.bits.head || at_dest)
io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest
io.in.ready := route_buffer.io.enq.ready && (
io.router_req.ready || !io.in.bits.head || at_dest)
route_q.io.enq.valid := io.router_req.fire
route_q.io.enq.bits := io.router_resp
when (io.in.fire && io.in.bits.head && at_dest) {
route_q.io.enq.valid := true.B
route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (egressParams(o).egressId.U === io.in.bits.egress_id) {
route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B
}
}
}
assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))
val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams),
1, pipe=true))
vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits
io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel
io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow
io.vcalloc_req.bits.in_vc := 0.U
val head = route_buffer.io.deq.bits.head
val tail = route_buffer.io.deq.bits.tail
vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head)
)
io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid &&
head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready)
route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head) &&
(vcalloc_q.io.enq.ready || !head))
route_q.io.deq.ready := (route_buffer.io.deq.fire && tail)
vcalloc_q.io.enq.valid := io.vcalloc_req.fire
vcalloc_q.io.enq.bits := io.vcalloc_resp
assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))
io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel
io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail
val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail
io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire
val out_bundle = if (combineSAST) {
Wire(Valid(new SwitchBundle(outParams, egressParams)))
} else {
Reg(Valid(new SwitchBundle(outParams, egressParams)))
}
io.out(0) := out_bundle
out_bundle.valid := vcalloc_buffer.io.deq.fire
out_bundle.bits.flit := vcalloc_buffer.io.deq.bits
out_bundle.bits.flit.virt_channel_id := 0.U
val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq
out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh,
vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq)
io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready
io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready
// TODO: We should not generate input/ingress/output/egress units for untraversable channels
if (!cParam.traversable) {
io.in.ready := false.B
io.router_req.valid := false.B
io.router_req.bits := DontCare
io.vcalloc_req.valid := false.B
io.vcalloc_req.bits := DontCare
io.salloc_req.foreach(_.valid := false.B)
io.salloc_req.foreach(_.bits := DontCare)
io.out.foreach(_.valid := false.B)
io.out.foreach(_.bits := DontCare)
}
}
|
module IngressUnit_63( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_8, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_9, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _GEN; // @[Decoupled.scala:51:35]
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'hB; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'h14; // @[IngressUnit.scala:30:72]
wire [1:0] _route_buffer_io_enq_bits_flow_egress_node_T_4 = {2{_route_buffer_io_enq_bits_flow_egress_node_id_T}}; // @[Mux.scala:30:73]
assign _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_4 == 2'h2; // @[Mux.scala:30:73]
wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_4 != 2'h2; // @[Mux.scala:30:73]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
|
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File SourceD.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import TLMessages._
import TLAtomics._
import TLPermissions._
class SourceDRequest(params: InclusiveCacheParameters) extends FullRequest(params)
{
val sink = UInt(params.inner.bundle.sinkBits.W)
val way = UInt(params.wayBits.W)
val bad = Bool()
}
class SourceDHazard(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val way = UInt(params.wayBits.W)
}
class PutBufferACEntry(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val data = UInt(params.inner.bundle.dataBits.W)
val mask = UInt((params.inner.bundle.dataBits/8).W)
val corrupt = Bool()
}
class SourceD(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val req = Flipped(Decoupled(new SourceDRequest(params)))
val d = Decoupled(new TLBundleD(params.inner.bundle))
// Put data from SinkA
val pb_pop = Decoupled(new PutBufferPop(params))
val pb_beat = Flipped(new PutBufferAEntry(params))
// Release data from SinkC
val rel_pop = Decoupled(new PutBufferPop(params))
val rel_beat = Flipped(new PutBufferCEntry(params))
// Access to the BankedStore
val bs_radr = Decoupled(new BankedStoreInnerAddress(params))
val bs_rdat = Flipped(new BankedStoreInnerDecoded(params))
val bs_wadr = Decoupled(new BankedStoreInnerAddress(params))
val bs_wdat = new BankedStoreInnerPoison(params)
// Is it safe to evict/replace this way?
val evict_req = Flipped(new SourceDHazard(params))
val evict_safe = Bool()
val grant_req = Flipped(new SourceDHazard(params))
val grant_safe = Bool()
})
val beatBytes = params.inner.manager.beatBytes
val writeBytes = params.micro.writeBytes
val s1_valid = Wire(Bool())
val s2_valid = Wire(Bool())
val s3_valid = Wire(Bool())
val s2_ready = Wire(Bool())
val s3_ready = Wire(Bool())
val s4_ready = Wire(Bool())
////////////////////////////////////// STAGE 1 //////////////////////////////////////
// Reform the request beats
val busy = RegInit(false.B)
val s1_block_r = RegInit(false.B)
val s1_counter = RegInit(0.U(params.innerBeatBits.W))
val s1_req_reg = RegEnable(io.req.bits, !busy && io.req.valid)
val s1_req = Mux(!busy, io.req.bits, s1_req_reg)
val s1_x_bypass = Wire(UInt((beatBytes/writeBytes).W)) // might go from high=>low during stall
val s1_latch_bypass = RegNext(!(busy || io.req.valid) || s2_ready)
val s1_bypass = Mux(s1_latch_bypass, s1_x_bypass, RegEnable(s1_x_bypass, s1_latch_bypass))
val s1_mask = MaskGen(s1_req.offset, s1_req.size, beatBytes, writeBytes) & ~s1_bypass
val s1_grant = (s1_req.opcode === AcquireBlock && s1_req.param === BtoT) || s1_req.opcode === AcquirePerm
val s1_need_r = s1_mask.orR && s1_req.prio(0) && s1_req.opcode =/= Hint && !s1_grant &&
(s1_req.opcode =/= PutFullData || s1_req.size < log2Ceil(writeBytes).U )
val s1_valid_r = (busy || io.req.valid) && s1_need_r && !s1_block_r
val s1_need_pb = Mux(s1_req.prio(0), !s1_req.opcode(2), s1_req.opcode(0)) // hasData
val s1_single = Mux(s1_req.prio(0), s1_req.opcode === Hint || s1_grant, s1_req.opcode === Release)
val s1_retires = !s1_single // retire all operations with data in s3 for bypass (saves energy)
// Alternatively: val s1_retires = s1_need_pb // retire only updates for bypass (less backpressure from WB)
val s1_beats1 = Mux(s1_single, 0.U, UIntToOH1(s1_req.size, log2Up(params.cache.blockBytes)) >> log2Ceil(beatBytes))
val s1_beat = (s1_req.offset >> log2Ceil(beatBytes)) | s1_counter
val s1_last = s1_counter === s1_beats1
val s1_first = s1_counter === 0.U
params.ccover(s1_block_r, "SOURCED_1_SRAM_HOLD", "SRAM read-out successful, but stalled by stage 2")
params.ccover(!s1_latch_bypass, "SOURCED_1_BYPASS_HOLD", "Bypass match successful, but stalled by stage 2")
params.ccover((busy || io.req.valid) && !s1_need_r, "SOURCED_1_NO_MODIFY", "Transaction servicable without SRAM")
io.bs_radr.valid := s1_valid_r
io.bs_radr.bits.noop := false.B
io.bs_radr.bits.way := s1_req.way
io.bs_radr.bits.set := s1_req.set
io.bs_radr.bits.beat := s1_beat
io.bs_radr.bits.mask := s1_mask
params.ccover(io.bs_radr.valid && !io.bs_radr.ready, "SOURCED_1_READ_STALL", "Data readout stalled")
// Make a queue to catch BS readout during stalls
val queue = Module(new Queue(chiselTypeOf(io.bs_rdat), 3, flow=true))
queue.io.enq.valid := RegNext(RegNext(io.bs_radr.fire))
queue.io.enq.bits := io.bs_rdat
assert (!queue.io.enq.valid || queue.io.enq.ready)
params.ccover(!queue.io.enq.ready, "SOURCED_1_QUEUE_FULL", "Filled SRAM skidpad queue completely")
when (io.bs_radr.fire) { s1_block_r := true.B }
when (io.req.valid) { busy := true.B }
when (s1_valid && s2_ready) {
s1_counter := s1_counter + 1.U
s1_block_r := false.B
when (s1_last) {
s1_counter := 0.U
busy := false.B
}
}
params.ccover(s1_valid && !s2_ready, "SOURCED_1_STALL", "Stage 1 pipeline blocked")
io.req.ready := !busy
s1_valid := (busy || io.req.valid) && (!s1_valid_r || io.bs_radr.ready)
////////////////////////////////////// STAGE 2 //////////////////////////////////////
// Fetch the request data
val s2_latch = s1_valid && s2_ready
val s2_full = RegInit(false.B)
val s2_valid_pb = RegInit(false.B)
val s2_beat = RegEnable(s1_beat, s2_latch)
val s2_bypass = RegEnable(s1_bypass, s2_latch)
val s2_req = RegEnable(s1_req, s2_latch)
val s2_last = RegEnable(s1_last, s2_latch)
val s2_need_r = RegEnable(s1_need_r, s2_latch)
val s2_need_pb = RegEnable(s1_need_pb, s2_latch)
val s2_retires = RegEnable(s1_retires, s2_latch)
val s2_need_d = RegEnable(!s1_need_pb || s1_first, s2_latch)
val s2_pdata_raw = Wire(new PutBufferACEntry(params))
val s2_pdata = s2_pdata_raw holdUnless s2_valid_pb
s2_pdata_raw.data := Mux(s2_req.prio(0), io.pb_beat.data, io.rel_beat.data)
s2_pdata_raw.mask := Mux(s2_req.prio(0), io.pb_beat.mask, ~0.U(params.inner.manager.beatBytes.W))
s2_pdata_raw.corrupt := Mux(s2_req.prio(0), io.pb_beat.corrupt, io.rel_beat.corrupt)
io.pb_pop.valid := s2_valid_pb && s2_req.prio(0)
io.pb_pop.bits.index := s2_req.put
io.pb_pop.bits.last := s2_last
io.rel_pop.valid := s2_valid_pb && !s2_req.prio(0)
io.rel_pop.bits.index := s2_req.put
io.rel_pop.bits.last := s2_last
params.ccover(io.pb_pop.valid && !io.pb_pop.ready, "SOURCED_2_PUTA_STALL", "Channel A put buffer was not ready in time")
if (!params.firstLevel)
params.ccover(io.rel_pop.valid && !io.rel_pop.ready, "SOURCED_2_PUTC_STALL", "Channel C put buffer was not ready in time")
val pb_ready = Mux(s2_req.prio(0), io.pb_pop.ready, io.rel_pop.ready)
when (pb_ready) { s2_valid_pb := false.B }
when (s2_valid && s3_ready) { s2_full := false.B }
when (s2_latch) { s2_valid_pb := s1_need_pb }
when (s2_latch) { s2_full := true.B }
params.ccover(s2_valid && !s3_ready, "SOURCED_2_STALL", "Stage 2 pipeline blocked")
s2_valid := s2_full && (!s2_valid_pb || pb_ready)
s2_ready := !s2_full || (s3_ready && (!s2_valid_pb || pb_ready))
////////////////////////////////////// STAGE 3 //////////////////////////////////////
// Send D response
val s3_latch = s2_valid && s3_ready
val s3_full = RegInit(false.B)
val s3_valid_d = RegInit(false.B)
val s3_beat = RegEnable(s2_beat, s3_latch)
val s3_bypass = RegEnable(s2_bypass, s3_latch)
val s3_req = RegEnable(s2_req, s3_latch)
val s3_adjusted_opcode = Mux(s3_req.bad, Get, s3_req.opcode) // kill update when denied
val s3_last = RegEnable(s2_last, s3_latch)
val s3_pdata = RegEnable(s2_pdata, s3_latch)
val s3_need_pb = RegEnable(s2_need_pb, s3_latch)
val s3_retires = RegEnable(s2_retires, s3_latch)
val s3_need_r = RegEnable(s2_need_r, s3_latch)
val s3_need_bs = s3_need_pb
val s3_acq = s3_req.opcode === AcquireBlock || s3_req.opcode === AcquirePerm
// Collect s3's data from either the BankedStore or bypass
// NOTE: we use the s3_bypass passed down from s1_bypass, because s2-s4 were guarded by the hazard checks and not stale
val s3_bypass_data = Wire(UInt())
def chunk(x: UInt): Seq[UInt] = Seq.tabulate(beatBytes/writeBytes) { i => x((i+1)*writeBytes*8-1, i*writeBytes*8) }
def chop (x: UInt): Seq[Bool] = Seq.tabulate(beatBytes/writeBytes) { i => x(i) }
def bypass(sel: UInt, x: UInt, y: UInt) =
(chop(sel) zip (chunk(x) zip chunk(y))) .map { case (s, (x, y)) => Mux(s, x, y) } .asUInt
val s3_rdata = bypass(s3_bypass, s3_bypass_data, queue.io.deq.bits.data)
// Lookup table for response codes
val grant = Mux(s3_req.param === BtoT, Grant, GrantData)
val resp_opcode = VecInit(Seq(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, grant, Grant))
// No restrictions on the type of buffer used here
val d = Wire(chiselTypeOf(io.d))
io.d <> params.micro.innerBuf.d(d)
d.valid := s3_valid_d
d.bits.opcode := Mux(s3_req.prio(0), resp_opcode(s3_req.opcode), ReleaseAck)
d.bits.param := Mux(s3_req.prio(0) && s3_acq, Mux(s3_req.param =/= NtoB, toT, toB), 0.U)
d.bits.size := s3_req.size
d.bits.source := s3_req.source
d.bits.sink := s3_req.sink
d.bits.denied := s3_req.bad
d.bits.data := s3_rdata
d.bits.corrupt := s3_req.bad && d.bits.opcode(0)
queue.io.deq.ready := s3_valid && s4_ready && s3_need_r
assert (!s3_full || !s3_need_r || queue.io.deq.valid)
when (d.ready) { s3_valid_d := false.B }
when (s3_valid && s4_ready) { s3_full := false.B }
when (s3_latch) { s3_valid_d := s2_need_d }
when (s3_latch) { s3_full := true.B }
params.ccover(s3_valid && !s4_ready, "SOURCED_3_STALL", "Stage 3 pipeline blocked")
s3_valid := s3_full && (!s3_valid_d || d.ready)
s3_ready := !s3_full || (s4_ready && (!s3_valid_d || d.ready))
////////////////////////////////////// STAGE 4 //////////////////////////////////////
// Writeback updated data
val s4_latch = s3_valid && s3_retires && s4_ready
val s4_full = RegInit(false.B)
val s4_beat = RegEnable(s3_beat, s4_latch)
val s4_need_r = RegEnable(s3_need_r, s4_latch)
val s4_need_bs = RegEnable(s3_need_bs, s4_latch)
val s4_need_pb = RegEnable(s3_need_pb, s4_latch)
val s4_req = RegEnable(s3_req, s4_latch)
val s4_adjusted_opcode = RegEnable(s3_adjusted_opcode, s4_latch)
val s4_pdata = RegEnable(s3_pdata, s4_latch)
val s4_rdata = RegEnable(s3_rdata, s4_latch)
val atomics = Module(new Atomics(params.inner.bundle))
atomics.io.write := s4_req.prio(2)
atomics.io.a.opcode := s4_adjusted_opcode
atomics.io.a.param := s4_req.param
atomics.io.a.size := 0.U
atomics.io.a.source := 0.U
atomics.io.a.address := 0.U
atomics.io.a.mask := s4_pdata.mask
atomics.io.a.data := s4_pdata.data
atomics.io.a.corrupt := DontCare
atomics.io.data_in := s4_rdata
io.bs_wadr.valid := s4_full && s4_need_bs
io.bs_wadr.bits.noop := false.B
io.bs_wadr.bits.way := s4_req.way
io.bs_wadr.bits.set := s4_req.set
io.bs_wadr.bits.beat := s4_beat
io.bs_wadr.bits.mask := Cat(s4_pdata.mask.asBools.grouped(writeBytes).map(_.reduce(_||_)).toList.reverse)
io.bs_wdat.data := atomics.io.data_out
assert (!(s4_full && s4_need_pb && s4_pdata.corrupt), "Data poisoning unsupported")
params.ccover(io.bs_wadr.valid && !io.bs_wadr.ready, "SOURCED_4_WRITEBACK_STALL", "Data writeback stalled")
params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === MIN, "SOURCED_4_ATOMIC_MIN", "Evaluated a signed minimum atomic")
params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === MAX, "SOURCED_4_ATOMIC_MAX", "Evaluated a signed maximum atomic")
params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === MINU, "SOURCED_4_ATOMIC_MINU", "Evaluated an unsigned minimum atomic")
params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === MAXU, "SOURCED_4_ATOMIC_MAXU", "Evaluated an unsigned minimum atomic")
params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === ADD, "SOURCED_4_ATOMIC_ADD", "Evaluated an addition atomic")
params.ccover(s4_req.prio(0) && s4_req.opcode === LogicalData && s4_req.param === XOR, "SOURCED_4_ATOMIC_XOR", "Evaluated a bitwise XOR atomic")
params.ccover(s4_req.prio(0) && s4_req.opcode === LogicalData && s4_req.param === OR, "SOURCED_4_ATOMIC_OR", "Evaluated a bitwise OR atomic")
params.ccover(s4_req.prio(0) && s4_req.opcode === LogicalData && s4_req.param === AND, "SOURCED_4_ATOMIC_AND", "Evaluated a bitwise AND atomic")
params.ccover(s4_req.prio(0) && s4_req.opcode === LogicalData && s4_req.param === SWAP, "SOURCED_4_ATOMIC_SWAP", "Evaluated a bitwise SWAP atomic")
when (io.bs_wadr.ready || !s4_need_bs) { s4_full := false.B }
when (s4_latch) { s4_full := true.B }
s4_ready := !s3_retires || !s4_full || io.bs_wadr.ready || !s4_need_bs
////////////////////////////////////// RETIRED //////////////////////////////////////
// Record for bypass the last three retired writebacks
// We need 3 slots to collect what was in s2, s3, s4 when the request was in s1
// ... you can't rely on s4 being full if bubbles got introduced between s1 and s2
val retire = s4_full && (io.bs_wadr.ready || !s4_need_bs)
val s5_req = RegEnable(s4_req, retire)
val s5_beat = RegEnable(s4_beat, retire)
val s5_dat = RegEnable(atomics.io.data_out, retire)
val s6_req = RegEnable(s5_req, retire)
val s6_beat = RegEnable(s5_beat, retire)
val s6_dat = RegEnable(s5_dat, retire)
val s7_dat = RegEnable(s6_dat, retire)
////////////////////////////////////// BYPASSS //////////////////////////////////////
// Manually retime this circuit to pull a register stage forward
val pre_s3_req = Mux(s3_latch, s2_req, s3_req)
val pre_s4_req = Mux(s4_latch, s3_req, s4_req)
val pre_s5_req = Mux(retire, s4_req, s5_req)
val pre_s6_req = Mux(retire, s5_req, s6_req)
val pre_s3_beat = Mux(s3_latch, s2_beat, s3_beat)
val pre_s4_beat = Mux(s4_latch, s3_beat, s4_beat)
val pre_s5_beat = Mux(retire, s4_beat, s5_beat)
val pre_s6_beat = Mux(retire, s5_beat, s6_beat)
val pre_s5_dat = Mux(retire, atomics.io.data_out, s5_dat)
val pre_s6_dat = Mux(retire, s5_dat, s6_dat)
val pre_s7_dat = Mux(retire, s6_dat, s7_dat)
val pre_s4_full = s4_latch || (!(io.bs_wadr.ready || !s4_need_bs) && s4_full)
val pre_s3_4_match = pre_s4_req.set === pre_s3_req.set && pre_s4_req.way === pre_s3_req.way && pre_s4_beat === pre_s3_beat && pre_s4_full
val pre_s3_5_match = pre_s5_req.set === pre_s3_req.set && pre_s5_req.way === pre_s3_req.way && pre_s5_beat === pre_s3_beat
val pre_s3_6_match = pre_s6_req.set === pre_s3_req.set && pre_s6_req.way === pre_s3_req.way && pre_s6_beat === pre_s3_beat
val pre_s3_4_bypass = Mux(pre_s3_4_match, MaskGen(pre_s4_req.offset, pre_s4_req.size, beatBytes, writeBytes), 0.U)
val pre_s3_5_bypass = Mux(pre_s3_5_match, MaskGen(pre_s5_req.offset, pre_s5_req.size, beatBytes, writeBytes), 0.U)
val pre_s3_6_bypass = Mux(pre_s3_6_match, MaskGen(pre_s6_req.offset, pre_s6_req.size, beatBytes, writeBytes), 0.U)
s3_bypass_data :=
bypass(RegNext(pre_s3_4_bypass), atomics.io.data_out, RegNext(
bypass(pre_s3_5_bypass, pre_s5_dat,
bypass(pre_s3_6_bypass, pre_s6_dat,
pre_s7_dat))))
// Detect which parts of s1 will be bypassed from later pipeline stages (s1-s4)
// Note: we also bypass from reads ahead in the pipeline to save power
val s1_2_match = s2_req.set === s1_req.set && s2_req.way === s1_req.way && s2_beat === s1_beat && s2_full && s2_retires
val s1_3_match = s3_req.set === s1_req.set && s3_req.way === s1_req.way && s3_beat === s1_beat && s3_full && s3_retires
val s1_4_match = s4_req.set === s1_req.set && s4_req.way === s1_req.way && s4_beat === s1_beat && s4_full
for (i <- 0 until 8) {
val cover = 1.U
val s2 = s1_2_match === cover(0)
val s3 = s1_3_match === cover(1)
val s4 = s1_4_match === cover(2)
params.ccover(io.req.valid && s2 && s3 && s4, "SOURCED_BYPASS_CASE_" + i, "Bypass data from all subsets of pipeline stages")
}
val s1_2_bypass = Mux(s1_2_match, MaskGen(s2_req.offset, s2_req.size, beatBytes, writeBytes), 0.U)
val s1_3_bypass = Mux(s1_3_match, MaskGen(s3_req.offset, s3_req.size, beatBytes, writeBytes), 0.U)
val s1_4_bypass = Mux(s1_4_match, MaskGen(s4_req.offset, s4_req.size, beatBytes, writeBytes), 0.U)
s1_x_bypass := s1_2_bypass | s1_3_bypass | s1_4_bypass
////////////////////////////////////// HAZARDS //////////////////////////////////////
// SinkC, SourceC, and SinkD can never interfer with each other because their operation
// is fully contained with an execution plan of an MSHR. That MSHR owns the entire set, so
// there is no way for a data race.
// However, SourceD is special. We allow it to run ahead after the MSHR and scheduler have
// released control of a set+way. This is necessary to allow single cycle occupancy for
// hits. Thus, we need to be careful about data hazards between SourceD and the other ports
// of the BankedStore. We can at least compare to registers 's1_req_reg', because the first
// cycle of SourceD falls within the occupancy of the MSHR's plan.
// Must ReleaseData=> be interlocked? RaW hazard
io.evict_safe :=
(!busy || io.evict_req.way =/= s1_req_reg.way || io.evict_req.set =/= s1_req_reg.set) &&
(!s2_full || io.evict_req.way =/= s2_req.way || io.evict_req.set =/= s2_req.set) &&
(!s3_full || io.evict_req.way =/= s3_req.way || io.evict_req.set =/= s3_req.set) &&
(!s4_full || io.evict_req.way =/= s4_req.way || io.evict_req.set =/= s4_req.set)
// Must =>GrantData be interlocked? WaR hazard
io.grant_safe :=
(!busy || io.grant_req.way =/= s1_req_reg.way || io.grant_req.set =/= s1_req_reg.set) &&
(!s2_full || io.grant_req.way =/= s2_req.way || io.grant_req.set =/= s2_req.set) &&
(!s3_full || io.grant_req.way =/= s3_req.way || io.grant_req.set =/= s3_req.set) &&
(!s4_full || io.grant_req.way =/= s4_req.way || io.grant_req.set =/= s4_req.set)
// SourceD cannot overlap with SinkC b/c the only way inner caches could become
// dirty such that they want to put data in via SinkC is if we Granted them permissions,
// which must flow through the SourecD pipeline.
}
|
module SourceD_3( // @[SourceD.scala:48:7]
input clock, // @[SourceD.scala:48:7]
input reset, // @[SourceD.scala:48:7]
output io_req_ready, // @[SourceD.scala:50:14]
input io_req_valid, // @[SourceD.scala:50:14]
input io_req_bits_prio_0, // @[SourceD.scala:50:14]
input io_req_bits_prio_1, // @[SourceD.scala:50:14]
input io_req_bits_prio_2, // @[SourceD.scala:50:14]
input io_req_bits_control, // @[SourceD.scala:50:14]
input [2:0] io_req_bits_opcode, // @[SourceD.scala:50:14]
input [2:0] io_req_bits_param, // @[SourceD.scala:50:14]
input [2:0] io_req_bits_size, // @[SourceD.scala:50:14]
input [5:0] io_req_bits_source, // @[SourceD.scala:50:14]
input [8:0] io_req_bits_tag, // @[SourceD.scala:50:14]
input [5:0] io_req_bits_offset, // @[SourceD.scala:50:14]
input [5:0] io_req_bits_put, // @[SourceD.scala:50:14]
input [10:0] io_req_bits_set, // @[SourceD.scala:50:14]
input [3:0] io_req_bits_sink, // @[SourceD.scala:50:14]
input [3:0] io_req_bits_way, // @[SourceD.scala:50:14]
input io_req_bits_bad, // @[SourceD.scala:50:14]
input io_d_ready, // @[SourceD.scala:50:14]
output io_d_valid, // @[SourceD.scala:50:14]
output [2:0] io_d_bits_opcode, // @[SourceD.scala:50:14]
output [1:0] io_d_bits_param, // @[SourceD.scala:50:14]
output [2:0] io_d_bits_size, // @[SourceD.scala:50:14]
output [5:0] io_d_bits_source, // @[SourceD.scala:50:14]
output [3:0] io_d_bits_sink, // @[SourceD.scala:50:14]
output io_d_bits_denied, // @[SourceD.scala:50:14]
output [127:0] io_d_bits_data, // @[SourceD.scala:50:14]
output io_d_bits_corrupt, // @[SourceD.scala:50:14]
input io_pb_pop_ready, // @[SourceD.scala:50:14]
output io_pb_pop_valid, // @[SourceD.scala:50:14]
output [5:0] io_pb_pop_bits_index, // @[SourceD.scala:50:14]
output io_pb_pop_bits_last, // @[SourceD.scala:50:14]
input [127:0] io_pb_beat_data, // @[SourceD.scala:50:14]
input [15:0] io_pb_beat_mask, // @[SourceD.scala:50:14]
input io_pb_beat_corrupt, // @[SourceD.scala:50:14]
input io_rel_pop_ready, // @[SourceD.scala:50:14]
output io_rel_pop_valid, // @[SourceD.scala:50:14]
output [5:0] io_rel_pop_bits_index, // @[SourceD.scala:50:14]
output io_rel_pop_bits_last, // @[SourceD.scala:50:14]
input [127:0] io_rel_beat_data, // @[SourceD.scala:50:14]
input io_rel_beat_corrupt, // @[SourceD.scala:50:14]
input io_bs_radr_ready, // @[SourceD.scala:50:14]
output io_bs_radr_valid, // @[SourceD.scala:50:14]
output [3:0] io_bs_radr_bits_way, // @[SourceD.scala:50:14]
output [10:0] io_bs_radr_bits_set, // @[SourceD.scala:50:14]
output [1:0] io_bs_radr_bits_beat, // @[SourceD.scala:50:14]
output [1:0] io_bs_radr_bits_mask, // @[SourceD.scala:50:14]
input [127:0] io_bs_rdat_data, // @[SourceD.scala:50:14]
input io_bs_wadr_ready, // @[SourceD.scala:50:14]
output io_bs_wadr_valid, // @[SourceD.scala:50:14]
output [3:0] io_bs_wadr_bits_way, // @[SourceD.scala:50:14]
output [10:0] io_bs_wadr_bits_set, // @[SourceD.scala:50:14]
output [1:0] io_bs_wadr_bits_beat, // @[SourceD.scala:50:14]
output [1:0] io_bs_wadr_bits_mask, // @[SourceD.scala:50:14]
output [127:0] io_bs_wdat_data, // @[SourceD.scala:50:14]
input [10:0] io_evict_req_set, // @[SourceD.scala:50:14]
input [3:0] io_evict_req_way, // @[SourceD.scala:50:14]
output io_evict_safe, // @[SourceD.scala:50:14]
input [10:0] io_grant_req_set, // @[SourceD.scala:50:14]
input [3:0] io_grant_req_way, // @[SourceD.scala:50:14]
output io_grant_safe // @[SourceD.scala:50:14]
);
wire [127:0] _atomics_io_data_out; // @[SourceD.scala:258:23]
wire _queue_io_enq_ready; // @[SourceD.scala:120:21]
wire _queue_io_deq_valid; // @[SourceD.scala:120:21]
wire [127:0] _queue_io_deq_bits_data; // @[SourceD.scala:120:21]
wire io_req_valid_0 = io_req_valid; // @[SourceD.scala:48:7]
wire io_req_bits_prio_0_0 = io_req_bits_prio_0; // @[SourceD.scala:48:7]
wire io_req_bits_prio_1_0 = io_req_bits_prio_1; // @[SourceD.scala:48:7]
wire io_req_bits_prio_2_0 = io_req_bits_prio_2; // @[SourceD.scala:48:7]
wire io_req_bits_control_0 = io_req_bits_control; // @[SourceD.scala:48:7]
wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceD.scala:48:7]
wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceD.scala:48:7]
wire [2:0] io_req_bits_size_0 = io_req_bits_size; // @[SourceD.scala:48:7]
wire [5:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceD.scala:48:7]
wire [8:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceD.scala:48:7]
wire [5:0] io_req_bits_offset_0 = io_req_bits_offset; // @[SourceD.scala:48:7]
wire [5:0] io_req_bits_put_0 = io_req_bits_put; // @[SourceD.scala:48:7]
wire [10:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceD.scala:48:7]
wire [3:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceD.scala:48:7]
wire [3:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceD.scala:48:7]
wire io_req_bits_bad_0 = io_req_bits_bad; // @[SourceD.scala:48:7]
wire io_d_ready_0 = io_d_ready; // @[SourceD.scala:48:7]
wire io_pb_pop_ready_0 = io_pb_pop_ready; // @[SourceD.scala:48:7]
wire [127:0] io_pb_beat_data_0 = io_pb_beat_data; // @[SourceD.scala:48:7]
wire [15:0] io_pb_beat_mask_0 = io_pb_beat_mask; // @[SourceD.scala:48:7]
wire io_pb_beat_corrupt_0 = io_pb_beat_corrupt; // @[SourceD.scala:48:7]
wire io_rel_pop_ready_0 = io_rel_pop_ready; // @[SourceD.scala:48:7]
wire [127:0] io_rel_beat_data_0 = io_rel_beat_data; // @[SourceD.scala:48:7]
wire io_rel_beat_corrupt_0 = io_rel_beat_corrupt; // @[SourceD.scala:48:7]
wire io_bs_radr_ready_0 = io_bs_radr_ready; // @[SourceD.scala:48:7]
wire [127:0] io_bs_rdat_data_0 = io_bs_rdat_data; // @[SourceD.scala:48:7]
wire io_bs_wadr_ready_0 = io_bs_wadr_ready; // @[SourceD.scala:48:7]
wire [10:0] io_evict_req_set_0 = io_evict_req_set; // @[SourceD.scala:48:7]
wire [3:0] io_evict_req_way_0 = io_evict_req_way; // @[SourceD.scala:48:7]
wire [10:0] io_grant_req_set_0 = io_grant_req_set; // @[SourceD.scala:48:7]
wire [3:0] io_grant_req_way_0 = io_grant_req_way; // @[SourceD.scala:48:7]
wire io_bs_radr_bits_noop = 1'h0; // @[SourceD.scala:48:7]
wire io_bs_wadr_bits_noop = 1'h0; // @[SourceD.scala:48:7]
wire s1_mask_size = 1'h1; // @[Misc.scala:209:26]
wire pre_s3_4_bypass_size = 1'h1; // @[Misc.scala:209:26]
wire pre_s3_5_bypass_size = 1'h1; // @[Misc.scala:209:26]
wire pre_s3_6_bypass_size = 1'h1; // @[Misc.scala:209:26]
wire s1_2_bypass_size = 1'h1; // @[Misc.scala:209:26]
wire s1_3_bypass_size = 1'h1; // @[Misc.scala:209:26]
wire s1_4_bypass_size = 1'h1; // @[Misc.scala:209:26]
wire [3:0] s1_mask_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [3:0] pre_s3_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [3:0] pre_s3_5_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [3:0] pre_s3_6_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [3:0] s1_2_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [3:0] s1_3_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [3:0] s1_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81]
wire [2:0] resp_opcode_0 = 3'h0; // @[SourceD.scala:215:28]
wire [2:0] resp_opcode_1 = 3'h0; // @[SourceD.scala:215:28]
wire [2:0] resp_opcode_7 = 3'h4; // @[SourceD.scala:215:28]
wire [2:0] resp_opcode_5 = 3'h2; // @[SourceD.scala:215:28]
wire [2:0] resp_opcode_2 = 3'h1; // @[SourceD.scala:215:28]
wire [2:0] resp_opcode_3 = 3'h1; // @[SourceD.scala:215:28]
wire [2:0] resp_opcode_4 = 3'h1; // @[SourceD.scala:215:28]
wire [15:0] _s2_pdata_raw_mask_T = 16'hFFFF; // @[SourceD.scala:161:64]
wire _io_req_ready_T; // @[SourceD.scala:140:19]
wire d_ready = io_d_ready_0; // @[SourceD.scala:48:7, :218:15]
wire d_valid; // @[SourceD.scala:218:15]
wire [2:0] d_bits_opcode; // @[SourceD.scala:218:15]
wire [1:0] d_bits_param; // @[SourceD.scala:218:15]
wire [2:0] d_bits_size; // @[SourceD.scala:218:15]
wire [5:0] d_bits_source; // @[SourceD.scala:218:15]
wire [3:0] d_bits_sink; // @[SourceD.scala:218:15]
wire d_bits_denied; // @[SourceD.scala:218:15]
wire [127:0] d_bits_data; // @[SourceD.scala:218:15]
wire d_bits_corrupt; // @[SourceD.scala:218:15]
wire _io_pb_pop_valid_T; // @[SourceD.scala:164:34]
wire _io_rel_pop_valid_T_1; // @[SourceD.scala:167:35]
wire s1_valid_r; // @[SourceD.scala:96:56]
wire [3:0] s1_req_way; // @[SourceD.scala:88:19]
wire [10:0] s1_req_set; // @[SourceD.scala:88:19]
wire [1:0] s1_beat; // @[SourceD.scala:102:56]
wire [1:0] s1_mask; // @[SourceD.scala:92:76]
wire _io_bs_wadr_valid_T; // @[SourceD.scala:270:31]
wire [1:0] _io_bs_wadr_bits_mask_T_30; // @[SourceD.scala:275:30]
wire _io_evict_safe_T_22; // @[SourceD.scala:378:90]
wire _io_grant_safe_T_22; // @[SourceD.scala:385:90]
wire io_req_ready_0; // @[SourceD.scala:48:7]
wire [2:0] io_d_bits_opcode_0; // @[SourceD.scala:48:7]
wire [1:0] io_d_bits_param_0; // @[SourceD.scala:48:7]
wire [2:0] io_d_bits_size_0; // @[SourceD.scala:48:7]
wire [5:0] io_d_bits_source_0; // @[SourceD.scala:48:7]
wire [3:0] io_d_bits_sink_0; // @[SourceD.scala:48:7]
wire io_d_bits_denied_0; // @[SourceD.scala:48:7]
wire [127:0] io_d_bits_data_0; // @[SourceD.scala:48:7]
wire io_d_bits_corrupt_0; // @[SourceD.scala:48:7]
wire io_d_valid_0; // @[SourceD.scala:48:7]
wire [5:0] io_pb_pop_bits_index_0; // @[SourceD.scala:48:7]
wire io_pb_pop_bits_last_0; // @[SourceD.scala:48:7]
wire io_pb_pop_valid_0; // @[SourceD.scala:48:7]
wire [5:0] io_rel_pop_bits_index_0; // @[SourceD.scala:48:7]
wire io_rel_pop_bits_last_0; // @[SourceD.scala:48:7]
wire io_rel_pop_valid_0; // @[SourceD.scala:48:7]
wire [3:0] io_bs_radr_bits_way_0; // @[SourceD.scala:48:7]
wire [10:0] io_bs_radr_bits_set_0; // @[SourceD.scala:48:7]
wire [1:0] io_bs_radr_bits_beat_0; // @[SourceD.scala:48:7]
wire [1:0] io_bs_radr_bits_mask_0; // @[SourceD.scala:48:7]
wire io_bs_radr_valid_0; // @[SourceD.scala:48:7]
wire [3:0] io_bs_wadr_bits_way_0; // @[SourceD.scala:48:7]
wire [10:0] io_bs_wadr_bits_set_0; // @[SourceD.scala:48:7]
wire [1:0] io_bs_wadr_bits_beat_0; // @[SourceD.scala:48:7]
wire [1:0] io_bs_wadr_bits_mask_0; // @[SourceD.scala:48:7]
wire io_bs_wadr_valid_0; // @[SourceD.scala:48:7]
wire [127:0] io_bs_wdat_data_0; // @[SourceD.scala:48:7]
wire io_evict_safe_0; // @[SourceD.scala:48:7]
wire io_grant_safe_0; // @[SourceD.scala:48:7]
wire _s1_valid_T_3; // @[SourceD.scala:141:38]
wire s1_valid; // @[SourceD.scala:74:22]
wire _s2_valid_T_2; // @[SourceD.scala:183:23]
wire s2_valid; // @[SourceD.scala:75:22]
wire _s3_valid_T_2; // @[SourceD.scala:241:23]
wire s3_valid; // @[SourceD.scala:76:22]
wire _s2_ready_T_4; // @[SourceD.scala:184:24]
wire s2_ready; // @[SourceD.scala:77:22]
wire _s3_ready_T_4; // @[SourceD.scala:242:24]
wire s3_ready; // @[SourceD.scala:78:22]
wire _s4_ready_T_5; // @[SourceD.scala:293:59]
wire s4_ready; // @[SourceD.scala:79:22]
reg busy; // @[SourceD.scala:84:21]
reg s1_block_r; // @[SourceD.scala:85:27]
reg [1:0] s1_counter; // @[SourceD.scala:86:27]
wire _s1_req_reg_T = ~busy; // @[SourceD.scala:84:21, :87:43]
wire _s1_req_reg_T_1 = _s1_req_reg_T & io_req_valid_0; // @[SourceD.scala:48:7, :87:{43,49}]
reg s1_req_reg_prio_0; // @[SourceD.scala:87:29]
reg s1_req_reg_prio_1; // @[SourceD.scala:87:29]
reg s1_req_reg_prio_2; // @[SourceD.scala:87:29]
reg s1_req_reg_control; // @[SourceD.scala:87:29]
reg [2:0] s1_req_reg_opcode; // @[SourceD.scala:87:29]
reg [2:0] s1_req_reg_param; // @[SourceD.scala:87:29]
reg [2:0] s1_req_reg_size; // @[SourceD.scala:87:29]
reg [5:0] s1_req_reg_source; // @[SourceD.scala:87:29]
reg [8:0] s1_req_reg_tag; // @[SourceD.scala:87:29]
reg [5:0] s1_req_reg_offset; // @[SourceD.scala:87:29]
reg [5:0] s1_req_reg_put; // @[SourceD.scala:87:29]
reg [10:0] s1_req_reg_set; // @[SourceD.scala:87:29]
reg [3:0] s1_req_reg_sink; // @[SourceD.scala:87:29]
reg [3:0] s1_req_reg_way; // @[SourceD.scala:87:29]
reg s1_req_reg_bad; // @[SourceD.scala:87:29]
wire _s1_req_T = ~busy; // @[SourceD.scala:84:21, :87:43, :88:20]
wire s1_req_prio_0 = _s1_req_T ? io_req_bits_prio_0_0 : s1_req_reg_prio_0; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire s1_req_prio_1 = _s1_req_T ? io_req_bits_prio_1_0 : s1_req_reg_prio_1; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire s1_req_prio_2 = _s1_req_T ? io_req_bits_prio_2_0 : s1_req_reg_prio_2; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire s1_req_control = _s1_req_T ? io_req_bits_control_0 : s1_req_reg_control; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [2:0] s1_req_opcode = _s1_req_T ? io_req_bits_opcode_0 : s1_req_reg_opcode; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [2:0] s1_req_param = _s1_req_T ? io_req_bits_param_0 : s1_req_reg_param; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [2:0] s1_req_size = _s1_req_T ? io_req_bits_size_0 : s1_req_reg_size; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [5:0] s1_req_source = _s1_req_T ? io_req_bits_source_0 : s1_req_reg_source; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [8:0] s1_req_tag = _s1_req_T ? io_req_bits_tag_0 : s1_req_reg_tag; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [5:0] s1_req_offset = _s1_req_T ? io_req_bits_offset_0 : s1_req_reg_offset; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [5:0] s1_req_put = _s1_req_T ? io_req_bits_put_0 : s1_req_reg_put; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
assign s1_req_set = _s1_req_T ? io_req_bits_set_0 : s1_req_reg_set; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire [3:0] s1_req_sink = _s1_req_T ? io_req_bits_sink_0 : s1_req_reg_sink; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
assign s1_req_way = _s1_req_T ? io_req_bits_way_0 : s1_req_reg_way; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
wire s1_req_bad = _s1_req_T ? io_req_bits_bad_0 : s1_req_reg_bad; // @[SourceD.scala:48:7, :87:29, :88:{19,20}]
assign io_bs_radr_bits_set_0 = s1_req_set; // @[SourceD.scala:48:7, :88:19]
assign io_bs_radr_bits_way_0 = s1_req_way; // @[SourceD.scala:48:7, :88:19]
wire [1:0] _s1_x_bypass_T_1; // @[SourceD.scala:360:44]
wire [1:0] s1_x_bypass; // @[SourceD.scala:89:25]
wire _T_1 = busy | io_req_valid_0; // @[SourceD.scala:48:7, :84:21, :90:40]
wire _s1_latch_bypass_T; // @[SourceD.scala:90:40]
assign _s1_latch_bypass_T = _T_1; // @[SourceD.scala:90:40]
wire _s1_valid_r_T; // @[SourceD.scala:96:26]
assign _s1_valid_r_T = _T_1; // @[SourceD.scala:90:40, :96:26]
wire _s1_valid_T; // @[SourceD.scala:141:21]
assign _s1_valid_T = _T_1; // @[SourceD.scala:90:40, :141:21]
wire _s1_latch_bypass_T_1 = ~_s1_latch_bypass_T; // @[SourceD.scala:90:{33,40}]
wire _s1_latch_bypass_T_2 = _s1_latch_bypass_T_1 | s2_ready; // @[SourceD.scala:77:22, :90:{33,57}]
reg s1_latch_bypass; // @[SourceD.scala:90:32]
reg [1:0] s1_bypass_r; // @[SourceD.scala:91:62]
wire [1:0] s1_bypass = s1_latch_bypass ? s1_x_bypass : s1_bypass_r; // @[SourceD.scala:89:25, :90:32, :91:{22,62}]
wire [3:0] _s1_mask_sizeOH_T = {1'h0, s1_req_size}; // @[Misc.scala:202:34]
wire [1:0] s1_mask_sizeOH_shiftAmount = _s1_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _s1_mask_sizeOH_T_1 = 4'h1 << s1_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] _s1_mask_sizeOH_T_2 = _s1_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire s1_mask_sub_0_1 = s1_req_size[2]; // @[Misc.scala:206:21]
wire s1_mask_bit = s1_req_offset[3]; // @[Misc.scala:210:26]
wire s1_mask_eq_1 = s1_mask_bit; // @[Misc.scala:210:26, :214:27]
wire s1_mask_nbit = ~s1_mask_bit; // @[Misc.scala:210:26, :211:20]
wire s1_mask_eq = s1_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _s1_mask_acc_T = s1_mask_eq; // @[Misc.scala:214:27, :215:38]
wire s1_mask_acc = s1_mask_sub_0_1 | _s1_mask_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _s1_mask_acc_T_1 = s1_mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire s1_mask_acc_1 = s1_mask_sub_0_1 | _s1_mask_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire [1:0] _s1_mask_T = {s1_mask_acc_1, s1_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] _s1_mask_T_1 = ~s1_bypass; // @[SourceD.scala:91:22, :92:78]
assign s1_mask = _s1_mask_T & _s1_mask_T_1; // @[Misc.scala:222:10]
assign io_bs_radr_bits_mask_0 = s1_mask; // @[SourceD.scala:48:7, :92:76]
wire _GEN = s1_req_opcode == 3'h6; // @[SourceD.scala:88:19, :93:33]
wire _s1_grant_T; // @[SourceD.scala:93:33]
assign _s1_grant_T = _GEN; // @[SourceD.scala:93:33]
wire _s1_single_T_2; // @[SourceD.scala:98:89]
assign _s1_single_T_2 = _GEN; // @[SourceD.scala:93:33, :98:89]
wire _s1_grant_T_1 = s1_req_param == 3'h2; // @[SourceD.scala:88:19, :93:66]
wire _s1_grant_T_2 = _s1_grant_T & _s1_grant_T_1; // @[SourceD.scala:93:{33,50,66}]
wire _s1_grant_T_3 = &s1_req_opcode; // @[SourceD.scala:88:19, :93:93]
wire s1_grant = _s1_grant_T_2 | _s1_grant_T_3; // @[SourceD.scala:93:{50,76,93}]
wire _s1_need_r_T = |s1_mask; // @[SourceD.scala:92:76, :94:27]
wire _s1_need_r_T_1 = _s1_need_r_T & s1_req_prio_0; // @[SourceD.scala:88:19, :94:{27,31}]
wire _s1_need_r_T_2 = s1_req_opcode != 3'h5; // @[SourceD.scala:88:19, :94:66]
wire _s1_need_r_T_3 = _s1_need_r_T_1 & _s1_need_r_T_2; // @[SourceD.scala:94:{31,49,66}]
wire _s1_need_r_T_4 = ~s1_grant; // @[SourceD.scala:93:76, :94:78]
wire _s1_need_r_T_5 = _s1_need_r_T_3 & _s1_need_r_T_4; // @[SourceD.scala:94:{49,75,78}]
wire _s1_need_r_T_6 = |s1_req_opcode; // @[SourceD.scala:88:19, :95:34]
wire _s1_need_r_T_7 = s1_req_size < 3'h3; // @[SourceD.scala:88:19, :95:65]
wire _s1_need_r_T_8 = _s1_need_r_T_6 | _s1_need_r_T_7; // @[SourceD.scala:95:{34,50,65}]
wire s1_need_r = _s1_need_r_T_5 & _s1_need_r_T_8; // @[SourceD.scala:94:{75,88}, :95:50]
wire _s1_valid_r_T_1 = _s1_valid_r_T & s1_need_r; // @[SourceD.scala:94:88, :96:{26,43}]
wire _s1_valid_r_T_2 = ~s1_block_r; // @[SourceD.scala:85:27, :96:59]
assign s1_valid_r = _s1_valid_r_T_1 & _s1_valid_r_T_2; // @[SourceD.scala:96:{43,56,59}]
assign io_bs_radr_valid_0 = s1_valid_r; // @[SourceD.scala:48:7, :96:56]
wire _s1_need_pb_T = s1_req_opcode[2]; // @[SourceD.scala:88:19, :97:54]
wire _s1_need_pb_T_1 = ~_s1_need_pb_T; // @[SourceD.scala:97:{40,54}]
wire _s1_need_pb_T_2 = s1_req_opcode[0]; // @[SourceD.scala:88:19, :97:72]
wire s1_need_pb = s1_req_prio_0 ? _s1_need_pb_T_1 : _s1_need_pb_T_2; // @[SourceD.scala:88:19, :97:{23,40,72}]
wire _s1_single_T = s1_req_opcode == 3'h5; // @[SourceD.scala:88:19, :98:53]
wire _s1_single_T_1 = _s1_single_T | s1_grant; // @[SourceD.scala:93:76, :98:{53,62}]
wire s1_single = s1_req_prio_0 ? _s1_single_T_1 : _s1_single_T_2; // @[SourceD.scala:88:19, :98:{22,62,89}]
wire s1_retires = ~s1_single; // @[SourceD.scala:98:22, :99:20]
wire [12:0] _s1_beats1_T = 13'h3F << s1_req_size; // @[package.scala:243:71]
wire [5:0] _s1_beats1_T_1 = _s1_beats1_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _s1_beats1_T_2 = ~_s1_beats1_T_1; // @[package.scala:243:{46,76}]
wire [1:0] _s1_beats1_T_3 = _s1_beats1_T_2[5:4]; // @[package.scala:243:46]
wire [1:0] s1_beats1 = s1_single ? 2'h0 : _s1_beats1_T_3; // @[SourceD.scala:98:22, :101:{22,95}]
wire [1:0] _s1_beat_T = s1_req_offset[5:4]; // @[SourceD.scala:88:19, :102:32]
assign s1_beat = _s1_beat_T | s1_counter; // @[SourceD.scala:86:27, :102:{32,56}]
assign io_bs_radr_bits_beat_0 = s1_beat; // @[SourceD.scala:48:7, :102:56]
wire s1_last = s1_counter == s1_beats1; // @[SourceD.scala:86:27, :101:22, :103:28]
wire s1_first = s1_counter == 2'h0; // @[SourceD.scala:86:27, :104:29]
wire _queue_io_enq_valid_T = io_bs_radr_ready_0 & io_bs_radr_valid_0; // @[Decoupled.scala:51:35]
reg queue_io_enq_valid_REG; // @[SourceD.scala:121:40]
reg queue_io_enq_valid_REG_1; // @[SourceD.scala:121:32]
wire s2_latch = s1_valid & s2_ready; // @[SourceD.scala:74:22, :77:22, :129:18, :146:27]
wire [2:0] _s1_counter_T = {1'h0, s1_counter} + 3'h1; // @[SourceD.scala:86:27, :130:30]
wire [1:0] _s1_counter_T_1 = _s1_counter_T[1:0]; // @[SourceD.scala:130:30]
assign _io_req_ready_T = ~busy; // @[SourceD.scala:84:21, :87:43, :140:19]
assign io_req_ready_0 = _io_req_ready_T; // @[SourceD.scala:48:7, :140:19]
wire _s1_valid_T_1 = ~s1_valid_r; // @[SourceD.scala:96:56, :141:42]
wire _s1_valid_T_2 = _s1_valid_T_1 | io_bs_radr_ready_0; // @[SourceD.scala:48:7, :141:{42,54}]
assign _s1_valid_T_3 = _s1_valid_T & _s1_valid_T_2; // @[SourceD.scala:141:{21,38,54}]
assign s1_valid = _s1_valid_T_3; // @[SourceD.scala:74:22, :141:38]
reg s2_full; // @[SourceD.scala:147:24]
reg s2_valid_pb; // @[SourceD.scala:148:28]
reg [1:0] s2_beat; // @[SourceD.scala:149:26]
reg [1:0] s2_bypass; // @[SourceD.scala:150:28]
reg s2_req_prio_0; // @[SourceD.scala:151:25]
reg s2_req_prio_1; // @[SourceD.scala:151:25]
reg s2_req_prio_2; // @[SourceD.scala:151:25]
reg s2_req_control; // @[SourceD.scala:151:25]
reg [2:0] s2_req_opcode; // @[SourceD.scala:151:25]
reg [2:0] s2_req_param; // @[SourceD.scala:151:25]
reg [2:0] s2_req_size; // @[SourceD.scala:151:25]
reg [5:0] s2_req_source; // @[SourceD.scala:151:25]
reg [8:0] s2_req_tag; // @[SourceD.scala:151:25]
reg [5:0] s2_req_offset; // @[SourceD.scala:151:25]
reg [5:0] s2_req_put; // @[SourceD.scala:151:25]
assign io_pb_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25]
assign io_rel_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25]
reg [10:0] s2_req_set; // @[SourceD.scala:151:25]
reg [3:0] s2_req_sink; // @[SourceD.scala:151:25]
reg [3:0] s2_req_way; // @[SourceD.scala:151:25]
reg s2_req_bad; // @[SourceD.scala:151:25]
reg s2_last; // @[SourceD.scala:152:26]
assign io_pb_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26]
assign io_rel_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26]
reg s2_need_r; // @[SourceD.scala:153:28]
reg s2_need_pb; // @[SourceD.scala:154:29]
reg s2_retires; // @[SourceD.scala:155:29]
wire _s2_need_d_T = ~s1_need_pb; // @[SourceD.scala:97:23, :156:29]
wire _s2_need_d_T_1 = _s2_need_d_T | s1_first; // @[SourceD.scala:104:29, :156:{29,41}]
reg s2_need_d; // @[SourceD.scala:156:28]
wire [127:0] _s2_pdata_raw_data_T; // @[SourceD.scala:160:30]
wire [15:0] _s2_pdata_raw_mask_T_1; // @[SourceD.scala:161:30]
wire _s2_pdata_raw_corrupt_T; // @[SourceD.scala:162:30]
wire [127:0] s2_pdata_raw_data; // @[SourceD.scala:157:26]
wire [15:0] s2_pdata_raw_mask; // @[SourceD.scala:157:26]
wire s2_pdata_raw_corrupt; // @[SourceD.scala:157:26]
reg [127:0] s2_pdata_r_data; // @[package.scala:88:63]
reg [15:0] s2_pdata_r_mask; // @[package.scala:88:63]
reg s2_pdata_r_corrupt; // @[package.scala:88:63]
wire [127:0] s2_pdata_data = s2_valid_pb ? s2_pdata_raw_data : s2_pdata_r_data; // @[package.scala:88:{42,63}]
wire [15:0] s2_pdata_mask = s2_valid_pb ? s2_pdata_raw_mask : s2_pdata_r_mask; // @[package.scala:88:{42,63}]
wire s2_pdata_corrupt = s2_valid_pb ? s2_pdata_raw_corrupt : s2_pdata_r_corrupt; // @[package.scala:88:{42,63}]
assign _s2_pdata_raw_data_T = s2_req_prio_0 ? io_pb_beat_data_0 : io_rel_beat_data_0; // @[SourceD.scala:48:7, :151:25, :160:30]
assign s2_pdata_raw_data = _s2_pdata_raw_data_T; // @[SourceD.scala:157:26, :160:30]
assign _s2_pdata_raw_mask_T_1 = s2_req_prio_0 ? io_pb_beat_mask_0 : 16'hFFFF; // @[SourceD.scala:48:7, :151:25, :161:30]
assign s2_pdata_raw_mask = _s2_pdata_raw_mask_T_1; // @[SourceD.scala:157:26, :161:30]
assign _s2_pdata_raw_corrupt_T = s2_req_prio_0 ? io_pb_beat_corrupt_0 : io_rel_beat_corrupt_0; // @[SourceD.scala:48:7, :151:25, :162:30]
assign s2_pdata_raw_corrupt = _s2_pdata_raw_corrupt_T; // @[SourceD.scala:157:26, :162:30]
assign _io_pb_pop_valid_T = s2_valid_pb & s2_req_prio_0; // @[SourceD.scala:148:28, :151:25, :164:34]
assign io_pb_pop_valid_0 = _io_pb_pop_valid_T; // @[SourceD.scala:48:7, :164:34]
wire _io_rel_pop_valid_T = ~s2_req_prio_0; // @[SourceD.scala:151:25, :167:38]
assign _io_rel_pop_valid_T_1 = s2_valid_pb & _io_rel_pop_valid_T; // @[SourceD.scala:148:28, :167:{35,38}]
assign io_rel_pop_valid_0 = _io_rel_pop_valid_T_1; // @[SourceD.scala:48:7, :167:35]
wire pb_ready = s2_req_prio_0 ? io_pb_pop_ready_0 : io_rel_pop_ready_0; // @[SourceD.scala:48:7, :151:25, :175:21]
wire s3_latch = s2_valid & s3_ready; // @[SourceD.scala:75:22, :78:22, :177:18, :189:27]
wire _s2_valid_T = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27]
wire _s2_valid_T_1 = _s2_valid_T | pb_ready; // @[SourceD.scala:175:21, :183:{27,40}]
assign _s2_valid_T_2 = s2_full & _s2_valid_T_1; // @[SourceD.scala:147:24, :183:{23,40}]
assign s2_valid = _s2_valid_T_2; // @[SourceD.scala:75:22, :183:23]
wire _s2_ready_T = ~s2_full; // @[SourceD.scala:147:24, :184:15]
wire _s2_ready_T_1 = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27, :184:41]
wire _s2_ready_T_2 = _s2_ready_T_1 | pb_ready; // @[SourceD.scala:175:21, :184:{41,54}]
wire _s2_ready_T_3 = s3_ready & _s2_ready_T_2; // @[SourceD.scala:78:22, :184:{37,54}]
assign _s2_ready_T_4 = _s2_ready_T | _s2_ready_T_3; // @[SourceD.scala:184:{15,24,37}]
assign s2_ready = _s2_ready_T_4; // @[SourceD.scala:77:22, :184:24]
reg s3_full; // @[SourceD.scala:190:24]
reg s3_valid_d; // @[SourceD.scala:191:27]
assign d_valid = s3_valid_d; // @[SourceD.scala:191:27, :218:15]
reg [1:0] s3_beat; // @[SourceD.scala:192:26]
wire [1:0] pre_s3_beat = s3_latch ? s2_beat : s3_beat; // @[SourceD.scala:149:26, :189:27, :192:26, :319:24]
reg [1:0] s3_bypass; // @[SourceD.scala:193:28]
reg s3_req_prio_0; // @[SourceD.scala:194:25]
reg s3_req_prio_1; // @[SourceD.scala:194:25]
reg s3_req_prio_2; // @[SourceD.scala:194:25]
reg s3_req_control; // @[SourceD.scala:194:25]
reg [2:0] s3_req_opcode; // @[SourceD.scala:194:25]
reg [2:0] s3_req_param; // @[SourceD.scala:194:25]
reg [2:0] s3_req_size; // @[SourceD.scala:194:25]
assign d_bits_size = s3_req_size; // @[SourceD.scala:194:25, :218:15]
reg [5:0] s3_req_source; // @[SourceD.scala:194:25]
assign d_bits_source = s3_req_source; // @[SourceD.scala:194:25, :218:15]
reg [8:0] s3_req_tag; // @[SourceD.scala:194:25]
reg [5:0] s3_req_offset; // @[SourceD.scala:194:25]
reg [5:0] s3_req_put; // @[SourceD.scala:194:25]
reg [10:0] s3_req_set; // @[SourceD.scala:194:25]
reg [3:0] s3_req_sink; // @[SourceD.scala:194:25]
assign d_bits_sink = s3_req_sink; // @[SourceD.scala:194:25, :218:15]
reg [3:0] s3_req_way; // @[SourceD.scala:194:25]
reg s3_req_bad; // @[SourceD.scala:194:25]
assign d_bits_denied = s3_req_bad; // @[SourceD.scala:194:25, :218:15]
wire pre_s3_req_prio_0 = s3_latch ? s2_req_prio_0 : s3_req_prio_0; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire pre_s3_req_prio_1 = s3_latch ? s2_req_prio_1 : s3_req_prio_1; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire pre_s3_req_prio_2 = s3_latch ? s2_req_prio_2 : s3_req_prio_2; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire pre_s3_req_control = s3_latch ? s2_req_control : s3_req_control; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [2:0] pre_s3_req_opcode = s3_latch ? s2_req_opcode : s3_req_opcode; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [2:0] pre_s3_req_param = s3_latch ? s2_req_param : s3_req_param; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [2:0] pre_s3_req_size = s3_latch ? s2_req_size : s3_req_size; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [5:0] pre_s3_req_source = s3_latch ? s2_req_source : s3_req_source; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [8:0] pre_s3_req_tag = s3_latch ? s2_req_tag : s3_req_tag; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [5:0] pre_s3_req_offset = s3_latch ? s2_req_offset : s3_req_offset; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [5:0] pre_s3_req_put = s3_latch ? s2_req_put : s3_req_put; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [10:0] pre_s3_req_set = s3_latch ? s2_req_set : s3_req_set; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [3:0] pre_s3_req_sink = s3_latch ? s2_req_sink : s3_req_sink; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [3:0] pre_s3_req_way = s3_latch ? s2_req_way : s3_req_way; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire pre_s3_req_bad = s3_latch ? s2_req_bad : s3_req_bad; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24]
wire [2:0] s3_adjusted_opcode = s3_req_bad ? 3'h4 : s3_req_opcode; // @[SourceD.scala:194:25, :195:31]
reg s3_last; // @[SourceD.scala:196:26]
reg [127:0] s3_pdata_data; // @[SourceD.scala:197:27]
reg [15:0] s3_pdata_mask; // @[SourceD.scala:197:27]
reg s3_pdata_corrupt; // @[SourceD.scala:197:27]
reg s3_need_pb; // @[SourceD.scala:198:29]
reg s3_retires; // @[SourceD.scala:199:29]
reg s3_need_r; // @[SourceD.scala:200:28]
wire _s3_acq_T = s3_req_opcode == 3'h6; // @[SourceD.scala:194:25, :202:30]
wire _s3_acq_T_1 = &s3_req_opcode; // @[SourceD.scala:194:25, :202:64]
wire s3_acq = _s3_acq_T | _s3_acq_T_1; // @[SourceD.scala:202:{30,47,64}]
wire [127:0] _s3_bypass_data_T_26; // @[package.scala:45:27]
wire [127:0] s3_bypass_data; // @[SourceD.scala:206:28]
wire _s3_rdata_T = s3_bypass[0]; // @[SourceD.scala:193:28, :208:78]
wire _s3_rdata_T_1 = s3_bypass[1]; // @[SourceD.scala:193:28, :208:78]
wire [63:0] _s3_rdata_T_2 = s3_bypass_data[63:0]; // @[SourceD.scala:206:28, :207:78]
wire [63:0] _s3_rdata_T_3 = s3_bypass_data[127:64]; // @[SourceD.scala:206:28, :207:78]
wire [63:0] _s3_rdata_T_4 = _queue_io_deq_bits_data[63:0]; // @[SourceD.scala:120:21, :207:78]
wire [63:0] _s3_rdata_T_5 = _queue_io_deq_bits_data[127:64]; // @[SourceD.scala:120:21, :207:78]
wire [63:0] _s3_rdata_T_6 = _s3_rdata_T ? _s3_rdata_T_2 : _s3_rdata_T_4; // @[SourceD.scala:207:78, :208:78, :210:75]
wire [63:0] _s3_rdata_T_7 = _s3_rdata_T_1 ? _s3_rdata_T_3 : _s3_rdata_T_5; // @[SourceD.scala:207:78, :208:78, :210:75]
wire [127:0] s3_rdata = {_s3_rdata_T_7, _s3_rdata_T_6}; // @[package.scala:45:27]
assign d_bits_data = s3_rdata; // @[package.scala:45:27]
wire _grant_T = s3_req_param == 3'h2; // @[SourceD.scala:194:25, :214:32]
wire [2:0] grant = {2'h2, ~_grant_T}; // @[SourceD.scala:214:{18,32}]
wire [2:0] resp_opcode_6 = grant; // @[SourceD.scala:214:18, :215:28]
assign io_d_valid_0 = d_valid; // @[SourceD.scala:48:7, :218:15]
wire [2:0] _d_bits_opcode_T; // @[SourceD.scala:222:24]
assign io_d_bits_opcode_0 = d_bits_opcode; // @[SourceD.scala:48:7, :218:15]
wire [1:0] _d_bits_param_T_3; // @[SourceD.scala:223:24]
assign io_d_bits_param_0 = d_bits_param; // @[SourceD.scala:48:7, :218:15]
assign io_d_bits_size_0 = d_bits_size; // @[SourceD.scala:48:7, :218:15]
assign io_d_bits_source_0 = d_bits_source; // @[SourceD.scala:48:7, :218:15]
assign io_d_bits_sink_0 = d_bits_sink; // @[SourceD.scala:48:7, :218:15]
assign io_d_bits_denied_0 = d_bits_denied; // @[SourceD.scala:48:7, :218:15]
assign io_d_bits_data_0 = d_bits_data; // @[SourceD.scala:48:7, :218:15]
wire _d_bits_corrupt_T_1; // @[SourceD.scala:229:32]
assign io_d_bits_corrupt_0 = d_bits_corrupt; // @[SourceD.scala:48:7, :218:15]
wire [7:0][2:0] _GEN_0 = {{3'h4}, {resp_opcode_6}, {3'h2}, {3'h1}, {3'h1}, {3'h1}, {3'h0}, {3'h0}}; // @[SourceD.scala:215:28, :222:24]
assign _d_bits_opcode_T = s3_req_prio_0 ? _GEN_0[s3_req_opcode] : 3'h6; // @[SourceD.scala:194:25, :222:24]
assign d_bits_opcode = _d_bits_opcode_T; // @[SourceD.scala:218:15, :222:24]
wire _d_bits_param_T = s3_req_prio_0 & s3_acq; // @[SourceD.scala:194:25, :202:47, :223:40]
wire _d_bits_param_T_1 = |s3_req_param; // @[SourceD.scala:194:25, :223:68]
wire [1:0] _d_bits_param_T_2 = {1'h0, ~_d_bits_param_T_1}; // @[SourceD.scala:223:{54,68}]
assign _d_bits_param_T_3 = _d_bits_param_T ? _d_bits_param_T_2 : 2'h0; // @[SourceD.scala:223:{24,40,54}]
assign d_bits_param = _d_bits_param_T_3; // @[SourceD.scala:218:15, :223:24]
wire _d_bits_corrupt_T = d_bits_opcode[0]; // @[SourceD.scala:218:15, :229:48]
assign _d_bits_corrupt_T_1 = s3_req_bad & _d_bits_corrupt_T; // @[SourceD.scala:194:25, :229:{32,48}]
assign d_bits_corrupt = _d_bits_corrupt_T_1; // @[SourceD.scala:218:15, :229:32]
wire _queue_io_deq_ready_T = s3_valid & s4_ready; // @[SourceD.scala:76:22, :79:22, :231:34]
wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & s3_need_r; // @[SourceD.scala:200:28, :231:{34,46}]
wire _s3_valid_T = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27]
wire _s3_valid_T_1 = _s3_valid_T | d_ready; // @[SourceD.scala:218:15, :241:{27,39}]
assign _s3_valid_T_2 = s3_full & _s3_valid_T_1; // @[SourceD.scala:190:24, :241:{23,39}]
assign s3_valid = _s3_valid_T_2; // @[SourceD.scala:76:22, :241:23]
wire _s3_ready_T = ~s3_full; // @[SourceD.scala:190:24, :232:11, :242:15]
wire _s3_ready_T_1 = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27, :242:41]
wire _s3_ready_T_2 = _s3_ready_T_1 | d_ready; // @[SourceD.scala:218:15, :242:{41,53}]
wire _s3_ready_T_3 = s4_ready & _s3_ready_T_2; // @[SourceD.scala:79:22, :242:{37,53}]
assign _s3_ready_T_4 = _s3_ready_T | _s3_ready_T_3; // @[SourceD.scala:242:{15,24,37}]
assign s3_ready = _s3_ready_T_4; // @[SourceD.scala:78:22, :242:24]
wire _s4_latch_T = s3_valid & s3_retires; // @[SourceD.scala:76:22, :199:29, :247:27]
wire s4_latch = _s4_latch_T & s4_ready; // @[SourceD.scala:79:22, :247:{27,41}]
reg s4_full; // @[SourceD.scala:248:24]
reg [1:0] s4_beat; // @[SourceD.scala:249:26]
assign io_bs_wadr_bits_beat_0 = s4_beat; // @[SourceD.scala:48:7, :249:26]
wire [1:0] pre_s4_beat = s4_latch ? s3_beat : s4_beat; // @[SourceD.scala:192:26, :247:41, :249:26, :320:24]
reg s4_need_r; // @[SourceD.scala:250:28]
reg s4_need_bs; // @[SourceD.scala:251:29]
reg s4_need_pb; // @[SourceD.scala:252:29]
reg s4_req_prio_0; // @[SourceD.scala:253:25]
reg s4_req_prio_1; // @[SourceD.scala:253:25]
reg s4_req_prio_2; // @[SourceD.scala:253:25]
reg s4_req_control; // @[SourceD.scala:253:25]
reg [2:0] s4_req_opcode; // @[SourceD.scala:253:25]
reg [2:0] s4_req_param; // @[SourceD.scala:253:25]
reg [2:0] s4_req_size; // @[SourceD.scala:253:25]
reg [5:0] s4_req_source; // @[SourceD.scala:253:25]
reg [8:0] s4_req_tag; // @[SourceD.scala:253:25]
reg [5:0] s4_req_offset; // @[SourceD.scala:253:25]
reg [5:0] s4_req_put; // @[SourceD.scala:253:25]
reg [10:0] s4_req_set; // @[SourceD.scala:253:25]
assign io_bs_wadr_bits_set_0 = s4_req_set; // @[SourceD.scala:48:7, :253:25]
reg [3:0] s4_req_sink; // @[SourceD.scala:253:25]
reg [3:0] s4_req_way; // @[SourceD.scala:253:25]
assign io_bs_wadr_bits_way_0 = s4_req_way; // @[SourceD.scala:48:7, :253:25]
reg s4_req_bad; // @[SourceD.scala:253:25]
wire pre_s4_req_prio_0 = s4_latch ? s3_req_prio_0 : s4_req_prio_0; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire pre_s4_req_prio_1 = s4_latch ? s3_req_prio_1 : s4_req_prio_1; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire pre_s4_req_prio_2 = s4_latch ? s3_req_prio_2 : s4_req_prio_2; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire pre_s4_req_control = s4_latch ? s3_req_control : s4_req_control; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [2:0] pre_s4_req_opcode = s4_latch ? s3_req_opcode : s4_req_opcode; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [2:0] pre_s4_req_param = s4_latch ? s3_req_param : s4_req_param; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [2:0] pre_s4_req_size = s4_latch ? s3_req_size : s4_req_size; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [5:0] pre_s4_req_source = s4_latch ? s3_req_source : s4_req_source; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [8:0] pre_s4_req_tag = s4_latch ? s3_req_tag : s4_req_tag; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [5:0] pre_s4_req_offset = s4_latch ? s3_req_offset : s4_req_offset; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [5:0] pre_s4_req_put = s4_latch ? s3_req_put : s4_req_put; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [10:0] pre_s4_req_set = s4_latch ? s3_req_set : s4_req_set; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [3:0] pre_s4_req_sink = s4_latch ? s3_req_sink : s4_req_sink; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire [3:0] pre_s4_req_way = s4_latch ? s3_req_way : s4_req_way; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
wire pre_s4_req_bad = s4_latch ? s3_req_bad : s4_req_bad; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24]
reg [2:0] s4_adjusted_opcode; // @[SourceD.scala:254:37]
reg [127:0] s4_pdata_data; // @[SourceD.scala:255:27]
reg [15:0] s4_pdata_mask; // @[SourceD.scala:255:27]
reg s4_pdata_corrupt; // @[SourceD.scala:255:27]
reg [127:0] s4_rdata; // @[SourceD.scala:256:27]
assign _io_bs_wadr_valid_T = s4_full & s4_need_bs; // @[SourceD.scala:248:24, :251:29, :270:31]
assign io_bs_wadr_valid_0 = _io_bs_wadr_valid_T; // @[SourceD.scala:48:7, :270:31]
wire _io_bs_wadr_bits_mask_T = s4_pdata_mask[0]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_1 = s4_pdata_mask[1]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_2 = s4_pdata_mask[2]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_3 = s4_pdata_mask[3]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_4 = s4_pdata_mask[4]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_5 = s4_pdata_mask[5]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_6 = s4_pdata_mask[6]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_7 = s4_pdata_mask[7]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_8 = s4_pdata_mask[8]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_9 = s4_pdata_mask[9]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_10 = s4_pdata_mask[10]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_11 = s4_pdata_mask[11]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_12 = s4_pdata_mask[12]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_13 = s4_pdata_mask[13]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_14 = s4_pdata_mask[14]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_15 = s4_pdata_mask[15]; // @[SourceD.scala:255:27, :275:45]
wire _io_bs_wadr_bits_mask_T_16 = _io_bs_wadr_bits_mask_T | _io_bs_wadr_bits_mask_T_1; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_17 = _io_bs_wadr_bits_mask_T_16 | _io_bs_wadr_bits_mask_T_2; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_18 = _io_bs_wadr_bits_mask_T_17 | _io_bs_wadr_bits_mask_T_3; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_19 = _io_bs_wadr_bits_mask_T_18 | _io_bs_wadr_bits_mask_T_4; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_20 = _io_bs_wadr_bits_mask_T_19 | _io_bs_wadr_bits_mask_T_5; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_21 = _io_bs_wadr_bits_mask_T_20 | _io_bs_wadr_bits_mask_T_6; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_22 = _io_bs_wadr_bits_mask_T_21 | _io_bs_wadr_bits_mask_T_7; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_23 = _io_bs_wadr_bits_mask_T_8 | _io_bs_wadr_bits_mask_T_9; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_24 = _io_bs_wadr_bits_mask_T_23 | _io_bs_wadr_bits_mask_T_10; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_25 = _io_bs_wadr_bits_mask_T_24 | _io_bs_wadr_bits_mask_T_11; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_26 = _io_bs_wadr_bits_mask_T_25 | _io_bs_wadr_bits_mask_T_12; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_27 = _io_bs_wadr_bits_mask_T_26 | _io_bs_wadr_bits_mask_T_13; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_28 = _io_bs_wadr_bits_mask_T_27 | _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:275:{45,87}]
wire _io_bs_wadr_bits_mask_T_29 = _io_bs_wadr_bits_mask_T_28 | _io_bs_wadr_bits_mask_T_15; // @[SourceD.scala:275:{45,87}]
assign _io_bs_wadr_bits_mask_T_30 = {_io_bs_wadr_bits_mask_T_29, _io_bs_wadr_bits_mask_T_22}; // @[SourceD.scala:275:{30,87}]
assign io_bs_wadr_bits_mask_0 = _io_bs_wadr_bits_mask_T_30; // @[SourceD.scala:48:7, :275:30]
|
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File FPU.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
case class FPUParams(
minFLen: Int = 32,
fLen: Int = 64,
divSqrt: Boolean = true,
sfmaLatency: Int = 3,
dfmaLatency: Int = 4,
fpmuLatency: Int = 2,
ifpuLatency: Int = 2
)
object FPConstants
{
val RM_SZ = 3
val FLAGS_SZ = 5
}
trait HasFPUCtrlSigs {
val ldst = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val swap12 = Bool()
val swap23 = Bool()
val typeTagIn = UInt(2.W)
val typeTagOut = UInt(2.W)
val fromint = Bool()
val toint = Bool()
val fastpipe = Bool()
val fma = Bool()
val div = Bool()
val sqrt = Bool()
val wflags = Bool()
val vec = Bool()
}
class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val inst = Input(Bits(32.W))
val sigs = Output(new FPUCtrlSigs())
})
private val X2 = BitPat.dontCare(2)
val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)
val h: Array[(BitPat, List[BitPat])] =
Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),
FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),
FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),
FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),
FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),
FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),
FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),
FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))
val f: Array[(BitPat, List[BitPat])] =
Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),
FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),
FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),
FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),
FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),
FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))
val d: Array[(BitPat, List[BitPat])] =
Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),
FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),
FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),
FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),
FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),
FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),
FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),
FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))
val fcvt_hd: Array[(BitPat, List[BitPat])] =
Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),
FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))
val vfmv_f_s: Array[(BitPat, List[BitPat])] =
Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))
val insns = ((minFLen, fLen) match {
case (32, 32) => f
case (16, 32) => h ++ f
case (32, 64) => f ++ d
case (16, 64) => h ++ f ++ d ++ fcvt_hd
case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration")
}) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())
val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,
s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val time = Input(UInt(xLen.W))
val inst = Input(Bits(32.W))
val fromint_data = Input(Bits(xLen.W))
val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))
val v_sew = Input(UInt(3.W))
val store_data = Output(Bits(fLen.W))
val toint_data = Output(Bits(xLen.W))
val ll_resp_val = Input(Bool())
val ll_resp_type = Input(Bits(3.W))
val ll_resp_tag = Input(UInt(5.W))
val ll_resp_data = Input(Bits(fLen.W))
val valid = Input(Bool())
val fcsr_rdy = Output(Bool())
val nack_mem = Output(Bool())
val illegal_rm = Output(Bool())
val killx = Input(Bool())
val killm = Input(Bool())
val dec = Output(new FPUCtrlSigs())
val sboard_set = Output(Bool())
val sboard_clr = Output(Bool())
val sboard_clra = Output(UInt(5.W))
val keep_clock_enabled = Input(Bool())
}
class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs
val cp_resp = Decoupled(new FPResult())
}
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val data = Bits((fLen+1).W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val typ = Bits(2.W)
val in1 = Bits(xLen.W)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val fmaCmd = Bits(2.W)
val typ = Bits(2.W)
val fmt = Bits(2.W)
val in1 = Bits((fLen+1).W)
val in2 = Bits((fLen+1).W)
val in3 = Bits((fLen+1).W)
}
case class FType(exp: Int, sig: Int) {
def ieeeWidth = exp + sig
def recodedWidth = ieeeWidth + 1
def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)
def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)
def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR
def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)
def classify(x: UInt) = {
val sign = x(sig + exp)
val code = x(exp + sig - 1, exp + sig - 3)
val codeHi = code(2, 1)
val isSpecial = codeHi === 3.U
val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U
val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn
val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U
val isZero = code === 0.U
val isInf = isSpecial && !code(0)
val isNaN = code.andR
val isSNaN = isNaN && !x(sig-2)
val isQNaN = isNaN && x(sig-2)
Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
isSubnormal && !sign, isZero && !sign, isZero && sign,
isSubnormal && sign, isNormal && sign, isInf && sign)
}
// convert between formats, ignoring rounding, range, NaN
def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {
val sign = x(sig + exp)
val fractIn = x(sig - 2, 0)
val expIn = x(sig + exp - 1, sig - 1)
val fractOut = fractIn << to.sig >> sig
val expOut = {
val expCode = expIn(exp, exp - 2)
val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U
Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))
}
Cat(sign, expOut, fractOut)
}
private def ieeeBundle = {
val expWidth = exp
class IEEEBundle extends Bundle {
val sign = Bool()
val exp = UInt(expWidth.W)
val sig = UInt((ieeeWidth-expWidth-1).W)
}
new IEEEBundle
}
def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)
def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
}
object FType {
val H = new FType(5, 11)
val S = new FType(8, 24)
val D = new FType(11, 53)
val all = List(H, S, D)
}
trait HasFPUParameters {
require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))
val minFLen: Int
val fLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)
def minType = floatTypes.head
def maxType = floatTypes.last
def prevType(t: FType) = floatTypes(typeTag(t) - 1)
def maxExpWidth = maxType.exp
def maxSigWidth = maxType.sig
def typeTag(t: FType) = floatTypes.indexOf(t)
def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U
def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U
// typeTag
def H = typeTagGroup(FType.H)
def S = typeTagGroup(FType.S)
def D = typeTagGroup(FType.D)
def I = typeTag(maxType).U
private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR
private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {
require(xt.ieeeWidth == 2 * yt.ieeeWidth)
val swizzledNaN = Cat(
x(xt.sig + xt.exp, xt.sig + xt.exp - 3),
x(xt.sig - 2, yt.recodedWidth - 1).andR,
x(xt.sig + xt.exp - 5, xt.sig),
y(yt.recodedWidth - 2),
x(xt.sig - 2, yt.recodedWidth - 1),
y(yt.recodedWidth - 1),
y(yt.recodedWidth - 3, 0))
Mux(xt.isNaN(x), swizzledNaN, x)
}
// implement NaN unboxing for FU inputs
def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {
val outType = exactType.getOrElse(maxType)
def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {
val prev =
if (t == minType) {
Seq()
} else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prev = helper(unswizzled, prevT)
val isbox = isBox(x, t)
prev.map(p => (isbox && p._1, p._2))
}
prev :+ (true.B, t.unsafeConvert(x, outType))
}
val (oks, floats) = helper(x, maxType).unzip
if (exactType.isEmpty || floatTypes.size == 1) {
Mux(oks(tag), floats(tag), maxType.qNaN)
} else {
val t = exactType.get
floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)
}
}
// make sure that the redundant bits in the NaN-boxed encoding are consistent
def consistent(x: UInt): Bool = {
def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prevOK = !isBox(x, t) || helper(unswizzled, prevT)
val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR
prevOK && curOK
}
helper(x, maxType)
}
// generate a NaN box from an FU result
def box(x: UInt, t: FType): UInt = {
if (t == maxType) {
x
} else {
val nt = floatTypes(typeTag(t) + 1)
val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)
bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U
}
}
// generate a NaN box from an FU result
def box(x: UInt, tag: UInt): UInt = {
val opts = floatTypes.map(t => box(x, t))
opts(tag)
}
// zap bits that hardfloat thinks are don't-cares, but we do care about
def sanitizeNaN(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
x
} else {
val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)
Mux(t.isNaN(x), maskedNaN, x)
}
}
// implement NaN boxing and recoding for FL*/fmv.*.x
def recode(x: UInt, tag: UInt): UInt = {
def helper(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
t.recode(x)
} else {
val prevT = prevType(t)
box(t.recode(x), t, helper(x, prevT), prevT)
}
}
// fill MSBs of subword loads to emulate a wider load of a NaN-boxed value
val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)
helper(boxes(tag) | x, maxType)
}
// implement NaN unboxing and un-recoding for FS*/fmv.x.*
def ieee(x: UInt, t: FType = maxType): UInt = {
if (typeTag(t) == 0) {
t.ieee(x)
} else {
val unrecoded = t.ieee(x)
val prevT = prevType(t)
val prevRecoded = Cat(
x(prevT.recodedWidth-2),
x(t.sig-1),
x(prevT.recodedWidth-3, 0))
val prevUnrecoded = ieee(prevRecoded, prevT)
Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))
}
}
}
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
val in = new FPInput
val lt = Bool()
val store = Bits(fLen.W)
val toint = Bits(xLen.W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new Output)
})
val in = RegEnable(io.in.bits, io.in.valid)
val valid = RegNext(io.in.valid)
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
dcmp.io.a := in.in1
dcmp.io.b := in.in2
dcmp.io.signaling := !in.rm(1)
val tag = in.typeTagOut
val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))
else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
val toint = WireDefault(toint_ieee)
val intType = WireDefault(in.fmt(0))
io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := 0.U
when (in.rm(0)) {
val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
toint := classify_out | (toint_ieee >> minXLen << minXLen)
intType := false.B
}
when (in.wflags) { // feq/flt/fle, fcvt
toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
io.out.bits.exc := dcmp.io.exceptionFlags
intType := false.B
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
conv.io.signedOut := ~in.typ(0)
toint := conv.io.out
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))
for (i <- 0 until nIntTypes-1) {
val w = minXLen << i
when (cvtType === i.U) {
val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
narrow.io.in := in.in1
narrow.io.roundingMode := in.rm
narrow.io.signedOut := ~in.typ(0)
val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)
val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))
val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
when (invalid) { toint := Cat(conv.io.out >> w, excOut) }
io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))
}
}
}
}
io.out.valid := valid
io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in
}
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new IntToFPInput))
val out = Valid(new FPResult)
})
val in = Pipe(io.in)
val tag = in.bits.typeTagIn
val mux = Wire(new FPResult)
mux.exc := 0.U
mux.data := recode(in.bits.in1, tag)
val intValue = {
val res = WireDefault(in.bits.in1.asSInt)
for (i <- 0 until nIntTypes-1) {
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
}
}
res.asUInt
}
when (in.bits.wflags) { // fcvt
// could be improved for RVD/RVQ with a single variable-position rounding
// unit, rather than N fixed-position ones
val i2fResults = for (t <- floatTypes) yield {
val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
i2f.io.signedIn := ~in.bits.typ(0)
i2f.io.in := intValue
i2f.io.roundingMode := in.bits.rm
i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding
(sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)
}
val (data, exc) = i2fResults.unzip
val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
mux.data := dataPadded(tag)
mux.exc := exc(tag)
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
val lt = Input(Bool()) // from FPToInt
})
val in = Pipe(io.in)
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
val fsgnjMux = Wire(new FPResult)
fsgnjMux.exc := 0.U
fsgnjMux.data := fsgnj
when (in.bits.wflags) { // fmin/fmax
val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
}
val inTag = in.bits.typeTagIn
val outTag = in.bits.typeTagOut
val mux = WireDefault(fsgnjMux)
for (t <- floatTypes.init) {
when (outTag === typeTag(t).U) {
mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))
}
}
when (in.bits.wflags && !in.bits.ren2) { // fcvt
if (floatTypes.size > 1) {
// widening conversions simply canonicalize NaN operands
val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)
fsgnjMux.data := widened
fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4
// narrowing conversions require rounding (for RVQ, this could be
// optimized to use a single variable-position rounding unit, rather
// than two fixed-position ones)
for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {
val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
narrower.io.in := in.bits.in1
narrower.io.roundingMode := in.bits.rm
narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
val narrowed = sanitizeNaN(narrower.io.out, outType)
mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
mux.exc := narrower.io.exceptionFlags
}
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
{
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
require(latency<=2)
val io = IO(new Bundle {
val validin = Input(Bool())
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
val validout = Output(Bool())
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
val valid_stage0 = Wire(Bool())
val roundingMode_stage0 = Wire(UInt(3.W))
val detectTininess_stage0 = Wire(UInt(1.W))
val postmul_regs = if(latency>0) 1 else 0
mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
val round_regs = if(latency==2) 1 else 0
roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
io.validout := Pipe(valid_stage0, false.B, round_regs).valid
roundRawFNToRecFN.io.infiniteExc := false.B
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
class FPUFMAPipe(val latency: Int, val t: FType)
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
require(latency>0)
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
})
val valid = RegNext(io.in.valid)
val in = Reg(new FPInput)
when (io.in.valid) {
val one = 1.U << (t.sig + t.exp - 1)
val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))
val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23
in := io.in.bits
when (cmd_addsub) { in.in2 := one }
when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
}
val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
fma.io.validin := valid
fma.io.op := in.fmaCmd
fma.io.roundingMode := in.rm
fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
fma.io.a := in.in1
fma.io.b := in.in2
fma.io.c := in.in3
val res = Wire(new FPResult)
res.data := sanitizeNaN(fma.io.out, t)
res.exc := fma.io.exceptionFlags
io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
}
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new FPUIO)
val (useClockGating, useDebugROB) = coreParams match {
case r: RocketCoreParams =>
val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
(r.clockGate, sz < 1)
case _ => (false, false)
}
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cp_req.valid
val gated_clock =
if (!useClockGating) clock
else ClockGate(clock, clock_en, "fpu_clock_gate")
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val id_ctrl = WireInit(fp_decoder.io.sigs)
coreParams match { case r: RocketCoreParams => r.vector.map(v => {
val v_decode = v.decoder(p) // Only need to get ren1
v_decode.io.inst := io.inst
v_decode.io.vconfig := DontCare // core deals with this
when (v_decode.io.legal && v_decode.io.read_frs1) {
id_ctrl.ren1 := true.B
id_ctrl.swap12 := false.B
id_ctrl.toint := true.B
id_ctrl.typeTagIn := I
id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
}
when (v_decode.io.write_frd) { id_ctrl.wen := true.B }
})}
val ex_reg_valid = RegNext(io.valid, false.B)
val ex_reg_inst = RegEnable(io.inst, io.valid)
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt()))
// load/vector response
val load_wb = RegNext(io.ll_resp_val)
val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)
val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)
val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)
class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid
val ex_cp_valid = io.cp_req.fire
val mem_cp_valid = RegNext(ex_cp_valid, false.B)
val wb_cp_valid = RegNext(mem_cp_valid, false.B)
val mem_reg_valid = RegInit(false.B)
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
// Kill X-stage instruction if M-stage is killed. This prevents it from
// speculatively being sent to the div-sqrt unit, which can cause priority
// inversion for two back-to-back divides, the first of which is killed.
val killx = io.killx || mem_reg_valid && killm
mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
io.cp_resp.valid := false.B
io.cp_resp.bits.data := 0.U
io.cp_resp.bits.exc := DontCare
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// CoreMonitorBundle to monitor fp register file writes
val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))
frfWriteBundle.foreach { i =>
i.clock := clock
i.reset := reset
i.hartid := io.hartid
i.timer := io.time(31,0)
i.valid := false.B
i.wrenx := false.B
i.wrenf := false.B
i.excpt := false.B
}
// regfile
val regfile = Mem(32, Bits((fLen+1).W))
when (load_wb) {
val wdata = recode(load_wb_data, load_wb_typeTag)
regfile(load_wb_tag) := wdata
assert(consistent(wdata))
if (enableCommitLog)
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))
if (useDebugROB)
DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))
frfWriteBundle(0).wrdst := load_wb_tag
frfWriteBundle(0).wrenf := true.B
frfWriteBundle(0).wrdata := ieee(wdata)
}
val ex_rs = ex_ra.map(a => regfile(a))
when (io.valid) {
when (id_ctrl.ren1) {
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }
}
when (id_ctrl.ren2) {
when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }
when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }
}
when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }
}
val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))
def fuInput(minT: Option[FType]): FPInput = {
val req = Wire(new FPInput)
val tag = ex_ctrl.typeTagIn
req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
req.rm := ex_rm
req.in1 := unbox(ex_rs(0), tag, minT)
req.in2 := unbox(ex_rs(1), tag, minT)
req.in3 := unbox(ex_rs(2), tag, minT)
req.typ := ex_reg_inst(21,20)
req.fmt := ex_reg_inst(26,25)
req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))
when (ex_cp_valid) {
req := io.cp_req.bits
when (io.cp_req.bits.swap12) {
req.in1 := io.cp_req.bits.in2
req.in2 := io.cp_req.bits.in1
}
when (io.cp_req.bits.swap23) {
req.in2 := io.cp_req.bits.in3
req.in3 := io.cp_req.bits.in2
}
}
req
}
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
io.store_data := fpiu.io.out.bits.store
io.toint_data := fpiu.io.out.bits.toint
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
io.cp_resp.bits.data := fpiu.io.out.bits.toint
io.cp_resp.valid := true.B
}
val ifpu = Module(new IntToFP(cfg.ifpuLatency))
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
ifpu.io.in.bits := fpiu.io.in.bits
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
val fpmu = Module(new FPToFP(cfg.fpmuLatency))
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt_wen = WireDefault(false.B)
val divSqrt_inFlight = WireDefault(false.B)
val divSqrt_waddr = Reg(UInt(5.W))
val divSqrt_cp = Reg(Bool())
val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
val divSqrt_wdata = Wire(UInt((fLen+1).W))
val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
divSqrt_typeTag := DontCare
divSqrt_wdata := DontCare
divSqrt_flags := DontCare
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++
(fLen > 32).option({
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D
dfma.io.in.bits := fuInput(Some(dfma.t))
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)
}) ++
(minFLen == 16).option({
val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))
hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H
hfma.io.in.bits := fuInput(Some(hfma.t))
Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)
})
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
require(pipes.forall(_.lat >= offset))
pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)
}
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
class WBInfo extends Bundle {
val rd = UInt(5.W)
val typeTag = UInt(log2Up(floatTypes.size).W)
val cp = Bool()
val pipeid = UInt(log2Ceil(pipes.size).W)
}
val wen = RegInit(0.U((maxLatency-1).W))
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
}
wen := wen >> 1
when (mem_wen) {
when (!killm) {
wen := wen >> 1 | memLatencyMask
}
for (i <- 0 until maxLatency-1) {
when (!write_port_busy && memLatencyMask(i)) {
wbInfo(i).cp := mem_cp_valid
wbInfo(i).typeTag := mem_ctrl.typeTagOut
wbInfo(i).pipeid := pipeid(mem_ctrl)
wbInfo(i).rd := mem_reg_inst(11,7)
}
}
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,
s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
// Avoid structural hazards and nacking of external requests
// toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
io.fcsr_flags.bits :=
Mux(wb_toint_valid, wb_toint_exc, 0.U) |
Mux(divSqrt_wen, divSqrt_flags, 0.U) |
Mux(wen(0), wexc, 0.U)
val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
io.dec <> id_ctrl
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U
if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
when (divSqrt_inValid) {
divSqrt_waddr := mem_reg_inst(11,7)
divSqrt_cp := mem_cp_valid
}
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) {
val tag = mem_ctrl.typeTagOut
val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }
divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight
when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {
divSqrt_wen := !divSqrt_killed
divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)
divSqrt_flags := divSqrt.io.exceptionFlags
divSqrt_typeTag := typeTag(t).U
}
}
when (divSqrt_killed) { divSqrt_inFlight := false.B }
} else {
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }
}
// gate the clock
clock_en_reg := !useClockGating.B ||
io.keep_clock_enabled || // chicken bit
io.valid || // ID stage
req_valid || // EX stage
mem_reg_valid || mem_cp_valid || // MEM stage
wb_reg_valid || wb_cp_valid || // WB stage
wen.orR || divSqrt_inFlight || // post-WB stage
io.ll_resp_val // load writeback
} // leaving gated-clock domain
val fpuImpl = withClock (gated_clock) { new FPUImpl }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FPU_$label", "Core;;" + desc)
}
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File fpu.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
package boom.v3.exu
import chisel3._
import chisel3.util._
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile.FPConstants._
import freechips.rocketchip.tile.{FPUCtrlSigs, HasFPUParameters}
import freechips.rocketchip.tile
import freechips.rocketchip.rocket
import freechips.rocketchip.util.uintToBitPat
import boom.v3.common._
import boom.v3.util.{ImmGenRm, ImmGenTyp}
/**
* FP Decoder for the FPU
*
* TODO get rid of this decoder and move into the Decode stage? Or the RRd stage?
* most of these signals are already created, just need to be translated
* to the Rocket FPU-speak
*/
class UOPCodeFPUDecoder(implicit p: Parameters) extends BoomModule with HasFPUParameters
{
val io = IO(new Bundle {
val uopc = Input(Bits(UOPC_SZ.W))
val sigs = Output(new FPUCtrlSigs())
})
// TODO change N,Y,X to BitPat("b1"), BitPat("b0"), and BitPat("b?")
val N = false.B
val Y = true.B
val X = false.B
val default: List[BitPat] = List(X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X)
val f_table: Array[(BitPat, List[BitPat])] =
// Note: not all of these signals are used or necessary, but we're
// constrained by the need to fit the rocket.FPU units' ctrl signals.
// swap12 fma
// | swap32 | div
// | | typeTagIn | | sqrt
// ldst | | | typeTagOut | | wflags
// | wen | | | | from_int | | |
// | | ren1 | | | | | to_int | | |
// | | | ren2 | | | | | | fastpipe |
// | | | | ren3 | | | | | | | | | |
// | | | | | | | | | | | | | | | |
Array(
BitPat(uopFCLASS_S) -> List(X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,N),
BitPat(uopFMV_W_X) -> List(X,X,N,N,N, X,X,S,D,Y,N,N, N,N,N,N),
BitPat(uopFMV_X_W) -> List(X,X,Y,N,N, N,X,D,S,N,Y,N, N,N,N,N),
BitPat(uopFCVT_S_X) -> List(X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y),
BitPat(uopFCVT_X_S) -> List(X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y),
BitPat(uopCMPR_S) -> List(X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y),
BitPat(uopFSGNJ_S) -> List(X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N),
BitPat(uopFMINMAX_S)-> List(X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,Y),
BitPat(uopFADD_S) -> List(X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFSUB_S) -> List(X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFMUL_S) -> List(X,X,Y,Y,N, N,N,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFMADD_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFMSUB_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFNMADD_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFNMSUB_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y)
)
val d_table: Array[(BitPat, List[BitPat])] =
Array(
BitPat(uopFCLASS_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N),
BitPat(uopFMV_D_X) -> List(X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,N),
BitPat(uopFMV_X_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N),
BitPat(uopFCVT_S_D) -> List(X,X,Y,N,N, N,X,D,S,N,N,Y, N,N,N,Y),
BitPat(uopFCVT_D_S) -> List(X,X,Y,N,N, N,X,S,D,N,N,Y, N,N,N,Y),
BitPat(uopFCVT_D_X) -> List(X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y),
BitPat(uopFCVT_X_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y),
BitPat(uopCMPR_D) -> List(X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y),
BitPat(uopFSGNJ_D) -> List(X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N),
BitPat(uopFMINMAX_D)-> List(X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,Y),
BitPat(uopFADD_D) -> List(X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFSUB_D) -> List(X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFMUL_D) -> List(X,X,Y,Y,N, N,N,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFMADD_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFMSUB_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFNMADD_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFNMSUB_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y)
)
// val insns = fLen match {
// case 32 => f_table
// case 64 => f_table ++ d_table
// }
val insns = f_table ++ d_table
val decoder = rocket.DecodeLogic(io.uopc, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma,
s.div, s.sqrt, s.wflags)
sigs zip decoder map {case(s,d) => s := d}
s.vec := false.B
}
/**
* FP fused multiple add decoder for the FPU
*/
class FMADecoder extends Module
{
val io = IO(new Bundle {
val uopc = Input(UInt(UOPC_SZ.W))
val cmd = Output(UInt(2.W))
})
val default: List[BitPat] = List(BitPat("b??"))
val table: Array[(BitPat, List[BitPat])] =
Array(
BitPat(uopFADD_S) -> List(BitPat("b00")),
BitPat(uopFSUB_S) -> List(BitPat("b01")),
BitPat(uopFMUL_S) -> List(BitPat("b00")),
BitPat(uopFMADD_S) -> List(BitPat("b00")),
BitPat(uopFMSUB_S) -> List(BitPat("b01")),
BitPat(uopFNMADD_S) -> List(BitPat("b11")),
BitPat(uopFNMSUB_S) -> List(BitPat("b10")),
BitPat(uopFADD_D) -> List(BitPat("b00")),
BitPat(uopFSUB_D) -> List(BitPat("b01")),
BitPat(uopFMUL_D) -> List(BitPat("b00")),
BitPat(uopFMADD_D) -> List(BitPat("b00")),
BitPat(uopFMSUB_D) -> List(BitPat("b01")),
BitPat(uopFNMADD_D) -> List(BitPat("b11")),
BitPat(uopFNMSUB_D) -> List(BitPat("b10"))
)
val decoder = rocket.DecodeLogic(io.uopc, default, table)
val (cmd: UInt) :: Nil = decoder
io.cmd := cmd
}
/**
* Bundle representing data to be sent to the FPU
*/
class FpuReq()(implicit p: Parameters) extends BoomBundle
{
val uop = new MicroOp()
val rs1_data = Bits(65.W)
val rs2_data = Bits(65.W)
val rs3_data = Bits(65.W)
val fcsr_rm = Bits(tile.FPConstants.RM_SZ.W)
}
/**
* FPU unit that wraps the RocketChip FPU units (which in turn wrap hardfloat)
*/
class FPU(implicit p: Parameters) extends BoomModule with tile.HasFPUParameters
{
val io = IO(new Bundle {
val req = Flipped(new ValidIO(new FpuReq))
val resp = new ValidIO(new ExeUnitResp(65))
})
io.resp.bits := DontCare
// all FP units are padded out to the same latency for easy scheduling of the write port
val fpu_latency = dfmaLatency
val io_req = io.req.bits
val fp_decoder = Module(new UOPCodeFPUDecoder)
fp_decoder.io.uopc := io_req.uop.uopc
val fp_ctrl = fp_decoder.io.sigs
val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io_req.fcsr_rm, ImmGenRm(io_req.uop.imm_packed))
def fuInput(minT: Option[tile.FType]): tile.FPInput = {
val req = Wire(new tile.FPInput)
val tag = fp_ctrl.typeTagIn
req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl
req.rm := fp_rm
req.in1 := unbox(io_req.rs1_data, tag, minT)
req.in2 := unbox(io_req.rs2_data, tag, minT)
req.in3 := unbox(io_req.rs3_data, tag, minT)
when (fp_ctrl.swap23) { req.in3 := req.in2 }
req.typ := ImmGenTyp(io_req.uop.imm_packed)
req.fmt := Mux(tag === S, 0.U, 1.U) // TODO support Zfh and avoid special-case below
when (io_req.uop.uopc === uopFMV_X_W) {
req.fmt := 0.U
}
val fma_decoder = Module(new FMADecoder)
fma_decoder.io.uopc := io_req.uop.uopc
req.fmaCmd := fma_decoder.io.cmd // ex_reg_inst(3,2) | (!fp_ctrl.ren3 && ex_reg_inst(27))
req
}
val dfma = Module(new tile.FPUFMAPipe(latency = fpu_latency, t = tile.FType.D))
dfma.io.in.valid := io.req.valid && fp_ctrl.fma && (fp_ctrl.typeTagOut === D)
dfma.io.in.bits := fuInput(Some(dfma.t))
val sfma = Module(new tile.FPUFMAPipe(latency = fpu_latency, t = tile.FType.S))
sfma.io.in.valid := io.req.valid && fp_ctrl.fma && (fp_ctrl.typeTagOut === S)
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new tile.FPToInt)
fpiu.io.in.valid := io.req.valid && (fp_ctrl.toint || (fp_ctrl.fastpipe && fp_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
val fpiu_out = Pipe(RegNext(fpiu.io.in.valid && !fp_ctrl.fastpipe),
fpiu.io.out.bits, fpu_latency-1)
val fpiu_result = Wire(new tile.FPResult)
fpiu_result.data := fpiu_out.bits.toint
fpiu_result.exc := fpiu_out.bits.exc
val fpmu = Module(new tile.FPToFP(fpu_latency)) // latency 2 for rocket
fpmu.io.in.valid := io.req.valid && fp_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val fpmu_double = Pipe(io.req.valid && fp_ctrl.fastpipe, fp_ctrl.typeTagOut === D, fpu_latency).bits
// Response (all FP units have been padded out to the same latency)
io.resp.valid := fpiu_out.valid ||
fpmu.io.out.valid ||
sfma.io.out.valid ||
dfma.io.out.valid
val fpu_out_data =
Mux(dfma.io.out.valid, box(dfma.io.out.bits.data, true.B),
Mux(sfma.io.out.valid, box(sfma.io.out.bits.data, false.B),
Mux(fpiu_out.valid, fpiu_result.data,
box(fpmu.io.out.bits.data, fpmu_double))))
val fpu_out_exc =
Mux(dfma.io.out.valid, dfma.io.out.bits.exc,
Mux(sfma.io.out.valid, sfma.io.out.bits.exc,
Mux(fpiu_out.valid, fpiu_result.exc,
fpmu.io.out.bits.exc)))
io.resp.bits.data := fpu_out_data
io.resp.bits.fflags.valid := io.resp.valid
io.resp.bits.fflags.bits.flags := fpu_out_exc
}
|
module FPU_3( // @[fpu.scala:170:7]
input clock, // @[fpu.scala:170:7]
input reset, // @[fpu.scala:170:7]
input io_req_valid, // @[fpu.scala:172:14]
input [6:0] io_req_bits_uop_uopc, // @[fpu.scala:172:14]
input [31:0] io_req_bits_uop_inst, // @[fpu.scala:172:14]
input [31:0] io_req_bits_uop_debug_inst, // @[fpu.scala:172:14]
input io_req_bits_uop_is_rvc, // @[fpu.scala:172:14]
input [39:0] io_req_bits_uop_debug_pc, // @[fpu.scala:172:14]
input [2:0] io_req_bits_uop_iq_type, // @[fpu.scala:172:14]
input [9:0] io_req_bits_uop_fu_code, // @[fpu.scala:172:14]
input [3:0] io_req_bits_uop_ctrl_br_type, // @[fpu.scala:172:14]
input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[fpu.scala:172:14]
input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[fpu.scala:172:14]
input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[fpu.scala:172:14]
input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[fpu.scala:172:14]
input io_req_bits_uop_ctrl_fcn_dw, // @[fpu.scala:172:14]
input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[fpu.scala:172:14]
input io_req_bits_uop_ctrl_is_load, // @[fpu.scala:172:14]
input io_req_bits_uop_ctrl_is_sta, // @[fpu.scala:172:14]
input io_req_bits_uop_ctrl_is_std, // @[fpu.scala:172:14]
input [1:0] io_req_bits_uop_iw_state, // @[fpu.scala:172:14]
input io_req_bits_uop_iw_p1_poisoned, // @[fpu.scala:172:14]
input io_req_bits_uop_iw_p2_poisoned, // @[fpu.scala:172:14]
input io_req_bits_uop_is_br, // @[fpu.scala:172:14]
input io_req_bits_uop_is_jalr, // @[fpu.scala:172:14]
input io_req_bits_uop_is_jal, // @[fpu.scala:172:14]
input io_req_bits_uop_is_sfb, // @[fpu.scala:172:14]
input [15:0] io_req_bits_uop_br_mask, // @[fpu.scala:172:14]
input [3:0] io_req_bits_uop_br_tag, // @[fpu.scala:172:14]
input [4:0] io_req_bits_uop_ftq_idx, // @[fpu.scala:172:14]
input io_req_bits_uop_edge_inst, // @[fpu.scala:172:14]
input [5:0] io_req_bits_uop_pc_lob, // @[fpu.scala:172:14]
input io_req_bits_uop_taken, // @[fpu.scala:172:14]
input [19:0] io_req_bits_uop_imm_packed, // @[fpu.scala:172:14]
input [11:0] io_req_bits_uop_csr_addr, // @[fpu.scala:172:14]
input [6:0] io_req_bits_uop_rob_idx, // @[fpu.scala:172:14]
input [4:0] io_req_bits_uop_ldq_idx, // @[fpu.scala:172:14]
input [4:0] io_req_bits_uop_stq_idx, // @[fpu.scala:172:14]
input [1:0] io_req_bits_uop_rxq_idx, // @[fpu.scala:172:14]
input [6:0] io_req_bits_uop_pdst, // @[fpu.scala:172:14]
input [6:0] io_req_bits_uop_prs1, // @[fpu.scala:172:14]
input [6:0] io_req_bits_uop_prs2, // @[fpu.scala:172:14]
input [6:0] io_req_bits_uop_prs3, // @[fpu.scala:172:14]
input [4:0] io_req_bits_uop_ppred, // @[fpu.scala:172:14]
input io_req_bits_uop_prs1_busy, // @[fpu.scala:172:14]
input io_req_bits_uop_prs2_busy, // @[fpu.scala:172:14]
input io_req_bits_uop_prs3_busy, // @[fpu.scala:172:14]
input io_req_bits_uop_ppred_busy, // @[fpu.scala:172:14]
input [6:0] io_req_bits_uop_stale_pdst, // @[fpu.scala:172:14]
input io_req_bits_uop_exception, // @[fpu.scala:172:14]
input [63:0] io_req_bits_uop_exc_cause, // @[fpu.scala:172:14]
input io_req_bits_uop_bypassable, // @[fpu.scala:172:14]
input [4:0] io_req_bits_uop_mem_cmd, // @[fpu.scala:172:14]
input [1:0] io_req_bits_uop_mem_size, // @[fpu.scala:172:14]
input io_req_bits_uop_mem_signed, // @[fpu.scala:172:14]
input io_req_bits_uop_is_fence, // @[fpu.scala:172:14]
input io_req_bits_uop_is_fencei, // @[fpu.scala:172:14]
input io_req_bits_uop_is_amo, // @[fpu.scala:172:14]
input io_req_bits_uop_uses_ldq, // @[fpu.scala:172:14]
input io_req_bits_uop_uses_stq, // @[fpu.scala:172:14]
input io_req_bits_uop_is_sys_pc2epc, // @[fpu.scala:172:14]
input io_req_bits_uop_is_unique, // @[fpu.scala:172:14]
input io_req_bits_uop_flush_on_commit, // @[fpu.scala:172:14]
input io_req_bits_uop_ldst_is_rs1, // @[fpu.scala:172:14]
input [5:0] io_req_bits_uop_ldst, // @[fpu.scala:172:14]
input [5:0] io_req_bits_uop_lrs1, // @[fpu.scala:172:14]
input [5:0] io_req_bits_uop_lrs2, // @[fpu.scala:172:14]
input [5:0] io_req_bits_uop_lrs3, // @[fpu.scala:172:14]
input io_req_bits_uop_ldst_val, // @[fpu.scala:172:14]
input [1:0] io_req_bits_uop_dst_rtype, // @[fpu.scala:172:14]
input [1:0] io_req_bits_uop_lrs1_rtype, // @[fpu.scala:172:14]
input [1:0] io_req_bits_uop_lrs2_rtype, // @[fpu.scala:172:14]
input io_req_bits_uop_frs3_en, // @[fpu.scala:172:14]
input io_req_bits_uop_fp_val, // @[fpu.scala:172:14]
input io_req_bits_uop_fp_single, // @[fpu.scala:172:14]
input io_req_bits_uop_xcpt_pf_if, // @[fpu.scala:172:14]
input io_req_bits_uop_xcpt_ae_if, // @[fpu.scala:172:14]
input io_req_bits_uop_xcpt_ma_if, // @[fpu.scala:172:14]
input io_req_bits_uop_bp_debug_if, // @[fpu.scala:172:14]
input io_req_bits_uop_bp_xcpt_if, // @[fpu.scala:172:14]
input [1:0] io_req_bits_uop_debug_fsrc, // @[fpu.scala:172:14]
input [1:0] io_req_bits_uop_debug_tsrc, // @[fpu.scala:172:14]
input [64:0] io_req_bits_rs1_data, // @[fpu.scala:172:14]
input [64:0] io_req_bits_rs2_data, // @[fpu.scala:172:14]
input [64:0] io_req_bits_rs3_data, // @[fpu.scala:172:14]
input [2:0] io_req_bits_fcsr_rm, // @[fpu.scala:172:14]
output [64:0] io_resp_bits_data, // @[fpu.scala:172:14]
output io_resp_bits_fflags_valid, // @[fpu.scala:172:14]
output [4:0] io_resp_bits_fflags_bits_flags // @[fpu.scala:172:14]
);
wire io_resp_valid; // @[fpu.scala:170:7]
wire _fpmu_io_out_valid; // @[fpu.scala:225:20]
wire [64:0] _fpmu_io_out_bits_data; // @[fpu.scala:225:20]
wire [4:0] _fpmu_io_out_bits_exc; // @[fpu.scala:225:20]
wire _fpiu_io_out_bits_in_ldst; // @[fpu.scala:216:20]
wire _fpiu_io_out_bits_in_wen; // @[fpu.scala:216:20]
wire _fpiu_io_out_bits_in_ren1; // @[fpu.scala:216:20]
wire _fpiu_io_out_bits_in_ren2; // @[fpu.scala:216:20]
wire _fpiu_io_out_bits_in_ren3; // @[fpu.scala:216:20]
wire _fpiu_io_out_bits_in_swap12; // @[fpu.scala:216:20]
wire _fpiu_io_out_bits_in_swap23; // @[fpu.scala:216:20]
wire [1:0] _fpiu_io_out_bits_in_typeTagIn; // @[fpu.scala:216:20]
wire [1:0] _fpiu_io_out_bits_in_typeTagOut; // @[fpu.scala:216:20]
wire _fpiu_io_out_bits_in_fromint; // @[fpu.scala:216:20]
wire _fpiu_io_out_bits_in_toint; // @[fpu.scala:216:20]
wire _fpiu_io_out_bits_in_fastpipe; // @[fpu.scala:216:20]
wire _fpiu_io_out_bits_in_fma; // @[fpu.scala:216:20]
wire _fpiu_io_out_bits_in_div; // @[fpu.scala:216:20]
wire _fpiu_io_out_bits_in_sqrt; // @[fpu.scala:216:20]
wire _fpiu_io_out_bits_in_wflags; // @[fpu.scala:216:20]
wire [2:0] _fpiu_io_out_bits_in_rm; // @[fpu.scala:216:20]
wire [1:0] _fpiu_io_out_bits_in_fmaCmd; // @[fpu.scala:216:20]
wire [1:0] _fpiu_io_out_bits_in_typ; // @[fpu.scala:216:20]
wire [1:0] _fpiu_io_out_bits_in_fmt; // @[fpu.scala:216:20]
wire [64:0] _fpiu_io_out_bits_in_in1; // @[fpu.scala:216:20]
wire [64:0] _fpiu_io_out_bits_in_in2; // @[fpu.scala:216:20]
wire [64:0] _fpiu_io_out_bits_in_in3; // @[fpu.scala:216:20]
wire _fpiu_io_out_bits_lt; // @[fpu.scala:216:20]
wire [63:0] _fpiu_io_out_bits_store; // @[fpu.scala:216:20]
wire [63:0] _fpiu_io_out_bits_toint; // @[fpu.scala:216:20]
wire [4:0] _fpiu_io_out_bits_exc; // @[fpu.scala:216:20]
wire _sfma_io_out_valid; // @[fpu.scala:212:20]
wire [64:0] _sfma_io_out_bits_data; // @[fpu.scala:212:20]
wire [4:0] _sfma_io_out_bits_exc; // @[fpu.scala:212:20]
wire _dfma_io_out_valid; // @[fpu.scala:208:20]
wire [64:0] _dfma_io_out_bits_data; // @[fpu.scala:208:20]
wire [4:0] _dfma_io_out_bits_exc; // @[fpu.scala:208:20]
wire _fp_decoder_io_sigs_ldst; // @[fpu.scala:182:26]
wire _fp_decoder_io_sigs_wen; // @[fpu.scala:182:26]
wire _fp_decoder_io_sigs_ren1; // @[fpu.scala:182:26]
wire _fp_decoder_io_sigs_ren2; // @[fpu.scala:182:26]
wire _fp_decoder_io_sigs_ren3; // @[fpu.scala:182:26]
wire _fp_decoder_io_sigs_swap12; // @[fpu.scala:182:26]
wire _fp_decoder_io_sigs_swap23; // @[fpu.scala:182:26]
wire [1:0] _fp_decoder_io_sigs_typeTagIn; // @[fpu.scala:182:26]
wire [1:0] _fp_decoder_io_sigs_typeTagOut; // @[fpu.scala:182:26]
wire _fp_decoder_io_sigs_fromint; // @[fpu.scala:182:26]
wire _fp_decoder_io_sigs_toint; // @[fpu.scala:182:26]
wire _fp_decoder_io_sigs_fastpipe; // @[fpu.scala:182:26]
wire _fp_decoder_io_sigs_fma; // @[fpu.scala:182:26]
wire _fp_decoder_io_sigs_div; // @[fpu.scala:182:26]
wire _fp_decoder_io_sigs_sqrt; // @[fpu.scala:182:26]
wire _fp_decoder_io_sigs_wflags; // @[fpu.scala:182:26]
wire io_req_valid_0 = io_req_valid; // @[fpu.scala:170:7]
wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[fpu.scala:170:7]
wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[fpu.scala:170:7]
wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[fpu.scala:170:7]
wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[fpu.scala:170:7]
wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[fpu.scala:170:7]
wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[fpu.scala:170:7]
wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[fpu.scala:170:7]
wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[fpu.scala:170:7]
wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[fpu.scala:170:7]
wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[fpu.scala:170:7]
wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[fpu.scala:170:7]
wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[fpu.scala:170:7]
wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[fpu.scala:170:7]
wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[fpu.scala:170:7]
wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[fpu.scala:170:7]
wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[fpu.scala:170:7]
wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[fpu.scala:170:7]
wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[fpu.scala:170:7]
wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[fpu.scala:170:7]
wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[fpu.scala:170:7]
wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[fpu.scala:170:7]
wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[fpu.scala:170:7]
wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[fpu.scala:170:7]
wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[fpu.scala:170:7]
wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[fpu.scala:170:7]
wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[fpu.scala:170:7]
wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[fpu.scala:170:7]
wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[fpu.scala:170:7]
wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[fpu.scala:170:7]
wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[fpu.scala:170:7]
wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[fpu.scala:170:7]
wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[fpu.scala:170:7]
wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[fpu.scala:170:7]
wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[fpu.scala:170:7]
wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[fpu.scala:170:7]
wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[fpu.scala:170:7]
wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[fpu.scala:170:7]
wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[fpu.scala:170:7]
wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[fpu.scala:170:7]
wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[fpu.scala:170:7]
wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[fpu.scala:170:7]
wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[fpu.scala:170:7]
wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[fpu.scala:170:7]
wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[fpu.scala:170:7]
wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[fpu.scala:170:7]
wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[fpu.scala:170:7]
wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[fpu.scala:170:7]
wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[fpu.scala:170:7]
wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[fpu.scala:170:7]
wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[fpu.scala:170:7]
wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[fpu.scala:170:7]
wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[fpu.scala:170:7]
wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[fpu.scala:170:7]
wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[fpu.scala:170:7]
wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[fpu.scala:170:7]
wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[fpu.scala:170:7]
wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[fpu.scala:170:7]
wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[fpu.scala:170:7]
wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[fpu.scala:170:7]
wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[fpu.scala:170:7]
wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[fpu.scala:170:7]
wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[fpu.scala:170:7]
wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[fpu.scala:170:7]
wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[fpu.scala:170:7]
wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[fpu.scala:170:7]
wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[fpu.scala:170:7]
wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[fpu.scala:170:7]
wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[fpu.scala:170:7]
wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[fpu.scala:170:7]
wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[fpu.scala:170:7]
wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[fpu.scala:170:7]
wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[fpu.scala:170:7]
wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[fpu.scala:170:7]
wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[fpu.scala:170:7]
wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[fpu.scala:170:7]
wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[fpu.scala:170:7]
wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[fpu.scala:170:7]
wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[fpu.scala:170:7]
wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[fpu.scala:170:7]
wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[fpu.scala:170:7]
wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[fpu.scala:170:7]
wire [64:0] io_req_bits_rs3_data_0 = io_req_bits_rs3_data; // @[fpu.scala:170:7]
wire [2:0] io_req_bits_fcsr_rm_0 = io_req_bits_fcsr_rm; // @[fpu.scala:170:7]
wire [64:0] _dfma_io_in_bits_req_in1_T = 65'h0; // @[FPU.scala:372:31]
wire [64:0] _dfma_io_in_bits_req_in2_T = 65'h0; // @[FPU.scala:372:31]
wire [64:0] _dfma_io_in_bits_req_in3_T = 65'h0; // @[FPU.scala:372:31]
wire [4:0] fpu_out_data_opts_bigger_swizzledNaN_hi_hi = 5'h1F; // @[FPU.scala:336:26]
wire [4:0] fpu_out_data_opts_bigger_swizzledNaN_hi_hi_1 = 5'h1F; // @[FPU.scala:336:26]
wire [4:0] fpu_out_data_opts_bigger_swizzledNaN_hi_hi_2 = 5'h1F; // @[FPU.scala:336:26]
wire _fpu_out_data_opts_bigger_swizzledNaN_T = 1'h1; // @[FPU.scala:338:42]
wire _fpu_out_data_opts_bigger_T = 1'h1; // @[FPU.scala:249:56]
wire _fpu_out_data_T = 1'h1; // @[package.scala:39:86]
wire _fpu_out_data_opts_bigger_swizzledNaN_T_4 = 1'h1; // @[FPU.scala:338:42]
wire _fpu_out_data_opts_bigger_T_1 = 1'h1; // @[FPU.scala:249:56]
wire _fpu_out_data_opts_bigger_swizzledNaN_T_8 = 1'h1; // @[FPU.scala:338:42]
wire _fpu_out_data_opts_bigger_T_2 = 1'h1; // @[FPU.scala:249:56]
wire [63:0] io_resp_bits_uop_exc_cause = 64'h0; // @[fpu.scala:170:7]
wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[fpu.scala:170:7]
wire [11:0] io_resp_bits_uop_csr_addr = 12'h0; // @[fpu.scala:170:7]
wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[fpu.scala:170:7]
wire [19:0] io_resp_bits_uop_imm_packed = 20'h0; // @[fpu.scala:170:7]
wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[fpu.scala:170:7]
wire [5:0] io_resp_bits_uop_pc_lob = 6'h0; // @[fpu.scala:170:7]
wire [5:0] io_resp_bits_uop_ldst = 6'h0; // @[fpu.scala:170:7]
wire [5:0] io_resp_bits_uop_lrs1 = 6'h0; // @[fpu.scala:170:7]
wire [5:0] io_resp_bits_uop_lrs2 = 6'h0; // @[fpu.scala:170:7]
wire [5:0] io_resp_bits_uop_lrs3 = 6'h0; // @[fpu.scala:170:7]
wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[fpu.scala:170:7]
wire [5:0] io_resp_bits_fflags_bits_uop_ldst = 6'h0; // @[fpu.scala:170:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[fpu.scala:170:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[fpu.scala:170:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[fpu.scala:170:7]
wire [15:0] io_resp_bits_uop_br_mask = 16'h0; // @[fpu.scala:170:7]
wire [15:0] io_resp_bits_fflags_bits_uop_br_mask = 16'h0; // @[fpu.scala:170:7]
wire [4:0] io_resp_bits_uop_ctrl_op_fcn = 5'h0; // @[fpu.scala:170:7]
wire [4:0] io_resp_bits_uop_ftq_idx = 5'h0; // @[fpu.scala:170:7]
wire [4:0] io_resp_bits_uop_ldq_idx = 5'h0; // @[fpu.scala:170:7]
wire [4:0] io_resp_bits_uop_stq_idx = 5'h0; // @[fpu.scala:170:7]
wire [4:0] io_resp_bits_uop_ppred = 5'h0; // @[fpu.scala:170:7]
wire [4:0] io_resp_bits_uop_mem_cmd = 5'h0; // @[fpu.scala:170:7]
wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[fpu.scala:170:7]
wire [4:0] io_resp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[fpu.scala:170:7]
wire [4:0] io_resp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[fpu.scala:170:7]
wire [4:0] io_resp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[fpu.scala:170:7]
wire [4:0] io_resp_bits_fflags_bits_uop_ppred = 5'h0; // @[fpu.scala:170:7]
wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[fpu.scala:170:7]
wire [1:0] io_resp_bits_uop_ctrl_op1_sel = 2'h0; // @[fpu.scala:170:7]
wire [1:0] io_resp_bits_uop_iw_state = 2'h0; // @[fpu.scala:170:7]
wire [1:0] io_resp_bits_uop_rxq_idx = 2'h0; // @[fpu.scala:170:7]
wire [1:0] io_resp_bits_uop_mem_size = 2'h0; // @[fpu.scala:170:7]
wire [1:0] io_resp_bits_uop_dst_rtype = 2'h0; // @[fpu.scala:170:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype = 2'h0; // @[fpu.scala:170:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype = 2'h0; // @[fpu.scala:170:7]
wire [1:0] io_resp_bits_uop_debug_fsrc = 2'h0; // @[fpu.scala:170:7]
wire [1:0] io_resp_bits_uop_debug_tsrc = 2'h0; // @[fpu.scala:170:7]
wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[fpu.scala:170:7]
wire [1:0] io_resp_bits_fflags_bits_uop_iw_state = 2'h0; // @[fpu.scala:170:7]
wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[fpu.scala:170:7]
wire [1:0] io_resp_bits_fflags_bits_uop_mem_size = 2'h0; // @[fpu.scala:170:7]
wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[fpu.scala:170:7]
wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[fpu.scala:170:7]
wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[fpu.scala:170:7]
wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[fpu.scala:170:7]
wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[fpu.scala:170:7]
wire [3:0] io_resp_bits_uop_ctrl_br_type = 4'h0; // @[fpu.scala:170:7]
wire [3:0] io_resp_bits_uop_br_tag = 4'h0; // @[fpu.scala:170:7]
wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[fpu.scala:170:7]
wire [3:0] io_resp_bits_fflags_bits_uop_br_tag = 4'h0; // @[fpu.scala:170:7]
wire [9:0] io_resp_bits_uop_fu_code = 10'h0; // @[fpu.scala:170:7]
wire [9:0] io_resp_bits_fflags_bits_uop_fu_code = 10'h0; // @[fpu.scala:170:7]
wire [2:0] io_resp_bits_uop_iq_type = 3'h0; // @[fpu.scala:170:7]
wire [2:0] io_resp_bits_uop_ctrl_op2_sel = 3'h0; // @[fpu.scala:170:7]
wire [2:0] io_resp_bits_uop_ctrl_imm_sel = 3'h0; // @[fpu.scala:170:7]
wire [2:0] io_resp_bits_uop_ctrl_csr_cmd = 3'h0; // @[fpu.scala:170:7]
wire [2:0] io_resp_bits_fflags_bits_uop_iq_type = 3'h0; // @[fpu.scala:170:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[fpu.scala:170:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[fpu.scala:170:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[fpu.scala:170:7]
wire [39:0] io_resp_bits_uop_debug_pc = 40'h0; // @[fpu.scala:170:7]
wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[fpu.scala:170:7]
wire [31:0] io_resp_bits_uop_inst = 32'h0; // @[fpu.scala:170:7]
wire [31:0] io_resp_bits_uop_debug_inst = 32'h0; // @[fpu.scala:170:7]
wire [31:0] io_resp_bits_fflags_bits_uop_inst = 32'h0; // @[fpu.scala:170:7]
wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[fpu.scala:170:7]
wire [6:0] io_resp_bits_uop_uopc = 7'h0; // @[fpu.scala:170:7]
wire [6:0] io_resp_bits_uop_rob_idx = 7'h0; // @[fpu.scala:170:7]
wire [6:0] io_resp_bits_uop_pdst = 7'h0; // @[fpu.scala:170:7]
wire [6:0] io_resp_bits_uop_prs1 = 7'h0; // @[fpu.scala:170:7]
wire [6:0] io_resp_bits_uop_prs2 = 7'h0; // @[fpu.scala:170:7]
wire [6:0] io_resp_bits_uop_prs3 = 7'h0; // @[fpu.scala:170:7]
wire [6:0] io_resp_bits_uop_stale_pdst = 7'h0; // @[fpu.scala:170:7]
wire [6:0] io_resp_bits_fflags_bits_uop_uopc = 7'h0; // @[fpu.scala:170:7]
wire [6:0] io_resp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[fpu.scala:170:7]
wire [6:0] io_resp_bits_fflags_bits_uop_pdst = 7'h0; // @[fpu.scala:170:7]
wire [6:0] io_resp_bits_fflags_bits_uop_prs1 = 7'h0; // @[fpu.scala:170:7]
wire [6:0] io_resp_bits_fflags_bits_uop_prs2 = 7'h0; // @[fpu.scala:170:7]
wire [6:0] io_resp_bits_fflags_bits_uop_prs3 = 7'h0; // @[fpu.scala:170:7]
wire [6:0] io_resp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_is_rvc = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_ctrl_fcn_dw = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_ctrl_is_load = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_ctrl_is_sta = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_ctrl_is_std = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_iw_p1_poisoned = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_iw_p2_poisoned = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_is_br = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_is_jalr = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_is_jal = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_is_sfb = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_edge_inst = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_taken = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_prs1_busy = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_prs2_busy = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_prs3_busy = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_ppred_busy = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_exception = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_bypassable = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_mem_signed = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_is_fence = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_is_fencei = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_is_amo = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_uses_ldq = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_uses_stq = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_is_sys_pc2epc = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_is_unique = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_flush_on_commit = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_ldst_is_rs1 = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_ldst_val = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_frs3_en = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_fp_val = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_fp_single = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_xcpt_pf_if = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_xcpt_ae_if = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_xcpt_ma_if = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_bp_debug_if = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_uop_bp_xcpt_if = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_predicated = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_is_br = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_is_jal = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_taken = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_exception = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_bypassable = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_is_fence = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_is_amo = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_is_unique = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_fp_val = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_fp_single = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[fpu.scala:170:7]
wire io_resp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[fpu.scala:170:7]
wire dfma_io_in_bits_req_vec = 1'h0; // @[fpu.scala:188:19]
wire sfma_io_in_bits_req_vec = 1'h0; // @[fpu.scala:188:19]
wire fpiu_io_in_bits_req_vec = 1'h0; // @[fpu.scala:188:19]
wire _fpu_out_data_T_2 = 1'h0; // @[package.scala:39:86]
wire [64:0] _dfma_io_in_bits_req_in1_T_1 = io_req_bits_rs1_data_0; // @[FPU.scala:372:26]
wire [64:0] _dfma_io_in_bits_req_in2_T_1 = io_req_bits_rs2_data_0; // @[FPU.scala:372:26]
wire [64:0] _dfma_io_in_bits_req_in3_T_1 = io_req_bits_rs3_data_0; // @[FPU.scala:372:26]
wire _io_resp_valid_T_2; // @[fpu.scala:234:38]
wire io_resp_bits_fflags_valid_0 = io_resp_valid; // @[fpu.scala:170:7]
wire [64:0] fpu_out_data; // @[fpu.scala:237:8]
wire [4:0] fpu_out_exc; // @[fpu.scala:243:8]
wire [4:0] io_resp_bits_fflags_bits_flags_0; // @[fpu.scala:170:7]
wire [64:0] io_resp_bits_data_0; // @[fpu.scala:170:7]
wire [2:0] _fp_rm_T = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58]
wire [2:0] _fp_rm_T_2 = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58]
wire _fp_rm_T_1 = &_fp_rm_T; // @[util.scala:289:58]
wire [2:0] fp_rm = _fp_rm_T_1 ? io_req_bits_fcsr_rm_0 : _fp_rm_T_2; // @[util.scala:289:58]
wire [2:0] dfma_io_in_bits_req_rm = fp_rm; // @[fpu.scala:185:18, :188:19]
wire [2:0] sfma_io_in_bits_req_rm = fp_rm; // @[fpu.scala:185:18, :188:19]
wire [2:0] fpiu_io_in_bits_req_rm = fp_rm; // @[fpu.scala:185:18, :188:19]
wire _GEN = io_req_valid_0 & _fp_decoder_io_sigs_fma; // @[fpu.scala:170:7, :182:26, :209:36]
wire _dfma_io_in_valid_T; // @[fpu.scala:209:36]
assign _dfma_io_in_valid_T = _GEN; // @[fpu.scala:209:36]
wire _sfma_io_in_valid_T; // @[fpu.scala:213:36]
assign _sfma_io_in_valid_T = _GEN; // @[fpu.scala:209:36, :213:36]
wire _GEN_0 = _fp_decoder_io_sigs_typeTagOut == 2'h1; // @[fpu.scala:182:26, :209:74]
wire _dfma_io_in_valid_T_1; // @[fpu.scala:209:74]
assign _dfma_io_in_valid_T_1 = _GEN_0; // @[fpu.scala:209:74]
wire _fpmu_double_T_1; // @[fpu.scala:229:79]
assign _fpmu_double_T_1 = _GEN_0; // @[fpu.scala:209:74, :229:79]
wire _dfma_io_in_valid_T_2 = _dfma_io_in_valid_T & _dfma_io_in_valid_T_1; // @[fpu.scala:209:{36,51,74}]
wire [1:0] _dfma_io_in_bits_req_typ_T; // @[util.scala:295:59]
wire dfma_io_in_bits_req_ldst; // @[fpu.scala:188:19]
wire dfma_io_in_bits_req_wen; // @[fpu.scala:188:19]
wire dfma_io_in_bits_req_ren1; // @[fpu.scala:188:19]
wire dfma_io_in_bits_req_ren2; // @[fpu.scala:188:19]
wire dfma_io_in_bits_req_ren3; // @[fpu.scala:188:19]
wire dfma_io_in_bits_req_swap12; // @[fpu.scala:188:19]
wire dfma_io_in_bits_req_swap23; // @[fpu.scala:188:19]
wire [1:0] dfma_io_in_bits_req_typeTagIn; // @[fpu.scala:188:19]
wire [1:0] dfma_io_in_bits_req_typeTagOut; // @[fpu.scala:188:19]
wire dfma_io_in_bits_req_fromint; // @[fpu.scala:188:19]
wire dfma_io_in_bits_req_toint; // @[fpu.scala:188:19]
wire dfma_io_in_bits_req_fastpipe; // @[fpu.scala:188:19]
wire dfma_io_in_bits_req_fma; // @[fpu.scala:188:19]
wire dfma_io_in_bits_req_div; // @[fpu.scala:188:19]
wire dfma_io_in_bits_req_sqrt; // @[fpu.scala:188:19]
wire dfma_io_in_bits_req_wflags; // @[fpu.scala:188:19]
wire [1:0] dfma_io_in_bits_req_fmaCmd; // @[fpu.scala:188:19]
wire [1:0] dfma_io_in_bits_req_typ; // @[fpu.scala:188:19]
wire [1:0] dfma_io_in_bits_req_fmt; // @[fpu.scala:188:19]
wire [64:0] dfma_io_in_bits_req_in1; // @[fpu.scala:188:19]
wire [64:0] dfma_io_in_bits_req_in2; // @[fpu.scala:188:19]
wire [64:0] dfma_io_in_bits_req_in3; // @[fpu.scala:188:19]
wire _dfma_io_in_bits_req_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14]
wire _sfma_io_in_bits_req_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14]
wire _fpiu_io_in_bits_req_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14]
wire _dfma_io_in_bits_req_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14]
wire _sfma_io_in_bits_req_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14]
wire _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14]
wire [30:0] _dfma_io_in_bits_req_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14]
wire [30:0] _sfma_io_in_bits_req_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14]
wire [30:0] _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14]
wire [1:0] dfma_io_in_bits_req_in1_prev_unswizzled_hi = {_dfma_io_in_bits_req_in1_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] dfma_io_in_bits_req_in1_prev_unswizzled = {dfma_io_in_bits_req_in1_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire dfma_io_in_bits_req_in1_prev_prev_sign = dfma_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] dfma_io_in_bits_req_in1_prev_prev_fractIn = dfma_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] dfma_io_in_bits_req_in1_prev_prev_expIn = dfma_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _dfma_io_in_bits_req_in1_prev_prev_fractOut_T = {dfma_io_in_bits_req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] dfma_io_in_bits_req_in1_prev_prev_fractOut = _dfma_io_in_bits_req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] dfma_io_in_bits_req_in1_prev_prev_expOut_expCode = dfma_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T = dfma_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in1_prev_prev_expOut_T | _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] dfma_io_in_bits_req_in1_prev_prev_expOut = _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] dfma_io_in_bits_req_in1_prev_prev_hi = {dfma_io_in_bits_req_in1_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] dfma_io_in_bits_req_in1_floats_0 = {dfma_io_in_bits_req_in1_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _dfma_io_in_bits_req_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49]
wire [4:0] _sfma_io_in_bits_req_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49]
wire [4:0] _fpiu_io_in_bits_req_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49]
wire dfma_io_in_bits_req_in1_prev_isbox = &_dfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire dfma_io_in_bits_req_in1_oks_0 = dfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32]
assign dfma_io_in_bits_req_in1 = _dfma_io_in_bits_req_in1_T_1; // @[FPU.scala:372:26]
wire _dfma_io_in_bits_req_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14]
wire _sfma_io_in_bits_req_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14]
wire _fpiu_io_in_bits_req_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14]
wire _dfma_io_in_bits_req_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14]
wire _sfma_io_in_bits_req_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14]
wire _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14]
wire [30:0] _dfma_io_in_bits_req_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14]
wire [30:0] _sfma_io_in_bits_req_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14]
wire [30:0] _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14]
wire [1:0] dfma_io_in_bits_req_in2_prev_unswizzled_hi = {_dfma_io_in_bits_req_in2_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] dfma_io_in_bits_req_in2_prev_unswizzled = {dfma_io_in_bits_req_in2_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire dfma_io_in_bits_req_in2_prev_prev_sign = dfma_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] dfma_io_in_bits_req_in2_prev_prev_fractIn = dfma_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] dfma_io_in_bits_req_in2_prev_prev_expIn = dfma_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _dfma_io_in_bits_req_in2_prev_prev_fractOut_T = {dfma_io_in_bits_req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] dfma_io_in_bits_req_in2_prev_prev_fractOut = _dfma_io_in_bits_req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] dfma_io_in_bits_req_in2_prev_prev_expOut_expCode = dfma_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T = dfma_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in2_prev_prev_expOut_T | _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] dfma_io_in_bits_req_in2_prev_prev_expOut = _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] dfma_io_in_bits_req_in2_prev_prev_hi = {dfma_io_in_bits_req_in2_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] dfma_io_in_bits_req_in2_floats_0 = {dfma_io_in_bits_req_in2_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _dfma_io_in_bits_req_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49]
wire [4:0] _sfma_io_in_bits_req_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49]
wire [4:0] _fpiu_io_in_bits_req_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49]
wire dfma_io_in_bits_req_in2_prev_isbox = &_dfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire dfma_io_in_bits_req_in2_oks_0 = dfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32]
assign dfma_io_in_bits_req_in2 = _dfma_io_in_bits_req_in2_T_1; // @[FPU.scala:372:26]
wire _dfma_io_in_bits_req_in3_prev_unswizzled_T = io_req_bits_rs3_data_0[31]; // @[FPU.scala:357:14]
wire _sfma_io_in_bits_req_in3_prev_unswizzled_T = io_req_bits_rs3_data_0[31]; // @[FPU.scala:357:14]
wire _fpiu_io_in_bits_req_in3_prev_unswizzled_T = io_req_bits_rs3_data_0[31]; // @[FPU.scala:357:14]
wire _dfma_io_in_bits_req_in3_prev_unswizzled_T_1 = io_req_bits_rs3_data_0[52]; // @[FPU.scala:358:14]
wire _sfma_io_in_bits_req_in3_prev_unswizzled_T_1 = io_req_bits_rs3_data_0[52]; // @[FPU.scala:358:14]
wire _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1 = io_req_bits_rs3_data_0[52]; // @[FPU.scala:358:14]
wire [30:0] _dfma_io_in_bits_req_in3_prev_unswizzled_T_2 = io_req_bits_rs3_data_0[30:0]; // @[FPU.scala:359:14]
wire [30:0] _sfma_io_in_bits_req_in3_prev_unswizzled_T_2 = io_req_bits_rs3_data_0[30:0]; // @[FPU.scala:359:14]
wire [30:0] _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2 = io_req_bits_rs3_data_0[30:0]; // @[FPU.scala:359:14]
wire [1:0] dfma_io_in_bits_req_in3_prev_unswizzled_hi = {_dfma_io_in_bits_req_in3_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] dfma_io_in_bits_req_in3_prev_unswizzled = {dfma_io_in_bits_req_in3_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire dfma_io_in_bits_req_in3_prev_prev_sign = dfma_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] dfma_io_in_bits_req_in3_prev_prev_fractIn = dfma_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] dfma_io_in_bits_req_in3_prev_prev_expIn = dfma_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _dfma_io_in_bits_req_in3_prev_prev_fractOut_T = {dfma_io_in_bits_req_in3_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] dfma_io_in_bits_req_in3_prev_prev_fractOut = _dfma_io_in_bits_req_in3_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] dfma_io_in_bits_req_in3_prev_prev_expOut_expCode = dfma_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in3_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T = dfma_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in3_prev_prev_expOut_T | _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] dfma_io_in_bits_req_in3_prev_prev_expOut = _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] dfma_io_in_bits_req_in3_prev_prev_hi = {dfma_io_in_bits_req_in3_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] dfma_io_in_bits_req_in3_floats_0 = {dfma_io_in_bits_req_in3_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _dfma_io_in_bits_req_in3_prev_isbox_T = io_req_bits_rs3_data_0[64:60]; // @[FPU.scala:332:49]
wire [4:0] _sfma_io_in_bits_req_in3_prev_isbox_T = io_req_bits_rs3_data_0[64:60]; // @[FPU.scala:332:49]
wire [4:0] _fpiu_io_in_bits_req_in3_prev_isbox_T = io_req_bits_rs3_data_0[64:60]; // @[FPU.scala:332:49]
wire dfma_io_in_bits_req_in3_prev_isbox = &_dfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire dfma_io_in_bits_req_in3_oks_0 = dfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32]
assign dfma_io_in_bits_req_in3 = _fp_decoder_io_sigs_swap23 ? dfma_io_in_bits_req_in2 : _dfma_io_in_bits_req_in3_T_1; // @[FPU.scala:372:26]
assign _dfma_io_in_bits_req_typ_T = io_req_bits_uop_imm_packed_0[9:8]; // @[util.scala:295:59]
wire [1:0] _sfma_io_in_bits_req_typ_T = io_req_bits_uop_imm_packed_0[9:8]; // @[util.scala:295:59]
wire [1:0] _fpiu_io_in_bits_req_typ_T = io_req_bits_uop_imm_packed_0[9:8]; // @[util.scala:295:59]
assign dfma_io_in_bits_req_typ = _dfma_io_in_bits_req_typ_T; // @[util.scala:295:59]
wire _GEN_1 = _fp_decoder_io_sigs_typeTagIn == 2'h0; // @[fpu.scala:182:26, :197:24]
wire _dfma_io_in_bits_req_fmt_T; // @[fpu.scala:197:24]
assign _dfma_io_in_bits_req_fmt_T = _GEN_1; // @[fpu.scala:197:24]
wire _sfma_io_in_bits_req_fmt_T; // @[fpu.scala:197:24]
assign _sfma_io_in_bits_req_fmt_T = _GEN_1; // @[fpu.scala:197:24]
wire _fpiu_io_in_bits_req_fmt_T; // @[fpu.scala:197:24]
assign _fpiu_io_in_bits_req_fmt_T = _GEN_1; // @[fpu.scala:197:24]
wire _dfma_io_in_bits_req_fmt_T_1 = ~_dfma_io_in_bits_req_fmt_T; // @[fpu.scala:197:{19,24}]
wire _GEN_2 = io_req_bits_uop_uopc_0 == 7'h46; // @[fpu.scala:170:7, :198:27]
wire _dfma_io_in_bits_T; // @[fpu.scala:198:27]
assign _dfma_io_in_bits_T = _GEN_2; // @[fpu.scala:198:27]
wire _sfma_io_in_bits_T; // @[fpu.scala:198:27]
assign _sfma_io_in_bits_T = _GEN_2; // @[fpu.scala:198:27]
wire _fpiu_io_in_bits_T; // @[fpu.scala:198:27]
assign _fpiu_io_in_bits_T = _GEN_2; // @[fpu.scala:198:27]
assign dfma_io_in_bits_req_fmt = _dfma_io_in_bits_T ? 2'h0 : {1'h0, _dfma_io_in_bits_req_fmt_T_1}; // @[fpu.scala:188:19, :197:{13,19}, :198:{27,43}, :199:15]
wire _sfma_io_in_valid_T_1 = _fp_decoder_io_sigs_typeTagOut == 2'h0; // @[fpu.scala:182:26, :213:74]
wire _sfma_io_in_valid_T_2 = _sfma_io_in_valid_T & _sfma_io_in_valid_T_1; // @[fpu.scala:213:{36,51,74}]
wire sfma_io_in_bits_req_ldst; // @[fpu.scala:188:19]
wire sfma_io_in_bits_req_wen; // @[fpu.scala:188:19]
wire sfma_io_in_bits_req_ren1; // @[fpu.scala:188:19]
wire sfma_io_in_bits_req_ren2; // @[fpu.scala:188:19]
wire sfma_io_in_bits_req_ren3; // @[fpu.scala:188:19]
wire sfma_io_in_bits_req_swap12; // @[fpu.scala:188:19]
wire sfma_io_in_bits_req_swap23; // @[fpu.scala:188:19]
wire [1:0] sfma_io_in_bits_req_typeTagIn; // @[fpu.scala:188:19]
wire [1:0] sfma_io_in_bits_req_typeTagOut; // @[fpu.scala:188:19]
wire sfma_io_in_bits_req_fromint; // @[fpu.scala:188:19]
wire sfma_io_in_bits_req_toint; // @[fpu.scala:188:19]
wire sfma_io_in_bits_req_fastpipe; // @[fpu.scala:188:19]
wire sfma_io_in_bits_req_fma; // @[fpu.scala:188:19]
wire sfma_io_in_bits_req_div; // @[fpu.scala:188:19]
wire sfma_io_in_bits_req_sqrt; // @[fpu.scala:188:19]
wire sfma_io_in_bits_req_wflags; // @[fpu.scala:188:19]
wire [1:0] sfma_io_in_bits_req_fmaCmd; // @[fpu.scala:188:19]
wire [1:0] sfma_io_in_bits_req_typ; // @[fpu.scala:188:19]
wire [1:0] sfma_io_in_bits_req_fmt; // @[fpu.scala:188:19]
wire [64:0] sfma_io_in_bits_req_in1; // @[fpu.scala:188:19]
wire [64:0] sfma_io_in_bits_req_in2; // @[fpu.scala:188:19]
wire [64:0] sfma_io_in_bits_req_in3; // @[fpu.scala:188:19]
wire [1:0] sfma_io_in_bits_req_in1_prev_unswizzled_hi = {_sfma_io_in_bits_req_in1_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] sfma_io_in_bits_req_in1_floats_0 = {sfma_io_in_bits_req_in1_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire sfma_io_in_bits_req_in1_prev_isbox = &_sfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire sfma_io_in_bits_req_in1_oks_0 = sfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire sfma_io_in_bits_req_in1_sign = io_req_bits_rs1_data_0[64]; // @[FPU.scala:274:17]
wire [51:0] sfma_io_in_bits_req_in1_fractIn = io_req_bits_rs1_data_0[51:0]; // @[FPU.scala:275:20]
wire [11:0] sfma_io_in_bits_req_in1_expIn = io_req_bits_rs1_data_0[63:52]; // @[FPU.scala:276:18]
wire [75:0] _sfma_io_in_bits_req_in1_fractOut_T = {sfma_io_in_bits_req_in1_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] sfma_io_in_bits_req_in1_fractOut = _sfma_io_in_bits_req_in1_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] sfma_io_in_bits_req_in1_expOut_expCode = sfma_io_in_bits_req_in1_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in1_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31]
wire [11:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in1_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in1_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] sfma_io_in_bits_req_in1_expOut_commonCase = _sfma_io_in_bits_req_in1_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _sfma_io_in_bits_req_in1_expOut_T = sfma_io_in_bits_req_in1_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _sfma_io_in_bits_req_in1_expOut_T_1 = sfma_io_in_bits_req_in1_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _sfma_io_in_bits_req_in1_expOut_T_2 = _sfma_io_in_bits_req_in1_expOut_T | _sfma_io_in_bits_req_in1_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _sfma_io_in_bits_req_in1_expOut_T_3 = sfma_io_in_bits_req_in1_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _sfma_io_in_bits_req_in1_expOut_T_4 = {sfma_io_in_bits_req_in1_expOut_expCode, _sfma_io_in_bits_req_in1_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] _sfma_io_in_bits_req_in1_expOut_T_5 = sfma_io_in_bits_req_in1_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97]
wire [8:0] sfma_io_in_bits_req_in1_expOut = _sfma_io_in_bits_req_in1_expOut_T_2 ? _sfma_io_in_bits_req_in1_expOut_T_4 : _sfma_io_in_bits_req_in1_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] sfma_io_in_bits_req_in1_hi = {sfma_io_in_bits_req_in1_sign, sfma_io_in_bits_req_in1_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] sfma_io_in_bits_req_in1_floats_1 = {sfma_io_in_bits_req_in1_hi, sfma_io_in_bits_req_in1_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [32:0] _sfma_io_in_bits_req_in1_T = sfma_io_in_bits_req_in1_oks_0 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31]
wire [32:0] _sfma_io_in_bits_req_in1_T_1 = sfma_io_in_bits_req_in1_floats_0 | _sfma_io_in_bits_req_in1_T; // @[FPU.scala:356:31, :372:{26,31}]
assign sfma_io_in_bits_req_in1 = {32'h0, _sfma_io_in_bits_req_in1_T_1}; // @[FPU.scala:372:26]
wire [1:0] sfma_io_in_bits_req_in2_prev_unswizzled_hi = {_sfma_io_in_bits_req_in2_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] sfma_io_in_bits_req_in2_floats_0 = {sfma_io_in_bits_req_in2_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire sfma_io_in_bits_req_in2_prev_isbox = &_sfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire sfma_io_in_bits_req_in2_oks_0 = sfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire sfma_io_in_bits_req_in2_sign = io_req_bits_rs2_data_0[64]; // @[FPU.scala:274:17]
wire [51:0] sfma_io_in_bits_req_in2_fractIn = io_req_bits_rs2_data_0[51:0]; // @[FPU.scala:275:20]
wire [11:0] sfma_io_in_bits_req_in2_expIn = io_req_bits_rs2_data_0[63:52]; // @[FPU.scala:276:18]
wire [75:0] _sfma_io_in_bits_req_in2_fractOut_T = {sfma_io_in_bits_req_in2_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] sfma_io_in_bits_req_in2_fractOut = _sfma_io_in_bits_req_in2_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] sfma_io_in_bits_req_in2_expOut_expCode = sfma_io_in_bits_req_in2_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in2_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31]
wire [11:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in2_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in2_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] sfma_io_in_bits_req_in2_expOut_commonCase = _sfma_io_in_bits_req_in2_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _sfma_io_in_bits_req_in2_expOut_T = sfma_io_in_bits_req_in2_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _sfma_io_in_bits_req_in2_expOut_T_1 = sfma_io_in_bits_req_in2_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _sfma_io_in_bits_req_in2_expOut_T_2 = _sfma_io_in_bits_req_in2_expOut_T | _sfma_io_in_bits_req_in2_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _sfma_io_in_bits_req_in2_expOut_T_3 = sfma_io_in_bits_req_in2_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _sfma_io_in_bits_req_in2_expOut_T_4 = {sfma_io_in_bits_req_in2_expOut_expCode, _sfma_io_in_bits_req_in2_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] _sfma_io_in_bits_req_in2_expOut_T_5 = sfma_io_in_bits_req_in2_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97]
wire [8:0] sfma_io_in_bits_req_in2_expOut = _sfma_io_in_bits_req_in2_expOut_T_2 ? _sfma_io_in_bits_req_in2_expOut_T_4 : _sfma_io_in_bits_req_in2_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] sfma_io_in_bits_req_in2_hi = {sfma_io_in_bits_req_in2_sign, sfma_io_in_bits_req_in2_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] sfma_io_in_bits_req_in2_floats_1 = {sfma_io_in_bits_req_in2_hi, sfma_io_in_bits_req_in2_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [32:0] _sfma_io_in_bits_req_in2_T = sfma_io_in_bits_req_in2_oks_0 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31]
wire [32:0] _sfma_io_in_bits_req_in2_T_1 = sfma_io_in_bits_req_in2_floats_0 | _sfma_io_in_bits_req_in2_T; // @[FPU.scala:356:31, :372:{26,31}]
assign sfma_io_in_bits_req_in2 = {32'h0, _sfma_io_in_bits_req_in2_T_1}; // @[FPU.scala:372:26]
wire [1:0] sfma_io_in_bits_req_in3_prev_unswizzled_hi = {_sfma_io_in_bits_req_in3_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] sfma_io_in_bits_req_in3_floats_0 = {sfma_io_in_bits_req_in3_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire sfma_io_in_bits_req_in3_prev_isbox = &_sfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire sfma_io_in_bits_req_in3_oks_0 = sfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire sfma_io_in_bits_req_in3_sign = io_req_bits_rs3_data_0[64]; // @[FPU.scala:274:17]
wire [51:0] sfma_io_in_bits_req_in3_fractIn = io_req_bits_rs3_data_0[51:0]; // @[FPU.scala:275:20]
wire [11:0] sfma_io_in_bits_req_in3_expIn = io_req_bits_rs3_data_0[63:52]; // @[FPU.scala:276:18]
wire [75:0] _sfma_io_in_bits_req_in3_fractOut_T = {sfma_io_in_bits_req_in3_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] sfma_io_in_bits_req_in3_fractOut = _sfma_io_in_bits_req_in3_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] sfma_io_in_bits_req_in3_expOut_expCode = sfma_io_in_bits_req_in3_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in3_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31]
wire [11:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in3_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in3_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] sfma_io_in_bits_req_in3_expOut_commonCase = _sfma_io_in_bits_req_in3_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _sfma_io_in_bits_req_in3_expOut_T = sfma_io_in_bits_req_in3_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _sfma_io_in_bits_req_in3_expOut_T_1 = sfma_io_in_bits_req_in3_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _sfma_io_in_bits_req_in3_expOut_T_2 = _sfma_io_in_bits_req_in3_expOut_T | _sfma_io_in_bits_req_in3_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _sfma_io_in_bits_req_in3_expOut_T_3 = sfma_io_in_bits_req_in3_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _sfma_io_in_bits_req_in3_expOut_T_4 = {sfma_io_in_bits_req_in3_expOut_expCode, _sfma_io_in_bits_req_in3_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] _sfma_io_in_bits_req_in3_expOut_T_5 = sfma_io_in_bits_req_in3_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97]
wire [8:0] sfma_io_in_bits_req_in3_expOut = _sfma_io_in_bits_req_in3_expOut_T_2 ? _sfma_io_in_bits_req_in3_expOut_T_4 : _sfma_io_in_bits_req_in3_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] sfma_io_in_bits_req_in3_hi = {sfma_io_in_bits_req_in3_sign, sfma_io_in_bits_req_in3_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] sfma_io_in_bits_req_in3_floats_1 = {sfma_io_in_bits_req_in3_hi, sfma_io_in_bits_req_in3_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [32:0] _sfma_io_in_bits_req_in3_T = sfma_io_in_bits_req_in3_oks_0 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31]
wire [32:0] _sfma_io_in_bits_req_in3_T_1 = sfma_io_in_bits_req_in3_floats_0 | _sfma_io_in_bits_req_in3_T; // @[FPU.scala:356:31, :372:{26,31}]
assign sfma_io_in_bits_req_in3 = _fp_decoder_io_sigs_swap23 ? sfma_io_in_bits_req_in2 : {32'h0, _sfma_io_in_bits_req_in3_T_1}; // @[FPU.scala:372:26]
assign sfma_io_in_bits_req_typ = _sfma_io_in_bits_req_typ_T; // @[util.scala:295:59]
wire _sfma_io_in_bits_req_fmt_T_1 = ~_sfma_io_in_bits_req_fmt_T; // @[fpu.scala:197:{19,24}]
assign sfma_io_in_bits_req_fmt = _sfma_io_in_bits_T ? 2'h0 : {1'h0, _sfma_io_in_bits_req_fmt_T_1}; // @[fpu.scala:188:19, :197:{13,19}, :198:{27,43}, :199:15]
wire _fpiu_io_in_valid_T = _fp_decoder_io_sigs_fastpipe & _fp_decoder_io_sigs_wflags; // @[fpu.scala:182:26, :217:75]
wire _fpiu_io_in_valid_T_1 = _fp_decoder_io_sigs_toint | _fpiu_io_in_valid_T; // @[fpu.scala:182:26, :217:{54,75}]
wire _fpiu_io_in_valid_T_2 = io_req_valid_0 & _fpiu_io_in_valid_T_1; // @[fpu.scala:170:7, :217:{36,54}]
wire [64:0] _fpiu_io_in_bits_req_in1_T_4; // @[FPU.scala:369:10]
wire [64:0] _fpiu_io_in_bits_req_in2_T_4; // @[FPU.scala:369:10]
wire fpiu_io_in_bits_req_ldst; // @[fpu.scala:188:19]
wire fpiu_io_in_bits_req_wen; // @[fpu.scala:188:19]
wire fpiu_io_in_bits_req_ren1; // @[fpu.scala:188:19]
wire fpiu_io_in_bits_req_ren2; // @[fpu.scala:188:19]
wire fpiu_io_in_bits_req_ren3; // @[fpu.scala:188:19]
wire fpiu_io_in_bits_req_swap12; // @[fpu.scala:188:19]
wire fpiu_io_in_bits_req_swap23; // @[fpu.scala:188:19]
wire [1:0] fpiu_io_in_bits_req_typeTagIn; // @[fpu.scala:188:19]
wire [1:0] fpiu_io_in_bits_req_typeTagOut; // @[fpu.scala:188:19]
wire fpiu_io_in_bits_req_fromint; // @[fpu.scala:188:19]
wire fpiu_io_in_bits_req_toint; // @[fpu.scala:188:19]
wire fpiu_io_in_bits_req_fastpipe; // @[fpu.scala:188:19]
wire fpiu_io_in_bits_req_fma; // @[fpu.scala:188:19]
wire fpiu_io_in_bits_req_div; // @[fpu.scala:188:19]
wire fpiu_io_in_bits_req_sqrt; // @[fpu.scala:188:19]
wire fpiu_io_in_bits_req_wflags; // @[fpu.scala:188:19]
wire [1:0] fpiu_io_in_bits_req_fmaCmd; // @[fpu.scala:188:19]
wire [1:0] fpiu_io_in_bits_req_typ; // @[fpu.scala:188:19]
wire [1:0] fpiu_io_in_bits_req_fmt; // @[fpu.scala:188:19]
wire [64:0] fpiu_io_in_bits_req_in1; // @[fpu.scala:188:19]
wire [64:0] fpiu_io_in_bits_req_in2; // @[fpu.scala:188:19]
wire [64:0] fpiu_io_in_bits_req_in3; // @[fpu.scala:188:19]
wire [1:0] fpiu_io_in_bits_req_in1_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in1_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] fpiu_io_in_bits_req_in1_prev_unswizzled = {fpiu_io_in_bits_req_in1_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire fpiu_io_in_bits_req_in1_prev_prev_sign = fpiu_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] fpiu_io_in_bits_req_in1_prev_prev_fractIn = fpiu_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] fpiu_io_in_bits_req_in1_prev_prev_expIn = fpiu_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] fpiu_io_in_bits_req_in1_prev_prev_fractOut = _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T = fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in1_prev_prev_expOut_T | _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_expOut = _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] fpiu_io_in_bits_req_in1_prev_prev_hi = {fpiu_io_in_bits_req_in1_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] fpiu_io_in_bits_req_in1_floats_0 = {fpiu_io_in_bits_req_in1_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire fpiu_io_in_bits_req_in1_prev_isbox = &_fpiu_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire fpiu_io_in_bits_req_in1_oks_0 = fpiu_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire [1:0] _fpiu_io_in_bits_req_in1_truncIdx_T; // @[package.scala:38:21]
wire fpiu_io_in_bits_req_in1_truncIdx = _fpiu_io_in_bits_req_in1_truncIdx_T[0]; // @[package.scala:38:{21,47}]
wire _fpiu_io_in_bits_req_in1_T = fpiu_io_in_bits_req_in1_truncIdx; // @[package.scala:38:47, :39:86]
wire _fpiu_io_in_bits_req_in1_T_1 = _fpiu_io_in_bits_req_in1_T | fpiu_io_in_bits_req_in1_oks_0; // @[package.scala:39:{76,86}]
wire [1:0] _fpiu_io_in_bits_req_in1_truncIdx_T_1; // @[package.scala:38:21]
wire fpiu_io_in_bits_req_in1_truncIdx_1 = _fpiu_io_in_bits_req_in1_truncIdx_T_1[0]; // @[package.scala:38:{21,47}]
wire _fpiu_io_in_bits_req_in1_T_2 = fpiu_io_in_bits_req_in1_truncIdx_1; // @[package.scala:38:47, :39:86]
wire [64:0] _fpiu_io_in_bits_req_in1_T_3 = _fpiu_io_in_bits_req_in1_T_2 ? io_req_bits_rs1_data_0 : fpiu_io_in_bits_req_in1_floats_0; // @[package.scala:39:{76,86}]
assign _fpiu_io_in_bits_req_in1_T_4 = _fpiu_io_in_bits_req_in1_T_1 ? _fpiu_io_in_bits_req_in1_T_3 : 65'hE008000000000000; // @[package.scala:39:76]
assign fpiu_io_in_bits_req_in1 = _fpiu_io_in_bits_req_in1_T_4; // @[FPU.scala:369:10]
wire [1:0] fpiu_io_in_bits_req_in2_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in2_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] fpiu_io_in_bits_req_in2_prev_unswizzled = {fpiu_io_in_bits_req_in2_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire fpiu_io_in_bits_req_in2_prev_prev_sign = fpiu_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] fpiu_io_in_bits_req_in2_prev_prev_fractIn = fpiu_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] fpiu_io_in_bits_req_in2_prev_prev_expIn = fpiu_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] fpiu_io_in_bits_req_in2_prev_prev_fractOut = _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T = fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in2_prev_prev_expOut_T | _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_expOut = _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] fpiu_io_in_bits_req_in2_prev_prev_hi = {fpiu_io_in_bits_req_in2_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] fpiu_io_in_bits_req_in2_floats_0 = {fpiu_io_in_bits_req_in2_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire fpiu_io_in_bits_req_in2_prev_isbox = &_fpiu_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire fpiu_io_in_bits_req_in2_oks_0 = fpiu_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire [1:0] _fpiu_io_in_bits_req_in2_truncIdx_T; // @[package.scala:38:21]
wire fpiu_io_in_bits_req_in2_truncIdx = _fpiu_io_in_bits_req_in2_truncIdx_T[0]; // @[package.scala:38:{21,47}]
wire _fpiu_io_in_bits_req_in2_T = fpiu_io_in_bits_req_in2_truncIdx; // @[package.scala:38:47, :39:86]
wire _fpiu_io_in_bits_req_in2_T_1 = _fpiu_io_in_bits_req_in2_T | fpiu_io_in_bits_req_in2_oks_0; // @[package.scala:39:{76,86}]
wire [1:0] _fpiu_io_in_bits_req_in2_truncIdx_T_1; // @[package.scala:38:21]
wire fpiu_io_in_bits_req_in2_truncIdx_1 = _fpiu_io_in_bits_req_in2_truncIdx_T_1[0]; // @[package.scala:38:{21,47}]
wire _fpiu_io_in_bits_req_in2_T_2 = fpiu_io_in_bits_req_in2_truncIdx_1; // @[package.scala:38:47, :39:86]
wire [64:0] _fpiu_io_in_bits_req_in2_T_3 = _fpiu_io_in_bits_req_in2_T_2 ? io_req_bits_rs2_data_0 : fpiu_io_in_bits_req_in2_floats_0; // @[package.scala:39:{76,86}]
assign _fpiu_io_in_bits_req_in2_T_4 = _fpiu_io_in_bits_req_in2_T_1 ? _fpiu_io_in_bits_req_in2_T_3 : 65'hE008000000000000; // @[package.scala:39:76]
assign fpiu_io_in_bits_req_in2 = _fpiu_io_in_bits_req_in2_T_4; // @[FPU.scala:369:10]
wire [1:0] fpiu_io_in_bits_req_in3_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in3_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] fpiu_io_in_bits_req_in3_prev_unswizzled = {fpiu_io_in_bits_req_in3_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire fpiu_io_in_bits_req_in3_prev_prev_sign = fpiu_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] fpiu_io_in_bits_req_in3_prev_prev_fractIn = fpiu_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] fpiu_io_in_bits_req_in3_prev_prev_expIn = fpiu_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in3_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] fpiu_io_in_bits_req_in3_prev_prev_fractOut = _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in3_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T = fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in3_prev_prev_expOut_T | _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_expOut = _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] fpiu_io_in_bits_req_in3_prev_prev_hi = {fpiu_io_in_bits_req_in3_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] fpiu_io_in_bits_req_in3_floats_0 = {fpiu_io_in_bits_req_in3_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire fpiu_io_in_bits_req_in3_prev_isbox = &_fpiu_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire fpiu_io_in_bits_req_in3_oks_0 = fpiu_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire [1:0] _fpiu_io_in_bits_req_in3_truncIdx_T; // @[package.scala:38:21]
wire fpiu_io_in_bits_req_in3_truncIdx = _fpiu_io_in_bits_req_in3_truncIdx_T[0]; // @[package.scala:38:{21,47}]
wire _fpiu_io_in_bits_req_in3_T = fpiu_io_in_bits_req_in3_truncIdx; // @[package.scala:38:47, :39:86]
wire _fpiu_io_in_bits_req_in3_T_1 = _fpiu_io_in_bits_req_in3_T | fpiu_io_in_bits_req_in3_oks_0; // @[package.scala:39:{76,86}]
wire [1:0] _fpiu_io_in_bits_req_in3_truncIdx_T_1; // @[package.scala:38:21]
wire fpiu_io_in_bits_req_in3_truncIdx_1 = _fpiu_io_in_bits_req_in3_truncIdx_T_1[0]; // @[package.scala:38:{21,47}]
wire _fpiu_io_in_bits_req_in3_T_2 = fpiu_io_in_bits_req_in3_truncIdx_1; // @[package.scala:38:47, :39:86]
wire [64:0] _fpiu_io_in_bits_req_in3_T_3 = _fpiu_io_in_bits_req_in3_T_2 ? io_req_bits_rs3_data_0 : fpiu_io_in_bits_req_in3_floats_0; // @[package.scala:39:{76,86}]
wire [64:0] _fpiu_io_in_bits_req_in3_T_4 = _fpiu_io_in_bits_req_in3_T_1 ? _fpiu_io_in_bits_req_in3_T_3 : 65'hE008000000000000; // @[package.scala:39:76]
assign fpiu_io_in_bits_req_in3 = _fp_decoder_io_sigs_swap23 ? fpiu_io_in_bits_req_in2 : _fpiu_io_in_bits_req_in3_T_4; // @[FPU.scala:369:10]
assign fpiu_io_in_bits_req_typ = _fpiu_io_in_bits_req_typ_T; // @[util.scala:295:59]
wire _fpiu_io_in_bits_req_fmt_T_1 = ~_fpiu_io_in_bits_req_fmt_T; // @[fpu.scala:197:{19,24}]
assign fpiu_io_in_bits_req_fmt = _fpiu_io_in_bits_T ? 2'h0 : {1'h0, _fpiu_io_in_bits_req_fmt_T_1}; // @[fpu.scala:188:19, :197:{13,19}, :198:{27,43}, :199:15]
wire _fpiu_out_T = ~_fp_decoder_io_sigs_fastpipe; // @[fpu.scala:182:26, :219:51]
wire _fpiu_out_T_1 = _fpiu_io_in_valid_T_2 & _fpiu_out_T; // @[fpu.scala:217:36, :219:{48,51}]
reg fpiu_out_REG; // @[fpu.scala:219:30]
reg fpiu_out_pipe_v; // @[Valid.scala:141:24]
reg fpiu_out_pipe_b_in_ldst; // @[Valid.scala:142:26]
reg fpiu_out_pipe_b_in_wen; // @[Valid.scala:142:26]
reg fpiu_out_pipe_b_in_ren1; // @[Valid.scala:142:26]
reg fpiu_out_pipe_b_in_ren2; // @[Valid.scala:142:26]
reg fpiu_out_pipe_b_in_ren3; // @[Valid.scala:142:26]
reg fpiu_out_pipe_b_in_swap12; // @[Valid.scala:142:26]
reg fpiu_out_pipe_b_in_swap23; // @[Valid.scala:142:26]
reg [1:0] fpiu_out_pipe_b_in_typeTagIn; // @[Valid.scala:142:26]
reg [1:0] fpiu_out_pipe_b_in_typeTagOut; // @[Valid.scala:142:26]
reg fpiu_out_pipe_b_in_fromint; // @[Valid.scala:142:26]
reg fpiu_out_pipe_b_in_toint; // @[Valid.scala:142:26]
reg fpiu_out_pipe_b_in_fastpipe; // @[Valid.scala:142:26]
reg fpiu_out_pipe_b_in_fma; // @[Valid.scala:142:26]
reg fpiu_out_pipe_b_in_div; // @[Valid.scala:142:26]
reg fpiu_out_pipe_b_in_sqrt; // @[Valid.scala:142:26]
reg fpiu_out_pipe_b_in_wflags; // @[Valid.scala:142:26]
reg fpiu_out_pipe_b_in_vec; // @[Valid.scala:142:26]
reg [2:0] fpiu_out_pipe_b_in_rm; // @[Valid.scala:142:26]
reg [1:0] fpiu_out_pipe_b_in_fmaCmd; // @[Valid.scala:142:26]
reg [1:0] fpiu_out_pipe_b_in_typ; // @[Valid.scala:142:26]
reg [1:0] fpiu_out_pipe_b_in_fmt; // @[Valid.scala:142:26]
reg [64:0] fpiu_out_pipe_b_in_in1; // @[Valid.scala:142:26]
reg [64:0] fpiu_out_pipe_b_in_in2; // @[Valid.scala:142:26]
reg [64:0] fpiu_out_pipe_b_in_in3; // @[Valid.scala:142:26]
reg fpiu_out_pipe_b_lt; // @[Valid.scala:142:26]
reg [63:0] fpiu_out_pipe_b_store; // @[Valid.scala:142:26]
reg [63:0] fpiu_out_pipe_b_toint; // @[Valid.scala:142:26]
reg [4:0] fpiu_out_pipe_b_exc; // @[Valid.scala:142:26]
reg fpiu_out_pipe_pipe_v; // @[Valid.scala:141:24]
reg fpiu_out_pipe_pipe_b_in_ldst; // @[Valid.scala:142:26]
reg fpiu_out_pipe_pipe_b_in_wen; // @[Valid.scala:142:26]
reg fpiu_out_pipe_pipe_b_in_ren1; // @[Valid.scala:142:26]
reg fpiu_out_pipe_pipe_b_in_ren2; // @[Valid.scala:142:26]
reg fpiu_out_pipe_pipe_b_in_ren3; // @[Valid.scala:142:26]
reg fpiu_out_pipe_pipe_b_in_swap12; // @[Valid.scala:142:26]
reg fpiu_out_pipe_pipe_b_in_swap23; // @[Valid.scala:142:26]
reg [1:0] fpiu_out_pipe_pipe_b_in_typeTagIn; // @[Valid.scala:142:26]
reg [1:0] fpiu_out_pipe_pipe_b_in_typeTagOut; // @[Valid.scala:142:26]
reg fpiu_out_pipe_pipe_b_in_fromint; // @[Valid.scala:142:26]
reg fpiu_out_pipe_pipe_b_in_toint; // @[Valid.scala:142:26]
reg fpiu_out_pipe_pipe_b_in_fastpipe; // @[Valid.scala:142:26]
reg fpiu_out_pipe_pipe_b_in_fma; // @[Valid.scala:142:26]
reg fpiu_out_pipe_pipe_b_in_div; // @[Valid.scala:142:26]
reg fpiu_out_pipe_pipe_b_in_sqrt; // @[Valid.scala:142:26]
reg fpiu_out_pipe_pipe_b_in_wflags; // @[Valid.scala:142:26]
reg fpiu_out_pipe_pipe_b_in_vec; // @[Valid.scala:142:26]
reg [2:0] fpiu_out_pipe_pipe_b_in_rm; // @[Valid.scala:142:26]
reg [1:0] fpiu_out_pipe_pipe_b_in_fmaCmd; // @[Valid.scala:142:26]
reg [1:0] fpiu_out_pipe_pipe_b_in_typ; // @[Valid.scala:142:26]
reg [1:0] fpiu_out_pipe_pipe_b_in_fmt; // @[Valid.scala:142:26]
reg [64:0] fpiu_out_pipe_pipe_b_in_in1; // @[Valid.scala:142:26]
reg [64:0] fpiu_out_pipe_pipe_b_in_in2; // @[Valid.scala:142:26]
reg [64:0] fpiu_out_pipe_pipe_b_in_in3; // @[Valid.scala:142:26]
reg fpiu_out_pipe_pipe_b_lt; // @[Valid.scala:142:26]
reg [63:0] fpiu_out_pipe_pipe_b_store; // @[Valid.scala:142:26]
reg [63:0] fpiu_out_pipe_pipe_b_toint; // @[Valid.scala:142:26]
reg [4:0] fpiu_out_pipe_pipe_b_exc; // @[Valid.scala:142:26]
reg fpiu_out_pipe_pipe_pipe_v; // @[Valid.scala:141:24]
wire fpiu_out_valid = fpiu_out_pipe_pipe_pipe_v; // @[Valid.scala:135:21, :141:24]
reg fpiu_out_pipe_pipe_pipe_b_in_ldst; // @[Valid.scala:142:26]
wire fpiu_out_bits_in_ldst = fpiu_out_pipe_pipe_pipe_b_in_ldst; // @[Valid.scala:135:21, :142:26]
reg fpiu_out_pipe_pipe_pipe_b_in_wen; // @[Valid.scala:142:26]
wire fpiu_out_bits_in_wen = fpiu_out_pipe_pipe_pipe_b_in_wen; // @[Valid.scala:135:21, :142:26]
reg fpiu_out_pipe_pipe_pipe_b_in_ren1; // @[Valid.scala:142:26]
wire fpiu_out_bits_in_ren1 = fpiu_out_pipe_pipe_pipe_b_in_ren1; // @[Valid.scala:135:21, :142:26]
reg fpiu_out_pipe_pipe_pipe_b_in_ren2; // @[Valid.scala:142:26]
wire fpiu_out_bits_in_ren2 = fpiu_out_pipe_pipe_pipe_b_in_ren2; // @[Valid.scala:135:21, :142:26]
reg fpiu_out_pipe_pipe_pipe_b_in_ren3; // @[Valid.scala:142:26]
wire fpiu_out_bits_in_ren3 = fpiu_out_pipe_pipe_pipe_b_in_ren3; // @[Valid.scala:135:21, :142:26]
reg fpiu_out_pipe_pipe_pipe_b_in_swap12; // @[Valid.scala:142:26]
wire fpiu_out_bits_in_swap12 = fpiu_out_pipe_pipe_pipe_b_in_swap12; // @[Valid.scala:135:21, :142:26]
reg fpiu_out_pipe_pipe_pipe_b_in_swap23; // @[Valid.scala:142:26]
wire fpiu_out_bits_in_swap23 = fpiu_out_pipe_pipe_pipe_b_in_swap23; // @[Valid.scala:135:21, :142:26]
reg [1:0] fpiu_out_pipe_pipe_pipe_b_in_typeTagIn; // @[Valid.scala:142:26]
wire [1:0] fpiu_out_bits_in_typeTagIn = fpiu_out_pipe_pipe_pipe_b_in_typeTagIn; // @[Valid.scala:135:21, :142:26]
reg [1:0] fpiu_out_pipe_pipe_pipe_b_in_typeTagOut; // @[Valid.scala:142:26]
wire [1:0] fpiu_out_bits_in_typeTagOut = fpiu_out_pipe_pipe_pipe_b_in_typeTagOut; // @[Valid.scala:135:21, :142:26]
reg fpiu_out_pipe_pipe_pipe_b_in_fromint; // @[Valid.scala:142:26]
wire fpiu_out_bits_in_fromint = fpiu_out_pipe_pipe_pipe_b_in_fromint; // @[Valid.scala:135:21, :142:26]
reg fpiu_out_pipe_pipe_pipe_b_in_toint; // @[Valid.scala:142:26]
wire fpiu_out_bits_in_toint = fpiu_out_pipe_pipe_pipe_b_in_toint; // @[Valid.scala:135:21, :142:26]
reg fpiu_out_pipe_pipe_pipe_b_in_fastpipe; // @[Valid.scala:142:26]
wire fpiu_out_bits_in_fastpipe = fpiu_out_pipe_pipe_pipe_b_in_fastpipe; // @[Valid.scala:135:21, :142:26]
reg fpiu_out_pipe_pipe_pipe_b_in_fma; // @[Valid.scala:142:26]
wire fpiu_out_bits_in_fma = fpiu_out_pipe_pipe_pipe_b_in_fma; // @[Valid.scala:135:21, :142:26]
reg fpiu_out_pipe_pipe_pipe_b_in_div; // @[Valid.scala:142:26]
wire fpiu_out_bits_in_div = fpiu_out_pipe_pipe_pipe_b_in_div; // @[Valid.scala:135:21, :142:26]
reg fpiu_out_pipe_pipe_pipe_b_in_sqrt; // @[Valid.scala:142:26]
wire fpiu_out_bits_in_sqrt = fpiu_out_pipe_pipe_pipe_b_in_sqrt; // @[Valid.scala:135:21, :142:26]
reg fpiu_out_pipe_pipe_pipe_b_in_wflags; // @[Valid.scala:142:26]
wire fpiu_out_bits_in_wflags = fpiu_out_pipe_pipe_pipe_b_in_wflags; // @[Valid.scala:135:21, :142:26]
reg fpiu_out_pipe_pipe_pipe_b_in_vec; // @[Valid.scala:142:26]
wire fpiu_out_bits_in_vec = fpiu_out_pipe_pipe_pipe_b_in_vec; // @[Valid.scala:135:21, :142:26]
reg [2:0] fpiu_out_pipe_pipe_pipe_b_in_rm; // @[Valid.scala:142:26]
wire [2:0] fpiu_out_bits_in_rm = fpiu_out_pipe_pipe_pipe_b_in_rm; // @[Valid.scala:135:21, :142:26]
reg [1:0] fpiu_out_pipe_pipe_pipe_b_in_fmaCmd; // @[Valid.scala:142:26]
wire [1:0] fpiu_out_bits_in_fmaCmd = fpiu_out_pipe_pipe_pipe_b_in_fmaCmd; // @[Valid.scala:135:21, :142:26]
reg [1:0] fpiu_out_pipe_pipe_pipe_b_in_typ; // @[Valid.scala:142:26]
wire [1:0] fpiu_out_bits_in_typ = fpiu_out_pipe_pipe_pipe_b_in_typ; // @[Valid.scala:135:21, :142:26]
reg [1:0] fpiu_out_pipe_pipe_pipe_b_in_fmt; // @[Valid.scala:142:26]
wire [1:0] fpiu_out_bits_in_fmt = fpiu_out_pipe_pipe_pipe_b_in_fmt; // @[Valid.scala:135:21, :142:26]
reg [64:0] fpiu_out_pipe_pipe_pipe_b_in_in1; // @[Valid.scala:142:26]
wire [64:0] fpiu_out_bits_in_in1 = fpiu_out_pipe_pipe_pipe_b_in_in1; // @[Valid.scala:135:21, :142:26]
reg [64:0] fpiu_out_pipe_pipe_pipe_b_in_in2; // @[Valid.scala:142:26]
wire [64:0] fpiu_out_bits_in_in2 = fpiu_out_pipe_pipe_pipe_b_in_in2; // @[Valid.scala:135:21, :142:26]
reg [64:0] fpiu_out_pipe_pipe_pipe_b_in_in3; // @[Valid.scala:142:26]
wire [64:0] fpiu_out_bits_in_in3 = fpiu_out_pipe_pipe_pipe_b_in_in3; // @[Valid.scala:135:21, :142:26]
reg fpiu_out_pipe_pipe_pipe_b_lt; // @[Valid.scala:142:26]
wire fpiu_out_bits_lt = fpiu_out_pipe_pipe_pipe_b_lt; // @[Valid.scala:135:21, :142:26]
reg [63:0] fpiu_out_pipe_pipe_pipe_b_store; // @[Valid.scala:142:26]
wire [63:0] fpiu_out_bits_store = fpiu_out_pipe_pipe_pipe_b_store; // @[Valid.scala:135:21, :142:26]
reg [63:0] fpiu_out_pipe_pipe_pipe_b_toint; // @[Valid.scala:142:26]
wire [63:0] fpiu_out_bits_toint = fpiu_out_pipe_pipe_pipe_b_toint; // @[Valid.scala:135:21, :142:26]
reg [4:0] fpiu_out_pipe_pipe_pipe_b_exc; // @[Valid.scala:142:26]
wire [4:0] fpiu_out_bits_exc = fpiu_out_pipe_pipe_pipe_b_exc; // @[Valid.scala:135:21, :142:26]
wire [4:0] fpiu_result_exc = fpiu_out_bits_exc; // @[Valid.scala:135:21]
wire [64:0] fpiu_result_data; // @[fpu.scala:221:26]
assign fpiu_result_data = {1'h0, fpiu_out_bits_toint}; // @[Valid.scala:135:21]
wire _GEN_3 = io_req_valid_0 & _fp_decoder_io_sigs_fastpipe; // @[fpu.scala:170:7, :182:26, :226:36]
wire _fpmu_io_in_valid_T; // @[fpu.scala:226:36]
assign _fpmu_io_in_valid_T = _GEN_3; // @[fpu.scala:226:36]
wire _fpmu_double_T; // @[fpu.scala:229:39]
assign _fpmu_double_T = _GEN_3; // @[fpu.scala:226:36, :229:39]
reg fpmu_double_pipe_v; // @[Valid.scala:141:24]
reg fpmu_double_pipe_b; // @[Valid.scala:142:26]
reg fpmu_double_pipe_pipe_v; // @[Valid.scala:141:24]
reg fpmu_double_pipe_pipe_b; // @[Valid.scala:142:26]
reg fpmu_double_pipe_pipe_pipe_v; // @[Valid.scala:141:24]
reg fpmu_double_pipe_pipe_pipe_b; // @[Valid.scala:142:26]
reg fpmu_double_pipe_pipe_pipe_pipe_v; // @[Valid.scala:141:24]
wire fpmu_double_pipe_pipe_pipe_pipe_out_valid = fpmu_double_pipe_pipe_pipe_pipe_v; // @[Valid.scala:135:21, :141:24]
reg fpmu_double_pipe_pipe_pipe_pipe_b; // @[Valid.scala:142:26]
wire fpmu_double_pipe_pipe_pipe_pipe_out_bits = fpmu_double_pipe_pipe_pipe_pipe_b; // @[Valid.scala:135:21, :142:26]
wire _fpu_out_data_T_4 = fpmu_double_pipe_pipe_pipe_pipe_out_bits; // @[Valid.scala:135:21]
wire _io_resp_valid_T = fpiu_out_valid | _fpmu_io_out_valid; // @[Valid.scala:135:21]
wire _io_resp_valid_T_1 = _io_resp_valid_T | _sfma_io_out_valid; // @[fpu.scala:212:20, :232:35, :233:38]
assign _io_resp_valid_T_2 = _io_resp_valid_T_1 | _dfma_io_out_valid; // @[fpu.scala:208:20, :233:38, :234:38]
assign io_resp_valid = _io_resp_valid_T_2; // @[fpu.scala:170:7, :234:38]
wire _fpu_out_data_opts_bigger_swizzledNaN_T_1 = _dfma_io_out_bits_data[31]; // @[FPU.scala:340:8]
wire _fpu_out_data_opts_bigger_swizzledNaN_T_2 = _dfma_io_out_bits_data[32]; // @[FPU.scala:342:8]
wire [30:0] _fpu_out_data_opts_bigger_swizzledNaN_T_3 = _dfma_io_out_bits_data[30:0]; // @[FPU.scala:343:8]
wire [20:0] fpu_out_data_opts_bigger_swizzledNaN_lo_hi = {20'hFFFFF, _fpu_out_data_opts_bigger_swizzledNaN_T_2}; // @[FPU.scala:336:26, :342:8]
wire [51:0] fpu_out_data_opts_bigger_swizzledNaN_lo = {fpu_out_data_opts_bigger_swizzledNaN_lo_hi, _fpu_out_data_opts_bigger_swizzledNaN_T_3}; // @[FPU.scala:336:26, :343:8]
wire [7:0] fpu_out_data_opts_bigger_swizzledNaN_hi_lo = {7'h7F, _fpu_out_data_opts_bigger_swizzledNaN_T_1}; // @[FPU.scala:336:26, :340:8]
wire [12:0] fpu_out_data_opts_bigger_swizzledNaN_hi = {5'h1F, fpu_out_data_opts_bigger_swizzledNaN_hi_lo}; // @[FPU.scala:336:26]
wire [64:0] fpu_out_data_opts_bigger_swizzledNaN = {fpu_out_data_opts_bigger_swizzledNaN_hi, fpu_out_data_opts_bigger_swizzledNaN_lo}; // @[FPU.scala:336:26]
wire [64:0] fpu_out_data_opts_bigger = fpu_out_data_opts_bigger_swizzledNaN; // @[FPU.scala:336:26, :344:8]
wire [64:0] fpu_out_data_opts_0 = fpu_out_data_opts_bigger; // @[FPU.scala:344:8, :398:14]
wire _fpu_out_data_opts_bigger_swizzledNaN_T_5 = _sfma_io_out_bits_data[31]; // @[FPU.scala:340:8]
wire _fpu_out_data_opts_bigger_swizzledNaN_T_6 = _sfma_io_out_bits_data[32]; // @[FPU.scala:342:8]
wire [30:0] _fpu_out_data_opts_bigger_swizzledNaN_T_7 = _sfma_io_out_bits_data[30:0]; // @[FPU.scala:343:8]
wire [20:0] fpu_out_data_opts_bigger_swizzledNaN_lo_hi_1 = {20'hFFFFF, _fpu_out_data_opts_bigger_swizzledNaN_T_6}; // @[FPU.scala:336:26, :342:8]
wire [51:0] fpu_out_data_opts_bigger_swizzledNaN_lo_1 = {fpu_out_data_opts_bigger_swizzledNaN_lo_hi_1, _fpu_out_data_opts_bigger_swizzledNaN_T_7}; // @[FPU.scala:336:26, :343:8]
wire [7:0] fpu_out_data_opts_bigger_swizzledNaN_hi_lo_1 = {7'h7F, _fpu_out_data_opts_bigger_swizzledNaN_T_5}; // @[FPU.scala:336:26, :340:8]
wire [12:0] fpu_out_data_opts_bigger_swizzledNaN_hi_1 = {5'h1F, fpu_out_data_opts_bigger_swizzledNaN_hi_lo_1}; // @[FPU.scala:336:26]
wire [64:0] fpu_out_data_opts_bigger_swizzledNaN_1 = {fpu_out_data_opts_bigger_swizzledNaN_hi_1, fpu_out_data_opts_bigger_swizzledNaN_lo_1}; // @[FPU.scala:336:26]
wire [64:0] fpu_out_data_opts_bigger_1 = fpu_out_data_opts_bigger_swizzledNaN_1; // @[FPU.scala:336:26, :344:8]
wire [64:0] fpu_out_data_opts_0_1 = fpu_out_data_opts_bigger_1; // @[FPU.scala:344:8, :398:14]
wire [64:0] _fpu_out_data_T_3 = fpu_out_data_opts_0_1; // @[package.scala:39:76]
wire _fpu_out_data_opts_bigger_swizzledNaN_T_9 = _fpmu_io_out_bits_data[31]; // @[FPU.scala:340:8]
wire _fpu_out_data_opts_bigger_swizzledNaN_T_10 = _fpmu_io_out_bits_data[32]; // @[FPU.scala:342:8]
wire [30:0] _fpu_out_data_opts_bigger_swizzledNaN_T_11 = _fpmu_io_out_bits_data[30:0]; // @[FPU.scala:343:8]
wire [20:0] fpu_out_data_opts_bigger_swizzledNaN_lo_hi_2 = {20'hFFFFF, _fpu_out_data_opts_bigger_swizzledNaN_T_10}; // @[FPU.scala:336:26, :342:8]
wire [51:0] fpu_out_data_opts_bigger_swizzledNaN_lo_2 = {fpu_out_data_opts_bigger_swizzledNaN_lo_hi_2, _fpu_out_data_opts_bigger_swizzledNaN_T_11}; // @[FPU.scala:336:26, :343:8]
wire [7:0] fpu_out_data_opts_bigger_swizzledNaN_hi_lo_2 = {7'h7F, _fpu_out_data_opts_bigger_swizzledNaN_T_9}; // @[FPU.scala:336:26, :340:8]
wire [12:0] fpu_out_data_opts_bigger_swizzledNaN_hi_2 = {5'h1F, fpu_out_data_opts_bigger_swizzledNaN_hi_lo_2}; // @[FPU.scala:336:26]
wire [64:0] fpu_out_data_opts_bigger_swizzledNaN_2 = {fpu_out_data_opts_bigger_swizzledNaN_hi_2, fpu_out_data_opts_bigger_swizzledNaN_lo_2}; // @[FPU.scala:336:26]
wire [64:0] fpu_out_data_opts_bigger_2 = fpu_out_data_opts_bigger_swizzledNaN_2; // @[FPU.scala:336:26, :344:8]
wire [64:0] fpu_out_data_opts_0_2 = fpu_out_data_opts_bigger_2; // @[FPU.scala:344:8, :398:14]
wire [64:0] _fpu_out_data_T_5 = _fpu_out_data_T_4 ? _fpmu_io_out_bits_data : fpu_out_data_opts_0_2; // @[package.scala:39:{76,86}]
wire [64:0] _fpu_out_data_T_6 = fpiu_out_valid ? fpiu_result_data : _fpu_out_data_T_5; // @[Valid.scala:135:21]
wire [64:0] _fpu_out_data_T_7 = _sfma_io_out_valid ? _fpu_out_data_T_3 : _fpu_out_data_T_6; // @[package.scala:39:76]
wire [64:0] _fpu_out_data_T_1; // @[package.scala:39:76]
assign fpu_out_data = _dfma_io_out_valid ? _fpu_out_data_T_1 : _fpu_out_data_T_7; // @[package.scala:39:76]
assign io_resp_bits_data_0 = fpu_out_data; // @[fpu.scala:170:7, :237:8]
wire [4:0] _fpu_out_exc_T = fpiu_out_valid ? fpiu_result_exc : _fpmu_io_out_bits_exc; // @[Valid.scala:135:21]
wire [4:0] _fpu_out_exc_T_1 = _sfma_io_out_valid ? _sfma_io_out_bits_exc : _fpu_out_exc_T; // @[fpu.scala:212:20, :244:8, :245:8]
assign fpu_out_exc = _dfma_io_out_valid ? _dfma_io_out_bits_exc : _fpu_out_exc_T_1; // @[fpu.scala:208:20, :243:8, :244:8]
assign io_resp_bits_fflags_bits_flags_0 = fpu_out_exc; // @[fpu.scala:170:7, :243:8]
always @(posedge clock) begin // @[fpu.scala:170:7]
fpiu_out_REG <= _fpiu_out_T_1; // @[fpu.scala:219:{30,48}]
if (fpiu_out_REG) begin // @[fpu.scala:219:30]
fpiu_out_pipe_b_in_ldst <= _fpiu_io_out_bits_in_ldst; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_wen <= _fpiu_io_out_bits_in_wen; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_ren1 <= _fpiu_io_out_bits_in_ren1; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_ren2 <= _fpiu_io_out_bits_in_ren2; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_ren3 <= _fpiu_io_out_bits_in_ren3; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_swap12 <= _fpiu_io_out_bits_in_swap12; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_swap23 <= _fpiu_io_out_bits_in_swap23; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_typeTagIn <= _fpiu_io_out_bits_in_typeTagIn; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_typeTagOut <= _fpiu_io_out_bits_in_typeTagOut; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_fromint <= _fpiu_io_out_bits_in_fromint; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_toint <= _fpiu_io_out_bits_in_toint; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_fastpipe <= _fpiu_io_out_bits_in_fastpipe; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_fma <= _fpiu_io_out_bits_in_fma; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_div <= _fpiu_io_out_bits_in_div; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_sqrt <= _fpiu_io_out_bits_in_sqrt; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_wflags <= _fpiu_io_out_bits_in_wflags; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_rm <= _fpiu_io_out_bits_in_rm; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_fmaCmd <= _fpiu_io_out_bits_in_fmaCmd; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_typ <= _fpiu_io_out_bits_in_typ; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_fmt <= _fpiu_io_out_bits_in_fmt; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_in1 <= _fpiu_io_out_bits_in_in1; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_in2 <= _fpiu_io_out_bits_in_in2; // @[Valid.scala:142:26]
fpiu_out_pipe_b_in_in3 <= _fpiu_io_out_bits_in_in3; // @[Valid.scala:142:26]
fpiu_out_pipe_b_lt <= _fpiu_io_out_bits_lt; // @[Valid.scala:142:26]
fpiu_out_pipe_b_store <= _fpiu_io_out_bits_store; // @[Valid.scala:142:26]
fpiu_out_pipe_b_toint <= _fpiu_io_out_bits_toint; // @[Valid.scala:142:26]
fpiu_out_pipe_b_exc <= _fpiu_io_out_bits_exc; // @[Valid.scala:142:26]
end
fpiu_out_pipe_b_in_vec <= ~fpiu_out_REG & fpiu_out_pipe_b_in_vec; // @[Valid.scala:142:26]
if (fpiu_out_pipe_v) begin // @[Valid.scala:141:24]
fpiu_out_pipe_pipe_b_in_ldst <= fpiu_out_pipe_b_in_ldst; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_wen <= fpiu_out_pipe_b_in_wen; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_ren1 <= fpiu_out_pipe_b_in_ren1; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_ren2 <= fpiu_out_pipe_b_in_ren2; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_ren3 <= fpiu_out_pipe_b_in_ren3; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_swap12 <= fpiu_out_pipe_b_in_swap12; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_swap23 <= fpiu_out_pipe_b_in_swap23; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_typeTagIn <= fpiu_out_pipe_b_in_typeTagIn; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_typeTagOut <= fpiu_out_pipe_b_in_typeTagOut; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_fromint <= fpiu_out_pipe_b_in_fromint; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_toint <= fpiu_out_pipe_b_in_toint; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_fastpipe <= fpiu_out_pipe_b_in_fastpipe; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_fma <= fpiu_out_pipe_b_in_fma; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_div <= fpiu_out_pipe_b_in_div; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_sqrt <= fpiu_out_pipe_b_in_sqrt; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_wflags <= fpiu_out_pipe_b_in_wflags; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_vec <= fpiu_out_pipe_b_in_vec; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_rm <= fpiu_out_pipe_b_in_rm; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_fmaCmd <= fpiu_out_pipe_b_in_fmaCmd; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_typ <= fpiu_out_pipe_b_in_typ; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_fmt <= fpiu_out_pipe_b_in_fmt; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_in1 <= fpiu_out_pipe_b_in_in1; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_in2 <= fpiu_out_pipe_b_in_in2; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_in_in3 <= fpiu_out_pipe_b_in_in3; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_lt <= fpiu_out_pipe_b_lt; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_store <= fpiu_out_pipe_b_store; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_toint <= fpiu_out_pipe_b_toint; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_b_exc <= fpiu_out_pipe_b_exc; // @[Valid.scala:142:26]
end
if (fpiu_out_pipe_pipe_v) begin // @[Valid.scala:141:24]
fpiu_out_pipe_pipe_pipe_b_in_ldst <= fpiu_out_pipe_pipe_b_in_ldst; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_wen <= fpiu_out_pipe_pipe_b_in_wen; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_ren1 <= fpiu_out_pipe_pipe_b_in_ren1; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_ren2 <= fpiu_out_pipe_pipe_b_in_ren2; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_ren3 <= fpiu_out_pipe_pipe_b_in_ren3; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_swap12 <= fpiu_out_pipe_pipe_b_in_swap12; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_swap23 <= fpiu_out_pipe_pipe_b_in_swap23; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_typeTagIn <= fpiu_out_pipe_pipe_b_in_typeTagIn; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_typeTagOut <= fpiu_out_pipe_pipe_b_in_typeTagOut; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_fromint <= fpiu_out_pipe_pipe_b_in_fromint; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_toint <= fpiu_out_pipe_pipe_b_in_toint; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_fastpipe <= fpiu_out_pipe_pipe_b_in_fastpipe; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_fma <= fpiu_out_pipe_pipe_b_in_fma; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_div <= fpiu_out_pipe_pipe_b_in_div; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_sqrt <= fpiu_out_pipe_pipe_b_in_sqrt; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_wflags <= fpiu_out_pipe_pipe_b_in_wflags; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_vec <= fpiu_out_pipe_pipe_b_in_vec; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_rm <= fpiu_out_pipe_pipe_b_in_rm; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_fmaCmd <= fpiu_out_pipe_pipe_b_in_fmaCmd; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_typ <= fpiu_out_pipe_pipe_b_in_typ; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_fmt <= fpiu_out_pipe_pipe_b_in_fmt; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_in1 <= fpiu_out_pipe_pipe_b_in_in1; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_in2 <= fpiu_out_pipe_pipe_b_in_in2; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_in_in3 <= fpiu_out_pipe_pipe_b_in_in3; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_lt <= fpiu_out_pipe_pipe_b_lt; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_store <= fpiu_out_pipe_pipe_b_store; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_toint <= fpiu_out_pipe_pipe_b_toint; // @[Valid.scala:142:26]
fpiu_out_pipe_pipe_pipe_b_exc <= fpiu_out_pipe_pipe_b_exc; // @[Valid.scala:142:26]
end
if (_fpmu_double_T) // @[fpu.scala:229:39]
fpmu_double_pipe_b <= _fpmu_double_T_1; // @[Valid.scala:142:26]
if (fpmu_double_pipe_v) // @[Valid.scala:141:24]
fpmu_double_pipe_pipe_b <= fpmu_double_pipe_b; // @[Valid.scala:142:26]
if (fpmu_double_pipe_pipe_v) // @[Valid.scala:141:24]
fpmu_double_pipe_pipe_pipe_b <= fpmu_double_pipe_pipe_b; // @[Valid.scala:142:26]
if (fpmu_double_pipe_pipe_pipe_v) // @[Valid.scala:141:24]
fpmu_double_pipe_pipe_pipe_pipe_b <= fpmu_double_pipe_pipe_pipe_b; // @[Valid.scala:142:26]
if (reset) begin // @[fpu.scala:170:7]
fpiu_out_pipe_v <= 1'h0; // @[Valid.scala:141:24]
fpiu_out_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24]
fpiu_out_pipe_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24]
fpmu_double_pipe_v <= 1'h0; // @[Valid.scala:141:24]
fpmu_double_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24]
fpmu_double_pipe_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24]
fpmu_double_pipe_pipe_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24]
end
else begin // @[fpu.scala:170:7]
fpiu_out_pipe_v <= fpiu_out_REG; // @[Valid.scala:141:24]
fpiu_out_pipe_pipe_v <= fpiu_out_pipe_v; // @[Valid.scala:141:24]
fpiu_out_pipe_pipe_pipe_v <= fpiu_out_pipe_pipe_v; // @[Valid.scala:141:24]
fpmu_double_pipe_v <= _fpmu_double_T; // @[Valid.scala:141:24]
fpmu_double_pipe_pipe_v <= fpmu_double_pipe_v; // @[Valid.scala:141:24]
fpmu_double_pipe_pipe_pipe_v <= fpmu_double_pipe_pipe_v; // @[Valid.scala:141:24]
fpmu_double_pipe_pipe_pipe_pipe_v <= fpmu_double_pipe_pipe_pipe_v; // @[Valid.scala:141:24]
end
always @(posedge)
UOPCodeFPUDecoder_3 fp_decoder ( // @[fpu.scala:182:26]
.clock (clock),
.reset (reset),
.io_uopc (io_req_bits_uop_uopc_0), // @[fpu.scala:170:7]
.io_sigs_ldst (_fp_decoder_io_sigs_ldst),
.io_sigs_wen (_fp_decoder_io_sigs_wen),
.io_sigs_ren1 (_fp_decoder_io_sigs_ren1),
.io_sigs_ren2 (_fp_decoder_io_sigs_ren2),
.io_sigs_ren3 (_fp_decoder_io_sigs_ren3),
.io_sigs_swap12 (_fp_decoder_io_sigs_swap12),
.io_sigs_swap23 (_fp_decoder_io_sigs_swap23),
.io_sigs_typeTagIn (_fp_decoder_io_sigs_typeTagIn),
.io_sigs_typeTagOut (_fp_decoder_io_sigs_typeTagOut),
.io_sigs_fromint (_fp_decoder_io_sigs_fromint),
.io_sigs_toint (_fp_decoder_io_sigs_toint),
.io_sigs_fastpipe (_fp_decoder_io_sigs_fastpipe),
.io_sigs_fma (_fp_decoder_io_sigs_fma),
.io_sigs_div (_fp_decoder_io_sigs_div),
.io_sigs_sqrt (_fp_decoder_io_sigs_sqrt),
.io_sigs_wflags (_fp_decoder_io_sigs_wflags)
); // @[fpu.scala:182:26]
assign dfma_io_in_bits_req_ldst = _fp_decoder_io_sigs_ldst; // @[fpu.scala:182:26, :188:19]
assign dfma_io_in_bits_req_wen = _fp_decoder_io_sigs_wen; // @[fpu.scala:182:26, :188:19]
assign dfma_io_in_bits_req_ren1 = _fp_decoder_io_sigs_ren1; // @[fpu.scala:182:26, :188:19]
assign dfma_io_in_bits_req_ren2 = _fp_decoder_io_sigs_ren2; // @[fpu.scala:182:26, :188:19]
assign dfma_io_in_bits_req_ren3 = _fp_decoder_io_sigs_ren3; // @[fpu.scala:182:26, :188:19]
assign dfma_io_in_bits_req_swap12 = _fp_decoder_io_sigs_swap12; // @[fpu.scala:182:26, :188:19]
assign dfma_io_in_bits_req_swap23 = _fp_decoder_io_sigs_swap23; // @[fpu.scala:182:26, :188:19]
assign dfma_io_in_bits_req_typeTagIn = _fp_decoder_io_sigs_typeTagIn; // @[fpu.scala:182:26, :188:19]
assign dfma_io_in_bits_req_typeTagOut = _fp_decoder_io_sigs_typeTagOut; // @[fpu.scala:182:26, :188:19]
assign dfma_io_in_bits_req_fromint = _fp_decoder_io_sigs_fromint; // @[fpu.scala:182:26, :188:19]
assign dfma_io_in_bits_req_toint = _fp_decoder_io_sigs_toint; // @[fpu.scala:182:26, :188:19]
assign dfma_io_in_bits_req_fastpipe = _fp_decoder_io_sigs_fastpipe; // @[fpu.scala:182:26, :188:19]
assign dfma_io_in_bits_req_fma = _fp_decoder_io_sigs_fma; // @[fpu.scala:182:26, :188:19]
assign dfma_io_in_bits_req_div = _fp_decoder_io_sigs_div; // @[fpu.scala:182:26, :188:19]
assign dfma_io_in_bits_req_sqrt = _fp_decoder_io_sigs_sqrt; // @[fpu.scala:182:26, :188:19]
assign dfma_io_in_bits_req_wflags = _fp_decoder_io_sigs_wflags; // @[fpu.scala:182:26, :188:19]
assign sfma_io_in_bits_req_ldst = _fp_decoder_io_sigs_ldst; // @[fpu.scala:182:26, :188:19]
assign sfma_io_in_bits_req_wen = _fp_decoder_io_sigs_wen; // @[fpu.scala:182:26, :188:19]
assign sfma_io_in_bits_req_ren1 = _fp_decoder_io_sigs_ren1; // @[fpu.scala:182:26, :188:19]
assign sfma_io_in_bits_req_ren2 = _fp_decoder_io_sigs_ren2; // @[fpu.scala:182:26, :188:19]
assign sfma_io_in_bits_req_ren3 = _fp_decoder_io_sigs_ren3; // @[fpu.scala:182:26, :188:19]
assign sfma_io_in_bits_req_swap12 = _fp_decoder_io_sigs_swap12; // @[fpu.scala:182:26, :188:19]
assign sfma_io_in_bits_req_swap23 = _fp_decoder_io_sigs_swap23; // @[fpu.scala:182:26, :188:19]
assign sfma_io_in_bits_req_typeTagIn = _fp_decoder_io_sigs_typeTagIn; // @[fpu.scala:182:26, :188:19]
assign sfma_io_in_bits_req_typeTagOut = _fp_decoder_io_sigs_typeTagOut; // @[fpu.scala:182:26, :188:19]
assign sfma_io_in_bits_req_fromint = _fp_decoder_io_sigs_fromint; // @[fpu.scala:182:26, :188:19]
assign sfma_io_in_bits_req_toint = _fp_decoder_io_sigs_toint; // @[fpu.scala:182:26, :188:19]
assign sfma_io_in_bits_req_fastpipe = _fp_decoder_io_sigs_fastpipe; // @[fpu.scala:182:26, :188:19]
assign sfma_io_in_bits_req_fma = _fp_decoder_io_sigs_fma; // @[fpu.scala:182:26, :188:19]
assign sfma_io_in_bits_req_div = _fp_decoder_io_sigs_div; // @[fpu.scala:182:26, :188:19]
assign sfma_io_in_bits_req_sqrt = _fp_decoder_io_sigs_sqrt; // @[fpu.scala:182:26, :188:19]
assign sfma_io_in_bits_req_wflags = _fp_decoder_io_sigs_wflags; // @[fpu.scala:182:26, :188:19]
assign fpiu_io_in_bits_req_ldst = _fp_decoder_io_sigs_ldst; // @[fpu.scala:182:26, :188:19]
assign fpiu_io_in_bits_req_wen = _fp_decoder_io_sigs_wen; // @[fpu.scala:182:26, :188:19]
assign fpiu_io_in_bits_req_ren1 = _fp_decoder_io_sigs_ren1; // @[fpu.scala:182:26, :188:19]
assign fpiu_io_in_bits_req_ren2 = _fp_decoder_io_sigs_ren2; // @[fpu.scala:182:26, :188:19]
assign fpiu_io_in_bits_req_ren3 = _fp_decoder_io_sigs_ren3; // @[fpu.scala:182:26, :188:19]
assign fpiu_io_in_bits_req_swap12 = _fp_decoder_io_sigs_swap12; // @[fpu.scala:182:26, :188:19]
assign fpiu_io_in_bits_req_swap23 = _fp_decoder_io_sigs_swap23; // @[fpu.scala:182:26, :188:19]
assign fpiu_io_in_bits_req_typeTagIn = _fp_decoder_io_sigs_typeTagIn; // @[fpu.scala:182:26, :188:19]
assign fpiu_io_in_bits_req_typeTagOut = _fp_decoder_io_sigs_typeTagOut; // @[fpu.scala:182:26, :188:19]
assign fpiu_io_in_bits_req_fromint = _fp_decoder_io_sigs_fromint; // @[fpu.scala:182:26, :188:19]
assign fpiu_io_in_bits_req_toint = _fp_decoder_io_sigs_toint; // @[fpu.scala:182:26, :188:19]
assign fpiu_io_in_bits_req_fastpipe = _fp_decoder_io_sigs_fastpipe; // @[fpu.scala:182:26, :188:19]
assign fpiu_io_in_bits_req_fma = _fp_decoder_io_sigs_fma; // @[fpu.scala:182:26, :188:19]
assign fpiu_io_in_bits_req_div = _fp_decoder_io_sigs_div; // @[fpu.scala:182:26, :188:19]
assign fpiu_io_in_bits_req_sqrt = _fp_decoder_io_sigs_sqrt; // @[fpu.scala:182:26, :188:19]
assign fpiu_io_in_bits_req_wflags = _fp_decoder_io_sigs_wflags; // @[fpu.scala:182:26, :188:19]
assign _fpiu_io_in_bits_req_in1_truncIdx_T = _fp_decoder_io_sigs_typeTagIn; // @[package.scala:38:21]
assign _fpiu_io_in_bits_req_in1_truncIdx_T_1 = _fp_decoder_io_sigs_typeTagIn; // @[package.scala:38:21]
assign _fpiu_io_in_bits_req_in2_truncIdx_T = _fp_decoder_io_sigs_typeTagIn; // @[package.scala:38:21]
assign _fpiu_io_in_bits_req_in2_truncIdx_T_1 = _fp_decoder_io_sigs_typeTagIn; // @[package.scala:38:21]
assign _fpiu_io_in_bits_req_in3_truncIdx_T = _fp_decoder_io_sigs_typeTagIn; // @[package.scala:38:21]
assign _fpiu_io_in_bits_req_in3_truncIdx_T_1 = _fp_decoder_io_sigs_typeTagIn; // @[package.scala:38:21]
FPUFMAPipe_l4_f64_3 dfma ( // @[fpu.scala:208:20]
.clock (clock),
.reset (reset),
.io_in_valid (_dfma_io_in_valid_T_2), // @[fpu.scala:209:51]
.io_in_bits_ldst (dfma_io_in_bits_req_ldst), // @[fpu.scala:188:19]
.io_in_bits_wen (dfma_io_in_bits_req_wen), // @[fpu.scala:188:19]
.io_in_bits_ren1 (dfma_io_in_bits_req_ren1), // @[fpu.scala:188:19]
.io_in_bits_ren2 (dfma_io_in_bits_req_ren2), // @[fpu.scala:188:19]
.io_in_bits_ren3 (dfma_io_in_bits_req_ren3), // @[fpu.scala:188:19]
.io_in_bits_swap12 (dfma_io_in_bits_req_swap12), // @[fpu.scala:188:19]
.io_in_bits_swap23 (dfma_io_in_bits_req_swap23), // @[fpu.scala:188:19]
.io_in_bits_typeTagIn (dfma_io_in_bits_req_typeTagIn), // @[fpu.scala:188:19]
.io_in_bits_typeTagOut (dfma_io_in_bits_req_typeTagOut), // @[fpu.scala:188:19]
.io_in_bits_fromint (dfma_io_in_bits_req_fromint), // @[fpu.scala:188:19]
.io_in_bits_toint (dfma_io_in_bits_req_toint), // @[fpu.scala:188:19]
.io_in_bits_fastpipe (dfma_io_in_bits_req_fastpipe), // @[fpu.scala:188:19]
.io_in_bits_fma (dfma_io_in_bits_req_fma), // @[fpu.scala:188:19]
.io_in_bits_div (dfma_io_in_bits_req_div), // @[fpu.scala:188:19]
.io_in_bits_sqrt (dfma_io_in_bits_req_sqrt), // @[fpu.scala:188:19]
.io_in_bits_wflags (dfma_io_in_bits_req_wflags), // @[fpu.scala:188:19]
.io_in_bits_rm (dfma_io_in_bits_req_rm), // @[fpu.scala:188:19]
.io_in_bits_fmaCmd (dfma_io_in_bits_req_fmaCmd), // @[fpu.scala:188:19]
.io_in_bits_typ (dfma_io_in_bits_req_typ), // @[fpu.scala:188:19]
.io_in_bits_fmt (dfma_io_in_bits_req_fmt), // @[fpu.scala:188:19]
.io_in_bits_in1 (dfma_io_in_bits_req_in1), // @[fpu.scala:188:19]
.io_in_bits_in2 (dfma_io_in_bits_req_in2), // @[fpu.scala:188:19]
.io_in_bits_in3 (dfma_io_in_bits_req_in3), // @[fpu.scala:188:19]
.io_out_valid (_dfma_io_out_valid),
.io_out_bits_data (_dfma_io_out_bits_data),
.io_out_bits_exc (_dfma_io_out_bits_exc)
); // @[fpu.scala:208:20]
assign _fpu_out_data_T_1 = _dfma_io_out_bits_data; // @[package.scala:39:76]
FMADecoder_3 dfma_io_in_bits_fma_decoder ( // @[fpu.scala:202:29]
.clock (clock),
.reset (reset),
.io_uopc (io_req_bits_uop_uopc_0), // @[fpu.scala:170:7]
.io_cmd (dfma_io_in_bits_req_fmaCmd)
); // @[fpu.scala:202:29]
FPUFMAPipe_l4_f32_1 sfma ( // @[fpu.scala:212:20]
.clock (clock),
.reset (reset),
.io_in_valid (_sfma_io_in_valid_T_2), // @[fpu.scala:213:51]
.io_in_bits_ldst (sfma_io_in_bits_req_ldst), // @[fpu.scala:188:19]
.io_in_bits_wen (sfma_io_in_bits_req_wen), // @[fpu.scala:188:19]
.io_in_bits_ren1 (sfma_io_in_bits_req_ren1), // @[fpu.scala:188:19]
.io_in_bits_ren2 (sfma_io_in_bits_req_ren2), // @[fpu.scala:188:19]
.io_in_bits_ren3 (sfma_io_in_bits_req_ren3), // @[fpu.scala:188:19]
.io_in_bits_swap12 (sfma_io_in_bits_req_swap12), // @[fpu.scala:188:19]
.io_in_bits_swap23 (sfma_io_in_bits_req_swap23), // @[fpu.scala:188:19]
.io_in_bits_typeTagIn (sfma_io_in_bits_req_typeTagIn), // @[fpu.scala:188:19]
.io_in_bits_typeTagOut (sfma_io_in_bits_req_typeTagOut), // @[fpu.scala:188:19]
.io_in_bits_fromint (sfma_io_in_bits_req_fromint), // @[fpu.scala:188:19]
.io_in_bits_toint (sfma_io_in_bits_req_toint), // @[fpu.scala:188:19]
.io_in_bits_fastpipe (sfma_io_in_bits_req_fastpipe), // @[fpu.scala:188:19]
.io_in_bits_fma (sfma_io_in_bits_req_fma), // @[fpu.scala:188:19]
.io_in_bits_div (sfma_io_in_bits_req_div), // @[fpu.scala:188:19]
.io_in_bits_sqrt (sfma_io_in_bits_req_sqrt), // @[fpu.scala:188:19]
.io_in_bits_wflags (sfma_io_in_bits_req_wflags), // @[fpu.scala:188:19]
.io_in_bits_rm (sfma_io_in_bits_req_rm), // @[fpu.scala:188:19]
.io_in_bits_fmaCmd (sfma_io_in_bits_req_fmaCmd), // @[fpu.scala:188:19]
.io_in_bits_typ (sfma_io_in_bits_req_typ), // @[fpu.scala:188:19]
.io_in_bits_fmt (sfma_io_in_bits_req_fmt), // @[fpu.scala:188:19]
.io_in_bits_in1 (sfma_io_in_bits_req_in1), // @[fpu.scala:188:19]
.io_in_bits_in2 (sfma_io_in_bits_req_in2), // @[fpu.scala:188:19]
.io_in_bits_in3 (sfma_io_in_bits_req_in3), // @[fpu.scala:188:19]
.io_out_valid (_sfma_io_out_valid),
.io_out_bits_data (_sfma_io_out_bits_data),
.io_out_bits_exc (_sfma_io_out_bits_exc)
); // @[fpu.scala:212:20]
FMADecoder_4 sfma_io_in_bits_fma_decoder ( // @[fpu.scala:202:29]
.clock (clock),
.reset (reset),
.io_uopc (io_req_bits_uop_uopc_0), // @[fpu.scala:170:7]
.io_cmd (sfma_io_in_bits_req_fmaCmd)
); // @[fpu.scala:202:29]
FPToInt_3 fpiu ( // @[fpu.scala:216:20]
.clock (clock),
.reset (reset),
.io_in_valid (_fpiu_io_in_valid_T_2), // @[fpu.scala:217:36]
.io_in_bits_ldst (fpiu_io_in_bits_req_ldst), // @[fpu.scala:188:19]
.io_in_bits_wen (fpiu_io_in_bits_req_wen), // @[fpu.scala:188:19]
.io_in_bits_ren1 (fpiu_io_in_bits_req_ren1), // @[fpu.scala:188:19]
.io_in_bits_ren2 (fpiu_io_in_bits_req_ren2), // @[fpu.scala:188:19]
.io_in_bits_ren3 (fpiu_io_in_bits_req_ren3), // @[fpu.scala:188:19]
.io_in_bits_swap12 (fpiu_io_in_bits_req_swap12), // @[fpu.scala:188:19]
.io_in_bits_swap23 (fpiu_io_in_bits_req_swap23), // @[fpu.scala:188:19]
.io_in_bits_typeTagIn (fpiu_io_in_bits_req_typeTagIn), // @[fpu.scala:188:19]
.io_in_bits_typeTagOut (fpiu_io_in_bits_req_typeTagOut), // @[fpu.scala:188:19]
.io_in_bits_fromint (fpiu_io_in_bits_req_fromint), // @[fpu.scala:188:19]
.io_in_bits_toint (fpiu_io_in_bits_req_toint), // @[fpu.scala:188:19]
.io_in_bits_fastpipe (fpiu_io_in_bits_req_fastpipe), // @[fpu.scala:188:19]
.io_in_bits_fma (fpiu_io_in_bits_req_fma), // @[fpu.scala:188:19]
.io_in_bits_div (fpiu_io_in_bits_req_div), // @[fpu.scala:188:19]
.io_in_bits_sqrt (fpiu_io_in_bits_req_sqrt), // @[fpu.scala:188:19]
.io_in_bits_wflags (fpiu_io_in_bits_req_wflags), // @[fpu.scala:188:19]
.io_in_bits_rm (fpiu_io_in_bits_req_rm), // @[fpu.scala:188:19]
.io_in_bits_fmaCmd (fpiu_io_in_bits_req_fmaCmd), // @[fpu.scala:188:19]
.io_in_bits_typ (fpiu_io_in_bits_req_typ), // @[fpu.scala:188:19]
.io_in_bits_fmt (fpiu_io_in_bits_req_fmt), // @[fpu.scala:188:19]
.io_in_bits_in1 (fpiu_io_in_bits_req_in1), // @[fpu.scala:188:19]
.io_in_bits_in2 (fpiu_io_in_bits_req_in2), // @[fpu.scala:188:19]
.io_in_bits_in3 (fpiu_io_in_bits_req_in3), // @[fpu.scala:188:19]
.io_out_bits_in_ldst (_fpiu_io_out_bits_in_ldst),
.io_out_bits_in_wen (_fpiu_io_out_bits_in_wen),
.io_out_bits_in_ren1 (_fpiu_io_out_bits_in_ren1),
.io_out_bits_in_ren2 (_fpiu_io_out_bits_in_ren2),
.io_out_bits_in_ren3 (_fpiu_io_out_bits_in_ren3),
.io_out_bits_in_swap12 (_fpiu_io_out_bits_in_swap12),
.io_out_bits_in_swap23 (_fpiu_io_out_bits_in_swap23),
.io_out_bits_in_typeTagIn (_fpiu_io_out_bits_in_typeTagIn),
.io_out_bits_in_typeTagOut (_fpiu_io_out_bits_in_typeTagOut),
.io_out_bits_in_fromint (_fpiu_io_out_bits_in_fromint),
.io_out_bits_in_toint (_fpiu_io_out_bits_in_toint),
.io_out_bits_in_fastpipe (_fpiu_io_out_bits_in_fastpipe),
.io_out_bits_in_fma (_fpiu_io_out_bits_in_fma),
.io_out_bits_in_div (_fpiu_io_out_bits_in_div),
.io_out_bits_in_sqrt (_fpiu_io_out_bits_in_sqrt),
.io_out_bits_in_wflags (_fpiu_io_out_bits_in_wflags),
.io_out_bits_in_rm (_fpiu_io_out_bits_in_rm),
.io_out_bits_in_fmaCmd (_fpiu_io_out_bits_in_fmaCmd),
.io_out_bits_in_typ (_fpiu_io_out_bits_in_typ),
.io_out_bits_in_fmt (_fpiu_io_out_bits_in_fmt),
.io_out_bits_in_in1 (_fpiu_io_out_bits_in_in1),
.io_out_bits_in_in2 (_fpiu_io_out_bits_in_in2),
.io_out_bits_in_in3 (_fpiu_io_out_bits_in_in3),
.io_out_bits_lt (_fpiu_io_out_bits_lt),
.io_out_bits_store (_fpiu_io_out_bits_store),
.io_out_bits_toint (_fpiu_io_out_bits_toint),
.io_out_bits_exc (_fpiu_io_out_bits_exc)
); // @[fpu.scala:216:20]
FMADecoder_5 fpiu_io_in_bits_fma_decoder ( // @[fpu.scala:202:29]
.clock (clock),
.reset (reset),
.io_uopc (io_req_bits_uop_uopc_0), // @[fpu.scala:170:7]
.io_cmd (fpiu_io_in_bits_req_fmaCmd)
); // @[fpu.scala:202:29]
FPToFP_3 fpmu ( // @[fpu.scala:225:20]
.clock (clock),
.reset (reset),
.io_in_valid (_fpmu_io_in_valid_T), // @[fpu.scala:226:36]
.io_in_bits_ldst (fpiu_io_in_bits_req_ldst), // @[fpu.scala:188:19]
.io_in_bits_wen (fpiu_io_in_bits_req_wen), // @[fpu.scala:188:19]
.io_in_bits_ren1 (fpiu_io_in_bits_req_ren1), // @[fpu.scala:188:19]
.io_in_bits_ren2 (fpiu_io_in_bits_req_ren2), // @[fpu.scala:188:19]
.io_in_bits_ren3 (fpiu_io_in_bits_req_ren3), // @[fpu.scala:188:19]
.io_in_bits_swap12 (fpiu_io_in_bits_req_swap12), // @[fpu.scala:188:19]
.io_in_bits_swap23 (fpiu_io_in_bits_req_swap23), // @[fpu.scala:188:19]
.io_in_bits_typeTagIn (fpiu_io_in_bits_req_typeTagIn), // @[fpu.scala:188:19]
.io_in_bits_typeTagOut (fpiu_io_in_bits_req_typeTagOut), // @[fpu.scala:188:19]
.io_in_bits_fromint (fpiu_io_in_bits_req_fromint), // @[fpu.scala:188:19]
.io_in_bits_toint (fpiu_io_in_bits_req_toint), // @[fpu.scala:188:19]
.io_in_bits_fastpipe (fpiu_io_in_bits_req_fastpipe), // @[fpu.scala:188:19]
.io_in_bits_fma (fpiu_io_in_bits_req_fma), // @[fpu.scala:188:19]
.io_in_bits_div (fpiu_io_in_bits_req_div), // @[fpu.scala:188:19]
.io_in_bits_sqrt (fpiu_io_in_bits_req_sqrt), // @[fpu.scala:188:19]
.io_in_bits_wflags (fpiu_io_in_bits_req_wflags), // @[fpu.scala:188:19]
.io_in_bits_rm (fpiu_io_in_bits_req_rm), // @[fpu.scala:188:19]
.io_in_bits_fmaCmd (fpiu_io_in_bits_req_fmaCmd), // @[fpu.scala:188:19]
.io_in_bits_typ (fpiu_io_in_bits_req_typ), // @[fpu.scala:188:19]
.io_in_bits_fmt (fpiu_io_in_bits_req_fmt), // @[fpu.scala:188:19]
.io_in_bits_in1 (fpiu_io_in_bits_req_in1), // @[fpu.scala:188:19]
.io_in_bits_in2 (fpiu_io_in_bits_req_in2), // @[fpu.scala:188:19]
.io_in_bits_in3 (fpiu_io_in_bits_req_in3), // @[fpu.scala:188:19]
.io_out_valid (_fpmu_io_out_valid),
.io_out_bits_data (_fpmu_io_out_bits_data),
.io_out_bits_exc (_fpmu_io_out_bits_exc),
.io_lt (_fpiu_io_out_bits_lt) // @[fpu.scala:216:20]
); // @[fpu.scala:225:20]
assign io_resp_bits_data = io_resp_bits_data_0; // @[fpu.scala:170:7]
assign io_resp_bits_fflags_valid = io_resp_bits_fflags_valid_0; // @[fpu.scala:170:7]
assign io_resp_bits_fflags_bits_flags = io_resp_bits_fflags_bits_flags_0; // @[fpu.scala:170:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File LatencyInjectionQueue.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
import freechips.rocketchip.util.DecoupledHelper
class LatencyInjectionQueue[T <: Data](data: T, depth: Int) extends Module {
val io = IO(new Bundle {
val latency_cycles = Input(UInt(64.W))
val enq = Flipped(Decoupled(data))
val deq = Decoupled(data)
})
val cur_cycle = RegInit(0.U(64.W))
cur_cycle := cur_cycle + 1.U
val queue = Module(new Queue(data, depth))
val release_ready_cycle_q = Module(new Queue(UInt(64.W), depth))
release_ready_cycle_q.io.enq.bits := cur_cycle + io.latency_cycles
queue.io.enq.bits := io.enq.bits
io.deq.bits := queue.io.deq.bits
val enq_fire = DecoupledHelper(
queue.io.enq.ready,
release_ready_cycle_q.io.enq.ready,
io.enq.valid
)
queue.io.enq.valid := enq_fire.fire(queue.io.enq.ready)
release_ready_cycle_q.io.enq.valid := enq_fire.fire(release_ready_cycle_q.io.enq.ready)
io.enq.ready := enq_fire.fire(io.enq.valid)
val deq_fire = DecoupledHelper(
queue.io.deq.valid,
release_ready_cycle_q.io.deq.valid,
release_ready_cycle_q.io.deq.bits <= cur_cycle,
io.deq.ready
)
queue.io.deq.ready := deq_fire.fire(queue.io.deq.valid)
release_ready_cycle_q.io.deq.ready := deq_fire.fire(release_ready_cycle_q.io.deq.valid)
io.deq.valid := deq_fire.fire(io.deq.ready)
}
|
module LatencyInjectionQueue_22( // @[LatencyInjectionQueue.scala:9:7]
input clock, // @[LatencyInjectionQueue.scala:9:7]
input reset, // @[LatencyInjectionQueue.scala:9:7]
input [63:0] io_latency_cycles, // @[LatencyInjectionQueue.scala:10:14]
output io_enq_ready, // @[LatencyInjectionQueue.scala:10:14]
input io_enq_valid, // @[LatencyInjectionQueue.scala:10:14]
input [2:0] io_enq_bits_opcode, // @[LatencyInjectionQueue.scala:10:14]
input [3:0] io_enq_bits_size, // @[LatencyInjectionQueue.scala:10:14]
input [4:0] io_enq_bits_source, // @[LatencyInjectionQueue.scala:10:14]
input [31:0] io_enq_bits_address, // @[LatencyInjectionQueue.scala:10:14]
input [31:0] io_enq_bits_mask, // @[LatencyInjectionQueue.scala:10:14]
input [255:0] io_enq_bits_data, // @[LatencyInjectionQueue.scala:10:14]
input io_deq_ready, // @[LatencyInjectionQueue.scala:10:14]
output io_deq_valid, // @[LatencyInjectionQueue.scala:10:14]
output [2:0] io_deq_bits_opcode, // @[LatencyInjectionQueue.scala:10:14]
output [2:0] io_deq_bits_param, // @[LatencyInjectionQueue.scala:10:14]
output [3:0] io_deq_bits_size, // @[LatencyInjectionQueue.scala:10:14]
output [4:0] io_deq_bits_source, // @[LatencyInjectionQueue.scala:10:14]
output [31:0] io_deq_bits_address, // @[LatencyInjectionQueue.scala:10:14]
output [31:0] io_deq_bits_mask, // @[LatencyInjectionQueue.scala:10:14]
output [255:0] io_deq_bits_data, // @[LatencyInjectionQueue.scala:10:14]
output io_deq_bits_corrupt // @[LatencyInjectionQueue.scala:10:14]
);
wire _release_ready_cycle_q_io_enq_ready; // @[LatencyInjectionQueue.scala:19:37]
wire _release_ready_cycle_q_io_deq_valid; // @[LatencyInjectionQueue.scala:19:37]
wire [63:0] _release_ready_cycle_q_io_deq_bits; // @[LatencyInjectionQueue.scala:19:37]
wire _queue_io_enq_ready; // @[LatencyInjectionQueue.scala:18:21]
wire _queue_io_deq_valid; // @[LatencyInjectionQueue.scala:18:21]
wire [63:0] io_latency_cycles_0 = io_latency_cycles; // @[LatencyInjectionQueue.scala:9:7]
wire io_enq_valid_0 = io_enq_valid; // @[LatencyInjectionQueue.scala:9:7]
wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[LatencyInjectionQueue.scala:9:7]
wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[LatencyInjectionQueue.scala:9:7]
wire [4:0] io_enq_bits_source_0 = io_enq_bits_source; // @[LatencyInjectionQueue.scala:9:7]
wire [31:0] io_enq_bits_address_0 = io_enq_bits_address; // @[LatencyInjectionQueue.scala:9:7]
wire [31:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[LatencyInjectionQueue.scala:9:7]
wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[LatencyInjectionQueue.scala:9:7]
wire io_deq_ready_0 = io_deq_ready; // @[LatencyInjectionQueue.scala:9:7]
wire io_enq_bits_corrupt = 1'h0; // @[LatencyInjectionQueue.scala:9:7, :10:14, :18:21]
wire [2:0] io_enq_bits_param = 3'h0; // @[LatencyInjectionQueue.scala:9:7, :10:14, :18:21]
wire _io_enq_ready_T; // @[Misc.scala:26:53]
wire _io_deq_valid_T_1; // @[Misc.scala:26:53]
wire io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7]
wire [2:0] io_deq_bits_opcode_0; // @[LatencyInjectionQueue.scala:9:7]
wire [2:0] io_deq_bits_param_0; // @[LatencyInjectionQueue.scala:9:7]
wire [3:0] io_deq_bits_size_0; // @[LatencyInjectionQueue.scala:9:7]
wire [4:0] io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7]
wire [31:0] io_deq_bits_address_0; // @[LatencyInjectionQueue.scala:9:7]
wire [31:0] io_deq_bits_mask_0; // @[LatencyInjectionQueue.scala:9:7]
wire [255:0] io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7]
wire io_deq_bits_corrupt_0; // @[LatencyInjectionQueue.scala:9:7]
wire io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7]
reg [63:0] cur_cycle; // @[LatencyInjectionQueue.scala:16:26]
wire [64:0] _GEN = {1'h0, cur_cycle}; // @[LatencyInjectionQueue.scala:9:7, :10:14, :16:26, :17:26, :18:21]
wire [64:0] _cur_cycle_T = _GEN + 65'h1; // @[LatencyInjectionQueue.scala:17:26]
wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[LatencyInjectionQueue.scala:17:26]
wire [64:0] _release_ready_cycle_q_io_enq_bits_T = _GEN + {1'h0, io_latency_cycles_0}; // @[LatencyInjectionQueue.scala:9:7, :10:14, :17:26, :18:21, :21:50]
wire [63:0] _release_ready_cycle_q_io_enq_bits_T_1 = _release_ready_cycle_q_io_enq_bits_T[63:0]; // @[LatencyInjectionQueue.scala:21:50]
wire _queue_io_enq_valid_T = _release_ready_cycle_q_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53]
wire _release_ready_cycle_q_io_enq_valid_T = _queue_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53]
assign _io_enq_ready_T = _queue_io_enq_ready & _release_ready_cycle_q_io_enq_ready; // @[Misc.scala:26:53]
assign io_enq_ready_0 = _io_enq_ready_T; // @[Misc.scala:26:53]
wire _T = _release_ready_cycle_q_io_deq_bits <= cur_cycle; // @[LatencyInjectionQueue.scala:16:26, :19:37, :38:39]
wire _queue_io_deq_ready_T = _release_ready_cycle_q_io_deq_valid & _T; // @[Misc.scala:26:53]
wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53]
wire _release_ready_cycle_q_io_deq_ready_T = _queue_io_deq_valid & _T; // @[Misc.scala:26:53]
wire _release_ready_cycle_q_io_deq_ready_T_1 = _release_ready_cycle_q_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53]
wire _io_deq_valid_T = _queue_io_deq_valid & _release_ready_cycle_q_io_deq_valid; // @[Misc.scala:26:53]
assign _io_deq_valid_T_1 = _io_deq_valid_T & _T; // @[Misc.scala:26:53]
assign io_deq_valid_0 = _io_deq_valid_T_1; // @[Misc.scala:26:53]
always @(posedge clock) begin // @[LatencyInjectionQueue.scala:9:7]
if (reset) // @[LatencyInjectionQueue.scala:9:7]
cur_cycle <= 64'h0; // @[LatencyInjectionQueue.scala:16:26]
else // @[LatencyInjectionQueue.scala:9:7]
cur_cycle <= _cur_cycle_T_1; // @[LatencyInjectionQueue.scala:16:26, :17:26]
always @(posedge)
Queue64_TLBundleA_a32d256s5k3z4u_7 queue ( // @[LatencyInjectionQueue.scala:18:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_queue_io_enq_ready),
.io_enq_valid (_queue_io_enq_valid_T), // @[Misc.scala:26:53]
.io_enq_bits_opcode (io_enq_bits_opcode_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_size (io_enq_bits_size_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_source (io_enq_bits_source_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_address (io_enq_bits_address_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_mask (io_enq_bits_mask_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_data (io_enq_bits_data_0), // @[LatencyInjectionQueue.scala:9:7]
.io_deq_ready (_queue_io_deq_ready_T_1), // @[Misc.scala:26:53]
.io_deq_valid (_queue_io_deq_valid),
.io_deq_bits_opcode (io_deq_bits_opcode_0),
.io_deq_bits_param (io_deq_bits_param_0),
.io_deq_bits_size (io_deq_bits_size_0),
.io_deq_bits_source (io_deq_bits_source_0),
.io_deq_bits_address (io_deq_bits_address_0),
.io_deq_bits_mask (io_deq_bits_mask_0),
.io_deq_bits_data (io_deq_bits_data_0),
.io_deq_bits_corrupt (io_deq_bits_corrupt_0)
); // @[LatencyInjectionQueue.scala:18:21]
Queue64_UInt64_14 release_ready_cycle_q ( // @[LatencyInjectionQueue.scala:19:37]
.clock (clock),
.reset (reset),
.io_enq_ready (_release_ready_cycle_q_io_enq_ready),
.io_enq_valid (_release_ready_cycle_q_io_enq_valid_T), // @[Misc.scala:26:53]
.io_enq_bits (_release_ready_cycle_q_io_enq_bits_T_1), // @[LatencyInjectionQueue.scala:21:50]
.io_deq_ready (_release_ready_cycle_q_io_deq_ready_T_1), // @[Misc.scala:26:53]
.io_deq_valid (_release_ready_cycle_q_io_deq_valid),
.io_deq_bits (_release_ready_cycle_q_io_deq_bits)
); // @[LatencyInjectionQueue.scala:19:37]
assign io_enq_ready = io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_valid = io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_bits_param = io_deq_bits_param_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_bits_size = io_deq_bits_size_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_bits_source = io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_bits_address = io_deq_bits_address_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_bits_mask = io_deq_bits_mask_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[LatencyInjectionQueue.scala:9:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
|
module MacUnit_133( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Decode.scala:
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.BitPat
import chisel3.util.experimental.decode._
object DecodeLogic
{
// TODO This should be a method on BitPat
private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width
// Pads BitPats that are safe to pad (no don't cares), errors otherwise
private def padBP(bp: BitPat, width: Int): BitPat = {
if (bp.width == width) bp
else {
require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares")
val diff = width - bp.width
require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!")
BitPat(0.U(diff.W)) ## bp
}
}
def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt =
chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default))
def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = {
val nElts = default.size
require(mappingIn.forall(_._2.size == nElts),
s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}"
)
val elementsGrouped = mappingIn.map(_._2).transpose
val elementWidths = elementsGrouped.zip(default).map { case (elts, default) =>
(default :: elts.toList).map(_.getWidth).max
}
val resultWidth = elementWidths.sum
val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r }
// All BitPats that correspond to a given element in the result must have the same width in the
// chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have
// any don't cares. If there are don't cares, it is an error and the user needs to pad the
// BitPat themselves
val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) }
val mappingInPadded = mappingIn.map { case (in, elts) =>
in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) }
}
val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) })
elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList
}
def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] =
apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]])
def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool =
apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool
}
File FPU.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
case class FPUParams(
minFLen: Int = 32,
fLen: Int = 64,
divSqrt: Boolean = true,
sfmaLatency: Int = 3,
dfmaLatency: Int = 4,
fpmuLatency: Int = 2,
ifpuLatency: Int = 2
)
object FPConstants
{
val RM_SZ = 3
val FLAGS_SZ = 5
}
trait HasFPUCtrlSigs {
val ldst = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val swap12 = Bool()
val swap23 = Bool()
val typeTagIn = UInt(2.W)
val typeTagOut = UInt(2.W)
val fromint = Bool()
val toint = Bool()
val fastpipe = Bool()
val fma = Bool()
val div = Bool()
val sqrt = Bool()
val wflags = Bool()
val vec = Bool()
}
class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val inst = Input(Bits(32.W))
val sigs = Output(new FPUCtrlSigs())
})
private val X2 = BitPat.dontCare(2)
val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)
val h: Array[(BitPat, List[BitPat])] =
Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),
FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),
FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),
FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),
FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),
FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),
FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),
FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))
val f: Array[(BitPat, List[BitPat])] =
Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),
FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),
FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),
FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),
FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),
FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))
val d: Array[(BitPat, List[BitPat])] =
Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),
FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),
FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),
FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),
FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),
FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),
FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),
FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))
val fcvt_hd: Array[(BitPat, List[BitPat])] =
Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),
FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))
val vfmv_f_s: Array[(BitPat, List[BitPat])] =
Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))
val insns = ((minFLen, fLen) match {
case (32, 32) => f
case (16, 32) => h ++ f
case (32, 64) => f ++ d
case (16, 64) => h ++ f ++ d ++ fcvt_hd
case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration")
}) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())
val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,
s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val time = Input(UInt(xLen.W))
val inst = Input(Bits(32.W))
val fromint_data = Input(Bits(xLen.W))
val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))
val v_sew = Input(UInt(3.W))
val store_data = Output(Bits(fLen.W))
val toint_data = Output(Bits(xLen.W))
val ll_resp_val = Input(Bool())
val ll_resp_type = Input(Bits(3.W))
val ll_resp_tag = Input(UInt(5.W))
val ll_resp_data = Input(Bits(fLen.W))
val valid = Input(Bool())
val fcsr_rdy = Output(Bool())
val nack_mem = Output(Bool())
val illegal_rm = Output(Bool())
val killx = Input(Bool())
val killm = Input(Bool())
val dec = Output(new FPUCtrlSigs())
val sboard_set = Output(Bool())
val sboard_clr = Output(Bool())
val sboard_clra = Output(UInt(5.W))
val keep_clock_enabled = Input(Bool())
}
class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs
val cp_resp = Decoupled(new FPResult())
}
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val data = Bits((fLen+1).W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val typ = Bits(2.W)
val in1 = Bits(xLen.W)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val fmaCmd = Bits(2.W)
val typ = Bits(2.W)
val fmt = Bits(2.W)
val in1 = Bits((fLen+1).W)
val in2 = Bits((fLen+1).W)
val in3 = Bits((fLen+1).W)
}
case class FType(exp: Int, sig: Int) {
def ieeeWidth = exp + sig
def recodedWidth = ieeeWidth + 1
def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)
def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)
def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR
def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)
def classify(x: UInt) = {
val sign = x(sig + exp)
val code = x(exp + sig - 1, exp + sig - 3)
val codeHi = code(2, 1)
val isSpecial = codeHi === 3.U
val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U
val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn
val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U
val isZero = code === 0.U
val isInf = isSpecial && !code(0)
val isNaN = code.andR
val isSNaN = isNaN && !x(sig-2)
val isQNaN = isNaN && x(sig-2)
Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
isSubnormal && !sign, isZero && !sign, isZero && sign,
isSubnormal && sign, isNormal && sign, isInf && sign)
}
// convert between formats, ignoring rounding, range, NaN
def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {
val sign = x(sig + exp)
val fractIn = x(sig - 2, 0)
val expIn = x(sig + exp - 1, sig - 1)
val fractOut = fractIn << to.sig >> sig
val expOut = {
val expCode = expIn(exp, exp - 2)
val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U
Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))
}
Cat(sign, expOut, fractOut)
}
private def ieeeBundle = {
val expWidth = exp
class IEEEBundle extends Bundle {
val sign = Bool()
val exp = UInt(expWidth.W)
val sig = UInt((ieeeWidth-expWidth-1).W)
}
new IEEEBundle
}
def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)
def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
}
object FType {
val H = new FType(5, 11)
val S = new FType(8, 24)
val D = new FType(11, 53)
val all = List(H, S, D)
}
trait HasFPUParameters {
require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))
val minFLen: Int
val fLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)
def minType = floatTypes.head
def maxType = floatTypes.last
def prevType(t: FType) = floatTypes(typeTag(t) - 1)
def maxExpWidth = maxType.exp
def maxSigWidth = maxType.sig
def typeTag(t: FType) = floatTypes.indexOf(t)
def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U
def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U
// typeTag
def H = typeTagGroup(FType.H)
def S = typeTagGroup(FType.S)
def D = typeTagGroup(FType.D)
def I = typeTag(maxType).U
private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR
private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {
require(xt.ieeeWidth == 2 * yt.ieeeWidth)
val swizzledNaN = Cat(
x(xt.sig + xt.exp, xt.sig + xt.exp - 3),
x(xt.sig - 2, yt.recodedWidth - 1).andR,
x(xt.sig + xt.exp - 5, xt.sig),
y(yt.recodedWidth - 2),
x(xt.sig - 2, yt.recodedWidth - 1),
y(yt.recodedWidth - 1),
y(yt.recodedWidth - 3, 0))
Mux(xt.isNaN(x), swizzledNaN, x)
}
// implement NaN unboxing for FU inputs
def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {
val outType = exactType.getOrElse(maxType)
def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {
val prev =
if (t == minType) {
Seq()
} else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prev = helper(unswizzled, prevT)
val isbox = isBox(x, t)
prev.map(p => (isbox && p._1, p._2))
}
prev :+ (true.B, t.unsafeConvert(x, outType))
}
val (oks, floats) = helper(x, maxType).unzip
if (exactType.isEmpty || floatTypes.size == 1) {
Mux(oks(tag), floats(tag), maxType.qNaN)
} else {
val t = exactType.get
floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)
}
}
// make sure that the redundant bits in the NaN-boxed encoding are consistent
def consistent(x: UInt): Bool = {
def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prevOK = !isBox(x, t) || helper(unswizzled, prevT)
val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR
prevOK && curOK
}
helper(x, maxType)
}
// generate a NaN box from an FU result
def box(x: UInt, t: FType): UInt = {
if (t == maxType) {
x
} else {
val nt = floatTypes(typeTag(t) + 1)
val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)
bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U
}
}
// generate a NaN box from an FU result
def box(x: UInt, tag: UInt): UInt = {
val opts = floatTypes.map(t => box(x, t))
opts(tag)
}
// zap bits that hardfloat thinks are don't-cares, but we do care about
def sanitizeNaN(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
x
} else {
val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)
Mux(t.isNaN(x), maskedNaN, x)
}
}
// implement NaN boxing and recoding for FL*/fmv.*.x
def recode(x: UInt, tag: UInt): UInt = {
def helper(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
t.recode(x)
} else {
val prevT = prevType(t)
box(t.recode(x), t, helper(x, prevT), prevT)
}
}
// fill MSBs of subword loads to emulate a wider load of a NaN-boxed value
val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)
helper(boxes(tag) | x, maxType)
}
// implement NaN unboxing and un-recoding for FS*/fmv.x.*
def ieee(x: UInt, t: FType = maxType): UInt = {
if (typeTag(t) == 0) {
t.ieee(x)
} else {
val unrecoded = t.ieee(x)
val prevT = prevType(t)
val prevRecoded = Cat(
x(prevT.recodedWidth-2),
x(t.sig-1),
x(prevT.recodedWidth-3, 0))
val prevUnrecoded = ieee(prevRecoded, prevT)
Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))
}
}
}
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
val in = new FPInput
val lt = Bool()
val store = Bits(fLen.W)
val toint = Bits(xLen.W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new Output)
})
val in = RegEnable(io.in.bits, io.in.valid)
val valid = RegNext(io.in.valid)
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
dcmp.io.a := in.in1
dcmp.io.b := in.in2
dcmp.io.signaling := !in.rm(1)
val tag = in.typeTagOut
val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))
else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
val toint = WireDefault(toint_ieee)
val intType = WireDefault(in.fmt(0))
io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := 0.U
when (in.rm(0)) {
val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
toint := classify_out | (toint_ieee >> minXLen << minXLen)
intType := false.B
}
when (in.wflags) { // feq/flt/fle, fcvt
toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
io.out.bits.exc := dcmp.io.exceptionFlags
intType := false.B
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
conv.io.signedOut := ~in.typ(0)
toint := conv.io.out
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))
for (i <- 0 until nIntTypes-1) {
val w = minXLen << i
when (cvtType === i.U) {
val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
narrow.io.in := in.in1
narrow.io.roundingMode := in.rm
narrow.io.signedOut := ~in.typ(0)
val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)
val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))
val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
when (invalid) { toint := Cat(conv.io.out >> w, excOut) }
io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))
}
}
}
}
io.out.valid := valid
io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in
}
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new IntToFPInput))
val out = Valid(new FPResult)
})
val in = Pipe(io.in)
val tag = in.bits.typeTagIn
val mux = Wire(new FPResult)
mux.exc := 0.U
mux.data := recode(in.bits.in1, tag)
val intValue = {
val res = WireDefault(in.bits.in1.asSInt)
for (i <- 0 until nIntTypes-1) {
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
}
}
res.asUInt
}
when (in.bits.wflags) { // fcvt
// could be improved for RVD/RVQ with a single variable-position rounding
// unit, rather than N fixed-position ones
val i2fResults = for (t <- floatTypes) yield {
val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
i2f.io.signedIn := ~in.bits.typ(0)
i2f.io.in := intValue
i2f.io.roundingMode := in.bits.rm
i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding
(sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)
}
val (data, exc) = i2fResults.unzip
val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
mux.data := dataPadded(tag)
mux.exc := exc(tag)
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
val lt = Input(Bool()) // from FPToInt
})
val in = Pipe(io.in)
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
val fsgnjMux = Wire(new FPResult)
fsgnjMux.exc := 0.U
fsgnjMux.data := fsgnj
when (in.bits.wflags) { // fmin/fmax
val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
}
val inTag = in.bits.typeTagIn
val outTag = in.bits.typeTagOut
val mux = WireDefault(fsgnjMux)
for (t <- floatTypes.init) {
when (outTag === typeTag(t).U) {
mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))
}
}
when (in.bits.wflags && !in.bits.ren2) { // fcvt
if (floatTypes.size > 1) {
// widening conversions simply canonicalize NaN operands
val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)
fsgnjMux.data := widened
fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4
// narrowing conversions require rounding (for RVQ, this could be
// optimized to use a single variable-position rounding unit, rather
// than two fixed-position ones)
for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {
val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
narrower.io.in := in.bits.in1
narrower.io.roundingMode := in.bits.rm
narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
val narrowed = sanitizeNaN(narrower.io.out, outType)
mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
mux.exc := narrower.io.exceptionFlags
}
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
{
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
require(latency<=2)
val io = IO(new Bundle {
val validin = Input(Bool())
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
val validout = Output(Bool())
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
val valid_stage0 = Wire(Bool())
val roundingMode_stage0 = Wire(UInt(3.W))
val detectTininess_stage0 = Wire(UInt(1.W))
val postmul_regs = if(latency>0) 1 else 0
mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
val round_regs = if(latency==2) 1 else 0
roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
io.validout := Pipe(valid_stage0, false.B, round_regs).valid
roundRawFNToRecFN.io.infiniteExc := false.B
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
class FPUFMAPipe(val latency: Int, val t: FType)
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
require(latency>0)
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
})
val valid = RegNext(io.in.valid)
val in = Reg(new FPInput)
when (io.in.valid) {
val one = 1.U << (t.sig + t.exp - 1)
val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))
val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23
in := io.in.bits
when (cmd_addsub) { in.in2 := one }
when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
}
val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
fma.io.validin := valid
fma.io.op := in.fmaCmd
fma.io.roundingMode := in.rm
fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
fma.io.a := in.in1
fma.io.b := in.in2
fma.io.c := in.in3
val res = Wire(new FPResult)
res.data := sanitizeNaN(fma.io.out, t)
res.exc := fma.io.exceptionFlags
io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
}
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new FPUIO)
val (useClockGating, useDebugROB) = coreParams match {
case r: RocketCoreParams =>
val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
(r.clockGate, sz < 1)
case _ => (false, false)
}
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cp_req.valid
val gated_clock =
if (!useClockGating) clock
else ClockGate(clock, clock_en, "fpu_clock_gate")
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val id_ctrl = WireInit(fp_decoder.io.sigs)
coreParams match { case r: RocketCoreParams => r.vector.map(v => {
val v_decode = v.decoder(p) // Only need to get ren1
v_decode.io.inst := io.inst
v_decode.io.vconfig := DontCare // core deals with this
when (v_decode.io.legal && v_decode.io.read_frs1) {
id_ctrl.ren1 := true.B
id_ctrl.swap12 := false.B
id_ctrl.toint := true.B
id_ctrl.typeTagIn := I
id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
}
when (v_decode.io.write_frd) { id_ctrl.wen := true.B }
})}
val ex_reg_valid = RegNext(io.valid, false.B)
val ex_reg_inst = RegEnable(io.inst, io.valid)
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt()))
// load/vector response
val load_wb = RegNext(io.ll_resp_val)
val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)
val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)
val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)
class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid
val ex_cp_valid = io.cp_req.fire
val mem_cp_valid = RegNext(ex_cp_valid, false.B)
val wb_cp_valid = RegNext(mem_cp_valid, false.B)
val mem_reg_valid = RegInit(false.B)
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
// Kill X-stage instruction if M-stage is killed. This prevents it from
// speculatively being sent to the div-sqrt unit, which can cause priority
// inversion for two back-to-back divides, the first of which is killed.
val killx = io.killx || mem_reg_valid && killm
mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
io.cp_resp.valid := false.B
io.cp_resp.bits.data := 0.U
io.cp_resp.bits.exc := DontCare
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// CoreMonitorBundle to monitor fp register file writes
val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))
frfWriteBundle.foreach { i =>
i.clock := clock
i.reset := reset
i.hartid := io.hartid
i.timer := io.time(31,0)
i.valid := false.B
i.wrenx := false.B
i.wrenf := false.B
i.excpt := false.B
}
// regfile
val regfile = Mem(32, Bits((fLen+1).W))
when (load_wb) {
val wdata = recode(load_wb_data, load_wb_typeTag)
regfile(load_wb_tag) := wdata
assert(consistent(wdata))
if (enableCommitLog)
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))
if (useDebugROB)
DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))
frfWriteBundle(0).wrdst := load_wb_tag
frfWriteBundle(0).wrenf := true.B
frfWriteBundle(0).wrdata := ieee(wdata)
}
val ex_rs = ex_ra.map(a => regfile(a))
when (io.valid) {
when (id_ctrl.ren1) {
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }
}
when (id_ctrl.ren2) {
when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }
when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }
}
when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }
}
val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))
def fuInput(minT: Option[FType]): FPInput = {
val req = Wire(new FPInput)
val tag = ex_ctrl.typeTagIn
req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
req.rm := ex_rm
req.in1 := unbox(ex_rs(0), tag, minT)
req.in2 := unbox(ex_rs(1), tag, minT)
req.in3 := unbox(ex_rs(2), tag, minT)
req.typ := ex_reg_inst(21,20)
req.fmt := ex_reg_inst(26,25)
req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))
when (ex_cp_valid) {
req := io.cp_req.bits
when (io.cp_req.bits.swap12) {
req.in1 := io.cp_req.bits.in2
req.in2 := io.cp_req.bits.in1
}
when (io.cp_req.bits.swap23) {
req.in2 := io.cp_req.bits.in3
req.in3 := io.cp_req.bits.in2
}
}
req
}
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
io.store_data := fpiu.io.out.bits.store
io.toint_data := fpiu.io.out.bits.toint
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
io.cp_resp.bits.data := fpiu.io.out.bits.toint
io.cp_resp.valid := true.B
}
val ifpu = Module(new IntToFP(cfg.ifpuLatency))
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
ifpu.io.in.bits := fpiu.io.in.bits
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
val fpmu = Module(new FPToFP(cfg.fpmuLatency))
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt_wen = WireDefault(false.B)
val divSqrt_inFlight = WireDefault(false.B)
val divSqrt_waddr = Reg(UInt(5.W))
val divSqrt_cp = Reg(Bool())
val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
val divSqrt_wdata = Wire(UInt((fLen+1).W))
val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
divSqrt_typeTag := DontCare
divSqrt_wdata := DontCare
divSqrt_flags := DontCare
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++
(fLen > 32).option({
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D
dfma.io.in.bits := fuInput(Some(dfma.t))
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)
}) ++
(minFLen == 16).option({
val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))
hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H
hfma.io.in.bits := fuInput(Some(hfma.t))
Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)
})
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
require(pipes.forall(_.lat >= offset))
pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)
}
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
class WBInfo extends Bundle {
val rd = UInt(5.W)
val typeTag = UInt(log2Up(floatTypes.size).W)
val cp = Bool()
val pipeid = UInt(log2Ceil(pipes.size).W)
}
val wen = RegInit(0.U((maxLatency-1).W))
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
}
wen := wen >> 1
when (mem_wen) {
when (!killm) {
wen := wen >> 1 | memLatencyMask
}
for (i <- 0 until maxLatency-1) {
when (!write_port_busy && memLatencyMask(i)) {
wbInfo(i).cp := mem_cp_valid
wbInfo(i).typeTag := mem_ctrl.typeTagOut
wbInfo(i).pipeid := pipeid(mem_ctrl)
wbInfo(i).rd := mem_reg_inst(11,7)
}
}
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,
s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
// Avoid structural hazards and nacking of external requests
// toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
io.fcsr_flags.bits :=
Mux(wb_toint_valid, wb_toint_exc, 0.U) |
Mux(divSqrt_wen, divSqrt_flags, 0.U) |
Mux(wen(0), wexc, 0.U)
val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
io.dec <> id_ctrl
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U
if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
when (divSqrt_inValid) {
divSqrt_waddr := mem_reg_inst(11,7)
divSqrt_cp := mem_cp_valid
}
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) {
val tag = mem_ctrl.typeTagOut
val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }
divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight
when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {
divSqrt_wen := !divSqrt_killed
divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)
divSqrt_flags := divSqrt.io.exceptionFlags
divSqrt_typeTag := typeTag(t).U
}
}
when (divSqrt_killed) { divSqrt_inFlight := false.B }
} else {
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }
}
// gate the clock
clock_en_reg := !useClockGating.B ||
io.keep_clock_enabled || // chicken bit
io.valid || // ID stage
req_valid || // EX stage
mem_reg_valid || mem_cp_valid || // MEM stage
wb_reg_valid || wb_cp_valid || // WB stage
wen.orR || divSqrt_inFlight || // post-WB stage
io.ll_resp_val // load writeback
} // leaving gated-clock domain
val fpuImpl = withClock (gated_clock) { new FPUImpl }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FPU_$label", "Core;;" + desc)
}
|
module FPUDecoder_6( // @[FPU.scala:55:7]
input clock, // @[FPU.scala:55:7]
input reset, // @[FPU.scala:55:7]
input [31:0] io_inst, // @[FPU.scala:56:14]
output io_sigs_ldst, // @[FPU.scala:56:14]
output io_sigs_wen, // @[FPU.scala:56:14]
output io_sigs_ren1, // @[FPU.scala:56:14]
output io_sigs_ren2, // @[FPU.scala:56:14]
output io_sigs_ren3, // @[FPU.scala:56:14]
output io_sigs_swap12, // @[FPU.scala:56:14]
output io_sigs_swap23, // @[FPU.scala:56:14]
output [1:0] io_sigs_typeTagIn, // @[FPU.scala:56:14]
output [1:0] io_sigs_typeTagOut, // @[FPU.scala:56:14]
output io_sigs_fromint, // @[FPU.scala:56:14]
output io_sigs_toint, // @[FPU.scala:56:14]
output io_sigs_fastpipe, // @[FPU.scala:56:14]
output io_sigs_fma, // @[FPU.scala:56:14]
output io_sigs_div, // @[FPU.scala:56:14]
output io_sigs_sqrt, // @[FPU.scala:56:14]
output io_sigs_wflags, // @[FPU.scala:56:14]
output io_sigs_vec // @[FPU.scala:56:14]
);
wire [31:0] io_inst_0 = io_inst; // @[FPU.scala:55:7]
wire [31:0] decoder_decoded_plaInput = io_inst_0; // @[pla.scala:77:22]
wire decoder_0; // @[Decode.scala:50:77]
wire decoder_1; // @[Decode.scala:50:77]
wire decoder_2; // @[Decode.scala:50:77]
wire decoder_3; // @[Decode.scala:50:77]
wire decoder_4; // @[Decode.scala:50:77]
wire decoder_5; // @[Decode.scala:50:77]
wire decoder_6; // @[Decode.scala:50:77]
wire [1:0] decoder_7; // @[Decode.scala:50:77]
wire [1:0] decoder_8; // @[Decode.scala:50:77]
wire decoder_9; // @[Decode.scala:50:77]
wire decoder_10; // @[Decode.scala:50:77]
wire decoder_11; // @[Decode.scala:50:77]
wire decoder_12; // @[Decode.scala:50:77]
wire decoder_13; // @[Decode.scala:50:77]
wire decoder_14; // @[Decode.scala:50:77]
wire decoder_15; // @[Decode.scala:50:77]
wire decoder_16; // @[Decode.scala:50:77]
wire io_sigs_ldst_0; // @[FPU.scala:55:7]
wire io_sigs_wen_0; // @[FPU.scala:55:7]
wire io_sigs_ren1_0; // @[FPU.scala:55:7]
wire io_sigs_ren2_0; // @[FPU.scala:55:7]
wire io_sigs_ren3_0; // @[FPU.scala:55:7]
wire io_sigs_swap12_0; // @[FPU.scala:55:7]
wire io_sigs_swap23_0; // @[FPU.scala:55:7]
wire [1:0] io_sigs_typeTagIn_0; // @[FPU.scala:55:7]
wire [1:0] io_sigs_typeTagOut_0; // @[FPU.scala:55:7]
wire io_sigs_fromint_0; // @[FPU.scala:55:7]
wire io_sigs_toint_0; // @[FPU.scala:55:7]
wire io_sigs_fastpipe_0; // @[FPU.scala:55:7]
wire io_sigs_fma_0; // @[FPU.scala:55:7]
wire io_sigs_div_0; // @[FPU.scala:55:7]
wire io_sigs_sqrt_0; // @[FPU.scala:55:7]
wire io_sigs_wflags_0; // @[FPU.scala:55:7]
wire io_sigs_vec_0; // @[FPU.scala:55:7]
wire [31:0] decoder_decoded_invInputs = ~decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21]
wire [18:0] decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37]
wire [18:0] decoder_decoded; // @[pla.scala:81:23]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_3, decoder_decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_0, decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi = {decoder_decoded_andMatrixOutputs_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53]
wire [4:0] _decoder_decoded_andMatrixOutputs_T = {decoder_decoded_andMatrixOutputs_hi, decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_72_2 = &_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire _decoder_decoded_orMatrixOutputs_T_26 = decoder_decoded_andMatrixOutputs_72_2; // @[pla.scala:98:70, :114:36]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_1 = {decoder_decoded_andMatrixOutputs_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_1 = {decoder_decoded_andMatrixOutputs_hi_hi_1, decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [6:0] _decoder_decoded_andMatrixOutputs_T_1 = {decoder_decoded_andMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_6_2 = &_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_9, decoder_decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_1 = {decoder_decoded_andMatrixOutputs_lo_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_2 = {decoder_decoded_andMatrixOutputs_lo_hi_1, decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_2, decoder_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_1 = {decoder_decoded_andMatrixOutputs_hi_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_2 = {decoder_decoded_andMatrixOutputs_hi_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_2 = {decoder_decoded_andMatrixOutputs_hi_hi_2, decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53]
wire [10:0] _decoder_decoded_andMatrixOutputs_T_2 = {decoder_decoded_andMatrixOutputs_hi_2, decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_16_2 = &_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_1, decoder_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_2 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_3 = {decoder_decoded_andMatrixOutputs_lo_hi_2, decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_3, decoder_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_2 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_3 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_3 = {decoder_decoded_andMatrixOutputs_hi_hi_3, decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53]
wire [10:0] _decoder_decoded_andMatrixOutputs_T_3 = {decoder_decoded_andMatrixOutputs_hi_3, decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_19_2 = &_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_2, decoder_decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_2 = {decoder_decoded_andMatrixOutputs_lo_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_3, decoder_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_3 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_lo_4 = {decoder_decoded_andMatrixOutputs_lo_hi_3, decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_4, decoder_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_3 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_4 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_4 = {decoder_decoded_andMatrixOutputs_hi_hi_4, decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53]
wire [11:0] _decoder_decoded_andMatrixOutputs_T_4 = {decoder_decoded_andMatrixOutputs_hi_4, decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_55_2 = &_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_3, decoder_decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_3 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, decoder_decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_4 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_8_3}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_lo_5 = {decoder_decoded_andMatrixOutputs_lo_hi_4, decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_4 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_5 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_5 = {decoder_decoded_andMatrixOutputs_hi_hi_5, decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53]
wire [11:0] _decoder_decoded_andMatrixOutputs_T_5 = {decoder_decoded_andMatrixOutputs_hi_5, decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_18_2 = &_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_4, decoder_decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_4 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_5, decoder_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_5 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_lo_6 = {decoder_decoded_andMatrixOutputs_lo_hi_5, decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_5 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_6 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_6 = {decoder_decoded_andMatrixOutputs_hi_hi_6, decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53]
wire [11:0] _decoder_decoded_andMatrixOutputs_T_6 = {decoder_decoded_andMatrixOutputs_hi_6, decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_8_2 = &_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_5, decoder_decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_5 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_6, decoder_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_6 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_8_5}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_lo_7 = {decoder_decoded_andMatrixOutputs_lo_hi_6, decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_6 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_7 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_7 = {decoder_decoded_andMatrixOutputs_hi_hi_7, decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53]
wire [11:0] _decoder_decoded_andMatrixOutputs_T_7 = {decoder_decoded_andMatrixOutputs_hi_7, decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_41_2 = &_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, decoder_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_6 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_7, decoder_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_7 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_lo_8 = {decoder_decoded_andMatrixOutputs_lo_hi_7, decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, decoder_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_7 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_8 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_8 = {decoder_decoded_andMatrixOutputs_hi_hi_8, decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53]
wire [11:0] _decoder_decoded_andMatrixOutputs_T_8 = {decoder_decoded_andMatrixOutputs_hi_8, decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_74_2 = &_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_9 = {decoder_decoded_andMatrixOutputs_lo_hi_8, decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, decoder_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_9 = {decoder_decoded_andMatrixOutputs_hi_hi_9, decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53]
wire [7:0] _decoder_decoded_andMatrixOutputs_T_9 = {decoder_decoded_andMatrixOutputs_hi_9, decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_71_2 = &_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_8, decoder_decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_9, decoder_decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_10 = {decoder_decoded_andMatrixOutputs_lo_hi_9, decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_10, decoder_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_10 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_10 = {decoder_decoded_andMatrixOutputs_hi_hi_10, decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53]
wire [8:0] _decoder_decoded_andMatrixOutputs_T_10 = {decoder_decoded_andMatrixOutputs_hi_10, decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_30_2 = &_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, decoder_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_10, decoder_decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_11 = {decoder_decoded_andMatrixOutputs_lo_hi_10, decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_11, decoder_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_11 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_11 = {decoder_decoded_andMatrixOutputs_hi_hi_11, decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53]
wire [8:0] _decoder_decoded_andMatrixOutputs_T_11 = {decoder_decoded_andMatrixOutputs_hi_11, decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_66_2 = &_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_11, decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_12 = {decoder_decoded_andMatrixOutputs_lo_hi_11, decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, decoder_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_12 = {decoder_decoded_andMatrixOutputs_hi_hi_12, decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53]
wire [7:0] _decoder_decoded_andMatrixOutputs_T_12 = {decoder_decoded_andMatrixOutputs_hi_12, decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_75_2 = &_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_11, decoder_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_12, decoder_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_13 = {decoder_decoded_andMatrixOutputs_lo_hi_12, decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_13, decoder_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_13 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_13 = {decoder_decoded_andMatrixOutputs_hi_hi_13, decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53]
wire [8:0] _decoder_decoded_andMatrixOutputs_T_13 = {decoder_decoded_andMatrixOutputs_hi_13, decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_37_2 = &_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_12, decoder_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_13, decoder_decoded_andMatrixOutputs_andMatrixInput_6_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_14 = {decoder_decoded_andMatrixOutputs_lo_hi_13, decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_14, decoder_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_14 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_14 = {decoder_decoded_andMatrixOutputs_hi_hi_14, decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53]
wire [8:0] _decoder_decoded_andMatrixOutputs_T_14 = {decoder_decoded_andMatrixOutputs_hi_14, decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_47_2 = &_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_11, decoder_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_14, decoder_decoded_andMatrixOutputs_andMatrixInput_6_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_14 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_15 = {decoder_decoded_andMatrixOutputs_lo_hi_14, decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_15, decoder_decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_15 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_15 = {decoder_decoded_andMatrixOutputs_hi_hi_15, decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53]
wire [9:0] _decoder_decoded_andMatrixOutputs_T_15 = {decoder_decoded_andMatrixOutputs_hi_15, decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_60_2 = &_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, decoder_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_15, decoder_decoded_andMatrixOutputs_andMatrixInput_6_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_15 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_16 = {decoder_decoded_andMatrixOutputs_lo_hi_15, decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_16, decoder_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_16 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_16 = {decoder_decoded_andMatrixOutputs_hi_hi_16, decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53]
wire [9:0] _decoder_decoded_andMatrixOutputs_T_16 = {decoder_decoded_andMatrixOutputs_hi_16, decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_15_2 = &_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_17, decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_17 = {decoder_decoded_andMatrixOutputs_lo_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_6_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, decoder_decoded_andMatrixOutputs_andMatrixInput_3_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_17 = {decoder_decoded_andMatrixOutputs_hi_hi_17, decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53]
wire [6:0] _decoder_decoded_andMatrixOutputs_T_17 = {decoder_decoded_andMatrixOutputs_hi_17, decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_29_2 = &_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, decoder_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_15 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_17 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_lo_18 = {decoder_decoded_andMatrixOutputs_lo_hi_17, decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_17 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_18 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_18 = {decoder_decoded_andMatrixOutputs_hi_hi_18, decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53]
wire [11:0] _decoder_decoded_andMatrixOutputs_T_18 = {decoder_decoded_andMatrixOutputs_hi_18, decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_39_2 = &_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_8, decoder_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_16 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_16, decoder_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_18 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_9_10}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_lo_19 = {decoder_decoded_andMatrixOutputs_lo_hi_18, decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_19, decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_18 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_6_18}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_19, decoder_decoded_andMatrixOutputs_andMatrixInput_3_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_19 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_14, decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_hi_19 = {decoder_decoded_andMatrixOutputs_hi_hi_19, decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53]
wire [12:0] _decoder_decoded_andMatrixOutputs_T_19 = {decoder_decoded_andMatrixOutputs_hi_19, decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_69_2 = &_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_9, decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_17 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_17, decoder_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_19 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_lo_20 = {decoder_decoded_andMatrixOutputs_lo_hi_19, decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_20, decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_19 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_6_19}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, decoder_decoded_andMatrixOutputs_andMatrixInput_3_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_20 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_hi_20 = {decoder_decoded_andMatrixOutputs_hi_hi_20, decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53]
wire [12:0] _decoder_decoded_andMatrixOutputs_T_20 = {decoder_decoded_andMatrixOutputs_hi_20, decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_42_2 = &_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_8, decoder_decoded_andMatrixOutputs_andMatrixInput_12_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_18 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_18, decoder_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_20 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_12, decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_21 = {decoder_decoded_andMatrixOutputs_lo_hi_20, decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_21, decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_20 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_21, decoder_decoded_andMatrixOutputs_andMatrixInput_3_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_21 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_hi_21 = {decoder_decoded_andMatrixOutputs_hi_hi_21, decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53]
wire [13:0] _decoder_decoded_andMatrixOutputs_T_21 = {decoder_decoded_andMatrixOutputs_hi_21, decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_49_2 = &_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_9, decoder_decoded_andMatrixOutputs_andMatrixInput_12_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_19 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_13, decoder_decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, decoder_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_21 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_13, decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_22 = {decoder_decoded_andMatrixOutputs_lo_hi_21, decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_21 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_6_21}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, decoder_decoded_andMatrixOutputs_andMatrixInput_3_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_22 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_hi_22 = {decoder_decoded_andMatrixOutputs_hi_hi_22, decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53]
wire [13:0] _decoder_decoded_andMatrixOutputs_T_22 = {decoder_decoded_andMatrixOutputs_hi_22, decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_24_2 = &_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_10, decoder_decoded_andMatrixOutputs_andMatrixInput_12_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_20 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_14, decoder_decoded_andMatrixOutputs_andMatrixInput_10_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_20, decoder_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_22 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_14, decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_23 = {decoder_decoded_andMatrixOutputs_lo_hi_22, decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_23, decoder_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_22 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_6_22}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_23, decoder_decoded_andMatrixOutputs_andMatrixInput_3_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_23 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_18, decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_hi_23 = {decoder_decoded_andMatrixOutputs_hi_hi_23, decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53]
wire [13:0] _decoder_decoded_andMatrixOutputs_T_23 = {decoder_decoded_andMatrixOutputs_hi_23, decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_9_2 = &_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_11, decoder_decoded_andMatrixOutputs_andMatrixInput_12_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_21 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_15, decoder_decoded_andMatrixOutputs_andMatrixInput_10_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_21, decoder_decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_23 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_15, decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_24 = {decoder_decoded_andMatrixOutputs_lo_hi_23, decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_24, decoder_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_23 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_6_23}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_24, decoder_decoded_andMatrixOutputs_andMatrixInput_3_24}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_24 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_hi_24 = {decoder_decoded_andMatrixOutputs_hi_hi_24, decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53]
wire [13:0] _decoder_decoded_andMatrixOutputs_T_24 = {decoder_decoded_andMatrixOutputs_hi_24, decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_57_2 = &_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_6, decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_22 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_14, decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, decoder_decoded_andMatrixOutputs_andMatrixInput_9_16}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_24 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_16, decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_25 = {decoder_decoded_andMatrixOutputs_lo_hi_24, decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_24, decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_25, decoder_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_24 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_14, decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_25, decoder_decoded_andMatrixOutputs_andMatrixInput_3_25}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_25 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_20, decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_25 = {decoder_decoded_andMatrixOutputs_hi_hi_25, decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_25 = {decoder_decoded_andMatrixOutputs_hi_25, decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_50_2 = &_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, decoder_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_23 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_21, decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_25 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_17, decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_26 = {decoder_decoded_andMatrixOutputs_lo_hi_25, decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_25, decoder_decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_25 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_15, decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, decoder_decoded_andMatrixOutputs_andMatrixInput_3_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_26 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_26 = {decoder_decoded_andMatrixOutputs_hi_hi_26, decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_26 = {decoder_decoded_andMatrixOutputs_hi_26, decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_21_2 = &_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_14, decoder_decoded_andMatrixOutputs_andMatrixInput_12_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_24 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_18, decoder_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_24, decoder_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_26 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_18, decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_27 = {decoder_decoded_andMatrixOutputs_lo_hi_26, decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_26 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_6_26}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, decoder_decoded_andMatrixOutputs_andMatrixInput_3_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_27 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_22, decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_hi_27 = {decoder_decoded_andMatrixOutputs_hi_hi_27, decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53]
wire [13:0] _decoder_decoded_andMatrixOutputs_T_27 = {decoder_decoded_andMatrixOutputs_hi_27, decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_61_2 = &_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, decoder_decoded_andMatrixOutputs_andMatrixInput_12_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_25 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_19, decoder_decoded_andMatrixOutputs_andMatrixInput_10_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_25, decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_27 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_19, decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_28 = {decoder_decoded_andMatrixOutputs_lo_hi_27, decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_27 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_6_27}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_28 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_23, decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_hi_28 = {decoder_decoded_andMatrixOutputs_hi_hi_28, decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53]
wire [13:0] _decoder_decoded_andMatrixOutputs_T_28 = {decoder_decoded_andMatrixOutputs_hi_28, decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_44_2 = &_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_26 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_18, decoder_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_24, decoder_decoded_andMatrixOutputs_andMatrixInput_9_20}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_28 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_20, decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_29 = {decoder_decoded_andMatrixOutputs_lo_hi_28, decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_28, decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_28 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_18, decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_29 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_24, decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_29 = {decoder_decoded_andMatrixOutputs_hi_hi_29, decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_29 = {decoder_decoded_andMatrixOutputs_hi_29, decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_43_2 = &_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_27 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_19, decoder_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_25, decoder_decoded_andMatrixOutputs_andMatrixInput_9_21}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_29 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_21, decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_30 = {decoder_decoded_andMatrixOutputs_lo_hi_29, decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_29, decoder_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_29 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_19, decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_30 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_25, decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_30 = {decoder_decoded_andMatrixOutputs_hi_hi_30, decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_30 = {decoder_decoded_andMatrixOutputs_hi_30, decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_73_2 = &_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_28 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_14_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_26, decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_30 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_22, decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_31 = {decoder_decoded_andMatrixOutputs_lo_hi_30, decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_30, decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_30 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_20, decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_31 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_26, decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_31 = {decoder_decoded_andMatrixOutputs_hi_hi_31, decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_31 = {decoder_decoded_andMatrixOutputs_hi_31, decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_23_2 = &_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_29 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_14_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, decoder_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_27, decoder_decoded_andMatrixOutputs_andMatrixInput_9_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_31 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_23, decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_32 = {decoder_decoded_andMatrixOutputs_lo_hi_31, decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, decoder_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, decoder_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_31 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_21, decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_32, decoder_decoded_andMatrixOutputs_andMatrixInput_3_32}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_32 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_27, decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_32 = {decoder_decoded_andMatrixOutputs_hi_hi_32, decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_32 = {decoder_decoded_andMatrixOutputs_hi_32, decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_38_2 = &_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_30 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_14_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_32 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_24, decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_33 = {decoder_decoded_andMatrixOutputs_lo_hi_32, decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, decoder_decoded_andMatrixOutputs_andMatrixInput_7_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_33, decoder_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_32 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_22, decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_33, decoder_decoded_andMatrixOutputs_andMatrixInput_3_33}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_33 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_28, decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_33 = {decoder_decoded_andMatrixOutputs_hi_hi_33, decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_33 = {decoder_decoded_andMatrixOutputs_hi_33, decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_10_2 = &_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_15, decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_31 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_14_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, decoder_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, decoder_decoded_andMatrixOutputs_andMatrixInput_9_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_33 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_25, decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_34 = {decoder_decoded_andMatrixOutputs_lo_hi_33, decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, decoder_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_33 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_23, decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, decoder_decoded_andMatrixOutputs_andMatrixInput_3_34}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_34 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_29, decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_34 = {decoder_decoded_andMatrixOutputs_hi_hi_34, decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_34 = {decoder_decoded_andMatrixOutputs_hi_34, decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_40_2 = &_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_16, decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_32 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_14_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_30, decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_34 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_26, decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_35 = {decoder_decoded_andMatrixOutputs_lo_hi_34, decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, decoder_decoded_andMatrixOutputs_andMatrixInput_7_32}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_34 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_24, decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_35 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_30, decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_35 = {decoder_decoded_andMatrixOutputs_hi_hi_35, decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_35 = {decoder_decoded_andMatrixOutputs_hi_35, decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_33_2 = &_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_33 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_14_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, decoder_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_31, decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_35 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_27, decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_36 = {decoder_decoded_andMatrixOutputs_lo_hi_35, decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_35, decoder_decoded_andMatrixOutputs_andMatrixInput_7_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_35 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_25, decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_36 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_31, decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_36 = {decoder_decoded_andMatrixOutputs_hi_hi_36, decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_36 = {decoder_decoded_andMatrixOutputs_hi_36, decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_67_2 = &_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_15, decoder_decoded_andMatrixOutputs_andMatrixInput_16}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_16, decoder_decoded_andMatrixOutputs_andMatrixInput_14_10}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_34 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_24, decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_24, decoder_decoded_andMatrixOutputs_andMatrixInput_12_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_28, decoder_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_36 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_28, decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_37 = {decoder_decoded_andMatrixOutputs_lo_hi_36, decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_34, decoder_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_36, decoder_decoded_andMatrixOutputs_andMatrixInput_6_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_36 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_26, decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_37, decoder_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_37 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_32, decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_37 = {decoder_decoded_andMatrixOutputs_hi_hi_37, decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53]
wire [16:0] _decoder_decoded_andMatrixOutputs_T_37 = {decoder_decoded_andMatrixOutputs_hi_37, decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_59_2 = &_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, decoder_decoded_andMatrixOutputs_andMatrixInput_17}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_11, decoder_decoded_andMatrixOutputs_andMatrixInput_15_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_35 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_25, decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_29, decoder_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_37 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_29, decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_38 = {decoder_decoded_andMatrixOutputs_lo_hi_37, decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_35, decoder_decoded_andMatrixOutputs_andMatrixInput_8_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_37, decoder_decoded_andMatrixOutputs_andMatrixInput_6_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_37 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_27, decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_38, decoder_decoded_andMatrixOutputs_andMatrixInput_4_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_2_38}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_38 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_33, decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_38 = {decoder_decoded_andMatrixOutputs_hi_hi_38, decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53]
wire [17:0] _decoder_decoded_andMatrixOutputs_T_38 = {decoder_decoded_andMatrixOutputs_hi_38, decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_5_2 = &_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_1, decoder_decoded_andMatrixOutputs_andMatrixInput_18}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_2, decoder_decoded_andMatrixOutputs_andMatrixInput_16_2}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_36 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_26, decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_18, decoder_decoded_andMatrixOutputs_andMatrixInput_14_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_28, decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_12_20}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_38 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_30, decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_39 = {decoder_decoded_andMatrixOutputs_lo_hi_38, decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_34, decoder_decoded_andMatrixOutputs_andMatrixInput_9_30}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_38, decoder_decoded_andMatrixOutputs_andMatrixInput_6_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_38 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_28, decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_39, decoder_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_39 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_34, decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_hi_39 = {decoder_decoded_andMatrixOutputs_hi_hi_39, decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53]
wire [18:0] _decoder_decoded_andMatrixOutputs_T_39 = {decoder_decoded_andMatrixOutputs_hi_39, decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_1_2 = &_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_3, decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_19, decoder_decoded_andMatrixOutputs_andMatrixInput_14_13}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_37 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_27, decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_27, decoder_decoded_andMatrixOutputs_andMatrixInput_12_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_31, decoder_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_39 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_31, decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_40 = {decoder_decoded_andMatrixOutputs_lo_hi_39, decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, decoder_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_39, decoder_decoded_andMatrixOutputs_andMatrixInput_6_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_39 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_29, decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_40, decoder_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_40 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_35, decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_40 = {decoder_decoded_andMatrixOutputs_hi_hi_40, decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53]
wire [16:0] _decoder_decoded_andMatrixOutputs_T_40 = {decoder_decoded_andMatrixOutputs_hi_40, decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_3_2 = &_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_4, decoder_decoded_andMatrixOutputs_andMatrixInput_17_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_14, decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_38 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_28, decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_32, decoder_decoded_andMatrixOutputs_andMatrixInput_10_30}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_40 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_32, decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_41 = {decoder_decoded_andMatrixOutputs_lo_hi_40, decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_38, decoder_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, decoder_decoded_andMatrixOutputs_andMatrixInput_6_40}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_40 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_30, decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_41 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_36, decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_41 = {decoder_decoded_andMatrixOutputs_hi_hi_41, decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53]
wire [17:0] _decoder_decoded_andMatrixOutputs_T_41 = {decoder_decoded_andMatrixOutputs_hi_41, decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_27_2 = &_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, decoder_decoded_andMatrixOutputs_andMatrixInput_18_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_5, decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_39 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_29, decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_21, decoder_decoded_andMatrixOutputs_andMatrixInput_14_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_31, decoder_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_12_23}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_41 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_33, decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_42 = {decoder_decoded_andMatrixOutputs_lo_hi_41, decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, decoder_decoded_andMatrixOutputs_andMatrixInput_9_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, decoder_decoded_andMatrixOutputs_andMatrixInput_6_41}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_41 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_31, decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_42 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_37, decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_hi_42 = {decoder_decoded_andMatrixOutputs_hi_hi_42, decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53]
wire [18:0] _decoder_decoded_andMatrixOutputs_T_42 = {decoder_decoded_andMatrixOutputs_hi_42, decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_53_2 = &_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_6, decoder_decoded_andMatrixOutputs_andMatrixInput_16_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_22, decoder_decoded_andMatrixOutputs_andMatrixInput_14_16}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_40 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_30, decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_30, decoder_decoded_andMatrixOutputs_andMatrixInput_12_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, decoder_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_42 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_34, decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_43 = {decoder_decoded_andMatrixOutputs_lo_hi_42, decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_40, decoder_decoded_andMatrixOutputs_andMatrixInput_8_38}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_42, decoder_decoded_andMatrixOutputs_andMatrixInput_6_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_42 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_32, decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_43, decoder_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_2_43}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_43 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_38, decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_43 = {decoder_decoded_andMatrixOutputs_hi_hi_43, decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53]
wire [16:0] _decoder_decoded_andMatrixOutputs_T_43 = {decoder_decoded_andMatrixOutputs_hi_43, decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_70_2 = &_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, decoder_decoded_andMatrixOutputs_andMatrixInput_17_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_17, decoder_decoded_andMatrixOutputs_andMatrixInput_15_7}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_41 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_31, decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_35, decoder_decoded_andMatrixOutputs_andMatrixInput_10_33}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_43 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_35, decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_44 = {decoder_decoded_andMatrixOutputs_lo_hi_43, decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, decoder_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_43, decoder_decoded_andMatrixOutputs_andMatrixInput_6_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_43 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_33, decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_44, decoder_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_44 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_39, decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_44 = {decoder_decoded_andMatrixOutputs_hi_hi_44, decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53]
wire [17:0] _decoder_decoded_andMatrixOutputs_T_44 = {decoder_decoded_andMatrixOutputs_hi_44, decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_32_2 = &_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_5, decoder_decoded_andMatrixOutputs_andMatrixInput_18_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_8, decoder_decoded_andMatrixOutputs_andMatrixInput_16_8}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_42 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_32, decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_24, decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, decoder_decoded_andMatrixOutputs_andMatrixInput_11_32}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_12_26}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_44 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_36, decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_45 = {decoder_decoded_andMatrixOutputs_lo_hi_44, decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_40, decoder_decoded_andMatrixOutputs_andMatrixInput_9_36}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_44, decoder_decoded_andMatrixOutputs_andMatrixInput_6_44}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_44 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_34, decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_45, decoder_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_2_45}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_45 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_40, decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_hi_45 = {decoder_decoded_andMatrixOutputs_hi_hi_45, decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53]
wire [18:0] _decoder_decoded_andMatrixOutputs_T_45 = {decoder_decoded_andMatrixOutputs_hi_45, decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_13_2 = &_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_9, decoder_decoded_andMatrixOutputs_andMatrixInput_16_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_25, decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_43 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_33, decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_33, decoder_decoded_andMatrixOutputs_andMatrixInput_12_27}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_37, decoder_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_45 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_37, decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_46 = {decoder_decoded_andMatrixOutputs_lo_hi_45, decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_43, decoder_decoded_andMatrixOutputs_andMatrixInput_8_41}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_45, decoder_decoded_andMatrixOutputs_andMatrixInput_6_45}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_45 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_35, decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_46, decoder_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_46 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_41, decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_46 = {decoder_decoded_andMatrixOutputs_hi_hi_46, decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53]
wire [16:0] _decoder_decoded_andMatrixOutputs_T_46 = {decoder_decoded_andMatrixOutputs_hi_46, decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_52_2 = &_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_10, decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_20, decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_44 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_34, decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_28, decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, decoder_decoded_andMatrixOutputs_andMatrixInput_10_36}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_46 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_38, decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_47 = {decoder_decoded_andMatrixOutputs_lo_hi_46, decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_44, decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_46, decoder_decoded_andMatrixOutputs_andMatrixInput_6_46}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_46 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_36, decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_47, decoder_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_47 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_42, decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_47 = {decoder_decoded_andMatrixOutputs_hi_hi_47, decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53]
wire [17:0] _decoder_decoded_andMatrixOutputs_T_47 = {decoder_decoded_andMatrixOutputs_hi_47, decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_64_2 = &_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_7, decoder_decoded_andMatrixOutputs_andMatrixInput_18_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_11, decoder_decoded_andMatrixOutputs_andMatrixInput_16_11}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_45 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_35, decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_27, decoder_decoded_andMatrixOutputs_andMatrixInput_14_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, decoder_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_12_29}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_47 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_39, decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_48 = {decoder_decoded_andMatrixOutputs_lo_hi_47, decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_43, decoder_decoded_andMatrixOutputs_andMatrixInput_9_39}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_47, decoder_decoded_andMatrixOutputs_andMatrixInput_6_47}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_47 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_37, decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_48, decoder_decoded_andMatrixOutputs_andMatrixInput_4_48}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_48 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_43, decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_hi_48 = {decoder_decoded_andMatrixOutputs_hi_hi_48, decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53]
wire [18:0] _decoder_decoded_andMatrixOutputs_T_48 = {decoder_decoded_andMatrixOutputs_hi_48, decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_11_2 = &_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_12, decoder_decoded_andMatrixOutputs_andMatrixInput_17_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_22, decoder_decoded_andMatrixOutputs_andMatrixInput_15_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_46 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_36, decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_40, decoder_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_48 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_40, decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_49 = {decoder_decoded_andMatrixOutputs_lo_hi_48, decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, decoder_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_48, decoder_decoded_andMatrixOutputs_andMatrixInput_6_48}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_48 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_38, decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, decoder_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_49 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_44, decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_49 = {decoder_decoded_andMatrixOutputs_hi_hi_49, decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53]
wire [17:0] _decoder_decoded_andMatrixOutputs_T_49 = {decoder_decoded_andMatrixOutputs_hi_49, decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_26_2 = &_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_13, decoder_decoded_andMatrixOutputs_andMatrixInput_17_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_23, decoder_decoded_andMatrixOutputs_andMatrixInput_15_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_47 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_37, decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_31, decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_41, decoder_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_49 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_41, decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_50 = {decoder_decoded_andMatrixOutputs_lo_hi_49, decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_47, decoder_decoded_andMatrixOutputs_andMatrixInput_8_45}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_49, decoder_decoded_andMatrixOutputs_andMatrixInput_6_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_49 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_39, decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, decoder_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_50 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_45, decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_50 = {decoder_decoded_andMatrixOutputs_hi_hi_50, decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53]
wire [17:0] _decoder_decoded_andMatrixOutputs_T_50 = {decoder_decoded_andMatrixOutputs_hi_50, decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_58_2 = &_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_10, decoder_decoded_andMatrixOutputs_andMatrixInput_18_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_14, decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_48 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_38, decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_30, decoder_decoded_andMatrixOutputs_andMatrixInput_14_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_12_32}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_50 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_42, decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_51 = {decoder_decoded_andMatrixOutputs_lo_hi_50, decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_46, decoder_decoded_andMatrixOutputs_andMatrixInput_9_42}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_50, decoder_decoded_andMatrixOutputs_andMatrixInput_6_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_50 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_40, decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, decoder_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_51 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_46, decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_hi_51 = {decoder_decoded_andMatrixOutputs_hi_hi_51, decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53]
wire [18:0] _decoder_decoded_andMatrixOutputs_T_51 = {decoder_decoded_andMatrixOutputs_hi_51, decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_76_2 = &_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, decoder_decoded_andMatrixOutputs_andMatrixInput_18_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_15, decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_49 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_39, decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_31, decoder_decoded_andMatrixOutputs_andMatrixInput_14_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, decoder_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_12_33}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_51 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_43, decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_52 = {decoder_decoded_andMatrixOutputs_lo_hi_51, decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_47, decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_51, decoder_decoded_andMatrixOutputs_andMatrixInput_6_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_51 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_41, decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_52 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_47, decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_hi_52 = {decoder_decoded_andMatrixOutputs_hi_hi_52, decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53]
wire [18:0] _decoder_decoded_andMatrixOutputs_T_52 = {decoder_decoded_andMatrixOutputs_hi_52, decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_51_2 = &_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_19 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_20 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_21 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_34, decoder_decoded_andMatrixOutputs_andMatrixInput_13_32}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_50 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_40, decoder_decoded_andMatrixOutputs_andMatrixInput_14_26}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_42, decoder_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_52 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_44, decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_53 = {decoder_decoded_andMatrixOutputs_lo_hi_52, decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_52, decoder_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_52 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_42, decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_53 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_48, decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_53 = {decoder_decoded_andMatrixOutputs_hi_hi_53, decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_53 = {decoder_decoded_andMatrixOutputs_hi_53, decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_2_2 = &_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_51 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_41, decoder_decoded_andMatrixOutputs_andMatrixInput_14_27}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, decoder_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_49, decoder_decoded_andMatrixOutputs_andMatrixInput_9_45}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_53 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_45, decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_54 = {decoder_decoded_andMatrixOutputs_lo_hi_53, decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_53, decoder_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_53 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_43, decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_54 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_49, decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_54 = {decoder_decoded_andMatrixOutputs_hi_hi_54, decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_54 = {decoder_decoded_andMatrixOutputs_hi_54, decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_31_2 = &_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_52 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_42, decoder_decoded_andMatrixOutputs_andMatrixInput_14_28}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_44, decoder_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, decoder_decoded_andMatrixOutputs_andMatrixInput_9_46}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_54 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_46, decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_55 = {decoder_decoded_andMatrixOutputs_lo_hi_54, decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_54, decoder_decoded_andMatrixOutputs_andMatrixInput_7_52}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_54 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_44, decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_55 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_50, decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_55 = {decoder_decoded_andMatrixOutputs_hi_hi_55, decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_55 = {decoder_decoded_andMatrixOutputs_hi_55, decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_68_2 = &_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, decoder_decoded_andMatrixOutputs_andMatrixInput_13_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_53 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_43, decoder_decoded_andMatrixOutputs_andMatrixInput_14_29}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, decoder_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_51, decoder_decoded_andMatrixOutputs_andMatrixInput_9_47}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_55 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_47, decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_56 = {decoder_decoded_andMatrixOutputs_lo_hi_55, decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, decoder_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_56, decoder_decoded_andMatrixOutputs_andMatrixInput_5_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_55 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_45, decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_56, decoder_decoded_andMatrixOutputs_andMatrixInput_3_56}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_56 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_51, decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_56 = {decoder_decoded_andMatrixOutputs_hi_hi_56, decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_56 = {decoder_decoded_andMatrixOutputs_hi_56, decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_62_2 = &_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_38, decoder_decoded_andMatrixOutputs_andMatrixInput_13_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_54 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_44, decoder_decoded_andMatrixOutputs_andMatrixInput_14_30}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_46, decoder_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, decoder_decoded_andMatrixOutputs_andMatrixInput_9_48}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_56 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_48, decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_57 = {decoder_decoded_andMatrixOutputs_lo_hi_56, decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_56, decoder_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_57, decoder_decoded_andMatrixOutputs_andMatrixInput_5_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_56 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_46, decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_57, decoder_decoded_andMatrixOutputs_andMatrixInput_3_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_57 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_52, decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_57 = {decoder_decoded_andMatrixOutputs_hi_hi_57, decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_57 = {decoder_decoded_andMatrixOutputs_hi_57, decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_65_2 = &_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_39, decoder_decoded_andMatrixOutputs_andMatrixInput_13_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_55 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_45, decoder_decoded_andMatrixOutputs_andMatrixInput_14_31}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, decoder_decoded_andMatrixOutputs_andMatrixInput_11_45}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, decoder_decoded_andMatrixOutputs_andMatrixInput_9_49}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_57 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_49, decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_58 = {decoder_decoded_andMatrixOutputs_lo_hi_57, decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_57, decoder_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_58, decoder_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_57 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_47, decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, decoder_decoded_andMatrixOutputs_andMatrixInput_3_58}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_58 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_53, decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_58 = {decoder_decoded_andMatrixOutputs_hi_hi_58, decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_58 = {decoder_decoded_andMatrixOutputs_hi_58, decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_45_2 = &_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_32, decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_40, decoder_decoded_andMatrixOutputs_andMatrixInput_13_38}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_56 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_46, decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_48, decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_54, decoder_decoded_andMatrixOutputs_andMatrixInput_9_50}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_58 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_50, decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_59 = {decoder_decoded_andMatrixOutputs_lo_hi_58, decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_58, decoder_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, decoder_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_58 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_48, decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, decoder_decoded_andMatrixOutputs_andMatrixInput_3_59}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_59 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_54, decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_59 = {decoder_decoded_andMatrixOutputs_hi_hi_59, decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53]
wire [15:0] _decoder_decoded_andMatrixOutputs_T_59 = {decoder_decoded_andMatrixOutputs_hi_59, decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_25_2 = &_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_33, decoder_decoded_andMatrixOutputs_andMatrixInput_15_17}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, decoder_decoded_andMatrixOutputs_andMatrixInput_13_39}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_57 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_47, decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_49, decoder_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_55, decoder_decoded_andMatrixOutputs_andMatrixInput_9_51}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_59 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_51, decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_60 = {decoder_decoded_andMatrixOutputs_lo_hi_59, decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_60, decoder_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_59 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_49, decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_60, decoder_decoded_andMatrixOutputs_andMatrixInput_3_60}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_60 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_55, decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_60 = {decoder_decoded_andMatrixOutputs_hi_hi_60, decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53]
wire [15:0] _decoder_decoded_andMatrixOutputs_T_60 = {decoder_decoded_andMatrixOutputs_hi_60, decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_0_2 = &_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_34, decoder_decoded_andMatrixOutputs_andMatrixInput_15_18}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_42, decoder_decoded_andMatrixOutputs_andMatrixInput_13_40}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_58 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_48, decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, decoder_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, decoder_decoded_andMatrixOutputs_andMatrixInput_9_52}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_60 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_52, decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_61 = {decoder_decoded_andMatrixOutputs_lo_hi_60, decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, decoder_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, decoder_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_60 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_50, decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, decoder_decoded_andMatrixOutputs_andMatrixInput_3_61}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_61 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_56, decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_61 = {decoder_decoded_andMatrixOutputs_hi_hi_61, decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53]
wire [15:0] _decoder_decoded_andMatrixOutputs_T_61 = {decoder_decoded_andMatrixOutputs_hi_61, decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_4_2 = &_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, decoder_decoded_andMatrixOutputs_andMatrixInput_15_19}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_59 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_49, decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_51, decoder_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, decoder_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_61 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_53, decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_62 = {decoder_decoded_andMatrixOutputs_lo_hi_61, decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_61, decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, decoder_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_61 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_51, decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, decoder_decoded_andMatrixOutputs_andMatrixInput_3_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_62 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_57, decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_62 = {decoder_decoded_andMatrixOutputs_hi_hi_62, decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53]
wire [15:0] _decoder_decoded_andMatrixOutputs_T_62 = {decoder_decoded_andMatrixOutputs_hi_62, decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_48_2 = &_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_36, decoder_decoded_andMatrixOutputs_andMatrixInput_15_20}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_44, decoder_decoded_andMatrixOutputs_andMatrixInput_13_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_60 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_50, decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_52, decoder_decoded_andMatrixOutputs_andMatrixInput_11_50}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_58, decoder_decoded_andMatrixOutputs_andMatrixInput_9_54}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_62 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_54, decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_63 = {decoder_decoded_andMatrixOutputs_lo_hi_62, decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_62, decoder_decoded_andMatrixOutputs_andMatrixInput_7_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_62 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_52, decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_63 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_58, decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_63 = {decoder_decoded_andMatrixOutputs_hi_hi_63, decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53]
wire [15:0] _decoder_decoded_andMatrixOutputs_T_63 = {decoder_decoded_andMatrixOutputs_hi_63, decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_46_2 = &_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, decoder_decoded_andMatrixOutputs_andMatrixInput_15_21}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, decoder_decoded_andMatrixOutputs_andMatrixInput_13_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_61 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_51, decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_53, decoder_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, decoder_decoded_andMatrixOutputs_andMatrixInput_9_55}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_63 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_55, decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_64 = {decoder_decoded_andMatrixOutputs_lo_hi_63, decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, decoder_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_64, decoder_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_63 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_53, decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, decoder_decoded_andMatrixOutputs_andMatrixInput_3_64}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_64 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_59, decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_64 = {decoder_decoded_andMatrixOutputs_hi_hi_64, decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53]
wire [15:0] _decoder_decoded_andMatrixOutputs_T_64 = {decoder_decoded_andMatrixOutputs_hi_64, decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_63_2 = &_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_22, decoder_decoded_andMatrixOutputs_andMatrixInput_16_16}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_44, decoder_decoded_andMatrixOutputs_andMatrixInput_14_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_62 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_52, decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, decoder_decoded_andMatrixOutputs_andMatrixInput_12_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_64 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_56, decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_65 = {decoder_decoded_andMatrixOutputs_lo_hi_64, decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_62, decoder_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_64, decoder_decoded_andMatrixOutputs_andMatrixInput_6_64}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_64 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_54, decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_65, decoder_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_65 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_60, decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_65 = {decoder_decoded_andMatrixOutputs_hi_hi_65, decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53]
wire [16:0] _decoder_decoded_andMatrixOutputs_T_65 = {decoder_decoded_andMatrixOutputs_hi_65, decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_12_2 = &_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_45, decoder_decoded_andMatrixOutputs_andMatrixInput_14_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_63 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_53, decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_53, decoder_decoded_andMatrixOutputs_andMatrixInput_12_47}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, decoder_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_65 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_57, decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_66 = {decoder_decoded_andMatrixOutputs_lo_hi_65, decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_63, decoder_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_65, decoder_decoded_andMatrixOutputs_andMatrixInput_6_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_65 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_55, decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_66, decoder_decoded_andMatrixOutputs_andMatrixInput_4_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_2_66}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_66 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_61, decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_66 = {decoder_decoded_andMatrixOutputs_hi_hi_66, decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53]
wire [16:0] _decoder_decoded_andMatrixOutputs_T_66 = {decoder_decoded_andMatrixOutputs_hi_66, decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_56_2 = &_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_24, decoder_decoded_andMatrixOutputs_andMatrixInput_16_18}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_17_12}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_64 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_54, decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_46, decoder_decoded_andMatrixOutputs_andMatrixInput_14_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_56, decoder_decoded_andMatrixOutputs_andMatrixInput_11_54}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_12_48}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_66 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_58, decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_lo_67 = {decoder_decoded_andMatrixOutputs_lo_hi_66, decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_62, decoder_decoded_andMatrixOutputs_andMatrixInput_9_58}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_66, decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_66 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_56, decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_67, decoder_decoded_andMatrixOutputs_andMatrixInput_4_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_67 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_62, decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_hi_67 = {decoder_decoded_andMatrixOutputs_hi_hi_67, decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53]
wire [19:0] _decoder_decoded_andMatrixOutputs_T_67 = {decoder_decoded_andMatrixOutputs_hi_67, decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_35_2 = &_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_1, decoder_decoded_andMatrixOutputs_andMatrixInput_20}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_19, decoder_decoded_andMatrixOutputs_andMatrixInput_17_13}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_18_7}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_65 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_55, decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_41, decoder_decoded_andMatrixOutputs_andMatrixInput_15_25}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_55, decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_13_47}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_67 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_59, decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_lo_68 = {decoder_decoded_andMatrixOutputs_lo_hi_67, decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, decoder_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_67, decoder_decoded_andMatrixOutputs_andMatrixInput_7_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_8_63}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_67 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_57, decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_68, decoder_decoded_andMatrixOutputs_andMatrixInput_4_68}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_2_68}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_68 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_63, decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53]
wire [10:0] decoder_decoded_andMatrixOutputs_hi_68 = {decoder_decoded_andMatrixOutputs_hi_hi_68, decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53]
wire [20:0] _decoder_decoded_andMatrixOutputs_T_68 = {decoder_decoded_andMatrixOutputs_hi_68, decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_34_2 = &_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_26, decoder_decoded_andMatrixOutputs_andMatrixInput_16_20}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_66 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_56, decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_48, decoder_decoded_andMatrixOutputs_andMatrixInput_14_42}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_58, decoder_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_68 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_60, decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_lo_69 = {decoder_decoded_andMatrixOutputs_lo_hi_68, decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_64, decoder_decoded_andMatrixOutputs_andMatrixInput_9_60}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_68, decoder_decoded_andMatrixOutputs_andMatrixInput_6_68}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_7_66}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_68 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_58, decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_69, decoder_decoded_andMatrixOutputs_andMatrixInput_4_69}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_69 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_64, decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_hi_69 = {decoder_decoded_andMatrixOutputs_hi_hi_69, decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53]
wire [19:0] _decoder_decoded_andMatrixOutputs_T_69 = {decoder_decoded_andMatrixOutputs_hi_69, decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_20_2 = &_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_3, decoder_decoded_andMatrixOutputs_andMatrixInput_20_1}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_21, decoder_decoded_andMatrixOutputs_andMatrixInput_17_15}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_18_9}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_67 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_57, decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_43, decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_57, decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_69 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_61, decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_lo_70 = {decoder_decoded_andMatrixOutputs_lo_hi_69, decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, decoder_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, decoder_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_69 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_59, decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_70 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_65, decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53]
wire [10:0] decoder_decoded_andMatrixOutputs_hi_70 = {decoder_decoded_andMatrixOutputs_hi_hi_70, decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53]
wire [20:0] _decoder_decoded_andMatrixOutputs_T_70 = {decoder_decoded_andMatrixOutputs_hi_70, decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_7_2 = &_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, decoder_decoded_andMatrixOutputs_andMatrixInput_21}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_16, decoder_decoded_andMatrixOutputs_andMatrixInput_18_10}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_68 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_58, decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_44, decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_16_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_58, decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_lo_hi_70 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_62, decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53]
wire [10:0] decoder_decoded_andMatrixOutputs_lo_71 = {decoder_decoded_andMatrixOutputs_lo_hi_70, decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_62, decoder_decoded_andMatrixOutputs_andMatrixInput_10_60}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, decoder_decoded_andMatrixOutputs_andMatrixInput_7_68}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_8_66}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_70 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_60, decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_71, decoder_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_71 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_66, decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53]
wire [10:0] decoder_decoded_andMatrixOutputs_hi_71 = {decoder_decoded_andMatrixOutputs_hi_hi_71, decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53]
wire [21:0] _decoder_decoded_andMatrixOutputs_T_71 = {decoder_decoded_andMatrixOutputs_hi_71, decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_17_2 = &_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_5, decoder_decoded_andMatrixOutputs_andMatrixInput_20_3}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_23, decoder_decoded_andMatrixOutputs_andMatrixInput_17_17}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_18_11}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_69 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_59, decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_45, decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_59, decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_71 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_63, decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_lo_72 = {decoder_decoded_andMatrixOutputs_lo_hi_71, decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_63, decoder_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_71, decoder_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_71 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_61, decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_72, decoder_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_72 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_67, decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53]
wire [10:0] decoder_decoded_andMatrixOutputs_hi_72 = {decoder_decoded_andMatrixOutputs_hi_hi_72, decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53]
wire [20:0] _decoder_decoded_andMatrixOutputs_T_72 = {decoder_decoded_andMatrixOutputs_hi_72, decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_36_2 = &_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_6, decoder_decoded_andMatrixOutputs_andMatrixInput_20_4}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, decoder_decoded_andMatrixOutputs_andMatrixInput_17_18}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_18_12}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_70 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_60, decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_46, decoder_decoded_andMatrixOutputs_andMatrixInput_15_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_60, decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_72 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_64, decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_lo_73 = {decoder_decoded_andMatrixOutputs_lo_hi_72, decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, decoder_decoded_andMatrixOutputs_andMatrixInput_10_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_72, decoder_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_72 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_62, decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_73, decoder_decoded_andMatrixOutputs_andMatrixInput_4_73}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, decoder_decoded_andMatrixOutputs_andMatrixInput_2_73}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_73 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_68, decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53]
wire [10:0] decoder_decoded_andMatrixOutputs_hi_73 = {decoder_decoded_andMatrixOutputs_hi_hi_73, decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53]
wire [20:0] _decoder_decoded_andMatrixOutputs_T_73 = {decoder_decoded_andMatrixOutputs_hi_73, decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_22_2 = &_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_7, decoder_decoded_andMatrixOutputs_andMatrixInput_20_5}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_25, decoder_decoded_andMatrixOutputs_andMatrixInput_17_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_18_13}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_71 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_61, decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_47, decoder_decoded_andMatrixOutputs_andMatrixInput_15_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_61, decoder_decoded_andMatrixOutputs_andMatrixInput_12_55}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_13_53}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_73 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_65, decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_lo_74 = {decoder_decoded_andMatrixOutputs_lo_hi_73, decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_65, decoder_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_73, decoder_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_73 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_63, decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_74, decoder_decoded_andMatrixOutputs_andMatrixInput_4_74}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, decoder_decoded_andMatrixOutputs_andMatrixInput_2_74}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_74 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_69, decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53]
wire [10:0] decoder_decoded_andMatrixOutputs_hi_74 = {decoder_decoded_andMatrixOutputs_hi_hi_74, decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53]
wire [20:0] _decoder_decoded_andMatrixOutputs_T_74 = {decoder_decoded_andMatrixOutputs_hi_74, decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_14_2 = &_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_8, decoder_decoded_andMatrixOutputs_andMatrixInput_20_6}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_18_14}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_72 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_62, decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_48, decoder_decoded_andMatrixOutputs_andMatrixInput_15_32}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_62, decoder_decoded_andMatrixOutputs_andMatrixInput_12_56}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_13_54}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_74 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_66, decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_lo_75 = {decoder_decoded_andMatrixOutputs_lo_hi_74, decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_66, decoder_decoded_andMatrixOutputs_andMatrixInput_10_64}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_74, decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_74 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_64, decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, decoder_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_5_74}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, decoder_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_75 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_70, decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53]
wire [10:0] decoder_decoded_andMatrixOutputs_hi_75 = {decoder_decoded_andMatrixOutputs_hi_hi_75, decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53]
wire [20:0] _decoder_decoded_andMatrixOutputs_T_75 = {decoder_decoded_andMatrixOutputs_hi_75, decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_28_2 = &_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, decoder_decoded_andMatrixOutputs_andMatrixInput_21_1}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_21, decoder_decoded_andMatrixOutputs_andMatrixInput_18_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_73 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_63, decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_49, decoder_decoded_andMatrixOutputs_andMatrixInput_15_33}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_16_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_63, decoder_decoded_andMatrixOutputs_andMatrixInput_12_57}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_13_55}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_lo_hi_75 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_67, decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53]
wire [10:0] decoder_decoded_andMatrixOutputs_lo_76 = {decoder_decoded_andMatrixOutputs_lo_hi_75, decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_67, decoder_decoded_andMatrixOutputs_andMatrixInput_10_65}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_75, decoder_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_75 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_65, decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, decoder_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_5_75}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, decoder_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_76 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_71, decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53]
wire [10:0] decoder_decoded_andMatrixOutputs_hi_76 = {decoder_decoded_andMatrixOutputs_hi_hi_76, decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53]
wire [21:0] _decoder_decoded_andMatrixOutputs_T_76 = {decoder_decoded_andMatrixOutputs_hi_76, decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_54_2 = &_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo = {decoder_decoded_andMatrixOutputs_65_2, decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi = {decoder_decoded_andMatrixOutputs_68_2, decoder_decoded_andMatrixOutputs_62_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo = {decoder_decoded_orMatrixOutputs_lo_lo_hi, decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo = {decoder_decoded_andMatrixOutputs_2_2, decoder_decoded_andMatrixOutputs_31_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN = {decoder_decoded_andMatrixOutputs_26_2, decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_lo_hi_hi = _GEN; // @[pla.scala:114:19]
wire [1:0] _decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:19]
assign _decoder_decoded_orMatrixOutputs_T_2 = _GEN; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_1; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = _GEN; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_2; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = _GEN; // @[pla.scala:114:19]
wire [3:0] decoder_decoded_orMatrixOutputs_lo_hi = {decoder_decoded_orMatrixOutputs_lo_hi_hi, decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19]
wire [7:0] decoder_decoded_orMatrixOutputs_lo = {decoder_decoded_orMatrixOutputs_lo_hi, decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo = {decoder_decoded_andMatrixOutputs_70_2, decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi = {decoder_decoded_andMatrixOutputs_59_2, decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] decoder_decoded_orMatrixOutputs_hi_lo = {decoder_decoded_orMatrixOutputs_hi_lo_hi, decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo = {decoder_decoded_andMatrixOutputs_33_2, decoder_decoded_andMatrixOutputs_67_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_0 = {decoder_decoded_andMatrixOutputs_72_2, decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = _GEN_0; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_6; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = _GEN_0; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = _GEN_0; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_0; // @[pla.scala:114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi = {decoder_decoded_orMatrixOutputs_hi_hi_hi, decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19]
wire [8:0] decoder_decoded_orMatrixOutputs_hi = {decoder_decoded_orMatrixOutputs_hi_hi, decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19]
wire [16:0] _decoder_decoded_orMatrixOutputs_T = {decoder_decoded_orMatrixOutputs_hi, decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_1 = |_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}]
wire _decoder_decoded_orMatrixOutputs_T_3 = |_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}]
wire [1:0] _decoder_decoded_orMatrixOutputs_T_4 = {decoder_decoded_andMatrixOutputs_69_2, decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19]
wire _decoder_decoded_orMatrixOutputs_T_5 = |_decoder_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_1 = {decoder_decoded_andMatrixOutputs_41_2, decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_1; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_lo_1 = _GEN_1; // @[pla.scala:114:19]
wire [1:0] _decoder_decoded_orMatrixOutputs_T_22; // @[pla.scala:114:19]
assign _decoder_decoded_orMatrixOutputs_T_22 = _GEN_1; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_1 = {decoder_decoded_andMatrixOutputs_72_2, decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_1 = {decoder_decoded_orMatrixOutputs_hi_hi_1, decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] _decoder_decoded_orMatrixOutputs_T_6 = {decoder_decoded_orMatrixOutputs_hi_1, decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_7 = |_decoder_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_1 = {decoder_decoded_andMatrixOutputs_32_2, decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_1 = {decoder_decoded_andMatrixOutputs_5_2, decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] decoder_decoded_orMatrixOutputs_lo_2 = {decoder_decoded_orMatrixOutputs_lo_hi_1, decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_1 = {decoder_decoded_andMatrixOutputs_73_2, decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_2 = {decoder_decoded_andMatrixOutputs_61_2, decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_2; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_hi_2 = _GEN_2; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_7; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_lo_lo_7 = _GEN_2; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = _GEN_2; // @[pla.scala:114:19]
wire [3:0] decoder_decoded_orMatrixOutputs_hi_2 = {decoder_decoded_orMatrixOutputs_hi_hi_2, decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19]
wire [7:0] _decoder_decoded_orMatrixOutputs_T_8 = {decoder_decoded_orMatrixOutputs_hi_2, decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_9 = |_decoder_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_3 = {decoder_decoded_andMatrixOutputs_35_2, decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_2; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_lo_lo_2 = _GEN_3; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_1; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = _GEN_3; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {decoder_decoded_andMatrixOutputs_62_2, decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_2 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_lo_3 = {decoder_decoded_orMatrixOutputs_lo_hi_2, decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_2 = {decoder_decoded_andMatrixOutputs_31_2, decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_4 = {decoder_decoded_andMatrixOutputs_66_2, decoder_decoded_andMatrixOutputs_47_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_1; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = _GEN_4; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_5; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = _GEN_4; // @[pla.scala:114:19]
wire [1:0] _decoder_decoded_orMatrixOutputs_T_24; // @[pla.scala:114:19]
assign _decoder_decoded_orMatrixOutputs_T_24 = _GEN_4; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_5; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = _GEN_4; // @[pla.scala:114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_3 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_hi_3 = {decoder_decoded_orMatrixOutputs_hi_hi_3, decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19]
wire [9:0] _decoder_decoded_orMatrixOutputs_T_10 = {decoder_decoded_orMatrixOutputs_hi_3, decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_11 = |_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_5 = {decoder_decoded_andMatrixOutputs_14_2, decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_4; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_lo_4 = _GEN_5; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_2; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = _GEN_5; // @[pla.scala:114:19]
wire [1:0] _GEN_6 = {decoder_decoded_andMatrixOutputs_46_2, decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_4; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_4 = _GEN_6; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_4; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = _GEN_6; // @[pla.scala:114:19]
wire [3:0] _decoder_decoded_orMatrixOutputs_T_12 = {decoder_decoded_orMatrixOutputs_hi_4, decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_13 = |_decoder_decoded_orMatrixOutputs_T_12; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_3 = {decoder_decoded_andMatrixOutputs_12_2, decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = {decoder_decoded_andMatrixOutputs_1_2, decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_3 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_lo_5 = {decoder_decoded_orMatrixOutputs_lo_hi_3, decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {decoder_decoded_andMatrixOutputs_50_2, decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_3 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_7 = {decoder_decoded_andMatrixOutputs_6_2, decoder_decoded_andMatrixOutputs_55_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_2; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = _GEN_7; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_4; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = _GEN_7; // @[pla.scala:114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_4 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] decoder_decoded_orMatrixOutputs_hi_5 = {decoder_decoded_orMatrixOutputs_hi_hi_4, decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19]
wire [10:0] _decoder_decoded_orMatrixOutputs_T_14 = {decoder_decoded_orMatrixOutputs_hi_5, decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_15 = |_decoder_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {decoder_decoded_andMatrixOutputs_36_2, decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_4 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_1, decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = {decoder_decoded_andMatrixOutputs_32_2, decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_4 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] decoder_decoded_orMatrixOutputs_lo_6 = {decoder_decoded_orMatrixOutputs_lo_hi_4, decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19]
wire [1:0] _GEN_8 = {decoder_decoded_andMatrixOutputs_38_2, decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_2; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = _GEN_8; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_4; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = _GEN_8; // @[pla.scala:114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_4 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = {decoder_decoded_andMatrixOutputs_15_2, decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_5 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_39_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] decoder_decoded_orMatrixOutputs_hi_6 = {decoder_decoded_orMatrixOutputs_hi_hi_5, decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19]
wire [11:0] _decoder_decoded_orMatrixOutputs_T_16 = {decoder_decoded_orMatrixOutputs_hi_6, decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_17 = |_decoder_decoded_orMatrixOutputs_T_16; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_5 = {decoder_decoded_andMatrixOutputs_17_2, decoder_decoded_andMatrixOutputs_54_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {decoder_decoded_andMatrixOutputs_11_2, decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_5 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_lo_7 = {decoder_decoded_orMatrixOutputs_lo_hi_5, decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = {decoder_decoded_andMatrixOutputs_21_2, decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_5 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_6 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] decoder_decoded_orMatrixOutputs_hi_7 = {decoder_decoded_orMatrixOutputs_hi_hi_6, decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19]
wire [10:0] _decoder_decoded_orMatrixOutputs_T_18 = {decoder_decoded_orMatrixOutputs_hi_7, decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_19 = |_decoder_decoded_orMatrixOutputs_T_18; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {decoder_decoded_andMatrixOutputs_34_2, decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_6 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_2, decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = {decoder_decoded_andMatrixOutputs_5_2, decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_6 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] decoder_decoded_orMatrixOutputs_lo_8 = {decoder_decoded_orMatrixOutputs_lo_hi_6, decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_6 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {decoder_decoded_andMatrixOutputs_29_2, decoder_decoded_andMatrixOutputs_39_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi_7 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_5, decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19]
wire [6:0] decoder_decoded_orMatrixOutputs_hi_8 = {decoder_decoded_orMatrixOutputs_hi_hi_7, decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19]
wire [12:0] _decoder_decoded_orMatrixOutputs_T_20 = {decoder_decoded_orMatrixOutputs_hi_8, decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_21 = |_decoder_decoded_orMatrixOutputs_T_20; // @[pla.scala:114:{19,36}]
wire _decoder_decoded_orMatrixOutputs_T_23 = |_decoder_decoded_orMatrixOutputs_T_22; // @[pla.scala:114:{19,36}]
wire _decoder_decoded_orMatrixOutputs_T_25 = |_decoder_decoded_orMatrixOutputs_T_24; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {decoder_decoded_andMatrixOutputs_24_2, decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_7 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_57_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_lo_9 = {decoder_decoded_orMatrixOutputs_lo_hi_7, decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_7 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_8 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] decoder_decoded_orMatrixOutputs_hi_9 = {decoder_decoded_orMatrixOutputs_hi_hi_8, decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19]
wire [10:0] _decoder_decoded_orMatrixOutputs_T_27 = {decoder_decoded_orMatrixOutputs_hi_9, decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_28 = |_decoder_decoded_orMatrixOutputs_T_27; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {decoder_decoded_andMatrixOutputs_0_2, decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_8 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_3, decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {decoder_decoded_andMatrixOutputs_3_2, decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_8 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_7, decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19]
wire [8:0] decoder_decoded_orMatrixOutputs_lo_10 = {decoder_decoded_orMatrixOutputs_lo_hi_8, decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {decoder_decoded_andMatrixOutputs_44_2, decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {decoder_decoded_andMatrixOutputs_9_2, decoder_decoded_andMatrixOutputs_57_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_8 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_6, decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {decoder_decoded_andMatrixOutputs_49_2, decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_9 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_7, decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19]
wire [9:0] decoder_decoded_orMatrixOutputs_hi_10 = {decoder_decoded_orMatrixOutputs_hi_hi_9, decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19]
wire [18:0] _decoder_decoded_orMatrixOutputs_T_29 = {decoder_decoded_orMatrixOutputs_hi_10, decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_30 = |_decoder_decoded_orMatrixOutputs_T_29; // @[pla.scala:114:{19,36}]
wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_9 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_4, decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_27_2, decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_9 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_8, decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19]
wire [8:0] decoder_decoded_orMatrixOutputs_lo_11 = {decoder_decoded_orMatrixOutputs_lo_hi_9, decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {decoder_decoded_andMatrixOutputs_23_2, decoder_decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_73_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_9 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_7, decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {decoder_decoded_andMatrixOutputs_30_2, decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_10 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_8, decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19]
wire [9:0] decoder_decoded_orMatrixOutputs_hi_11 = {decoder_decoded_orMatrixOutputs_hi_hi_10, decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19]
wire [18:0] _decoder_decoded_orMatrixOutputs_T_31 = {decoder_decoded_orMatrixOutputs_hi_11, decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_32 = |_decoder_decoded_orMatrixOutputs_T_31; // @[pla.scala:114:{19,36}]
wire [1:0] _decoder_decoded_orMatrixOutputs_T_33 = {decoder_decoded_andMatrixOutputs_71_2, decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19]
wire _decoder_decoded_orMatrixOutputs_T_34 = |_decoder_decoded_orMatrixOutputs_T_33; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {_decoder_decoded_orMatrixOutputs_T_1, 1'h0}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {_decoder_decoded_orMatrixOutputs_T_5, _decoder_decoded_orMatrixOutputs_T_3}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_10 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_5, decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:102:36]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = {_decoder_decoded_orMatrixOutputs_T_9, _decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = {_decoder_decoded_orMatrixOutputs_T_15, _decoder_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, _decoder_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_10 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_9, decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:102:36]
wire [8:0] decoder_decoded_orMatrixOutputs_lo_12 = {decoder_decoded_orMatrixOutputs_lo_hi_10, decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:102:36]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = {_decoder_decoded_orMatrixOutputs_T_19, _decoder_decoded_orMatrixOutputs_T_17}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = {_decoder_decoded_orMatrixOutputs_T_25, _decoder_decoded_orMatrixOutputs_T_23}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, _decoder_decoded_orMatrixOutputs_T_21}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_10 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_8, decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:102:36]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = {_decoder_decoded_orMatrixOutputs_T_28, _decoder_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = {_decoder_decoded_orMatrixOutputs_T_34, _decoder_decoded_orMatrixOutputs_T_32}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, _decoder_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_11 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_9, decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:102:36]
wire [9:0] decoder_decoded_orMatrixOutputs_hi_12 = {decoder_decoded_orMatrixOutputs_hi_hi_11, decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:102:36]
wire [18:0] decoder_decoded_orMatrixOutputs = {decoder_decoded_orMatrixOutputs_hi_12, decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:102:36]
wire _decoder_decoded_invMatrixOutputs_T = decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_1 = decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_2 = decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_3 = decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_4 = decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_5 = decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_6 = decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_7 = decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_8 = decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_9 = decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_10 = decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_11 = decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_12 = decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_13 = decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_14 = decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_15 = decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_16 = decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_17 = decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_18 = decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31]
wire [1:0] decoder_decoded_invMatrixOutputs_lo_lo_lo = {_decoder_decoded_invMatrixOutputs_T_1, _decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoder_decoded_invMatrixOutputs_lo_lo_hi = {_decoder_decoded_invMatrixOutputs_T_3, _decoder_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoder_decoded_invMatrixOutputs_lo_lo = {decoder_decoded_invMatrixOutputs_lo_lo_hi, decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoder_decoded_invMatrixOutputs_lo_hi_lo = {_decoder_decoded_invMatrixOutputs_T_5, _decoder_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {_decoder_decoded_invMatrixOutputs_T_8, _decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoder_decoded_invMatrixOutputs_lo_hi_hi = {decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, _decoder_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoder_decoded_invMatrixOutputs_lo_hi = {decoder_decoded_invMatrixOutputs_lo_hi_hi, decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoder_decoded_invMatrixOutputs_lo = {decoder_decoded_invMatrixOutputs_lo_hi, decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoder_decoded_invMatrixOutputs_hi_lo_lo = {_decoder_decoded_invMatrixOutputs_T_10, _decoder_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {_decoder_decoded_invMatrixOutputs_T_13, _decoder_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoder_decoded_invMatrixOutputs_hi_lo_hi = {decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, _decoder_decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoder_decoded_invMatrixOutputs_hi_lo = {decoder_decoded_invMatrixOutputs_hi_lo_hi, decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoder_decoded_invMatrixOutputs_hi_hi_lo = {_decoder_decoded_invMatrixOutputs_T_15, _decoder_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {_decoder_decoded_invMatrixOutputs_T_18, _decoder_decoded_invMatrixOutputs_T_17}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoder_decoded_invMatrixOutputs_hi_hi_hi = {decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, _decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoder_decoded_invMatrixOutputs_hi_hi = {decoder_decoded_invMatrixOutputs_hi_hi_hi, decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoder_decoded_invMatrixOutputs_hi = {decoder_decoded_invMatrixOutputs_hi_hi, decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37]
assign decoder_decoded_invMatrixOutputs = {decoder_decoded_invMatrixOutputs_hi, decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37]
assign decoder_decoded = decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37]
assign decoder_0 = decoder_decoded[18]; // @[pla.scala:81:23]
assign io_sigs_ldst_0 = decoder_0; // @[FPU.scala:55:7]
assign decoder_1 = decoder_decoded[17]; // @[pla.scala:81:23]
assign io_sigs_wen_0 = decoder_1; // @[FPU.scala:55:7]
assign decoder_2 = decoder_decoded[16]; // @[pla.scala:81:23]
assign io_sigs_ren1_0 = decoder_2; // @[FPU.scala:55:7]
assign decoder_3 = decoder_decoded[15]; // @[pla.scala:81:23]
assign io_sigs_ren2_0 = decoder_3; // @[FPU.scala:55:7]
assign decoder_4 = decoder_decoded[14]; // @[pla.scala:81:23]
assign io_sigs_ren3_0 = decoder_4; // @[FPU.scala:55:7]
assign decoder_5 = decoder_decoded[13]; // @[pla.scala:81:23]
assign io_sigs_swap12_0 = decoder_5; // @[FPU.scala:55:7]
assign decoder_6 = decoder_decoded[12]; // @[pla.scala:81:23]
assign io_sigs_swap23_0 = decoder_6; // @[FPU.scala:55:7]
assign decoder_7 = decoder_decoded[11:10]; // @[pla.scala:81:23]
assign io_sigs_typeTagIn_0 = decoder_7; // @[FPU.scala:55:7]
assign decoder_8 = decoder_decoded[9:8]; // @[pla.scala:81:23]
assign io_sigs_typeTagOut_0 = decoder_8; // @[FPU.scala:55:7]
assign decoder_9 = decoder_decoded[7]; // @[pla.scala:81:23]
assign io_sigs_fromint_0 = decoder_9; // @[FPU.scala:55:7]
assign decoder_10 = decoder_decoded[6]; // @[pla.scala:81:23]
assign io_sigs_toint_0 = decoder_10; // @[FPU.scala:55:7]
assign decoder_11 = decoder_decoded[5]; // @[pla.scala:81:23]
assign io_sigs_fastpipe_0 = decoder_11; // @[FPU.scala:55:7]
assign decoder_12 = decoder_decoded[4]; // @[pla.scala:81:23]
assign io_sigs_fma_0 = decoder_12; // @[FPU.scala:55:7]
assign decoder_13 = decoder_decoded[3]; // @[pla.scala:81:23]
assign io_sigs_div_0 = decoder_13; // @[FPU.scala:55:7]
assign decoder_14 = decoder_decoded[2]; // @[pla.scala:81:23]
assign io_sigs_sqrt_0 = decoder_14; // @[FPU.scala:55:7]
assign decoder_15 = decoder_decoded[1]; // @[pla.scala:81:23]
assign io_sigs_wflags_0 = decoder_15; // @[FPU.scala:55:7]
assign decoder_16 = decoder_decoded[0]; // @[pla.scala:81:23]
assign io_sigs_vec_0 = decoder_16; // @[FPU.scala:55:7]
assign io_sigs_ldst = io_sigs_ldst_0; // @[FPU.scala:55:7]
assign io_sigs_wen = io_sigs_wen_0; // @[FPU.scala:55:7]
assign io_sigs_ren1 = io_sigs_ren1_0; // @[FPU.scala:55:7]
assign io_sigs_ren2 = io_sigs_ren2_0; // @[FPU.scala:55:7]
assign io_sigs_ren3 = io_sigs_ren3_0; // @[FPU.scala:55:7]
assign io_sigs_swap12 = io_sigs_swap12_0; // @[FPU.scala:55:7]
assign io_sigs_swap23 = io_sigs_swap23_0; // @[FPU.scala:55:7]
assign io_sigs_typeTagIn = io_sigs_typeTagIn_0; // @[FPU.scala:55:7]
assign io_sigs_typeTagOut = io_sigs_typeTagOut_0; // @[FPU.scala:55:7]
assign io_sigs_fromint = io_sigs_fromint_0; // @[FPU.scala:55:7]
assign io_sigs_toint = io_sigs_toint_0; // @[FPU.scala:55:7]
assign io_sigs_fastpipe = io_sigs_fastpipe_0; // @[FPU.scala:55:7]
assign io_sigs_fma = io_sigs_fma_0; // @[FPU.scala:55:7]
assign io_sigs_div = io_sigs_div_0; // @[FPU.scala:55:7]
assign io_sigs_sqrt = io_sigs_sqrt_0; // @[FPU.scala:55:7]
assign io_sigs_wflags = io_sigs_wflags_0; // @[FPU.scala:55:7]
assign io_sigs_vec = io_sigs_vec_0; // @[FPU.scala:55:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
|
module OptimizationBarrier_TLBEntryData_161( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Replacement.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import freechips.rocketchip.util.property.cover
abstract class ReplacementPolicy {
def nBits: Int
def perSet: Boolean
def way: UInt
def miss: Unit
def hit: Unit
def access(touch_way: UInt): Unit
def access(touch_ways: Seq[Valid[UInt]]): Unit
def state_read: UInt
def get_next_state(state: UInt, touch_way: UInt): UInt
def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = {
touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev))
}
def get_replace_way(state: UInt): UInt
}
object ReplacementPolicy {
def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match {
case "random" => new RandomReplacement(n_ways)
case "lru" => new TrueLRU(n_ways)
case "plru" => new PseudoLRU(n_ways)
case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t")
}
}
class RandomReplacement(n_ways: Int) extends ReplacementPolicy {
private val replace = Wire(Bool())
replace := false.B
def nBits = 16
def perSet = false
private val lfsr = LFSR(nBits, replace)
def state_read = WireDefault(lfsr)
def way = Random(n_ways, lfsr)
def miss = replace := true.B
def hit = {}
def access(touch_way: UInt) = {}
def access(touch_ways: Seq[Valid[UInt]]) = {}
def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare
def get_replace_way(state: UInt) = way
}
abstract class SeqReplacementPolicy {
def access(set: UInt): Unit
def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit
def way: UInt
}
abstract class SetAssocReplacementPolicy {
def access(set: UInt, touch_way: UInt): Unit
def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit
def way(set: UInt): UInt
}
class SeqRandom(n_ways: Int) extends SeqReplacementPolicy {
val logic = new RandomReplacement(n_ways)
def access(set: UInt) = { }
def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = {
when (valid && !hit) { logic.miss }
}
def way = logic.way
}
class TrueLRU(n_ways: Int) extends ReplacementPolicy {
// True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others.
// The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits):
// [5] - 3 more recent than 2
// [4] - 3 more recent than 1
// [3] - 2 more recent than 1
// [2] - 3 more recent than 0
// [1] - 2 more recent than 0
// [0] - 1 more recent than 0
def nBits = (n_ways * (n_ways-1)) / 2
def perSet = true
private val state_reg = RegInit(0.U(nBits.W))
def state_read = WireDefault(state_reg)
private def extractMRUVec(state: UInt): Seq[UInt] = {
// Extract per-way information about which higher-indexed ways are more recently used
val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W)))
var lsb = 0
for (i <- 0 until n_ways-1) {
moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W))
lsb = lsb + (n_ways - i - 1)
}
moreRecentVec
}
def get_next_state(state: UInt, touch_way: UInt): UInt = {
val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W)))
val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix
val wayDec = UIntToOH(touch_way, n_ways)
// Compute next value of triangular matrix
// set the touched way as more recent than every other way
nextState.zipWithIndex.map { case (e, i) =>
e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) | wayDec)
}
nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1
}
def access(touch_way: UInt): Unit = {
state_reg := get_next_state(state_reg, touch_way)
}
def access(touch_ways: Seq[Valid[UInt]]): Unit = {
when (touch_ways.map(_.valid).orR) {
state_reg := get_next_state(state_reg, touch_ways)
}
for (i <- 1 until touch_ways.size) {
cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous")
}
}
def get_replace_way(state: UInt): UInt = {
val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix
// For each way, determine if all other ways are more recent
val mruWayDec = (0 until n_ways).map { i =>
val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR)
val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _))
upperMoreRecent && lowerMoreRecent
}
OHToUInt(mruWayDec)
}
def way = get_replace_way(state_reg)
def miss = access(way)
def hit = {}
@deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05")
def replace: UInt = way
}
class PseudoLRU(n_ways: Int) extends ReplacementPolicy {
// Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU
//
//
// - bits storage example for 4-way PLRU binary tree:
// bit[2]: ways 3+2 older than ways 1+0
// / \
// bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0
//
//
// - bits storage example for 3-way PLRU binary tree:
// bit[1]: way 2 older than ways 1+0
// \
// bit[0]: way 1 older than way 0
//
//
// - bits storage example for 8-way PLRU binary tree:
// bit[6]: ways 7-4 older than ways 3-0
// / \
// bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0
// / \ / \
// bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0
def nBits = n_ways - 1
def perSet = true
private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W))
def state_read = WireDefault(state_reg)
def access(touch_way: UInt): Unit = {
state_reg := get_next_state(state_reg, touch_way)
}
def access(touch_ways: Seq[Valid[UInt]]): Unit = {
when (touch_ways.map(_.valid).orR) {
state_reg := get_next_state(state_reg, touch_ways)
}
for (i <- 1 until touch_ways.size) {
cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous")
}
}
/** @param state state_reg bits for this sub-tree
* @param touch_way touched way encoded value bits for this sub-tree
* @param tree_nways number of ways in this sub-tree
*/
def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = {
require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways")
require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways")
if (tree_nways > 2) {
// we are at a branching node in the tree, so recurse
val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree
val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree
val set_left_older = !touch_way(log2Ceil(tree_nways)-1)
val left_subtree_state = state.extract(tree_nways-3, right_nways-1)
val right_subtree_state = state(right_nways-2, 0)
if (left_nways > 1) {
// we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees
Cat(set_left_older,
Mux(set_left_older,
left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree
get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer
Mux(set_left_older,
get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer
right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree
} else {
// we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree
Cat(set_left_older,
Mux(set_left_older,
get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer
right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree
}
} else if (tree_nways == 2) {
// we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value
!touch_way(0)
} else { // tree_nways <= 1
// we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires)
0.U(1.W)
}
}
def get_next_state(state: UInt, touch_way: UInt): UInt = {
val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways))
else touch_way.extract(log2Ceil(n_ways)-1,0)
get_next_state(state, touch_way_sized, n_ways)
}
/** @param state state_reg bits for this sub-tree
* @param tree_nways number of ways in this sub-tree
*/
def get_replace_way(state: UInt, tree_nways: Int): UInt = {
require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways")
// this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb
if (tree_nways > 2) {
// we are at a branching node in the tree, so recurse
val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree
val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree
val left_subtree_older = state(tree_nways-2)
val left_subtree_state = state.extract(tree_nways-3, right_nways-1)
val right_subtree_state = state(right_nways-2, 0)
if (left_nways > 1) {
// we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees
Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value
Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right
get_replace_way(left_subtree_state, left_nways), // recurse left
get_replace_way(right_subtree_state, right_nways))) // recurse right
} else {
// we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree
Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value
Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right
0.U(1.W),
get_replace_way(right_subtree_state, right_nways))) // recurse right
}
} else if (tree_nways == 2) {
// we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value
state(0)
} else { // tree_nways <= 1
// we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value
0.U(1.W)
}
}
def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways)
def way = get_replace_way(state_reg)
def miss = access(way)
def hit = {}
}
class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy {
val logic = new PseudoLRU(n_ways)
val state = SyncReadMem(n_sets, UInt(logic.nBits.W))
val current_state = Wire(UInt(logic.nBits.W))
val next_state = Wire(UInt(logic.nBits.W))
val plru_way = logic.get_replace_way(current_state)
def access(set: UInt) = {
current_state := state.read(set)
}
def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = {
val update_way = Mux(hit, way, plru_way)
next_state := logic.get_next_state(current_state, update_way)
when (valid) { state.write(set, next_state) }
}
def way = plru_way
}
class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy {
val logic = policy.toLowerCase match {
case "plru" => new PseudoLRU(n_ways)
case "lru" => new TrueLRU(n_ways)
case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t")
}
val state_vec =
if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line
else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W))))
def access(set: UInt, touch_way: UInt) = {
state_vec(set) := logic.get_next_state(state_vec(set), touch_way)
}
def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = {
require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways")
for (set <- 0 until n_sets) {
val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) =>
Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)}
when (set_touch_ways.map(_.valid).orR) {
state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways)
}
}
}
def way(set: UInt) = logic.get_replace_way(state_vec(set))
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) {
val plru = new PseudoLRU(n_ways)
// step
io.finished := RegNext(true.B, false.B)
val get_replace_ways = (0 until (1 << (n_ways-1))).map(state =>
plru.get_replace_way(state = state.U((n_ways-1).W)))
val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way =>
plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W))))
n_ways match {
case 2 => {
assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0))
assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1))
assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0))
assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1))
assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0))
assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1))
}
case 3 => {
assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0))
assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1))
assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2))
assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3))
assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0))
assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1))
assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2))
assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0))
assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1))
assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2))
assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0))
assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1))
assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2))
assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0))
assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1))
assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2))
}
case 4 => {
assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0))
assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1))
assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2))
assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3))
assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4))
assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5))
assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6))
assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7))
assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0))
assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1))
assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2))
assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3))
assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0))
assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1))
assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2))
assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3))
assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0))
assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1))
assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2))
assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3))
assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0))
assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1))
assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2))
assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3))
assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0))
assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1))
assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2))
assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3))
assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0))
assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1))
assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2))
assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3))
assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0))
assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1))
assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2))
assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3))
assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0))
assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1))
assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2))
assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3))
}
case 5 => {
assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0))
assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1))
assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2))
assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3))
assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4))
assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5))
assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6))
assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7))
assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8))
assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9))
assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10))
assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11))
assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12))
assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13))
assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14))
assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15))
assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0))
assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1))
assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2))
assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3))
assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4))
assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0))
assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1))
assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2))
assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3))
assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4))
assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0))
assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1))
assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2))
assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3))
assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4))
assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0))
assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1))
assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2))
assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3))
assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4))
assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0))
assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1))
assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2))
assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3))
assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4))
assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0))
assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1))
assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2))
assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3))
assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4))
assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0))
assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1))
assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2))
assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3))
assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4))
assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0))
assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1))
assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2))
assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3))
assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4))
assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0))
assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1))
assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2))
assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3))
assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4))
assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0))
assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1))
assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2))
assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3))
assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4))
assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0))
assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1))
assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2))
assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3))
assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4))
assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0))
assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1))
assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2))
assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3))
assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4))
assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0))
assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1))
assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2))
assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3))
assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4))
assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0))
assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1))
assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2))
assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3))
assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4))
assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0))
assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1))
assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2))
assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3))
assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4))
assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0))
assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1))
assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2))
assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3))
assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4))
}
case 6 => {
assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0))
assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1))
assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2))
assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3))
assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4))
assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5))
assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6))
assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7))
assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8))
assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9))
assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10))
assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11))
assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12))
assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13))
assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14))
assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15))
assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16))
assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17))
assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18))
assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19))
assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20))
assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21))
assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22))
assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23))
assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24))
assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25))
assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26))
assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27))
assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28))
assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29))
assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30))
assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31))
}
case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways")
}
}
File Consts.scala:
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket.constants
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
trait ScalarOpConstants {
val SZ_BR = 3
def BR_X = BitPat("b???")
def BR_EQ = 0.U(3.W)
def BR_NE = 1.U(3.W)
def BR_J = 2.U(3.W)
def BR_N = 3.U(3.W)
def BR_LT = 4.U(3.W)
def BR_GE = 5.U(3.W)
def BR_LTU = 6.U(3.W)
def BR_GEU = 7.U(3.W)
def A1_X = BitPat("b??")
def A1_ZERO = 0.U(2.W)
def A1_RS1 = 1.U(2.W)
def A1_PC = 2.U(2.W)
def A1_RS1SHL = 3.U(2.W)
def IMM_X = BitPat("b???")
def IMM_S = 0.U(3.W)
def IMM_SB = 1.U(3.W)
def IMM_U = 2.U(3.W)
def IMM_UJ = 3.U(3.W)
def IMM_I = 4.U(3.W)
def IMM_Z = 5.U(3.W)
def A2_X = BitPat("b???")
def A2_ZERO = 0.U(3.W)
def A2_SIZE = 1.U(3.W)
def A2_RS2 = 2.U(3.W)
def A2_IMM = 3.U(3.W)
def A2_RS2OH = 4.U(3.W)
def A2_IMMOH = 5.U(3.W)
def X = BitPat("b?")
def N = BitPat("b0")
def Y = BitPat("b1")
val SZ_DW = 1
def DW_X = X
def DW_32 = false.B
def DW_64 = true.B
def DW_XPR = DW_64
}
trait MemoryOpConstants {
val NUM_XA_OPS = 9
val M_SZ = 5
def M_X = BitPat("b?????");
def M_XRD = "b00000".U; // int load
def M_XWR = "b00001".U; // int store
def M_PFR = "b00010".U; // prefetch with intent to read
def M_PFW = "b00011".U; // prefetch with intent to write
def M_XA_SWAP = "b00100".U
def M_FLUSH_ALL = "b00101".U // flush all lines
def M_XLR = "b00110".U
def M_XSC = "b00111".U
def M_XA_ADD = "b01000".U
def M_XA_XOR = "b01001".U
def M_XA_OR = "b01010".U
def M_XA_AND = "b01011".U
def M_XA_MIN = "b01100".U
def M_XA_MAX = "b01101".U
def M_XA_MINU = "b01110".U
def M_XA_MAXU = "b01111".U
def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions
def M_PWR = "b10001".U // partial (masked) store
def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions
def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions
def M_SFENCE = "b10100".U // SFENCE.VMA
def M_HFENCEV = "b10101".U // HFENCE.VVMA
def M_HFENCEG = "b10110".U // HFENCE.GVMA
def M_WOK = "b10111".U // check write permissions but don't perform a write
def M_HLVX = "b10000".U // HLVX instruction
def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND)
def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU)
def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd)
def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW
def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd)
def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd)
def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
}
File TLB.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.devices.debug.DebugModuleKey
import freechips.rocketchip.diplomacy.RegionType
import freechips.rocketchip.subsystem.CacheBlockBytes
import freechips.rocketchip.tile.{CoreModule, CoreBundle}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.{OptimizationBarrier, SetAssocLRU, PseudoLRU, PopCountAtLeast, property}
import freechips.rocketchip.util.BooleanToAugmentedBoolean
import freechips.rocketchip.util.IntToAugmentedInt
import freechips.rocketchip.util.UIntToAugmentedUInt
import freechips.rocketchip.util.UIntIsOneOf
import freechips.rocketchip.util.SeqToAugmentedSeq
import freechips.rocketchip.util.SeqBoolBitwiseOps
case object ASIdBits extends Field[Int](0)
case object VMIdBits extends Field[Int](0)
/** =SFENCE=
* rs1 rs2
* {{{
* 0 0 -> flush All
* 0 1 -> flush by ASID
* 1 1 -> flush by ADDR
* 1 0 -> flush by ADDR and ASID
* }}}
* {{{
* If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces.
* If rs1=x0 and rs2!=x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see Section 4.3.1) are not ordered.
* If rs1!=x0 and rs2=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for all address spaces.
* If rs1!=x0 and rs2!=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered.
* }}}
*/
class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) {
val rs1 = Bool()
val rs2 = Bool()
val addr = UInt(vaddrBits.W)
val asid = UInt((asIdBits max 1).W) // TODO zero-width
val hv = Bool()
val hg = Bool()
}
class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) {
/** request address from CPU. */
val vaddr = UInt(vaddrBitsExtended.W)
/** don't lookup TLB, bypass vaddr as paddr */
val passthrough = Bool()
/** granularity */
val size = UInt(log2Ceil(lgMaxSize + 1).W)
/** memory command. */
val cmd = Bits(M_SZ.W)
val prv = UInt(PRV.SZ.W)
/** virtualization mode */
val v = Bool()
}
class TLBExceptions extends Bundle {
val ld = Bool()
val st = Bool()
val inst = Bool()
}
class TLBResp(lgMaxSize: Int = 3)(implicit p: Parameters) extends CoreBundle()(p) {
// lookup responses
val miss = Bool()
/** physical address */
val paddr = UInt(paddrBits.W)
val gpa = UInt(vaddrBitsExtended.W)
val gpa_is_pte = Bool()
/** page fault exception */
val pf = new TLBExceptions
/** guest page fault exception */
val gf = new TLBExceptions
/** access exception */
val ae = new TLBExceptions
/** misaligned access exception */
val ma = new TLBExceptions
/** if this address is cacheable */
val cacheable = Bool()
/** if caches must allocate this address */
val must_alloc = Bool()
/** if this address is prefetchable for caches*/
val prefetchable = Bool()
/** size/cmd of request that generated this response*/
val size = UInt(log2Ceil(lgMaxSize + 1).W)
val cmd = UInt(M_SZ.W)
}
class TLBEntryData(implicit p: Parameters) extends CoreBundle()(p) {
val ppn = UInt(ppnBits.W)
/** pte.u user */
val u = Bool()
/** pte.g global */
val g = Bool()
/** access exception.
* D$ -> PTW -> TLB AE
* Alignment failed.
*/
val ae_ptw = Bool()
val ae_final = Bool()
val ae_stage2 = Bool()
/** page fault */
val pf = Bool()
/** guest page fault */
val gf = Bool()
/** supervisor write */
val sw = Bool()
/** supervisor execute */
val sx = Bool()
/** supervisor read */
val sr = Bool()
/** hypervisor write */
val hw = Bool()
/** hypervisor excute */
val hx = Bool()
/** hypervisor read */
val hr = Bool()
/** prot_w */
val pw = Bool()
/** prot_x */
val px = Bool()
/** prot_r */
val pr = Bool()
/** PutPartial */
val ppp = Bool()
/** AMO logical */
val pal = Bool()
/** AMO arithmetic */
val paa = Bool()
/** get/put effects */
val eff = Bool()
/** cacheable */
val c = Bool()
/** fragmented_superpage support */
val fragmented_superpage = Bool()
}
/** basic cell for TLB data */
class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boolean)(implicit p: Parameters) extends CoreBundle()(p) {
require(nSectors == 1 || !superpage)
require(!superpageOnly || superpage)
val level = UInt(log2Ceil(pgLevels).W)
/** use vpn as tag */
val tag_vpn = UInt(vpnBits.W)
/** tag in vitualization mode */
val tag_v = Bool()
/** entry data */
val data = Vec(nSectors, UInt(new TLBEntryData().getWidth.W))
/** valid bit */
val valid = Vec(nSectors, Bool())
/** returns all entry data in this entry */
def entry_data = data.map(_.asTypeOf(new TLBEntryData))
/** returns the index of sector */
private def sectorIdx(vpn: UInt) = vpn.extract(nSectors.log2-1, 0)
/** returns the entry data matched with this vpn*/
def getData(vpn: UInt) = OptimizationBarrier(data(sectorIdx(vpn)).asTypeOf(new TLBEntryData))
/** returns whether a sector hits */
def sectorHit(vpn: UInt, virtual: Bool) = valid.orR && sectorTagMatch(vpn, virtual)
/** returns whether tag matches vpn */
def sectorTagMatch(vpn: UInt, virtual: Bool) = (((tag_vpn ^ vpn) >> nSectors.log2) === 0.U) && (tag_v === virtual)
/** returns hit signal */
def hit(vpn: UInt, virtual: Bool): Bool = {
if (superpage && usingVM) {
var tagMatch = valid.head && (tag_v === virtual)
for (j <- 0 until pgLevels) {
val base = (pgLevels - 1 - j) * pgLevelBits
val n = pgLevelBits + (if (j == 0) hypervisorExtraAddrBits else 0)
val ignore = level < j.U || (superpageOnly && j == pgLevels - 1).B
tagMatch = tagMatch && (ignore || (tag_vpn ^ vpn)(base + n - 1, base) === 0.U)
}
tagMatch
} else {
val idx = sectorIdx(vpn)
valid(idx) && sectorTagMatch(vpn, virtual)
}
}
/** returns the ppn of the input TLBEntryData */
def ppn(vpn: UInt, data: TLBEntryData) = {
val supervisorVPNBits = pgLevels * pgLevelBits
if (superpage && usingVM) {
var res = data.ppn >> pgLevelBits*(pgLevels - 1)
for (j <- 1 until pgLevels) {
val ignore = level < j.U || (superpageOnly && j == pgLevels - 1).B
res = Cat(res, (Mux(ignore, vpn, 0.U) | data.ppn)(supervisorVPNBits - j*pgLevelBits - 1, supervisorVPNBits - (j + 1)*pgLevelBits))
}
res
} else {
data.ppn
}
}
/** does the refill
*
* find the target entry with vpn tag
* and replace the target entry with the input entry data
*/
def insert(vpn: UInt, virtual: Bool, level: UInt, entry: TLBEntryData): Unit = {
this.tag_vpn := vpn
this.tag_v := virtual
this.level := level.extract(log2Ceil(pgLevels - superpageOnly.toInt)-1, 0)
val idx = sectorIdx(vpn)
valid(idx) := true.B
data(idx) := entry.asUInt
}
def invalidate(): Unit = { valid.foreach(_ := false.B) }
def invalidate(virtual: Bool): Unit = {
for ((v, e) <- valid zip entry_data)
when (tag_v === virtual) { v := false.B }
}
def invalidateVPN(vpn: UInt, virtual: Bool): Unit = {
if (superpage) {
when (hit(vpn, virtual)) { invalidate() }
} else {
when (sectorTagMatch(vpn, virtual)) {
for (((v, e), i) <- (valid zip entry_data).zipWithIndex)
when (tag_v === virtual && i.U === sectorIdx(vpn)) { v := false.B }
}
}
// For fragmented superpage mappings, we assume the worst (largest)
// case, and zap entries whose most-significant VPNs match
when (((tag_vpn ^ vpn) >> (pgLevelBits * (pgLevels - 1))) === 0.U) {
for ((v, e) <- valid zip entry_data)
when (tag_v === virtual && e.fragmented_superpage) { v := false.B }
}
}
def invalidateNonGlobal(virtual: Bool): Unit = {
for ((v, e) <- valid zip entry_data)
when (tag_v === virtual && !e.g) { v := false.B }
}
}
/** TLB config
*
* @param nSets the number of sets of PTE, follow [[ICacheParams.nSets]]
* @param nWays the total number of wayss of PTE, follow [[ICacheParams.nWays]]
* @param nSectors the number of ways in a single PTE TLBEntry
* @param nSuperpageEntries the number of SuperpageEntries
*/
case class TLBConfig(
nSets: Int,
nWays: Int,
nSectors: Int = 4,
nSuperpageEntries: Int = 4)
/** =Overview=
* [[TLB]] is a TLB template which contains PMA logic and PMP checker.
*
* TLB caches PTE and accelerates the address translation process.
* When tlb miss happens, ask PTW(L2TLB) for Page Table Walk.
* Perform PMP and PMA check during the translation and throw exception if there were any.
*
* ==Cache Structure==
* - Sectored Entry (PTE)
* - set-associative or direct-mapped
* - nsets = [[TLBConfig.nSets]]
* - nways = [[TLBConfig.nWays]] / [[TLBConfig.nSectors]]
* - PTEEntry( sectors = [[TLBConfig.nSectors]] )
* - LRU(if set-associative)
*
* - Superpage Entry(superpage PTE)
* - fully associative
* - nsets = [[TLBConfig.nSuperpageEntries]]
* - PTEEntry(sectors = 1)
* - PseudoLRU
*
* - Special Entry(PTE across PMP)
* - nsets = 1
* - PTEEntry(sectors = 1)
*
* ==Address structure==
* {{{
* |vaddr |
* |ppn/vpn | pgIndex |
* | | |
* | |nSets |nSector | |}}}
*
* ==State Machine==
* {{{
* s_ready: ready to accept request from CPU.
* s_request: when L1TLB(this) miss, send request to PTW(L2TLB), .
* s_wait: wait for PTW to refill L1TLB.
* s_wait_invalidate: L1TLB is waiting for respond from PTW, but L1TLB will invalidate respond from PTW.}}}
*
* ==PMP==
* pmp check
* - special_entry: always check
* - other entry: check on refill
*
* ==Note==
* PMA consume diplomacy parameter generate physical memory address checking logic
*
* Boom use Rocket ITLB, and its own DTLB.
*
* Accelerators:{{{
* sha3: DTLB
* gemmini: DTLB
* hwacha: DTLB*2+ITLB}}}
* @param instruction true for ITLB, false for DTLB
* @param lgMaxSize @todo seems granularity
* @param cfg [[TLBConfig]]
* @param edge collect SoC metadata.
*/
class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
override def desiredName = if (instruction) "ITLB" else "DTLB"
val io = IO(new Bundle {
/** request from Core */
val req = Flipped(Decoupled(new TLBReq(lgMaxSize)))
/** response to Core */
val resp = Output(new TLBResp(lgMaxSize))
/** SFence Input */
val sfence = Flipped(Valid(new SFenceReq))
/** IO to PTW */
val ptw = new TLBPTWIO
/** suppress a TLB refill, one cycle after a miss */
val kill = Input(Bool())
})
io.ptw.customCSRs := DontCare
val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits)
val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits)
/** index for sectored_Entry */
val memIdx = vpn.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2)
/** TLB Entry */
val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nWays / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false))))
/** Superpage Entry */
val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new TLBEntry(1, true, true)))
/** Special Entry
*
* If PMP granularity is less than page size, thus need additional "special" entry manage PMP.
*/
val special_entry = (!pageGranularityPMPs).option(Reg(new TLBEntry(1, true, false)))
def ordinary_entries = sectored_entries(memIdx) ++ superpage_entries
def all_entries = ordinary_entries ++ special_entry
def all_real_entries = sectored_entries.flatten ++ superpage_entries ++ special_entry
val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4)
val state = RegInit(s_ready)
// use vpn as refill_tag
val r_refill_tag = Reg(UInt(vpnBits.W))
val r_superpage_repl_addr = Reg(UInt(log2Ceil(superpage_entries.size).W))
val r_sectored_repl_addr = Reg(UInt(log2Ceil(sectored_entries.head.size).W))
val r_sectored_hit = Reg(Valid(UInt(log2Ceil(sectored_entries.head.size).W)))
val r_superpage_hit = Reg(Valid(UInt(log2Ceil(superpage_entries.size).W)))
val r_vstage1_en = Reg(Bool())
val r_stage2_en = Reg(Bool())
val r_need_gpa = Reg(Bool())
val r_gpa_valid = Reg(Bool())
val r_gpa = Reg(UInt(vaddrBits.W))
val r_gpa_vpn = Reg(UInt(vpnBits.W))
val r_gpa_is_pte = Reg(Bool())
/** privilege mode */
val priv = io.req.bits.prv
val priv_v = usingHypervisor.B && io.req.bits.v
val priv_s = priv(0)
// user mode and supervisor mode
val priv_uses_vm = priv <= PRV.S.U
val satp = Mux(priv_v, io.ptw.vsatp, io.ptw.ptbr)
val stage1_en = usingVM.B && satp.mode(satp.mode.getWidth-1)
/** VS-stage translation enable */
val vstage1_en = usingHypervisor.B && priv_v && io.ptw.vsatp.mode(io.ptw.vsatp.mode.getWidth-1)
/** G-stage translation enable */
val stage2_en = usingHypervisor.B && priv_v && io.ptw.hgatp.mode(io.ptw.hgatp.mode.getWidth-1)
/** Enable Virtual Memory when:
* 1. statically configured
* 1. satp highest bits enabled
* i. RV32:
* - 0 -> Bare
* - 1 -> SV32
* i. RV64:
* - 0000 -> Bare
* - 1000 -> SV39
* - 1001 -> SV48
* - 1010 -> SV57
* - 1011 -> SV64
* 1. In virtualization mode, vsatp highest bits enabled
* 1. priv mode in U and S.
* 1. in H & M mode, disable VM.
* 1. no passthrough(micro-arch defined.)
*
* @see RV-priv spec 4.1.11 Supervisor Address Translation and Protection (satp) Register
* @see RV-priv spec 8.2.18 Virtual Supervisor Address Translation and Protection Register (vsatp)
*/
val vm_enabled = (stage1_en || stage2_en) && priv_uses_vm && !io.req.bits.passthrough
// flush guest entries on vsatp.MODE Bare <-> SvXX transitions
val v_entries_use_stage1 = RegInit(false.B)
val vsatp_mode_mismatch = priv_v && (vstage1_en =/= v_entries_use_stage1) && !io.req.bits.passthrough
// share a single physical memory attribute checker (unshare if critical path)
val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0)
/** refill signal */
val do_refill = usingVM.B && io.ptw.resp.valid
/** sfence invalidate refill */
val invalidate_refill = state.isOneOf(s_request /* don't care */, s_wait_invalidate) || io.sfence.valid
// PMP
val mpu_ppn = Mux(do_refill, refill_ppn,
Mux(vm_enabled && special_entry.nonEmpty.B, special_entry.map(e => e.ppn(vpn, e.getData(vpn))).getOrElse(0.U), io.req.bits.vaddr >> pgIdxBits))
val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0))
val mpu_priv = Mux[UInt](usingVM.B && (do_refill || io.req.bits.passthrough /* PTW */), PRV.S.U, Cat(io.ptw.status.debug, priv))
val pmp = Module(new PMPChecker(lgMaxSize))
pmp.io.addr := mpu_physaddr
pmp.io.size := io.req.bits.size
pmp.io.pmp := (io.ptw.pmp: Seq[PMP])
pmp.io.prv := mpu_priv
val pma = Module(new PMAChecker(edge.manager)(p))
pma.io.paddr := mpu_physaddr
// todo: using DataScratchpad doesn't support cacheable.
val cacheable = pma.io.resp.cacheable && (instruction || !usingDataScratchpad).B
val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits, 1 << lgMaxSize)(mpu_physaddr).homogeneous
// In M mode, if access DM address(debug module program buffer)
val deny_access_to_debug = mpu_priv <= PRV.M.U && p(DebugModuleKey).map(dmp => dmp.address.contains(mpu_physaddr)).getOrElse(false.B)
val prot_r = pma.io.resp.r && !deny_access_to_debug && pmp.io.r
val prot_w = pma.io.resp.w && !deny_access_to_debug && pmp.io.w
val prot_pp = pma.io.resp.pp
val prot_al = pma.io.resp.al
val prot_aa = pma.io.resp.aa
val prot_x = pma.io.resp.x && !deny_access_to_debug && pmp.io.x
val prot_eff = pma.io.resp.eff
// hit check
val sector_hits = sectored_entries(memIdx).map(_.sectorHit(vpn, priv_v))
val superpage_hits = superpage_entries.map(_.hit(vpn, priv_v))
val hitsVec = all_entries.map(vm_enabled && _.hit(vpn, priv_v))
val real_hits = hitsVec.asUInt
val hits = Cat(!vm_enabled, real_hits)
// use ptw response to refill
// permission bit arrays
when (do_refill) {
val pte = io.ptw.resp.bits.pte
val refill_v = r_vstage1_en || r_stage2_en
val newEntry = Wire(new TLBEntryData)
newEntry.ppn := pte.ppn
newEntry.c := cacheable
newEntry.u := pte.u
newEntry.g := pte.g && pte.v
newEntry.ae_ptw := io.ptw.resp.bits.ae_ptw
newEntry.ae_final := io.ptw.resp.bits.ae_final
newEntry.ae_stage2 := io.ptw.resp.bits.ae_final && io.ptw.resp.bits.gpa_is_pte && r_stage2_en
newEntry.pf := io.ptw.resp.bits.pf
newEntry.gf := io.ptw.resp.bits.gf
newEntry.hr := io.ptw.resp.bits.hr
newEntry.hw := io.ptw.resp.bits.hw
newEntry.hx := io.ptw.resp.bits.hx
newEntry.sr := pte.sr()
newEntry.sw := pte.sw()
newEntry.sx := pte.sx()
newEntry.pr := prot_r
newEntry.pw := prot_w
newEntry.px := prot_x
newEntry.ppp := prot_pp
newEntry.pal := prot_al
newEntry.paa := prot_aa
newEntry.eff := prot_eff
newEntry.fragmented_superpage := io.ptw.resp.bits.fragmented_superpage
// refill special_entry
when (special_entry.nonEmpty.B && !io.ptw.resp.bits.homogeneous) {
special_entry.foreach(_.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry))
}.elsewhen (io.ptw.resp.bits.level < (pgLevels-1).U) {
val waddr = Mux(r_superpage_hit.valid && usingHypervisor.B, r_superpage_hit.bits, r_superpage_repl_addr)
for ((e, i) <- superpage_entries.zipWithIndex) when (r_superpage_repl_addr === i.U) {
e.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry)
when (invalidate_refill) { e.invalidate() }
}
// refill sectored_hit
}.otherwise {
val r_memIdx = r_refill_tag.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2)
val waddr = Mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr)
for ((e, i) <- sectored_entries(r_memIdx).zipWithIndex) when (waddr === i.U) {
when (!r_sectored_hit.valid) { e.invalidate() }
e.insert(r_refill_tag, refill_v, 0.U, newEntry)
when (invalidate_refill) { e.invalidate() }
}
}
r_gpa_valid := io.ptw.resp.bits.gpa.valid
r_gpa := io.ptw.resp.bits.gpa.bits
r_gpa_is_pte := io.ptw.resp.bits.gpa_is_pte
}
// get all entries data.
val entries = all_entries.map(_.getData(vpn))
val normal_entries = entries.take(ordinary_entries.size)
// parallel query PPN from [[all_entries]], if VM not enabled return VPN instead
val ppn = Mux1H(hitsVec :+ !vm_enabled, (all_entries zip entries).map{ case (entry, data) => entry.ppn(vpn, data) } :+ vpn(ppnBits-1, 0))
val nPhysicalEntries = 1 + special_entry.size
// generally PTW misaligned load exception.
val ptw_ae_array = Cat(false.B, entries.map(_.ae_ptw).asUInt)
val final_ae_array = Cat(false.B, entries.map(_.ae_final).asUInt)
val ptw_pf_array = Cat(false.B, entries.map(_.pf).asUInt)
val ptw_gf_array = Cat(false.B, entries.map(_.gf).asUInt)
val sum = Mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum)
// if in hypervisor/machine mode, cannot read/write user entries.
// if in superviosr/user mode, "If the SUM bit in the sstatus register is set, supervisor mode software may also access pages with U=1.(from spec)"
val priv_rw_ok = Mux(!priv_s || sum, entries.map(_.u).asUInt, 0.U) | Mux(priv_s, ~entries.map(_.u).asUInt, 0.U)
// if in hypervisor/machine mode, other than user pages, all pages are executable.
// if in superviosr/user mode, only user page can execute.
val priv_x_ok = Mux(priv_s, ~entries.map(_.u).asUInt, entries.map(_.u).asUInt)
val stage1_bypass = Fill(entries.size, usingHypervisor.B) & (Fill(entries.size, !stage1_en) | entries.map(_.ae_stage2).asUInt)
val mxr = io.ptw.status.mxr | Mux(priv_v, io.ptw.gstatus.mxr, false.B)
// "The vsstatus field MXR, which makes execute-only pages readable, only overrides VS-stage page protection.(from spec)"
val r_array = Cat(true.B, (priv_rw_ok & (entries.map(_.sr).asUInt | Mux(mxr, entries.map(_.sx).asUInt, 0.U))) | stage1_bypass)
val w_array = Cat(true.B, (priv_rw_ok & entries.map(_.sw).asUInt) | stage1_bypass)
val x_array = Cat(true.B, (priv_x_ok & entries.map(_.sx).asUInt) | stage1_bypass)
val stage2_bypass = Fill(entries.size, !stage2_en)
val hr_array = Cat(true.B, entries.map(_.hr).asUInt | Mux(io.ptw.status.mxr, entries.map(_.hx).asUInt, 0.U) | stage2_bypass)
val hw_array = Cat(true.B, entries.map(_.hw).asUInt | stage2_bypass)
val hx_array = Cat(true.B, entries.map(_.hx).asUInt | stage2_bypass)
// These array is for each TLB entries.
// user mode can read: PMA OK, TLB OK, AE OK
val pr_array = Cat(Fill(nPhysicalEntries, prot_r), normal_entries.map(_.pr).asUInt) & ~(ptw_ae_array | final_ae_array)
// user mode can write: PMA OK, TLB OK, AE OK
val pw_array = Cat(Fill(nPhysicalEntries, prot_w), normal_entries.map(_.pw).asUInt) & ~(ptw_ae_array | final_ae_array)
// user mode can write: PMA OK, TLB OK, AE OK
val px_array = Cat(Fill(nPhysicalEntries, prot_x), normal_entries.map(_.px).asUInt) & ~(ptw_ae_array | final_ae_array)
// put effect
val eff_array = Cat(Fill(nPhysicalEntries, prot_eff), normal_entries.map(_.eff).asUInt)
// cacheable
val c_array = Cat(Fill(nPhysicalEntries, cacheable), normal_entries.map(_.c).asUInt)
// put partial
val ppp_array = Cat(Fill(nPhysicalEntries, prot_pp), normal_entries.map(_.ppp).asUInt)
// atomic arithmetic
val paa_array = Cat(Fill(nPhysicalEntries, prot_aa), normal_entries.map(_.paa).asUInt)
// atomic logic
val pal_array = Cat(Fill(nPhysicalEntries, prot_al), normal_entries.map(_.pal).asUInt)
val ppp_array_if_cached = ppp_array | c_array
val paa_array_if_cached = paa_array | (if(usingAtomicsInCache) c_array else 0.U)
val pal_array_if_cached = pal_array | (if(usingAtomicsInCache) c_array else 0.U)
val prefetchable_array = Cat((cacheable && homogeneous) << (nPhysicalEntries-1), normal_entries.map(_.c).asUInt)
// vaddr misaligned: vaddr[1:0]=b00
val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1.U)).orR
def badVA(guestPA: Boolean): Bool = {
val additionalPgLevels = (if (guestPA) io.ptw.hgatp else satp).additionalPgLevels
val extraBits = if (guestPA) hypervisorExtraAddrBits else 0
val signed = !guestPA
val nPgLevelChoices = pgLevels - minPgLevels + 1
val minVAddrBits = pgIdxBits + minPgLevels * pgLevelBits + extraBits
(for (i <- 0 until nPgLevelChoices) yield {
val mask = ((BigInt(1) << vaddrBitsExtended) - (BigInt(1) << (minVAddrBits + i * pgLevelBits - signed.toInt))).U
val maskedVAddr = io.req.bits.vaddr & mask
additionalPgLevels === i.U && !(maskedVAddr === 0.U || signed.B && maskedVAddr === mask)
}).orR
}
val bad_gpa =
if (!usingHypervisor) false.B
else vm_enabled && !stage1_en && badVA(true)
val bad_va =
if (!usingVM || (minPgLevels == pgLevels && vaddrBits == vaddrBitsExtended)) false.B
else vm_enabled && stage1_en && badVA(false)
val cmd_lrsc = usingAtomics.B && io.req.bits.cmd.isOneOf(M_XLR, M_XSC)
val cmd_amo_logical = usingAtomics.B && isAMOLogical(io.req.bits.cmd)
val cmd_amo_arithmetic = usingAtomics.B && isAMOArithmetic(io.req.bits.cmd)
val cmd_put_partial = io.req.bits.cmd === M_PWR
val cmd_read = isRead(io.req.bits.cmd)
val cmd_readx = usingHypervisor.B && io.req.bits.cmd === M_HLVX
val cmd_write = isWrite(io.req.bits.cmd)
val cmd_write_perms = cmd_write ||
io.req.bits.cmd.isOneOf(M_FLUSH_ALL, M_WOK) // not a write, but needs write permissions
val lrscAllowed = Mux((usingDataScratchpad || usingAtomicsOnlyForIO).B, 0.U, c_array)
val ae_array =
Mux(misaligned, eff_array, 0.U) |
Mux(cmd_lrsc, ~lrscAllowed, 0.U)
// access exception needs SoC information from PMA
val ae_ld_array = Mux(cmd_read, ae_array | ~pr_array, 0.U)
val ae_st_array =
Mux(cmd_write_perms, ae_array | ~pw_array, 0.U) |
Mux(cmd_put_partial, ~ppp_array_if_cached, 0.U) |
Mux(cmd_amo_logical, ~pal_array_if_cached, 0.U) |
Mux(cmd_amo_arithmetic, ~paa_array_if_cached, 0.U)
val must_alloc_array =
Mux(cmd_put_partial, ~ppp_array, 0.U) |
Mux(cmd_amo_logical, ~pal_array, 0.U) |
Mux(cmd_amo_arithmetic, ~paa_array, 0.U) |
Mux(cmd_lrsc, ~0.U(pal_array.getWidth.W), 0.U)
val pf_ld_array = Mux(cmd_read, ((~Mux(cmd_readx, x_array, r_array) & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array, 0.U)
val pf_st_array = Mux(cmd_write_perms, ((~w_array & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array, 0.U)
val pf_inst_array = ((~x_array & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array
val gf_ld_array = Mux(priv_v && cmd_read, (~Mux(cmd_readx, hx_array, hr_array) | ptw_gf_array) & ~ptw_ae_array, 0.U)
val gf_st_array = Mux(priv_v && cmd_write_perms, (~hw_array | ptw_gf_array) & ~ptw_ae_array, 0.U)
val gf_inst_array = Mux(priv_v, (~hx_array | ptw_gf_array) & ~ptw_ae_array, 0.U)
val gpa_hits = {
val need_gpa_mask = if (instruction) gf_inst_array else gf_ld_array | gf_st_array
val hit_mask = Fill(ordinary_entries.size, r_gpa_valid && r_gpa_vpn === vpn) | Fill(all_entries.size, !vstage1_en)
hit_mask | ~need_gpa_mask(all_entries.size-1, 0)
}
val tlb_hit_if_not_gpa_miss = real_hits.orR
val tlb_hit = (real_hits & gpa_hits).orR
// leads to s_request
val tlb_miss = vm_enabled && !vsatp_mode_mismatch && !bad_va && !tlb_hit
val sectored_plru = new SetAssocLRU(cfg.nSets, sectored_entries.head.size, "plru")
val superpage_plru = new PseudoLRU(superpage_entries.size)
when (io.req.valid && vm_enabled) {
// replace
when (sector_hits.orR) { sectored_plru.access(memIdx, OHToUInt(sector_hits)) }
when (superpage_hits.orR) { superpage_plru.access(OHToUInt(superpage_hits)) }
}
// Superpages create the possibility that two entries in the TLB may match.
// This corresponds to a software bug, but we can't return complete garbage;
// we must return either the old translation or the new translation. This
// isn't compatible with the Mux1H approach. So, flush the TLB and report
// a miss on duplicate entries.
val multipleHits = PopCountAtLeast(real_hits, 2)
// only pull up req.ready when this is s_ready state.
io.req.ready := state === s_ready
// page fault
io.resp.pf.ld := (bad_va && cmd_read) || (pf_ld_array & hits).orR
io.resp.pf.st := (bad_va && cmd_write_perms) || (pf_st_array & hits).orR
io.resp.pf.inst := bad_va || (pf_inst_array & hits).orR
// guest page fault
io.resp.gf.ld := (bad_gpa && cmd_read) || (gf_ld_array & hits).orR
io.resp.gf.st := (bad_gpa && cmd_write_perms) || (gf_st_array & hits).orR
io.resp.gf.inst := bad_gpa || (gf_inst_array & hits).orR
// access exception
io.resp.ae.ld := (ae_ld_array & hits).orR
io.resp.ae.st := (ae_st_array & hits).orR
io.resp.ae.inst := (~px_array & hits).orR
// misaligned
io.resp.ma.ld := misaligned && cmd_read
io.resp.ma.st := misaligned && cmd_write
io.resp.ma.inst := false.B // this is up to the pipeline to figure out
io.resp.cacheable := (c_array & hits).orR
io.resp.must_alloc := (must_alloc_array & hits).orR
io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB || m.supportsHint).B
io.resp.miss := do_refill || vsatp_mode_mismatch || tlb_miss || multipleHits
io.resp.paddr := Cat(ppn, io.req.bits.vaddr(pgIdxBits-1, 0))
io.resp.size := io.req.bits.size
io.resp.cmd := io.req.bits.cmd
io.resp.gpa_is_pte := vstage1_en && r_gpa_is_pte
io.resp.gpa := {
val page = Mux(!vstage1_en, Cat(bad_gpa, vpn), r_gpa >> pgIdxBits)
val offset = Mux(io.resp.gpa_is_pte, r_gpa(pgIdxBits-1, 0), io.req.bits.vaddr(pgIdxBits-1, 0))
Cat(page, offset)
}
io.ptw.req.valid := state === s_request
io.ptw.req.bits.valid := !io.kill
io.ptw.req.bits.bits.addr := r_refill_tag
io.ptw.req.bits.bits.vstage1 := r_vstage1_en
io.ptw.req.bits.bits.stage2 := r_stage2_en
io.ptw.req.bits.bits.need_gpa := r_need_gpa
if (usingVM) {
when(io.ptw.req.fire && io.ptw.req.bits.valid) {
r_gpa_valid := false.B
r_gpa_vpn := r_refill_tag
}
val sfence = io.sfence.valid
// this is [[s_ready]]
// handle miss/hit at the first cycle.
// if miss, request PTW(L2TLB).
when (io.req.fire && tlb_miss) {
state := s_request
r_refill_tag := vpn
r_need_gpa := tlb_hit_if_not_gpa_miss
r_vstage1_en := vstage1_en
r_stage2_en := stage2_en
r_superpage_repl_addr := replacementEntry(superpage_entries, superpage_plru.way)
r_sectored_repl_addr := replacementEntry(sectored_entries(memIdx), sectored_plru.way(memIdx))
r_sectored_hit.valid := sector_hits.orR
r_sectored_hit.bits := OHToUInt(sector_hits)
r_superpage_hit.valid := superpage_hits.orR
r_superpage_hit.bits := OHToUInt(superpage_hits)
}
// Handle SFENCE.VMA when send request to PTW.
// SFENCE.VMA io.ptw.req.ready kill
// ? ? 1
// 0 0 0
// 0 1 0 -> s_wait
// 1 0 0 -> s_wait_invalidate
// 1 0 0 -> s_ready
when (state === s_request) {
// SFENCE.VMA will kill TLB entries based on rs1 and rs2. It will take 1 cycle.
when (sfence) { state := s_ready }
// here should be io.ptw.req.fire, but assert(io.ptw.req.ready === true.B)
// fire -> s_wait
when (io.ptw.req.ready) { state := Mux(sfence, s_wait_invalidate, s_wait) }
// If CPU kills request(frontend.s2_redirect)
when (io.kill) { state := s_ready }
}
// sfence in refill will results in invalidate
when (state === s_wait && sfence) {
state := s_wait_invalidate
}
// after CPU acquire response, go back to s_ready.
when (io.ptw.resp.valid) {
state := s_ready
}
// SFENCE processing logic.
when (sfence) {
assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn)
for (e <- all_real_entries) {
val hv = usingHypervisor.B && io.sfence.bits.hv
val hg = usingHypervisor.B && io.sfence.bits.hg
when (!hg && io.sfence.bits.rs1) { e.invalidateVPN(vpn, hv) }
.elsewhen (!hg && io.sfence.bits.rs2) { e.invalidateNonGlobal(hv) }
.otherwise { e.invalidate(hv || hg) }
}
}
when(io.req.fire && vsatp_mode_mismatch) {
all_real_entries.foreach(_.invalidate(true.B))
v_entries_use_stage1 := vstage1_en
}
when (multipleHits || reset.asBool) {
all_real_entries.foreach(_.invalidate())
}
ccover(io.ptw.req.fire, "MISS", "TLB miss")
ccover(io.ptw.req.valid && !io.ptw.req.ready, "PTW_STALL", "TLB miss, but PTW busy")
ccover(state === s_wait_invalidate, "SFENCE_DURING_REFILL", "flush TLB during TLB refill")
ccover(sfence && !io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_ALL", "flush TLB")
ccover(sfence && !io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_ASID", "flush TLB ASID")
ccover(sfence && io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_LINE", "flush TLB line")
ccover(sfence && io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_LINE_ASID", "flush TLB line/ASID")
ccover(multipleHits, "MULTIPLE_HITS", "Two matching translations in TLB")
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"${if (instruction) "I" else "D"}TLB_$label", "MemorySystem;;" + desc)
/** Decides which entry to be replaced
*
* If there is a invalid entry, replace it with priorityencoder;
* if not, replace the alt entry
*
* @return mask for TLBEntry replacement
*/
def replacementEntry(set: Seq[TLBEntry], alt: UInt) = {
val valids = set.map(_.valid.orR).asUInt
Mux(valids.andR, alt, PriorityEncoder(~valids))
}
}
File TLBPermissions.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder}
import freechips.rocketchip.tilelink.TLManagerParameters
case class TLBPermissions(
homogeneous: Bool, // if false, the below are undefined
r: Bool, // readable
w: Bool, // writeable
x: Bool, // executable
c: Bool, // cacheable
a: Bool, // arithmetic ops
l: Bool) // logical ops
object TLBPageLookup
{
private case class TLBFixedPermissions(
e: Boolean, // get-/put-effects
r: Boolean, // readable
w: Boolean, // writeable
x: Boolean, // executable
c: Boolean, // cacheable
a: Boolean, // arithmetic ops
l: Boolean) { // logical ops
val useful = r || w || x || c || a || l
}
private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = {
val permissions = managers.map { m =>
(m.address, TLBFixedPermissions(
e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType,
r = m.supportsGet || m.supportsAcquireB, // if cached, never uses Get
w = m.supportsPutFull || m.supportsAcquireT, // if cached, never uses Put
x = m.executable,
c = m.supportsAcquireB,
a = m.supportsArithmetic,
l = m.supportsLogical))
}
permissions
.filter(_._2.useful) // get rid of no-permission devices
.groupBy(_._2) // group by permission type
.mapValues(seq =>
AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions
.toMap
}
// Unmapped memory is considered to be inhomogeneous
def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = {
require (isPow2(xLen) && xLen >= 8)
require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8)
require (isPow2(pageSize) && pageSize >= cacheBlockBytes)
val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes)
val allSizes = TransferSizes(1, maxRequestBytes)
val amoSizes = TransferSizes(4, xLen/8)
val permissions = managers.foreach { m =>
require (!m.supportsGet || m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}")
require (!m.supportsPutFull || m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}")
require (!m.supportsPutPartial || m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}")
require (!m.supportsAcquireB || m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}")
require (!m.supportsAcquireT || m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}")
require (!m.supportsLogical || m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}")
require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}")
require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)")
}
val grouped = groupRegions(managers)
.mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough
def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = {
val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) }
val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList)
// Find the minimal bits needed to distinguish between yes and no
val decisionMask = AddressDecoder(Seq(yes, no))
def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct)
val (yesf, nof) = (simplify(yes), simplify(no))
if (yesf.size < no.size) {
(x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ || _)
} else {
(x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ || _)
}
}
// Derive simplified property circuits (don't care when !homo)
val rfn = lowCostProperty(_.r)
val wfn = lowCostProperty(_.w)
val xfn = lowCostProperty(_.x)
val cfn = lowCostProperty(_.c)
val afn = lowCostProperty(_.a)
val lfn = lowCostProperty(_.l)
val homo = AddressSet.unify(grouped.values.flatten.toList)
(x: UInt) => TLBPermissions(
homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ || _),
r = rfn(x),
w = wfn(x),
x = xfn(x),
c = cfn(x),
a = afn(x),
l = lfn(x))
}
// Are all pageSize intervals of mapped regions homogeneous?
def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = {
groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize))
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File PTW.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch}
import chisel3.withClock
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.subsystem.CacheBlockBytes
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
import scala.collection.mutable.ListBuffer
/** PTE request from TLB to PTW
*
* TLB send a PTE request to PTW when L1TLB miss
*/
class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
val addr = UInt(vpnBits.W)
val need_gpa = Bool()
val vstage1 = Bool()
val stage2 = Bool()
}
/** PTE info from L2TLB to TLB
*
* containing: target PTE, exceptions, two-satge tanslation info
*/
class PTWResp(implicit p: Parameters) extends CoreBundle()(p) {
/** ptw access exception */
val ae_ptw = Bool()
/** final access exception */
val ae_final = Bool()
/** page fault */
val pf = Bool()
/** guest page fault */
val gf = Bool()
/** hypervisor read */
val hr = Bool()
/** hypervisor write */
val hw = Bool()
/** hypervisor execute */
val hx = Bool()
/** PTE to refill L1TLB
*
* source: L2TLB
*/
val pte = new PTE
/** pte pglevel */
val level = UInt(log2Ceil(pgLevels).W)
/** fragmented_superpage support */
val fragmented_superpage = Bool()
/** homogeneous for both pma and pmp */
val homogeneous = Bool()
val gpa = Valid(UInt(vaddrBits.W))
val gpa_is_pte = Bool()
}
/** IO between TLB and PTW
*
* PTW receives :
* - PTE request
* - CSRs info
* - pmp results from PMP(in TLB)
*/
class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
val req = Decoupled(Valid(new PTWReq))
val resp = Flipped(Valid(new PTWResp))
val ptbr = Input(new PTBR())
val hgatp = Input(new PTBR())
val vsatp = Input(new PTBR())
val status = Input(new MStatus())
val hstatus = Input(new HStatus())
val gstatus = Input(new MStatus())
val pmp = Input(Vec(nPMPs, new PMP))
val customCSRs = Flipped(coreParams.customCSRs)
}
/** PTW performance statistics */
class PTWPerfEvents extends Bundle {
val l2miss = Bool()
val l2hit = Bool()
val pte_miss = Bool()
val pte_hit = Bool()
}
/** Datapath IO between PTW and Core
*
* PTW receives CSRs info, pmp checks, sfence instruction info
*
* PTW sends its performance statistics to core
*/
class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
val ptbr = Input(new PTBR())
val hgatp = Input(new PTBR())
val vsatp = Input(new PTBR())
val sfence = Flipped(Valid(new SFenceReq))
val status = Input(new MStatus())
val hstatus = Input(new HStatus())
val gstatus = Input(new MStatus())
val pmp = Input(Vec(nPMPs, new PMP))
val perf = Output(new PTWPerfEvents())
val customCSRs = Flipped(coreParams.customCSRs)
/** enable clock generated by ptw */
val clock_enabled = Output(Bool())
}
/** PTE template for transmission
*
* contains useful methods to check PTE attributes
* @see RV-priv spec 4.3.1 for pgae table entry format
*/
class PTE(implicit p: Parameters) extends CoreBundle()(p) {
val reserved_for_future = UInt(10.W)
val ppn = UInt(44.W)
val reserved_for_software = Bits(2.W)
/** dirty bit */
val d = Bool()
/** access bit */
val a = Bool()
/** global mapping */
val g = Bool()
/** user mode accessible */
val u = Bool()
/** whether the page is executable */
val x = Bool()
/** whether the page is writable */
val w = Bool()
/** whether the page is readable */
val r = Bool()
/** valid bit */
val v = Bool()
/** return true if find a pointer to next level page table */
def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U
/** return true if find a leaf PTE */
def leaf(dummy: Int = 0) = v && (r || (x && !w)) && a
/** user read */
def ur(dummy: Int = 0) = sr() && u
/** user write*/
def uw(dummy: Int = 0) = sw() && u
/** user execute */
def ux(dummy: Int = 0) = sx() && u
/** supervisor read */
def sr(dummy: Int = 0) = leaf() && r
/** supervisor write */
def sw(dummy: Int = 0) = leaf() && w && d
/** supervisor execute */
def sx(dummy: Int = 0) = leaf() && x
/** full permission: writable and executable in user mode */
def isFullPerm(dummy: Int = 0) = uw() && ux()
}
/** L2TLB PTE template
*
* contains tag bits
* @param nSets number of sets in L2TLB
* @see RV-priv spec 4.3.1 for page table entry format
*/
class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
val idxBits = log2Ceil(nSets)
val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0)
val tag = UInt(tagBits.W)
val ppn = UInt(ppnBits.W)
/** dirty bit */
val d = Bool()
/** access bit */
val a = Bool()
/** user mode accessible */
val u = Bool()
/** whether the page is executable */
val x = Bool()
/** whether the page is writable */
val w = Bool()
/** whether the page is readable */
val r = Bool()
}
/** PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC)
*
* It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb.
* Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process.
*
* ==Structure==
* - l2tlb : for leaf PTEs
* - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]]))
* - PLRU
* - pte_cache: for non-leaf PTEs
* - set-associative
* - LRU
* - s2_pte_cache: for non-leaf PTEs in 2-stage translation
* - set-associative
* - PLRU
*
* l2tlb Pipeline: 3 stage
* {{{
* stage 0 : read
* stage 1 : decode
* stage 2 : hit check
* }}}
* ==State Machine==
* s_ready: ready to reveive request from TLB
* s_req: request mem; pte_cache hit judge
* s_wait1: deal with l2tlb error
* s_wait2: final hit judge
* s_wait3: receive mem response
* s_fragment_superpage: for superpage PTE
*
* @note l2tlb hit happens in s_req or s_wait1
* @see RV-priv spec 4.3-4.6 for Virtual-Memory System
* @see RV-priv spec 8.5 for Two-Stage Address Translation
* @todo details in two-stage translation
*/
class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
val io = IO(new Bundle {
/** to n TLB */
val requestor = Flipped(Vec(n, new TLBPTWIO))
/** to HellaCache */
val mem = new HellaCacheIO
/** to Core
*
* contains CSRs info and performance statistics
*/
val dpath = new DatapathPTWIO
})
val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8)
val state = RegInit(s_ready)
val l2_refill_wire = Wire(Bool())
/** Arbiter to arbite request from n TLB */
val arb = Module(new Arbiter(Valid(new PTWReq), n))
// use TLB req as arbitor's input
arb.io.in <> io.requestor.map(_.req)
// receive req only when s_ready and not in refill
arb.io.out.ready := (state === s_ready) && !l2_refill_wire
val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B)))
val clock_en = state =/= s_ready || l2_refill_wire || arb.io.out.valid || io.dpath.sfence.valid || io.dpath.customCSRs.disableDCacheClockGate
io.dpath.clock_enabled := usingVM.B && clock_en
val gated_clock =
if (!usingVM || !tileParams.dcache.get.clockGate) clock
else ClockGate(clock, clock_en, "ptw_clock_gate")
withClock (gated_clock) { // entering gated-clock domain
val invalidated = Reg(Bool())
/** current PTE level
* {{{
* 0 <= count <= pgLevel-1
* count = pgLevel - 1 : leaf PTE
* count < pgLevel - 1 : non-leaf PTE
* }}}
*/
val count = Reg(UInt(log2Ceil(pgLevels).W))
val resp_ae_ptw = Reg(Bool())
val resp_ae_final = Reg(Bool())
val resp_pf = Reg(Bool())
val resp_gf = Reg(Bool())
val resp_hr = Reg(Bool())
val resp_hw = Reg(Bool())
val resp_hx = Reg(Bool())
val resp_fragmented_superpage = Reg(Bool())
/** tlb request */
val r_req = Reg(new PTWReq)
/** current selected way in arbitor */
val r_req_dest = Reg(Bits())
// to respond to L1TLB : l2_hit
// to construct mem.req.addr
val r_pte = Reg(new PTE)
val r_hgatp = Reg(new PTBR)
// 2-stage pageLevel
val aux_count = Reg(UInt(log2Ceil(pgLevels).W))
/** pte for 2-stage translation */
val aux_pte = Reg(new PTE)
val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case
val stage2 = Reg(Bool())
val stage2_final = Reg(Bool())
val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr)
val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels
/** 2-stage translation both enable */
val do_both_stages = r_req.vstage1 && r_req.stage2
val max_count = count max aux_count
val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr)
val mem_resp_valid = RegNext(io.mem.resp.valid)
val mem_resp_data = RegNext(io.mem.resp.bits.data)
io.mem.uncached_resp.map { resp =>
assert(!(resp.valid && io.mem.resp.valid))
resp.ready := true.B
when (resp.valid) {
mem_resp_valid := true.B
mem_resp_data := resp.bits.data
}
}
// construct pte from mem.resp
val (pte, invalid_paddr, invalid_gpa) = {
val tmp = mem_resp_data.asTypeOf(new PTE())
val res = WireDefault(tmp)
res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0))
when (tmp.r || tmp.w || tmp.x) {
// for superpage mappings, make sure PPN LSBs are zero
for (i <- 0 until pgLevels-1)
when (count <= i.U && tmp.ppn((pgLevels-1-i)*pgLevelBits-1, (pgLevels-2-i)*pgLevelBits) =/= 0.U) { res.v := false.B }
}
(res,
Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U),
do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn))
}
// find non-leaf PTE, need traverse
val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U
/** address send to mem for enquerry */
val pte_addr = if (!usingVM) 0.U else {
val vpn_idxs = (0 until pgLevels).map { i =>
val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0)
(vpn >> (pgLevels - i - 1) * pgLevelBits)(width - 1, 0)
}
val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U)
val vpn_idx = vpn_idxs(count) & mask
val raw_pte_addr = ((r_pte.ppn << pgLevelBits) | vpn_idx) << log2Ceil(xLen / 8)
val size = if (usingHypervisor) vaddrBits else paddrBits
//use r_pte.ppn as page table base address
//use vpn slice as offset
raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0)
}
/** stage2_pte_cache input addr */
val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else {
val vpn_idxs = (0 until pgLevels - 1).map { i =>
(r_req.addr >> (pgLevels - i - 1) * pgLevelBits)(pgLevelBits - 1, 0)
}
val vpn_idx = vpn_idxs(aux_count)
val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8)
raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0)
}
def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = {
(pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBits*i), r_req.addr(((pgLevelBits*i) min vpnBits)-1, 0).padTo(pgLevelBits*i)))
}
/** PTECache caches non-leaf PTE
* @param s2 true: 2-stage address translation
*/
def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) {
(false.B, 0.U)
} else {
val plru = new PseudoLRU(coreParams.nPTECacheEntries)
val valid = RegInit(0.U(coreParams.nPTECacheEntries.W))
val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W)))
// not include full pte, only ppn
val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W)))
val can_hit =
if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final
else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2)
val can_refill =
if (s2) do_both_stages && !stage2 && !stage2_final
else can_hit
val tag =
if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits))
else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits))
val hits = tags.map(_ === tag).asUInt & valid
val hit = hits.orR && can_hit
// refill with mem response
when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) {
val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid))
valid := valid | UIntToOH(r)
tags(r) := tag
data(r) := pte.ppn
plru.access(r)
}
// replace
when (hit && state === s_req) { plru.access(OHToUInt(hits)) }
when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 || usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U }
val lcount = if (s2) aux_count else count
for (i <- 0 until pgLevels-1) {
ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i")
}
(hit, Mux1H(hits, data))
}
// generate pte_cache
val (pte_cache_hit, pte_cache_data) = makePTECache(false)
// generate pte_cache with 2-stage translation
val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true)
// pte_cache hit or 2-stage pte_cache hit
val pte_hit = RegNext(false.B)
io.dpath.perf.pte_miss := false.B
io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit
assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)),
"PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event")
// l2_refill happens when find the leaf pte
val l2_refill = RegNext(false.B)
l2_refill_wire := l2_refill
io.dpath.perf.l2miss := false.B
io.dpath.perf.l2hit := false.B
// l2tlb
val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else {
val code = new ParityCode
require(isPow2(coreParams.nL2TLBEntries))
require(isPow2(coreParams.nL2TLBWays))
require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays)
val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays
require(isPow2(nL2TLBSets))
val idxBits = log2Ceil(nL2TLBSets)
val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru")
val ram = DescribedSRAM(
name = "l2_tlb_ram",
desc = "L2 TLB",
size = nL2TLBSets,
data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W))
)
val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W)))
val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W))))
// use r_req to construct tag
val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits)
/** the valid vec for the selected set(including n ways) */
val r_valid_vec = valid.map(_(r_idx)).asUInt
val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W))
val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W))
r_valid_vec_q := r_valid_vec
// replacement way
r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U)
// refill with r_pte(leaf pte)
when (l2_refill && !invalidated) {
val entry = Wire(new L2TLBEntry(nL2TLBSets))
entry.ppn := r_pte.ppn
entry.d := r_pte.d
entry.a := r_pte.a
entry.u := r_pte.u
entry.x := r_pte.x
entry.w := r_pte.w
entry.r := r_pte.r
entry.tag := r_tag
// if all the way are valid, use plru to select one way to be replaced,
// otherwise use PriorityEncoderOH to select one
val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W)
ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools)
val mask = UIntToOH(r_idx)
for (way <- 0 until coreParams.nL2TLBWays) {
when (wmask(way)) {
valid(way) := valid(way) | mask
g(way) := Mux(r_pte.g, g(way) | mask, g(way) & ~mask)
}
}
}
// sfence happens
when (io.dpath.sfence.valid) {
val hg = usingHypervisor.B && io.dpath.sfence.bits.hg
for (way <- 0 until coreParams.nL2TLBWays) {
valid(way) :=
Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)),
Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way),
0.U))
}
}
val s0_valid = !l2_refill && arb.io.out.fire
val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa
val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid)
val s2_valid = RegNext(s1_valid)
// read from tlb idx
val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid)
val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid)))
val s2_valid_vec = RegEnable(r_valid_vec, s1_valid)
val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid)
val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR
when (s2_valid && s2_error) { valid.foreach { _ := 0.U }}
// decode
val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets)))
val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag))
val s2_hit = s2_valid && s2_hit_vec.orR
io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR)
io.dpath.perf.l2hit := s2_hit
when (s2_hit) {
l2_plru.access(r_idx, OHToUInt(s2_hit_vec))
assert((PopCount(s2_hit_vec) === 1.U) || s2_error, "L2 TLB multi-hit")
}
val s2_pte = Wire(new PTE)
val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec)
s2_pte.ppn := s2_hit_entry.ppn
s2_pte.d := s2_hit_entry.d
s2_pte.a := s2_hit_entry.a
s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec)
s2_pte.u := s2_hit_entry.u
s2_pte.x := s2_hit_entry.x
s2_pte.w := s2_hit_entry.w
s2_pte.r := s2_hit_entry.r
s2_pte.v := true.B
s2_pte.reserved_for_future := 0.U
s2_pte.reserved_for_software := 0.U
for (way <- 0 until coreParams.nL2TLBWays) {
ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way")
}
(s2_hit, s2_error, s2_pte, Some(ram))
}
// if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk
invalidated := io.dpath.sfence.valid || (invalidated && state =/= s_ready)
// mem request
io.mem.keep_clock_enabled := false.B
io.mem.req.valid := state === s_req || state === s_dummy1
io.mem.req.bits.phys := true.B
io.mem.req.bits.cmd := M_XRD
io.mem.req.bits.size := log2Ceil(xLen/8).U
io.mem.req.bits.signed := false.B
io.mem.req.bits.addr := pte_addr
io.mem.req.bits.idx.foreach(_ := pte_addr)
io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition
io.mem.req.bits.dv := do_both_stages && !stage2
io.mem.req.bits.tag := DontCare
io.mem.req.bits.no_resp := false.B
io.mem.req.bits.no_alloc := DontCare
io.mem.req.bits.no_xcpt := DontCare
io.mem.req.bits.data := DontCare
io.mem.req.bits.mask := DontCare
io.mem.s1_kill := l2_hit || (state =/= s_wait1) || resp_gf
io.mem.s1_data := DontCare
io.mem.s2_kill := false.B
val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits)
require(!usingHypervisor || pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}")
val pmaPgLevelHomogeneous = (0 until pgLevels) map { i =>
val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) * pgLevelBits))
if (pageGranularityPMPs && i == pgLevels - 1) {
require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned")
true.B
} else {
TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous
}
}
val pmaHomogeneous = pmaPgLevelHomogeneous(count)
val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count)
val homogeneous = pmaHomogeneous && pmpHomogeneous
// response to tlb
for (i <- 0 until io.requestor.size) {
io.requestor(i).resp.valid := resp_valid(i)
io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw
io.requestor(i).resp.bits.ae_final := resp_ae_final
io.requestor(i).resp.bits.pf := resp_pf
io.requestor(i).resp.bits.gf := resp_gf
io.requestor(i).resp.bits.hr := resp_hr
io.requestor(i).resp.bits.hw := resp_hw
io.requestor(i).resp.bits.hx := resp_hx
io.requestor(i).resp.bits.pte := r_pte
io.requestor(i).resp.bits.level := max_count
io.requestor(i).resp.bits.homogeneous := homogeneous || pageGranularityPMPs.B
io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B
io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa
io.requestor(i).resp.bits.gpa.bits :=
Cat(Mux(!stage2_final || !r_req.vstage1 || aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff)
io.requestor(i).resp.bits.gpa_is_pte := !stage2_final
io.requestor(i).ptbr := io.dpath.ptbr
io.requestor(i).hgatp := io.dpath.hgatp
io.requestor(i).vsatp := io.dpath.vsatp
io.requestor(i).customCSRs <> io.dpath.customCSRs
io.requestor(i).status := io.dpath.status
io.requestor(i).hstatus := io.dpath.hstatus
io.requestor(i).gstatus := io.dpath.gstatus
io.requestor(i).pmp := io.dpath.pmp
}
// control state machine
val next_state = WireDefault(state)
state := OptimizationBarrier(next_state)
val do_switch = WireDefault(false.B)
switch (state) {
is (s_ready) {
when (arb.io.out.fire) {
val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels
val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels
val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels
val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr)
r_req := arb.io.out.bits.bits
r_req_dest := arb.io.chosen
next_state := Mux(arb.io.out.bits.valid, s_req, s_ready)
stage2 := arb.io.out.bits.bits.stage2
stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1
count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count)
aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U)
aux_pte.ppn := aux_ppn
aux_pte.reserved_for_future := 0.U
resp_ae_ptw := false.B
resp_ae_final := false.B
resp_pf := false.B
resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2
resp_hr := true.B
resp_hw := true.B
resp_hx := true.B
resp_fragmented_superpage := false.B
r_hgatp := io.dpath.hgatp
assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2)
}
}
is (s_req) {
when(stage2 && count === r_hgatp_initial_count) {
gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr)
}
// pte_cache hit
when (stage2_pte_cache_hit) {
aux_count := aux_count + 1.U
aux_pte.ppn := stage2_pte_cache_data
aux_pte.reserved_for_future := 0.U
pte_hit := true.B
}.elsewhen (pte_cache_hit) {
count := count + 1.U
pte_hit := true.B
}.otherwise {
next_state := Mux(io.mem.req.ready, s_wait1, s_req)
}
when(resp_gf) {
next_state := s_ready
resp_valid(r_req_dest) := true.B
}
}
is (s_wait1) {
// This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below
next_state := Mux(l2_hit, s_req, s_wait2)
}
is (s_wait2) {
next_state := s_wait3
io.dpath.perf.pte_miss := count < (pgLevels-1).U
when (io.mem.s2_xcpt.ae.ld) {
resp_ae_ptw := true.B
next_state := s_ready
resp_valid(r_req_dest) := true.B
}
}
is (s_fragment_superpage) {
next_state := s_ready
resp_valid(r_req_dest) := true.B
when (!homogeneous) {
count := (pgLevels-1).U
resp_fragmented_superpage := true.B
}
when (do_both_stages) {
resp_fragmented_superpage := true.B
}
}
}
val merged_pte = {
val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)*pgLevelBits)).U)
val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U))
val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), aux_pte.ppn((pgLevels-i-1)*pgLevelBits-1,0))) :+ pte.ppn
val stage1_ppn = stage1_ppns(count)
makePTE(stage1_ppn & superpage_mask, aux_pte)
}
r_pte := OptimizationBarrier(
// l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB
Mux(l2_hit && !l2_error && !resp_gf, l2_pte,
// S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp
Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte),
// pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem
Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte),
// 2-stage translation
Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte),
// when mem respond, store mem.resp.pte
Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte),
// fragment_superpage
Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte),
// when tlb request come->request mem, use root address in satp(or vsatp,hgatp)
Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)),
r_pte))))))))
when (l2_hit && !l2_error && !resp_gf) {
assert(state === s_req || state === s_wait1)
next_state := s_ready
resp_valid(r_req_dest) := true.B
count := (pgLevels-1).U
}
when (mem_resp_valid) {
assert(state === s_wait3)
next_state := s_req
when (traverse) {
when (do_both_stages && !stage2) { do_switch := true.B }
count := count + 1.U
}.otherwise {
val gf = (stage2 && !stage2_final && !pte.ur()) || (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa)
val ae = pte.v && invalid_paddr
val pf = pte.v && pte.reserved_for_future =/= 0.U
val success = pte.v && !ae && !pf && !gf
when (do_both_stages && !stage2_final && success) {
when (stage2) {
stage2 := false.B
count := aux_count
}.otherwise {
stage2_final := true.B
do_switch := true.B
}
}.otherwise {
// find a leaf pte, start l2 refill
l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa &&
(!r_req.vstage1 && !r_req.stage2 ||
do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm())
count := max_count
when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages || aux_count === (pgLevels-1).U))) {
next_state := s_fragment_superpage
}.otherwise {
next_state := s_ready
resp_valid(r_req_dest) := true.B
}
resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table()
resp_ae_final := ae && pte.leaf()
resp_pf := pf && !stage2
resp_gf := gf || (pf && stage2)
resp_hr := !stage2 || (!pf && !gf && pte.ur())
resp_hw := !stage2 || (!pf && !gf && pte.uw())
resp_hx := !stage2 || (!pf && !gf && pte.ux())
}
}
}
when (io.mem.s2_nack) {
assert(state === s_wait2)
next_state := s_req
}
when (do_switch) {
aux_count := Mux(traverse, count + 1.U, count)
count := r_hgatp_initial_count
aux_pte := Mux(traverse, pte, {
val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), r_req.addr(((pgLevels-i-1)*pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)*pgLevelBits))) :+ pte.ppn
makePTE(s1_ppns(count), pte)
})
stage2 := true.B
}
for (i <- 0 until pgLevels) {
val leaf = mem_resp_valid && !traverse && count === i.U
ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i")
ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i")
ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i")
ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i")
ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i")
if (i != pgLevels-1)
ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i")
}
ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep")
ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access")
ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table")
} // leaving gated-clock domain
private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc)
/** Relace PTE.ppn with ppn */
private def makePTE(ppn: UInt, default: PTE) = {
val pte = WireDefault(default)
pte.ppn := ppn
pte
}
/** use hgatp and vpn to construct a new ppn */
private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = {
val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels
val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)*pgLevelBits))
val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count))
val pte = WireDefault(default)
pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs)
pte
}
/** use hgatp and vpn to check for gpa out of range */
private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = {
val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels
val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)*pgLevelBits)+maxHypervisorExtraAddrBits))
idxs.extract(count) =/= 0.U
}
}
/** Mix-ins for constructing tiles that might have a PTW */
trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile =>
val module: CanHavePTWModule
var nPTWPorts = 1
nDCachePorts += usingPTW.toInt
}
trait CanHavePTWModule extends HasHellaCacheModule {
val outer: CanHavePTW
val ptwPorts = ListBuffer(outer.dcache.module.io.ptw)
val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p))
ptw.io.mem <> DontCare
if (outer.usingPTW) {
dcachePorts += ptw.io.mem
}
}
|
module DTLB_9( // @[TLB.scala:318:7]
input clock, // @[TLB.scala:318:7]
input reset, // @[TLB.scala:318:7]
output io_req_ready, // @[TLB.scala:320:14]
input io_req_valid, // @[TLB.scala:320:14]
input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14]
input [1:0] io_req_bits_size, // @[TLB.scala:320:14]
input [4:0] io_req_bits_cmd, // @[TLB.scala:320:14]
output io_resp_miss, // @[TLB.scala:320:14]
output [31:0] io_resp_paddr, // @[TLB.scala:320:14]
input io_sfence_valid, // @[TLB.scala:320:14]
input io_ptw_req_ready, // @[TLB.scala:320:14]
output io_ptw_req_valid, // @[TLB.scala:320:14]
output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14]
output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14]
input io_ptw_resp_valid, // @[TLB.scala:320:14]
input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14]
input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pf, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gf, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hr, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hw, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hx, // @[TLB.scala:320:14]
input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14]
input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14]
input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14]
input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14]
input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14]
input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14]
input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14]
input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14]
input io_ptw_status_debug, // @[TLB.scala:320:14]
input io_ptw_status_cease, // @[TLB.scala:320:14]
input io_ptw_status_wfi, // @[TLB.scala:320:14]
input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14]
input io_ptw_status_dv, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14]
input io_ptw_status_v, // @[TLB.scala:320:14]
input io_ptw_status_sd, // @[TLB.scala:320:14]
input [22:0] io_ptw_status_zero2, // @[TLB.scala:320:14]
input io_ptw_status_mpv, // @[TLB.scala:320:14]
input io_ptw_status_gva, // @[TLB.scala:320:14]
input io_ptw_status_mbe, // @[TLB.scala:320:14]
input io_ptw_status_sbe, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_sxl, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_uxl, // @[TLB.scala:320:14]
input io_ptw_status_sd_rv32, // @[TLB.scala:320:14]
input [7:0] io_ptw_status_zero1, // @[TLB.scala:320:14]
input io_ptw_status_tsr, // @[TLB.scala:320:14]
input io_ptw_status_tw, // @[TLB.scala:320:14]
input io_ptw_status_tvm, // @[TLB.scala:320:14]
input io_ptw_status_mxr, // @[TLB.scala:320:14]
input io_ptw_status_sum, // @[TLB.scala:320:14]
input io_ptw_status_mprv, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_xs, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_vs, // @[TLB.scala:320:14]
input io_ptw_status_spp, // @[TLB.scala:320:14]
input io_ptw_status_mpie, // @[TLB.scala:320:14]
input io_ptw_status_ube, // @[TLB.scala:320:14]
input io_ptw_status_spie, // @[TLB.scala:320:14]
input io_ptw_status_upie, // @[TLB.scala:320:14]
input io_ptw_status_mie, // @[TLB.scala:320:14]
input io_ptw_status_hie, // @[TLB.scala:320:14]
input io_ptw_status_sie, // @[TLB.scala:320:14]
input io_ptw_status_uie, // @[TLB.scala:320:14]
input io_ptw_hstatus_spvp, // @[TLB.scala:320:14]
input io_ptw_hstatus_spv, // @[TLB.scala:320:14]
input io_ptw_hstatus_gva, // @[TLB.scala:320:14]
input io_ptw_gstatus_debug, // @[TLB.scala:320:14]
input io_ptw_gstatus_cease, // @[TLB.scala:320:14]
input io_ptw_gstatus_wfi, // @[TLB.scala:320:14]
input [31:0] io_ptw_gstatus_isa, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_dprv, // @[TLB.scala:320:14]
input io_ptw_gstatus_dv, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_prv, // @[TLB.scala:320:14]
input io_ptw_gstatus_v, // @[TLB.scala:320:14]
input [22:0] io_ptw_gstatus_zero2, // @[TLB.scala:320:14]
input io_ptw_gstatus_mpv, // @[TLB.scala:320:14]
input io_ptw_gstatus_gva, // @[TLB.scala:320:14]
input io_ptw_gstatus_mbe, // @[TLB.scala:320:14]
input io_ptw_gstatus_sbe, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_sxl, // @[TLB.scala:320:14]
input [7:0] io_ptw_gstatus_zero1, // @[TLB.scala:320:14]
input io_ptw_gstatus_tsr, // @[TLB.scala:320:14]
input io_ptw_gstatus_tw, // @[TLB.scala:320:14]
input io_ptw_gstatus_tvm, // @[TLB.scala:320:14]
input io_ptw_gstatus_mxr, // @[TLB.scala:320:14]
input io_ptw_gstatus_sum, // @[TLB.scala:320:14]
input io_ptw_gstatus_mprv, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_fs, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_mpp, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_vs, // @[TLB.scala:320:14]
input io_ptw_gstatus_spp, // @[TLB.scala:320:14]
input io_ptw_gstatus_mpie, // @[TLB.scala:320:14]
input io_ptw_gstatus_ube, // @[TLB.scala:320:14]
input io_ptw_gstatus_spie, // @[TLB.scala:320:14]
input io_ptw_gstatus_upie, // @[TLB.scala:320:14]
input io_ptw_gstatus_mie, // @[TLB.scala:320:14]
input io_ptw_gstatus_hie, // @[TLB.scala:320:14]
input io_ptw_gstatus_sie, // @[TLB.scala:320:14]
input io_ptw_gstatus_uie, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_0_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_0_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_0_value, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_1_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_1_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_1_value, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_2_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_2_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_2_value, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_3_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_3_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_3_value // @[TLB.scala:320:14]
);
wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25]
wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_io_y_c; // @[package.scala:267:25]
wire _pma_io_resp_r; // @[TLB.scala:422:19]
wire _pma_io_resp_w; // @[TLB.scala:422:19]
wire _pma_io_resp_pp; // @[TLB.scala:422:19]
wire _pma_io_resp_al; // @[TLB.scala:422:19]
wire _pma_io_resp_aa; // @[TLB.scala:422:19]
wire _pma_io_resp_x; // @[TLB.scala:422:19]
wire _pma_io_resp_eff; // @[TLB.scala:422:19]
wire _pmp_io_r; // @[TLB.scala:416:19]
wire _pmp_io_w; // @[TLB.scala:416:19]
wire _pmp_io_x; // @[TLB.scala:416:19]
wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25]
wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7]
wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7]
wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[TLB.scala:318:7]
wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[TLB.scala:318:7]
wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7]
wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7]
wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7]
wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7]
wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7]
wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7]
wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7]
wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7]
wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7]
wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7]
wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7]
wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7]
wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7]
wire [22:0] io_ptw_status_zero2_0 = io_ptw_status_zero2; // @[TLB.scala:318:7]
wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7]
wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7]
wire io_ptw_status_mbe_0 = io_ptw_status_mbe; // @[TLB.scala:318:7]
wire io_ptw_status_sbe_0 = io_ptw_status_sbe; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_sxl_0 = io_ptw_status_sxl; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_uxl_0 = io_ptw_status_uxl; // @[TLB.scala:318:7]
wire io_ptw_status_sd_rv32_0 = io_ptw_status_sd_rv32; // @[TLB.scala:318:7]
wire [7:0] io_ptw_status_zero1_0 = io_ptw_status_zero1; // @[TLB.scala:318:7]
wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7]
wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7]
wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7]
wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7]
wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7]
wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_xs_0 = io_ptw_status_xs; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_vs_0 = io_ptw_status_vs; // @[TLB.scala:318:7]
wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7]
wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7]
wire io_ptw_status_ube_0 = io_ptw_status_ube; // @[TLB.scala:318:7]
wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7]
wire io_ptw_status_upie_0 = io_ptw_status_upie; // @[TLB.scala:318:7]
wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7]
wire io_ptw_status_hie_0 = io_ptw_status_hie; // @[TLB.scala:318:7]
wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7]
wire io_ptw_status_uie_0 = io_ptw_status_uie; // @[TLB.scala:318:7]
wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[TLB.scala:318:7]
wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[TLB.scala:318:7]
wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[TLB.scala:318:7]
wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[TLB.scala:318:7]
wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[TLB.scala:318:7]
wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[TLB.scala:318:7]
wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[TLB.scala:318:7]
wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[TLB.scala:318:7]
wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[TLB.scala:318:7]
wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[TLB.scala:318:7]
wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[TLB.scala:318:7]
wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[TLB.scala:318:7]
wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[TLB.scala:318:7]
wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[TLB.scala:318:7]
wire [6:0] hr_array = 7'h7F; // @[TLB.scala:524:21]
wire [6:0] hw_array = 7'h7F; // @[TLB.scala:525:21]
wire [6:0] hx_array = 7'h7F; // @[TLB.scala:526:21]
wire [6:0] _must_alloc_array_T_8 = 7'h7F; // @[TLB.scala:596:19]
wire [6:0] _gf_ld_array_T_1 = 7'h7F; // @[TLB.scala:600:50]
wire [5:0] stage2_bypass = 6'h3F; // @[TLB.scala:523:27]
wire [5:0] _hr_array_T_4 = 6'h3F; // @[TLB.scala:524:111]
wire [5:0] _hw_array_T_1 = 6'h3F; // @[TLB.scala:525:55]
wire [5:0] _hx_array_T_1 = 6'h3F; // @[TLB.scala:526:55]
wire [5:0] _gpa_hits_hit_mask_T_4 = 6'h3F; // @[TLB.scala:606:88]
wire [5:0] gpa_hits_hit_mask = 6'h3F; // @[TLB.scala:606:82]
wire [5:0] _gpa_hits_T_1 = 6'h3F; // @[TLB.scala:607:16]
wire [5:0] gpa_hits = 6'h3F; // @[TLB.scala:607:14]
wire [2:0] _state_vec_WIRE_0 = 3'h0; // @[Replacement.scala:305:25]
wire [2:0] _state_vec_WIRE_1 = 3'h0; // @[Replacement.scala:305:25]
wire [2:0] _state_vec_WIRE_2 = 3'h0; // @[Replacement.scala:305:25]
wire [2:0] _state_vec_WIRE_3 = 3'h0; // @[Replacement.scala:305:25]
wire [6:0] _gf_ld_array_T_2 = 7'h0; // @[TLB.scala:600:46]
wire [6:0] gf_ld_array = 7'h0; // @[TLB.scala:600:24]
wire [6:0] _gf_st_array_T_1 = 7'h0; // @[TLB.scala:601:53]
wire [6:0] gf_st_array = 7'h0; // @[TLB.scala:601:24]
wire [6:0] _gf_inst_array_T = 7'h0; // @[TLB.scala:602:36]
wire [6:0] gf_inst_array = 7'h0; // @[TLB.scala:602:26]
wire [6:0] gpa_hits_need_gpa_mask = 7'h0; // @[TLB.scala:605:73]
wire [6:0] _io_resp_gf_ld_T_1 = 7'h0; // @[TLB.scala:637:58]
wire [6:0] _io_resp_gf_st_T_1 = 7'h0; // @[TLB.scala:638:65]
wire [6:0] _io_resp_gf_inst_T = 7'h0; // @[TLB.scala:639:48]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[TLB.scala:318:7]
wire [38:0] io_sfence_bits_addr = 39'h0; // @[TLB.scala:318:7, :320:14]
wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[TLB.scala:318:7]
wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sd = 1'h1; // @[TLB.scala:318:7]
wire priv_uses_vm = 1'h1; // @[TLB.scala:372:27]
wire _vm_enabled_T_2 = 1'h1; // @[TLB.scala:399:64]
wire _vsatp_mode_mismatch_T_2 = 1'h1; // @[TLB.scala:403:81]
wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22]
wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_37 = 1'h1; // @[TLB.scala:183:40]
wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34]
wire _priv_rw_ok_T = 1'h1; // @[TLB.scala:513:24]
wire _priv_rw_ok_T_1 = 1'h1; // @[TLB.scala:513:32]
wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42]
wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26]
wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107]
wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32]
wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20]
wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28]
wire ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7]
wire [5:0] _priv_rw_ok_T_6 = 6'h0; // @[TLB.scala:513:75]
wire [5:0] _stage1_bypass_T = 6'h0; // @[TLB.scala:517:27]
wire [5:0] stage1_bypass = 6'h0; // @[TLB.scala:517:61]
wire [5:0] _gpa_hits_T = 6'h0; // @[TLB.scala:607:30]
wire [1:0] io_req_bits_prv = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7, :320:14]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7, :320:14]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17]
wire [15:0] satp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17]
wire io_req_bits_passthrough = 1'h0; // @[TLB.scala:318:7]
wire io_req_bits_v = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7]
wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7]
wire io_sfence_bits_rs1 = 1'h0; // @[TLB.scala:318:7]
wire io_sfence_bits_rs2 = 1'h0; // @[TLB.scala:318:7]
wire io_sfence_bits_asid = 1'h0; // @[TLB.scala:318:7]
wire io_sfence_bits_hv = 1'h0; // @[TLB.scala:318:7]
wire io_sfence_bits_hg = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[TLB.scala:318:7]
wire io_kill = 1'h0; // @[TLB.scala:318:7]
wire priv_v = 1'h0; // @[TLB.scala:369:34]
wire priv_s = 1'h0; // @[TLB.scala:370:20]
wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38]
wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68]
wire vstage1_en = 1'h0; // @[TLB.scala:376:48]
wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38]
wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68]
wire stage2_en = 1'h0; // @[TLB.scala:378:48]
wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52]
wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37]
wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78]
wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire refill_v = 1'h0; // @[TLB.scala:448:33]
wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24]
wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24]
wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84]
wire _waddr_T = 1'h0; // @[TLB.scala:477:45]
wire _mxr_T = 1'h0; // @[TLB.scala:518:36]
wire cmd_readx = 1'h0; // @[TLB.scala:575:37]
wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32]
wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32]
wire _multipleHits_T_5 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_14 = 1'h0; // @[Misc.scala:183:37]
wire _io_req_ready_T; // @[TLB.scala:631:25]
wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29]
wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66]
wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42]
wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29]
wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73]
wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49]
wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56]
wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30]
wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36]
wire _r_superpage_repl_addr_T_3 = 1'h0; // @[TLB.scala:757:8]
wire hv = 1'h0; // @[TLB.scala:721:36]
wire hg = 1'h0; // @[TLB.scala:722:36]
wire hv_1 = 1'h0; // @[TLB.scala:721:36]
wire hg_1 = 1'h0; // @[TLB.scala:722:36]
wire hv_2 = 1'h0; // @[TLB.scala:721:36]
wire hg_2 = 1'h0; // @[TLB.scala:722:36]
wire hv_3 = 1'h0; // @[TLB.scala:721:36]
wire hg_3 = 1'h0; // @[TLB.scala:722:36]
wire hv_4 = 1'h0; // @[TLB.scala:721:36]
wire hg_4 = 1'h0; // @[TLB.scala:722:36]
wire hv_5 = 1'h0; // @[TLB.scala:721:36]
wire hg_5 = 1'h0; // @[TLB.scala:722:36]
wire hv_6 = 1'h0; // @[TLB.scala:721:36]
wire hg_6 = 1'h0; // @[TLB.scala:722:36]
wire hv_7 = 1'h0; // @[TLB.scala:721:36]
wire hg_7 = 1'h0; // @[TLB.scala:722:36]
wire hv_8 = 1'h0; // @[TLB.scala:721:36]
wire hg_8 = 1'h0; // @[TLB.scala:722:36]
wire hv_9 = 1'h0; // @[TLB.scala:721:36]
wire hg_9 = 1'h0; // @[TLB.scala:722:36]
wire hv_10 = 1'h0; // @[TLB.scala:721:36]
wire hg_10 = 1'h0; // @[TLB.scala:722:36]
wire hv_11 = 1'h0; // @[TLB.scala:721:36]
wire hg_11 = 1'h0; // @[TLB.scala:722:36]
wire hv_12 = 1'h0; // @[TLB.scala:721:36]
wire hg_12 = 1'h0; // @[TLB.scala:722:36]
wire hv_13 = 1'h0; // @[TLB.scala:721:36]
wire hg_13 = 1'h0; // @[TLB.scala:722:36]
wire hv_14 = 1'h0; // @[TLB.scala:721:36]
wire hg_14 = 1'h0; // @[TLB.scala:722:36]
wire hv_15 = 1'h0; // @[TLB.scala:721:36]
wire hg_15 = 1'h0; // @[TLB.scala:722:36]
wire hv_16 = 1'h0; // @[TLB.scala:721:36]
wire hg_16 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T = 1'h0; // @[TLB.scala:182:28]
wire ignore = 1'h0; // @[TLB.scala:182:34]
wire hv_17 = 1'h0; // @[TLB.scala:721:36]
wire hg_17 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire [1:0] io_resp_size = io_req_bits_size_0; // @[TLB.scala:318:7]
wire [4:0] io_resp_cmd = io_req_bits_cmd_0; // @[TLB.scala:318:7]
wire _io_resp_miss_T_2; // @[TLB.scala:651:64]
wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23]
wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8]
wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41]
wire _io_resp_pf_st_T_3; // @[TLB.scala:634:48]
wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29]
wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41]
wire _io_resp_ae_st_T_1; // @[TLB.scala:642:41]
wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41]
wire _io_resp_ma_ld_T; // @[TLB.scala:645:31]
wire _io_resp_ma_st_T; // @[TLB.scala:646:31]
wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41]
wire _io_resp_must_alloc_T_1; // @[TLB.scala:649:51]
wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59]
wire _io_ptw_req_valid_T; // @[TLB.scala:662:29]
wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29]
wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24]
wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13]
wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17]
wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17]
wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31]
wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16]
wire io_req_ready_0; // @[TLB.scala:318:7]
wire io_resp_pf_ld; // @[TLB.scala:318:7]
wire io_resp_pf_st; // @[TLB.scala:318:7]
wire io_resp_pf_inst; // @[TLB.scala:318:7]
wire io_resp_ae_ld; // @[TLB.scala:318:7]
wire io_resp_ae_st; // @[TLB.scala:318:7]
wire io_resp_ae_inst; // @[TLB.scala:318:7]
wire io_resp_ma_ld; // @[TLB.scala:318:7]
wire io_resp_ma_st; // @[TLB.scala:318:7]
wire io_resp_miss_0; // @[TLB.scala:318:7]
wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7]
wire [39:0] io_resp_gpa; // @[TLB.scala:318:7]
wire io_resp_cacheable; // @[TLB.scala:318:7]
wire io_resp_must_alloc; // @[TLB.scala:318:7]
wire io_resp_prefetchable; // @[TLB.scala:318:7]
wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7]
wire io_ptw_req_valid_0; // @[TLB.scala:318:7]
wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30]
wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30]
wire [1:0] memIdx = vpn[1:0]; // @[package.scala:163:13]
reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_1_0_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_1_0_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_1_0_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_1_0_data_0; // @[TLB.scala:339:29]
reg sectored_entries_1_0_valid_0; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_1_1_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_1_1_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_1_1_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_1_1_data_0; // @[TLB.scala:339:29]
reg sectored_entries_1_1_valid_0; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_1_2_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_1_2_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_1_2_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_1_2_data_0; // @[TLB.scala:339:29]
reg sectored_entries_1_2_valid_0; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_1_3_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_1_3_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_1_3_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_1_3_data_0; // @[TLB.scala:339:29]
reg sectored_entries_1_3_valid_0; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_2_0_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_2_0_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_2_0_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_2_0_data_0; // @[TLB.scala:339:29]
reg sectored_entries_2_0_valid_0; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_2_1_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_2_1_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_2_1_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_2_1_data_0; // @[TLB.scala:339:29]
reg sectored_entries_2_1_valid_0; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_2_2_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_2_2_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_2_2_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_2_2_data_0; // @[TLB.scala:339:29]
reg sectored_entries_2_2_valid_0; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_2_3_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_2_3_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_2_3_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_2_3_data_0; // @[TLB.scala:339:29]
reg sectored_entries_2_3_valid_0; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_3_0_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_3_0_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_3_0_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_3_0_data_0; // @[TLB.scala:339:29]
reg sectored_entries_3_0_valid_0; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_3_1_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_3_1_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_3_1_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_3_1_data_0; // @[TLB.scala:339:29]
reg sectored_entries_3_1_valid_0; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_3_2_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_3_2_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_3_2_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_3_2_data_0; // @[TLB.scala:339:29]
reg sectored_entries_3_2_valid_0; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_3_3_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_3_3_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_3_3_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_3_3_data_0; // @[TLB.scala:339:29]
reg sectored_entries_3_3_valid_0; // @[TLB.scala:339:29]
reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_0_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_9 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_0_valid_0; // @[TLB.scala:341:30]
wire _r_superpage_repl_addr_T = superpage_entries_0_valid_0; // @[TLB.scala:341:30, :757:16]
reg [1:0] special_entry_level; // @[TLB.scala:346:56]
reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56]
reg special_entry_tag_v; // @[TLB.scala:346:56]
reg [41:0] special_entry_data_0; // @[TLB.scala:346:56]
wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56]
wire [41:0] _entries_WIRE_11 = special_entry_data_0; // @[TLB.scala:170:77, :346:56]
reg special_entry_valid_0; // @[TLB.scala:346:56]
reg [1:0] state; // @[TLB.scala:352:22]
reg [26:0] r_refill_tag; // @[TLB.scala:354:25]
assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25]
reg [1:0] r_sectored_repl_addr; // @[TLB.scala:356:33]
reg r_sectored_hit_valid; // @[TLB.scala:357:27]
reg [1:0] r_sectored_hit_bits; // @[TLB.scala:357:27]
reg r_superpage_hit_valid; // @[TLB.scala:358:28]
reg r_need_gpa; // @[TLB.scala:361:23]
assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23]
reg r_gpa_valid; // @[TLB.scala:362:24]
reg [38:0] r_gpa; // @[TLB.scala:363:18]
reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22]
reg r_gpa_is_pte; // @[TLB.scala:365:25]
wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41]
wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}]
wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31]
wire _vm_enabled_T_1 = _vm_enabled_T; // @[TLB.scala:399:{31,45}]
wire vm_enabled = _vm_enabled_T_1; // @[TLB.scala:399:{45,61}]
wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32]
wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29]
wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44]
wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24]
wire _mpu_priv_T = do_refill; // @[TLB.scala:408:29, :415:52]
wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29]
wire _T_25 = state == 2'h1; // @[package.scala:16:47]
wire _invalidate_refill_T; // @[package.scala:16:47]
assign _invalidate_refill_T = _T_25; // @[package.scala:16:47]
assign _io_ptw_req_valid_T = _T_25; // @[package.scala:16:47]
wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47]
wire _invalidate_refill_T_2 = _invalidate_refill_T | _invalidate_refill_T_1; // @[package.scala:16:47, :81:59]
wire invalidate_refill = _invalidate_refill_T_2 | io_sfence_valid_0; // @[package.scala:81:59]
wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77]
wire _mpu_ppn_T_22; // @[TLB.scala:170:77]
wire _mpu_ppn_T_21; // @[TLB.scala:170:77]
wire _mpu_ppn_T_20; // @[TLB.scala:170:77]
wire _mpu_ppn_T_19; // @[TLB.scala:170:77]
wire _mpu_ppn_T_18; // @[TLB.scala:170:77]
wire _mpu_ppn_T_17; // @[TLB.scala:170:77]
wire _mpu_ppn_T_16; // @[TLB.scala:170:77]
wire _mpu_ppn_T_15; // @[TLB.scala:170:77]
wire _mpu_ppn_T_14; // @[TLB.scala:170:77]
wire _mpu_ppn_T_13; // @[TLB.scala:170:77]
wire _mpu_ppn_T_12; // @[TLB.scala:170:77]
wire _mpu_ppn_T_11; // @[TLB.scala:170:77]
wire _mpu_ppn_T_10; // @[TLB.scala:170:77]
wire _mpu_ppn_T_9; // @[TLB.scala:170:77]
wire _mpu_ppn_T_8; // @[TLB.scala:170:77]
wire _mpu_ppn_T_7; // @[TLB.scala:170:77]
wire _mpu_ppn_T_6; // @[TLB.scala:170:77]
wire _mpu_ppn_T_5; // @[TLB.scala:170:77]
wire _mpu_ppn_T_4; // @[TLB.scala:170:77]
wire _mpu_ppn_T_3; // @[TLB.scala:170:77]
wire _mpu_ppn_T_2; // @[TLB.scala:170:77]
wire _mpu_ppn_T_1; // @[TLB.scala:170:77]
assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77]
assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77]
assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77]
assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77]
assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77]
assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77]
assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77]
assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77]
assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77]
assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77]
assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77]
assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77]
assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77]
assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77]
assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77]
assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77]
assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77]
assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77]
assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77]
assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77]
assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77]
assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77]
assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77]
wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25]
wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56]
wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28]
assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28]
wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_4 = _GEN; // @[TLB.scala:182:28, :197:28]
wire _ppn_ignore_T_2; // @[TLB.scala:197:28]
assign _ppn_ignore_T_2 = _GEN; // @[TLB.scala:197:28]
wire _ignore_T_4; // @[TLB.scala:182:28]
assign _ignore_T_4 = _GEN; // @[TLB.scala:182:28, :197:28]
wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}]
wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}]
wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56]
wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}]
wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}]
wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146]
wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}]
wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20]
wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52]
wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46]
wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82]
wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}]
wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25]
wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25]
wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}]
wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, 2'h0}; // @[TLB.scala:318:7, :415:103]
wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}]
wire cacheable; // @[TLB.scala:425:41]
wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24]
wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46]
wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65]
wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31]
assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31]
assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46]
wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31]
assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31]
assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31]
assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31]
assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31]
assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46]
wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46]
wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46]
wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46]
wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31]
assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31]
assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31]
assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46]
wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46]
wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46]
wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15]
wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31]
assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31]
assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31]
assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46]
wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_51 = _homogeneous_T_50 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_52 = _homogeneous_T_51 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_53 = _homogeneous_T_52 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_54 = _homogeneous_T_53 | _homogeneous_T_24; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_55 = _homogeneous_T_54 | _homogeneous_T_29; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_56 = _homogeneous_T_55 | _homogeneous_T_34; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_57 = _homogeneous_T_56 | _homogeneous_T_39; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_58 = _homogeneous_T_57 | _homogeneous_T_44; // @[TLBPermissions.scala:101:65]
wire homogeneous = _homogeneous_T_58 | _homogeneous_T_49; // @[TLBPermissions.scala:101:65]
wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46]
wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}]
wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46]
wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46]
wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46]
wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46]
wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46]
wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_93 = _homogeneous_T_92 | _homogeneous_T_76; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_94 = _homogeneous_T_93 | _homogeneous_T_81; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_95 = _homogeneous_T_94 | _homogeneous_T_86; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_96 = _homogeneous_T_95 | _homogeneous_T_91; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46]
wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46]
wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_108 = _homogeneous_T_107 | _homogeneous_T_106; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46]
wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}]
wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46]
wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}]
wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39]
wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46]
wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}]
wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33]
wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}]
wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}]
wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24]
wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33]
wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}]
wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}]
wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24]
wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33]
wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}]
wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}]
wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24]
wire [3:0][26:0] _GEN_4 = {{sectored_entries_3_0_tag_vpn}, {sectored_entries_2_0_tag_vpn}, {sectored_entries_1_0_tag_vpn}, {sectored_entries_0_0_tag_vpn}}; // @[TLB.scala:174:61, :339:29]
wire [3:0] _GEN_5 = {{sectored_entries_3_0_tag_v}, {sectored_entries_2_0_tag_v}, {sectored_entries_1_0_tag_v}, {sectored_entries_0_0_tag_v}}; // @[TLB.scala:174:61, :339:29]
wire [3:0][41:0] _GEN_6 = {{sectored_entries_3_0_data_0}, {sectored_entries_2_0_data_0}, {sectored_entries_1_0_data_0}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:174:61, :339:29]
wire [41:0] _entries_WIRE_1 = _GEN_6[memIdx]; // @[package.scala:163:13]
wire [3:0] _GEN_7 = {{sectored_entries_3_0_valid_0}, {sectored_entries_2_0_valid_0}, {sectored_entries_1_0_valid_0}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:174:61, :339:29]
wire [3:0][26:0] _GEN_8 = {{sectored_entries_3_1_tag_vpn}, {sectored_entries_2_1_tag_vpn}, {sectored_entries_1_1_tag_vpn}, {sectored_entries_0_1_tag_vpn}}; // @[TLB.scala:174:61, :339:29]
wire [3:0] _GEN_9 = {{sectored_entries_3_1_tag_v}, {sectored_entries_2_1_tag_v}, {sectored_entries_1_1_tag_v}, {sectored_entries_0_1_tag_v}}; // @[TLB.scala:174:61, :339:29]
wire [3:0][41:0] _GEN_10 = {{sectored_entries_3_1_data_0}, {sectored_entries_2_1_data_0}, {sectored_entries_1_1_data_0}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:174:61, :339:29]
wire [41:0] _entries_WIRE_3 = _GEN_10[memIdx]; // @[package.scala:163:13]
wire [3:0] _GEN_11 = {{sectored_entries_3_1_valid_0}, {sectored_entries_2_1_valid_0}, {sectored_entries_1_1_valid_0}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:174:61, :339:29]
wire [3:0][26:0] _GEN_12 = {{sectored_entries_3_2_tag_vpn}, {sectored_entries_2_2_tag_vpn}, {sectored_entries_1_2_tag_vpn}, {sectored_entries_0_2_tag_vpn}}; // @[TLB.scala:174:61, :339:29]
wire [3:0] _GEN_13 = {{sectored_entries_3_2_tag_v}, {sectored_entries_2_2_tag_v}, {sectored_entries_1_2_tag_v}, {sectored_entries_0_2_tag_v}}; // @[TLB.scala:174:61, :339:29]
wire [3:0][41:0] _GEN_14 = {{sectored_entries_3_2_data_0}, {sectored_entries_2_2_data_0}, {sectored_entries_1_2_data_0}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:174:61, :339:29]
wire [41:0] _entries_WIRE_5 = _GEN_14[memIdx]; // @[package.scala:163:13]
wire [3:0] _GEN_15 = {{sectored_entries_3_2_valid_0}, {sectored_entries_2_2_valid_0}, {sectored_entries_1_2_valid_0}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:174:61, :339:29]
wire [3:0][26:0] _GEN_16 = {{sectored_entries_3_3_tag_vpn}, {sectored_entries_2_3_tag_vpn}, {sectored_entries_1_3_tag_vpn}, {sectored_entries_0_3_tag_vpn}}; // @[TLB.scala:174:61, :339:29]
wire [3:0] _GEN_17 = {{sectored_entries_3_3_tag_v}, {sectored_entries_2_3_tag_v}, {sectored_entries_1_3_tag_v}, {sectored_entries_0_3_tag_v}}; // @[TLB.scala:174:61, :339:29]
wire [3:0][41:0] _GEN_18 = {{sectored_entries_3_3_data_0}, {sectored_entries_2_3_data_0}, {sectored_entries_1_3_data_0}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:174:61, :339:29]
wire [41:0] _entries_WIRE_7 = _GEN_18[memIdx]; // @[package.scala:163:13]
wire [3:0] _GEN_19 = {{sectored_entries_3_3_valid_0}, {sectored_entries_2_3_valid_0}, {sectored_entries_1_3_valid_0}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:174:61, :339:29]
wire [26:0] _GEN_20 = _GEN_4[memIdx] ^ vpn; // @[package.scala:163:13]
wire [26:0] _sector_hits_T; // @[TLB.scala:174:61]
assign _sector_hits_T = _GEN_20; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T; // @[TLB.scala:174:61]
assign _hitsVec_T = _GEN_20; // @[TLB.scala:174:61]
wire [26:0] _sector_hits_T_1 = _sector_hits_T; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_2 = _sector_hits_T_1 == 27'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_3 = ~_GEN_5[memIdx]; // @[package.scala:163:13]
wire _sector_hits_T_4 = _sector_hits_T_2 & _sector_hits_T_3; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_0 = _GEN_7[memIdx] & _sector_hits_T_4; // @[package.scala:163:13]
wire [26:0] _GEN_21 = _GEN_8[memIdx] ^ vpn; // @[package.scala:163:13]
wire [26:0] _sector_hits_T_5; // @[TLB.scala:174:61]
assign _sector_hits_T_5 = _GEN_21; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61]
assign _hitsVec_T_6 = _GEN_21; // @[TLB.scala:174:61]
wire [26:0] _sector_hits_T_6 = _sector_hits_T_5; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_7 = _sector_hits_T_6 == 27'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_8 = ~_GEN_9[memIdx]; // @[package.scala:163:13]
wire _sector_hits_T_9 = _sector_hits_T_7 & _sector_hits_T_8; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_1 = _GEN_11[memIdx] & _sector_hits_T_9; // @[package.scala:163:13]
wire [26:0] _GEN_22 = _GEN_12[memIdx] ^ vpn; // @[package.scala:163:13]
wire [26:0] _sector_hits_T_10; // @[TLB.scala:174:61]
assign _sector_hits_T_10 = _GEN_22; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61]
assign _hitsVec_T_12 = _GEN_22; // @[TLB.scala:174:61]
wire [26:0] _sector_hits_T_11 = _sector_hits_T_10; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_12 = _sector_hits_T_11 == 27'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_13 = ~_GEN_13[memIdx]; // @[package.scala:163:13]
wire _sector_hits_T_14 = _sector_hits_T_12 & _sector_hits_T_13; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_2 = _GEN_15[memIdx] & _sector_hits_T_14; // @[package.scala:163:13]
wire [26:0] _GEN_23 = _GEN_16[memIdx] ^ vpn; // @[package.scala:163:13]
wire [26:0] _sector_hits_T_15; // @[TLB.scala:174:61]
assign _sector_hits_T_15 = _GEN_23; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61]
assign _hitsVec_T_18 = _GEN_23; // @[TLB.scala:174:61]
wire [26:0] _sector_hits_T_16 = _sector_hits_T_15; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_17 = _sector_hits_T_16 == 27'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_18 = ~_GEN_17[memIdx]; // @[package.scala:163:13]
wire _sector_hits_T_19 = _sector_hits_T_17 & _sector_hits_T_18; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_3 = _GEN_19[memIdx] & _sector_hits_T_19; // @[package.scala:163:13]
wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_1876 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52]
assign _superpage_hits_T = _T_1876; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52]
assign _superpage_hits_T_5 = _T_1876; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52]
assign _superpage_hits_T_10 = _T_1876; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_24; // @[TLB.scala:183:52]
assign _hitsVec_T_24 = _T_1876; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_29; // @[TLB.scala:183:52]
assign _hitsVec_T_29 = _T_1876; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_34; // @[TLB.scala:183:52]
assign _hitsVec_T_34 = _T_1876; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14]
wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_24 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_1 = _GEN_24; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_1 = _GEN_24; // @[TLB.scala:182:28]
wire _ppn_ignore_T; // @[TLB.scala:197:28]
assign _ppn_ignore_T = _GEN_24; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_1; // @[TLB.scala:182:28]
assign _ignore_T_1 = _GEN_24; // @[TLB.scala:182:28]
wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14]
wire _superpage_hits_T_8 = superpage_hits_ignore_1 | _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}]
wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14]
wire [26:0] _hitsVec_T_1 = _hitsVec_T; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_2 = _hitsVec_T_1 == 27'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_3 = ~_GEN_5[memIdx]; // @[package.scala:163:13]
wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}]
wire _hitsVec_T_5 = _GEN_7[memIdx] & _hitsVec_T_4; // @[package.scala:163:13]
wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44]
wire [26:0] _hitsVec_T_7 = _hitsVec_T_6; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_8 = _hitsVec_T_7 == 27'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_9 = ~_GEN_9[memIdx]; // @[package.scala:163:13]
wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}]
wire _hitsVec_T_11 = _GEN_11[memIdx] & _hitsVec_T_10; // @[package.scala:163:13]
wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44]
wire [26:0] _hitsVec_T_13 = _hitsVec_T_12; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_14 = _hitsVec_T_13 == 27'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_15 = ~_GEN_13[memIdx]; // @[package.scala:163:13]
wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}]
wire _hitsVec_T_17 = _GEN_15[memIdx] & _hitsVec_T_16; // @[package.scala:163:13]
wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44]
wire [26:0] _hitsVec_T_19 = _hitsVec_T_18; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_20 = _hitsVec_T_19 == 27'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_21 = ~_GEN_17[memIdx]; // @[package.scala:163:13]
wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}]
wire _hitsVec_T_23 = _GEN_19[memIdx] & _hitsVec_T_22; // @[package.scala:163:13]
wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44]
wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_25 = _hitsVec_T_24[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_26 = _hitsVec_T_25 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14]
wire _hitsVec_T_27 = _hitsVec_T_26; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_28 = hitsVec_tagMatch & _hitsVec_T_27; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_30 = _hitsVec_T_29[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_31 = _hitsVec_T_30 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14]
wire _hitsVec_T_32 = hitsVec_ignore_1 | _hitsVec_T_31; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_33 = _hitsVec_T_28 & _hitsVec_T_32; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_38 = _hitsVec_T_33; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_35 = _hitsVec_T_34[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_36 = _hitsVec_T_35 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14]
wire hitsVec_4 = vm_enabled & _hitsVec_T_38; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_1 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56]
wire hitsVec_tagMatch_1 = special_entry_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :346:56]
wire [26:0] _T_1974 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56]
wire [26:0] _hitsVec_T_39; // @[TLB.scala:183:52]
assign _hitsVec_T_39 = _T_1974; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_44; // @[TLB.scala:183:52]
assign _hitsVec_T_44 = _T_1974; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_49; // @[TLB.scala:183:52]
assign _hitsVec_T_49 = _T_1974; // @[TLB.scala:183:52]
wire [8:0] _hitsVec_T_40 = _hitsVec_T_39[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_41 = _hitsVec_T_40 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14]
wire _hitsVec_T_42 = _hitsVec_T_41; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_43 = hitsVec_tagMatch_1 & _hitsVec_T_42; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_45 = _hitsVec_T_44[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_46 = _hitsVec_T_45 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14]
wire _hitsVec_T_47 = hitsVec_ignore_4 | _hitsVec_T_46; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_48 = _hitsVec_T_43 & _hitsVec_T_47; // @[TLB.scala:183:{29,40}]
wire _hitsVec_ignore_T_5 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56]
wire hitsVec_ignore_5 = _hitsVec_ignore_T_5; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_50 = _hitsVec_T_49[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_51 = _hitsVec_T_50 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14]
wire _hitsVec_T_52 = hitsVec_ignore_5 | _hitsVec_T_51; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_53 = _hitsVec_T_48 & _hitsVec_T_52; // @[TLB.scala:183:{29,40}]
wire hitsVec_5 = vm_enabled & _hitsVec_T_53; // @[TLB.scala:183:29, :399:61, :440:44]
wire [1:0] real_hits_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27]
wire [2:0] real_hits_lo = {real_hits_lo_hi, hitsVec_0}; // @[package.scala:45:27]
wire [1:0] real_hits_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27]
wire [2:0] real_hits_hi = {real_hits_hi_hi, hitsVec_3}; // @[package.scala:45:27]
wire [5:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27]
wire [5:0] _tlb_hit_T = real_hits; // @[package.scala:45:27]
wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18]
wire [6:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27]
wire _newEntry_g_T; // @[TLB.scala:453:25]
wire _newEntry_sw_T_6; // @[PTW.scala:151:40]
wire _newEntry_sx_T_5; // @[PTW.scala:153:35]
wire _newEntry_sr_T_5; // @[PTW.scala:149:35]
wire newEntry_g; // @[TLB.scala:449:24]
wire newEntry_sw; // @[TLB.scala:449:24]
wire newEntry_sx; // @[TLB.scala:449:24]
wire newEntry_sr; // @[TLB.scala:449:24]
wire newEntry_ppp; // @[TLB.scala:449:24]
wire newEntry_pal; // @[TLB.scala:449:24]
wire newEntry_paa; // @[TLB.scala:449:24]
wire newEntry_eff; // @[TLB.scala:449:24]
assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25]
assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25]
wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53]
wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7]
wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sr_T_1; // @[TLB.scala:318:7]
wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7]
wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7]
assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24]
wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7]
wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sw_T_1; // @[TLB.scala:318:7]
wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7]
wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7]
assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24]
wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7]
wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sx_T_1; // @[TLB.scala:318:7]
wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7]
wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7]
assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24]
wire [1:0] _GEN_25 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_1_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_2_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_3_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] _GEN_26 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_1_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_2_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_3_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_27 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_1_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_2_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_3_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [1:0] _GEN_28 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_1_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_2_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_3_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_29 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_1_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_2_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_3_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [1:0] _GEN_30 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_1_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_2_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_3_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_31 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_1_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_2_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_3_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [20:0] _GEN_32 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24]
wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_1_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_2_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_3_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24]
wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24]
wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24]
wire [1:0] r_memIdx = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22]
wire [2:0] sectored_entries_0_data_0_lo_lo_hi = {sectored_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_data_0_lo_lo = {sectored_entries_0_data_0_lo_lo_hi, sectored_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_data_0_lo_hi_lo = {sectored_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_data_0_lo_hi_hi = {sectored_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_data_0_lo_hi = {sectored_entries_0_data_0_lo_hi_hi, sectored_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_data_0_lo = {sectored_entries_0_data_0_lo_hi, sectored_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_data_0_hi_lo_lo = {sectored_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_data_0_hi_lo_hi = {sectored_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_data_0_hi_lo = {sectored_entries_0_data_0_hi_lo_hi, sectored_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_data_0_hi_hi_lo = {sectored_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_data_0_hi_hi_hi = {sectored_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_data_0_hi_hi = {sectored_entries_0_data_0_hi_hi_hi, sectored_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_data_0_hi = {sectored_entries_0_data_0_hi_hi, sectored_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_data_0_T = {sectored_entries_0_data_0_hi, sectored_entries_0_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_1_data_0_lo_lo_hi = {sectored_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_1_data_0_lo_lo = {sectored_entries_1_data_0_lo_lo_hi, sectored_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_1_data_0_lo_hi_lo = {sectored_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_1_data_0_lo_hi_hi = {sectored_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_1_data_0_lo_hi = {sectored_entries_1_data_0_lo_hi_hi, sectored_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_1_data_0_lo = {sectored_entries_1_data_0_lo_hi, sectored_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_1_data_0_hi_lo_lo = {sectored_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_1_data_0_hi_lo_hi = {sectored_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_1_data_0_hi_lo = {sectored_entries_1_data_0_hi_lo_hi, sectored_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_1_data_0_hi_hi_lo = {sectored_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_1_data_0_hi_hi_hi = {sectored_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_1_data_0_hi_hi = {sectored_entries_1_data_0_hi_hi_hi, sectored_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_1_data_0_hi = {sectored_entries_1_data_0_hi_hi, sectored_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_1_data_0_T = {sectored_entries_1_data_0_hi, sectored_entries_1_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_2_data_0_lo_lo_hi = {sectored_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_2_data_0_lo_lo = {sectored_entries_2_data_0_lo_lo_hi, sectored_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_2_data_0_lo_hi_lo = {sectored_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_2_data_0_lo_hi_hi = {sectored_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_2_data_0_lo_hi = {sectored_entries_2_data_0_lo_hi_hi, sectored_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_2_data_0_lo = {sectored_entries_2_data_0_lo_hi, sectored_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_2_data_0_hi_lo_lo = {sectored_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_2_data_0_hi_lo_hi = {sectored_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_2_data_0_hi_lo = {sectored_entries_2_data_0_hi_lo_hi, sectored_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_2_data_0_hi_hi_lo = {sectored_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_2_data_0_hi_hi_hi = {sectored_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_2_data_0_hi_hi = {sectored_entries_2_data_0_hi_hi_hi, sectored_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_2_data_0_hi = {sectored_entries_2_data_0_hi_hi, sectored_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_2_data_0_T = {sectored_entries_2_data_0_hi, sectored_entries_2_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_3_data_0_lo_lo_hi = {sectored_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_3_data_0_lo_lo = {sectored_entries_3_data_0_lo_lo_hi, sectored_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_3_data_0_lo_hi_lo = {sectored_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_3_data_0_lo_hi_hi = {sectored_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_3_data_0_lo_hi = {sectored_entries_3_data_0_lo_hi_hi, sectored_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_3_data_0_lo = {sectored_entries_3_data_0_lo_hi, sectored_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_3_data_0_hi_lo_lo = {sectored_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_3_data_0_hi_lo_hi = {sectored_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_3_data_0_hi_lo = {sectored_entries_3_data_0_hi_lo_hi, sectored_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_3_data_0_hi_hi_lo = {sectored_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_3_data_0_hi_hi_hi = {sectored_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_3_data_0_hi_hi = {sectored_entries_3_data_0_hi_hi_hi, sectored_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_3_data_0_hi = {sectored_entries_3_data_0_hi_hi, sectored_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_3_data_0_T = {sectored_entries_3_data_0_hi, sectored_entries_3_data_0_lo}; // @[TLB.scala:217:24]
wire [19:0] _entries_T_22; // @[TLB.scala:170:77]
wire _entries_T_21; // @[TLB.scala:170:77]
wire _entries_T_20; // @[TLB.scala:170:77]
wire _entries_T_19; // @[TLB.scala:170:77]
wire _entries_T_18; // @[TLB.scala:170:77]
wire _entries_T_17; // @[TLB.scala:170:77]
wire _entries_T_16; // @[TLB.scala:170:77]
wire _entries_T_15; // @[TLB.scala:170:77]
wire _entries_T_14; // @[TLB.scala:170:77]
wire _entries_T_13; // @[TLB.scala:170:77]
wire _entries_T_12; // @[TLB.scala:170:77]
wire _entries_T_11; // @[TLB.scala:170:77]
wire _entries_T_10; // @[TLB.scala:170:77]
wire _entries_T_9; // @[TLB.scala:170:77]
wire _entries_T_8; // @[TLB.scala:170:77]
wire _entries_T_7; // @[TLB.scala:170:77]
wire _entries_T_6; // @[TLB.scala:170:77]
wire _entries_T_5; // @[TLB.scala:170:77]
wire _entries_T_4; // @[TLB.scala:170:77]
wire _entries_T_3; // @[TLB.scala:170:77]
wire _entries_T_2; // @[TLB.scala:170:77]
wire _entries_T_1; // @[TLB.scala:170:77]
wire _entries_T; // @[TLB.scala:170:77]
assign _entries_T = _entries_WIRE_1[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_fragmented_superpage = _entries_T; // @[TLB.scala:170:77]
assign _entries_T_1 = _entries_WIRE_1[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_c = _entries_T_1; // @[TLB.scala:170:77]
assign _entries_T_2 = _entries_WIRE_1[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_eff = _entries_T_2; // @[TLB.scala:170:77]
assign _entries_T_3 = _entries_WIRE_1[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_paa = _entries_T_3; // @[TLB.scala:170:77]
assign _entries_T_4 = _entries_WIRE_1[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_pal = _entries_T_4; // @[TLB.scala:170:77]
assign _entries_T_5 = _entries_WIRE_1[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_ppp = _entries_T_5; // @[TLB.scala:170:77]
assign _entries_T_6 = _entries_WIRE_1[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_pr = _entries_T_6; // @[TLB.scala:170:77]
assign _entries_T_7 = _entries_WIRE_1[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_px = _entries_T_7; // @[TLB.scala:170:77]
assign _entries_T_8 = _entries_WIRE_1[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_pw = _entries_T_8; // @[TLB.scala:170:77]
assign _entries_T_9 = _entries_WIRE_1[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_hr = _entries_T_9; // @[TLB.scala:170:77]
assign _entries_T_10 = _entries_WIRE_1[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_hx = _entries_T_10; // @[TLB.scala:170:77]
assign _entries_T_11 = _entries_WIRE_1[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_hw = _entries_T_11; // @[TLB.scala:170:77]
assign _entries_T_12 = _entries_WIRE_1[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_sr = _entries_T_12; // @[TLB.scala:170:77]
assign _entries_T_13 = _entries_WIRE_1[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_sx = _entries_T_13; // @[TLB.scala:170:77]
assign _entries_T_14 = _entries_WIRE_1[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_sw = _entries_T_14; // @[TLB.scala:170:77]
assign _entries_T_15 = _entries_WIRE_1[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_gf = _entries_T_15; // @[TLB.scala:170:77]
assign _entries_T_16 = _entries_WIRE_1[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_pf = _entries_T_16; // @[TLB.scala:170:77]
assign _entries_T_17 = _entries_WIRE_1[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_stage2 = _entries_T_17; // @[TLB.scala:170:77]
assign _entries_T_18 = _entries_WIRE_1[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_final = _entries_T_18; // @[TLB.scala:170:77]
assign _entries_T_19 = _entries_WIRE_1[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_ptw = _entries_T_19; // @[TLB.scala:170:77]
assign _entries_T_20 = _entries_WIRE_1[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_g = _entries_T_20; // @[TLB.scala:170:77]
assign _entries_T_21 = _entries_WIRE_1[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_u = _entries_T_21; // @[TLB.scala:170:77]
assign _entries_T_22 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_ppn = _entries_T_22; // @[TLB.scala:170:77]
wire [19:0] _entries_T_45; // @[TLB.scala:170:77]
wire _entries_T_44; // @[TLB.scala:170:77]
wire _entries_T_43; // @[TLB.scala:170:77]
wire _entries_T_42; // @[TLB.scala:170:77]
wire _entries_T_41; // @[TLB.scala:170:77]
wire _entries_T_40; // @[TLB.scala:170:77]
wire _entries_T_39; // @[TLB.scala:170:77]
wire _entries_T_38; // @[TLB.scala:170:77]
wire _entries_T_37; // @[TLB.scala:170:77]
wire _entries_T_36; // @[TLB.scala:170:77]
wire _entries_T_35; // @[TLB.scala:170:77]
wire _entries_T_34; // @[TLB.scala:170:77]
wire _entries_T_33; // @[TLB.scala:170:77]
wire _entries_T_32; // @[TLB.scala:170:77]
wire _entries_T_31; // @[TLB.scala:170:77]
wire _entries_T_30; // @[TLB.scala:170:77]
wire _entries_T_29; // @[TLB.scala:170:77]
wire _entries_T_28; // @[TLB.scala:170:77]
wire _entries_T_27; // @[TLB.scala:170:77]
wire _entries_T_26; // @[TLB.scala:170:77]
wire _entries_T_25; // @[TLB.scala:170:77]
wire _entries_T_24; // @[TLB.scala:170:77]
wire _entries_T_23; // @[TLB.scala:170:77]
assign _entries_T_23 = _entries_WIRE_3[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_fragmented_superpage = _entries_T_23; // @[TLB.scala:170:77]
assign _entries_T_24 = _entries_WIRE_3[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_c = _entries_T_24; // @[TLB.scala:170:77]
assign _entries_T_25 = _entries_WIRE_3[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_eff = _entries_T_25; // @[TLB.scala:170:77]
assign _entries_T_26 = _entries_WIRE_3[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_paa = _entries_T_26; // @[TLB.scala:170:77]
assign _entries_T_27 = _entries_WIRE_3[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pal = _entries_T_27; // @[TLB.scala:170:77]
assign _entries_T_28 = _entries_WIRE_3[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ppp = _entries_T_28; // @[TLB.scala:170:77]
assign _entries_T_29 = _entries_WIRE_3[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pr = _entries_T_29; // @[TLB.scala:170:77]
assign _entries_T_30 = _entries_WIRE_3[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_px = _entries_T_30; // @[TLB.scala:170:77]
assign _entries_T_31 = _entries_WIRE_3[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pw = _entries_T_31; // @[TLB.scala:170:77]
assign _entries_T_32 = _entries_WIRE_3[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hr = _entries_T_32; // @[TLB.scala:170:77]
assign _entries_T_33 = _entries_WIRE_3[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hx = _entries_T_33; // @[TLB.scala:170:77]
assign _entries_T_34 = _entries_WIRE_3[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hw = _entries_T_34; // @[TLB.scala:170:77]
assign _entries_T_35 = _entries_WIRE_3[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sr = _entries_T_35; // @[TLB.scala:170:77]
assign _entries_T_36 = _entries_WIRE_3[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sx = _entries_T_36; // @[TLB.scala:170:77]
assign _entries_T_37 = _entries_WIRE_3[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sw = _entries_T_37; // @[TLB.scala:170:77]
assign _entries_T_38 = _entries_WIRE_3[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_gf = _entries_T_38; // @[TLB.scala:170:77]
assign _entries_T_39 = _entries_WIRE_3[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pf = _entries_T_39; // @[TLB.scala:170:77]
assign _entries_T_40 = _entries_WIRE_3[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_stage2 = _entries_T_40; // @[TLB.scala:170:77]
assign _entries_T_41 = _entries_WIRE_3[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_final = _entries_T_41; // @[TLB.scala:170:77]
assign _entries_T_42 = _entries_WIRE_3[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_ptw = _entries_T_42; // @[TLB.scala:170:77]
assign _entries_T_43 = _entries_WIRE_3[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_g = _entries_T_43; // @[TLB.scala:170:77]
assign _entries_T_44 = _entries_WIRE_3[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_u = _entries_T_44; // @[TLB.scala:170:77]
assign _entries_T_45 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_2_ppn = _entries_T_45; // @[TLB.scala:170:77]
wire [19:0] _entries_T_68; // @[TLB.scala:170:77]
wire _entries_T_67; // @[TLB.scala:170:77]
wire _entries_T_66; // @[TLB.scala:170:77]
wire _entries_T_65; // @[TLB.scala:170:77]
wire _entries_T_64; // @[TLB.scala:170:77]
wire _entries_T_63; // @[TLB.scala:170:77]
wire _entries_T_62; // @[TLB.scala:170:77]
wire _entries_T_61; // @[TLB.scala:170:77]
wire _entries_T_60; // @[TLB.scala:170:77]
wire _entries_T_59; // @[TLB.scala:170:77]
wire _entries_T_58; // @[TLB.scala:170:77]
wire _entries_T_57; // @[TLB.scala:170:77]
wire _entries_T_56; // @[TLB.scala:170:77]
wire _entries_T_55; // @[TLB.scala:170:77]
wire _entries_T_54; // @[TLB.scala:170:77]
wire _entries_T_53; // @[TLB.scala:170:77]
wire _entries_T_52; // @[TLB.scala:170:77]
wire _entries_T_51; // @[TLB.scala:170:77]
wire _entries_T_50; // @[TLB.scala:170:77]
wire _entries_T_49; // @[TLB.scala:170:77]
wire _entries_T_48; // @[TLB.scala:170:77]
wire _entries_T_47; // @[TLB.scala:170:77]
wire _entries_T_46; // @[TLB.scala:170:77]
assign _entries_T_46 = _entries_WIRE_5[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_fragmented_superpage = _entries_T_46; // @[TLB.scala:170:77]
assign _entries_T_47 = _entries_WIRE_5[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_c = _entries_T_47; // @[TLB.scala:170:77]
assign _entries_T_48 = _entries_WIRE_5[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_eff = _entries_T_48; // @[TLB.scala:170:77]
assign _entries_T_49 = _entries_WIRE_5[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_paa = _entries_T_49; // @[TLB.scala:170:77]
assign _entries_T_50 = _entries_WIRE_5[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pal = _entries_T_50; // @[TLB.scala:170:77]
assign _entries_T_51 = _entries_WIRE_5[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ppp = _entries_T_51; // @[TLB.scala:170:77]
assign _entries_T_52 = _entries_WIRE_5[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pr = _entries_T_52; // @[TLB.scala:170:77]
assign _entries_T_53 = _entries_WIRE_5[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_px = _entries_T_53; // @[TLB.scala:170:77]
assign _entries_T_54 = _entries_WIRE_5[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pw = _entries_T_54; // @[TLB.scala:170:77]
assign _entries_T_55 = _entries_WIRE_5[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hr = _entries_T_55; // @[TLB.scala:170:77]
assign _entries_T_56 = _entries_WIRE_5[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hx = _entries_T_56; // @[TLB.scala:170:77]
assign _entries_T_57 = _entries_WIRE_5[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hw = _entries_T_57; // @[TLB.scala:170:77]
assign _entries_T_58 = _entries_WIRE_5[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sr = _entries_T_58; // @[TLB.scala:170:77]
assign _entries_T_59 = _entries_WIRE_5[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sx = _entries_T_59; // @[TLB.scala:170:77]
assign _entries_T_60 = _entries_WIRE_5[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sw = _entries_T_60; // @[TLB.scala:170:77]
assign _entries_T_61 = _entries_WIRE_5[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_gf = _entries_T_61; // @[TLB.scala:170:77]
assign _entries_T_62 = _entries_WIRE_5[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pf = _entries_T_62; // @[TLB.scala:170:77]
assign _entries_T_63 = _entries_WIRE_5[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_stage2 = _entries_T_63; // @[TLB.scala:170:77]
assign _entries_T_64 = _entries_WIRE_5[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_final = _entries_T_64; // @[TLB.scala:170:77]
assign _entries_T_65 = _entries_WIRE_5[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_ptw = _entries_T_65; // @[TLB.scala:170:77]
assign _entries_T_66 = _entries_WIRE_5[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_g = _entries_T_66; // @[TLB.scala:170:77]
assign _entries_T_67 = _entries_WIRE_5[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_u = _entries_T_67; // @[TLB.scala:170:77]
assign _entries_T_68 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_4_ppn = _entries_T_68; // @[TLB.scala:170:77]
wire [19:0] _entries_T_91; // @[TLB.scala:170:77]
wire _entries_T_90; // @[TLB.scala:170:77]
wire _entries_T_89; // @[TLB.scala:170:77]
wire _entries_T_88; // @[TLB.scala:170:77]
wire _entries_T_87; // @[TLB.scala:170:77]
wire _entries_T_86; // @[TLB.scala:170:77]
wire _entries_T_85; // @[TLB.scala:170:77]
wire _entries_T_84; // @[TLB.scala:170:77]
wire _entries_T_83; // @[TLB.scala:170:77]
wire _entries_T_82; // @[TLB.scala:170:77]
wire _entries_T_81; // @[TLB.scala:170:77]
wire _entries_T_80; // @[TLB.scala:170:77]
wire _entries_T_79; // @[TLB.scala:170:77]
wire _entries_T_78; // @[TLB.scala:170:77]
wire _entries_T_77; // @[TLB.scala:170:77]
wire _entries_T_76; // @[TLB.scala:170:77]
wire _entries_T_75; // @[TLB.scala:170:77]
wire _entries_T_74; // @[TLB.scala:170:77]
wire _entries_T_73; // @[TLB.scala:170:77]
wire _entries_T_72; // @[TLB.scala:170:77]
wire _entries_T_71; // @[TLB.scala:170:77]
wire _entries_T_70; // @[TLB.scala:170:77]
wire _entries_T_69; // @[TLB.scala:170:77]
assign _entries_T_69 = _entries_WIRE_7[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_fragmented_superpage = _entries_T_69; // @[TLB.scala:170:77]
assign _entries_T_70 = _entries_WIRE_7[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_c = _entries_T_70; // @[TLB.scala:170:77]
assign _entries_T_71 = _entries_WIRE_7[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_eff = _entries_T_71; // @[TLB.scala:170:77]
assign _entries_T_72 = _entries_WIRE_7[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_paa = _entries_T_72; // @[TLB.scala:170:77]
assign _entries_T_73 = _entries_WIRE_7[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pal = _entries_T_73; // @[TLB.scala:170:77]
assign _entries_T_74 = _entries_WIRE_7[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ppp = _entries_T_74; // @[TLB.scala:170:77]
assign _entries_T_75 = _entries_WIRE_7[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pr = _entries_T_75; // @[TLB.scala:170:77]
assign _entries_T_76 = _entries_WIRE_7[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_px = _entries_T_76; // @[TLB.scala:170:77]
assign _entries_T_77 = _entries_WIRE_7[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pw = _entries_T_77; // @[TLB.scala:170:77]
assign _entries_T_78 = _entries_WIRE_7[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hr = _entries_T_78; // @[TLB.scala:170:77]
assign _entries_T_79 = _entries_WIRE_7[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hx = _entries_T_79; // @[TLB.scala:170:77]
assign _entries_T_80 = _entries_WIRE_7[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hw = _entries_T_80; // @[TLB.scala:170:77]
assign _entries_T_81 = _entries_WIRE_7[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sr = _entries_T_81; // @[TLB.scala:170:77]
assign _entries_T_82 = _entries_WIRE_7[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sx = _entries_T_82; // @[TLB.scala:170:77]
assign _entries_T_83 = _entries_WIRE_7[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sw = _entries_T_83; // @[TLB.scala:170:77]
assign _entries_T_84 = _entries_WIRE_7[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_gf = _entries_T_84; // @[TLB.scala:170:77]
assign _entries_T_85 = _entries_WIRE_7[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pf = _entries_T_85; // @[TLB.scala:170:77]
assign _entries_T_86 = _entries_WIRE_7[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_stage2 = _entries_T_86; // @[TLB.scala:170:77]
assign _entries_T_87 = _entries_WIRE_7[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_final = _entries_T_87; // @[TLB.scala:170:77]
assign _entries_T_88 = _entries_WIRE_7[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_ptw = _entries_T_88; // @[TLB.scala:170:77]
assign _entries_T_89 = _entries_WIRE_7[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_g = _entries_T_89; // @[TLB.scala:170:77]
assign _entries_T_90 = _entries_WIRE_7[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_u = _entries_T_90; // @[TLB.scala:170:77]
assign _entries_T_91 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_6_ppn = _entries_T_91; // @[TLB.scala:170:77]
wire [19:0] _entries_T_114; // @[TLB.scala:170:77]
wire _entries_T_113; // @[TLB.scala:170:77]
wire _entries_T_112; // @[TLB.scala:170:77]
wire _entries_T_111; // @[TLB.scala:170:77]
wire _entries_T_110; // @[TLB.scala:170:77]
wire _entries_T_109; // @[TLB.scala:170:77]
wire _entries_T_108; // @[TLB.scala:170:77]
wire _entries_T_107; // @[TLB.scala:170:77]
wire _entries_T_106; // @[TLB.scala:170:77]
wire _entries_T_105; // @[TLB.scala:170:77]
wire _entries_T_104; // @[TLB.scala:170:77]
wire _entries_T_103; // @[TLB.scala:170:77]
wire _entries_T_102; // @[TLB.scala:170:77]
wire _entries_T_101; // @[TLB.scala:170:77]
wire _entries_T_100; // @[TLB.scala:170:77]
wire _entries_T_99; // @[TLB.scala:170:77]
wire _entries_T_98; // @[TLB.scala:170:77]
wire _entries_T_97; // @[TLB.scala:170:77]
wire _entries_T_96; // @[TLB.scala:170:77]
wire _entries_T_95; // @[TLB.scala:170:77]
wire _entries_T_94; // @[TLB.scala:170:77]
wire _entries_T_93; // @[TLB.scala:170:77]
wire _entries_T_92; // @[TLB.scala:170:77]
assign _entries_T_92 = _entries_WIRE_9[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_fragmented_superpage = _entries_T_92; // @[TLB.scala:170:77]
assign _entries_T_93 = _entries_WIRE_9[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_c = _entries_T_93; // @[TLB.scala:170:77]
assign _entries_T_94 = _entries_WIRE_9[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_eff = _entries_T_94; // @[TLB.scala:170:77]
assign _entries_T_95 = _entries_WIRE_9[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_paa = _entries_T_95; // @[TLB.scala:170:77]
assign _entries_T_96 = _entries_WIRE_9[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pal = _entries_T_96; // @[TLB.scala:170:77]
assign _entries_T_97 = _entries_WIRE_9[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ppp = _entries_T_97; // @[TLB.scala:170:77]
assign _entries_T_98 = _entries_WIRE_9[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pr = _entries_T_98; // @[TLB.scala:170:77]
assign _entries_T_99 = _entries_WIRE_9[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_px = _entries_T_99; // @[TLB.scala:170:77]
assign _entries_T_100 = _entries_WIRE_9[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pw = _entries_T_100; // @[TLB.scala:170:77]
assign _entries_T_101 = _entries_WIRE_9[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hr = _entries_T_101; // @[TLB.scala:170:77]
assign _entries_T_102 = _entries_WIRE_9[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hx = _entries_T_102; // @[TLB.scala:170:77]
assign _entries_T_103 = _entries_WIRE_9[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hw = _entries_T_103; // @[TLB.scala:170:77]
assign _entries_T_104 = _entries_WIRE_9[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sr = _entries_T_104; // @[TLB.scala:170:77]
assign _entries_T_105 = _entries_WIRE_9[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sx = _entries_T_105; // @[TLB.scala:170:77]
assign _entries_T_106 = _entries_WIRE_9[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sw = _entries_T_106; // @[TLB.scala:170:77]
assign _entries_T_107 = _entries_WIRE_9[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_gf = _entries_T_107; // @[TLB.scala:170:77]
assign _entries_T_108 = _entries_WIRE_9[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pf = _entries_T_108; // @[TLB.scala:170:77]
assign _entries_T_109 = _entries_WIRE_9[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_stage2 = _entries_T_109; // @[TLB.scala:170:77]
assign _entries_T_110 = _entries_WIRE_9[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_final = _entries_T_110; // @[TLB.scala:170:77]
assign _entries_T_111 = _entries_WIRE_9[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_ptw = _entries_T_111; // @[TLB.scala:170:77]
assign _entries_T_112 = _entries_WIRE_9[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_g = _entries_T_112; // @[TLB.scala:170:77]
assign _entries_T_113 = _entries_WIRE_9[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_u = _entries_T_113; // @[TLB.scala:170:77]
assign _entries_T_114 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_8_ppn = _entries_T_114; // @[TLB.scala:170:77]
wire [19:0] _entries_T_137; // @[TLB.scala:170:77]
wire _entries_T_136; // @[TLB.scala:170:77]
wire _entries_T_135; // @[TLB.scala:170:77]
wire _entries_T_134; // @[TLB.scala:170:77]
wire _entries_T_133; // @[TLB.scala:170:77]
wire _entries_T_132; // @[TLB.scala:170:77]
wire _entries_T_131; // @[TLB.scala:170:77]
wire _entries_T_130; // @[TLB.scala:170:77]
wire _entries_T_129; // @[TLB.scala:170:77]
wire _entries_T_128; // @[TLB.scala:170:77]
wire _entries_T_127; // @[TLB.scala:170:77]
wire _entries_T_126; // @[TLB.scala:170:77]
wire _entries_T_125; // @[TLB.scala:170:77]
wire _entries_T_124; // @[TLB.scala:170:77]
wire _entries_T_123; // @[TLB.scala:170:77]
wire _entries_T_122; // @[TLB.scala:170:77]
wire _entries_T_121; // @[TLB.scala:170:77]
wire _entries_T_120; // @[TLB.scala:170:77]
wire _entries_T_119; // @[TLB.scala:170:77]
wire _entries_T_118; // @[TLB.scala:170:77]
wire _entries_T_117; // @[TLB.scala:170:77]
wire _entries_T_116; // @[TLB.scala:170:77]
wire _entries_T_115; // @[TLB.scala:170:77]
assign _entries_T_115 = _entries_WIRE_11[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_fragmented_superpage = _entries_T_115; // @[TLB.scala:170:77]
assign _entries_T_116 = _entries_WIRE_11[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_c = _entries_T_116; // @[TLB.scala:170:77]
assign _entries_T_117 = _entries_WIRE_11[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_eff = _entries_T_117; // @[TLB.scala:170:77]
assign _entries_T_118 = _entries_WIRE_11[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_paa = _entries_T_118; // @[TLB.scala:170:77]
assign _entries_T_119 = _entries_WIRE_11[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pal = _entries_T_119; // @[TLB.scala:170:77]
assign _entries_T_120 = _entries_WIRE_11[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ppp = _entries_T_120; // @[TLB.scala:170:77]
assign _entries_T_121 = _entries_WIRE_11[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pr = _entries_T_121; // @[TLB.scala:170:77]
assign _entries_T_122 = _entries_WIRE_11[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_px = _entries_T_122; // @[TLB.scala:170:77]
assign _entries_T_123 = _entries_WIRE_11[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pw = _entries_T_123; // @[TLB.scala:170:77]
assign _entries_T_124 = _entries_WIRE_11[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hr = _entries_T_124; // @[TLB.scala:170:77]
assign _entries_T_125 = _entries_WIRE_11[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hx = _entries_T_125; // @[TLB.scala:170:77]
assign _entries_T_126 = _entries_WIRE_11[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hw = _entries_T_126; // @[TLB.scala:170:77]
assign _entries_T_127 = _entries_WIRE_11[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sr = _entries_T_127; // @[TLB.scala:170:77]
assign _entries_T_128 = _entries_WIRE_11[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sx = _entries_T_128; // @[TLB.scala:170:77]
assign _entries_T_129 = _entries_WIRE_11[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sw = _entries_T_129; // @[TLB.scala:170:77]
assign _entries_T_130 = _entries_WIRE_11[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_gf = _entries_T_130; // @[TLB.scala:170:77]
assign _entries_T_131 = _entries_WIRE_11[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pf = _entries_T_131; // @[TLB.scala:170:77]
assign _entries_T_132 = _entries_WIRE_11[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_stage2 = _entries_T_132; // @[TLB.scala:170:77]
assign _entries_T_133 = _entries_WIRE_11[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_final = _entries_T_133; // @[TLB.scala:170:77]
assign _entries_T_134 = _entries_WIRE_11[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_ptw = _entries_T_134; // @[TLB.scala:170:77]
assign _entries_T_135 = _entries_WIRE_11[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_g = _entries_T_135; // @[TLB.scala:170:77]
assign _entries_T_136 = _entries_WIRE_11[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_u = _entries_T_136; // @[TLB.scala:170:77]
assign _entries_T_137 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_10_ppn = _entries_T_137; // @[TLB.scala:170:77]
wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30]
wire [1:0] ppn_res = _entries_barrier_4_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] | _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] | _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_1 = _entries_barrier_5_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] | _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_3 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56]
wire ppn_ignore_3 = _ppn_ignore_T_3; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_13 = ppn_ignore_3 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] | _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}]
wire [19:0] _ppn_T_17 = vpn[19:0]; // @[TLB.scala:335:30, :502:125]
wire [19:0] _ppn_T_18 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_19 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_20 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_21 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_22 = hitsVec_4 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_23 = hitsVec_5 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_24 = _ppn_T ? _ppn_T_17 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_25 = _ppn_T_18 | _ppn_T_19; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_26 = _ppn_T_25 | _ppn_T_20; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_27 = _ppn_T_26 | _ppn_T_21; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_28 = _ppn_T_27 | _ppn_T_22; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_29 = _ppn_T_28 | _ppn_T_23; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_30 = _ppn_T_29 | _ppn_T_24; // @[Mux.scala:30:73]
wire [19:0] ppn = _ppn_T_30; // @[Mux.scala:30:73]
wire [1:0] ptw_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [5:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27]
wire [6:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27]
wire [1:0] final_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_lo = {final_ae_array_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_hi = {final_ae_array_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [5:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27]
wire [6:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27]
wire [1:0] ptw_pf_array_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [5:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27]
wire [6:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27]
wire [1:0] ptw_gf_array_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [5:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27]
wire [6:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27]
wire [6:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82]
wire [6:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63]
wire [6:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46]
wire [1:0] _GEN_33 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi = _GEN_33; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_1 = _GEN_33; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_hi = _GEN_33; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_1 = _GEN_33; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_34 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi = _GEN_34; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_1 = _GEN_34; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_hi = _GEN_34; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_1 = _GEN_34; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27]
wire [5:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_2; // @[package.scala:45:27]
wire [5:0] priv_rw_ok = _priv_rw_ok_T_3; // @[TLB.scala:513:{23,70}]
wire [2:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27]
wire [5:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27]
wire [2:0] priv_x_ok_lo = {priv_x_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_x_ok_hi = {priv_x_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27]
wire [5:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27]
wire [2:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27]
wire [5:0] priv_x_ok = _priv_x_ok_T_2; // @[package.scala:45:27]
wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83]
wire [5:0] _stage1_bypass_T_2 = {6{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}]
wire [1:0] stage1_bypass_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_lo = {stage1_bypass_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_hi = {stage1_bypass_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [5:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27]
wire [5:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 | _stage1_bypass_T_3; // @[package.scala:45:27]
wire [1:0] r_array_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_lo = {r_array_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_hi = {r_array_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [5:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_35 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_hi_1; // @[package.scala:45:27]
assign r_array_lo_hi_1 = _GEN_35; // @[package.scala:45:27]
wire [1:0] x_array_lo_hi; // @[package.scala:45:27]
assign x_array_lo_hi = _GEN_35; // @[package.scala:45:27]
wire [2:0] r_array_lo_1 = {r_array_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_36 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_1; // @[package.scala:45:27]
assign r_array_hi_hi_1 = _GEN_36; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi; // @[package.scala:45:27]
assign x_array_hi_hi = _GEN_36; // @[package.scala:45:27]
wire [2:0] r_array_hi_1 = {r_array_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27]
wire [5:0] _r_array_T_2 = mxr ? _r_array_T_1 : 6'h0; // @[package.scala:45:27]
wire [5:0] _r_array_T_3 = _r_array_T | _r_array_T_2; // @[package.scala:45:27]
wire [5:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}]
wire [5:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}]
wire [6:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}]
wire [6:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41]
wire [1:0] w_array_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_lo = {w_array_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_hi = {w_array_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [5:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27]
wire [5:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27]
wire [5:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}]
wire [6:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}]
wire [2:0] x_array_lo = {x_array_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [2:0] x_array_hi = {x_array_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27]
wire [5:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27]
wire [5:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}]
wire [6:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}]
wire [1:0] hr_array_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_lo = {hr_array_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_hi = {hr_array_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [5:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_37 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_hi_1; // @[package.scala:45:27]
assign hr_array_lo_hi_1 = _GEN_37; // @[package.scala:45:27]
wire [1:0] hx_array_lo_hi; // @[package.scala:45:27]
assign hx_array_lo_hi = _GEN_37; // @[package.scala:45:27]
wire [2:0] hr_array_lo_1 = {hr_array_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_38 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_1; // @[package.scala:45:27]
assign hr_array_hi_hi_1 = _GEN_38; // @[package.scala:45:27]
wire [1:0] hx_array_hi_hi; // @[package.scala:45:27]
assign hx_array_hi_hi = _GEN_38; // @[package.scala:45:27]
wire [2:0] hr_array_hi_1 = {hr_array_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27]
wire [5:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 6'h0; // @[package.scala:45:27]
wire [5:0] _hr_array_T_3 = _hr_array_T | _hr_array_T_2; // @[package.scala:45:27]
wire [1:0] hw_array_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_lo = {hw_array_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_hi = {hw_array_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [5:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27]
wire [2:0] hx_array_lo = {hx_array_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [2:0] hx_array_hi = {hx_array_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27]
wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26]
wire [1:0] pr_array_lo = {_entries_barrier_1_io_y_pr, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pr_array_hi_hi = {_entries_barrier_4_io_y_pr, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_hi = {pr_array_hi_hi, _entries_barrier_2_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [4:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27]
wire [6:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27]
wire [6:0] _GEN_39 = ptw_ae_array | final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104]
wire [6:0] _pr_array_T_3; // @[TLB.scala:529:104]
assign _pr_array_T_3 = _GEN_39; // @[TLB.scala:529:104]
wire [6:0] _pw_array_T_3; // @[TLB.scala:531:104]
assign _pw_array_T_3 = _GEN_39; // @[TLB.scala:529:104, :531:104]
wire [6:0] _px_array_T_3; // @[TLB.scala:533:104]
assign _px_array_T_3 = _GEN_39; // @[TLB.scala:529:104, :533:104]
wire [6:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}]
wire [6:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}]
wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26]
wire [1:0] pw_array_lo = {_entries_barrier_1_io_y_pw, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pw_array_hi_hi = {_entries_barrier_4_io_y_pw, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_hi = {pw_array_hi_hi, _entries_barrier_2_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [4:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27]
wire [6:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27]
wire [6:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}]
wire [6:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}]
wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26]
wire [1:0] px_array_lo = {_entries_barrier_1_io_y_px, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] px_array_hi_hi = {_entries_barrier_4_io_y_px, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_hi = {px_array_hi_hi, _entries_barrier_2_io_y_px}; // @[package.scala:45:27, :267:25]
wire [4:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27]
wire [6:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27]
wire [6:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}]
wire [6:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}]
wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27]
wire [1:0] eff_array_lo = {_entries_barrier_1_io_y_eff, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] eff_array_hi_hi = {_entries_barrier_4_io_y_eff, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_hi = {eff_array_hi_hi, _entries_barrier_2_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [4:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27]
wire [6:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27]
wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25]
wire [1:0] _GEN_40 = {_entries_barrier_1_io_y_c, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_lo; // @[package.scala:45:27]
assign c_array_lo = _GEN_40; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo; // @[package.scala:45:27]
assign prefetchable_array_lo = _GEN_40; // @[package.scala:45:27]
wire [1:0] _GEN_41 = {_entries_barrier_4_io_y_c, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_hi_hi; // @[package.scala:45:27]
assign c_array_hi_hi = _GEN_41; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_hi = _GEN_41; // @[package.scala:45:27]
wire [2:0] c_array_hi = {c_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25]
wire [4:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27]
wire [6:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27]
wire [6:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24]
wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27]
wire [1:0] ppp_array_lo = {_entries_barrier_1_io_y_ppp, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] ppp_array_hi_hi = {_entries_barrier_4_io_y_ppp, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_hi = {ppp_array_hi_hi, _entries_barrier_2_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [4:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27]
wire [6:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27]
wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27]
wire [1:0] paa_array_lo = {_entries_barrier_1_io_y_paa, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] paa_array_hi_hi = {_entries_barrier_4_io_y_paa, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_hi = {paa_array_hi_hi, _entries_barrier_2_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [4:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27]
wire [6:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27]
wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27]
wire [1:0] pal_array_lo = {_entries_barrier_1_io_y_pal, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pal_array_hi_hi = {_entries_barrier_4_io_y_pal, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_hi = {pal_array_hi_hi, _entries_barrier_2_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [4:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27]
wire [6:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27]
wire [6:0] ppp_array_if_cached = ppp_array | c_array; // @[TLB.scala:537:20, :539:22, :544:39]
wire [6:0] paa_array_if_cached = paa_array | c_array; // @[TLB.scala:537:20, :541:22, :545:39]
wire [6:0] pal_array_if_cached = pal_array | c_array; // @[TLB.scala:537:20, :543:22, :546:39]
wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65]
wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}]
wire [2:0] prefetchable_array_hi = {prefetchable_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25]
wire [4:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27]
wire [6:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27]
wire [3:0] _misaligned_T = 4'h1 << io_req_bits_size_0; // @[OneHot.scala:58:35]
wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35]
wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[TLB.scala:550:69]
wire [39:0] _misaligned_T_3 = {36'h0, io_req_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[TLB.scala:318:7, :550:{39,69}]
wire misaligned = |_misaligned_T_3; // @[TLB.scala:550:{39,77}]
wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21]
wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43]
wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:550:77, :559:43, :560:51]
wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86]
wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}]
wire _bad_va_T_5 = _bad_va_T_2 | _bad_va_T_4; // @[TLB.scala:560:{51,59,71}]
wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}]
wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}]
wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}]
wire _GEN_42 = io_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47]
wire _cmd_lrsc_T; // @[package.scala:16:47]
assign _cmd_lrsc_T = _GEN_42; // @[package.scala:16:47]
wire _cmd_read_T_2; // @[package.scala:16:47]
assign _cmd_read_T_2 = _GEN_42; // @[package.scala:16:47]
wire _GEN_43 = io_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47]
wire _cmd_lrsc_T_1; // @[package.scala:16:47]
assign _cmd_lrsc_T_1 = _GEN_43; // @[package.scala:16:47]
wire _cmd_read_T_3; // @[package.scala:16:47]
assign _cmd_read_T_3 = _GEN_43; // @[package.scala:16:47]
wire _cmd_write_T_3; // @[Consts.scala:90:66]
assign _cmd_write_T_3 = _GEN_43; // @[package.scala:16:47]
wire _cmd_lrsc_T_2 = _cmd_lrsc_T | _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59]
wire cmd_lrsc = _cmd_lrsc_T_2; // @[package.scala:81:59]
wire _GEN_44 = io_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _cmd_amo_logical_T; // @[package.scala:16:47]
assign _cmd_amo_logical_T = _GEN_44; // @[package.scala:16:47]
wire _cmd_read_T_7; // @[package.scala:16:47]
assign _cmd_read_T_7 = _GEN_44; // @[package.scala:16:47]
wire _cmd_write_T_5; // @[package.scala:16:47]
assign _cmd_write_T_5 = _GEN_44; // @[package.scala:16:47]
wire _GEN_45 = io_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _cmd_amo_logical_T_1; // @[package.scala:16:47]
assign _cmd_amo_logical_T_1 = _GEN_45; // @[package.scala:16:47]
wire _cmd_read_T_8; // @[package.scala:16:47]
assign _cmd_read_T_8 = _GEN_45; // @[package.scala:16:47]
wire _cmd_write_T_6; // @[package.scala:16:47]
assign _cmd_write_T_6 = _GEN_45; // @[package.scala:16:47]
wire _GEN_46 = io_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _cmd_amo_logical_T_2; // @[package.scala:16:47]
assign _cmd_amo_logical_T_2 = _GEN_46; // @[package.scala:16:47]
wire _cmd_read_T_9; // @[package.scala:16:47]
assign _cmd_read_T_9 = _GEN_46; // @[package.scala:16:47]
wire _cmd_write_T_7; // @[package.scala:16:47]
assign _cmd_write_T_7 = _GEN_46; // @[package.scala:16:47]
wire _GEN_47 = io_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _cmd_amo_logical_T_3; // @[package.scala:16:47]
assign _cmd_amo_logical_T_3 = _GEN_47; // @[package.scala:16:47]
wire _cmd_read_T_10; // @[package.scala:16:47]
assign _cmd_read_T_10 = _GEN_47; // @[package.scala:16:47]
wire _cmd_write_T_8; // @[package.scala:16:47]
assign _cmd_write_T_8 = _GEN_47; // @[package.scala:16:47]
wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T | _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 | _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 | _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59]
wire cmd_amo_logical = _cmd_amo_logical_T_6; // @[package.scala:81:59]
wire _GEN_48 = io_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T = _GEN_48; // @[package.scala:16:47]
wire _cmd_read_T_14; // @[package.scala:16:47]
assign _cmd_read_T_14 = _GEN_48; // @[package.scala:16:47]
wire _cmd_write_T_12; // @[package.scala:16:47]
assign _cmd_write_T_12 = _GEN_48; // @[package.scala:16:47]
wire _GEN_49 = io_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_1 = _GEN_49; // @[package.scala:16:47]
wire _cmd_read_T_15; // @[package.scala:16:47]
assign _cmd_read_T_15 = _GEN_49; // @[package.scala:16:47]
wire _cmd_write_T_13; // @[package.scala:16:47]
assign _cmd_write_T_13 = _GEN_49; // @[package.scala:16:47]
wire _GEN_50 = io_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_2 = _GEN_50; // @[package.scala:16:47]
wire _cmd_read_T_16; // @[package.scala:16:47]
assign _cmd_read_T_16 = _GEN_50; // @[package.scala:16:47]
wire _cmd_write_T_14; // @[package.scala:16:47]
assign _cmd_write_T_14 = _GEN_50; // @[package.scala:16:47]
wire _GEN_51 = io_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_3 = _GEN_51; // @[package.scala:16:47]
wire _cmd_read_T_17; // @[package.scala:16:47]
assign _cmd_read_T_17 = _GEN_51; // @[package.scala:16:47]
wire _cmd_write_T_15; // @[package.scala:16:47]
assign _cmd_write_T_15 = _GEN_51; // @[package.scala:16:47]
wire _GEN_52 = io_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_4 = _GEN_52; // @[package.scala:16:47]
wire _cmd_read_T_18; // @[package.scala:16:47]
assign _cmd_read_T_18 = _GEN_52; // @[package.scala:16:47]
wire _cmd_write_T_16; // @[package.scala:16:47]
assign _cmd_write_T_16 = _GEN_52; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T | _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 | _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 | _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 | _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59]
wire cmd_amo_arithmetic = _cmd_amo_arithmetic_T_8; // @[package.scala:81:59]
wire _GEN_53 = io_req_bits_cmd_0 == 5'h11; // @[TLB.scala:318:7, :573:41]
wire cmd_put_partial; // @[TLB.scala:573:41]
assign cmd_put_partial = _GEN_53; // @[TLB.scala:573:41]
wire _cmd_write_T_1; // @[Consts.scala:90:49]
assign _cmd_write_T_1 = _GEN_53; // @[TLB.scala:573:41]
wire _cmd_read_T = io_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47]
wire _GEN_54 = io_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47]
wire _cmd_read_T_1; // @[package.scala:16:47]
assign _cmd_read_T_1 = _GEN_54; // @[package.scala:16:47]
wire _cmd_readx_T; // @[TLB.scala:575:56]
assign _cmd_readx_T = _GEN_54; // @[package.scala:16:47]
wire _cmd_read_T_4 = _cmd_read_T | _cmd_read_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_5 = _cmd_read_T_4 | _cmd_read_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_6 = _cmd_read_T_5 | _cmd_read_T_3; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_11 = _cmd_read_T_7 | _cmd_read_T_8; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_12 = _cmd_read_T_11 | _cmd_read_T_9; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_13 = _cmd_read_T_12 | _cmd_read_T_10; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_19 = _cmd_read_T_14 | _cmd_read_T_15; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_20 = _cmd_read_T_19 | _cmd_read_T_16; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_21 = _cmd_read_T_20 | _cmd_read_T_17; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_22 = _cmd_read_T_21 | _cmd_read_T_18; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_23 = _cmd_read_T_13 | _cmd_read_T_22; // @[package.scala:81:59]
wire cmd_read = _cmd_read_T_6 | _cmd_read_T_23; // @[package.scala:81:59]
wire _cmd_write_T = io_req_bits_cmd_0 == 5'h1; // @[TLB.scala:318:7]
wire _cmd_write_T_2 = _cmd_write_T | _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}]
wire _cmd_write_T_4 = _cmd_write_T_2 | _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}]
wire _cmd_write_T_9 = _cmd_write_T_5 | _cmd_write_T_6; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_10 = _cmd_write_T_9 | _cmd_write_T_7; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_11 = _cmd_write_T_10 | _cmd_write_T_8; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_17 = _cmd_write_T_12 | _cmd_write_T_13; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_18 = _cmd_write_T_17 | _cmd_write_T_14; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_19 = _cmd_write_T_18 | _cmd_write_T_15; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_20 = _cmd_write_T_19 | _cmd_write_T_16; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_21 = _cmd_write_T_11 | _cmd_write_T_20; // @[package.scala:81:59]
wire cmd_write = _cmd_write_T_4 | _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _cmd_write_perms_T = io_req_bits_cmd_0 == 5'h5; // @[package.scala:16:47]
wire _cmd_write_perms_T_1 = io_req_bits_cmd_0 == 5'h17; // @[package.scala:16:47]
wire _cmd_write_perms_T_2 = _cmd_write_perms_T | _cmd_write_perms_T_1; // @[package.scala:16:47, :81:59]
wire cmd_write_perms = cmd_write | _cmd_write_perms_T_2; // @[package.scala:81:59]
wire [6:0] _ae_array_T = misaligned ? eff_array : 7'h0; // @[TLB.scala:535:22, :550:77, :582:8]
wire [6:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19]
wire [6:0] _ae_array_T_2 = cmd_lrsc ? _ae_array_T_1 : 7'h0; // @[TLB.scala:570:33, :583:{8,19}]
wire [6:0] ae_array = _ae_array_T | _ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8]
wire [6:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46]
wire [6:0] _ae_ld_array_T_1 = ae_array | _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}]
wire [6:0] ae_ld_array = cmd_read ? _ae_ld_array_T_1 : 7'h0; // @[TLB.scala:586:{24,44}]
wire [6:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37]
wire [6:0] _ae_st_array_T_1 = ae_array | _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}]
wire [6:0] _ae_st_array_T_2 = cmd_write_perms ? _ae_st_array_T_1 : 7'h0; // @[TLB.scala:577:35, :588:{8,35}]
wire [6:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26]
wire [6:0] _ae_st_array_T_4 = cmd_put_partial ? _ae_st_array_T_3 : 7'h0; // @[TLB.scala:573:41, :589:{8,26}]
wire [6:0] _ae_st_array_T_5 = _ae_st_array_T_2 | _ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8]
wire [6:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26]
wire [6:0] _ae_st_array_T_7 = cmd_amo_logical ? _ae_st_array_T_6 : 7'h0; // @[TLB.scala:571:40, :590:{8,26}]
wire [6:0] _ae_st_array_T_8 = _ae_st_array_T_5 | _ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8]
wire [6:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29]
wire [6:0] _ae_st_array_T_10 = cmd_amo_arithmetic ? _ae_st_array_T_9 : 7'h0; // @[TLB.scala:572:43, :591:{8,29}]
wire [6:0] ae_st_array = _ae_st_array_T_8 | _ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8]
wire [6:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26]
wire [6:0] _must_alloc_array_T_1 = cmd_put_partial ? _must_alloc_array_T : 7'h0; // @[TLB.scala:573:41, :593:{8,26}]
wire [6:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26]
wire [6:0] _must_alloc_array_T_3 = cmd_amo_logical ? _must_alloc_array_T_2 : 7'h0; // @[TLB.scala:571:40, :594:{8,26}]
wire [6:0] _must_alloc_array_T_4 = _must_alloc_array_T_1 | _must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8]
wire [6:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29]
wire [6:0] _must_alloc_array_T_6 = cmd_amo_arithmetic ? _must_alloc_array_T_5 : 7'h0; // @[TLB.scala:572:43, :595:{8,29}]
wire [6:0] _must_alloc_array_T_7 = _must_alloc_array_T_4 | _must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8]
wire [6:0] _must_alloc_array_T_9 = {7{cmd_lrsc}}; // @[TLB.scala:570:33, :596:8]
wire [6:0] must_alloc_array = _must_alloc_array_T_7 | _must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8]
wire [6:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}]
wire [6:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73]
wire [6:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}]
wire [6:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 | ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}]
wire [6:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106]
wire [6:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}]
wire [6:0] pf_ld_array = cmd_read ? _pf_ld_array_T_6 : 7'h0; // @[TLB.scala:597:{24,104}]
wire [6:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44]
wire [6:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55]
wire [6:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}]
wire [6:0] _pf_st_array_T_3 = _pf_st_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}]
wire [6:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88]
wire [6:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}]
wire [6:0] pf_st_array = cmd_write_perms ? _pf_st_array_T_5 : 7'h0; // @[TLB.scala:577:35, :598:{24,86}]
wire [6:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25]
wire [6:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36]
wire [6:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}]
wire [6:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}]
wire [6:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69]
wire [6:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}]
wire [6:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100]
wire [6:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}]
wire [6:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81]
wire [6:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}]
wire [6:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64]
wire [6:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}]
wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73]
wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}]
wire [4:0] _gpa_hits_hit_mask_T_2 = {5{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}]
wire tlb_hit_if_not_gpa_miss = |real_hits; // @[package.scala:45:27]
wire tlb_hit = |_tlb_hit_T; // @[TLB.scala:611:{28,40}]
wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56]
wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}]
wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67]
wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}]
reg [2:0] state_vec_0; // @[Replacement.scala:305:17]
reg [2:0] state_vec_1; // @[Replacement.scala:305:17]
reg [2:0] state_vec_2; // @[Replacement.scala:305:17]
reg [2:0] state_vec_3; // @[Replacement.scala:305:17]
wire [1:0] _GEN_55 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45]
wire [1:0] lo; // @[OneHot.scala:21:45]
assign lo = _GEN_55; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_lo; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_lo = _GEN_55; // @[OneHot.scala:21:45]
wire [1:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18]
wire [1:0] _GEN_56 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45]
wire [1:0] hi; // @[OneHot.scala:21:45]
assign hi = _GEN_56; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_hi; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_hi = _GEN_56; // @[OneHot.scala:21:45]
wire [1:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18]
wire [1:0] state_vec_touch_way_sized = {|hi_1, hi_1[1] | lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_vec_set_left_older_T = state_vec_touch_way_sized[1]; // @[package.scala:163:13]
wire state_vec_set_left_older = ~_state_vec_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire [3:0][2:0] _GEN_57 = {{state_vec_3}, {state_vec_2}, {state_vec_1}, {state_vec_0}}; // @[package.scala:163:13]
wire state_vec_left_subtree_state = _GEN_57[memIdx][1]; // @[package.scala:163:13]
wire r_sectored_repl_addr_left_subtree_state = _GEN_57[memIdx][1]; // @[package.scala:163:13]
wire state_vec_right_subtree_state = _GEN_57[memIdx][0]; // @[package.scala:163:13]
wire r_sectored_repl_addr_right_subtree_state = _GEN_57[memIdx][0]; // @[package.scala:163:13]
wire _state_vec_T = state_vec_touch_way_sized[0]; // @[package.scala:163:13]
wire _state_vec_T_4 = state_vec_touch_way_sized[0]; // @[package.scala:163:13]
wire _state_vec_T_1 = _state_vec_T; // @[package.scala:163:13]
wire _state_vec_T_2 = ~_state_vec_T_1; // @[Replacement.scala:218:{7,17}]
wire _state_vec_T_3 = state_vec_set_left_older ? state_vec_left_subtree_state : _state_vec_T_2; // @[package.scala:163:13]
wire _state_vec_T_5 = _state_vec_T_4; // @[Replacement.scala:207:62, :218:17]
wire _state_vec_T_6 = ~_state_vec_T_5; // @[Replacement.scala:218:{7,17}]
wire _state_vec_T_7 = state_vec_set_left_older ? _state_vec_T_6 : state_vec_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_vec_hi = {state_vec_set_left_older, _state_vec_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_vec_T_8 = {state_vec_hi, _state_vec_T_7}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _multipleHits_T = real_hits[2:0]; // @[package.scala:45:27]
wire _multipleHits_T_1 = _multipleHits_T[0]; // @[Misc.scala:181:37]
wire multipleHits_leftOne = _multipleHits_T_1; // @[Misc.scala:178:18, :181:37]
wire [1:0] _multipleHits_T_2 = _multipleHits_T[2:1]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_3 = _multipleHits_T_2[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_1 = _multipleHits_T_3; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_4 = _multipleHits_T_2[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne = _multipleHits_T_4; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_1 = multipleHits_leftOne_1 | multipleHits_rightOne; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_6 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo = _multipleHits_T_6; // @[Misc.scala:183:{49,61}]
wire _multipleHits_T_7 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}]
wire multipleHits_leftOne_2 = multipleHits_leftOne | multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_8 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}]
wire multipleHits_leftTwo = _multipleHits_T_7 | _multipleHits_T_8; // @[Misc.scala:183:{37,49,61}]
wire [2:0] _multipleHits_T_9 = real_hits[5:3]; // @[package.scala:45:27]
wire _multipleHits_T_10 = _multipleHits_T_9[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_3 = _multipleHits_T_10; // @[Misc.scala:178:18, :181:37]
wire [1:0] _multipleHits_T_11 = _multipleHits_T_9[2:1]; // @[Misc.scala:182:39]
wire _multipleHits_T_12 = _multipleHits_T_11[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_4 = _multipleHits_T_12; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_13 = _multipleHits_T_11[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne_2 = _multipleHits_T_13; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_3 = multipleHits_leftOne_4 | multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_15 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo_1 = _multipleHits_T_15; // @[Misc.scala:183:{49,61}]
wire _multipleHits_T_16 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}]
wire multipleHits_rightOne_4 = multipleHits_leftOne_3 | multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_17 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}]
wire multipleHits_rightTwo_2 = _multipleHits_T_16 | _multipleHits_T_17; // @[Misc.scala:183:{37,49,61}]
wire _multipleHits_T_18 = multipleHits_leftOne_2 | multipleHits_rightOne_4; // @[Misc.scala:183:16]
wire _multipleHits_T_19 = multipleHits_leftTwo | multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}]
wire multipleHits = _multipleHits_T_19 | _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}]
assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25]
assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25]
wire _io_resp_pf_ld_T = bad_va & cmd_read; // @[TLB.scala:568:34, :633:28]
wire [6:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57]
wire _io_resp_pf_ld_T_2 = |_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}]
assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T | _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}]
assign io_resp_pf_ld = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41]
wire _io_resp_pf_st_T = bad_va & cmd_write_perms; // @[TLB.scala:568:34, :577:35, :634:28]
wire [6:0] _io_resp_pf_st_T_1 = pf_st_array & hits; // @[TLB.scala:442:17, :598:24, :634:64]
wire _io_resp_pf_st_T_2 = |_io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}]
assign _io_resp_pf_st_T_3 = _io_resp_pf_st_T | _io_resp_pf_st_T_2; // @[TLB.scala:634:{28,48,72}]
assign io_resp_pf_st = _io_resp_pf_st_T_3; // @[TLB.scala:318:7, :634:48]
wire [6:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47]
wire _io_resp_pf_inst_T_1 = |_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}]
assign _io_resp_pf_inst_T_2 = bad_va | _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}]
assign io_resp_pf_inst = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29]
wire [6:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33]
assign _io_resp_ae_ld_T_1 = |_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}]
assign io_resp_ae_ld = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41]
wire [6:0] _io_resp_ae_st_T = ae_st_array & hits; // @[TLB.scala:442:17, :590:53, :642:33]
assign _io_resp_ae_st_T_1 = |_io_resp_ae_st_T; // @[TLB.scala:642:{33,41}]
assign io_resp_ae_st = _io_resp_ae_st_T_1; // @[TLB.scala:318:7, :642:41]
wire [6:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23]
wire [6:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}]
assign _io_resp_ae_inst_T_2 = |_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}]
assign io_resp_ae_inst = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41]
assign _io_resp_ma_ld_T = misaligned & cmd_read; // @[TLB.scala:550:77, :645:31]
assign io_resp_ma_ld = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31]
assign _io_resp_ma_st_T = misaligned & cmd_write; // @[TLB.scala:550:77, :646:31]
assign io_resp_ma_st = _io_resp_ma_st_T; // @[TLB.scala:318:7, :646:31]
wire [6:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33]
assign _io_resp_cacheable_T_1 = |_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}]
assign io_resp_cacheable = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41]
wire [6:0] _io_resp_must_alloc_T = must_alloc_array & hits; // @[TLB.scala:442:17, :595:46, :649:43]
assign _io_resp_must_alloc_T_1 = |_io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}]
assign io_resp_must_alloc = _io_resp_must_alloc_T_1; // @[TLB.scala:318:7, :649:51]
wire [6:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47]
wire _io_resp_prefetchable_T_1 = |_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}]
assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}]
assign io_resp_prefetchable = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59]
wire _io_resp_miss_T_1 = _io_resp_miss_T | tlb_miss; // @[TLB.scala:613:64, :651:{29,52}]
assign _io_resp_miss_T_2 = _io_resp_miss_T_1 | multipleHits; // @[Misc.scala:183:49]
assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64]
assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73]
assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23]
wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36]
wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}]
wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58]
wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47]
wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}]
assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8]
assign io_resp_gpa = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8]
assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29]
wire _r_superpage_repl_addr_T_1 = ~superpage_entries_0_valid_0; // @[TLB.scala:341:30, :757:43]
wire _r_superpage_repl_addr_T_2 = _r_superpage_repl_addr_T_1; // @[OneHot.scala:48:45]
wire r_sectored_repl_addr_left_subtree_older = _GEN_57[memIdx][2]; // @[package.scala:163:13]
wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state; // @[package.scala:163:13]
wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12]
wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] r_sectored_repl_addr_valids_lo = {_GEN_11[memIdx], _GEN_7[memIdx]}; // @[package.scala:45:27, :163:13]
wire [1:0] r_sectored_repl_addr_valids_hi = {_GEN_19[memIdx], _GEN_15[memIdx]}; // @[package.scala:45:27, :163:13]
wire [3:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27]
wire _r_sectored_repl_addr_T_4 = &r_sectored_repl_addr_valids; // @[package.scala:45:27]
wire [3:0] _r_sectored_repl_addr_T_5 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27]
wire _r_sectored_repl_addr_T_6 = _r_sectored_repl_addr_T_5[0]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_7 = _r_sectored_repl_addr_T_5[1]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_8 = _r_sectored_repl_addr_T_5[2]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_9 = _r_sectored_repl_addr_T_5[3]; // @[OneHot.scala:48:45]
wire [1:0] _r_sectored_repl_addr_T_10 = {1'h1, ~_r_sectored_repl_addr_T_8}; // @[OneHot.scala:48:45]
wire [1:0] _r_sectored_repl_addr_T_11 = _r_sectored_repl_addr_T_7 ? 2'h1 : _r_sectored_repl_addr_T_10; // @[OneHot.scala:48:45]
wire [1:0] _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_6 ? 2'h0 : _r_sectored_repl_addr_T_11; // @[OneHot.scala:48:45]
wire [1:0] _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_4 ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_12; // @[Mux.scala:50:70]
wire _r_sectored_hit_valid_T = sector_hits_0 | sector_hits_1; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T | sector_hits_2; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 | sector_hits_3; // @[package.scala:81:59]
wire [3:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18]
wire [1:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18]
wire _r_sectored_hit_bits_T_1 = |r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 | r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _r_sectored_hit_bits_T_3 = _r_sectored_hit_bits_T_2[1]; // @[OneHot.scala:32:28]
wire [1:0] _r_sectored_hit_bits_T_4 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}]
wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45]
wire _tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30]
wire tagMatch = superpage_entries_0_valid_0 & _tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30]
wire ignore_1 = _ignore_T_1; // @[TLB.scala:182:{28,34}]
wire _ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30]
wire _tagMatch_T_1 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56]
wire tagMatch_1 = special_entry_valid_0 & _tagMatch_T_1; // @[TLB.scala:178:{33,43}, :346:56]
wire ignore_4 = _ignore_T_4; // @[TLB.scala:182:{28,34}]
wire _ignore_T_5 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56]
wire ignore_5 = _ignore_T_5; // @[TLB.scala:182:{28,34}]
wire _T_12 = io_req_valid_0 & vm_enabled; // @[TLB.scala:318:7, :399:61, :617:22]
wire _T_15 = sector_hits_0 | sector_hits_1 | sector_hits_2 | sector_hits_3; // @[package.scala:81:59]
wire _GEN_58 = do_refill & ~io_ptw_resp_bits_homogeneous_0; // @[TLB.scala:211:18, :318:7, :346:56, :408:29, :446:20, :474:{39,70}]
wire _GEN_59 = ~do_refill | ~io_ptw_resp_bits_homogeneous_0 | io_ptw_resp_bits_level_0[1]; // @[TLB.scala:318:7, :341:30, :408:29, :446:20, :474:70, :476:{40,58}]
wire _T_4 = waddr_1 == 2'h0; // @[TLB.scala:485:22, :486:75]
wire _GEN_60 = r_memIdx == 2'h0; // @[package.scala:163:13]
wire _GEN_61 = r_memIdx == 2'h1; // @[package.scala:163:13]
wire _GEN_62 = r_memIdx == 2'h2; // @[package.scala:163:13]
wire _GEN_63 = ~io_ptw_resp_bits_homogeneous_0 | ~(io_ptw_resp_bits_level_0[1]); // @[TLB.scala:318:7, :339:29, :474:{39,70}, :476:{40,58}, :486:84]
wire _GEN_64 = ~do_refill | _GEN_63 | ~(_T_4 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}]
wire _GEN_65 = ~do_refill | _GEN_63 | ~(_T_4 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}]
wire _GEN_66 = ~do_refill | _GEN_63 | ~(_T_4 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}]
wire _GEN_67 = ~do_refill | _GEN_63 | ~(_T_4 & (&r_memIdx)); // @[package.scala:163:13]
wire _GEN_68 = invalidate_refill & _GEN_60; // @[TLB.scala:216:16, :220:46, :410:88, :489:34]
wire _GEN_69 = ~do_refill | _GEN_63 | ~_T_4; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}]
wire _GEN_70 = invalidate_refill & _GEN_61; // @[TLB.scala:216:16, :220:46, :410:88, :489:34]
wire _GEN_71 = invalidate_refill & _GEN_62; // @[TLB.scala:216:16, :220:46, :410:88, :489:34]
wire _GEN_72 = invalidate_refill & (&r_memIdx); // @[package.scala:163:13]
wire _T_6 = waddr_1 == 2'h1; // @[TLB.scala:197:28, :485:22, :486:75]
wire _GEN_73 = ~do_refill | _GEN_63 | ~(_T_6 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}]
wire _GEN_74 = ~do_refill | _GEN_63 | ~(_T_6 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}]
wire _GEN_75 = ~do_refill | _GEN_63 | ~(_T_6 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}]
wire _GEN_76 = ~do_refill | _GEN_63 | ~(_T_6 & (&r_memIdx)); // @[package.scala:163:13]
wire _GEN_77 = ~do_refill | _GEN_63 | ~_T_6; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}]
wire _T_8 = waddr_1 == 2'h2; // @[TLB.scala:485:22, :486:75]
wire _GEN_78 = ~do_refill | _GEN_63 | ~(_T_8 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}]
wire _GEN_79 = ~do_refill | _GEN_63 | ~(_T_8 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}]
wire _GEN_80 = ~do_refill | _GEN_63 | ~(_T_8 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}]
wire _GEN_81 = ~do_refill | _GEN_63 | ~(_T_8 & (&r_memIdx)); // @[package.scala:163:13]
wire _GEN_82 = ~do_refill | _GEN_63 | ~_T_8; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}]
wire _GEN_83 = ~do_refill | _GEN_63 | ~((&waddr_1) & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}]
wire _GEN_84 = ~do_refill | _GEN_63 | ~((&waddr_1) & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}]
wire _GEN_85 = ~do_refill | _GEN_63 | ~((&waddr_1) & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}]
wire _GEN_86 = ~do_refill | _GEN_63 | ~((&waddr_1) & (&r_memIdx)); // @[package.scala:163:13]
wire _GEN_87 = ~do_refill | _GEN_63 | ~(&waddr_1); // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}]
wire _T_2491 = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35]
wire _T_24 = io_req_ready_0 & io_req_valid_0 & tlb_miss; // @[Decoupled.scala:51:35]
wire _T_2490 = multipleHits | reset; // @[Misc.scala:183:49]
always @(posedge clock) begin // @[TLB.scala:318:7]
if (_GEN_64) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_0_0_level <= 2'h0; // @[TLB.scala:339:29]
sectored_entries_0_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25]
end
sectored_entries_0_0_tag_v <= _GEN_64 & sectored_entries_0_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
if (_GEN_64) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_0_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29]
sectored_entries_0_0_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_0_0_tag_v) & (_GEN_69 ? sectored_entries_0_0_valid_0 : ~_GEN_68 & (_GEN_60 | ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}]
if (_GEN_73) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_0_1_level <= 2'h0; // @[TLB.scala:339:29]
sectored_entries_0_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25]
end
sectored_entries_0_1_tag_v <= _GEN_73 & sectored_entries_0_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
if (_GEN_73) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_0_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29]
sectored_entries_0_1_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_0_1_tag_v) & (_GEN_77 ? sectored_entries_0_1_valid_0 : ~_GEN_68 & (_GEN_60 | ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}]
if (_GEN_78) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_0_2_level <= 2'h0; // @[TLB.scala:339:29]
sectored_entries_0_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25]
end
sectored_entries_0_2_tag_v <= _GEN_78 & sectored_entries_0_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
if (_GEN_78) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_0_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29]
sectored_entries_0_2_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_0_2_tag_v) & (_GEN_82 ? sectored_entries_0_2_valid_0 : ~_GEN_68 & (_GEN_60 | ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}]
if (_GEN_83) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_0_3_level <= 2'h0; // @[TLB.scala:339:29]
sectored_entries_0_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25]
end
sectored_entries_0_3_tag_v <= _GEN_83 & sectored_entries_0_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
if (_GEN_83) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_0_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29]
sectored_entries_0_3_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_0_3_tag_v) & (_GEN_87 ? sectored_entries_0_3_valid_0 : ~_GEN_68 & (_GEN_60 | ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}]
if (_GEN_65) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_1_0_level <= 2'h0; // @[TLB.scala:339:29]
sectored_entries_1_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25]
end
sectored_entries_1_0_tag_v <= _GEN_65 & sectored_entries_1_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
if (_GEN_65) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_1_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29]
sectored_entries_1_0_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_1_0_tag_v) & (_GEN_69 ? sectored_entries_1_0_valid_0 : ~_GEN_70 & (_GEN_61 | ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}]
if (_GEN_74) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_1_1_level <= 2'h0; // @[TLB.scala:339:29]
sectored_entries_1_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25]
end
sectored_entries_1_1_tag_v <= _GEN_74 & sectored_entries_1_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
if (_GEN_74) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_1_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29]
sectored_entries_1_1_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_1_1_tag_v) & (_GEN_77 ? sectored_entries_1_1_valid_0 : ~_GEN_70 & (_GEN_61 | ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}]
if (_GEN_79) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_1_2_level <= 2'h0; // @[TLB.scala:339:29]
sectored_entries_1_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25]
end
sectored_entries_1_2_tag_v <= _GEN_79 & sectored_entries_1_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
if (_GEN_79) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_1_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29]
sectored_entries_1_2_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_1_2_tag_v) & (_GEN_82 ? sectored_entries_1_2_valid_0 : ~_GEN_70 & (_GEN_61 | ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}]
if (_GEN_84) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_1_3_level <= 2'h0; // @[TLB.scala:339:29]
sectored_entries_1_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25]
end
sectored_entries_1_3_tag_v <= _GEN_84 & sectored_entries_1_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
if (_GEN_84) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_1_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29]
sectored_entries_1_3_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_1_3_tag_v) & (_GEN_87 ? sectored_entries_1_3_valid_0 : ~_GEN_70 & (_GEN_61 | ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}]
if (_GEN_66) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_2_0_level <= 2'h0; // @[TLB.scala:339:29]
sectored_entries_2_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25]
end
sectored_entries_2_0_tag_v <= _GEN_66 & sectored_entries_2_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
if (_GEN_66) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_2_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29]
sectored_entries_2_0_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_2_0_tag_v) & (_GEN_69 ? sectored_entries_2_0_valid_0 : ~_GEN_71 & (_GEN_62 | ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}]
if (_GEN_75) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_2_1_level <= 2'h0; // @[TLB.scala:339:29]
sectored_entries_2_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25]
end
sectored_entries_2_1_tag_v <= _GEN_75 & sectored_entries_2_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
if (_GEN_75) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_2_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29]
sectored_entries_2_1_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_2_1_tag_v) & (_GEN_77 ? sectored_entries_2_1_valid_0 : ~_GEN_71 & (_GEN_62 | ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}]
if (_GEN_80) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_2_2_level <= 2'h0; // @[TLB.scala:339:29]
sectored_entries_2_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25]
end
sectored_entries_2_2_tag_v <= _GEN_80 & sectored_entries_2_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
if (_GEN_80) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_2_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29]
sectored_entries_2_2_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_2_2_tag_v) & (_GEN_82 ? sectored_entries_2_2_valid_0 : ~_GEN_71 & (_GEN_62 | ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}]
if (_GEN_85) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_2_3_level <= 2'h0; // @[TLB.scala:339:29]
sectored_entries_2_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25]
end
sectored_entries_2_3_tag_v <= _GEN_85 & sectored_entries_2_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
if (_GEN_85) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_2_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29]
sectored_entries_2_3_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_2_3_tag_v) & (_GEN_87 ? sectored_entries_2_3_valid_0 : ~_GEN_71 & (_GEN_62 | ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}]
if (_GEN_67) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_3_0_level <= 2'h0; // @[TLB.scala:339:29]
sectored_entries_3_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25]
end
sectored_entries_3_0_tag_v <= _GEN_67 & sectored_entries_3_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
if (_GEN_67) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_3_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29]
sectored_entries_3_0_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_3_0_tag_v) & (_GEN_69 ? sectored_entries_3_0_valid_0 : ~_GEN_72 & ((&r_memIdx) | ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_0_valid_0)); // @[package.scala:163:13]
if (_GEN_76) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_3_1_level <= 2'h0; // @[TLB.scala:339:29]
sectored_entries_3_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25]
end
sectored_entries_3_1_tag_v <= _GEN_76 & sectored_entries_3_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
if (_GEN_76) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_3_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29]
sectored_entries_3_1_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_3_1_tag_v) & (_GEN_77 ? sectored_entries_3_1_valid_0 : ~_GEN_72 & ((&r_memIdx) | ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_1_valid_0)); // @[package.scala:163:13]
if (_GEN_81) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_3_2_level <= 2'h0; // @[TLB.scala:339:29]
sectored_entries_3_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25]
end
sectored_entries_3_2_tag_v <= _GEN_81 & sectored_entries_3_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
if (_GEN_81) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_3_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29]
sectored_entries_3_2_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_3_2_tag_v) & (_GEN_82 ? sectored_entries_3_2_valid_0 : ~_GEN_72 & ((&r_memIdx) | ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_2_valid_0)); // @[package.scala:163:13]
if (_GEN_86) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_3_3_level <= 2'h0; // @[TLB.scala:339:29]
sectored_entries_3_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25]
end
sectored_entries_3_3_tag_v <= _GEN_86 & sectored_entries_3_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
if (_GEN_86) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
end
else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84]
sectored_entries_3_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29]
sectored_entries_3_3_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_3_3_tag_v) & (_GEN_87 ? sectored_entries_3_3_valid_0 : ~_GEN_72 & ((&r_memIdx) | ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_3_valid_0)); // @[package.scala:163:13]
if (_GEN_59) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58]
end
else begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58]
superpage_entries_0_level <= {1'h0, _superpage_entries_0_level_T}; // @[package.scala:163:13]
superpage_entries_0_tag_vpn <= r_refill_tag; // @[TLB.scala:341:30, :354:25]
end
superpage_entries_0_tag_v <= _GEN_59 & superpage_entries_0_tag_v; // @[TLB.scala:341:30, :446:20, :474:70, :476:58]
if (_GEN_59) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58]
end
else // @[TLB.scala:341:30, :446:20, :474:70, :476:58]
superpage_entries_0_data_0 <= _superpage_entries_0_data_0_T; // @[TLB.scala:217:24, :341:30]
superpage_entries_0_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~superpage_entries_0_tag_v) & (_GEN_59 ? superpage_entries_0_valid_0 : ~invalidate_refill); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :341:30, :410:88, :446:20, :474:70, :476:58, :480:34, :718:19, :723:42, :728:46, :732:{24,41}]
if (_GEN_58) begin // @[TLB.scala:211:18, :346:56, :446:20, :474:70]
special_entry_level <= _special_entry_level_T; // @[package.scala:163:13]
special_entry_tag_vpn <= r_refill_tag; // @[TLB.scala:346:56, :354:25]
special_entry_data_0 <= _special_entry_data_0_T; // @[TLB.scala:217:24, :346:56]
end
special_entry_tag_v <= ~_GEN_58 & special_entry_tag_v; // @[TLB.scala:211:18, :212:16, :346:56, :446:20, :474:70]
special_entry_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~special_entry_tag_v) & (_GEN_58 | special_entry_valid_0); // @[TLB.scala:211:18, :216:16, :220:46, :223:{19,32,36}, :318:7, :346:56, :446:20, :474:70, :718:19, :723:42, :728:46, :732:{24,41}]
if (_T_24) begin // @[Decoupled.scala:51:35]
r_refill_tag <= vpn; // @[TLB.scala:335:30, :354:25]
r_sectored_repl_addr <= _r_sectored_repl_addr_T_13; // @[TLB.scala:356:33, :757:8]
r_sectored_hit_valid <= _r_sectored_hit_valid_T_2; // @[package.scala:81:59]
r_sectored_hit_bits <= _r_sectored_hit_bits_T_4; // @[OneHot.scala:32:10]
r_superpage_hit_valid <= superpage_hits_0; // @[TLB.scala:183:29, :358:28]
r_need_gpa <= tlb_hit_if_not_gpa_miss; // @[TLB.scala:361:23, :610:43]
end
r_gpa_valid <= ~_T_2491 & (do_refill ? io_ptw_resp_bits_gpa_valid_0 : r_gpa_valid); // @[Decoupled.scala:51:35]
if (do_refill) begin // @[TLB.scala:408:29]
r_gpa <= io_ptw_resp_bits_gpa_bits_0; // @[TLB.scala:318:7, :363:18]
r_gpa_is_pte <= io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :365:25]
end
if (_T_2491) // @[Decoupled.scala:51:35]
r_gpa_vpn <= r_refill_tag; // @[TLB.scala:354:25, :364:22]
if (reset) begin // @[TLB.scala:318:7]
state <= 2'h0; // @[TLB.scala:352:22]
state_vec_0 <= 3'h0; // @[Replacement.scala:305:17]
state_vec_1 <= 3'h0; // @[Replacement.scala:305:17]
state_vec_2 <= 3'h0; // @[Replacement.scala:305:17]
state_vec_3 <= 3'h0; // @[Replacement.scala:305:17]
end
else begin // @[TLB.scala:318:7]
if (io_ptw_resp_valid_0) // @[TLB.scala:318:7]
state <= 2'h0; // @[TLB.scala:352:22]
else if (state == 2'h2 & io_sfence_valid_0) // @[TLB.scala:318:7, :352:22, :709:{17,28}]
state <= 2'h3; // @[TLB.scala:352:22]
else if (_T_25) begin // @[package.scala:16:47]
if (io_ptw_req_ready_0) // @[TLB.scala:318:7]
state <= _state_T; // @[TLB.scala:352:22, :704:45]
else if (io_sfence_valid_0) // @[TLB.scala:318:7]
state <= 2'h0; // @[TLB.scala:352:22]
else if (_T_24) // @[Decoupled.scala:51:35]
state <= 2'h1; // @[TLB.scala:197:28, :352:22]
end
else if (_T_24) // @[Decoupled.scala:51:35]
state <= 2'h1; // @[TLB.scala:197:28, :352:22]
if (_T_12 & _T_15 & memIdx == 2'h0) // @[package.scala:81:59, :163:13]
state_vec_0 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17]
if (_T_12 & _T_15 & memIdx == 2'h1) // @[package.scala:81:59, :163:13]
state_vec_1 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17]
if (_T_12 & _T_15 & memIdx == 2'h2) // @[package.scala:81:59, :163:13]
state_vec_2 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17]
if (_T_12 & _T_15 & (&memIdx)) // @[package.scala:81:59, :163:13]
state_vec_3 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17]
end
always @(posedge)
OptimizationBarrier_TLBEntryData_77 mpu_ppn_barrier ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_mpu_ppn_WIRE_ppn), // @[TLB.scala:170:77]
.io_x_u (_mpu_ppn_WIRE_u), // @[TLB.scala:170:77]
.io_x_g (_mpu_ppn_WIRE_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_mpu_ppn_WIRE_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_mpu_ppn_WIRE_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_mpu_ppn_WIRE_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_mpu_ppn_WIRE_pf), // @[TLB.scala:170:77]
.io_x_gf (_mpu_ppn_WIRE_gf), // @[TLB.scala:170:77]
.io_x_sw (_mpu_ppn_WIRE_sw), // @[TLB.scala:170:77]
.io_x_sx (_mpu_ppn_WIRE_sx), // @[TLB.scala:170:77]
.io_x_sr (_mpu_ppn_WIRE_sr), // @[TLB.scala:170:77]
.io_x_hw (_mpu_ppn_WIRE_hw), // @[TLB.scala:170:77]
.io_x_hx (_mpu_ppn_WIRE_hx), // @[TLB.scala:170:77]
.io_x_hr (_mpu_ppn_WIRE_hr), // @[TLB.scala:170:77]
.io_x_pw (_mpu_ppn_WIRE_pw), // @[TLB.scala:170:77]
.io_x_px (_mpu_ppn_WIRE_px), // @[TLB.scala:170:77]
.io_x_pr (_mpu_ppn_WIRE_pr), // @[TLB.scala:170:77]
.io_x_ppp (_mpu_ppn_WIRE_ppp), // @[TLB.scala:170:77]
.io_x_pal (_mpu_ppn_WIRE_pal), // @[TLB.scala:170:77]
.io_x_paa (_mpu_ppn_WIRE_paa), // @[TLB.scala:170:77]
.io_x_eff (_mpu_ppn_WIRE_eff), // @[TLB.scala:170:77]
.io_x_c (_mpu_ppn_WIRE_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_mpu_ppn_WIRE_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_ppn (_mpu_ppn_barrier_io_y_ppn)
); // @[package.scala:267:25]
PMPChecker_s3_9 pmp ( // @[TLB.scala:416:19]
.clock (clock),
.reset (reset),
.io_prv (mpu_priv[1:0]), // @[TLB.scala:415:27, :420:14]
.io_pmp_0_cfg_l (io_ptw_pmp_0_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_0_cfg_a (io_ptw_pmp_0_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_0_cfg_x (io_ptw_pmp_0_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_0_cfg_w (io_ptw_pmp_0_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_0_cfg_r (io_ptw_pmp_0_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_0_addr (io_ptw_pmp_0_addr_0), // @[TLB.scala:318:7]
.io_pmp_0_mask (io_ptw_pmp_0_mask_0), // @[TLB.scala:318:7]
.io_pmp_1_cfg_l (io_ptw_pmp_1_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_1_cfg_a (io_ptw_pmp_1_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_1_cfg_x (io_ptw_pmp_1_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_1_cfg_w (io_ptw_pmp_1_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_1_cfg_r (io_ptw_pmp_1_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_1_addr (io_ptw_pmp_1_addr_0), // @[TLB.scala:318:7]
.io_pmp_1_mask (io_ptw_pmp_1_mask_0), // @[TLB.scala:318:7]
.io_pmp_2_cfg_l (io_ptw_pmp_2_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_2_cfg_a (io_ptw_pmp_2_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_2_cfg_x (io_ptw_pmp_2_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_2_cfg_w (io_ptw_pmp_2_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_2_cfg_r (io_ptw_pmp_2_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_2_addr (io_ptw_pmp_2_addr_0), // @[TLB.scala:318:7]
.io_pmp_2_mask (io_ptw_pmp_2_mask_0), // @[TLB.scala:318:7]
.io_pmp_3_cfg_l (io_ptw_pmp_3_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_3_cfg_a (io_ptw_pmp_3_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_3_cfg_x (io_ptw_pmp_3_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_3_cfg_w (io_ptw_pmp_3_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_3_cfg_r (io_ptw_pmp_3_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_3_addr (io_ptw_pmp_3_addr_0), // @[TLB.scala:318:7]
.io_pmp_3_mask (io_ptw_pmp_3_mask_0), // @[TLB.scala:318:7]
.io_pmp_4_cfg_l (io_ptw_pmp_4_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_4_cfg_a (io_ptw_pmp_4_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_4_cfg_x (io_ptw_pmp_4_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_4_cfg_w (io_ptw_pmp_4_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_4_cfg_r (io_ptw_pmp_4_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_4_addr (io_ptw_pmp_4_addr_0), // @[TLB.scala:318:7]
.io_pmp_4_mask (io_ptw_pmp_4_mask_0), // @[TLB.scala:318:7]
.io_pmp_5_cfg_l (io_ptw_pmp_5_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_5_cfg_a (io_ptw_pmp_5_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_5_cfg_x (io_ptw_pmp_5_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_5_cfg_w (io_ptw_pmp_5_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_5_cfg_r (io_ptw_pmp_5_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_5_addr (io_ptw_pmp_5_addr_0), // @[TLB.scala:318:7]
.io_pmp_5_mask (io_ptw_pmp_5_mask_0), // @[TLB.scala:318:7]
.io_pmp_6_cfg_l (io_ptw_pmp_6_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_6_cfg_a (io_ptw_pmp_6_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_6_cfg_x (io_ptw_pmp_6_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_6_cfg_w (io_ptw_pmp_6_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_6_cfg_r (io_ptw_pmp_6_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_6_addr (io_ptw_pmp_6_addr_0), // @[TLB.scala:318:7]
.io_pmp_6_mask (io_ptw_pmp_6_mask_0), // @[TLB.scala:318:7]
.io_pmp_7_cfg_l (io_ptw_pmp_7_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_7_cfg_a (io_ptw_pmp_7_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_7_cfg_x (io_ptw_pmp_7_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_7_cfg_w (io_ptw_pmp_7_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_7_cfg_r (io_ptw_pmp_7_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_7_addr (io_ptw_pmp_7_addr_0), // @[TLB.scala:318:7]
.io_pmp_7_mask (io_ptw_pmp_7_mask_0), // @[TLB.scala:318:7]
.io_addr (mpu_physaddr[31:0]), // @[TLB.scala:414:25, :417:15]
.io_size (io_req_bits_size_0), // @[TLB.scala:318:7]
.io_r (_pmp_io_r),
.io_w (_pmp_io_w),
.io_x (_pmp_io_x)
); // @[TLB.scala:416:19]
PMAChecker_9 pma ( // @[TLB.scala:422:19]
.clock (clock),
.reset (reset),
.io_paddr (mpu_physaddr), // @[TLB.scala:414:25]
.io_resp_cacheable (cacheable),
.io_resp_r (_pma_io_resp_r),
.io_resp_w (_pma_io_resp_w),
.io_resp_pp (_pma_io_resp_pp),
.io_resp_al (_pma_io_resp_al),
.io_resp_aa (_pma_io_resp_aa),
.io_resp_x (_pma_io_resp_x),
.io_resp_eff (_pma_io_resp_eff)
); // @[TLB.scala:422:19]
assign newEntry_ppp = _pma_io_resp_pp; // @[TLB.scala:422:19, :449:24]
assign newEntry_pal = _pma_io_resp_al; // @[TLB.scala:422:19, :449:24]
assign newEntry_paa = _pma_io_resp_aa; // @[TLB.scala:422:19, :449:24]
assign newEntry_eff = _pma_io_resp_eff; // @[TLB.scala:422:19, :449:24]
OptimizationBarrier_TLBEntryData_78 entries_barrier ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_ppn (_entries_barrier_io_y_ppn),
.io_y_u (_entries_barrier_io_y_u),
.io_y_ae_ptw (_entries_barrier_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_io_y_ae_stage2),
.io_y_pf (_entries_barrier_io_y_pf),
.io_y_gf (_entries_barrier_io_y_gf),
.io_y_sw (_entries_barrier_io_y_sw),
.io_y_sx (_entries_barrier_io_y_sx),
.io_y_sr (_entries_barrier_io_y_sr),
.io_y_hw (_entries_barrier_io_y_hw),
.io_y_hx (_entries_barrier_io_y_hx),
.io_y_hr (_entries_barrier_io_y_hr),
.io_y_pw (_entries_barrier_io_y_pw),
.io_y_px (_entries_barrier_io_y_px),
.io_y_pr (_entries_barrier_io_y_pr),
.io_y_ppp (_entries_barrier_io_y_ppp),
.io_y_pal (_entries_barrier_io_y_pal),
.io_y_paa (_entries_barrier_io_y_paa),
.io_y_eff (_entries_barrier_io_y_eff),
.io_y_c (_entries_barrier_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_79 entries_barrier_1 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_2_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_2_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_2_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_2_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_2_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_2_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_2_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_2_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_2_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_2_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_2_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_2_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_2_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_2_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_2_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_2_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_2_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_2_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_2_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_2_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_2_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_2_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_2_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_ppn (_entries_barrier_1_io_y_ppn),
.io_y_u (_entries_barrier_1_io_y_u),
.io_y_ae_ptw (_entries_barrier_1_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_1_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_1_io_y_ae_stage2),
.io_y_pf (_entries_barrier_1_io_y_pf),
.io_y_gf (_entries_barrier_1_io_y_gf),
.io_y_sw (_entries_barrier_1_io_y_sw),
.io_y_sx (_entries_barrier_1_io_y_sx),
.io_y_sr (_entries_barrier_1_io_y_sr),
.io_y_hw (_entries_barrier_1_io_y_hw),
.io_y_hx (_entries_barrier_1_io_y_hx),
.io_y_hr (_entries_barrier_1_io_y_hr),
.io_y_pw (_entries_barrier_1_io_y_pw),
.io_y_px (_entries_barrier_1_io_y_px),
.io_y_pr (_entries_barrier_1_io_y_pr),
.io_y_ppp (_entries_barrier_1_io_y_ppp),
.io_y_pal (_entries_barrier_1_io_y_pal),
.io_y_paa (_entries_barrier_1_io_y_paa),
.io_y_eff (_entries_barrier_1_io_y_eff),
.io_y_c (_entries_barrier_1_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_80 entries_barrier_2 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_4_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_4_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_4_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_4_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_4_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_4_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_4_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_4_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_4_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_4_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_4_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_4_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_4_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_4_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_4_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_4_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_4_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_4_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_4_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_4_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_4_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_4_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_4_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_ppn (_entries_barrier_2_io_y_ppn),
.io_y_u (_entries_barrier_2_io_y_u),
.io_y_ae_ptw (_entries_barrier_2_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_2_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_2_io_y_ae_stage2),
.io_y_pf (_entries_barrier_2_io_y_pf),
.io_y_gf (_entries_barrier_2_io_y_gf),
.io_y_sw (_entries_barrier_2_io_y_sw),
.io_y_sx (_entries_barrier_2_io_y_sx),
.io_y_sr (_entries_barrier_2_io_y_sr),
.io_y_hw (_entries_barrier_2_io_y_hw),
.io_y_hx (_entries_barrier_2_io_y_hx),
.io_y_hr (_entries_barrier_2_io_y_hr),
.io_y_pw (_entries_barrier_2_io_y_pw),
.io_y_px (_entries_barrier_2_io_y_px),
.io_y_pr (_entries_barrier_2_io_y_pr),
.io_y_ppp (_entries_barrier_2_io_y_ppp),
.io_y_pal (_entries_barrier_2_io_y_pal),
.io_y_paa (_entries_barrier_2_io_y_paa),
.io_y_eff (_entries_barrier_2_io_y_eff),
.io_y_c (_entries_barrier_2_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_81 entries_barrier_3 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_6_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_6_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_6_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_6_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_6_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_6_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_6_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_6_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_6_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_6_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_6_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_6_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_6_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_6_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_6_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_6_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_6_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_6_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_6_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_6_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_6_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_6_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_6_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_ppn (_entries_barrier_3_io_y_ppn),
.io_y_u (_entries_barrier_3_io_y_u),
.io_y_ae_ptw (_entries_barrier_3_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_3_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_3_io_y_ae_stage2),
.io_y_pf (_entries_barrier_3_io_y_pf),
.io_y_gf (_entries_barrier_3_io_y_gf),
.io_y_sw (_entries_barrier_3_io_y_sw),
.io_y_sx (_entries_barrier_3_io_y_sx),
.io_y_sr (_entries_barrier_3_io_y_sr),
.io_y_hw (_entries_barrier_3_io_y_hw),
.io_y_hx (_entries_barrier_3_io_y_hx),
.io_y_hr (_entries_barrier_3_io_y_hr),
.io_y_pw (_entries_barrier_3_io_y_pw),
.io_y_px (_entries_barrier_3_io_y_px),
.io_y_pr (_entries_barrier_3_io_y_pr),
.io_y_ppp (_entries_barrier_3_io_y_ppp),
.io_y_pal (_entries_barrier_3_io_y_pal),
.io_y_paa (_entries_barrier_3_io_y_paa),
.io_y_eff (_entries_barrier_3_io_y_eff),
.io_y_c (_entries_barrier_3_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_82 entries_barrier_4 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_8_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_8_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_8_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_8_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_8_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_8_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_8_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_8_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_8_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_8_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_8_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_8_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_8_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_8_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_8_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_8_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_8_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_8_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_8_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_8_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_8_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_8_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_8_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_ppn (_entries_barrier_4_io_y_ppn),
.io_y_u (_entries_barrier_4_io_y_u),
.io_y_ae_ptw (_entries_barrier_4_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_4_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_4_io_y_ae_stage2),
.io_y_pf (_entries_barrier_4_io_y_pf),
.io_y_gf (_entries_barrier_4_io_y_gf),
.io_y_sw (_entries_barrier_4_io_y_sw),
.io_y_sx (_entries_barrier_4_io_y_sx),
.io_y_sr (_entries_barrier_4_io_y_sr),
.io_y_hw (_entries_barrier_4_io_y_hw),
.io_y_hx (_entries_barrier_4_io_y_hx),
.io_y_hr (_entries_barrier_4_io_y_hr),
.io_y_pw (_entries_barrier_4_io_y_pw),
.io_y_px (_entries_barrier_4_io_y_px),
.io_y_pr (_entries_barrier_4_io_y_pr),
.io_y_ppp (_entries_barrier_4_io_y_ppp),
.io_y_pal (_entries_barrier_4_io_y_pal),
.io_y_paa (_entries_barrier_4_io_y_paa),
.io_y_eff (_entries_barrier_4_io_y_eff),
.io_y_c (_entries_barrier_4_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_83 entries_barrier_5 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_10_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_10_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_10_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_10_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_10_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_10_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_10_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_10_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_10_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_10_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_10_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_10_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_10_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_10_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_10_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_10_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_10_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_10_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_10_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_10_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_10_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_10_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_10_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_ppn (_entries_barrier_5_io_y_ppn),
.io_y_u (_entries_barrier_5_io_y_u),
.io_y_ae_ptw (_entries_barrier_5_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_5_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_5_io_y_ae_stage2),
.io_y_pf (_entries_barrier_5_io_y_pf),
.io_y_gf (_entries_barrier_5_io_y_gf),
.io_y_sw (_entries_barrier_5_io_y_sw),
.io_y_sx (_entries_barrier_5_io_y_sx),
.io_y_sr (_entries_barrier_5_io_y_sr),
.io_y_hw (_entries_barrier_5_io_y_hw),
.io_y_hx (_entries_barrier_5_io_y_hx),
.io_y_hr (_entries_barrier_5_io_y_hr)
); // @[package.scala:267:25]
assign io_req_ready = io_req_ready_0; // @[TLB.scala:318:7]
assign io_resp_miss = io_resp_miss_0; // @[TLB.scala:318:7]
assign io_resp_paddr = io_resp_paddr_0; // @[TLB.scala:318:7]
assign io_ptw_req_valid = io_ptw_req_valid_0; // @[TLB.scala:318:7]
assign io_ptw_req_bits_bits_addr = io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7]
assign io_ptw_req_bits_bits_need_gpa = io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLMonitor_29( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Arbiter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
object TLArbiter
{
// (valids, select) => readys
type Policy = (Integer, UInt, Bool) => UInt
val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0)
val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width))
val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else {
val valid = valids(width-1, 0)
assert (valid === valids)
val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0))
val filter = Cat(valid & ~mask, valid)
val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width)
val readys = ~((unready >> width) & unready(width-1, 0))
when (select && valid.orR) {
mask := leftOR(readys & valid, width)
}
readys(width-1, 0)
}
def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = {
apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = {
if (sources.isEmpty) {
sink.bits := DontCare
} else if (sources.size == 1) {
sink :<>= sources.head._2
} else {
val pairs = sources.toList
val beatsIn = pairs.map(_._1)
val sourcesIn = pairs.map(_._2)
// The number of beats which remain to be sent
val beatsLeft = RegInit(0.U)
val idle = beatsLeft === 0.U
val latch = idle && sink.ready // winner (if any) claims sink
// Who wants access to the sink?
val valids = sourcesIn.map(_.valid)
// Arbitrate amongst the requests
val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools)
// Which request wins arbitration?
val winner = VecInit((readys zip valids) map { case (r,v) => r&&v })
// Confirm the policy works properly
require (readys.size == valids.size)
// Never two winners
val prefixOR = winner.scanLeft(false.B)(_||_).init
assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})
// If there was any request, there is a winner
assert (!valids.reduce(_||_) || winner.reduce(_||_))
// Track remaining beats
val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) }
val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats
beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire)
// The one-hot source granted access in the previous cycle
val state = RegInit(VecInit(Seq.fill(sources.size)(false.B)))
val muxState = Mux(idle, winner, state)
state := muxState
val allowed = Mux(idle, readys, state)
(sourcesIn zip allowed) foreach { case (s, r) =>
s.ready := sink.ready && r
}
sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids))
sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits))
}
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
abstract class DecoupledArbiterTest(
policy: TLArbiter.Policy,
txns: Int,
timeout: Int,
val numSources: Int,
beatsLeftFromIdx: Int => UInt)
(implicit p: Parameters) extends UnitTest(timeout)
{
val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W))))
dontTouch(sources.suggestName("sources"))
val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W)))
dontTouch(sink.suggestName("sink"))
val count = RegInit(0.U(log2Ceil(txns).W))
val lfsr = LFSR(16, true.B)
sources.zipWithIndex.map { case (z, i) => z.bits := i.U }
TLArbiter(policy)(sink, sources.zipWithIndex.map {
case (z, i) => (beatsLeftFromIdx(i), z)
}:_*)
count := count + 1.U
io.finished := count >= txns.U
}
/** This tests that when a specific pattern of source valids are driven,
* a new index from amongst that pattern is always selected,
* unless one of those sources takes multiple beats,
* in which case the same index should be selected until the arbiter goes idle.
*/
class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false)
(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U)
{
val lastWinner = RegInit((numSources+1).U)
val beatsLeft = RegInit(0.U(log2Ceil(numSources).W))
val first = lastWinner > numSources.U
val valid = lfsr(0)
val ready = lfsr(15)
sink.ready := ready
sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way
case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid)
}
when (sink.fire) {
if (print) { printf("TestRobin: %d\n", sink.bits) }
when (beatsLeft === 0.U) {
assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.")
lastWinner := sink.bits
beatsLeft := sink.bits
} .otherwise {
assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats")
beatsLeft := beatsLeft - 1.U
}
}
if (print) {
when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) }
}
}
/** This tests that the lowest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertLowest(id: Int): Unit = {
when (sources(id).valid) {
assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) }
}
/** This tests that the highest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertHighest(id: Int): Unit = {
when (sources(id).valid) {
assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) }
}
File Xbar.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue}
import freechips.rocketchip.util.BundleField
// Trades off slave port proximity against routing resource cost
object ForceFanout
{
def apply[T](
a: TriStateValue = TriStateValue.unset,
b: TriStateValue = TriStateValue.unset,
c: TriStateValue = TriStateValue.unset,
d: TriStateValue = TriStateValue.unset,
e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) =
{
body(p.alterPartial {
case ForceFanoutKey => p(ForceFanoutKey) match {
case ForceFanoutParams(pa, pb, pc, pd, pe) =>
ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe))
}
})
}
}
private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean)
private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false))
class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
val node = new TLNexusNode(
clientFn = { seq =>
seq(0).v1copy(
echoFields = BundleField.union(seq.flatMap(_.echoFields)),
requestFields = BundleField.union(seq.flatMap(_.requestFields)),
responseKeys = seq.flatMap(_.responseKeys).distinct,
minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
port.clients map { client => client.v1copy(
sourceId = client.sourceId.shift(range.start)
)}
}
)
},
managerFn = { seq =>
val fifoIdFactory = TLXbar.relabeler()
seq(0).v1copy(
responseFields = BundleField.union(seq.flatMap(_.responseFields)),
requestKeys = seq.flatMap(_.requestKeys).distinct,
minLatency = seq.map(_.minLatency).min,
endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes,
s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
val fifoIdMapper = fifoIdFactory()
port.managers map { manager => manager.v1copy(
fifoId = manager.fifoId.map(fifoIdMapper(_))
)}
}
)
}
){
override def circuitIdentity = outputs.size == 1 && inputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
if ((node.in.size * node.out.size) > (8*32)) {
println (s"!!! WARNING !!!")
println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.")
println (s"!!! WARNING !!!")
}
val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle))
override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_")
TLXbar.circuit(policy, node.in, node.out)
}
}
object TLXbar
{
def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId))
def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId))
def assignRanges(sizes: Seq[Int]) = {
val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) }
val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size
val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions
val ranges = (tuples zip starts) map { case ((sz, i), st) =>
(if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i)
}
ranges.sortBy(_._2).map(_._1) // Restore orignal order
}
def relabeler() = {
var idFactory = 0
() => {
val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int]
(x: Int) => {
if (fifoMap.contains(x)) fifoMap(x) else {
val out = idFactory
idFactory = idFactory + 1
fifoMap += (x -> out)
out
}
}
}
}
def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) {
val (io_in, edgesIn) = seqIn.unzip
val (io_out, edgesOut) = seqOut.unzip
// Not every master need connect to every slave on every channel; determine which connections are necessary
val reachableIO = edgesIn.map { cp => edgesOut.map { mp =>
cp.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)}}}}
}.toVector}.toVector
val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED)
}.toVector}.toVector
val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector}.toVector
val connectAIO = reachableIO
val connectBIO = probeIO
val connectCIO = releaseIO
val connectDIO = reachableIO
val connectEIO = releaseIO
def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } }
val connectAOI = transpose(connectAIO)
val connectBOI = transpose(connectBIO)
val connectCOI = transpose(connectCIO)
val connectDOI = transpose(connectDIO)
val connectEOI = transpose(connectEIO)
// Grab the port ID mapping
val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
// We need an intermediate size of bundle with the widest possible identifiers
val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params))
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
// Transform input bundle sources (sinks use global namespace on both sides)
val in = Wire(Vec(io_in.size, TLBundle(wide_bundle)))
for (i <- 0 until in.size) {
val r = inputIdRanges(i)
if (connectAIO(i).exists(x=>x)) {
in(i).a.bits.user := DontCare
in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll
in(i).a.bits.source := io_in(i).a.bits.source | r.start.U
} else {
in(i).a := DontCare
io_in(i).a := DontCare
in(i).a.valid := false.B
io_in(i).a.ready := true.B
}
if (connectBIO(i).exists(x=>x)) {
io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll
io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size)
} else {
in(i).b := DontCare
io_in(i).b := DontCare
in(i).b.ready := true.B
io_in(i).b.valid := false.B
}
if (connectCIO(i).exists(x=>x)) {
in(i).c.bits.user := DontCare
in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll
in(i).c.bits.source := io_in(i).c.bits.source | r.start.U
} else {
in(i).c := DontCare
io_in(i).c := DontCare
in(i).c.valid := false.B
io_in(i).c.ready := true.B
}
if (connectDIO(i).exists(x=>x)) {
io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll
io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size)
} else {
in(i).d := DontCare
io_in(i).d := DontCare
in(i).d.ready := true.B
io_in(i).d.valid := false.B
}
if (connectEIO(i).exists(x=>x)) {
in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll
} else {
in(i).e := DontCare
io_in(i).e := DontCare
in(i).e.valid := false.B
io_in(i).e.ready := true.B
}
}
// Transform output bundle sinks (sources use global namespace on both sides)
val out = Wire(Vec(io_out.size, TLBundle(wide_bundle)))
for (o <- 0 until out.size) {
val r = outputIdRanges(o)
if (connectAOI(o).exists(x=>x)) {
out(o).a.bits.user := DontCare
io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll
} else {
out(o).a := DontCare
io_out(o).a := DontCare
out(o).a.ready := true.B
io_out(o).a.valid := false.B
}
if (connectBOI(o).exists(x=>x)) {
out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll
} else {
out(o).b := DontCare
io_out(o).b := DontCare
out(o).b.valid := false.B
io_out(o).b.ready := true.B
}
if (connectCOI(o).exists(x=>x)) {
out(o).c.bits.user := DontCare
io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll
} else {
out(o).c := DontCare
io_out(o).c := DontCare
out(o).c.ready := true.B
io_out(o).c.valid := false.B
}
if (connectDOI(o).exists(x=>x)) {
out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll
out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U
} else {
out(o).d := DontCare
io_out(o).d := DontCare
out(o).d.valid := false.B
io_out(o).d.ready := true.B
}
if (connectEOI(o).exists(x=>x)) {
io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll
io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size)
} else {
out(o).e := DontCare
io_out(o).e := DontCare
out(o).e.ready := true.B
io_out(o).e.valid := false.B
}
}
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
// Based on input=>output connectivity, create per-input minimal address decode circuits
val requiredAC = (connectAIO ++ connectCIO).distinct
val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO =>
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
// Print the address mapping
if (false) {
println("Xbar mapping:")
route_addrs.foreach { p =>
print(" ")
p.foreach { a => print(s" ${a}") }
println("")
}
println("--")
}
(connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _)))
}.toMap
// Print the ID mapping
if (false) {
println(s"XBar mapping:")
(edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) =>
println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}")
}
println("")
}
val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) }
val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) }
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } }
val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } }
val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } }
val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) }
val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) }
val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) }
val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) }
val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) }
// Fanout the input sources to the output sinks
val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) })
val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) })
val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) })
val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) })
val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) })
// Arbitrate amongst the sources
for (o <- 0 until out.size) {
TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*)
TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*)
TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*)
filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B }
}
for (i <- 0 until in.size) {
TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*)
TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*)
filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B }
filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B }
}
}
def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
val xbar = LazyModule(new TLXbar(policy, nameSuffix))
xbar.node
}
// Replicate an input port to each output port
def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = {
val filtered = Wire(Vec(select.size, chiselTypeOf(input)))
for (i <- 0 until select.size) {
filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits)
filtered(i).valid := input.valid && (select(i) || (select.size == 1).B)
}
input.ready := Mux1H(select, filtered.map(_.ready))
filtered
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Xbar"))
val xbar = LazyModule(new TLXbar)
xbar.node := TLDelayer(0.1) := model.node := fuzz.node
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val xbar = LazyModule(new TLXbar)
val fuzzers = (0 until nClients) map { n =>
val fuzz = LazyModule(new TLFuzzer(txns))
xbar.node := TLDelayer(0.1) := fuzz.node
fuzz
}
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzzers.last.module.io.finished
}
}
class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
|
module TLXbar_fbus_i3_o1_a32d64s5k3z4u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_2_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_2_a_valid, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_2_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_2_d_valid, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire requestDOI_0_0 = auto_anon_out_d_bits_source == 5'h11; // @[Parameters.scala:46:9]
wire requestDOI_0_2 = auto_anon_out_d_bits_source == 5'h10; // @[Parameters.scala:46:9]
wire portsDIO_filtered_0_valid = auto_anon_out_d_valid & requestDOI_0_0; // @[Xbar.scala:355:40]
wire portsDIO_filtered_1_valid = auto_anon_out_d_valid & ~(auto_anon_out_d_bits_source[4]); // @[Xbar.scala:355:40]
wire portsDIO_filtered_2_valid = auto_anon_out_d_valid & requestDOI_0_2; // @[Xbar.scala:355:40]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire [2:0] readys_valid = {auto_anon_in_2_a_valid, auto_anon_in_1_a_valid, auto_anon_in_0_a_valid}; // @[Arbiter.scala:68:51]
reg [2:0] readys_mask; // @[Arbiter.scala:23:23]
wire [2:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [3:0] _GEN = {_readys_filter_T_1[1:0], auto_anon_in_2_a_valid, auto_anon_in_1_a_valid} | {_readys_filter_T_1, auto_anon_in_2_a_valid}; // @[package.scala:262:{43,48}]
wire [2:0] readys_readys = ~({readys_mask[2], _readys_filter_T_1[2] | readys_mask[1], _GEN[3] | readys_mask[0]} & (_GEN[2:0] | {_readys_filter_T_1[2], _GEN[3:2]})); // @[package.scala:262:{43,48}]
wire winner_0 = readys_readys[0] & auto_anon_in_0_a_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_1 = readys_readys[1] & auto_anon_in_1_a_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_2 = readys_readys[2] & auto_anon_in_2_a_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire _out_0_a_valid_T = auto_anon_in_0_a_valid | auto_anon_in_1_a_valid; // @[Arbiter.scala:79:31]
|
Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
|
module RoundRawFNToRecFN_e8_s24_53( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_53 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Xbar.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue}
import freechips.rocketchip.util.BundleField
// Trades off slave port proximity against routing resource cost
object ForceFanout
{
def apply[T](
a: TriStateValue = TriStateValue.unset,
b: TriStateValue = TriStateValue.unset,
c: TriStateValue = TriStateValue.unset,
d: TriStateValue = TriStateValue.unset,
e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) =
{
body(p.alterPartial {
case ForceFanoutKey => p(ForceFanoutKey) match {
case ForceFanoutParams(pa, pb, pc, pd, pe) =>
ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe))
}
})
}
}
private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean)
private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false))
class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
val node = new TLNexusNode(
clientFn = { seq =>
seq(0).v1copy(
echoFields = BundleField.union(seq.flatMap(_.echoFields)),
requestFields = BundleField.union(seq.flatMap(_.requestFields)),
responseKeys = seq.flatMap(_.responseKeys).distinct,
minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
port.clients map { client => client.v1copy(
sourceId = client.sourceId.shift(range.start)
)}
}
)
},
managerFn = { seq =>
val fifoIdFactory = TLXbar.relabeler()
seq(0).v1copy(
responseFields = BundleField.union(seq.flatMap(_.responseFields)),
requestKeys = seq.flatMap(_.requestKeys).distinct,
minLatency = seq.map(_.minLatency).min,
endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes,
s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
val fifoIdMapper = fifoIdFactory()
port.managers map { manager => manager.v1copy(
fifoId = manager.fifoId.map(fifoIdMapper(_))
)}
}
)
}
){
override def circuitIdentity = outputs.size == 1 && inputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
if ((node.in.size * node.out.size) > (8*32)) {
println (s"!!! WARNING !!!")
println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.")
println (s"!!! WARNING !!!")
}
val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle))
override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_")
TLXbar.circuit(policy, node.in, node.out)
}
}
object TLXbar
{
def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId))
def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId))
def assignRanges(sizes: Seq[Int]) = {
val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) }
val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size
val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions
val ranges = (tuples zip starts) map { case ((sz, i), st) =>
(if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i)
}
ranges.sortBy(_._2).map(_._1) // Restore orignal order
}
def relabeler() = {
var idFactory = 0
() => {
val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int]
(x: Int) => {
if (fifoMap.contains(x)) fifoMap(x) else {
val out = idFactory
idFactory = idFactory + 1
fifoMap += (x -> out)
out
}
}
}
}
def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) {
val (io_in, edgesIn) = seqIn.unzip
val (io_out, edgesOut) = seqOut.unzip
// Not every master need connect to every slave on every channel; determine which connections are necessary
val reachableIO = edgesIn.map { cp => edgesOut.map { mp =>
cp.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)}}}}
}.toVector}.toVector
val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED)
}.toVector}.toVector
val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector}.toVector
val connectAIO = reachableIO
val connectBIO = probeIO
val connectCIO = releaseIO
val connectDIO = reachableIO
val connectEIO = releaseIO
def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } }
val connectAOI = transpose(connectAIO)
val connectBOI = transpose(connectBIO)
val connectCOI = transpose(connectCIO)
val connectDOI = transpose(connectDIO)
val connectEOI = transpose(connectEIO)
// Grab the port ID mapping
val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
// We need an intermediate size of bundle with the widest possible identifiers
val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params))
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
// Transform input bundle sources (sinks use global namespace on both sides)
val in = Wire(Vec(io_in.size, TLBundle(wide_bundle)))
for (i <- 0 until in.size) {
val r = inputIdRanges(i)
if (connectAIO(i).exists(x=>x)) {
in(i).a.bits.user := DontCare
in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll
in(i).a.bits.source := io_in(i).a.bits.source | r.start.U
} else {
in(i).a := DontCare
io_in(i).a := DontCare
in(i).a.valid := false.B
io_in(i).a.ready := true.B
}
if (connectBIO(i).exists(x=>x)) {
io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll
io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size)
} else {
in(i).b := DontCare
io_in(i).b := DontCare
in(i).b.ready := true.B
io_in(i).b.valid := false.B
}
if (connectCIO(i).exists(x=>x)) {
in(i).c.bits.user := DontCare
in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll
in(i).c.bits.source := io_in(i).c.bits.source | r.start.U
} else {
in(i).c := DontCare
io_in(i).c := DontCare
in(i).c.valid := false.B
io_in(i).c.ready := true.B
}
if (connectDIO(i).exists(x=>x)) {
io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll
io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size)
} else {
in(i).d := DontCare
io_in(i).d := DontCare
in(i).d.ready := true.B
io_in(i).d.valid := false.B
}
if (connectEIO(i).exists(x=>x)) {
in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll
} else {
in(i).e := DontCare
io_in(i).e := DontCare
in(i).e.valid := false.B
io_in(i).e.ready := true.B
}
}
// Transform output bundle sinks (sources use global namespace on both sides)
val out = Wire(Vec(io_out.size, TLBundle(wide_bundle)))
for (o <- 0 until out.size) {
val r = outputIdRanges(o)
if (connectAOI(o).exists(x=>x)) {
out(o).a.bits.user := DontCare
io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll
} else {
out(o).a := DontCare
io_out(o).a := DontCare
out(o).a.ready := true.B
io_out(o).a.valid := false.B
}
if (connectBOI(o).exists(x=>x)) {
out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll
} else {
out(o).b := DontCare
io_out(o).b := DontCare
out(o).b.valid := false.B
io_out(o).b.ready := true.B
}
if (connectCOI(o).exists(x=>x)) {
out(o).c.bits.user := DontCare
io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll
} else {
out(o).c := DontCare
io_out(o).c := DontCare
out(o).c.ready := true.B
io_out(o).c.valid := false.B
}
if (connectDOI(o).exists(x=>x)) {
out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll
out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U
} else {
out(o).d := DontCare
io_out(o).d := DontCare
out(o).d.valid := false.B
io_out(o).d.ready := true.B
}
if (connectEOI(o).exists(x=>x)) {
io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll
io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size)
} else {
out(o).e := DontCare
io_out(o).e := DontCare
out(o).e.ready := true.B
io_out(o).e.valid := false.B
}
}
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
// Based on input=>output connectivity, create per-input minimal address decode circuits
val requiredAC = (connectAIO ++ connectCIO).distinct
val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO =>
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
// Print the address mapping
if (false) {
println("Xbar mapping:")
route_addrs.foreach { p =>
print(" ")
p.foreach { a => print(s" ${a}") }
println("")
}
println("--")
}
(connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _)))
}.toMap
// Print the ID mapping
if (false) {
println(s"XBar mapping:")
(edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) =>
println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}")
}
println("")
}
val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) }
val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) }
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } }
val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } }
val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } }
val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) }
val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) }
val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) }
val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) }
val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) }
// Fanout the input sources to the output sinks
val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) })
val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) })
val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) })
val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) })
val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) })
// Arbitrate amongst the sources
for (o <- 0 until out.size) {
TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*)
TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*)
TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*)
filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B }
}
for (i <- 0 until in.size) {
TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*)
TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*)
filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B }
filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B }
}
}
def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
val xbar = LazyModule(new TLXbar(policy, nameSuffix))
xbar.node
}
// Replicate an input port to each output port
def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = {
val filtered = Wire(Vec(select.size, chiselTypeOf(input)))
for (i <- 0 until select.size) {
filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits)
filtered(i).valid := input.valid && (select(i) || (select.size == 1).B)
}
input.ready := Mux1H(select, filtered.map(_.ready))
filtered
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Xbar"))
val xbar = LazyModule(new TLXbar)
xbar.node := TLDelayer(0.1) := model.node := fuzz.node
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val xbar = LazyModule(new TLXbar)
val fuzzers = (0 until nClients) map { n =>
val fuzz = LazyModule(new TLFuzzer(txns))
xbar.node := TLDelayer(0.1) := fuzz.node
fuzz
}
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzzers.last.module.io.finished
}
}
class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
|
module TLXbar_fbus_i0_o0_a1d8s1k1z1u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset // @[Xbar.scala:74:9]
);
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File Nodes.scala:
package constellation.channel
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.diplomacy._
case class EmptyParams()
case class ChannelEdgeParams(cp: ChannelParams, p: Parameters)
object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] {
def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
ChannelEdgeParams(pu, p)
}
def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p)
def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString)
}
override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = {
val monitor = Module(new NoCMonitor(edge.cp)(edge.p))
monitor.io.in := bundle
}
// TODO: Add nodepath stuff? override def mixO, override def mixI
}
case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams()))
case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams))
case class ChannelAdapterNode(
slaveFn: ChannelParams => ChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn)
case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)()
case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)()
case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters)
case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters)
object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] {
def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
IngressChannelEdgeParams(pu, p)
}
def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p)
def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString)
}
}
object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] {
def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
EgressChannelEdgeParams(pu, p)
}
def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p)
def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString)
}
}
case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams()))
case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams))
case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams()))
case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams))
case class IngressChannelAdapterNode(
slaveFn: IngressChannelParams => IngressChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn)
case class EgressChannelAdapterNode(
slaveFn: EgressChannelParams => EgressChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn)
case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)()
case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)()
case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)()
case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)()
File Router.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{RoutingRelation}
import constellation.noc.{HasNoCParams}
case class UserRouterParams(
// Payload width. Must match payload width on all channels attached to this routing node
payloadBits: Int = 64,
// Combines SA and ST stages (removes pipeline register)
combineSAST: Boolean = false,
// Combines RC and VA stages (removes pipeline register)
combineRCVA: Boolean = false,
// Adds combinational path from SA to VA
coupleSAVA: Boolean = false,
vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p)
)
case class RouterParams(
nodeId: Int,
nIngress: Int,
nEgress: Int,
user: UserRouterParams
)
trait HasRouterOutputParams {
def outParams: Seq[ChannelParams]
def egressParams: Seq[EgressChannelParams]
def allOutParams = outParams ++ egressParams
def nOutputs = outParams.size
def nEgress = egressParams.size
def nAllOutputs = allOutParams.size
}
trait HasRouterInputParams {
def inParams: Seq[ChannelParams]
def ingressParams: Seq[IngressChannelParams]
def allInParams = inParams ++ ingressParams
def nInputs = inParams.size
def nIngress = ingressParams.size
def nAllInputs = allInParams.size
}
trait HasRouterParams
{
def routerParams: RouterParams
def nodeId = routerParams.nodeId
def payloadBits = routerParams.user.payloadBits
}
class DebugBundle(val nIn: Int) extends Bundle {
val va_stall = Vec(nIn, UInt())
val sa_stall = Vec(nIn, UInt())
}
class Router(
val routerParams: RouterParams,
preDiplomaticInParams: Seq[ChannelParams],
preDiplomaticIngressParams: Seq[IngressChannelParams],
outDests: Seq[Int],
egressIds: Seq[Int]
)(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams {
val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams
val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u))
val sourceNodes = outDests.map(u => ChannelSourceNode(u))
val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u))
val egressNodes = egressIds.map(u => EgressChannelSourceNode(u))
val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size))
val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None
def inParams = module.inParams
def outParams = module.outParams
def ingressParams = module.ingressParams
def egressParams = module.egressParams
lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams {
val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip
val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip
val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip
val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip
val io_debug = debugNode.out(0)._1
val inParams = edgesIn.map(_.cp)
val outParams = edgesOut.map(_.cp)
val ingressParams = edgesIngress.map(_.cp)
val egressParams = edgesEgress.map(_.cp)
allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits))
allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits))
require(nIngress == routerParams.nIngress)
require(nEgress == routerParams.nEgress)
require(nAllInputs >= 1)
require(nAllOutputs >= 1)
require(nodeId < (1 << nodeIdBits))
val input_units = inParams.zipWithIndex.map { case (u,i) =>
Module(new InputUnit(u, outParams, egressParams,
routerParams.user.combineRCVA, routerParams.user.combineSAST))
.suggestName(s"input_unit_${i}_from_${u.srcId}") }
val ingress_units = ingressParams.zipWithIndex.map { case (u,i) =>
Module(new IngressUnit(i, u, outParams, egressParams,
routerParams.user.combineRCVA, routerParams.user.combineSAST))
.suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") }
val all_input_units = input_units ++ ingress_units
val output_units = outParams.zipWithIndex.map { case (u,i) =>
Module(new OutputUnit(inParams, ingressParams, u))
.suggestName(s"output_unit_${i}_to_${u.destId}")}
val egress_units = egressParams.zipWithIndex.map { case (u,i) =>
Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1,
routerParams.user.combineSAST,
inParams, ingressParams, u))
.suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")}
val all_output_units = output_units ++ egress_units
val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams))
val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams))
val vc_allocator = Module(routerParams.user.vcAllocator(
VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams)
)(p))
val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams))
val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire)))
dontTouch(fires_count)
(io_in zip input_units ).foreach { case (i,u) => u.io.in <> i }
(io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit }
(output_units zip io_out ).foreach { case (u,o) => o <> u.io.out }
(egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out }
(route_computer.io.req zip all_input_units).foreach {
case (i,u) => i <> u.io.router_req }
(all_input_units zip route_computer.io.resp).foreach {
case (u,o) => u.io.router_resp <> o }
(vc_allocator.io.req zip all_input_units).foreach {
case (i,u) => i <> u.io.vcalloc_req }
(all_input_units zip vc_allocator.io.resp).foreach {
case (u,o) => u.io.vcalloc_resp <> o }
(all_output_units zip vc_allocator.io.out_allocs).foreach {
case (u,a) => u.io.allocs <> a }
(vc_allocator.io.channel_status zip all_output_units).foreach {
case (a,u) => a := u.io.channel_status }
all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) =>
in.io.out_credit_available(outIdx) := out.io.credit_available
})
(all_input_units zip switch_allocator.io.req).foreach {
case (u,r) => r <> u.io.salloc_req }
(all_output_units zip switch_allocator.io.credit_alloc).foreach {
case (u,a) => u.io.credit_alloc := a }
(switch.io.in zip all_input_units).foreach {
case (i,u) => i <> u.io.out }
(all_output_units zip switch.io.out).foreach {
case (u,o) => u.io.in <> o }
switch.io.sel := (if (routerParams.user.combineSAST) {
switch_allocator.io.switch_sel
} else {
RegNext(switch_allocator.io.switch_sel)
})
if (hasCtrl) {
val io_ctrl = ctrlNode.get.out(0)._1
val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams))
io_ctrl <> ctrl.io.ctrl
(all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r }
(all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) }
} else {
input_units.foreach(_.io.block := false.B)
ingress_units.foreach(_.io.block := false.B)
}
(io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r }
(io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r }
val debug_tsc = RegInit(0.U(64.W))
debug_tsc := debug_tsc + 1.U
val debug_sample = RegInit(0.U(64.W))
debug_sample := debug_sample + 1.U
val sample_rate = PlusArg("noc_util_sample_rate", width=20)
when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U }
def sample(fire: Bool, s: String) = {
val util_ctr = RegInit(0.U(64.W))
val fired = RegInit(false.B)
util_ctr := util_ctr + fire
fired := fired || fire
when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) {
val fmtStr = s"nocsample %d $s %d\n"
printf(fmtStr, debug_tsc, util_ctr);
fired := fire
}
}
destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f =>
sample(f.fire, s"${edge.cp.srcId} $nodeId")
} }
ingressNodes.map(_.in(0)).foreach { case (in, edge) =>
sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId")
}
egressNodes.map(_.out(0)).foreach { case (out, edge) =>
sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}")
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
|
module Router_14( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [1:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [36:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [36:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [36:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [36:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_3; // @[Router.scala:136:32]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [36:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [36:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _egress_unit_1_to_2_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_1_to_2_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_1_to_2_io_out_valid; // @[Router.scala:125:13]
wire _output_unit_0_to_2_io_credit_available_0; // @[Router.scala:122:13]
wire _output_unit_0_to_2_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_0_to_2_io_credit_available_2; // @[Router.scala:122:13]
wire _output_unit_0_to_2_io_credit_available_3; // @[Router.scala:122:13]
wire _output_unit_0_to_2_io_channel_status_0_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_2_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_2_io_channel_status_2_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_2_io_channel_status_3_occupied; // @[Router.scala:122:13]
wire _ingress_unit_1_from_2_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [36:0] _ingress_unit_1_from_2_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_2_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_2_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_1_from_2_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_in_ready; // @[Router.scala:116:13]
wire [1:0] _input_unit_0_from_0_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_0_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_0_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [36:0] _input_unit_0_from_0_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_0_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_0_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_0_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_0_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_2_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35]
reg REG_1_0_1_0; // @[Router.scala:178:14]
reg REG_1_0_0_0; // @[Router.scala:178:14]
reg REG_0_0_1_0; // @[Router.scala:178:14]
reg REG_0_0_0_0; // @[Router.scala:178:14]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLMonitor_36( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File RecFNToIN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of
the University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.log2Up
import scala.math._
import consts._
class RecFNToIN(expWidth: Int, sigWidth: Int, intWidth: Int) extends chisel3.Module
{
override def desiredName = s"RecFNToIN_e${expWidth}_s${sigWidth}_i${intWidth}"
val io = IO(new Bundle {
val in = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val signedOut = Input(Bool())
val out = Output(Bits(intWidth.W))
val intExceptionFlags = Output(Bits(3.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(expWidth, sigWidth, io.in)
val magGeOne = rawIn.sExp(expWidth)
val posExp = rawIn.sExp(expWidth - 1, 0)
val magJustBelowOne = !magGeOne && posExp.andR
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
/*------------------------------------------------------------------------
| Assuming the input floating-point value is not a NaN, its magnitude is
| at least 1, and it is not obviously so large as to lead to overflow,
| convert its significand to fixed-point (i.e., with the binary point in a
| fixed location). For a non-NaN input with a magnitude less than 1, this
| expression contrives to ensure that the integer bits of 'alignedSig'
| will all be zeros.
*------------------------------------------------------------------------*/
val shiftedSig =
(magGeOne ## rawIn.sig(sigWidth - 2, 0))<<
Mux(magGeOne,
rawIn.sExp(min(expWidth - 2, log2Up(intWidth) - 1), 0),
0.U
)
val alignedSig =
(shiftedSig>>(sigWidth - 2)) ## shiftedSig(sigWidth - 3, 0).orR
val unroundedInt = 0.U(intWidth.W) | alignedSig>>2
val common_inexact = Mux(magGeOne, alignedSig(1, 0).orR, !rawIn.isZero)
val roundIncr_near_even =
(magGeOne && (alignedSig(2, 1).andR || alignedSig(1, 0).andR)) ||
(magJustBelowOne && alignedSig(1, 0).orR)
val roundIncr_near_maxMag = (magGeOne && alignedSig(1)) || magJustBelowOne
val roundIncr =
(roundingMode_near_even && roundIncr_near_even ) ||
(roundingMode_near_maxMag && roundIncr_near_maxMag) ||
((roundingMode_min || roundingMode_odd) &&
(rawIn.sign && common_inexact)) ||
(roundingMode_max && (!rawIn.sign && common_inexact))
val complUnroundedInt = Mux(rawIn.sign, ~unroundedInt, unroundedInt)
val roundedInt =
Mux(roundIncr ^ rawIn.sign,
complUnroundedInt + 1.U,
complUnroundedInt
) | (roundingMode_odd && common_inexact)
val magGeOne_atOverflowEdge = (posExp === (intWidth - 1).U)
//*** CHANGE TO TAKE BITS FROM THE ORIGINAL 'rawIn.sig' INSTEAD OF FROM
//*** 'unroundedInt'?:
val roundCarryBut2 = unroundedInt(intWidth - 3, 0).andR && roundIncr
val common_overflow =
Mux(magGeOne,
(posExp >= intWidth.U) ||
Mux(io.signedOut,
Mux(rawIn.sign,
magGeOne_atOverflowEdge &&
(unroundedInt(intWidth - 2, 0).orR || roundIncr),
magGeOne_atOverflowEdge ||
((posExp === (intWidth - 2).U) && roundCarryBut2)
),
rawIn.sign ||
(magGeOne_atOverflowEdge &&
unroundedInt(intWidth - 2) && roundCarryBut2)
),
!io.signedOut && rawIn.sign && roundIncr
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val invalidExc = rawIn.isNaN || rawIn.isInf
val overflow = !invalidExc && common_overflow
val inexact = !invalidExc && !common_overflow && common_inexact
val excSign = !rawIn.isNaN && rawIn.sign
val excOut =
Mux((io.signedOut === excSign),
(BigInt(1)<<(intWidth - 1)).U,
0.U
) |
Mux(!excSign, ((BigInt(1)<<(intWidth - 1)) - 1).U, 0.U)
io.out := Mux(invalidExc || common_overflow, excOut, roundedInt)
io.intExceptionFlags := invalidExc ## overflow ## inexact
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
|
module RecFNToIN_e8_s24_i8_2( // @[RecFNToIN.scala:46:7]
input clock, // @[RecFNToIN.scala:46:7]
input reset, // @[RecFNToIN.scala:46:7]
input [32:0] io_in, // @[RecFNToIN.scala:49:16]
output [7:0] io_out, // @[RecFNToIN.scala:49:16]
output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToIN.scala:46:7]
wire roundingMode_minMag = 1'h0; // @[RecFNToIN.scala:68:53]
wire roundingMode_min = 1'h0; // @[RecFNToIN.scala:69:53]
wire roundingMode_max = 1'h0; // @[RecFNToIN.scala:70:53]
wire roundingMode_near_maxMag = 1'h0; // @[RecFNToIN.scala:71:53]
wire roundingMode_odd = 1'h0; // @[RecFNToIN.scala:72:53]
wire _roundIncr_T_1 = 1'h0; // @[RecFNToIN.scala:99:35]
wire _roundIncr_T_3 = 1'h0; // @[RecFNToIN.scala:100:28]
wire _roundIncr_T_5 = 1'h0; // @[RecFNToIN.scala:100:49]
wire _roundIncr_T_9 = 1'h0; // @[RecFNToIN.scala:102:27]
wire _roundedInt_T_4 = 1'h0; // @[RecFNToIN.scala:108:31]
wire _common_overflow_T_15 = 1'h0; // @[RecFNToIN.scala:128:13]
wire _common_overflow_T_16 = 1'h0; // @[RecFNToIN.scala:128:27]
wire _common_overflow_T_17 = 1'h0; // @[RecFNToIN.scala:128:41]
wire io_signedOut = 1'h1; // @[RecFNToIN.scala:46:7]
wire roundingMode_near_even = 1'h1; // @[RecFNToIN.scala:67:53]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToIN.scala:46:7]
wire [7:0] _io_out_T_1; // @[RecFNToIN.scala:145:18]
wire [2:0] _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:146:52]
wire [7:0] io_out_0; // @[RecFNToIN.scala:46:7]
wire [2:0] io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire magGeOne = rawIn_sExp[8]; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] posExp = rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire _magJustBelowOne_T = ~magGeOne; // @[RecFNToIN.scala:61:30, :63:27]
wire _magJustBelowOne_T_1 = &posExp; // @[RecFNToIN.scala:62:28, :63:47]
wire magJustBelowOne = _magJustBelowOne_T & _magJustBelowOne_T_1; // @[RecFNToIN.scala:63:{27,37,47}]
wire [22:0] _shiftedSig_T = rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _shiftedSig_T_1 = {magGeOne, _shiftedSig_T}; // @[RecFNToIN.scala:61:30, :83:{19,31}]
wire [2:0] _shiftedSig_T_2 = rawIn_sExp[2:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [2:0] _shiftedSig_T_3 = magGeOne ? _shiftedSig_T_2 : 3'h0; // @[RecFNToIN.scala:61:30, :84:16, :85:27]
wire [30:0] shiftedSig = {7'h0, _shiftedSig_T_1} << _shiftedSig_T_3; // @[RecFNToIN.scala:83:{19,49}, :84:16]
wire [8:0] _alignedSig_T = shiftedSig[30:22]; // @[RecFNToIN.scala:83:49, :89:20]
wire [21:0] _alignedSig_T_1 = shiftedSig[21:0]; // @[RecFNToIN.scala:83:49, :89:51]
wire _alignedSig_T_2 = |_alignedSig_T_1; // @[RecFNToIN.scala:89:{51,69}]
wire [9:0] alignedSig = {_alignedSig_T, _alignedSig_T_2}; // @[RecFNToIN.scala:89:{20,38,69}]
wire [7:0] _unroundedInt_T = alignedSig[9:2]; // @[RecFNToIN.scala:89:38, :90:52]
wire [7:0] unroundedInt = _unroundedInt_T; // @[RecFNToIN.scala:90:{40,52}]
wire [1:0] _common_inexact_T = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50]
wire [1:0] _roundIncr_near_even_T_2 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :94:64]
wire [1:0] _roundIncr_near_even_T_6 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :95:39]
wire _common_inexact_T_1 = |_common_inexact_T; // @[RecFNToIN.scala:92:{50,57}]
wire _common_inexact_T_2 = ~rawIn_isZero_0; // @[rawFloatFromRecFN.scala:55:23]
wire common_inexact = magGeOne ? _common_inexact_T_1 : _common_inexact_T_2; // @[RecFNToIN.scala:61:30, :92:{29,57,62}]
wire [1:0] _roundIncr_near_even_T = alignedSig[2:1]; // @[RecFNToIN.scala:89:38, :94:39]
wire _roundIncr_near_even_T_1 = &_roundIncr_near_even_T; // @[RecFNToIN.scala:94:{39,46}]
wire _roundIncr_near_even_T_3 = &_roundIncr_near_even_T_2; // @[RecFNToIN.scala:94:{64,71}]
wire _roundIncr_near_even_T_4 = _roundIncr_near_even_T_1 | _roundIncr_near_even_T_3; // @[RecFNToIN.scala:94:{46,51,71}]
wire _roundIncr_near_even_T_5 = magGeOne & _roundIncr_near_even_T_4; // @[RecFNToIN.scala:61:30, :94:{25,51}]
wire _roundIncr_near_even_T_7 = |_roundIncr_near_even_T_6; // @[RecFNToIN.scala:95:{39,46}]
wire _roundIncr_near_even_T_8 = magJustBelowOne & _roundIncr_near_even_T_7; // @[RecFNToIN.scala:63:37, :95:{26,46}]
wire roundIncr_near_even = _roundIncr_near_even_T_5 | _roundIncr_near_even_T_8; // @[RecFNToIN.scala:94:{25,78}, :95:26]
wire _roundIncr_T = roundIncr_near_even; // @[RecFNToIN.scala:94:78, :98:35]
wire _roundIncr_near_maxMag_T = alignedSig[1]; // @[RecFNToIN.scala:89:38, :96:56]
wire _roundIncr_near_maxMag_T_1 = magGeOne & _roundIncr_near_maxMag_T; // @[RecFNToIN.scala:61:30, :96:{43,56}]
wire roundIncr_near_maxMag = _roundIncr_near_maxMag_T_1 | magJustBelowOne; // @[RecFNToIN.scala:63:37, :96:{43,61}]
wire _roundIncr_T_2 = _roundIncr_T; // @[RecFNToIN.scala:98:{35,61}]
wire _roundIncr_T_6 = _roundIncr_T_2; // @[RecFNToIN.scala:98:61, :99:61]
wire _roundIncr_T_4 = rawIn_sign & common_inexact; // @[rawFloatFromRecFN.scala:55:23]
wire roundIncr = _roundIncr_T_6; // @[RecFNToIN.scala:99:61, :101:46]
wire _roundIncr_T_7 = ~rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _roundIncr_T_8 = _roundIncr_T_7 & common_inexact; // @[RecFNToIN.scala:92:29, :102:{31,43}]
wire [7:0] _complUnroundedInt_T = ~unroundedInt; // @[RecFNToIN.scala:90:40, :103:45]
wire [7:0] complUnroundedInt = rawIn_sign ? _complUnroundedInt_T : unroundedInt; // @[rawFloatFromRecFN.scala:55:23]
wire _roundedInt_T = roundIncr ^ rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _roundedInt_T_1 = {1'h0, complUnroundedInt} + 9'h1; // @[RecFNToIN.scala:103:32, :106:31]
wire [7:0] _roundedInt_T_2 = _roundedInt_T_1[7:0]; // @[RecFNToIN.scala:106:31]
wire [7:0] _roundedInt_T_3 = _roundedInt_T ? _roundedInt_T_2 : complUnroundedInt; // @[RecFNToIN.scala:103:32, :105:{12,23}, :106:31]
wire [7:0] roundedInt = _roundedInt_T_3; // @[RecFNToIN.scala:105:12, :108:11]
wire magGeOne_atOverflowEdge = posExp == 8'h7; // @[RecFNToIN.scala:62:28, :110:43]
wire [5:0] _roundCarryBut2_T = unroundedInt[5:0]; // @[RecFNToIN.scala:90:40, :113:38]
wire _roundCarryBut2_T_1 = &_roundCarryBut2_T; // @[RecFNToIN.scala:113:{38,56}]
wire roundCarryBut2 = _roundCarryBut2_T_1 & roundIncr; // @[RecFNToIN.scala:101:46, :113:{56,61}]
wire _common_overflow_T = |(posExp[7:3]); // @[RecFNToIN.scala:62:28, :116:21]
wire [6:0] _common_overflow_T_1 = unroundedInt[6:0]; // @[RecFNToIN.scala:90:40, :120:42]
wire _common_overflow_T_2 = |_common_overflow_T_1; // @[RecFNToIN.scala:120:{42,60}]
wire _common_overflow_T_3 = _common_overflow_T_2 | roundIncr; // @[RecFNToIN.scala:101:46, :120:{60,64}]
wire _common_overflow_T_4 = magGeOne_atOverflowEdge & _common_overflow_T_3; // @[RecFNToIN.scala:110:43, :119:49, :120:64]
wire _common_overflow_T_5 = posExp == 8'h6; // @[RecFNToIN.scala:62:28, :122:38]
wire _common_overflow_T_6 = _common_overflow_T_5 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :122:{38,60}]
wire _common_overflow_T_7 = magGeOne_atOverflowEdge | _common_overflow_T_6; // @[RecFNToIN.scala:110:43, :121:49, :122:60]
wire _common_overflow_T_8 = rawIn_sign ? _common_overflow_T_4 : _common_overflow_T_7; // @[rawFloatFromRecFN.scala:55:23]
wire _common_overflow_T_13 = _common_overflow_T_8; // @[RecFNToIN.scala:117:20, :118:24]
wire _common_overflow_T_9 = unroundedInt[6]; // @[RecFNToIN.scala:90:40, :126:42]
wire _common_overflow_T_10 = magGeOne_atOverflowEdge & _common_overflow_T_9; // @[RecFNToIN.scala:110:43, :125:50, :126:42]
wire _common_overflow_T_11 = _common_overflow_T_10 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :125:50, :126:57]
wire _common_overflow_T_12 = rawIn_sign | _common_overflow_T_11; // @[rawFloatFromRecFN.scala:55:23]
wire _common_overflow_T_14 = _common_overflow_T | _common_overflow_T_13; // @[RecFNToIN.scala:116:{21,36}, :117:20]
wire common_overflow = magGeOne & _common_overflow_T_14; // @[RecFNToIN.scala:61:30, :115:12, :116:36]
wire invalidExc = rawIn_isNaN | rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire _overflow_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20]
wire overflow = _overflow_T & common_overflow; // @[RecFNToIN.scala:115:12, :134:{20,32}]
wire _inexact_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20, :135:20]
wire _inexact_T_1 = ~common_overflow; // @[RecFNToIN.scala:115:12, :135:35]
wire _inexact_T_2 = _inexact_T & _inexact_T_1; // @[RecFNToIN.scala:135:{20,32,35}]
wire inexact = _inexact_T_2 & common_inexact; // @[RecFNToIN.scala:92:29, :135:{32,52}]
wire _excSign_T = ~rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire excSign = _excSign_T & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _excOut_T = excSign; // @[RecFNToIN.scala:137:32, :139:27]
wire [7:0] _excOut_T_1 = {_excOut_T, 7'h0}; // @[RecFNToIN.scala:139:{12,27}]
wire _excOut_T_2 = ~excSign; // @[RecFNToIN.scala:137:32, :143:13]
wire [6:0] _excOut_T_3 = {7{_excOut_T_2}}; // @[RecFNToIN.scala:143:{12,13}]
wire [7:0] excOut = {_excOut_T_1[7], _excOut_T_1[6:0] | _excOut_T_3}; // @[RecFNToIN.scala:139:12, :142:11, :143:12]
wire _io_out_T = invalidExc | common_overflow; // @[RecFNToIN.scala:115:12, :133:34, :145:30]
assign _io_out_T_1 = _io_out_T ? excOut : roundedInt; // @[RecFNToIN.scala:108:11, :142:11, :145:{18,30}]
assign io_out_0 = _io_out_T_1; // @[RecFNToIN.scala:46:7, :145:18]
wire [1:0] _io_intExceptionFlags_T = {invalidExc, overflow}; // @[RecFNToIN.scala:133:34, :134:32, :146:40]
assign _io_intExceptionFlags_T_1 = {_io_intExceptionFlags_T, inexact}; // @[RecFNToIN.scala:135:52, :146:{40,52}]
assign io_intExceptionFlags_0 = _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:46:7, :146:52]
assign io_out = io_out_0; // @[RecFNToIN.scala:46:7]
assign io_intExceptionFlags = io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLMonitor_23( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_28 = _source_ok_T_27 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_31 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [25:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_33 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_39 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_45 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_51 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_34 = _source_ok_T_33 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_40 = _source_ok_T_39 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_44; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_46 = _source_ok_T_45 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_52 = _source_ok_T_51 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire _source_ok_T_57 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_57; // @[Parameters.scala:1138:31]
wire _source_ok_T_58 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire _source_ok_T_59 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_63 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _T_950 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_950; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_950; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [25:0] address; // @[Monitor.scala:391:22]
wire _T_1018 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1018; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1018; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1018; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_883 = _T_950 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_883 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_883 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_883 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_883 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_883 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_929 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_929 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_898 = _T_1018 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_898 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_898 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_898 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_994 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_994 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_976 = _T_1018 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_976 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_976 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_976 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File DescribedSRAM.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
}
|
module dataArrayWay_3( // @[DescribedSRAM.scala:17:26]
input [8:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [63:0] RW0_wdata,
output [63:0] RW0_rdata
);
dataArrayWay_0_ext dataArrayWay_0_ext ( // @[DescribedSRAM.scala:17:26]
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata)
); // @[DescribedSRAM.scala:17:26]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File RecFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class
RecFNToRecFN(
inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int)
extends chisel3.RawModule
{
val io = IO(new Bundle {
val in = Input(Bits((inExpWidth + inSigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in);
if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
io.out := io.in<<(outSigWidth - inSigWidth)
io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W)
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
inExpWidth,
inSigWidth,
outExpWidth,
outSigWidth,
flRoundOpt_sigMSBitAlwaysZero
))
roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn)
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := rawIn
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
|
module RecFNToRecFN_97( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Replacement.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import freechips.rocketchip.util.property.cover
abstract class ReplacementPolicy {
def nBits: Int
def perSet: Boolean
def way: UInt
def miss: Unit
def hit: Unit
def access(touch_way: UInt): Unit
def access(touch_ways: Seq[Valid[UInt]]): Unit
def state_read: UInt
def get_next_state(state: UInt, touch_way: UInt): UInt
def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = {
touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev))
}
def get_replace_way(state: UInt): UInt
}
object ReplacementPolicy {
def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match {
case "random" => new RandomReplacement(n_ways)
case "lru" => new TrueLRU(n_ways)
case "plru" => new PseudoLRU(n_ways)
case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t")
}
}
class RandomReplacement(n_ways: Int) extends ReplacementPolicy {
private val replace = Wire(Bool())
replace := false.B
def nBits = 16
def perSet = false
private val lfsr = LFSR(nBits, replace)
def state_read = WireDefault(lfsr)
def way = Random(n_ways, lfsr)
def miss = replace := true.B
def hit = {}
def access(touch_way: UInt) = {}
def access(touch_ways: Seq[Valid[UInt]]) = {}
def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare
def get_replace_way(state: UInt) = way
}
abstract class SeqReplacementPolicy {
def access(set: UInt): Unit
def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit
def way: UInt
}
abstract class SetAssocReplacementPolicy {
def access(set: UInt, touch_way: UInt): Unit
def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit
def way(set: UInt): UInt
}
class SeqRandom(n_ways: Int) extends SeqReplacementPolicy {
val logic = new RandomReplacement(n_ways)
def access(set: UInt) = { }
def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = {
when (valid && !hit) { logic.miss }
}
def way = logic.way
}
class TrueLRU(n_ways: Int) extends ReplacementPolicy {
// True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others.
// The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits):
// [5] - 3 more recent than 2
// [4] - 3 more recent than 1
// [3] - 2 more recent than 1
// [2] - 3 more recent than 0
// [1] - 2 more recent than 0
// [0] - 1 more recent than 0
def nBits = (n_ways * (n_ways-1)) / 2
def perSet = true
private val state_reg = RegInit(0.U(nBits.W))
def state_read = WireDefault(state_reg)
private def extractMRUVec(state: UInt): Seq[UInt] = {
// Extract per-way information about which higher-indexed ways are more recently used
val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W)))
var lsb = 0
for (i <- 0 until n_ways-1) {
moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W))
lsb = lsb + (n_ways - i - 1)
}
moreRecentVec
}
def get_next_state(state: UInt, touch_way: UInt): UInt = {
val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W)))
val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix
val wayDec = UIntToOH(touch_way, n_ways)
// Compute next value of triangular matrix
// set the touched way as more recent than every other way
nextState.zipWithIndex.map { case (e, i) =>
e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) | wayDec)
}
nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1
}
def access(touch_way: UInt): Unit = {
state_reg := get_next_state(state_reg, touch_way)
}
def access(touch_ways: Seq[Valid[UInt]]): Unit = {
when (touch_ways.map(_.valid).orR) {
state_reg := get_next_state(state_reg, touch_ways)
}
for (i <- 1 until touch_ways.size) {
cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous")
}
}
def get_replace_way(state: UInt): UInt = {
val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix
// For each way, determine if all other ways are more recent
val mruWayDec = (0 until n_ways).map { i =>
val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR)
val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _))
upperMoreRecent && lowerMoreRecent
}
OHToUInt(mruWayDec)
}
def way = get_replace_way(state_reg)
def miss = access(way)
def hit = {}
@deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05")
def replace: UInt = way
}
class PseudoLRU(n_ways: Int) extends ReplacementPolicy {
// Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU
//
//
// - bits storage example for 4-way PLRU binary tree:
// bit[2]: ways 3+2 older than ways 1+0
// / \
// bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0
//
//
// - bits storage example for 3-way PLRU binary tree:
// bit[1]: way 2 older than ways 1+0
// \
// bit[0]: way 1 older than way 0
//
//
// - bits storage example for 8-way PLRU binary tree:
// bit[6]: ways 7-4 older than ways 3-0
// / \
// bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0
// / \ / \
// bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0
def nBits = n_ways - 1
def perSet = true
private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W))
def state_read = WireDefault(state_reg)
def access(touch_way: UInt): Unit = {
state_reg := get_next_state(state_reg, touch_way)
}
def access(touch_ways: Seq[Valid[UInt]]): Unit = {
when (touch_ways.map(_.valid).orR) {
state_reg := get_next_state(state_reg, touch_ways)
}
for (i <- 1 until touch_ways.size) {
cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous")
}
}
/** @param state state_reg bits for this sub-tree
* @param touch_way touched way encoded value bits for this sub-tree
* @param tree_nways number of ways in this sub-tree
*/
def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = {
require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways")
require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways")
if (tree_nways > 2) {
// we are at a branching node in the tree, so recurse
val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree
val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree
val set_left_older = !touch_way(log2Ceil(tree_nways)-1)
val left_subtree_state = state.extract(tree_nways-3, right_nways-1)
val right_subtree_state = state(right_nways-2, 0)
if (left_nways > 1) {
// we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees
Cat(set_left_older,
Mux(set_left_older,
left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree
get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer
Mux(set_left_older,
get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer
right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree
} else {
// we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree
Cat(set_left_older,
Mux(set_left_older,
get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer
right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree
}
} else if (tree_nways == 2) {
// we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value
!touch_way(0)
} else { // tree_nways <= 1
// we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires)
0.U(1.W)
}
}
def get_next_state(state: UInt, touch_way: UInt): UInt = {
val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways))
else touch_way.extract(log2Ceil(n_ways)-1,0)
get_next_state(state, touch_way_sized, n_ways)
}
/** @param state state_reg bits for this sub-tree
* @param tree_nways number of ways in this sub-tree
*/
def get_replace_way(state: UInt, tree_nways: Int): UInt = {
require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways")
// this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb
if (tree_nways > 2) {
// we are at a branching node in the tree, so recurse
val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree
val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree
val left_subtree_older = state(tree_nways-2)
val left_subtree_state = state.extract(tree_nways-3, right_nways-1)
val right_subtree_state = state(right_nways-2, 0)
if (left_nways > 1) {
// we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees
Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value
Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right
get_replace_way(left_subtree_state, left_nways), // recurse left
get_replace_way(right_subtree_state, right_nways))) // recurse right
} else {
// we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree
Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value
Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right
0.U(1.W),
get_replace_way(right_subtree_state, right_nways))) // recurse right
}
} else if (tree_nways == 2) {
// we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value
state(0)
} else { // tree_nways <= 1
// we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value
0.U(1.W)
}
}
def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways)
def way = get_replace_way(state_reg)
def miss = access(way)
def hit = {}
}
class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy {
val logic = new PseudoLRU(n_ways)
val state = SyncReadMem(n_sets, UInt(logic.nBits.W))
val current_state = Wire(UInt(logic.nBits.W))
val next_state = Wire(UInt(logic.nBits.W))
val plru_way = logic.get_replace_way(current_state)
def access(set: UInt) = {
current_state := state.read(set)
}
def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = {
val update_way = Mux(hit, way, plru_way)
next_state := logic.get_next_state(current_state, update_way)
when (valid) { state.write(set, next_state) }
}
def way = plru_way
}
class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy {
val logic = policy.toLowerCase match {
case "plru" => new PseudoLRU(n_ways)
case "lru" => new TrueLRU(n_ways)
case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t")
}
val state_vec =
if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line
else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W))))
def access(set: UInt, touch_way: UInt) = {
state_vec(set) := logic.get_next_state(state_vec(set), touch_way)
}
def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = {
require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways")
for (set <- 0 until n_sets) {
val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) =>
Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)}
when (set_touch_ways.map(_.valid).orR) {
state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways)
}
}
}
def way(set: UInt) = logic.get_replace_way(state_vec(set))
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) {
val plru = new PseudoLRU(n_ways)
// step
io.finished := RegNext(true.B, false.B)
val get_replace_ways = (0 until (1 << (n_ways-1))).map(state =>
plru.get_replace_way(state = state.U((n_ways-1).W)))
val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way =>
plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W))))
n_ways match {
case 2 => {
assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0))
assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1))
assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0))
assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1))
assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0))
assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1))
}
case 3 => {
assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0))
assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1))
assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2))
assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3))
assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0))
assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1))
assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2))
assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0))
assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1))
assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2))
assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0))
assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1))
assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2))
assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0))
assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1))
assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2))
}
case 4 => {
assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0))
assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1))
assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2))
assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3))
assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4))
assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5))
assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6))
assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7))
assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0))
assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1))
assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2))
assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3))
assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0))
assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1))
assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2))
assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3))
assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0))
assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1))
assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2))
assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3))
assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0))
assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1))
assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2))
assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3))
assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0))
assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1))
assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2))
assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3))
assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0))
assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1))
assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2))
assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3))
assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0))
assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1))
assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2))
assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3))
assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0))
assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1))
assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2))
assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3))
}
case 5 => {
assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0))
assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1))
assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2))
assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3))
assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4))
assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5))
assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6))
assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7))
assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8))
assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9))
assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10))
assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11))
assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12))
assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13))
assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14))
assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15))
assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0))
assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1))
assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2))
assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3))
assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4))
assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0))
assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1))
assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2))
assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3))
assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4))
assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0))
assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1))
assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2))
assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3))
assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4))
assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0))
assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1))
assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2))
assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3))
assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4))
assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0))
assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1))
assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2))
assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3))
assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4))
assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0))
assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1))
assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2))
assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3))
assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4))
assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0))
assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1))
assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2))
assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3))
assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4))
assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0))
assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1))
assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2))
assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3))
assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4))
assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0))
assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1))
assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2))
assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3))
assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4))
assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0))
assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1))
assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2))
assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3))
assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4))
assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0))
assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1))
assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2))
assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3))
assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4))
assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0))
assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1))
assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2))
assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3))
assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4))
assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0))
assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1))
assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2))
assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3))
assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4))
assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0))
assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1))
assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2))
assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3))
assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4))
assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0))
assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1))
assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2))
assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3))
assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4))
assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0))
assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1))
assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2))
assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3))
assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4))
}
case 6 => {
assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0))
assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1))
assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2))
assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3))
assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4))
assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5))
assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6))
assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7))
assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8))
assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9))
assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10))
assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11))
assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12))
assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13))
assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14))
assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15))
assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16))
assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17))
assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18))
assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19))
assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20))
assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21))
assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22))
assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23))
assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24))
assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25))
assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26))
assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27))
assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28))
assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29))
assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30))
assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31))
}
case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways")
}
}
File Consts.scala:
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket.constants
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
trait ScalarOpConstants {
val SZ_BR = 3
def BR_X = BitPat("b???")
def BR_EQ = 0.U(3.W)
def BR_NE = 1.U(3.W)
def BR_J = 2.U(3.W)
def BR_N = 3.U(3.W)
def BR_LT = 4.U(3.W)
def BR_GE = 5.U(3.W)
def BR_LTU = 6.U(3.W)
def BR_GEU = 7.U(3.W)
def A1_X = BitPat("b??")
def A1_ZERO = 0.U(2.W)
def A1_RS1 = 1.U(2.W)
def A1_PC = 2.U(2.W)
def A1_RS1SHL = 3.U(2.W)
def IMM_X = BitPat("b???")
def IMM_S = 0.U(3.W)
def IMM_SB = 1.U(3.W)
def IMM_U = 2.U(3.W)
def IMM_UJ = 3.U(3.W)
def IMM_I = 4.U(3.W)
def IMM_Z = 5.U(3.W)
def A2_X = BitPat("b???")
def A2_ZERO = 0.U(3.W)
def A2_SIZE = 1.U(3.W)
def A2_RS2 = 2.U(3.W)
def A2_IMM = 3.U(3.W)
def A2_RS2OH = 4.U(3.W)
def A2_IMMOH = 5.U(3.W)
def X = BitPat("b?")
def N = BitPat("b0")
def Y = BitPat("b1")
val SZ_DW = 1
def DW_X = X
def DW_32 = false.B
def DW_64 = true.B
def DW_XPR = DW_64
}
trait MemoryOpConstants {
val NUM_XA_OPS = 9
val M_SZ = 5
def M_X = BitPat("b?????");
def M_XRD = "b00000".U; // int load
def M_XWR = "b00001".U; // int store
def M_PFR = "b00010".U; // prefetch with intent to read
def M_PFW = "b00011".U; // prefetch with intent to write
def M_XA_SWAP = "b00100".U
def M_FLUSH_ALL = "b00101".U // flush all lines
def M_XLR = "b00110".U
def M_XSC = "b00111".U
def M_XA_ADD = "b01000".U
def M_XA_XOR = "b01001".U
def M_XA_OR = "b01010".U
def M_XA_AND = "b01011".U
def M_XA_MIN = "b01100".U
def M_XA_MAX = "b01101".U
def M_XA_MINU = "b01110".U
def M_XA_MAXU = "b01111".U
def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions
def M_PWR = "b10001".U // partial (masked) store
def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions
def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions
def M_SFENCE = "b10100".U // SFENCE.VMA
def M_HFENCEV = "b10101".U // HFENCE.VVMA
def M_HFENCEG = "b10110".U // HFENCE.GVMA
def M_WOK = "b10111".U // check write permissions but don't perform a write
def M_HLVX = "b10000".U // HLVX instruction
def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND)
def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU)
def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd)
def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW
def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd)
def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd)
def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
}
File TLB.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.devices.debug.DebugModuleKey
import freechips.rocketchip.diplomacy.RegionType
import freechips.rocketchip.subsystem.CacheBlockBytes
import freechips.rocketchip.tile.{CoreModule, CoreBundle}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.{OptimizationBarrier, SetAssocLRU, PseudoLRU, PopCountAtLeast, property}
import freechips.rocketchip.util.BooleanToAugmentedBoolean
import freechips.rocketchip.util.IntToAugmentedInt
import freechips.rocketchip.util.UIntToAugmentedUInt
import freechips.rocketchip.util.UIntIsOneOf
import freechips.rocketchip.util.SeqToAugmentedSeq
import freechips.rocketchip.util.SeqBoolBitwiseOps
case object ASIdBits extends Field[Int](0)
case object VMIdBits extends Field[Int](0)
/** =SFENCE=
* rs1 rs2
* {{{
* 0 0 -> flush All
* 0 1 -> flush by ASID
* 1 1 -> flush by ADDR
* 1 0 -> flush by ADDR and ASID
* }}}
* {{{
* If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces.
* If rs1=x0 and rs2!=x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see Section 4.3.1) are not ordered.
* If rs1!=x0 and rs2=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for all address spaces.
* If rs1!=x0 and rs2!=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered.
* }}}
*/
class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) {
val rs1 = Bool()
val rs2 = Bool()
val addr = UInt(vaddrBits.W)
val asid = UInt((asIdBits max 1).W) // TODO zero-width
val hv = Bool()
val hg = Bool()
}
class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) {
/** request address from CPU. */
val vaddr = UInt(vaddrBitsExtended.W)
/** don't lookup TLB, bypass vaddr as paddr */
val passthrough = Bool()
/** granularity */
val size = UInt(log2Ceil(lgMaxSize + 1).W)
/** memory command. */
val cmd = Bits(M_SZ.W)
val prv = UInt(PRV.SZ.W)
/** virtualization mode */
val v = Bool()
}
class TLBExceptions extends Bundle {
val ld = Bool()
val st = Bool()
val inst = Bool()
}
class TLBResp(lgMaxSize: Int = 3)(implicit p: Parameters) extends CoreBundle()(p) {
// lookup responses
val miss = Bool()
/** physical address */
val paddr = UInt(paddrBits.W)
val gpa = UInt(vaddrBitsExtended.W)
val gpa_is_pte = Bool()
/** page fault exception */
val pf = new TLBExceptions
/** guest page fault exception */
val gf = new TLBExceptions
/** access exception */
val ae = new TLBExceptions
/** misaligned access exception */
val ma = new TLBExceptions
/** if this address is cacheable */
val cacheable = Bool()
/** if caches must allocate this address */
val must_alloc = Bool()
/** if this address is prefetchable for caches*/
val prefetchable = Bool()
/** size/cmd of request that generated this response*/
val size = UInt(log2Ceil(lgMaxSize + 1).W)
val cmd = UInt(M_SZ.W)
}
class TLBEntryData(implicit p: Parameters) extends CoreBundle()(p) {
val ppn = UInt(ppnBits.W)
/** pte.u user */
val u = Bool()
/** pte.g global */
val g = Bool()
/** access exception.
* D$ -> PTW -> TLB AE
* Alignment failed.
*/
val ae_ptw = Bool()
val ae_final = Bool()
val ae_stage2 = Bool()
/** page fault */
val pf = Bool()
/** guest page fault */
val gf = Bool()
/** supervisor write */
val sw = Bool()
/** supervisor execute */
val sx = Bool()
/** supervisor read */
val sr = Bool()
/** hypervisor write */
val hw = Bool()
/** hypervisor excute */
val hx = Bool()
/** hypervisor read */
val hr = Bool()
/** prot_w */
val pw = Bool()
/** prot_x */
val px = Bool()
/** prot_r */
val pr = Bool()
/** PutPartial */
val ppp = Bool()
/** AMO logical */
val pal = Bool()
/** AMO arithmetic */
val paa = Bool()
/** get/put effects */
val eff = Bool()
/** cacheable */
val c = Bool()
/** fragmented_superpage support */
val fragmented_superpage = Bool()
}
/** basic cell for TLB data */
class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boolean)(implicit p: Parameters) extends CoreBundle()(p) {
require(nSectors == 1 || !superpage)
require(!superpageOnly || superpage)
val level = UInt(log2Ceil(pgLevels).W)
/** use vpn as tag */
val tag_vpn = UInt(vpnBits.W)
/** tag in vitualization mode */
val tag_v = Bool()
/** entry data */
val data = Vec(nSectors, UInt(new TLBEntryData().getWidth.W))
/** valid bit */
val valid = Vec(nSectors, Bool())
/** returns all entry data in this entry */
def entry_data = data.map(_.asTypeOf(new TLBEntryData))
/** returns the index of sector */
private def sectorIdx(vpn: UInt) = vpn.extract(nSectors.log2-1, 0)
/** returns the entry data matched with this vpn*/
def getData(vpn: UInt) = OptimizationBarrier(data(sectorIdx(vpn)).asTypeOf(new TLBEntryData))
/** returns whether a sector hits */
def sectorHit(vpn: UInt, virtual: Bool) = valid.orR && sectorTagMatch(vpn, virtual)
/** returns whether tag matches vpn */
def sectorTagMatch(vpn: UInt, virtual: Bool) = (((tag_vpn ^ vpn) >> nSectors.log2) === 0.U) && (tag_v === virtual)
/** returns hit signal */
def hit(vpn: UInt, virtual: Bool): Bool = {
if (superpage && usingVM) {
var tagMatch = valid.head && (tag_v === virtual)
for (j <- 0 until pgLevels) {
val base = (pgLevels - 1 - j) * pgLevelBits
val n = pgLevelBits + (if (j == 0) hypervisorExtraAddrBits else 0)
val ignore = level < j.U || (superpageOnly && j == pgLevels - 1).B
tagMatch = tagMatch && (ignore || (tag_vpn ^ vpn)(base + n - 1, base) === 0.U)
}
tagMatch
} else {
val idx = sectorIdx(vpn)
valid(idx) && sectorTagMatch(vpn, virtual)
}
}
/** returns the ppn of the input TLBEntryData */
def ppn(vpn: UInt, data: TLBEntryData) = {
val supervisorVPNBits = pgLevels * pgLevelBits
if (superpage && usingVM) {
var res = data.ppn >> pgLevelBits*(pgLevels - 1)
for (j <- 1 until pgLevels) {
val ignore = level < j.U || (superpageOnly && j == pgLevels - 1).B
res = Cat(res, (Mux(ignore, vpn, 0.U) | data.ppn)(supervisorVPNBits - j*pgLevelBits - 1, supervisorVPNBits - (j + 1)*pgLevelBits))
}
res
} else {
data.ppn
}
}
/** does the refill
*
* find the target entry with vpn tag
* and replace the target entry with the input entry data
*/
def insert(vpn: UInt, virtual: Bool, level: UInt, entry: TLBEntryData): Unit = {
this.tag_vpn := vpn
this.tag_v := virtual
this.level := level.extract(log2Ceil(pgLevels - superpageOnly.toInt)-1, 0)
val idx = sectorIdx(vpn)
valid(idx) := true.B
data(idx) := entry.asUInt
}
def invalidate(): Unit = { valid.foreach(_ := false.B) }
def invalidate(virtual: Bool): Unit = {
for ((v, e) <- valid zip entry_data)
when (tag_v === virtual) { v := false.B }
}
def invalidateVPN(vpn: UInt, virtual: Bool): Unit = {
if (superpage) {
when (hit(vpn, virtual)) { invalidate() }
} else {
when (sectorTagMatch(vpn, virtual)) {
for (((v, e), i) <- (valid zip entry_data).zipWithIndex)
when (tag_v === virtual && i.U === sectorIdx(vpn)) { v := false.B }
}
}
// For fragmented superpage mappings, we assume the worst (largest)
// case, and zap entries whose most-significant VPNs match
when (((tag_vpn ^ vpn) >> (pgLevelBits * (pgLevels - 1))) === 0.U) {
for ((v, e) <- valid zip entry_data)
when (tag_v === virtual && e.fragmented_superpage) { v := false.B }
}
}
def invalidateNonGlobal(virtual: Bool): Unit = {
for ((v, e) <- valid zip entry_data)
when (tag_v === virtual && !e.g) { v := false.B }
}
}
/** TLB config
*
* @param nSets the number of sets of PTE, follow [[ICacheParams.nSets]]
* @param nWays the total number of wayss of PTE, follow [[ICacheParams.nWays]]
* @param nSectors the number of ways in a single PTE TLBEntry
* @param nSuperpageEntries the number of SuperpageEntries
*/
case class TLBConfig(
nSets: Int,
nWays: Int,
nSectors: Int = 4,
nSuperpageEntries: Int = 4)
/** =Overview=
* [[TLB]] is a TLB template which contains PMA logic and PMP checker.
*
* TLB caches PTE and accelerates the address translation process.
* When tlb miss happens, ask PTW(L2TLB) for Page Table Walk.
* Perform PMP and PMA check during the translation and throw exception if there were any.
*
* ==Cache Structure==
* - Sectored Entry (PTE)
* - set-associative or direct-mapped
* - nsets = [[TLBConfig.nSets]]
* - nways = [[TLBConfig.nWays]] / [[TLBConfig.nSectors]]
* - PTEEntry( sectors = [[TLBConfig.nSectors]] )
* - LRU(if set-associative)
*
* - Superpage Entry(superpage PTE)
* - fully associative
* - nsets = [[TLBConfig.nSuperpageEntries]]
* - PTEEntry(sectors = 1)
* - PseudoLRU
*
* - Special Entry(PTE across PMP)
* - nsets = 1
* - PTEEntry(sectors = 1)
*
* ==Address structure==
* {{{
* |vaddr |
* |ppn/vpn | pgIndex |
* | | |
* | |nSets |nSector | |}}}
*
* ==State Machine==
* {{{
* s_ready: ready to accept request from CPU.
* s_request: when L1TLB(this) miss, send request to PTW(L2TLB), .
* s_wait: wait for PTW to refill L1TLB.
* s_wait_invalidate: L1TLB is waiting for respond from PTW, but L1TLB will invalidate respond from PTW.}}}
*
* ==PMP==
* pmp check
* - special_entry: always check
* - other entry: check on refill
*
* ==Note==
* PMA consume diplomacy parameter generate physical memory address checking logic
*
* Boom use Rocket ITLB, and its own DTLB.
*
* Accelerators:{{{
* sha3: DTLB
* gemmini: DTLB
* hwacha: DTLB*2+ITLB}}}
* @param instruction true for ITLB, false for DTLB
* @param lgMaxSize @todo seems granularity
* @param cfg [[TLBConfig]]
* @param edge collect SoC metadata.
*/
class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
override def desiredName = if (instruction) "ITLB" else "DTLB"
val io = IO(new Bundle {
/** request from Core */
val req = Flipped(Decoupled(new TLBReq(lgMaxSize)))
/** response to Core */
val resp = Output(new TLBResp(lgMaxSize))
/** SFence Input */
val sfence = Flipped(Valid(new SFenceReq))
/** IO to PTW */
val ptw = new TLBPTWIO
/** suppress a TLB refill, one cycle after a miss */
val kill = Input(Bool())
})
io.ptw.customCSRs := DontCare
val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits)
val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits)
/** index for sectored_Entry */
val memIdx = vpn.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2)
/** TLB Entry */
val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nWays / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false))))
/** Superpage Entry */
val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new TLBEntry(1, true, true)))
/** Special Entry
*
* If PMP granularity is less than page size, thus need additional "special" entry manage PMP.
*/
val special_entry = (!pageGranularityPMPs).option(Reg(new TLBEntry(1, true, false)))
def ordinary_entries = sectored_entries(memIdx) ++ superpage_entries
def all_entries = ordinary_entries ++ special_entry
def all_real_entries = sectored_entries.flatten ++ superpage_entries ++ special_entry
val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4)
val state = RegInit(s_ready)
// use vpn as refill_tag
val r_refill_tag = Reg(UInt(vpnBits.W))
val r_superpage_repl_addr = Reg(UInt(log2Ceil(superpage_entries.size).W))
val r_sectored_repl_addr = Reg(UInt(log2Ceil(sectored_entries.head.size).W))
val r_sectored_hit = Reg(Valid(UInt(log2Ceil(sectored_entries.head.size).W)))
val r_superpage_hit = Reg(Valid(UInt(log2Ceil(superpage_entries.size).W)))
val r_vstage1_en = Reg(Bool())
val r_stage2_en = Reg(Bool())
val r_need_gpa = Reg(Bool())
val r_gpa_valid = Reg(Bool())
val r_gpa = Reg(UInt(vaddrBits.W))
val r_gpa_vpn = Reg(UInt(vpnBits.W))
val r_gpa_is_pte = Reg(Bool())
/** privilege mode */
val priv = io.req.bits.prv
val priv_v = usingHypervisor.B && io.req.bits.v
val priv_s = priv(0)
// user mode and supervisor mode
val priv_uses_vm = priv <= PRV.S.U
val satp = Mux(priv_v, io.ptw.vsatp, io.ptw.ptbr)
val stage1_en = usingVM.B && satp.mode(satp.mode.getWidth-1)
/** VS-stage translation enable */
val vstage1_en = usingHypervisor.B && priv_v && io.ptw.vsatp.mode(io.ptw.vsatp.mode.getWidth-1)
/** G-stage translation enable */
val stage2_en = usingHypervisor.B && priv_v && io.ptw.hgatp.mode(io.ptw.hgatp.mode.getWidth-1)
/** Enable Virtual Memory when:
* 1. statically configured
* 1. satp highest bits enabled
* i. RV32:
* - 0 -> Bare
* - 1 -> SV32
* i. RV64:
* - 0000 -> Bare
* - 1000 -> SV39
* - 1001 -> SV48
* - 1010 -> SV57
* - 1011 -> SV64
* 1. In virtualization mode, vsatp highest bits enabled
* 1. priv mode in U and S.
* 1. in H & M mode, disable VM.
* 1. no passthrough(micro-arch defined.)
*
* @see RV-priv spec 4.1.11 Supervisor Address Translation and Protection (satp) Register
* @see RV-priv spec 8.2.18 Virtual Supervisor Address Translation and Protection Register (vsatp)
*/
val vm_enabled = (stage1_en || stage2_en) && priv_uses_vm && !io.req.bits.passthrough
// flush guest entries on vsatp.MODE Bare <-> SvXX transitions
val v_entries_use_stage1 = RegInit(false.B)
val vsatp_mode_mismatch = priv_v && (vstage1_en =/= v_entries_use_stage1) && !io.req.bits.passthrough
// share a single physical memory attribute checker (unshare if critical path)
val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0)
/** refill signal */
val do_refill = usingVM.B && io.ptw.resp.valid
/** sfence invalidate refill */
val invalidate_refill = state.isOneOf(s_request /* don't care */, s_wait_invalidate) || io.sfence.valid
// PMP
val mpu_ppn = Mux(do_refill, refill_ppn,
Mux(vm_enabled && special_entry.nonEmpty.B, special_entry.map(e => e.ppn(vpn, e.getData(vpn))).getOrElse(0.U), io.req.bits.vaddr >> pgIdxBits))
val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0))
val mpu_priv = Mux[UInt](usingVM.B && (do_refill || io.req.bits.passthrough /* PTW */), PRV.S.U, Cat(io.ptw.status.debug, priv))
val pmp = Module(new PMPChecker(lgMaxSize))
pmp.io.addr := mpu_physaddr
pmp.io.size := io.req.bits.size
pmp.io.pmp := (io.ptw.pmp: Seq[PMP])
pmp.io.prv := mpu_priv
val pma = Module(new PMAChecker(edge.manager)(p))
pma.io.paddr := mpu_physaddr
// todo: using DataScratchpad doesn't support cacheable.
val cacheable = pma.io.resp.cacheable && (instruction || !usingDataScratchpad).B
val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits, 1 << lgMaxSize)(mpu_physaddr).homogeneous
// In M mode, if access DM address(debug module program buffer)
val deny_access_to_debug = mpu_priv <= PRV.M.U && p(DebugModuleKey).map(dmp => dmp.address.contains(mpu_physaddr)).getOrElse(false.B)
val prot_r = pma.io.resp.r && !deny_access_to_debug && pmp.io.r
val prot_w = pma.io.resp.w && !deny_access_to_debug && pmp.io.w
val prot_pp = pma.io.resp.pp
val prot_al = pma.io.resp.al
val prot_aa = pma.io.resp.aa
val prot_x = pma.io.resp.x && !deny_access_to_debug && pmp.io.x
val prot_eff = pma.io.resp.eff
// hit check
val sector_hits = sectored_entries(memIdx).map(_.sectorHit(vpn, priv_v))
val superpage_hits = superpage_entries.map(_.hit(vpn, priv_v))
val hitsVec = all_entries.map(vm_enabled && _.hit(vpn, priv_v))
val real_hits = hitsVec.asUInt
val hits = Cat(!vm_enabled, real_hits)
// use ptw response to refill
// permission bit arrays
when (do_refill) {
val pte = io.ptw.resp.bits.pte
val refill_v = r_vstage1_en || r_stage2_en
val newEntry = Wire(new TLBEntryData)
newEntry.ppn := pte.ppn
newEntry.c := cacheable
newEntry.u := pte.u
newEntry.g := pte.g && pte.v
newEntry.ae_ptw := io.ptw.resp.bits.ae_ptw
newEntry.ae_final := io.ptw.resp.bits.ae_final
newEntry.ae_stage2 := io.ptw.resp.bits.ae_final && io.ptw.resp.bits.gpa_is_pte && r_stage2_en
newEntry.pf := io.ptw.resp.bits.pf
newEntry.gf := io.ptw.resp.bits.gf
newEntry.hr := io.ptw.resp.bits.hr
newEntry.hw := io.ptw.resp.bits.hw
newEntry.hx := io.ptw.resp.bits.hx
newEntry.sr := pte.sr()
newEntry.sw := pte.sw()
newEntry.sx := pte.sx()
newEntry.pr := prot_r
newEntry.pw := prot_w
newEntry.px := prot_x
newEntry.ppp := prot_pp
newEntry.pal := prot_al
newEntry.paa := prot_aa
newEntry.eff := prot_eff
newEntry.fragmented_superpage := io.ptw.resp.bits.fragmented_superpage
// refill special_entry
when (special_entry.nonEmpty.B && !io.ptw.resp.bits.homogeneous) {
special_entry.foreach(_.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry))
}.elsewhen (io.ptw.resp.bits.level < (pgLevels-1).U) {
val waddr = Mux(r_superpage_hit.valid && usingHypervisor.B, r_superpage_hit.bits, r_superpage_repl_addr)
for ((e, i) <- superpage_entries.zipWithIndex) when (r_superpage_repl_addr === i.U) {
e.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry)
when (invalidate_refill) { e.invalidate() }
}
// refill sectored_hit
}.otherwise {
val r_memIdx = r_refill_tag.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2)
val waddr = Mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr)
for ((e, i) <- sectored_entries(r_memIdx).zipWithIndex) when (waddr === i.U) {
when (!r_sectored_hit.valid) { e.invalidate() }
e.insert(r_refill_tag, refill_v, 0.U, newEntry)
when (invalidate_refill) { e.invalidate() }
}
}
r_gpa_valid := io.ptw.resp.bits.gpa.valid
r_gpa := io.ptw.resp.bits.gpa.bits
r_gpa_is_pte := io.ptw.resp.bits.gpa_is_pte
}
// get all entries data.
val entries = all_entries.map(_.getData(vpn))
val normal_entries = entries.take(ordinary_entries.size)
// parallel query PPN from [[all_entries]], if VM not enabled return VPN instead
val ppn = Mux1H(hitsVec :+ !vm_enabled, (all_entries zip entries).map{ case (entry, data) => entry.ppn(vpn, data) } :+ vpn(ppnBits-1, 0))
val nPhysicalEntries = 1 + special_entry.size
// generally PTW misaligned load exception.
val ptw_ae_array = Cat(false.B, entries.map(_.ae_ptw).asUInt)
val final_ae_array = Cat(false.B, entries.map(_.ae_final).asUInt)
val ptw_pf_array = Cat(false.B, entries.map(_.pf).asUInt)
val ptw_gf_array = Cat(false.B, entries.map(_.gf).asUInt)
val sum = Mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum)
// if in hypervisor/machine mode, cannot read/write user entries.
// if in superviosr/user mode, "If the SUM bit in the sstatus register is set, supervisor mode software may also access pages with U=1.(from spec)"
val priv_rw_ok = Mux(!priv_s || sum, entries.map(_.u).asUInt, 0.U) | Mux(priv_s, ~entries.map(_.u).asUInt, 0.U)
// if in hypervisor/machine mode, other than user pages, all pages are executable.
// if in superviosr/user mode, only user page can execute.
val priv_x_ok = Mux(priv_s, ~entries.map(_.u).asUInt, entries.map(_.u).asUInt)
val stage1_bypass = Fill(entries.size, usingHypervisor.B) & (Fill(entries.size, !stage1_en) | entries.map(_.ae_stage2).asUInt)
val mxr = io.ptw.status.mxr | Mux(priv_v, io.ptw.gstatus.mxr, false.B)
// "The vsstatus field MXR, which makes execute-only pages readable, only overrides VS-stage page protection.(from spec)"
val r_array = Cat(true.B, (priv_rw_ok & (entries.map(_.sr).asUInt | Mux(mxr, entries.map(_.sx).asUInt, 0.U))) | stage1_bypass)
val w_array = Cat(true.B, (priv_rw_ok & entries.map(_.sw).asUInt) | stage1_bypass)
val x_array = Cat(true.B, (priv_x_ok & entries.map(_.sx).asUInt) | stage1_bypass)
val stage2_bypass = Fill(entries.size, !stage2_en)
val hr_array = Cat(true.B, entries.map(_.hr).asUInt | Mux(io.ptw.status.mxr, entries.map(_.hx).asUInt, 0.U) | stage2_bypass)
val hw_array = Cat(true.B, entries.map(_.hw).asUInt | stage2_bypass)
val hx_array = Cat(true.B, entries.map(_.hx).asUInt | stage2_bypass)
// These array is for each TLB entries.
// user mode can read: PMA OK, TLB OK, AE OK
val pr_array = Cat(Fill(nPhysicalEntries, prot_r), normal_entries.map(_.pr).asUInt) & ~(ptw_ae_array | final_ae_array)
// user mode can write: PMA OK, TLB OK, AE OK
val pw_array = Cat(Fill(nPhysicalEntries, prot_w), normal_entries.map(_.pw).asUInt) & ~(ptw_ae_array | final_ae_array)
// user mode can write: PMA OK, TLB OK, AE OK
val px_array = Cat(Fill(nPhysicalEntries, prot_x), normal_entries.map(_.px).asUInt) & ~(ptw_ae_array | final_ae_array)
// put effect
val eff_array = Cat(Fill(nPhysicalEntries, prot_eff), normal_entries.map(_.eff).asUInt)
// cacheable
val c_array = Cat(Fill(nPhysicalEntries, cacheable), normal_entries.map(_.c).asUInt)
// put partial
val ppp_array = Cat(Fill(nPhysicalEntries, prot_pp), normal_entries.map(_.ppp).asUInt)
// atomic arithmetic
val paa_array = Cat(Fill(nPhysicalEntries, prot_aa), normal_entries.map(_.paa).asUInt)
// atomic logic
val pal_array = Cat(Fill(nPhysicalEntries, prot_al), normal_entries.map(_.pal).asUInt)
val ppp_array_if_cached = ppp_array | c_array
val paa_array_if_cached = paa_array | (if(usingAtomicsInCache) c_array else 0.U)
val pal_array_if_cached = pal_array | (if(usingAtomicsInCache) c_array else 0.U)
val prefetchable_array = Cat((cacheable && homogeneous) << (nPhysicalEntries-1), normal_entries.map(_.c).asUInt)
// vaddr misaligned: vaddr[1:0]=b00
val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1.U)).orR
def badVA(guestPA: Boolean): Bool = {
val additionalPgLevels = (if (guestPA) io.ptw.hgatp else satp).additionalPgLevels
val extraBits = if (guestPA) hypervisorExtraAddrBits else 0
val signed = !guestPA
val nPgLevelChoices = pgLevels - minPgLevels + 1
val minVAddrBits = pgIdxBits + minPgLevels * pgLevelBits + extraBits
(for (i <- 0 until nPgLevelChoices) yield {
val mask = ((BigInt(1) << vaddrBitsExtended) - (BigInt(1) << (minVAddrBits + i * pgLevelBits - signed.toInt))).U
val maskedVAddr = io.req.bits.vaddr & mask
additionalPgLevels === i.U && !(maskedVAddr === 0.U || signed.B && maskedVAddr === mask)
}).orR
}
val bad_gpa =
if (!usingHypervisor) false.B
else vm_enabled && !stage1_en && badVA(true)
val bad_va =
if (!usingVM || (minPgLevels == pgLevels && vaddrBits == vaddrBitsExtended)) false.B
else vm_enabled && stage1_en && badVA(false)
val cmd_lrsc = usingAtomics.B && io.req.bits.cmd.isOneOf(M_XLR, M_XSC)
val cmd_amo_logical = usingAtomics.B && isAMOLogical(io.req.bits.cmd)
val cmd_amo_arithmetic = usingAtomics.B && isAMOArithmetic(io.req.bits.cmd)
val cmd_put_partial = io.req.bits.cmd === M_PWR
val cmd_read = isRead(io.req.bits.cmd)
val cmd_readx = usingHypervisor.B && io.req.bits.cmd === M_HLVX
val cmd_write = isWrite(io.req.bits.cmd)
val cmd_write_perms = cmd_write ||
io.req.bits.cmd.isOneOf(M_FLUSH_ALL, M_WOK) // not a write, but needs write permissions
val lrscAllowed = Mux((usingDataScratchpad || usingAtomicsOnlyForIO).B, 0.U, c_array)
val ae_array =
Mux(misaligned, eff_array, 0.U) |
Mux(cmd_lrsc, ~lrscAllowed, 0.U)
// access exception needs SoC information from PMA
val ae_ld_array = Mux(cmd_read, ae_array | ~pr_array, 0.U)
val ae_st_array =
Mux(cmd_write_perms, ae_array | ~pw_array, 0.U) |
Mux(cmd_put_partial, ~ppp_array_if_cached, 0.U) |
Mux(cmd_amo_logical, ~pal_array_if_cached, 0.U) |
Mux(cmd_amo_arithmetic, ~paa_array_if_cached, 0.U)
val must_alloc_array =
Mux(cmd_put_partial, ~ppp_array, 0.U) |
Mux(cmd_amo_logical, ~pal_array, 0.U) |
Mux(cmd_amo_arithmetic, ~paa_array, 0.U) |
Mux(cmd_lrsc, ~0.U(pal_array.getWidth.W), 0.U)
val pf_ld_array = Mux(cmd_read, ((~Mux(cmd_readx, x_array, r_array) & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array, 0.U)
val pf_st_array = Mux(cmd_write_perms, ((~w_array & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array, 0.U)
val pf_inst_array = ((~x_array & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array
val gf_ld_array = Mux(priv_v && cmd_read, (~Mux(cmd_readx, hx_array, hr_array) | ptw_gf_array) & ~ptw_ae_array, 0.U)
val gf_st_array = Mux(priv_v && cmd_write_perms, (~hw_array | ptw_gf_array) & ~ptw_ae_array, 0.U)
val gf_inst_array = Mux(priv_v, (~hx_array | ptw_gf_array) & ~ptw_ae_array, 0.U)
val gpa_hits = {
val need_gpa_mask = if (instruction) gf_inst_array else gf_ld_array | gf_st_array
val hit_mask = Fill(ordinary_entries.size, r_gpa_valid && r_gpa_vpn === vpn) | Fill(all_entries.size, !vstage1_en)
hit_mask | ~need_gpa_mask(all_entries.size-1, 0)
}
val tlb_hit_if_not_gpa_miss = real_hits.orR
val tlb_hit = (real_hits & gpa_hits).orR
// leads to s_request
val tlb_miss = vm_enabled && !vsatp_mode_mismatch && !bad_va && !tlb_hit
val sectored_plru = new SetAssocLRU(cfg.nSets, sectored_entries.head.size, "plru")
val superpage_plru = new PseudoLRU(superpage_entries.size)
when (io.req.valid && vm_enabled) {
// replace
when (sector_hits.orR) { sectored_plru.access(memIdx, OHToUInt(sector_hits)) }
when (superpage_hits.orR) { superpage_plru.access(OHToUInt(superpage_hits)) }
}
// Superpages create the possibility that two entries in the TLB may match.
// This corresponds to a software bug, but we can't return complete garbage;
// we must return either the old translation or the new translation. This
// isn't compatible with the Mux1H approach. So, flush the TLB and report
// a miss on duplicate entries.
val multipleHits = PopCountAtLeast(real_hits, 2)
// only pull up req.ready when this is s_ready state.
io.req.ready := state === s_ready
// page fault
io.resp.pf.ld := (bad_va && cmd_read) || (pf_ld_array & hits).orR
io.resp.pf.st := (bad_va && cmd_write_perms) || (pf_st_array & hits).orR
io.resp.pf.inst := bad_va || (pf_inst_array & hits).orR
// guest page fault
io.resp.gf.ld := (bad_gpa && cmd_read) || (gf_ld_array & hits).orR
io.resp.gf.st := (bad_gpa && cmd_write_perms) || (gf_st_array & hits).orR
io.resp.gf.inst := bad_gpa || (gf_inst_array & hits).orR
// access exception
io.resp.ae.ld := (ae_ld_array & hits).orR
io.resp.ae.st := (ae_st_array & hits).orR
io.resp.ae.inst := (~px_array & hits).orR
// misaligned
io.resp.ma.ld := misaligned && cmd_read
io.resp.ma.st := misaligned && cmd_write
io.resp.ma.inst := false.B // this is up to the pipeline to figure out
io.resp.cacheable := (c_array & hits).orR
io.resp.must_alloc := (must_alloc_array & hits).orR
io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB || m.supportsHint).B
io.resp.miss := do_refill || vsatp_mode_mismatch || tlb_miss || multipleHits
io.resp.paddr := Cat(ppn, io.req.bits.vaddr(pgIdxBits-1, 0))
io.resp.size := io.req.bits.size
io.resp.cmd := io.req.bits.cmd
io.resp.gpa_is_pte := vstage1_en && r_gpa_is_pte
io.resp.gpa := {
val page = Mux(!vstage1_en, Cat(bad_gpa, vpn), r_gpa >> pgIdxBits)
val offset = Mux(io.resp.gpa_is_pte, r_gpa(pgIdxBits-1, 0), io.req.bits.vaddr(pgIdxBits-1, 0))
Cat(page, offset)
}
io.ptw.req.valid := state === s_request
io.ptw.req.bits.valid := !io.kill
io.ptw.req.bits.bits.addr := r_refill_tag
io.ptw.req.bits.bits.vstage1 := r_vstage1_en
io.ptw.req.bits.bits.stage2 := r_stage2_en
io.ptw.req.bits.bits.need_gpa := r_need_gpa
if (usingVM) {
when(io.ptw.req.fire && io.ptw.req.bits.valid) {
r_gpa_valid := false.B
r_gpa_vpn := r_refill_tag
}
val sfence = io.sfence.valid
// this is [[s_ready]]
// handle miss/hit at the first cycle.
// if miss, request PTW(L2TLB).
when (io.req.fire && tlb_miss) {
state := s_request
r_refill_tag := vpn
r_need_gpa := tlb_hit_if_not_gpa_miss
r_vstage1_en := vstage1_en
r_stage2_en := stage2_en
r_superpage_repl_addr := replacementEntry(superpage_entries, superpage_plru.way)
r_sectored_repl_addr := replacementEntry(sectored_entries(memIdx), sectored_plru.way(memIdx))
r_sectored_hit.valid := sector_hits.orR
r_sectored_hit.bits := OHToUInt(sector_hits)
r_superpage_hit.valid := superpage_hits.orR
r_superpage_hit.bits := OHToUInt(superpage_hits)
}
// Handle SFENCE.VMA when send request to PTW.
// SFENCE.VMA io.ptw.req.ready kill
// ? ? 1
// 0 0 0
// 0 1 0 -> s_wait
// 1 0 0 -> s_wait_invalidate
// 1 0 0 -> s_ready
when (state === s_request) {
// SFENCE.VMA will kill TLB entries based on rs1 and rs2. It will take 1 cycle.
when (sfence) { state := s_ready }
// here should be io.ptw.req.fire, but assert(io.ptw.req.ready === true.B)
// fire -> s_wait
when (io.ptw.req.ready) { state := Mux(sfence, s_wait_invalidate, s_wait) }
// If CPU kills request(frontend.s2_redirect)
when (io.kill) { state := s_ready }
}
// sfence in refill will results in invalidate
when (state === s_wait && sfence) {
state := s_wait_invalidate
}
// after CPU acquire response, go back to s_ready.
when (io.ptw.resp.valid) {
state := s_ready
}
// SFENCE processing logic.
when (sfence) {
assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn)
for (e <- all_real_entries) {
val hv = usingHypervisor.B && io.sfence.bits.hv
val hg = usingHypervisor.B && io.sfence.bits.hg
when (!hg && io.sfence.bits.rs1) { e.invalidateVPN(vpn, hv) }
.elsewhen (!hg && io.sfence.bits.rs2) { e.invalidateNonGlobal(hv) }
.otherwise { e.invalidate(hv || hg) }
}
}
when(io.req.fire && vsatp_mode_mismatch) {
all_real_entries.foreach(_.invalidate(true.B))
v_entries_use_stage1 := vstage1_en
}
when (multipleHits || reset.asBool) {
all_real_entries.foreach(_.invalidate())
}
ccover(io.ptw.req.fire, "MISS", "TLB miss")
ccover(io.ptw.req.valid && !io.ptw.req.ready, "PTW_STALL", "TLB miss, but PTW busy")
ccover(state === s_wait_invalidate, "SFENCE_DURING_REFILL", "flush TLB during TLB refill")
ccover(sfence && !io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_ALL", "flush TLB")
ccover(sfence && !io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_ASID", "flush TLB ASID")
ccover(sfence && io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_LINE", "flush TLB line")
ccover(sfence && io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_LINE_ASID", "flush TLB line/ASID")
ccover(multipleHits, "MULTIPLE_HITS", "Two matching translations in TLB")
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"${if (instruction) "I" else "D"}TLB_$label", "MemorySystem;;" + desc)
/** Decides which entry to be replaced
*
* If there is a invalid entry, replace it with priorityencoder;
* if not, replace the alt entry
*
* @return mask for TLBEntry replacement
*/
def replacementEntry(set: Seq[TLBEntry], alt: UInt) = {
val valids = set.map(_.valid.orR).asUInt
Mux(valids.andR, alt, PriorityEncoder(~valids))
}
}
File TLBPermissions.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder}
import freechips.rocketchip.tilelink.TLManagerParameters
case class TLBPermissions(
homogeneous: Bool, // if false, the below are undefined
r: Bool, // readable
w: Bool, // writeable
x: Bool, // executable
c: Bool, // cacheable
a: Bool, // arithmetic ops
l: Bool) // logical ops
object TLBPageLookup
{
private case class TLBFixedPermissions(
e: Boolean, // get-/put-effects
r: Boolean, // readable
w: Boolean, // writeable
x: Boolean, // executable
c: Boolean, // cacheable
a: Boolean, // arithmetic ops
l: Boolean) { // logical ops
val useful = r || w || x || c || a || l
}
private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = {
val permissions = managers.map { m =>
(m.address, TLBFixedPermissions(
e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType,
r = m.supportsGet || m.supportsAcquireB, // if cached, never uses Get
w = m.supportsPutFull || m.supportsAcquireT, // if cached, never uses Put
x = m.executable,
c = m.supportsAcquireB,
a = m.supportsArithmetic,
l = m.supportsLogical))
}
permissions
.filter(_._2.useful) // get rid of no-permission devices
.groupBy(_._2) // group by permission type
.mapValues(seq =>
AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions
.toMap
}
// Unmapped memory is considered to be inhomogeneous
def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = {
require (isPow2(xLen) && xLen >= 8)
require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8)
require (isPow2(pageSize) && pageSize >= cacheBlockBytes)
val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes)
val allSizes = TransferSizes(1, maxRequestBytes)
val amoSizes = TransferSizes(4, xLen/8)
val permissions = managers.foreach { m =>
require (!m.supportsGet || m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}")
require (!m.supportsPutFull || m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}")
require (!m.supportsPutPartial || m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}")
require (!m.supportsAcquireB || m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}")
require (!m.supportsAcquireT || m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}")
require (!m.supportsLogical || m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}")
require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}")
require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)")
}
val grouped = groupRegions(managers)
.mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough
def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = {
val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) }
val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList)
// Find the minimal bits needed to distinguish between yes and no
val decisionMask = AddressDecoder(Seq(yes, no))
def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct)
val (yesf, nof) = (simplify(yes), simplify(no))
if (yesf.size < no.size) {
(x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ || _)
} else {
(x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ || _)
}
}
// Derive simplified property circuits (don't care when !homo)
val rfn = lowCostProperty(_.r)
val wfn = lowCostProperty(_.w)
val xfn = lowCostProperty(_.x)
val cfn = lowCostProperty(_.c)
val afn = lowCostProperty(_.a)
val lfn = lowCostProperty(_.l)
val homo = AddressSet.unify(grouped.values.flatten.toList)
(x: UInt) => TLBPermissions(
homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ || _),
r = rfn(x),
w = wfn(x),
x = xfn(x),
c = cfn(x),
a = afn(x),
l = lfn(x))
}
// Are all pageSize intervals of mapped regions homogeneous?
def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = {
groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize))
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File PTW.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch}
import chisel3.withClock
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.subsystem.CacheBlockBytes
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
import scala.collection.mutable.ListBuffer
/** PTE request from TLB to PTW
*
* TLB send a PTE request to PTW when L1TLB miss
*/
class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
val addr = UInt(vpnBits.W)
val need_gpa = Bool()
val vstage1 = Bool()
val stage2 = Bool()
}
/** PTE info from L2TLB to TLB
*
* containing: target PTE, exceptions, two-satge tanslation info
*/
class PTWResp(implicit p: Parameters) extends CoreBundle()(p) {
/** ptw access exception */
val ae_ptw = Bool()
/** final access exception */
val ae_final = Bool()
/** page fault */
val pf = Bool()
/** guest page fault */
val gf = Bool()
/** hypervisor read */
val hr = Bool()
/** hypervisor write */
val hw = Bool()
/** hypervisor execute */
val hx = Bool()
/** PTE to refill L1TLB
*
* source: L2TLB
*/
val pte = new PTE
/** pte pglevel */
val level = UInt(log2Ceil(pgLevels).W)
/** fragmented_superpage support */
val fragmented_superpage = Bool()
/** homogeneous for both pma and pmp */
val homogeneous = Bool()
val gpa = Valid(UInt(vaddrBits.W))
val gpa_is_pte = Bool()
}
/** IO between TLB and PTW
*
* PTW receives :
* - PTE request
* - CSRs info
* - pmp results from PMP(in TLB)
*/
class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
val req = Decoupled(Valid(new PTWReq))
val resp = Flipped(Valid(new PTWResp))
val ptbr = Input(new PTBR())
val hgatp = Input(new PTBR())
val vsatp = Input(new PTBR())
val status = Input(new MStatus())
val hstatus = Input(new HStatus())
val gstatus = Input(new MStatus())
val pmp = Input(Vec(nPMPs, new PMP))
val customCSRs = Flipped(coreParams.customCSRs)
}
/** PTW performance statistics */
class PTWPerfEvents extends Bundle {
val l2miss = Bool()
val l2hit = Bool()
val pte_miss = Bool()
val pte_hit = Bool()
}
/** Datapath IO between PTW and Core
*
* PTW receives CSRs info, pmp checks, sfence instruction info
*
* PTW sends its performance statistics to core
*/
class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
val ptbr = Input(new PTBR())
val hgatp = Input(new PTBR())
val vsatp = Input(new PTBR())
val sfence = Flipped(Valid(new SFenceReq))
val status = Input(new MStatus())
val hstatus = Input(new HStatus())
val gstatus = Input(new MStatus())
val pmp = Input(Vec(nPMPs, new PMP))
val perf = Output(new PTWPerfEvents())
val customCSRs = Flipped(coreParams.customCSRs)
/** enable clock generated by ptw */
val clock_enabled = Output(Bool())
}
/** PTE template for transmission
*
* contains useful methods to check PTE attributes
* @see RV-priv spec 4.3.1 for pgae table entry format
*/
class PTE(implicit p: Parameters) extends CoreBundle()(p) {
val reserved_for_future = UInt(10.W)
val ppn = UInt(44.W)
val reserved_for_software = Bits(2.W)
/** dirty bit */
val d = Bool()
/** access bit */
val a = Bool()
/** global mapping */
val g = Bool()
/** user mode accessible */
val u = Bool()
/** whether the page is executable */
val x = Bool()
/** whether the page is writable */
val w = Bool()
/** whether the page is readable */
val r = Bool()
/** valid bit */
val v = Bool()
/** return true if find a pointer to next level page table */
def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U
/** return true if find a leaf PTE */
def leaf(dummy: Int = 0) = v && (r || (x && !w)) && a
/** user read */
def ur(dummy: Int = 0) = sr() && u
/** user write*/
def uw(dummy: Int = 0) = sw() && u
/** user execute */
def ux(dummy: Int = 0) = sx() && u
/** supervisor read */
def sr(dummy: Int = 0) = leaf() && r
/** supervisor write */
def sw(dummy: Int = 0) = leaf() && w && d
/** supervisor execute */
def sx(dummy: Int = 0) = leaf() && x
/** full permission: writable and executable in user mode */
def isFullPerm(dummy: Int = 0) = uw() && ux()
}
/** L2TLB PTE template
*
* contains tag bits
* @param nSets number of sets in L2TLB
* @see RV-priv spec 4.3.1 for page table entry format
*/
class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
val idxBits = log2Ceil(nSets)
val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0)
val tag = UInt(tagBits.W)
val ppn = UInt(ppnBits.W)
/** dirty bit */
val d = Bool()
/** access bit */
val a = Bool()
/** user mode accessible */
val u = Bool()
/** whether the page is executable */
val x = Bool()
/** whether the page is writable */
val w = Bool()
/** whether the page is readable */
val r = Bool()
}
/** PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC)
*
* It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb.
* Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process.
*
* ==Structure==
* - l2tlb : for leaf PTEs
* - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]]))
* - PLRU
* - pte_cache: for non-leaf PTEs
* - set-associative
* - LRU
* - s2_pte_cache: for non-leaf PTEs in 2-stage translation
* - set-associative
* - PLRU
*
* l2tlb Pipeline: 3 stage
* {{{
* stage 0 : read
* stage 1 : decode
* stage 2 : hit check
* }}}
* ==State Machine==
* s_ready: ready to reveive request from TLB
* s_req: request mem; pte_cache hit judge
* s_wait1: deal with l2tlb error
* s_wait2: final hit judge
* s_wait3: receive mem response
* s_fragment_superpage: for superpage PTE
*
* @note l2tlb hit happens in s_req or s_wait1
* @see RV-priv spec 4.3-4.6 for Virtual-Memory System
* @see RV-priv spec 8.5 for Two-Stage Address Translation
* @todo details in two-stage translation
*/
class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
val io = IO(new Bundle {
/** to n TLB */
val requestor = Flipped(Vec(n, new TLBPTWIO))
/** to HellaCache */
val mem = new HellaCacheIO
/** to Core
*
* contains CSRs info and performance statistics
*/
val dpath = new DatapathPTWIO
})
val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8)
val state = RegInit(s_ready)
val l2_refill_wire = Wire(Bool())
/** Arbiter to arbite request from n TLB */
val arb = Module(new Arbiter(Valid(new PTWReq), n))
// use TLB req as arbitor's input
arb.io.in <> io.requestor.map(_.req)
// receive req only when s_ready and not in refill
arb.io.out.ready := (state === s_ready) && !l2_refill_wire
val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B)))
val clock_en = state =/= s_ready || l2_refill_wire || arb.io.out.valid || io.dpath.sfence.valid || io.dpath.customCSRs.disableDCacheClockGate
io.dpath.clock_enabled := usingVM.B && clock_en
val gated_clock =
if (!usingVM || !tileParams.dcache.get.clockGate) clock
else ClockGate(clock, clock_en, "ptw_clock_gate")
withClock (gated_clock) { // entering gated-clock domain
val invalidated = Reg(Bool())
/** current PTE level
* {{{
* 0 <= count <= pgLevel-1
* count = pgLevel - 1 : leaf PTE
* count < pgLevel - 1 : non-leaf PTE
* }}}
*/
val count = Reg(UInt(log2Ceil(pgLevels).W))
val resp_ae_ptw = Reg(Bool())
val resp_ae_final = Reg(Bool())
val resp_pf = Reg(Bool())
val resp_gf = Reg(Bool())
val resp_hr = Reg(Bool())
val resp_hw = Reg(Bool())
val resp_hx = Reg(Bool())
val resp_fragmented_superpage = Reg(Bool())
/** tlb request */
val r_req = Reg(new PTWReq)
/** current selected way in arbitor */
val r_req_dest = Reg(Bits())
// to respond to L1TLB : l2_hit
// to construct mem.req.addr
val r_pte = Reg(new PTE)
val r_hgatp = Reg(new PTBR)
// 2-stage pageLevel
val aux_count = Reg(UInt(log2Ceil(pgLevels).W))
/** pte for 2-stage translation */
val aux_pte = Reg(new PTE)
val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case
val stage2 = Reg(Bool())
val stage2_final = Reg(Bool())
val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr)
val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels
/** 2-stage translation both enable */
val do_both_stages = r_req.vstage1 && r_req.stage2
val max_count = count max aux_count
val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr)
val mem_resp_valid = RegNext(io.mem.resp.valid)
val mem_resp_data = RegNext(io.mem.resp.bits.data)
io.mem.uncached_resp.map { resp =>
assert(!(resp.valid && io.mem.resp.valid))
resp.ready := true.B
when (resp.valid) {
mem_resp_valid := true.B
mem_resp_data := resp.bits.data
}
}
// construct pte from mem.resp
val (pte, invalid_paddr, invalid_gpa) = {
val tmp = mem_resp_data.asTypeOf(new PTE())
val res = WireDefault(tmp)
res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0))
when (tmp.r || tmp.w || tmp.x) {
// for superpage mappings, make sure PPN LSBs are zero
for (i <- 0 until pgLevels-1)
when (count <= i.U && tmp.ppn((pgLevels-1-i)*pgLevelBits-1, (pgLevels-2-i)*pgLevelBits) =/= 0.U) { res.v := false.B }
}
(res,
Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U),
do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn))
}
// find non-leaf PTE, need traverse
val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U
/** address send to mem for enquerry */
val pte_addr = if (!usingVM) 0.U else {
val vpn_idxs = (0 until pgLevels).map { i =>
val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0)
(vpn >> (pgLevels - i - 1) * pgLevelBits)(width - 1, 0)
}
val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U)
val vpn_idx = vpn_idxs(count) & mask
val raw_pte_addr = ((r_pte.ppn << pgLevelBits) | vpn_idx) << log2Ceil(xLen / 8)
val size = if (usingHypervisor) vaddrBits else paddrBits
//use r_pte.ppn as page table base address
//use vpn slice as offset
raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0)
}
/** stage2_pte_cache input addr */
val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else {
val vpn_idxs = (0 until pgLevels - 1).map { i =>
(r_req.addr >> (pgLevels - i - 1) * pgLevelBits)(pgLevelBits - 1, 0)
}
val vpn_idx = vpn_idxs(aux_count)
val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8)
raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0)
}
def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = {
(pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBits*i), r_req.addr(((pgLevelBits*i) min vpnBits)-1, 0).padTo(pgLevelBits*i)))
}
/** PTECache caches non-leaf PTE
* @param s2 true: 2-stage address translation
*/
def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) {
(false.B, 0.U)
} else {
val plru = new PseudoLRU(coreParams.nPTECacheEntries)
val valid = RegInit(0.U(coreParams.nPTECacheEntries.W))
val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W)))
// not include full pte, only ppn
val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W)))
val can_hit =
if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final
else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2)
val can_refill =
if (s2) do_both_stages && !stage2 && !stage2_final
else can_hit
val tag =
if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits))
else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits))
val hits = tags.map(_ === tag).asUInt & valid
val hit = hits.orR && can_hit
// refill with mem response
when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) {
val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid))
valid := valid | UIntToOH(r)
tags(r) := tag
data(r) := pte.ppn
plru.access(r)
}
// replace
when (hit && state === s_req) { plru.access(OHToUInt(hits)) }
when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 || usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U }
val lcount = if (s2) aux_count else count
for (i <- 0 until pgLevels-1) {
ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i")
}
(hit, Mux1H(hits, data))
}
// generate pte_cache
val (pte_cache_hit, pte_cache_data) = makePTECache(false)
// generate pte_cache with 2-stage translation
val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true)
// pte_cache hit or 2-stage pte_cache hit
val pte_hit = RegNext(false.B)
io.dpath.perf.pte_miss := false.B
io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit
assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)),
"PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event")
// l2_refill happens when find the leaf pte
val l2_refill = RegNext(false.B)
l2_refill_wire := l2_refill
io.dpath.perf.l2miss := false.B
io.dpath.perf.l2hit := false.B
// l2tlb
val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else {
val code = new ParityCode
require(isPow2(coreParams.nL2TLBEntries))
require(isPow2(coreParams.nL2TLBWays))
require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays)
val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays
require(isPow2(nL2TLBSets))
val idxBits = log2Ceil(nL2TLBSets)
val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru")
val ram = DescribedSRAM(
name = "l2_tlb_ram",
desc = "L2 TLB",
size = nL2TLBSets,
data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W))
)
val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W)))
val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W))))
// use r_req to construct tag
val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits)
/** the valid vec for the selected set(including n ways) */
val r_valid_vec = valid.map(_(r_idx)).asUInt
val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W))
val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W))
r_valid_vec_q := r_valid_vec
// replacement way
r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U)
// refill with r_pte(leaf pte)
when (l2_refill && !invalidated) {
val entry = Wire(new L2TLBEntry(nL2TLBSets))
entry.ppn := r_pte.ppn
entry.d := r_pte.d
entry.a := r_pte.a
entry.u := r_pte.u
entry.x := r_pte.x
entry.w := r_pte.w
entry.r := r_pte.r
entry.tag := r_tag
// if all the way are valid, use plru to select one way to be replaced,
// otherwise use PriorityEncoderOH to select one
val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W)
ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools)
val mask = UIntToOH(r_idx)
for (way <- 0 until coreParams.nL2TLBWays) {
when (wmask(way)) {
valid(way) := valid(way) | mask
g(way) := Mux(r_pte.g, g(way) | mask, g(way) & ~mask)
}
}
}
// sfence happens
when (io.dpath.sfence.valid) {
val hg = usingHypervisor.B && io.dpath.sfence.bits.hg
for (way <- 0 until coreParams.nL2TLBWays) {
valid(way) :=
Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)),
Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way),
0.U))
}
}
val s0_valid = !l2_refill && arb.io.out.fire
val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa
val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid)
val s2_valid = RegNext(s1_valid)
// read from tlb idx
val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid)
val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid)))
val s2_valid_vec = RegEnable(r_valid_vec, s1_valid)
val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid)
val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR
when (s2_valid && s2_error) { valid.foreach { _ := 0.U }}
// decode
val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets)))
val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag))
val s2_hit = s2_valid && s2_hit_vec.orR
io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR)
io.dpath.perf.l2hit := s2_hit
when (s2_hit) {
l2_plru.access(r_idx, OHToUInt(s2_hit_vec))
assert((PopCount(s2_hit_vec) === 1.U) || s2_error, "L2 TLB multi-hit")
}
val s2_pte = Wire(new PTE)
val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec)
s2_pte.ppn := s2_hit_entry.ppn
s2_pte.d := s2_hit_entry.d
s2_pte.a := s2_hit_entry.a
s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec)
s2_pte.u := s2_hit_entry.u
s2_pte.x := s2_hit_entry.x
s2_pte.w := s2_hit_entry.w
s2_pte.r := s2_hit_entry.r
s2_pte.v := true.B
s2_pte.reserved_for_future := 0.U
s2_pte.reserved_for_software := 0.U
for (way <- 0 until coreParams.nL2TLBWays) {
ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way")
}
(s2_hit, s2_error, s2_pte, Some(ram))
}
// if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk
invalidated := io.dpath.sfence.valid || (invalidated && state =/= s_ready)
// mem request
io.mem.keep_clock_enabled := false.B
io.mem.req.valid := state === s_req || state === s_dummy1
io.mem.req.bits.phys := true.B
io.mem.req.bits.cmd := M_XRD
io.mem.req.bits.size := log2Ceil(xLen/8).U
io.mem.req.bits.signed := false.B
io.mem.req.bits.addr := pte_addr
io.mem.req.bits.idx.foreach(_ := pte_addr)
io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition
io.mem.req.bits.dv := do_both_stages && !stage2
io.mem.req.bits.tag := DontCare
io.mem.req.bits.no_resp := false.B
io.mem.req.bits.no_alloc := DontCare
io.mem.req.bits.no_xcpt := DontCare
io.mem.req.bits.data := DontCare
io.mem.req.bits.mask := DontCare
io.mem.s1_kill := l2_hit || (state =/= s_wait1) || resp_gf
io.mem.s1_data := DontCare
io.mem.s2_kill := false.B
val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits)
require(!usingHypervisor || pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}")
val pmaPgLevelHomogeneous = (0 until pgLevels) map { i =>
val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) * pgLevelBits))
if (pageGranularityPMPs && i == pgLevels - 1) {
require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned")
true.B
} else {
TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous
}
}
val pmaHomogeneous = pmaPgLevelHomogeneous(count)
val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count)
val homogeneous = pmaHomogeneous && pmpHomogeneous
// response to tlb
for (i <- 0 until io.requestor.size) {
io.requestor(i).resp.valid := resp_valid(i)
io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw
io.requestor(i).resp.bits.ae_final := resp_ae_final
io.requestor(i).resp.bits.pf := resp_pf
io.requestor(i).resp.bits.gf := resp_gf
io.requestor(i).resp.bits.hr := resp_hr
io.requestor(i).resp.bits.hw := resp_hw
io.requestor(i).resp.bits.hx := resp_hx
io.requestor(i).resp.bits.pte := r_pte
io.requestor(i).resp.bits.level := max_count
io.requestor(i).resp.bits.homogeneous := homogeneous || pageGranularityPMPs.B
io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B
io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa
io.requestor(i).resp.bits.gpa.bits :=
Cat(Mux(!stage2_final || !r_req.vstage1 || aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff)
io.requestor(i).resp.bits.gpa_is_pte := !stage2_final
io.requestor(i).ptbr := io.dpath.ptbr
io.requestor(i).hgatp := io.dpath.hgatp
io.requestor(i).vsatp := io.dpath.vsatp
io.requestor(i).customCSRs <> io.dpath.customCSRs
io.requestor(i).status := io.dpath.status
io.requestor(i).hstatus := io.dpath.hstatus
io.requestor(i).gstatus := io.dpath.gstatus
io.requestor(i).pmp := io.dpath.pmp
}
// control state machine
val next_state = WireDefault(state)
state := OptimizationBarrier(next_state)
val do_switch = WireDefault(false.B)
switch (state) {
is (s_ready) {
when (arb.io.out.fire) {
val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels
val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels
val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels
val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr)
r_req := arb.io.out.bits.bits
r_req_dest := arb.io.chosen
next_state := Mux(arb.io.out.bits.valid, s_req, s_ready)
stage2 := arb.io.out.bits.bits.stage2
stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1
count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count)
aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U)
aux_pte.ppn := aux_ppn
aux_pte.reserved_for_future := 0.U
resp_ae_ptw := false.B
resp_ae_final := false.B
resp_pf := false.B
resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2
resp_hr := true.B
resp_hw := true.B
resp_hx := true.B
resp_fragmented_superpage := false.B
r_hgatp := io.dpath.hgatp
assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2)
}
}
is (s_req) {
when(stage2 && count === r_hgatp_initial_count) {
gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr)
}
// pte_cache hit
when (stage2_pte_cache_hit) {
aux_count := aux_count + 1.U
aux_pte.ppn := stage2_pte_cache_data
aux_pte.reserved_for_future := 0.U
pte_hit := true.B
}.elsewhen (pte_cache_hit) {
count := count + 1.U
pte_hit := true.B
}.otherwise {
next_state := Mux(io.mem.req.ready, s_wait1, s_req)
}
when(resp_gf) {
next_state := s_ready
resp_valid(r_req_dest) := true.B
}
}
is (s_wait1) {
// This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below
next_state := Mux(l2_hit, s_req, s_wait2)
}
is (s_wait2) {
next_state := s_wait3
io.dpath.perf.pte_miss := count < (pgLevels-1).U
when (io.mem.s2_xcpt.ae.ld) {
resp_ae_ptw := true.B
next_state := s_ready
resp_valid(r_req_dest) := true.B
}
}
is (s_fragment_superpage) {
next_state := s_ready
resp_valid(r_req_dest) := true.B
when (!homogeneous) {
count := (pgLevels-1).U
resp_fragmented_superpage := true.B
}
when (do_both_stages) {
resp_fragmented_superpage := true.B
}
}
}
val merged_pte = {
val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)*pgLevelBits)).U)
val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U))
val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), aux_pte.ppn((pgLevels-i-1)*pgLevelBits-1,0))) :+ pte.ppn
val stage1_ppn = stage1_ppns(count)
makePTE(stage1_ppn & superpage_mask, aux_pte)
}
r_pte := OptimizationBarrier(
// l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB
Mux(l2_hit && !l2_error && !resp_gf, l2_pte,
// S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp
Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte),
// pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem
Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte),
// 2-stage translation
Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte),
// when mem respond, store mem.resp.pte
Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte),
// fragment_superpage
Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte),
// when tlb request come->request mem, use root address in satp(or vsatp,hgatp)
Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)),
r_pte))))))))
when (l2_hit && !l2_error && !resp_gf) {
assert(state === s_req || state === s_wait1)
next_state := s_ready
resp_valid(r_req_dest) := true.B
count := (pgLevels-1).U
}
when (mem_resp_valid) {
assert(state === s_wait3)
next_state := s_req
when (traverse) {
when (do_both_stages && !stage2) { do_switch := true.B }
count := count + 1.U
}.otherwise {
val gf = (stage2 && !stage2_final && !pte.ur()) || (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa)
val ae = pte.v && invalid_paddr
val pf = pte.v && pte.reserved_for_future =/= 0.U
val success = pte.v && !ae && !pf && !gf
when (do_both_stages && !stage2_final && success) {
when (stage2) {
stage2 := false.B
count := aux_count
}.otherwise {
stage2_final := true.B
do_switch := true.B
}
}.otherwise {
// find a leaf pte, start l2 refill
l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa &&
(!r_req.vstage1 && !r_req.stage2 ||
do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm())
count := max_count
when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages || aux_count === (pgLevels-1).U))) {
next_state := s_fragment_superpage
}.otherwise {
next_state := s_ready
resp_valid(r_req_dest) := true.B
}
resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table()
resp_ae_final := ae && pte.leaf()
resp_pf := pf && !stage2
resp_gf := gf || (pf && stage2)
resp_hr := !stage2 || (!pf && !gf && pte.ur())
resp_hw := !stage2 || (!pf && !gf && pte.uw())
resp_hx := !stage2 || (!pf && !gf && pte.ux())
}
}
}
when (io.mem.s2_nack) {
assert(state === s_wait2)
next_state := s_req
}
when (do_switch) {
aux_count := Mux(traverse, count + 1.U, count)
count := r_hgatp_initial_count
aux_pte := Mux(traverse, pte, {
val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), r_req.addr(((pgLevels-i-1)*pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)*pgLevelBits))) :+ pte.ppn
makePTE(s1_ppns(count), pte)
})
stage2 := true.B
}
for (i <- 0 until pgLevels) {
val leaf = mem_resp_valid && !traverse && count === i.U
ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i")
ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i")
ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i")
ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i")
ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i")
if (i != pgLevels-1)
ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i")
}
ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep")
ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access")
ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table")
} // leaving gated-clock domain
private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc)
/** Relace PTE.ppn with ppn */
private def makePTE(ppn: UInt, default: PTE) = {
val pte = WireDefault(default)
pte.ppn := ppn
pte
}
/** use hgatp and vpn to construct a new ppn */
private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = {
val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels
val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)*pgLevelBits))
val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count))
val pte = WireDefault(default)
pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs)
pte
}
/** use hgatp and vpn to check for gpa out of range */
private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = {
val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels
val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)*pgLevelBits)+maxHypervisorExtraAddrBits))
idxs.extract(count) =/= 0.U
}
}
/** Mix-ins for constructing tiles that might have a PTW */
trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile =>
val module: CanHavePTWModule
var nPTWPorts = 1
nDCachePorts += usingPTW.toInt
}
trait CanHavePTWModule extends HasHellaCacheModule {
val outer: CanHavePTW
val ptwPorts = ListBuffer(outer.dcache.module.io.ptw)
val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p))
ptw.io.mem <> DontCare
if (outer.usingPTW) {
dcachePorts += ptw.io.mem
}
}
|
module DTLB( // @[TLB.scala:318:7]
input clock, // @[TLB.scala:318:7]
input reset, // @[TLB.scala:318:7]
input io_req_valid, // @[TLB.scala:320:14]
input [33:0] io_req_bits_vaddr, // @[TLB.scala:320:14]
input io_req_bits_passthrough, // @[TLB.scala:320:14]
input [1:0] io_req_bits_size, // @[TLB.scala:320:14]
input [4:0] io_req_bits_cmd, // @[TLB.scala:320:14]
input [1:0] io_req_bits_prv, // @[TLB.scala:320:14]
input io_req_bits_v, // @[TLB.scala:320:14]
output [31:0] io_resp_paddr, // @[TLB.scala:320:14]
output [33:0] io_resp_gpa, // @[TLB.scala:320:14]
output io_resp_pf_ld, // @[TLB.scala:320:14]
output io_resp_pf_st, // @[TLB.scala:320:14]
output io_resp_pf_inst, // @[TLB.scala:320:14]
output io_resp_ae_ld, // @[TLB.scala:320:14]
output io_resp_ae_st, // @[TLB.scala:320:14]
output io_resp_ae_inst, // @[TLB.scala:320:14]
output io_resp_ma_ld, // @[TLB.scala:320:14]
output io_resp_ma_st, // @[TLB.scala:320:14]
output io_resp_cacheable, // @[TLB.scala:320:14]
output io_resp_must_alloc, // @[TLB.scala:320:14]
output io_resp_prefetchable, // @[TLB.scala:320:14]
output [1:0] io_resp_size, // @[TLB.scala:320:14]
output [4:0] io_resp_cmd, // @[TLB.scala:320:14]
input io_sfence_valid, // @[TLB.scala:320:14]
input io_sfence_bits_rs1, // @[TLB.scala:320:14]
input io_sfence_bits_rs2, // @[TLB.scala:320:14]
input [32:0] io_sfence_bits_addr, // @[TLB.scala:320:14]
input io_sfence_bits_asid, // @[TLB.scala:320:14]
input io_sfence_bits_hv, // @[TLB.scala:320:14]
input io_sfence_bits_hg, // @[TLB.scala:320:14]
input io_ptw_req_ready, // @[TLB.scala:320:14]
output [20:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14]
output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14]
output io_ptw_req_bits_bits_vstage1, // @[TLB.scala:320:14]
output io_ptw_req_bits_bits_stage2, // @[TLB.scala:320:14]
input io_ptw_resp_valid, // @[TLB.scala:320:14]
input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14]
input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pf, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gf, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hr, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hw, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hx, // @[TLB.scala:320:14]
input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14]
input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14]
input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14]
input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14]
input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14]
input [32:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14]
input io_ptw_status_debug, // @[TLB.scala:320:14]
input io_ptw_status_cease, // @[TLB.scala:320:14]
input io_ptw_status_wfi, // @[TLB.scala:320:14]
input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14]
input io_ptw_status_dv, // @[TLB.scala:320:14]
input io_ptw_status_v, // @[TLB.scala:320:14]
input io_ptw_status_sd, // @[TLB.scala:320:14]
input io_ptw_status_mpv, // @[TLB.scala:320:14]
input io_ptw_status_gva, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14]
input io_ptw_status_mpie, // @[TLB.scala:320:14]
input io_ptw_status_mie, // @[TLB.scala:320:14]
input io_ptw_gstatus_debug, // @[TLB.scala:320:14]
input io_ptw_gstatus_cease, // @[TLB.scala:320:14]
input io_ptw_gstatus_wfi, // @[TLB.scala:320:14]
input [31:0] io_ptw_gstatus_isa, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_dprv, // @[TLB.scala:320:14]
input io_ptw_gstatus_dv, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_prv, // @[TLB.scala:320:14]
input io_ptw_gstatus_v, // @[TLB.scala:320:14]
input io_ptw_gstatus_sd, // @[TLB.scala:320:14]
input [22:0] io_ptw_gstatus_zero2, // @[TLB.scala:320:14]
input io_ptw_gstatus_mpv, // @[TLB.scala:320:14]
input io_ptw_gstatus_gva, // @[TLB.scala:320:14]
input io_ptw_gstatus_mbe, // @[TLB.scala:320:14]
input io_ptw_gstatus_sbe, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_sxl, // @[TLB.scala:320:14]
input [7:0] io_ptw_gstatus_zero1, // @[TLB.scala:320:14]
input io_ptw_gstatus_tsr, // @[TLB.scala:320:14]
input io_ptw_gstatus_tw, // @[TLB.scala:320:14]
input io_ptw_gstatus_tvm, // @[TLB.scala:320:14]
input io_ptw_gstatus_mxr, // @[TLB.scala:320:14]
input io_ptw_gstatus_sum, // @[TLB.scala:320:14]
input io_ptw_gstatus_mprv, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_fs, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_mpp, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_vs, // @[TLB.scala:320:14]
input io_ptw_gstatus_spp, // @[TLB.scala:320:14]
input io_ptw_gstatus_mpie, // @[TLB.scala:320:14]
input io_ptw_gstatus_ube, // @[TLB.scala:320:14]
input io_ptw_gstatus_spie, // @[TLB.scala:320:14]
input io_ptw_gstatus_upie, // @[TLB.scala:320:14]
input io_ptw_gstatus_mie, // @[TLB.scala:320:14]
input io_ptw_gstatus_hie, // @[TLB.scala:320:14]
input io_ptw_gstatus_sie, // @[TLB.scala:320:14]
input io_ptw_gstatus_uie, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_0_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_0_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_0_value, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_1_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_1_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_1_value, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_2_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_2_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_2_value, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_3_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_3_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_3_value // @[TLB.scala:320:14]
);
wire _entries_barrier_12_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_c; // @[package.scala:267:25]
wire _entries_barrier_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_io_y_c; // @[package.scala:267:25]
wire _pma_io_resp_r; // @[TLB.scala:422:19]
wire _pma_io_resp_w; // @[TLB.scala:422:19]
wire _pma_io_resp_pp; // @[TLB.scala:422:19]
wire _pma_io_resp_al; // @[TLB.scala:422:19]
wire _pma_io_resp_aa; // @[TLB.scala:422:19]
wire _pma_io_resp_x; // @[TLB.scala:422:19]
wire _pma_io_resp_eff; // @[TLB.scala:422:19]
wire _pmp_io_r; // @[TLB.scala:416:19]
wire _pmp_io_w; // @[TLB.scala:416:19]
wire _pmp_io_x; // @[TLB.scala:416:19]
wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7]
wire [33:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7]
wire io_req_bits_passthrough_0 = io_req_bits_passthrough; // @[TLB.scala:318:7]
wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[TLB.scala:318:7]
wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[TLB.scala:318:7]
wire [1:0] io_req_bits_prv_0 = io_req_bits_prv; // @[TLB.scala:318:7]
wire io_req_bits_v_0 = io_req_bits_v; // @[TLB.scala:318:7]
wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7]
wire io_sfence_bits_rs1_0 = io_sfence_bits_rs1; // @[TLB.scala:318:7]
wire io_sfence_bits_rs2_0 = io_sfence_bits_rs2; // @[TLB.scala:318:7]
wire [32:0] io_sfence_bits_addr_0 = io_sfence_bits_addr; // @[TLB.scala:318:7]
wire io_sfence_bits_asid_0 = io_sfence_bits_asid; // @[TLB.scala:318:7]
wire io_sfence_bits_hv_0 = io_sfence_bits_hv; // @[TLB.scala:318:7]
wire io_sfence_bits_hg_0 = io_sfence_bits_hg; // @[TLB.scala:318:7]
wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7]
wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7]
wire [32:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7]
wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7]
wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7]
wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7]
wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7]
wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7]
wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7]
wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7]
wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7]
wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7]
wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7]
wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[TLB.scala:318:7]
wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[TLB.scala:318:7]
wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[TLB.scala:318:7]
wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[TLB.scala:318:7]
wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[TLB.scala:318:7]
wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sd_0 = io_ptw_gstatus_sd; // @[TLB.scala:318:7]
wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[TLB.scala:318:7]
wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[TLB.scala:318:7]
wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[TLB.scala:318:7]
wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[TLB.scala:318:7]
wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[TLB.scala:318:7]
wire [41:0] _mpu_ppn_WIRE_1 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_1 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_3 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_5 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_7 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_9 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_11 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_13 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_15 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_17 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_19 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_21 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_23 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] _entries_WIRE_25 = 42'h0; // @[TLB.scala:170:77]
wire [20:0] io_ptw_req_bits_bits_addr_0 = 21'h0; // @[TLB.scala:318:7, :339:29]
wire [20:0] _io_resp_gpa_page_T_2 = 21'h0; // @[TLB.scala:339:29, :657:58]
wire [11:0] _io_resp_gpa_offset_T = 12'h0; // @[TLB.scala:658:47]
wire [13:0] hits = 14'h2000; // @[TLB.scala:442:17]
wire [19:0] _ppn_T_2 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_3 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_4 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_5 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_6 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_7 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_8 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_9 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_10 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_11 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_12 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_13 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_14 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_16 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_17 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_18 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_19 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_20 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_21 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_22 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_23 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_24 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_25 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_26 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_27 = 20'h0; // @[Mux.scala:30:73]
wire [13:0] hr_array = 14'h3FFF; // @[TLB.scala:524:21]
wire [13:0] hw_array = 14'h3FFF; // @[TLB.scala:525:21]
wire [13:0] hx_array = 14'h3FFF; // @[TLB.scala:526:21]
wire [13:0] _ae_array_T_1 = 14'h3FFF; // @[TLB.scala:583:19]
wire [13:0] _must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19]
wire [13:0] _gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50]
wire [12:0] _stage1_bypass_T_2 = 13'h1FFF; // @[TLB.scala:517:{68,95}, :523:27, :524:111, :525:55, :526:55, :606:{82,88}, :607:{14,16}]
wire [12:0] _stage1_bypass_T_4 = 13'h1FFF; // @[TLB.scala:517:{68,95}, :523:27, :524:111, :525:55, :526:55, :606:{82,88}, :607:{14,16}]
wire [12:0] stage2_bypass = 13'h1FFF; // @[TLB.scala:517:{68,95}, :523:27, :524:111, :525:55, :526:55, :606:{82,88}, :607:{14,16}]
wire [12:0] _hr_array_T_4 = 13'h1FFF; // @[TLB.scala:517:{68,95}, :523:27, :524:111, :525:55, :526:55, :606:{82,88}, :607:{14,16}]
wire [12:0] _hw_array_T_1 = 13'h1FFF; // @[TLB.scala:517:{68,95}, :523:27, :524:111, :525:55, :526:55, :606:{82,88}, :607:{14,16}]
wire [12:0] _hx_array_T_1 = 13'h1FFF; // @[TLB.scala:517:{68,95}, :523:27, :524:111, :525:55, :526:55, :606:{82,88}, :607:{14,16}]
wire [12:0] _gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:517:{68,95}, :523:27, :524:111, :525:55, :526:55, :606:{82,88}, :607:{14,16}]
wire [12:0] gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:517:{68,95}, :523:27, :524:111, :525:55, :526:55, :606:{82,88}, :607:{14,16}]
wire [12:0] _gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:517:{68,95}, :523:27, :524:111, :525:55, :526:55, :606:{82,88}, :607:{14,16}]
wire [12:0] gpa_hits = 13'h1FFF; // @[TLB.scala:517:{68,95}, :523:27, :524:111, :525:55, :526:55, :606:{82,88}, :607:{14,16}]
wire [6:0] real_hits_hi = 7'h0; // @[package.scala:45:27]
wire [6:0] _state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25]
wire [6:0] _multipleHits_T_21 = 7'h0; // @[Misc.scala:182:39]
wire [13:0] lrscAllowed = 14'h0; // @[TLB.scala:580:24]
wire [13:0] _gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46]
wire [13:0] gf_ld_array = 14'h0; // @[TLB.scala:600:24]
wire [13:0] _gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53]
wire [13:0] gf_st_array = 14'h0; // @[TLB.scala:601:24]
wire [13:0] _gf_inst_array_T = 14'h0; // @[TLB.scala:602:36]
wire [13:0] gf_inst_array = 14'h0; // @[TLB.scala:602:26]
wire [13:0] gpa_hits_need_gpa_mask = 14'h0; // @[TLB.scala:605:73]
wire [13:0] _io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58]
wire [13:0] _io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65]
wire [13:0] _io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[TLB.scala:318:7]
wire [12:0] real_hits = 13'h0; // @[package.scala:45:27]
wire [12:0] _stage1_bypass_T = 13'h0; // @[TLB.scala:517:27]
wire [12:0] stage1_bypass = 13'h0; // @[TLB.scala:517:61]
wire [12:0] _r_array_T_2 = 13'h0; // @[TLB.scala:520:74]
wire [12:0] _hr_array_T_2 = 13'h0; // @[TLB.scala:524:60]
wire [12:0] _gpa_hits_T = 13'h0; // @[TLB.scala:607:30]
wire [12:0] _tlb_hit_T = 13'h0; // @[TLB.scala:611:28]
wire [2:0] real_hits_lo_lo = 3'h0; // @[package.scala:45:27]
wire [2:0] real_hits_lo_hi = 3'h0; // @[package.scala:45:27]
wire [2:0] real_hits_hi_lo = 3'h0; // @[package.scala:45:27]
wire [2:0] waddr_1 = 3'h0; // @[TLB.scala:485:22]
wire [2:0] state_vec_0_left_subtree_state = 3'h0; // @[package.scala:163:13]
wire [2:0] state_vec_0_right_subtree_state = 3'h0; // @[Replacement.scala:198:38]
wire [2:0] _multipleHits_T_1 = 3'h0; // @[Misc.scala:181:37]
wire [2:0] _multipleHits_T_10 = 3'h0; // @[Misc.scala:182:39]
wire [2:0] _multipleHits_T_22 = 3'h0; // @[Misc.scala:181:37]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7, :320:14]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7]
wire [5:0] real_hits_lo = 6'h0; // @[package.scala:45:27]
wire [5:0] _multipleHits_T = 6'h0; // @[Misc.scala:181:37]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7, :320:14]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7, :320:14]
wire [1:0] io_ptw_status_sxl = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_uxl = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_xs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] real_hits_lo_lo_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] real_hits_lo_hi_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] real_hits_hi_lo_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] real_hits_hi_hi_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] real_hits_hi_hi_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] special_entry_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] waddr = 2'h0; // @[TLB.scala:477:22]
wire [1:0] superpage_entries_0_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] idx = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_0_0_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] idx_1 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_0_1_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] idx_2 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_0_2_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] idx_3 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_0_3_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] idx_4 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_0_4_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] idx_5 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_0_5_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] idx_6 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_0_6_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] idx_7 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_0_7_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] _c_array_T = 2'h0; // @[TLB.scala:537:25]
wire [1:0] _prefetchable_array_T_1 = 2'h0; // @[TLB.scala:547:59]
wire [1:0] _multipleHits_T_3 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] _multipleHits_T_12 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] _multipleHits_T_24 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] _multipleHits_T_32 = 2'h0; // @[Misc.scala:181:37]
wire [1:0] _multipleHits_T_37 = 2'h0; // @[Misc.scala:182:39]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[TLB.scala:318:7, :320:14]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[TLB.scala:318:7, :320:14]
wire [1:0] io_ptw_status_dprv = 2'h3; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_prv = 2'h3; // @[TLB.scala:318:7]
wire [43:0] io_ptw_ptbr_ppn = 44'h0; // @[TLB.scala:318:7, :320:14, :373:17]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14, :373:17]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14, :373:17]
wire [43:0] satp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14, :373:17]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17]
wire [15:0] satp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17]
wire [3:0] io_ptw_ptbr_mode = 4'h0; // @[TLB.scala:318:7]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7]
wire [3:0] satp_mode = 4'h0; // @[TLB.scala:373:17]
wire [3:0] real_hits_hi_hi = 4'h0; // @[package.scala:45:27]
wire [3:0] _multipleHits_T_31 = 4'h0; // @[Misc.scala:182:39]
wire io_resp_miss = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7]
wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_valid = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_need_gpa_0 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_vstage1_0 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_stage2_0 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_mbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_sbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_tsr = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_tw = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_tvm = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_mxr = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_sum = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_mprv = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_spp = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_ube = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_spie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_upie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_hie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_sie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_uie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_spvp = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_spv = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_gva = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[TLB.scala:318:7]
wire io_kill = 1'h0; // @[TLB.scala:318:7]
wire priv_v = 1'h0; // @[TLB.scala:369:34]
wire _stage1_en_T = 1'h0; // @[TLB.scala:374:41]
wire stage1_en = 1'h0; // @[TLB.scala:374:29]
wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38]
wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68]
wire vstage1_en = 1'h0; // @[TLB.scala:376:48]
wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38]
wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68]
wire stage2_en = 1'h0; // @[TLB.scala:378:48]
wire _vm_enabled_T = 1'h0; // @[TLB.scala:399:31]
wire _vm_enabled_T_1 = 1'h0; // @[TLB.scala:399:45]
wire vm_enabled = 1'h0; // @[TLB.scala:399:61]
wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52]
wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37]
wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78]
wire do_refill = 1'h0; // @[TLB.scala:408:29]
wire _invalidate_refill_T = 1'h0; // @[package.scala:16:47]
wire _invalidate_refill_T_1 = 1'h0; // @[package.scala:16:47]
wire _invalidate_refill_T_2 = 1'h0; // @[package.scala:81:59]
wire _mpu_ppn_T = 1'h0; // @[TLB.scala:413:32]
wire _mpu_priv_T_1 = 1'h0; // @[TLB.scala:415:38]
wire cacheable = 1'h0; // @[TLB.scala:425:41]
wire _sector_hits_T = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_8 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_16 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_24 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_32 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_40 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_48 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_56 = 1'h0; // @[package.scala:81:59]
wire superpage_hits_0 = 1'h0; // @[TLB.scala:188:18]
wire superpage_hits_1 = 1'h0; // @[TLB.scala:188:18]
wire superpage_hits_2 = 1'h0; // @[TLB.scala:188:18]
wire superpage_hits_3 = 1'h0; // @[TLB.scala:188:18]
wire _hitsVec_T_5 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_0 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_11 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_1 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_17 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_2 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_23 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_3 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_29 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_4 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_35 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_5 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_41 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_6 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_47 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_7 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_53 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_8 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_59 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_9 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_65 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_10 = 1'h0; // @[TLB.scala:440:44]
wire _hitsVec_T_71 = 1'h0; // @[TLB.scala:188:18]
wire hitsVec_11 = 1'h0; // @[TLB.scala:440:44]
wire hitsVec_12 = 1'h0; // @[TLB.scala:440:44]
wire refill_v = 1'h0; // @[TLB.scala:448:33]
wire newEntry_c = 1'h0; // @[TLB.scala:449:24]
wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24]
wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84]
wire _waddr_T = 1'h0; // @[TLB.scala:477:45]
wire sum = 1'h0; // @[TLB.scala:510:16]
wire _mxr_T = 1'h0; // @[TLB.scala:518:36]
wire mxr = 1'h0; // @[TLB.scala:518:31]
wire _prefetchable_array_T = 1'h0; // @[TLB.scala:547:43]
wire cmd_readx = 1'h0; // @[TLB.scala:575:37]
wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32]
wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32]
wire _gpa_hits_hit_mask_T_1 = 1'h0; // @[TLB.scala:606:60]
wire tlb_hit_if_not_gpa_miss = 1'h0; // @[TLB.scala:610:43]
wire tlb_hit = 1'h0; // @[TLB.scala:611:40]
wire _tlb_miss_T_1 = 1'h0; // @[TLB.scala:613:29]
wire _tlb_miss_T_3 = 1'h0; // @[TLB.scala:613:53]
wire tlb_miss = 1'h0; // @[TLB.scala:613:64]
wire state_vec_0_left_subtree_state_1 = 1'h0; // @[package.scala:163:13]
wire state_vec_0_right_subtree_state_1 = 1'h0; // @[Replacement.scala:198:38]
wire state_vec_0_left_subtree_state_2 = 1'h0; // @[package.scala:163:13]
wire state_vec_0_right_subtree_state_2 = 1'h0; // @[Replacement.scala:198:38]
wire state_reg_left_subtree_state = 1'h0; // @[package.scala:163:13]
wire state_reg_right_subtree_state = 1'h0; // @[Replacement.scala:198:38]
wire _multipleHits_T_2 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_4 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_1 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_5 = 1'h0; // @[Misc.scala:182:39]
wire multipleHits_rightOne = 1'h0; // @[Misc.scala:178:18]
wire multipleHits_rightOne_1 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_7 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_leftOne_2 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_8 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_9 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_leftTwo = 1'h0; // @[Misc.scala:183:49]
wire _multipleHits_T_11 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_3 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_13 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_4 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_14 = 1'h0; // @[Misc.scala:182:39]
wire multipleHits_rightOne_2 = 1'h0; // @[Misc.scala:178:18]
wire multipleHits_rightOne_3 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_16 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_1 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_rightOne_4 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_17 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_18 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_2 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_leftOne_5 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_19 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_20 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_leftTwo_1 = 1'h0; // @[Misc.scala:183:49]
wire _multipleHits_T_23 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_6 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_25 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_7 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_26 = 1'h0; // @[Misc.scala:182:39]
wire multipleHits_rightOne_5 = 1'h0; // @[Misc.scala:178:18]
wire multipleHits_rightOne_6 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_28 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_3 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_leftOne_8 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_29 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_30 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_leftTwo_2 = 1'h0; // @[Misc.scala:183:49]
wire _multipleHits_T_33 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_9 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_34 = 1'h0; // @[Misc.scala:182:39]
wire multipleHits_rightOne_7 = 1'h0; // @[Misc.scala:178:18]
wire multipleHits_leftOne_10 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_36 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_leftTwo_3 = 1'h0; // @[Misc.scala:183:49]
wire _multipleHits_T_38 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_11 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_39 = 1'h0; // @[Misc.scala:182:39]
wire multipleHits_rightOne_8 = 1'h0; // @[Misc.scala:178:18]
wire multipleHits_rightOne_9 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_41 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_4 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_rightOne_10 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_42 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_43 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_5 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_rightOne_11 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_44 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_45 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_6 = 1'h0; // @[Misc.scala:183:49]
wire _multipleHits_T_46 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_47 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_48 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits = 1'h0; // @[Misc.scala:183:49]
wire _io_resp_pf_ld_T = 1'h0; // @[TLB.scala:633:28]
wire _io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28]
wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29]
wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66]
wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42]
wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29]
wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73]
wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49]
wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56]
wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30]
wire _io_resp_miss_T = 1'h0; // @[TLB.scala:651:29]
wire _io_resp_miss_T_1 = 1'h0; // @[TLB.scala:651:52]
wire _io_resp_miss_T_2 = 1'h0; // @[TLB.scala:651:64]
wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36]
wire _io_ptw_req_valid_T = 1'h0; // @[TLB.scala:662:29]
wire io_req_ready = 1'h1; // @[TLB.scala:318:7]
wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7]
wire _homogeneous_T_53 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _sector_hits_T_6 = 1'h1; // @[TLB.scala:174:105]
wire _sector_hits_T_14 = 1'h1; // @[TLB.scala:174:105]
wire _sector_hits_T_22 = 1'h1; // @[TLB.scala:174:105]
wire _sector_hits_T_30 = 1'h1; // @[TLB.scala:174:105]
wire _sector_hits_T_38 = 1'h1; // @[TLB.scala:174:105]
wire _sector_hits_T_46 = 1'h1; // @[TLB.scala:174:105]
wire _sector_hits_T_54 = 1'h1; // @[TLB.scala:174:105]
wire _sector_hits_T_62 = 1'h1; // @[TLB.scala:174:105]
wire _superpage_hits_T_3 = 1'h1; // @[TLB.scala:174:105]
wire _superpage_hits_T_8 = 1'h1; // @[TLB.scala:174:105]
wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:174:105]
wire _superpage_hits_T_18 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_3 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_9 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_15 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_21 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_27 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_33 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_39 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_45 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_51 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_57 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_63 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_69 = 1'h1; // @[TLB.scala:174:105]
wire _hitsVec_T_75 = 1'h1; // @[TLB.scala:174:105]
wire _hits_T = 1'h1; // @[TLB.scala:442:18]
wire _ppn_T = 1'h1; // @[TLB.scala:502:30]
wire _stage1_bypass_T_1 = 1'h1; // @[TLB.scala:517:83]
wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42]
wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107]
wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32]
wire _tlb_miss_T_2 = 1'h1; // @[TLB.scala:613:56]
wire _tlb_miss_T_4 = 1'h1; // @[TLB.scala:613:67]
wire _io_req_ready_T = 1'h1; // @[TLB.scala:631:25]
wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20]
wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28]
wire _mpu_priv_T = io_req_bits_passthrough_0; // @[TLB.scala:318:7, :415:52]
wire [1:0] io_resp_size_0 = io_req_bits_size_0; // @[TLB.scala:318:7]
wire [4:0] io_resp_cmd_0 = io_req_bits_cmd_0; // @[TLB.scala:318:7]
wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23]
wire [33:0] _io_resp_gpa_T; // @[TLB.scala:659:8]
wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41]
wire _io_resp_pf_st_T_3; // @[TLB.scala:634:48]
wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29]
wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41]
wire _io_resp_ae_st_T_1; // @[TLB.scala:642:41]
wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41]
wire _io_resp_ma_ld_T; // @[TLB.scala:645:31]
wire _io_resp_ma_st_T; // @[TLB.scala:646:31]
wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41]
wire _io_resp_must_alloc_T_1; // @[TLB.scala:649:51]
wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59]
wire invalidate_refill = io_sfence_valid_0; // @[TLB.scala:318:7, :410:88]
wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24]
wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13]
wire io_resp_pf_ld_0; // @[TLB.scala:318:7]
wire io_resp_pf_st_0; // @[TLB.scala:318:7]
wire io_resp_pf_inst_0; // @[TLB.scala:318:7]
wire io_resp_ae_ld_0; // @[TLB.scala:318:7]
wire io_resp_ae_st_0; // @[TLB.scala:318:7]
wire io_resp_ae_inst_0; // @[TLB.scala:318:7]
wire io_resp_ma_ld_0; // @[TLB.scala:318:7]
wire io_resp_ma_st_0; // @[TLB.scala:318:7]
wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7]
wire [33:0] io_resp_gpa_0; // @[TLB.scala:318:7]
wire io_resp_cacheable_0; // @[TLB.scala:318:7]
wire io_resp_must_alloc_0; // @[TLB.scala:318:7]
wire io_resp_prefetchable_0; // @[TLB.scala:318:7]
wire [20:0] vpn = io_req_bits_vaddr_0[32:12]; // @[TLB.scala:318:7, :335:30]
wire [20:0] _sector_hits_T_3 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _sector_hits_T_11 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _sector_hits_T_19 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _sector_hits_T_27 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _sector_hits_T_35 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _sector_hits_T_43 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _sector_hits_T_51 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _sector_hits_T_59 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _superpage_hits_T = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _superpage_hits_T_5 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _superpage_hits_T_10 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _superpage_hits_T_15 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_6 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_12 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_18 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_24 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_30 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_36 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_42 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_48 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_54 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_60 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_66 = vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] _hitsVec_T_72 = vpn; // @[TLB.scala:174:61, :335:30]
wire priv_s = io_req_bits_prv_0[0]; // @[TLB.scala:318:7, :370:20]
wire priv_uses_vm = ~(io_req_bits_prv_0[1]); // @[TLB.scala:318:7, :372:27]
wire _vm_enabled_T_2 = ~io_req_bits_passthrough_0; // @[TLB.scala:318:7, :399:64]
wire _vsatp_mode_mismatch_T_2 = ~io_req_bits_passthrough_0; // @[TLB.scala:318:7, :399:64, :403:81]
wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44]
wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24]
wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77]
wire _mpu_ppn_T_22; // @[TLB.scala:170:77]
wire _mpu_ppn_T_21; // @[TLB.scala:170:77]
wire _mpu_ppn_T_20; // @[TLB.scala:170:77]
wire _mpu_ppn_T_19; // @[TLB.scala:170:77]
wire _mpu_ppn_T_18; // @[TLB.scala:170:77]
wire _mpu_ppn_T_17; // @[TLB.scala:170:77]
wire _mpu_ppn_T_16; // @[TLB.scala:170:77]
wire _mpu_ppn_T_15; // @[TLB.scala:170:77]
wire _mpu_ppn_T_14; // @[TLB.scala:170:77]
wire _mpu_ppn_T_13; // @[TLB.scala:170:77]
wire _mpu_ppn_T_12; // @[TLB.scala:170:77]
wire _mpu_ppn_T_11; // @[TLB.scala:170:77]
wire _mpu_ppn_T_10; // @[TLB.scala:170:77]
wire _mpu_ppn_T_9; // @[TLB.scala:170:77]
wire _mpu_ppn_T_8; // @[TLB.scala:170:77]
wire _mpu_ppn_T_7; // @[TLB.scala:170:77]
wire _mpu_ppn_T_6; // @[TLB.scala:170:77]
wire _mpu_ppn_T_5; // @[TLB.scala:170:77]
wire _mpu_ppn_T_4; // @[TLB.scala:170:77]
wire _mpu_ppn_T_3; // @[TLB.scala:170:77]
wire _mpu_ppn_T_2; // @[TLB.scala:170:77]
wire _mpu_ppn_T_1; // @[TLB.scala:170:77]
assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77]
assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77]
assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77]
assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77]
assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77]
assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77]
assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77]
assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77]
assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77]
assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77]
assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77]
assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77]
assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77]
assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77]
assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77]
assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77]
assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77]
assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77]
assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77]
assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77]
assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77]
assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77]
assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77]
wire [21:0] _mpu_ppn_T_24 = io_req_bits_vaddr_0[33:12]; // @[TLB.scala:318:7, :413:146]
wire [21:0] _mpu_ppn_T_25 = _mpu_ppn_T_24; // @[TLB.scala:413:{20,146}]
wire [21:0] mpu_ppn = _mpu_ppn_T_25; // @[TLB.scala:412:20, :413:20]
wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52]
wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46]
wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82]
wire [33:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}]
wire [33:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25]
wire [33:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25]
wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, io_req_bits_prv_0}; // @[TLB.scala:318:7, :415:103]
wire [2:0] mpu_priv = _mpu_priv_T_2; // @[TLB.scala:415:{27,103}]
wire [34:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_2 = _homogeneous_T_1 & 35'h7FFFFE000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46]
wire _homogeneous_T_4 = _homogeneous_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_45 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65]
wire [33:0] _homogeneous_T_5 = {mpu_physaddr[33:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25]
wire [34:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_7 = _homogeneous_T_6 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46]
wire _homogeneous_T_9 = _homogeneous_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _GEN = {mpu_physaddr[33:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25]
wire [33:0] _homogeneous_T_10; // @[Parameters.scala:137:31]
assign _homogeneous_T_10 = _GEN; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_54; // @[Parameters.scala:137:31]
assign _homogeneous_T_54 = _GEN; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_92; // @[Parameters.scala:137:31]
assign _homogeneous_T_92 = _GEN; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_105; // @[Parameters.scala:137:31]
assign _homogeneous_T_105 = _GEN; // @[Parameters.scala:137:31]
wire [34:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_12 = _homogeneous_T_11 & 35'h7FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46]
wire _homogeneous_T_14 = _homogeneous_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _GEN_0 = {mpu_physaddr[33:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25]
wire [33:0] _homogeneous_T_15; // @[Parameters.scala:137:31]
assign _homogeneous_T_15 = _GEN_0; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_66; // @[Parameters.scala:137:31]
assign _homogeneous_T_66 = _GEN_0; // @[Parameters.scala:137:31]
wire [34:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_17 = _homogeneous_T_16 & 35'h7FFFEF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46]
wire _homogeneous_T_19 = _homogeneous_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _GEN_1 = {mpu_physaddr[33:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25]
wire [33:0] _homogeneous_T_20; // @[Parameters.scala:137:31]
assign _homogeneous_T_20 = _GEN_1; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_71; // @[Parameters.scala:137:31]
assign _homogeneous_T_71 = _GEN_1; // @[Parameters.scala:137:31]
wire [34:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_22 = _homogeneous_T_21 & 35'h7FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46]
wire _homogeneous_T_24 = _homogeneous_T_23 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _homogeneous_T_25 = {mpu_physaddr[33:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25]
wire [34:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_27 = _homogeneous_T_26 & 35'h7FC000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46]
wire _homogeneous_T_29 = _homogeneous_T_28 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _homogeneous_T_30 = {mpu_physaddr[33:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25]
wire [34:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_32 = _homogeneous_T_31 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46]
wire _homogeneous_T_34 = _homogeneous_T_33 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _homogeneous_T_35 = {mpu_physaddr[33:31], mpu_physaddr[30:0] ^ 31'h60000000}; // @[TLB.scala:414:25]
wire [34:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_37 = _homogeneous_T_36 & 35'h7E0000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46]
wire _homogeneous_T_39 = _homogeneous_T_38 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _homogeneous_T_40 = {mpu_physaddr[33:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15]
wire [34:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_42 = _homogeneous_T_41 & 35'h7FFFFC000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46]
wire _homogeneous_T_44 = _homogeneous_T_43 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_46 = _homogeneous_T_45 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_47 = _homogeneous_T_46 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_48 = _homogeneous_T_47 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_49 = _homogeneous_T_48 | _homogeneous_T_24; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_50 = _homogeneous_T_49 | _homogeneous_T_29; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_51 = _homogeneous_T_50 | _homogeneous_T_34; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_52 = _homogeneous_T_51 | _homogeneous_T_39; // @[TLBPermissions.scala:101:65]
wire homogeneous = _homogeneous_T_52 | _homogeneous_T_44; // @[TLBPermissions.scala:101:65]
wire [34:0] _homogeneous_T_55 = {1'h0, _homogeneous_T_54}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_56 = _homogeneous_T_55 & 35'hD8110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_57 = _homogeneous_T_56; // @[Parameters.scala:137:46]
wire _homogeneous_T_58 = _homogeneous_T_57 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_59 = _homogeneous_T_58; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_60 = ~_homogeneous_T_59; // @[TLBPermissions.scala:87:{22,66}]
wire [33:0] _homogeneous_T_61 = {mpu_physaddr[33:13], mpu_physaddr[12:0] ^ 13'h1000}; // @[TLB.scala:414:25]
wire [34:0] _homogeneous_T_62 = {1'h0, _homogeneous_T_61}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_63 = _homogeneous_T_62 & 35'hDA113000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_64 = _homogeneous_T_63; // @[Parameters.scala:137:46]
wire _homogeneous_T_65 = _homogeneous_T_64 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_86 = _homogeneous_T_65; // @[TLBPermissions.scala:87:66]
wire [34:0] _homogeneous_T_67 = {1'h0, _homogeneous_T_66}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_68 = _homogeneous_T_67 & 35'hDA103000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_69 = _homogeneous_T_68; // @[Parameters.scala:137:46]
wire _homogeneous_T_70 = _homogeneous_T_69 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _homogeneous_T_72 = {1'h0, _homogeneous_T_71}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_73 = _homogeneous_T_72 & 35'hDA110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_74 = _homogeneous_T_73; // @[Parameters.scala:137:46]
wire _homogeneous_T_75 = _homogeneous_T_74 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _homogeneous_T_76 = {mpu_physaddr[33:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25]
wire [34:0] _homogeneous_T_77 = {1'h0, _homogeneous_T_76}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_78 = _homogeneous_T_77 & 35'hD8000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_79 = _homogeneous_T_78; // @[Parameters.scala:137:46]
wire _homogeneous_T_80 = _homogeneous_T_79 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _homogeneous_T_81 = {mpu_physaddr[33:29], mpu_physaddr[28:0] ^ 29'h10000000}; // @[TLB.scala:414:25]
wire [34:0] _homogeneous_T_82 = {1'h0, _homogeneous_T_81}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_83 = _homogeneous_T_82 & 35'hDA113000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_84 = _homogeneous_T_83; // @[Parameters.scala:137:46]
wire _homogeneous_T_85 = _homogeneous_T_84 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_87 = _homogeneous_T_86 | _homogeneous_T_70; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_88 = _homogeneous_T_87 | _homogeneous_T_75; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_89 = _homogeneous_T_88 | _homogeneous_T_80; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_90 = _homogeneous_T_89 | _homogeneous_T_85; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_91 = ~_homogeneous_T_90; // @[TLBPermissions.scala:87:{22,66}]
wire [34:0] _homogeneous_T_93 = {1'h0, _homogeneous_T_92}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_94 = _homogeneous_T_93 & 35'hD8110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_95 = _homogeneous_T_94; // @[Parameters.scala:137:46]
wire _homogeneous_T_96 = _homogeneous_T_95 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_102 = _homogeneous_T_96; // @[TLBPermissions.scala:87:66]
wire [33:0] _GEN_2 = {mpu_physaddr[33:31], mpu_physaddr[30:0] ^ 31'h40000000}; // @[TLB.scala:414:25]
wire [33:0] _homogeneous_T_97; // @[Parameters.scala:137:31]
assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_110; // @[Parameters.scala:137:31]
assign _homogeneous_T_110 = _GEN_2; // @[Parameters.scala:137:31]
wire [34:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_99 = _homogeneous_T_98 & 35'hC0000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46]
wire _homogeneous_T_101 = _homogeneous_T_100 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_103 = _homogeneous_T_102 | _homogeneous_T_101; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_104 = ~_homogeneous_T_103; // @[TLBPermissions.scala:87:{22,66}]
wire [34:0] _homogeneous_T_106 = {1'h0, _homogeneous_T_105}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_107 = _homogeneous_T_106 & 35'hD8110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_108 = _homogeneous_T_107; // @[Parameters.scala:137:46]
wire _homogeneous_T_109 = _homogeneous_T_108 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_115 = _homogeneous_T_109; // @[TLBPermissions.scala:87:66]
wire [34:0] _homogeneous_T_111 = {1'h0, _homogeneous_T_110}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_112 = _homogeneous_T_111 & 35'hC0000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_113 = _homogeneous_T_112; // @[Parameters.scala:137:46]
wire _homogeneous_T_114 = _homogeneous_T_113 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_116 = _homogeneous_T_115 | _homogeneous_T_114; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_117 = ~_homogeneous_T_116; // @[TLBPermissions.scala:87:{22,66}]
wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39]
wire [34:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46]
wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}]
wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33]
wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}]
wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}]
wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24]
wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33]
wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}]
wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}]
wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24]
wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33]
wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}]
wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}]
wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24]
wire _sector_hits_T_1 = _sector_hits_T; // @[package.scala:81:59]
wire _sector_hits_T_2 = _sector_hits_T_1; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_4 = _sector_hits_T_3[20:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_5 = _sector_hits_T_4 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_7 = _sector_hits_T_5 & _sector_hits_T_6; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_0 = _sector_hits_T_2 & _sector_hits_T_7; // @[package.scala:81:59]
wire _sector_hits_T_9 = _sector_hits_T_8; // @[package.scala:81:59]
wire _sector_hits_T_10 = _sector_hits_T_9; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_12 = _sector_hits_T_11[20:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_13 = _sector_hits_T_12 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_15 = _sector_hits_T_13 & _sector_hits_T_14; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_1 = _sector_hits_T_10 & _sector_hits_T_15; // @[package.scala:81:59]
wire _sector_hits_T_17 = _sector_hits_T_16; // @[package.scala:81:59]
wire _sector_hits_T_18 = _sector_hits_T_17; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_20 = _sector_hits_T_19[20:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_21 = _sector_hits_T_20 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_23 = _sector_hits_T_21 & _sector_hits_T_22; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_2 = _sector_hits_T_18 & _sector_hits_T_23; // @[package.scala:81:59]
wire _sector_hits_T_25 = _sector_hits_T_24; // @[package.scala:81:59]
wire _sector_hits_T_26 = _sector_hits_T_25; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_28 = _sector_hits_T_27[20:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_29 = _sector_hits_T_28 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_31 = _sector_hits_T_29 & _sector_hits_T_30; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_3 = _sector_hits_T_26 & _sector_hits_T_31; // @[package.scala:81:59]
wire _sector_hits_T_33 = _sector_hits_T_32; // @[package.scala:81:59]
wire _sector_hits_T_34 = _sector_hits_T_33; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_36 = _sector_hits_T_35[20:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_37 = _sector_hits_T_36 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_39 = _sector_hits_T_37 & _sector_hits_T_38; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_4 = _sector_hits_T_34 & _sector_hits_T_39; // @[package.scala:81:59]
wire _sector_hits_T_41 = _sector_hits_T_40; // @[package.scala:81:59]
wire _sector_hits_T_42 = _sector_hits_T_41; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_44 = _sector_hits_T_43[20:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_45 = _sector_hits_T_44 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_47 = _sector_hits_T_45 & _sector_hits_T_46; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_5 = _sector_hits_T_42 & _sector_hits_T_47; // @[package.scala:81:59]
wire _sector_hits_T_49 = _sector_hits_T_48; // @[package.scala:81:59]
wire _sector_hits_T_50 = _sector_hits_T_49; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_52 = _sector_hits_T_51[20:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_53 = _sector_hits_T_52 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_55 = _sector_hits_T_53 & _sector_hits_T_54; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_6 = _sector_hits_T_50 & _sector_hits_T_55; // @[package.scala:81:59]
wire _sector_hits_T_57 = _sector_hits_T_56; // @[package.scala:81:59]
wire _sector_hits_T_58 = _sector_hits_T_57; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_60 = _sector_hits_T_59[20:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_61 = _sector_hits_T_60 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_63 = _sector_hits_T_61 & _sector_hits_T_62; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_7 = _sector_hits_T_58 & _sector_hits_T_63; // @[package.scala:81:59]
wire [20:0] _superpage_hits_T_1 = _superpage_hits_T; // @[TLB.scala:174:{61,68}]
wire _superpage_hits_T_2 = _superpage_hits_T_1 == 21'h0; // @[TLB.scala:174:{68,86}, :339:29]
wire _superpage_hits_T_4 = _superpage_hits_T_2 & _superpage_hits_T_3; // @[TLB.scala:174:{86,95,105}]
wire [20:0] _superpage_hits_T_6 = _superpage_hits_T_5; // @[TLB.scala:174:{61,68}]
wire _superpage_hits_T_7 = _superpage_hits_T_6 == 21'h0; // @[TLB.scala:174:{68,86}, :339:29]
wire _superpage_hits_T_9 = _superpage_hits_T_7 & _superpage_hits_T_8; // @[TLB.scala:174:{86,95,105}]
wire [20:0] _superpage_hits_T_11 = _superpage_hits_T_10; // @[TLB.scala:174:{61,68}]
wire _superpage_hits_T_12 = _superpage_hits_T_11 == 21'h0; // @[TLB.scala:174:{68,86}, :339:29]
wire _superpage_hits_T_14 = _superpage_hits_T_12 & _superpage_hits_T_13; // @[TLB.scala:174:{86,95,105}]
wire [20:0] _superpage_hits_T_16 = _superpage_hits_T_15; // @[TLB.scala:174:{61,68}]
wire _superpage_hits_T_17 = _superpage_hits_T_16 == 21'h0; // @[TLB.scala:174:{68,86}, :339:29]
wire _superpage_hits_T_19 = _superpage_hits_T_17 & _superpage_hits_T_18; // @[TLB.scala:174:{86,95,105}]
wire [1:0] hitsVec_idx = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_1 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_2 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_3 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_4 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_5 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_6 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_7 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_24 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_48 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_72 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_96 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_120 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_144 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_168 = vpn[1:0]; // @[package.scala:163:13]
wire [18:0] _hitsVec_T_1 = _hitsVec_T[20:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_2 = _hitsVec_T_1 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}]
wire [18:0] _hitsVec_T_7 = _hitsVec_T_6[20:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_8 = _hitsVec_T_7 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}]
wire [18:0] _hitsVec_T_13 = _hitsVec_T_12[20:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_14 = _hitsVec_T_13 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}]
wire [18:0] _hitsVec_T_19 = _hitsVec_T_18[20:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_20 = _hitsVec_T_19 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}]
wire [18:0] _hitsVec_T_25 = _hitsVec_T_24[20:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_26 = _hitsVec_T_25 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_28 = _hitsVec_T_26 & _hitsVec_T_27; // @[TLB.scala:174:{86,95,105}]
wire [18:0] _hitsVec_T_31 = _hitsVec_T_30[20:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_32 = _hitsVec_T_31 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_34 = _hitsVec_T_32 & _hitsVec_T_33; // @[TLB.scala:174:{86,95,105}]
wire [18:0] _hitsVec_T_37 = _hitsVec_T_36[20:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_38 = _hitsVec_T_37 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_40 = _hitsVec_T_38 & _hitsVec_T_39; // @[TLB.scala:174:{86,95,105}]
wire [18:0] _hitsVec_T_43 = _hitsVec_T_42[20:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_44 = _hitsVec_T_43 == 19'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_46 = _hitsVec_T_44 & _hitsVec_T_45; // @[TLB.scala:174:{86,95,105}]
wire [20:0] _hitsVec_T_49 = _hitsVec_T_48; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_50 = _hitsVec_T_49 == 21'h0; // @[TLB.scala:174:{68,86}, :339:29]
wire _hitsVec_T_52 = _hitsVec_T_50 & _hitsVec_T_51; // @[TLB.scala:174:{86,95,105}]
wire [20:0] _hitsVec_T_55 = _hitsVec_T_54; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_56 = _hitsVec_T_55 == 21'h0; // @[TLB.scala:174:{68,86}, :339:29]
wire _hitsVec_T_58 = _hitsVec_T_56 & _hitsVec_T_57; // @[TLB.scala:174:{86,95,105}]
wire [20:0] _hitsVec_T_61 = _hitsVec_T_60; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_62 = _hitsVec_T_61 == 21'h0; // @[TLB.scala:174:{68,86}, :339:29]
wire _hitsVec_T_64 = _hitsVec_T_62 & _hitsVec_T_63; // @[TLB.scala:174:{86,95,105}]
wire [20:0] _hitsVec_T_67 = _hitsVec_T_66; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_68 = _hitsVec_T_67 == 21'h0; // @[TLB.scala:174:{68,86}, :339:29]
wire _hitsVec_T_70 = _hitsVec_T_68 & _hitsVec_T_69; // @[TLB.scala:174:{86,95,105}]
wire [20:0] _hitsVec_T_73 = _hitsVec_T_72; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_74 = _hitsVec_T_73 == 21'h0; // @[TLB.scala:174:{68,86}, :339:29]
wire _hitsVec_T_76 = _hitsVec_T_74 & _hitsVec_T_75; // @[TLB.scala:174:{86,95,105}]
wire _hitsVec_T_77 = _hitsVec_T_76; // @[TLB.scala:174:95, :188:18]
wire _newEntry_g_T; // @[TLB.scala:453:25]
wire _newEntry_sw_T_6; // @[PTW.scala:151:40]
wire _newEntry_sx_T_5; // @[PTW.scala:153:35]
wire _newEntry_sr_T_5; // @[PTW.scala:149:35]
wire newEntry_g; // @[TLB.scala:449:24]
wire newEntry_ae_stage2; // @[TLB.scala:449:24]
wire newEntry_sw; // @[TLB.scala:449:24]
wire newEntry_sx; // @[TLB.scala:449:24]
wire newEntry_sr; // @[TLB.scala:449:24]
wire newEntry_ppp; // @[TLB.scala:449:24]
wire newEntry_pal; // @[TLB.scala:449:24]
wire newEntry_paa; // @[TLB.scala:449:24]
wire newEntry_eff; // @[TLB.scala:449:24]
assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25]
assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25]
wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53]
assign newEntry_ae_stage2 = _newEntry_ae_stage2_T_1; // @[TLB.scala:449:24, :456:84]
wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7]
wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sr_T_1; // @[TLB.scala:318:7]
wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7]
wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7]
assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24]
wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7]
wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sw_T_1; // @[TLB.scala:318:7]
wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7]
wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7]
assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24]
wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7]
wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sx_T_1; // @[TLB.scala:318:7]
wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7]
wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7]
assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24]
wire [1:0] _GEN_3 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [1:0] _GEN_4 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [1:0] _GEN_5 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_hi_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_6 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_lo_lo_hi = _GEN_6; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [1:0] _GEN_7 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_lo_hi_hi = _GEN_7; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_8 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_hi_lo_hi = _GEN_8; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [20:0] _GEN_9 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24]
wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_0_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_1_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_2_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_3_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_4_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_5_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_6_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_7_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_hi_hi_hi = _GEN_9; // @[TLB.scala:217:24]
wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24]
wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_lo_lo_hi = {superpage_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_lo_hi_lo = {superpage_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_1_data_0_lo_hi_hi = {superpage_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_hi_lo_lo = {superpage_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_1_data_0_hi_lo_hi = {superpage_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_hi_hi_lo = {superpage_entries_1_data_0_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] superpage_entries_1_data_0_hi_hi_hi = {superpage_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_lo_lo_hi = {superpage_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_lo_hi_lo = {superpage_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_2_data_0_lo_hi_hi = {superpage_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_hi_lo_lo = {superpage_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_2_data_0_hi_lo_hi = {superpage_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_hi_hi_lo = {superpage_entries_2_data_0_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] superpage_entries_2_data_0_hi_hi_hi = {superpage_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_lo_lo_hi = {superpage_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_lo_hi_lo = {superpage_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_3_data_0_lo_hi_hi = {superpage_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_hi_lo_lo = {superpage_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_3_data_0_hi_lo_hi = {superpage_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_hi_hi_lo = {superpage_entries_3_data_0_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] superpage_entries_3_data_0_hi_hi_hi = {superpage_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_lo_lo_hi = {sectored_entries_0_0_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_0_data_lo_lo = {sectored_entries_0_0_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_lo_hi_lo = {sectored_entries_0_0_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_0_data_lo_hi_hi = {sectored_entries_0_0_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_0_data_lo_hi = {sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_0_data_lo = {sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_hi_lo_lo = {sectored_entries_0_0_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_0_data_hi_lo_hi = {sectored_entries_0_0_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_0_data_hi_lo = {sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_hi_hi_lo = {sectored_entries_0_0_data_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] sectored_entries_0_0_data_hi_hi_hi = {sectored_entries_0_0_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_0_data_hi_hi = {sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_0_data_hi = {sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_0_data_T = {sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_lo_lo_hi = {sectored_entries_0_1_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_1_data_lo_lo = {sectored_entries_0_1_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_lo_hi_lo = {sectored_entries_0_1_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_1_data_lo_hi_hi = {sectored_entries_0_1_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_1_data_lo_hi = {sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_1_data_lo = {sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_hi_lo_lo = {sectored_entries_0_1_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_1_data_hi_lo_hi = {sectored_entries_0_1_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_1_data_hi_lo = {sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_hi_hi_lo = {sectored_entries_0_1_data_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] sectored_entries_0_1_data_hi_hi_hi = {sectored_entries_0_1_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_1_data_hi_hi = {sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_1_data_hi = {sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_1_data_T = {sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_lo_lo_hi = {sectored_entries_0_2_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_2_data_lo_lo = {sectored_entries_0_2_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_lo_hi_lo = {sectored_entries_0_2_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_2_data_lo_hi_hi = {sectored_entries_0_2_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_2_data_lo_hi = {sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_2_data_lo = {sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_hi_lo_lo = {sectored_entries_0_2_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_2_data_hi_lo_hi = {sectored_entries_0_2_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_2_data_hi_lo = {sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_hi_hi_lo = {sectored_entries_0_2_data_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] sectored_entries_0_2_data_hi_hi_hi = {sectored_entries_0_2_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_2_data_hi_hi = {sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_2_data_hi = {sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_2_data_T = {sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_lo_lo_hi = {sectored_entries_0_3_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_3_data_lo_lo = {sectored_entries_0_3_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_lo_hi_lo = {sectored_entries_0_3_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_3_data_lo_hi_hi = {sectored_entries_0_3_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_3_data_lo_hi = {sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_3_data_lo = {sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_hi_lo_lo = {sectored_entries_0_3_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_3_data_hi_lo_hi = {sectored_entries_0_3_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_3_data_hi_lo = {sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_hi_hi_lo = {sectored_entries_0_3_data_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] sectored_entries_0_3_data_hi_hi_hi = {sectored_entries_0_3_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_3_data_hi_hi = {sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_3_data_hi = {sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_3_data_T = {sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_lo_lo_hi = {sectored_entries_0_4_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_4_data_lo_lo = {sectored_entries_0_4_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_lo_hi_lo = {sectored_entries_0_4_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_4_data_lo_hi_hi = {sectored_entries_0_4_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_4_data_lo_hi = {sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_4_data_lo = {sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_hi_lo_lo = {sectored_entries_0_4_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_4_data_hi_lo_hi = {sectored_entries_0_4_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_4_data_hi_lo = {sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_hi_hi_lo = {sectored_entries_0_4_data_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] sectored_entries_0_4_data_hi_hi_hi = {sectored_entries_0_4_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_4_data_hi_hi = {sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_4_data_hi = {sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_4_data_T = {sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_lo_lo_hi = {sectored_entries_0_5_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_5_data_lo_lo = {sectored_entries_0_5_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_lo_hi_lo = {sectored_entries_0_5_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_5_data_lo_hi_hi = {sectored_entries_0_5_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_5_data_lo_hi = {sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_5_data_lo = {sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_hi_lo_lo = {sectored_entries_0_5_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_5_data_hi_lo_hi = {sectored_entries_0_5_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_5_data_hi_lo = {sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_hi_hi_lo = {sectored_entries_0_5_data_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] sectored_entries_0_5_data_hi_hi_hi = {sectored_entries_0_5_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_5_data_hi_hi = {sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_5_data_hi = {sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_5_data_T = {sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_lo_lo_hi = {sectored_entries_0_6_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_6_data_lo_lo = {sectored_entries_0_6_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_lo_hi_lo = {sectored_entries_0_6_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_6_data_lo_hi_hi = {sectored_entries_0_6_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_6_data_lo_hi = {sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_6_data_lo = {sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_hi_lo_lo = {sectored_entries_0_6_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_6_data_hi_lo_hi = {sectored_entries_0_6_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_6_data_hi_lo = {sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_hi_hi_lo = {sectored_entries_0_6_data_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] sectored_entries_0_6_data_hi_hi_hi = {sectored_entries_0_6_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_6_data_hi_hi = {sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_6_data_hi = {sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_6_data_T = {sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_lo_lo_hi = {sectored_entries_0_7_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_7_data_lo_lo = {sectored_entries_0_7_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_lo_hi_lo = {sectored_entries_0_7_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_7_data_lo_hi_hi = {sectored_entries_0_7_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_7_data_lo_hi = {sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_7_data_lo = {sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_hi_lo_lo = {sectored_entries_0_7_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_7_data_hi_lo_hi = {sectored_entries_0_7_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_7_data_hi_lo = {sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_hi_hi_lo = {sectored_entries_0_7_data_hi_hi_lo_hi, newEntry_ae_stage2}; // @[TLB.scala:217:24, :449:24]
wire [21:0] sectored_entries_0_7_data_hi_hi_hi = {sectored_entries_0_7_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_7_data_hi_hi = {sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_7_data_hi = {sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_7_data_T = {sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24]
wire [19:0] _entries_T_23; // @[TLB.scala:170:77]
wire _entries_T_22; // @[TLB.scala:170:77]
wire _entries_T_21; // @[TLB.scala:170:77]
wire _entries_T_20; // @[TLB.scala:170:77]
wire _entries_T_19; // @[TLB.scala:170:77]
wire _entries_T_18; // @[TLB.scala:170:77]
wire _entries_T_17; // @[TLB.scala:170:77]
wire _entries_T_16; // @[TLB.scala:170:77]
wire _entries_T_15; // @[TLB.scala:170:77]
wire _entries_T_14; // @[TLB.scala:170:77]
wire _entries_T_13; // @[TLB.scala:170:77]
wire _entries_T_12; // @[TLB.scala:170:77]
wire _entries_T_11; // @[TLB.scala:170:77]
wire _entries_T_10; // @[TLB.scala:170:77]
wire _entries_T_9; // @[TLB.scala:170:77]
wire _entries_T_8; // @[TLB.scala:170:77]
wire _entries_T_7; // @[TLB.scala:170:77]
wire _entries_T_6; // @[TLB.scala:170:77]
wire _entries_T_5; // @[TLB.scala:170:77]
wire _entries_T_4; // @[TLB.scala:170:77]
wire _entries_T_3; // @[TLB.scala:170:77]
wire _entries_T_2; // @[TLB.scala:170:77]
wire _entries_T_1; // @[TLB.scala:170:77]
assign _entries_T_1 = _entries_WIRE_1[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[TLB.scala:170:77]
assign _entries_T_2 = _entries_WIRE_1[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_c = _entries_T_2; // @[TLB.scala:170:77]
assign _entries_T_3 = _entries_WIRE_1[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_eff = _entries_T_3; // @[TLB.scala:170:77]
assign _entries_T_4 = _entries_WIRE_1[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_paa = _entries_T_4; // @[TLB.scala:170:77]
assign _entries_T_5 = _entries_WIRE_1[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_pal = _entries_T_5; // @[TLB.scala:170:77]
assign _entries_T_6 = _entries_WIRE_1[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_ppp = _entries_T_6; // @[TLB.scala:170:77]
assign _entries_T_7 = _entries_WIRE_1[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_pr = _entries_T_7; // @[TLB.scala:170:77]
assign _entries_T_8 = _entries_WIRE_1[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_px = _entries_T_8; // @[TLB.scala:170:77]
assign _entries_T_9 = _entries_WIRE_1[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_pw = _entries_T_9; // @[TLB.scala:170:77]
assign _entries_T_10 = _entries_WIRE_1[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_hr = _entries_T_10; // @[TLB.scala:170:77]
assign _entries_T_11 = _entries_WIRE_1[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_hx = _entries_T_11; // @[TLB.scala:170:77]
assign _entries_T_12 = _entries_WIRE_1[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_hw = _entries_T_12; // @[TLB.scala:170:77]
assign _entries_T_13 = _entries_WIRE_1[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_sr = _entries_T_13; // @[TLB.scala:170:77]
assign _entries_T_14 = _entries_WIRE_1[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_sx = _entries_T_14; // @[TLB.scala:170:77]
assign _entries_T_15 = _entries_WIRE_1[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_sw = _entries_T_15; // @[TLB.scala:170:77]
assign _entries_T_16 = _entries_WIRE_1[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_gf = _entries_T_16; // @[TLB.scala:170:77]
assign _entries_T_17 = _entries_WIRE_1[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_pf = _entries_T_17; // @[TLB.scala:170:77]
assign _entries_T_18 = _entries_WIRE_1[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_stage2 = _entries_T_18; // @[TLB.scala:170:77]
assign _entries_T_19 = _entries_WIRE_1[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_final = _entries_T_19; // @[TLB.scala:170:77]
assign _entries_T_20 = _entries_WIRE_1[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_ptw = _entries_T_20; // @[TLB.scala:170:77]
assign _entries_T_21 = _entries_WIRE_1[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_g = _entries_T_21; // @[TLB.scala:170:77]
assign _entries_T_22 = _entries_WIRE_1[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_u = _entries_T_22; // @[TLB.scala:170:77]
assign _entries_T_23 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_ppn = _entries_T_23; // @[TLB.scala:170:77]
wire [19:0] _entries_T_47; // @[TLB.scala:170:77]
wire _entries_T_46; // @[TLB.scala:170:77]
wire _entries_T_45; // @[TLB.scala:170:77]
wire _entries_T_44; // @[TLB.scala:170:77]
wire _entries_T_43; // @[TLB.scala:170:77]
wire _entries_T_42; // @[TLB.scala:170:77]
wire _entries_T_41; // @[TLB.scala:170:77]
wire _entries_T_40; // @[TLB.scala:170:77]
wire _entries_T_39; // @[TLB.scala:170:77]
wire _entries_T_38; // @[TLB.scala:170:77]
wire _entries_T_37; // @[TLB.scala:170:77]
wire _entries_T_36; // @[TLB.scala:170:77]
wire _entries_T_35; // @[TLB.scala:170:77]
wire _entries_T_34; // @[TLB.scala:170:77]
wire _entries_T_33; // @[TLB.scala:170:77]
wire _entries_T_32; // @[TLB.scala:170:77]
wire _entries_T_31; // @[TLB.scala:170:77]
wire _entries_T_30; // @[TLB.scala:170:77]
wire _entries_T_29; // @[TLB.scala:170:77]
wire _entries_T_28; // @[TLB.scala:170:77]
wire _entries_T_27; // @[TLB.scala:170:77]
wire _entries_T_26; // @[TLB.scala:170:77]
wire _entries_T_25; // @[TLB.scala:170:77]
assign _entries_T_25 = _entries_WIRE_3[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_fragmented_superpage = _entries_T_25; // @[TLB.scala:170:77]
assign _entries_T_26 = _entries_WIRE_3[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_c = _entries_T_26; // @[TLB.scala:170:77]
assign _entries_T_27 = _entries_WIRE_3[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_eff = _entries_T_27; // @[TLB.scala:170:77]
assign _entries_T_28 = _entries_WIRE_3[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_paa = _entries_T_28; // @[TLB.scala:170:77]
assign _entries_T_29 = _entries_WIRE_3[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pal = _entries_T_29; // @[TLB.scala:170:77]
assign _entries_T_30 = _entries_WIRE_3[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ppp = _entries_T_30; // @[TLB.scala:170:77]
assign _entries_T_31 = _entries_WIRE_3[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pr = _entries_T_31; // @[TLB.scala:170:77]
assign _entries_T_32 = _entries_WIRE_3[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_px = _entries_T_32; // @[TLB.scala:170:77]
assign _entries_T_33 = _entries_WIRE_3[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pw = _entries_T_33; // @[TLB.scala:170:77]
assign _entries_T_34 = _entries_WIRE_3[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hr = _entries_T_34; // @[TLB.scala:170:77]
assign _entries_T_35 = _entries_WIRE_3[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hx = _entries_T_35; // @[TLB.scala:170:77]
assign _entries_T_36 = _entries_WIRE_3[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hw = _entries_T_36; // @[TLB.scala:170:77]
assign _entries_T_37 = _entries_WIRE_3[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sr = _entries_T_37; // @[TLB.scala:170:77]
assign _entries_T_38 = _entries_WIRE_3[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sx = _entries_T_38; // @[TLB.scala:170:77]
assign _entries_T_39 = _entries_WIRE_3[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sw = _entries_T_39; // @[TLB.scala:170:77]
assign _entries_T_40 = _entries_WIRE_3[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_gf = _entries_T_40; // @[TLB.scala:170:77]
assign _entries_T_41 = _entries_WIRE_3[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pf = _entries_T_41; // @[TLB.scala:170:77]
assign _entries_T_42 = _entries_WIRE_3[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_stage2 = _entries_T_42; // @[TLB.scala:170:77]
assign _entries_T_43 = _entries_WIRE_3[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_final = _entries_T_43; // @[TLB.scala:170:77]
assign _entries_T_44 = _entries_WIRE_3[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_ptw = _entries_T_44; // @[TLB.scala:170:77]
assign _entries_T_45 = _entries_WIRE_3[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_g = _entries_T_45; // @[TLB.scala:170:77]
assign _entries_T_46 = _entries_WIRE_3[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_u = _entries_T_46; // @[TLB.scala:170:77]
assign _entries_T_47 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_2_ppn = _entries_T_47; // @[TLB.scala:170:77]
wire [19:0] _entries_T_71; // @[TLB.scala:170:77]
wire _entries_T_70; // @[TLB.scala:170:77]
wire _entries_T_69; // @[TLB.scala:170:77]
wire _entries_T_68; // @[TLB.scala:170:77]
wire _entries_T_67; // @[TLB.scala:170:77]
wire _entries_T_66; // @[TLB.scala:170:77]
wire _entries_T_65; // @[TLB.scala:170:77]
wire _entries_T_64; // @[TLB.scala:170:77]
wire _entries_T_63; // @[TLB.scala:170:77]
wire _entries_T_62; // @[TLB.scala:170:77]
wire _entries_T_61; // @[TLB.scala:170:77]
wire _entries_T_60; // @[TLB.scala:170:77]
wire _entries_T_59; // @[TLB.scala:170:77]
wire _entries_T_58; // @[TLB.scala:170:77]
wire _entries_T_57; // @[TLB.scala:170:77]
wire _entries_T_56; // @[TLB.scala:170:77]
wire _entries_T_55; // @[TLB.scala:170:77]
wire _entries_T_54; // @[TLB.scala:170:77]
wire _entries_T_53; // @[TLB.scala:170:77]
wire _entries_T_52; // @[TLB.scala:170:77]
wire _entries_T_51; // @[TLB.scala:170:77]
wire _entries_T_50; // @[TLB.scala:170:77]
wire _entries_T_49; // @[TLB.scala:170:77]
assign _entries_T_49 = _entries_WIRE_5[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_fragmented_superpage = _entries_T_49; // @[TLB.scala:170:77]
assign _entries_T_50 = _entries_WIRE_5[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_c = _entries_T_50; // @[TLB.scala:170:77]
assign _entries_T_51 = _entries_WIRE_5[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_eff = _entries_T_51; // @[TLB.scala:170:77]
assign _entries_T_52 = _entries_WIRE_5[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_paa = _entries_T_52; // @[TLB.scala:170:77]
assign _entries_T_53 = _entries_WIRE_5[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pal = _entries_T_53; // @[TLB.scala:170:77]
assign _entries_T_54 = _entries_WIRE_5[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ppp = _entries_T_54; // @[TLB.scala:170:77]
assign _entries_T_55 = _entries_WIRE_5[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pr = _entries_T_55; // @[TLB.scala:170:77]
assign _entries_T_56 = _entries_WIRE_5[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_px = _entries_T_56; // @[TLB.scala:170:77]
assign _entries_T_57 = _entries_WIRE_5[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pw = _entries_T_57; // @[TLB.scala:170:77]
assign _entries_T_58 = _entries_WIRE_5[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hr = _entries_T_58; // @[TLB.scala:170:77]
assign _entries_T_59 = _entries_WIRE_5[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hx = _entries_T_59; // @[TLB.scala:170:77]
assign _entries_T_60 = _entries_WIRE_5[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hw = _entries_T_60; // @[TLB.scala:170:77]
assign _entries_T_61 = _entries_WIRE_5[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sr = _entries_T_61; // @[TLB.scala:170:77]
assign _entries_T_62 = _entries_WIRE_5[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sx = _entries_T_62; // @[TLB.scala:170:77]
assign _entries_T_63 = _entries_WIRE_5[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sw = _entries_T_63; // @[TLB.scala:170:77]
assign _entries_T_64 = _entries_WIRE_5[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_gf = _entries_T_64; // @[TLB.scala:170:77]
assign _entries_T_65 = _entries_WIRE_5[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pf = _entries_T_65; // @[TLB.scala:170:77]
assign _entries_T_66 = _entries_WIRE_5[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_stage2 = _entries_T_66; // @[TLB.scala:170:77]
assign _entries_T_67 = _entries_WIRE_5[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_final = _entries_T_67; // @[TLB.scala:170:77]
assign _entries_T_68 = _entries_WIRE_5[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_ptw = _entries_T_68; // @[TLB.scala:170:77]
assign _entries_T_69 = _entries_WIRE_5[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_g = _entries_T_69; // @[TLB.scala:170:77]
assign _entries_T_70 = _entries_WIRE_5[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_u = _entries_T_70; // @[TLB.scala:170:77]
assign _entries_T_71 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_4_ppn = _entries_T_71; // @[TLB.scala:170:77]
wire [19:0] _entries_T_95; // @[TLB.scala:170:77]
wire _entries_T_94; // @[TLB.scala:170:77]
wire _entries_T_93; // @[TLB.scala:170:77]
wire _entries_T_92; // @[TLB.scala:170:77]
wire _entries_T_91; // @[TLB.scala:170:77]
wire _entries_T_90; // @[TLB.scala:170:77]
wire _entries_T_89; // @[TLB.scala:170:77]
wire _entries_T_88; // @[TLB.scala:170:77]
wire _entries_T_87; // @[TLB.scala:170:77]
wire _entries_T_86; // @[TLB.scala:170:77]
wire _entries_T_85; // @[TLB.scala:170:77]
wire _entries_T_84; // @[TLB.scala:170:77]
wire _entries_T_83; // @[TLB.scala:170:77]
wire _entries_T_82; // @[TLB.scala:170:77]
wire _entries_T_81; // @[TLB.scala:170:77]
wire _entries_T_80; // @[TLB.scala:170:77]
wire _entries_T_79; // @[TLB.scala:170:77]
wire _entries_T_78; // @[TLB.scala:170:77]
wire _entries_T_77; // @[TLB.scala:170:77]
wire _entries_T_76; // @[TLB.scala:170:77]
wire _entries_T_75; // @[TLB.scala:170:77]
wire _entries_T_74; // @[TLB.scala:170:77]
wire _entries_T_73; // @[TLB.scala:170:77]
assign _entries_T_73 = _entries_WIRE_7[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_fragmented_superpage = _entries_T_73; // @[TLB.scala:170:77]
assign _entries_T_74 = _entries_WIRE_7[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_c = _entries_T_74; // @[TLB.scala:170:77]
assign _entries_T_75 = _entries_WIRE_7[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_eff = _entries_T_75; // @[TLB.scala:170:77]
assign _entries_T_76 = _entries_WIRE_7[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_paa = _entries_T_76; // @[TLB.scala:170:77]
assign _entries_T_77 = _entries_WIRE_7[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pal = _entries_T_77; // @[TLB.scala:170:77]
assign _entries_T_78 = _entries_WIRE_7[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ppp = _entries_T_78; // @[TLB.scala:170:77]
assign _entries_T_79 = _entries_WIRE_7[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pr = _entries_T_79; // @[TLB.scala:170:77]
assign _entries_T_80 = _entries_WIRE_7[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_px = _entries_T_80; // @[TLB.scala:170:77]
assign _entries_T_81 = _entries_WIRE_7[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pw = _entries_T_81; // @[TLB.scala:170:77]
assign _entries_T_82 = _entries_WIRE_7[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hr = _entries_T_82; // @[TLB.scala:170:77]
assign _entries_T_83 = _entries_WIRE_7[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hx = _entries_T_83; // @[TLB.scala:170:77]
assign _entries_T_84 = _entries_WIRE_7[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hw = _entries_T_84; // @[TLB.scala:170:77]
assign _entries_T_85 = _entries_WIRE_7[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sr = _entries_T_85; // @[TLB.scala:170:77]
assign _entries_T_86 = _entries_WIRE_7[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sx = _entries_T_86; // @[TLB.scala:170:77]
assign _entries_T_87 = _entries_WIRE_7[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sw = _entries_T_87; // @[TLB.scala:170:77]
assign _entries_T_88 = _entries_WIRE_7[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_gf = _entries_T_88; // @[TLB.scala:170:77]
assign _entries_T_89 = _entries_WIRE_7[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pf = _entries_T_89; // @[TLB.scala:170:77]
assign _entries_T_90 = _entries_WIRE_7[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_stage2 = _entries_T_90; // @[TLB.scala:170:77]
assign _entries_T_91 = _entries_WIRE_7[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_final = _entries_T_91; // @[TLB.scala:170:77]
assign _entries_T_92 = _entries_WIRE_7[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_ptw = _entries_T_92; // @[TLB.scala:170:77]
assign _entries_T_93 = _entries_WIRE_7[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_g = _entries_T_93; // @[TLB.scala:170:77]
assign _entries_T_94 = _entries_WIRE_7[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_u = _entries_T_94; // @[TLB.scala:170:77]
assign _entries_T_95 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_6_ppn = _entries_T_95; // @[TLB.scala:170:77]
wire [19:0] _entries_T_119; // @[TLB.scala:170:77]
wire _entries_T_118; // @[TLB.scala:170:77]
wire _entries_T_117; // @[TLB.scala:170:77]
wire _entries_T_116; // @[TLB.scala:170:77]
wire _entries_T_115; // @[TLB.scala:170:77]
wire _entries_T_114; // @[TLB.scala:170:77]
wire _entries_T_113; // @[TLB.scala:170:77]
wire _entries_T_112; // @[TLB.scala:170:77]
wire _entries_T_111; // @[TLB.scala:170:77]
wire _entries_T_110; // @[TLB.scala:170:77]
wire _entries_T_109; // @[TLB.scala:170:77]
wire _entries_T_108; // @[TLB.scala:170:77]
wire _entries_T_107; // @[TLB.scala:170:77]
wire _entries_T_106; // @[TLB.scala:170:77]
wire _entries_T_105; // @[TLB.scala:170:77]
wire _entries_T_104; // @[TLB.scala:170:77]
wire _entries_T_103; // @[TLB.scala:170:77]
wire _entries_T_102; // @[TLB.scala:170:77]
wire _entries_T_101; // @[TLB.scala:170:77]
wire _entries_T_100; // @[TLB.scala:170:77]
wire _entries_T_99; // @[TLB.scala:170:77]
wire _entries_T_98; // @[TLB.scala:170:77]
wire _entries_T_97; // @[TLB.scala:170:77]
assign _entries_T_97 = _entries_WIRE_9[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_fragmented_superpage = _entries_T_97; // @[TLB.scala:170:77]
assign _entries_T_98 = _entries_WIRE_9[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_c = _entries_T_98; // @[TLB.scala:170:77]
assign _entries_T_99 = _entries_WIRE_9[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_eff = _entries_T_99; // @[TLB.scala:170:77]
assign _entries_T_100 = _entries_WIRE_9[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_paa = _entries_T_100; // @[TLB.scala:170:77]
assign _entries_T_101 = _entries_WIRE_9[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pal = _entries_T_101; // @[TLB.scala:170:77]
assign _entries_T_102 = _entries_WIRE_9[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ppp = _entries_T_102; // @[TLB.scala:170:77]
assign _entries_T_103 = _entries_WIRE_9[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pr = _entries_T_103; // @[TLB.scala:170:77]
assign _entries_T_104 = _entries_WIRE_9[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_px = _entries_T_104; // @[TLB.scala:170:77]
assign _entries_T_105 = _entries_WIRE_9[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pw = _entries_T_105; // @[TLB.scala:170:77]
assign _entries_T_106 = _entries_WIRE_9[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hr = _entries_T_106; // @[TLB.scala:170:77]
assign _entries_T_107 = _entries_WIRE_9[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hx = _entries_T_107; // @[TLB.scala:170:77]
assign _entries_T_108 = _entries_WIRE_9[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hw = _entries_T_108; // @[TLB.scala:170:77]
assign _entries_T_109 = _entries_WIRE_9[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sr = _entries_T_109; // @[TLB.scala:170:77]
assign _entries_T_110 = _entries_WIRE_9[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sx = _entries_T_110; // @[TLB.scala:170:77]
assign _entries_T_111 = _entries_WIRE_9[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sw = _entries_T_111; // @[TLB.scala:170:77]
assign _entries_T_112 = _entries_WIRE_9[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_gf = _entries_T_112; // @[TLB.scala:170:77]
assign _entries_T_113 = _entries_WIRE_9[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pf = _entries_T_113; // @[TLB.scala:170:77]
assign _entries_T_114 = _entries_WIRE_9[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_stage2 = _entries_T_114; // @[TLB.scala:170:77]
assign _entries_T_115 = _entries_WIRE_9[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_final = _entries_T_115; // @[TLB.scala:170:77]
assign _entries_T_116 = _entries_WIRE_9[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_ptw = _entries_T_116; // @[TLB.scala:170:77]
assign _entries_T_117 = _entries_WIRE_9[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_g = _entries_T_117; // @[TLB.scala:170:77]
assign _entries_T_118 = _entries_WIRE_9[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_u = _entries_T_118; // @[TLB.scala:170:77]
assign _entries_T_119 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_8_ppn = _entries_T_119; // @[TLB.scala:170:77]
wire [19:0] _entries_T_143; // @[TLB.scala:170:77]
wire _entries_T_142; // @[TLB.scala:170:77]
wire _entries_T_141; // @[TLB.scala:170:77]
wire _entries_T_140; // @[TLB.scala:170:77]
wire _entries_T_139; // @[TLB.scala:170:77]
wire _entries_T_138; // @[TLB.scala:170:77]
wire _entries_T_137; // @[TLB.scala:170:77]
wire _entries_T_136; // @[TLB.scala:170:77]
wire _entries_T_135; // @[TLB.scala:170:77]
wire _entries_T_134; // @[TLB.scala:170:77]
wire _entries_T_133; // @[TLB.scala:170:77]
wire _entries_T_132; // @[TLB.scala:170:77]
wire _entries_T_131; // @[TLB.scala:170:77]
wire _entries_T_130; // @[TLB.scala:170:77]
wire _entries_T_129; // @[TLB.scala:170:77]
wire _entries_T_128; // @[TLB.scala:170:77]
wire _entries_T_127; // @[TLB.scala:170:77]
wire _entries_T_126; // @[TLB.scala:170:77]
wire _entries_T_125; // @[TLB.scala:170:77]
wire _entries_T_124; // @[TLB.scala:170:77]
wire _entries_T_123; // @[TLB.scala:170:77]
wire _entries_T_122; // @[TLB.scala:170:77]
wire _entries_T_121; // @[TLB.scala:170:77]
assign _entries_T_121 = _entries_WIRE_11[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_fragmented_superpage = _entries_T_121; // @[TLB.scala:170:77]
assign _entries_T_122 = _entries_WIRE_11[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_c = _entries_T_122; // @[TLB.scala:170:77]
assign _entries_T_123 = _entries_WIRE_11[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_eff = _entries_T_123; // @[TLB.scala:170:77]
assign _entries_T_124 = _entries_WIRE_11[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_paa = _entries_T_124; // @[TLB.scala:170:77]
assign _entries_T_125 = _entries_WIRE_11[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pal = _entries_T_125; // @[TLB.scala:170:77]
assign _entries_T_126 = _entries_WIRE_11[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ppp = _entries_T_126; // @[TLB.scala:170:77]
assign _entries_T_127 = _entries_WIRE_11[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pr = _entries_T_127; // @[TLB.scala:170:77]
assign _entries_T_128 = _entries_WIRE_11[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_px = _entries_T_128; // @[TLB.scala:170:77]
assign _entries_T_129 = _entries_WIRE_11[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pw = _entries_T_129; // @[TLB.scala:170:77]
assign _entries_T_130 = _entries_WIRE_11[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hr = _entries_T_130; // @[TLB.scala:170:77]
assign _entries_T_131 = _entries_WIRE_11[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hx = _entries_T_131; // @[TLB.scala:170:77]
assign _entries_T_132 = _entries_WIRE_11[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hw = _entries_T_132; // @[TLB.scala:170:77]
assign _entries_T_133 = _entries_WIRE_11[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sr = _entries_T_133; // @[TLB.scala:170:77]
assign _entries_T_134 = _entries_WIRE_11[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sx = _entries_T_134; // @[TLB.scala:170:77]
assign _entries_T_135 = _entries_WIRE_11[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sw = _entries_T_135; // @[TLB.scala:170:77]
assign _entries_T_136 = _entries_WIRE_11[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_gf = _entries_T_136; // @[TLB.scala:170:77]
assign _entries_T_137 = _entries_WIRE_11[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pf = _entries_T_137; // @[TLB.scala:170:77]
assign _entries_T_138 = _entries_WIRE_11[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_stage2 = _entries_T_138; // @[TLB.scala:170:77]
assign _entries_T_139 = _entries_WIRE_11[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_final = _entries_T_139; // @[TLB.scala:170:77]
assign _entries_T_140 = _entries_WIRE_11[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_ptw = _entries_T_140; // @[TLB.scala:170:77]
assign _entries_T_141 = _entries_WIRE_11[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_g = _entries_T_141; // @[TLB.scala:170:77]
assign _entries_T_142 = _entries_WIRE_11[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_u = _entries_T_142; // @[TLB.scala:170:77]
assign _entries_T_143 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_10_ppn = _entries_T_143; // @[TLB.scala:170:77]
wire [19:0] _entries_T_167; // @[TLB.scala:170:77]
wire _entries_T_166; // @[TLB.scala:170:77]
wire _entries_T_165; // @[TLB.scala:170:77]
wire _entries_T_164; // @[TLB.scala:170:77]
wire _entries_T_163; // @[TLB.scala:170:77]
wire _entries_T_162; // @[TLB.scala:170:77]
wire _entries_T_161; // @[TLB.scala:170:77]
wire _entries_T_160; // @[TLB.scala:170:77]
wire _entries_T_159; // @[TLB.scala:170:77]
wire _entries_T_158; // @[TLB.scala:170:77]
wire _entries_T_157; // @[TLB.scala:170:77]
wire _entries_T_156; // @[TLB.scala:170:77]
wire _entries_T_155; // @[TLB.scala:170:77]
wire _entries_T_154; // @[TLB.scala:170:77]
wire _entries_T_153; // @[TLB.scala:170:77]
wire _entries_T_152; // @[TLB.scala:170:77]
wire _entries_T_151; // @[TLB.scala:170:77]
wire _entries_T_150; // @[TLB.scala:170:77]
wire _entries_T_149; // @[TLB.scala:170:77]
wire _entries_T_148; // @[TLB.scala:170:77]
wire _entries_T_147; // @[TLB.scala:170:77]
wire _entries_T_146; // @[TLB.scala:170:77]
wire _entries_T_145; // @[TLB.scala:170:77]
assign _entries_T_145 = _entries_WIRE_13[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_fragmented_superpage = _entries_T_145; // @[TLB.scala:170:77]
assign _entries_T_146 = _entries_WIRE_13[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_c = _entries_T_146; // @[TLB.scala:170:77]
assign _entries_T_147 = _entries_WIRE_13[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_eff = _entries_T_147; // @[TLB.scala:170:77]
assign _entries_T_148 = _entries_WIRE_13[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_paa = _entries_T_148; // @[TLB.scala:170:77]
assign _entries_T_149 = _entries_WIRE_13[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pal = _entries_T_149; // @[TLB.scala:170:77]
assign _entries_T_150 = _entries_WIRE_13[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ppp = _entries_T_150; // @[TLB.scala:170:77]
assign _entries_T_151 = _entries_WIRE_13[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pr = _entries_T_151; // @[TLB.scala:170:77]
assign _entries_T_152 = _entries_WIRE_13[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_px = _entries_T_152; // @[TLB.scala:170:77]
assign _entries_T_153 = _entries_WIRE_13[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pw = _entries_T_153; // @[TLB.scala:170:77]
assign _entries_T_154 = _entries_WIRE_13[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hr = _entries_T_154; // @[TLB.scala:170:77]
assign _entries_T_155 = _entries_WIRE_13[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hx = _entries_T_155; // @[TLB.scala:170:77]
assign _entries_T_156 = _entries_WIRE_13[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hw = _entries_T_156; // @[TLB.scala:170:77]
assign _entries_T_157 = _entries_WIRE_13[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sr = _entries_T_157; // @[TLB.scala:170:77]
assign _entries_T_158 = _entries_WIRE_13[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sx = _entries_T_158; // @[TLB.scala:170:77]
assign _entries_T_159 = _entries_WIRE_13[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sw = _entries_T_159; // @[TLB.scala:170:77]
assign _entries_T_160 = _entries_WIRE_13[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_gf = _entries_T_160; // @[TLB.scala:170:77]
assign _entries_T_161 = _entries_WIRE_13[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pf = _entries_T_161; // @[TLB.scala:170:77]
assign _entries_T_162 = _entries_WIRE_13[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_stage2 = _entries_T_162; // @[TLB.scala:170:77]
assign _entries_T_163 = _entries_WIRE_13[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_final = _entries_T_163; // @[TLB.scala:170:77]
assign _entries_T_164 = _entries_WIRE_13[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_ptw = _entries_T_164; // @[TLB.scala:170:77]
assign _entries_T_165 = _entries_WIRE_13[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_g = _entries_T_165; // @[TLB.scala:170:77]
assign _entries_T_166 = _entries_WIRE_13[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_u = _entries_T_166; // @[TLB.scala:170:77]
assign _entries_T_167 = _entries_WIRE_13[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_12_ppn = _entries_T_167; // @[TLB.scala:170:77]
wire [19:0] _entries_T_191; // @[TLB.scala:170:77]
wire _entries_T_190; // @[TLB.scala:170:77]
wire _entries_T_189; // @[TLB.scala:170:77]
wire _entries_T_188; // @[TLB.scala:170:77]
wire _entries_T_187; // @[TLB.scala:170:77]
wire _entries_T_186; // @[TLB.scala:170:77]
wire _entries_T_185; // @[TLB.scala:170:77]
wire _entries_T_184; // @[TLB.scala:170:77]
wire _entries_T_183; // @[TLB.scala:170:77]
wire _entries_T_182; // @[TLB.scala:170:77]
wire _entries_T_181; // @[TLB.scala:170:77]
wire _entries_T_180; // @[TLB.scala:170:77]
wire _entries_T_179; // @[TLB.scala:170:77]
wire _entries_T_178; // @[TLB.scala:170:77]
wire _entries_T_177; // @[TLB.scala:170:77]
wire _entries_T_176; // @[TLB.scala:170:77]
wire _entries_T_175; // @[TLB.scala:170:77]
wire _entries_T_174; // @[TLB.scala:170:77]
wire _entries_T_173; // @[TLB.scala:170:77]
wire _entries_T_172; // @[TLB.scala:170:77]
wire _entries_T_171; // @[TLB.scala:170:77]
wire _entries_T_170; // @[TLB.scala:170:77]
wire _entries_T_169; // @[TLB.scala:170:77]
assign _entries_T_169 = _entries_WIRE_15[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_fragmented_superpage = _entries_T_169; // @[TLB.scala:170:77]
assign _entries_T_170 = _entries_WIRE_15[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_c = _entries_T_170; // @[TLB.scala:170:77]
assign _entries_T_171 = _entries_WIRE_15[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_eff = _entries_T_171; // @[TLB.scala:170:77]
assign _entries_T_172 = _entries_WIRE_15[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_paa = _entries_T_172; // @[TLB.scala:170:77]
assign _entries_T_173 = _entries_WIRE_15[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pal = _entries_T_173; // @[TLB.scala:170:77]
assign _entries_T_174 = _entries_WIRE_15[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ppp = _entries_T_174; // @[TLB.scala:170:77]
assign _entries_T_175 = _entries_WIRE_15[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pr = _entries_T_175; // @[TLB.scala:170:77]
assign _entries_T_176 = _entries_WIRE_15[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_px = _entries_T_176; // @[TLB.scala:170:77]
assign _entries_T_177 = _entries_WIRE_15[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pw = _entries_T_177; // @[TLB.scala:170:77]
assign _entries_T_178 = _entries_WIRE_15[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hr = _entries_T_178; // @[TLB.scala:170:77]
assign _entries_T_179 = _entries_WIRE_15[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hx = _entries_T_179; // @[TLB.scala:170:77]
assign _entries_T_180 = _entries_WIRE_15[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hw = _entries_T_180; // @[TLB.scala:170:77]
assign _entries_T_181 = _entries_WIRE_15[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sr = _entries_T_181; // @[TLB.scala:170:77]
assign _entries_T_182 = _entries_WIRE_15[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sx = _entries_T_182; // @[TLB.scala:170:77]
assign _entries_T_183 = _entries_WIRE_15[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sw = _entries_T_183; // @[TLB.scala:170:77]
assign _entries_T_184 = _entries_WIRE_15[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_gf = _entries_T_184; // @[TLB.scala:170:77]
assign _entries_T_185 = _entries_WIRE_15[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pf = _entries_T_185; // @[TLB.scala:170:77]
assign _entries_T_186 = _entries_WIRE_15[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_stage2 = _entries_T_186; // @[TLB.scala:170:77]
assign _entries_T_187 = _entries_WIRE_15[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_final = _entries_T_187; // @[TLB.scala:170:77]
assign _entries_T_188 = _entries_WIRE_15[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_ptw = _entries_T_188; // @[TLB.scala:170:77]
assign _entries_T_189 = _entries_WIRE_15[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_g = _entries_T_189; // @[TLB.scala:170:77]
assign _entries_T_190 = _entries_WIRE_15[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_u = _entries_T_190; // @[TLB.scala:170:77]
assign _entries_T_191 = _entries_WIRE_15[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_14_ppn = _entries_T_191; // @[TLB.scala:170:77]
wire [19:0] _entries_T_214; // @[TLB.scala:170:77]
wire _entries_T_213; // @[TLB.scala:170:77]
wire _entries_T_212; // @[TLB.scala:170:77]
wire _entries_T_211; // @[TLB.scala:170:77]
wire _entries_T_210; // @[TLB.scala:170:77]
wire _entries_T_209; // @[TLB.scala:170:77]
wire _entries_T_208; // @[TLB.scala:170:77]
wire _entries_T_207; // @[TLB.scala:170:77]
wire _entries_T_206; // @[TLB.scala:170:77]
wire _entries_T_205; // @[TLB.scala:170:77]
wire _entries_T_204; // @[TLB.scala:170:77]
wire _entries_T_203; // @[TLB.scala:170:77]
wire _entries_T_202; // @[TLB.scala:170:77]
wire _entries_T_201; // @[TLB.scala:170:77]
wire _entries_T_200; // @[TLB.scala:170:77]
wire _entries_T_199; // @[TLB.scala:170:77]
wire _entries_T_198; // @[TLB.scala:170:77]
wire _entries_T_197; // @[TLB.scala:170:77]
wire _entries_T_196; // @[TLB.scala:170:77]
wire _entries_T_195; // @[TLB.scala:170:77]
wire _entries_T_194; // @[TLB.scala:170:77]
wire _entries_T_193; // @[TLB.scala:170:77]
wire _entries_T_192; // @[TLB.scala:170:77]
assign _entries_T_192 = _entries_WIRE_17[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_fragmented_superpage = _entries_T_192; // @[TLB.scala:170:77]
assign _entries_T_193 = _entries_WIRE_17[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_c = _entries_T_193; // @[TLB.scala:170:77]
assign _entries_T_194 = _entries_WIRE_17[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_eff = _entries_T_194; // @[TLB.scala:170:77]
assign _entries_T_195 = _entries_WIRE_17[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_paa = _entries_T_195; // @[TLB.scala:170:77]
assign _entries_T_196 = _entries_WIRE_17[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pal = _entries_T_196; // @[TLB.scala:170:77]
assign _entries_T_197 = _entries_WIRE_17[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ppp = _entries_T_197; // @[TLB.scala:170:77]
assign _entries_T_198 = _entries_WIRE_17[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pr = _entries_T_198; // @[TLB.scala:170:77]
assign _entries_T_199 = _entries_WIRE_17[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_px = _entries_T_199; // @[TLB.scala:170:77]
assign _entries_T_200 = _entries_WIRE_17[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pw = _entries_T_200; // @[TLB.scala:170:77]
assign _entries_T_201 = _entries_WIRE_17[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hr = _entries_T_201; // @[TLB.scala:170:77]
assign _entries_T_202 = _entries_WIRE_17[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hx = _entries_T_202; // @[TLB.scala:170:77]
assign _entries_T_203 = _entries_WIRE_17[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hw = _entries_T_203; // @[TLB.scala:170:77]
assign _entries_T_204 = _entries_WIRE_17[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sr = _entries_T_204; // @[TLB.scala:170:77]
assign _entries_T_205 = _entries_WIRE_17[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sx = _entries_T_205; // @[TLB.scala:170:77]
assign _entries_T_206 = _entries_WIRE_17[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sw = _entries_T_206; // @[TLB.scala:170:77]
assign _entries_T_207 = _entries_WIRE_17[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_gf = _entries_T_207; // @[TLB.scala:170:77]
assign _entries_T_208 = _entries_WIRE_17[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pf = _entries_T_208; // @[TLB.scala:170:77]
assign _entries_T_209 = _entries_WIRE_17[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_stage2 = _entries_T_209; // @[TLB.scala:170:77]
assign _entries_T_210 = _entries_WIRE_17[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_final = _entries_T_210; // @[TLB.scala:170:77]
assign _entries_T_211 = _entries_WIRE_17[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_ptw = _entries_T_211; // @[TLB.scala:170:77]
assign _entries_T_212 = _entries_WIRE_17[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_g = _entries_T_212; // @[TLB.scala:170:77]
assign _entries_T_213 = _entries_WIRE_17[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_u = _entries_T_213; // @[TLB.scala:170:77]
assign _entries_T_214 = _entries_WIRE_17[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_16_ppn = _entries_T_214; // @[TLB.scala:170:77]
wire [19:0] _entries_T_237; // @[TLB.scala:170:77]
wire _entries_T_236; // @[TLB.scala:170:77]
wire _entries_T_235; // @[TLB.scala:170:77]
wire _entries_T_234; // @[TLB.scala:170:77]
wire _entries_T_233; // @[TLB.scala:170:77]
wire _entries_T_232; // @[TLB.scala:170:77]
wire _entries_T_231; // @[TLB.scala:170:77]
wire _entries_T_230; // @[TLB.scala:170:77]
wire _entries_T_229; // @[TLB.scala:170:77]
wire _entries_T_228; // @[TLB.scala:170:77]
wire _entries_T_227; // @[TLB.scala:170:77]
wire _entries_T_226; // @[TLB.scala:170:77]
wire _entries_T_225; // @[TLB.scala:170:77]
wire _entries_T_224; // @[TLB.scala:170:77]
wire _entries_T_223; // @[TLB.scala:170:77]
wire _entries_T_222; // @[TLB.scala:170:77]
wire _entries_T_221; // @[TLB.scala:170:77]
wire _entries_T_220; // @[TLB.scala:170:77]
wire _entries_T_219; // @[TLB.scala:170:77]
wire _entries_T_218; // @[TLB.scala:170:77]
wire _entries_T_217; // @[TLB.scala:170:77]
wire _entries_T_216; // @[TLB.scala:170:77]
wire _entries_T_215; // @[TLB.scala:170:77]
assign _entries_T_215 = _entries_WIRE_19[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_fragmented_superpage = _entries_T_215; // @[TLB.scala:170:77]
assign _entries_T_216 = _entries_WIRE_19[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_c = _entries_T_216; // @[TLB.scala:170:77]
assign _entries_T_217 = _entries_WIRE_19[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_eff = _entries_T_217; // @[TLB.scala:170:77]
assign _entries_T_218 = _entries_WIRE_19[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_paa = _entries_T_218; // @[TLB.scala:170:77]
assign _entries_T_219 = _entries_WIRE_19[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pal = _entries_T_219; // @[TLB.scala:170:77]
assign _entries_T_220 = _entries_WIRE_19[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ppp = _entries_T_220; // @[TLB.scala:170:77]
assign _entries_T_221 = _entries_WIRE_19[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pr = _entries_T_221; // @[TLB.scala:170:77]
assign _entries_T_222 = _entries_WIRE_19[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_px = _entries_T_222; // @[TLB.scala:170:77]
assign _entries_T_223 = _entries_WIRE_19[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pw = _entries_T_223; // @[TLB.scala:170:77]
assign _entries_T_224 = _entries_WIRE_19[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hr = _entries_T_224; // @[TLB.scala:170:77]
assign _entries_T_225 = _entries_WIRE_19[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hx = _entries_T_225; // @[TLB.scala:170:77]
assign _entries_T_226 = _entries_WIRE_19[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hw = _entries_T_226; // @[TLB.scala:170:77]
assign _entries_T_227 = _entries_WIRE_19[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sr = _entries_T_227; // @[TLB.scala:170:77]
assign _entries_T_228 = _entries_WIRE_19[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sx = _entries_T_228; // @[TLB.scala:170:77]
assign _entries_T_229 = _entries_WIRE_19[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sw = _entries_T_229; // @[TLB.scala:170:77]
assign _entries_T_230 = _entries_WIRE_19[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_gf = _entries_T_230; // @[TLB.scala:170:77]
assign _entries_T_231 = _entries_WIRE_19[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pf = _entries_T_231; // @[TLB.scala:170:77]
assign _entries_T_232 = _entries_WIRE_19[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_stage2 = _entries_T_232; // @[TLB.scala:170:77]
assign _entries_T_233 = _entries_WIRE_19[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_final = _entries_T_233; // @[TLB.scala:170:77]
assign _entries_T_234 = _entries_WIRE_19[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_ptw = _entries_T_234; // @[TLB.scala:170:77]
assign _entries_T_235 = _entries_WIRE_19[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_g = _entries_T_235; // @[TLB.scala:170:77]
assign _entries_T_236 = _entries_WIRE_19[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_u = _entries_T_236; // @[TLB.scala:170:77]
assign _entries_T_237 = _entries_WIRE_19[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_18_ppn = _entries_T_237; // @[TLB.scala:170:77]
wire [19:0] _entries_T_260; // @[TLB.scala:170:77]
wire _entries_T_259; // @[TLB.scala:170:77]
wire _entries_T_258; // @[TLB.scala:170:77]
wire _entries_T_257; // @[TLB.scala:170:77]
wire _entries_T_256; // @[TLB.scala:170:77]
wire _entries_T_255; // @[TLB.scala:170:77]
wire _entries_T_254; // @[TLB.scala:170:77]
wire _entries_T_253; // @[TLB.scala:170:77]
wire _entries_T_252; // @[TLB.scala:170:77]
wire _entries_T_251; // @[TLB.scala:170:77]
wire _entries_T_250; // @[TLB.scala:170:77]
wire _entries_T_249; // @[TLB.scala:170:77]
wire _entries_T_248; // @[TLB.scala:170:77]
wire _entries_T_247; // @[TLB.scala:170:77]
wire _entries_T_246; // @[TLB.scala:170:77]
wire _entries_T_245; // @[TLB.scala:170:77]
wire _entries_T_244; // @[TLB.scala:170:77]
wire _entries_T_243; // @[TLB.scala:170:77]
wire _entries_T_242; // @[TLB.scala:170:77]
wire _entries_T_241; // @[TLB.scala:170:77]
wire _entries_T_240; // @[TLB.scala:170:77]
wire _entries_T_239; // @[TLB.scala:170:77]
wire _entries_T_238; // @[TLB.scala:170:77]
assign _entries_T_238 = _entries_WIRE_21[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_fragmented_superpage = _entries_T_238; // @[TLB.scala:170:77]
assign _entries_T_239 = _entries_WIRE_21[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_c = _entries_T_239; // @[TLB.scala:170:77]
assign _entries_T_240 = _entries_WIRE_21[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_eff = _entries_T_240; // @[TLB.scala:170:77]
assign _entries_T_241 = _entries_WIRE_21[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_paa = _entries_T_241; // @[TLB.scala:170:77]
assign _entries_T_242 = _entries_WIRE_21[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pal = _entries_T_242; // @[TLB.scala:170:77]
assign _entries_T_243 = _entries_WIRE_21[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ppp = _entries_T_243; // @[TLB.scala:170:77]
assign _entries_T_244 = _entries_WIRE_21[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pr = _entries_T_244; // @[TLB.scala:170:77]
assign _entries_T_245 = _entries_WIRE_21[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_px = _entries_T_245; // @[TLB.scala:170:77]
assign _entries_T_246 = _entries_WIRE_21[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pw = _entries_T_246; // @[TLB.scala:170:77]
assign _entries_T_247 = _entries_WIRE_21[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hr = _entries_T_247; // @[TLB.scala:170:77]
assign _entries_T_248 = _entries_WIRE_21[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hx = _entries_T_248; // @[TLB.scala:170:77]
assign _entries_T_249 = _entries_WIRE_21[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hw = _entries_T_249; // @[TLB.scala:170:77]
assign _entries_T_250 = _entries_WIRE_21[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sr = _entries_T_250; // @[TLB.scala:170:77]
assign _entries_T_251 = _entries_WIRE_21[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sx = _entries_T_251; // @[TLB.scala:170:77]
assign _entries_T_252 = _entries_WIRE_21[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sw = _entries_T_252; // @[TLB.scala:170:77]
assign _entries_T_253 = _entries_WIRE_21[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_gf = _entries_T_253; // @[TLB.scala:170:77]
assign _entries_T_254 = _entries_WIRE_21[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pf = _entries_T_254; // @[TLB.scala:170:77]
assign _entries_T_255 = _entries_WIRE_21[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_stage2 = _entries_T_255; // @[TLB.scala:170:77]
assign _entries_T_256 = _entries_WIRE_21[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_final = _entries_T_256; // @[TLB.scala:170:77]
assign _entries_T_257 = _entries_WIRE_21[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_ptw = _entries_T_257; // @[TLB.scala:170:77]
assign _entries_T_258 = _entries_WIRE_21[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_g = _entries_T_258; // @[TLB.scala:170:77]
assign _entries_T_259 = _entries_WIRE_21[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_u = _entries_T_259; // @[TLB.scala:170:77]
assign _entries_T_260 = _entries_WIRE_21[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_20_ppn = _entries_T_260; // @[TLB.scala:170:77]
wire [19:0] _entries_T_283; // @[TLB.scala:170:77]
wire _entries_T_282; // @[TLB.scala:170:77]
wire _entries_T_281; // @[TLB.scala:170:77]
wire _entries_T_280; // @[TLB.scala:170:77]
wire _entries_T_279; // @[TLB.scala:170:77]
wire _entries_T_278; // @[TLB.scala:170:77]
wire _entries_T_277; // @[TLB.scala:170:77]
wire _entries_T_276; // @[TLB.scala:170:77]
wire _entries_T_275; // @[TLB.scala:170:77]
wire _entries_T_274; // @[TLB.scala:170:77]
wire _entries_T_273; // @[TLB.scala:170:77]
wire _entries_T_272; // @[TLB.scala:170:77]
wire _entries_T_271; // @[TLB.scala:170:77]
wire _entries_T_270; // @[TLB.scala:170:77]
wire _entries_T_269; // @[TLB.scala:170:77]
wire _entries_T_268; // @[TLB.scala:170:77]
wire _entries_T_267; // @[TLB.scala:170:77]
wire _entries_T_266; // @[TLB.scala:170:77]
wire _entries_T_265; // @[TLB.scala:170:77]
wire _entries_T_264; // @[TLB.scala:170:77]
wire _entries_T_263; // @[TLB.scala:170:77]
wire _entries_T_262; // @[TLB.scala:170:77]
wire _entries_T_261; // @[TLB.scala:170:77]
assign _entries_T_261 = _entries_WIRE_23[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_fragmented_superpage = _entries_T_261; // @[TLB.scala:170:77]
assign _entries_T_262 = _entries_WIRE_23[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_c = _entries_T_262; // @[TLB.scala:170:77]
assign _entries_T_263 = _entries_WIRE_23[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_eff = _entries_T_263; // @[TLB.scala:170:77]
assign _entries_T_264 = _entries_WIRE_23[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_paa = _entries_T_264; // @[TLB.scala:170:77]
assign _entries_T_265 = _entries_WIRE_23[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pal = _entries_T_265; // @[TLB.scala:170:77]
assign _entries_T_266 = _entries_WIRE_23[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ppp = _entries_T_266; // @[TLB.scala:170:77]
assign _entries_T_267 = _entries_WIRE_23[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pr = _entries_T_267; // @[TLB.scala:170:77]
assign _entries_T_268 = _entries_WIRE_23[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_px = _entries_T_268; // @[TLB.scala:170:77]
assign _entries_T_269 = _entries_WIRE_23[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pw = _entries_T_269; // @[TLB.scala:170:77]
assign _entries_T_270 = _entries_WIRE_23[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hr = _entries_T_270; // @[TLB.scala:170:77]
assign _entries_T_271 = _entries_WIRE_23[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hx = _entries_T_271; // @[TLB.scala:170:77]
assign _entries_T_272 = _entries_WIRE_23[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hw = _entries_T_272; // @[TLB.scala:170:77]
assign _entries_T_273 = _entries_WIRE_23[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sr = _entries_T_273; // @[TLB.scala:170:77]
assign _entries_T_274 = _entries_WIRE_23[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sx = _entries_T_274; // @[TLB.scala:170:77]
assign _entries_T_275 = _entries_WIRE_23[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sw = _entries_T_275; // @[TLB.scala:170:77]
assign _entries_T_276 = _entries_WIRE_23[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_gf = _entries_T_276; // @[TLB.scala:170:77]
assign _entries_T_277 = _entries_WIRE_23[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pf = _entries_T_277; // @[TLB.scala:170:77]
assign _entries_T_278 = _entries_WIRE_23[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_stage2 = _entries_T_278; // @[TLB.scala:170:77]
assign _entries_T_279 = _entries_WIRE_23[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_final = _entries_T_279; // @[TLB.scala:170:77]
assign _entries_T_280 = _entries_WIRE_23[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_ptw = _entries_T_280; // @[TLB.scala:170:77]
assign _entries_T_281 = _entries_WIRE_23[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_g = _entries_T_281; // @[TLB.scala:170:77]
assign _entries_T_282 = _entries_WIRE_23[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_u = _entries_T_282; // @[TLB.scala:170:77]
assign _entries_T_283 = _entries_WIRE_23[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_22_ppn = _entries_T_283; // @[TLB.scala:170:77]
wire [19:0] _entries_T_306; // @[TLB.scala:170:77]
wire _entries_T_305; // @[TLB.scala:170:77]
wire _entries_T_304; // @[TLB.scala:170:77]
wire _entries_T_303; // @[TLB.scala:170:77]
wire _entries_T_302; // @[TLB.scala:170:77]
wire _entries_T_301; // @[TLB.scala:170:77]
wire _entries_T_300; // @[TLB.scala:170:77]
wire _entries_T_299; // @[TLB.scala:170:77]
wire _entries_T_298; // @[TLB.scala:170:77]
wire _entries_T_297; // @[TLB.scala:170:77]
wire _entries_T_296; // @[TLB.scala:170:77]
wire _entries_T_295; // @[TLB.scala:170:77]
wire _entries_T_294; // @[TLB.scala:170:77]
wire _entries_T_293; // @[TLB.scala:170:77]
wire _entries_T_292; // @[TLB.scala:170:77]
wire _entries_T_291; // @[TLB.scala:170:77]
wire _entries_T_290; // @[TLB.scala:170:77]
wire _entries_T_289; // @[TLB.scala:170:77]
wire _entries_T_288; // @[TLB.scala:170:77]
wire _entries_T_287; // @[TLB.scala:170:77]
wire _entries_T_286; // @[TLB.scala:170:77]
wire _entries_T_285; // @[TLB.scala:170:77]
wire _entries_T_284; // @[TLB.scala:170:77]
assign _entries_T_284 = _entries_WIRE_25[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_fragmented_superpage = _entries_T_284; // @[TLB.scala:170:77]
assign _entries_T_285 = _entries_WIRE_25[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_c = _entries_T_285; // @[TLB.scala:170:77]
assign _entries_T_286 = _entries_WIRE_25[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_eff = _entries_T_286; // @[TLB.scala:170:77]
assign _entries_T_287 = _entries_WIRE_25[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_paa = _entries_T_287; // @[TLB.scala:170:77]
assign _entries_T_288 = _entries_WIRE_25[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pal = _entries_T_288; // @[TLB.scala:170:77]
assign _entries_T_289 = _entries_WIRE_25[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ppp = _entries_T_289; // @[TLB.scala:170:77]
assign _entries_T_290 = _entries_WIRE_25[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pr = _entries_T_290; // @[TLB.scala:170:77]
assign _entries_T_291 = _entries_WIRE_25[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_px = _entries_T_291; // @[TLB.scala:170:77]
assign _entries_T_292 = _entries_WIRE_25[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pw = _entries_T_292; // @[TLB.scala:170:77]
assign _entries_T_293 = _entries_WIRE_25[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hr = _entries_T_293; // @[TLB.scala:170:77]
assign _entries_T_294 = _entries_WIRE_25[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hx = _entries_T_294; // @[TLB.scala:170:77]
assign _entries_T_295 = _entries_WIRE_25[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hw = _entries_T_295; // @[TLB.scala:170:77]
assign _entries_T_296 = _entries_WIRE_25[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sr = _entries_T_296; // @[TLB.scala:170:77]
assign _entries_T_297 = _entries_WIRE_25[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sx = _entries_T_297; // @[TLB.scala:170:77]
assign _entries_T_298 = _entries_WIRE_25[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sw = _entries_T_298; // @[TLB.scala:170:77]
assign _entries_T_299 = _entries_WIRE_25[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_gf = _entries_T_299; // @[TLB.scala:170:77]
assign _entries_T_300 = _entries_WIRE_25[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pf = _entries_T_300; // @[TLB.scala:170:77]
assign _entries_T_301 = _entries_WIRE_25[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_stage2 = _entries_T_301; // @[TLB.scala:170:77]
assign _entries_T_302 = _entries_WIRE_25[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_final = _entries_T_302; // @[TLB.scala:170:77]
assign _entries_T_303 = _entries_WIRE_25[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_ptw = _entries_T_303; // @[TLB.scala:170:77]
assign _entries_T_304 = _entries_WIRE_25[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_g = _entries_T_304; // @[TLB.scala:170:77]
assign _entries_T_305 = _entries_WIRE_25[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_u = _entries_T_305; // @[TLB.scala:170:77]
assign _entries_T_306 = _entries_WIRE_25[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_24_ppn = _entries_T_306; // @[TLB.scala:170:77]
wire [19:0] _ppn_T_1 = vpn[19:0]; // @[TLB.scala:335:30, :502:125]
wire [19:0] _ppn_T_15 = _ppn_T_1; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_28 = _ppn_T_15; // @[Mux.scala:30:73]
wire [19:0] ppn = _ppn_T_28; // @[Mux.scala:30:73]
wire [1:0] ptw_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_ptw, _entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_ptw, _entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_ptw, _entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27]
wire [1:0] final_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_lo_lo = {final_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_lo_hi = {final_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [5:0] final_ae_array_lo = {final_ae_array_lo_hi, final_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] final_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_final, _entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_hi_lo = {final_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_final, _entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_final, _entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [3:0] final_ae_array_hi_hi = {final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] final_ae_array_hi = {final_ae_array_hi_hi, final_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27]
wire [1:0] ptw_pf_array_lo_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_lo_lo = {ptw_pf_array_lo_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_lo_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_lo_hi = {ptw_pf_array_lo_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, ptw_pf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_pf_array_hi_lo_hi = {_entries_barrier_8_io_y_pf, _entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_hi_lo = {ptw_pf_array_hi_lo_hi, _entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_hi_hi_lo = {_entries_barrier_10_io_y_pf, _entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_hi_hi_hi = {_entries_barrier_12_io_y_pf, _entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_pf_array_hi_hi = {ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, ptw_pf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27]
wire [1:0] ptw_gf_array_lo_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_lo_lo = {ptw_gf_array_lo_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_lo_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_lo_hi = {ptw_gf_array_lo_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, ptw_gf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_gf_array_hi_lo_hi = {_entries_barrier_8_io_y_gf, _entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_hi_lo = {ptw_gf_array_hi_lo_hi, _entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_hi_hi_lo = {_entries_barrier_10_io_y_gf, _entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_hi_hi_hi = {_entries_barrier_12_io_y_gf, _entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_gf_array_hi_hi = {ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, ptw_gf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27]
wire [13:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82]
wire [13:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63]
wire [13:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46]
wire _priv_rw_ok_T = ~priv_s; // @[TLB.scala:370:20, :513:24]
wire _priv_rw_ok_T_1 = _priv_rw_ok_T; // @[TLB.scala:513:{24,32}]
wire [1:0] _GEN_10 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_lo_hi = _GEN_10; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_lo_hi_1 = _GEN_10; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_lo_hi = _GEN_10; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_lo_hi_1 = _GEN_10; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_11 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_hi = _GEN_11; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_hi_1 = _GEN_11; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_hi = _GEN_11; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_hi_1 = _GEN_11; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_12 = {_entries_barrier_8_io_y_u, _entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_lo_hi = _GEN_12; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_lo_hi_1 = _GEN_12; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_lo_hi = _GEN_12; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_lo_hi_1 = _GEN_12; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_13 = {_entries_barrier_10_io_y_u, _entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_lo = _GEN_13; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_lo_1 = _GEN_13; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_lo = _GEN_13; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_lo_1 = _GEN_13; // @[package.scala:45:27]
wire [1:0] _GEN_14 = {_entries_barrier_12_io_y_u, _entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_hi = _GEN_14; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_hi_1 = _GEN_14; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_hi = _GEN_14; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_hi_1 = _GEN_14; // @[package.scala:45:27]
wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_1 ? _priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_6 = priv_s ? _priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}]
wire [12:0] priv_rw_ok = _priv_rw_ok_T_3 | _priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}]
wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27]
wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] priv_x_ok = priv_s ? _priv_x_ok_T_1 : _priv_x_ok_T_2; // @[package.scala:45:27]
wire [1:0] stage1_bypass_lo_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_lo_lo = {stage1_bypass_lo_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_lo_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_lo_hi = {stage1_bypass_lo_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [5:0] stage1_bypass_lo = {stage1_bypass_lo_hi, stage1_bypass_lo_lo}; // @[package.scala:45:27]
wire [1:0] stage1_bypass_hi_lo_hi = {_entries_barrier_8_io_y_ae_stage2, _entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_hi_lo = {stage1_bypass_hi_lo_hi, _entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_hi_hi_lo = {_entries_barrier_10_io_y_ae_stage2, _entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_hi_hi_hi = {_entries_barrier_12_io_y_ae_stage2, _entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [3:0] stage1_bypass_hi_hi = {stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] stage1_bypass_hi = {stage1_bypass_hi_hi, stage1_bypass_hi_lo}; // @[package.scala:45:27]
wire [12:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27]
wire [1:0] r_array_lo_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] r_array_hi_lo_hi = {_entries_barrier_8_io_y_sr, _entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, _entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_lo = {_entries_barrier_10_io_y_sr, _entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_hi = {_entries_barrier_12_io_y_sr, _entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27]
wire [12:0] _r_array_T_3 = _r_array_T; // @[package.scala:45:27]
wire [1:0] _GEN_15 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27]
assign r_array_lo_lo_hi_1 = _GEN_15; // @[package.scala:45:27]
wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27]
assign x_array_lo_lo_hi = _GEN_15; // @[package.scala:45:27]
wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_16 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27]
assign r_array_lo_hi_hi_1 = _GEN_16; // @[package.scala:45:27]
wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27]
assign x_array_lo_hi_hi = _GEN_16; // @[package.scala:45:27]
wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_17 = {_entries_barrier_8_io_y_sx, _entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27]
assign r_array_hi_lo_hi_1 = _GEN_17; // @[package.scala:45:27]
wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27]
assign x_array_hi_lo_hi = _GEN_17; // @[package.scala:45:27]
wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_18 = {_entries_barrier_10_io_y_sx, _entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27]
assign r_array_hi_hi_lo_1 = _GEN_18; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27]
assign x_array_hi_hi_lo = _GEN_18; // @[package.scala:45:27]
wire [1:0] _GEN_19 = {_entries_barrier_12_io_y_sx, _entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27]
assign r_array_hi_hi_hi_1 = _GEN_19; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27]
assign x_array_hi_hi_hi = _GEN_19; // @[package.scala:45:27]
wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27]
wire [12:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}]
wire [12:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}]
wire [13:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}]
wire [13:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41]
wire [1:0] w_array_lo_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_lo_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] w_array_hi_lo_hi = {_entries_barrier_8_io_y_sw, _entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, _entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_hi_hi_lo = {_entries_barrier_10_io_y_sw, _entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_hi_hi_hi = {_entries_barrier_12_io_y_sw, _entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27]
wire [12:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27]
wire [12:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}]
wire [13:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}]
wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27]
wire [12:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27]
wire [12:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}]
wire [13:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}]
wire [1:0] hr_array_lo_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_lo_lo = {hr_array_lo_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_lo_hi = {hr_array_lo_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [5:0] hr_array_lo = {hr_array_lo_hi, hr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] hr_array_hi_lo_hi = {_entries_barrier_8_io_y_hr, _entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_hi_lo = {hr_array_hi_lo_hi, _entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_lo = {_entries_barrier_10_io_y_hr, _entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_hi = {_entries_barrier_12_io_y_hr, _entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [3:0] hr_array_hi_hi = {hr_array_hi_hi_hi, hr_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hr_array_hi = {hr_array_hi_hi, hr_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27]
wire [12:0] _hr_array_T_3 = _hr_array_T; // @[package.scala:45:27]
wire [1:0] _GEN_20 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_lo_hi_1; // @[package.scala:45:27]
assign hr_array_lo_lo_hi_1 = _GEN_20; // @[package.scala:45:27]
wire [1:0] hx_array_lo_lo_hi; // @[package.scala:45:27]
assign hx_array_lo_lo_hi = _GEN_20; // @[package.scala:45:27]
wire [2:0] hr_array_lo_lo_1 = {hr_array_lo_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_21 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_hi_hi_1; // @[package.scala:45:27]
assign hr_array_lo_hi_hi_1 = _GEN_21; // @[package.scala:45:27]
wire [1:0] hx_array_lo_hi_hi; // @[package.scala:45:27]
assign hx_array_lo_hi_hi = _GEN_21; // @[package.scala:45:27]
wire [2:0] hr_array_lo_hi_1 = {hr_array_lo_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] hr_array_lo_1 = {hr_array_lo_hi_1, hr_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_22 = {_entries_barrier_8_io_y_hx, _entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_lo_hi_1; // @[package.scala:45:27]
assign hr_array_hi_lo_hi_1 = _GEN_22; // @[package.scala:45:27]
wire [1:0] hx_array_hi_lo_hi; // @[package.scala:45:27]
assign hx_array_hi_lo_hi = _GEN_22; // @[package.scala:45:27]
wire [2:0] hr_array_hi_lo_1 = {hr_array_hi_lo_hi_1, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_23 = {_entries_barrier_10_io_y_hx, _entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_lo_1; // @[package.scala:45:27]
assign hr_array_hi_hi_lo_1 = _GEN_23; // @[package.scala:45:27]
wire [1:0] hx_array_hi_hi_lo; // @[package.scala:45:27]
assign hx_array_hi_hi_lo = _GEN_23; // @[package.scala:45:27]
wire [1:0] _GEN_24 = {_entries_barrier_12_io_y_hx, _entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_hi_1; // @[package.scala:45:27]
assign hr_array_hi_hi_hi_1 = _GEN_24; // @[package.scala:45:27]
wire [1:0] hx_array_hi_hi_hi; // @[package.scala:45:27]
assign hx_array_hi_hi_hi = _GEN_24; // @[package.scala:45:27]
wire [3:0] hr_array_hi_hi_1 = {hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] hr_array_hi_1 = {hr_array_hi_hi_1, hr_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27]
wire [1:0] hw_array_lo_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_lo_lo = {hw_array_lo_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_lo_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_lo_hi = {hw_array_lo_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [5:0] hw_array_lo = {hw_array_lo_hi, hw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] hw_array_hi_lo_hi = {_entries_barrier_8_io_y_hw, _entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_hi_lo = {hw_array_hi_lo_hi, _entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_hi_hi_lo = {_entries_barrier_10_io_y_hw, _entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_hi_hi_hi = {_entries_barrier_12_io_y_hw, _entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [3:0] hw_array_hi_hi = {hw_array_hi_hi_hi, hw_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hw_array_hi = {hw_array_hi_hi, hw_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27]
wire [2:0] hx_array_lo_lo = {hx_array_lo_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [2:0] hx_array_lo_hi = {hx_array_lo_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] hx_array_lo = {hx_array_lo_hi, hx_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] hx_array_hi_lo = {hx_array_hi_lo_hi, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [3:0] hx_array_hi_hi = {hx_array_hi_hi_hi, hx_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hx_array_hi = {hx_array_hi_hi, hx_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27]
wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26]
wire [1:0] pr_array_lo_lo_hi = {_entries_barrier_2_io_y_pr, _entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pr_array_lo_hi_hi = {_entries_barrier_5_io_y_pr, _entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pr_array_hi_lo_hi = {_entries_barrier_8_io_y_pr, _entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, _entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pr_array_hi_hi_hi = {_entries_barrier_11_io_y_pr, _entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, _entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27]
wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27]
wire [13:0] _GEN_25 = ptw_ae_array | final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104]
wire [13:0] _pr_array_T_3; // @[TLB.scala:529:104]
assign _pr_array_T_3 = _GEN_25; // @[TLB.scala:529:104]
wire [13:0] _pw_array_T_3; // @[TLB.scala:531:104]
assign _pw_array_T_3 = _GEN_25; // @[TLB.scala:529:104, :531:104]
wire [13:0] _px_array_T_3; // @[TLB.scala:533:104]
assign _px_array_T_3 = _GEN_25; // @[TLB.scala:529:104, :533:104]
wire [13:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}]
wire [13:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}]
wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26]
wire [1:0] pw_array_lo_lo_hi = {_entries_barrier_2_io_y_pw, _entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pw_array_lo_hi_hi = {_entries_barrier_5_io_y_pw, _entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pw_array_hi_lo_hi = {_entries_barrier_8_io_y_pw, _entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, _entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pw_array_hi_hi_hi = {_entries_barrier_11_io_y_pw, _entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, _entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27]
wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27]
wire [13:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}]
wire [13:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}]
wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26]
wire [1:0] px_array_lo_lo_hi = {_entries_barrier_2_io_y_px, _entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] px_array_lo_hi_hi = {_entries_barrier_5_io_y_px, _entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] px_array_hi_lo_hi = {_entries_barrier_8_io_y_px, _entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, _entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] px_array_hi_hi_hi = {_entries_barrier_11_io_y_px, _entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, _entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27]
wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27]
wire [13:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}]
wire [13:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}]
wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27]
wire [1:0] eff_array_lo_lo_hi = {_entries_barrier_2_io_y_eff, _entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] eff_array_lo_hi_hi = {_entries_barrier_5_io_y_eff, _entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] eff_array_hi_lo_hi = {_entries_barrier_8_io_y_eff, _entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, _entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] eff_array_hi_hi_hi = {_entries_barrier_11_io_y_eff, _entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, _entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27]
wire [13:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27]
wire [1:0] _GEN_26 = {_entries_barrier_2_io_y_c, _entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27]
assign c_array_lo_lo_hi = _GEN_26; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27]
assign prefetchable_array_lo_lo_hi = _GEN_26; // @[package.scala:45:27]
wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_27 = {_entries_barrier_5_io_y_c, _entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27]
assign c_array_lo_hi_hi = _GEN_27; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_lo_hi_hi = _GEN_27; // @[package.scala:45:27]
wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_28 = {_entries_barrier_8_io_y_c, _entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27]
assign c_array_hi_lo_hi = _GEN_28; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_lo_hi = _GEN_28; // @[package.scala:45:27]
wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_29 = {_entries_barrier_11_io_y_c, _entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27]
assign c_array_hi_hi_hi = _GEN_29; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_hi_hi = _GEN_29; // @[package.scala:45:27]
wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27]
wire [13:0] c_array = {2'h0, _c_array_T_1}; // @[package.scala:45:27]
wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27]
wire [1:0] ppp_array_lo_lo_hi = {_entries_barrier_2_io_y_ppp, _entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_lo_lo = {ppp_array_lo_lo_hi, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] ppp_array_lo_hi_hi = {_entries_barrier_5_io_y_ppp, _entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_lo_hi = {ppp_array_lo_hi_hi, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] ppp_array_lo = {ppp_array_lo_hi, ppp_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ppp_array_hi_lo_hi = {_entries_barrier_8_io_y_ppp, _entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_hi_lo = {ppp_array_hi_lo_hi, _entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] ppp_array_hi_hi_hi = {_entries_barrier_11_io_y_ppp, _entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_hi_hi = {ppp_array_hi_hi_hi, _entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] ppp_array_hi = {ppp_array_hi_hi, ppp_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27]
wire [13:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27]
wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27]
wire [1:0] paa_array_lo_lo_hi = {_entries_barrier_2_io_y_paa, _entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] paa_array_lo_hi_hi = {_entries_barrier_5_io_y_paa, _entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] paa_array_hi_lo_hi = {_entries_barrier_8_io_y_paa, _entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, _entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] paa_array_hi_hi_hi = {_entries_barrier_11_io_y_paa, _entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, _entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27]
wire [13:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27]
wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27]
wire [1:0] pal_array_lo_lo_hi = {_entries_barrier_2_io_y_pal, _entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pal_array_lo_hi_hi = {_entries_barrier_5_io_y_pal, _entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pal_array_hi_lo_hi = {_entries_barrier_8_io_y_pal, _entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, _entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pal_array_hi_hi_hi = {_entries_barrier_11_io_y_pal, _entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, _entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27]
wire [13:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27]
wire [13:0] ppp_array_if_cached = ppp_array | c_array; // @[TLB.scala:537:20, :539:22, :544:39]
wire [13:0] paa_array_if_cached = paa_array | c_array; // @[TLB.scala:537:20, :541:22, :545:39]
wire [13:0] pal_array_if_cached = pal_array | c_array; // @[TLB.scala:537:20, :543:22, :546:39]
wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27]
wire [13:0] prefetchable_array = {2'h0, _prefetchable_array_T_2}; // @[package.scala:45:27]
wire [3:0] _misaligned_T = 4'h1 << io_req_bits_size_0; // @[OneHot.scala:58:35]
wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35]
wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[TLB.scala:550:69]
wire [33:0] _misaligned_T_3 = {30'h0, io_req_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[TLB.scala:318:7, :320:14, :550:{39,69}]
wire misaligned = |_misaligned_T_3; // @[TLB.scala:550:{39,77}]
wire _GEN_30 = io_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47]
wire _cmd_lrsc_T; // @[package.scala:16:47]
assign _cmd_lrsc_T = _GEN_30; // @[package.scala:16:47]
wire _cmd_read_T_2; // @[package.scala:16:47]
assign _cmd_read_T_2 = _GEN_30; // @[package.scala:16:47]
wire _GEN_31 = io_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47]
wire _cmd_lrsc_T_1; // @[package.scala:16:47]
assign _cmd_lrsc_T_1 = _GEN_31; // @[package.scala:16:47]
wire _cmd_read_T_3; // @[package.scala:16:47]
assign _cmd_read_T_3 = _GEN_31; // @[package.scala:16:47]
wire _cmd_write_T_3; // @[Consts.scala:90:66]
assign _cmd_write_T_3 = _GEN_31; // @[package.scala:16:47]
wire _cmd_lrsc_T_2 = _cmd_lrsc_T | _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59]
wire cmd_lrsc = _cmd_lrsc_T_2; // @[package.scala:81:59]
wire _GEN_32 = io_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _cmd_amo_logical_T; // @[package.scala:16:47]
assign _cmd_amo_logical_T = _GEN_32; // @[package.scala:16:47]
wire _cmd_read_T_7; // @[package.scala:16:47]
assign _cmd_read_T_7 = _GEN_32; // @[package.scala:16:47]
wire _cmd_write_T_5; // @[package.scala:16:47]
assign _cmd_write_T_5 = _GEN_32; // @[package.scala:16:47]
wire _GEN_33 = io_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _cmd_amo_logical_T_1; // @[package.scala:16:47]
assign _cmd_amo_logical_T_1 = _GEN_33; // @[package.scala:16:47]
wire _cmd_read_T_8; // @[package.scala:16:47]
assign _cmd_read_T_8 = _GEN_33; // @[package.scala:16:47]
wire _cmd_write_T_6; // @[package.scala:16:47]
assign _cmd_write_T_6 = _GEN_33; // @[package.scala:16:47]
wire _GEN_34 = io_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _cmd_amo_logical_T_2; // @[package.scala:16:47]
assign _cmd_amo_logical_T_2 = _GEN_34; // @[package.scala:16:47]
wire _cmd_read_T_9; // @[package.scala:16:47]
assign _cmd_read_T_9 = _GEN_34; // @[package.scala:16:47]
wire _cmd_write_T_7; // @[package.scala:16:47]
assign _cmd_write_T_7 = _GEN_34; // @[package.scala:16:47]
wire _GEN_35 = io_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _cmd_amo_logical_T_3; // @[package.scala:16:47]
assign _cmd_amo_logical_T_3 = _GEN_35; // @[package.scala:16:47]
wire _cmd_read_T_10; // @[package.scala:16:47]
assign _cmd_read_T_10 = _GEN_35; // @[package.scala:16:47]
wire _cmd_write_T_8; // @[package.scala:16:47]
assign _cmd_write_T_8 = _GEN_35; // @[package.scala:16:47]
wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T | _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 | _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 | _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59]
wire cmd_amo_logical = _cmd_amo_logical_T_6; // @[package.scala:81:59]
wire _GEN_36 = io_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T = _GEN_36; // @[package.scala:16:47]
wire _cmd_read_T_14; // @[package.scala:16:47]
assign _cmd_read_T_14 = _GEN_36; // @[package.scala:16:47]
wire _cmd_write_T_12; // @[package.scala:16:47]
assign _cmd_write_T_12 = _GEN_36; // @[package.scala:16:47]
wire _GEN_37 = io_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_1 = _GEN_37; // @[package.scala:16:47]
wire _cmd_read_T_15; // @[package.scala:16:47]
assign _cmd_read_T_15 = _GEN_37; // @[package.scala:16:47]
wire _cmd_write_T_13; // @[package.scala:16:47]
assign _cmd_write_T_13 = _GEN_37; // @[package.scala:16:47]
wire _GEN_38 = io_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_2 = _GEN_38; // @[package.scala:16:47]
wire _cmd_read_T_16; // @[package.scala:16:47]
assign _cmd_read_T_16 = _GEN_38; // @[package.scala:16:47]
wire _cmd_write_T_14; // @[package.scala:16:47]
assign _cmd_write_T_14 = _GEN_38; // @[package.scala:16:47]
wire _GEN_39 = io_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_3 = _GEN_39; // @[package.scala:16:47]
wire _cmd_read_T_17; // @[package.scala:16:47]
assign _cmd_read_T_17 = _GEN_39; // @[package.scala:16:47]
wire _cmd_write_T_15; // @[package.scala:16:47]
assign _cmd_write_T_15 = _GEN_39; // @[package.scala:16:47]
wire _GEN_40 = io_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_4 = _GEN_40; // @[package.scala:16:47]
wire _cmd_read_T_18; // @[package.scala:16:47]
assign _cmd_read_T_18 = _GEN_40; // @[package.scala:16:47]
wire _cmd_write_T_16; // @[package.scala:16:47]
assign _cmd_write_T_16 = _GEN_40; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T | _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 | _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 | _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 | _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59]
wire cmd_amo_arithmetic = _cmd_amo_arithmetic_T_8; // @[package.scala:81:59]
wire _GEN_41 = io_req_bits_cmd_0 == 5'h11; // @[TLB.scala:318:7, :573:41]
wire cmd_put_partial; // @[TLB.scala:573:41]
assign cmd_put_partial = _GEN_41; // @[TLB.scala:573:41]
wire _cmd_write_T_1; // @[Consts.scala:90:49]
assign _cmd_write_T_1 = _GEN_41; // @[TLB.scala:573:41]
wire _cmd_read_T = io_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47]
wire _GEN_42 = io_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47]
wire _cmd_read_T_1; // @[package.scala:16:47]
assign _cmd_read_T_1 = _GEN_42; // @[package.scala:16:47]
wire _cmd_readx_T; // @[TLB.scala:575:56]
assign _cmd_readx_T = _GEN_42; // @[package.scala:16:47]
wire _cmd_read_T_4 = _cmd_read_T | _cmd_read_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_5 = _cmd_read_T_4 | _cmd_read_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_6 = _cmd_read_T_5 | _cmd_read_T_3; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_11 = _cmd_read_T_7 | _cmd_read_T_8; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_12 = _cmd_read_T_11 | _cmd_read_T_9; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_13 = _cmd_read_T_12 | _cmd_read_T_10; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_19 = _cmd_read_T_14 | _cmd_read_T_15; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_20 = _cmd_read_T_19 | _cmd_read_T_16; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_21 = _cmd_read_T_20 | _cmd_read_T_17; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_22 = _cmd_read_T_21 | _cmd_read_T_18; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_23 = _cmd_read_T_13 | _cmd_read_T_22; // @[package.scala:81:59]
wire cmd_read = _cmd_read_T_6 | _cmd_read_T_23; // @[package.scala:81:59]
wire _cmd_write_T = io_req_bits_cmd_0 == 5'h1; // @[TLB.scala:318:7]
wire _cmd_write_T_2 = _cmd_write_T | _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}]
wire _cmd_write_T_4 = _cmd_write_T_2 | _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}]
wire _cmd_write_T_9 = _cmd_write_T_5 | _cmd_write_T_6; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_10 = _cmd_write_T_9 | _cmd_write_T_7; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_11 = _cmd_write_T_10 | _cmd_write_T_8; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_17 = _cmd_write_T_12 | _cmd_write_T_13; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_18 = _cmd_write_T_17 | _cmd_write_T_14; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_19 = _cmd_write_T_18 | _cmd_write_T_15; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_20 = _cmd_write_T_19 | _cmd_write_T_16; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_21 = _cmd_write_T_11 | _cmd_write_T_20; // @[package.scala:81:59]
wire cmd_write = _cmd_write_T_4 | _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _cmd_write_perms_T = io_req_bits_cmd_0 == 5'h5; // @[package.scala:16:47]
wire _cmd_write_perms_T_1 = io_req_bits_cmd_0 == 5'h17; // @[package.scala:16:47]
wire _cmd_write_perms_T_2 = _cmd_write_perms_T | _cmd_write_perms_T_1; // @[package.scala:16:47, :81:59]
wire cmd_write_perms = cmd_write | _cmd_write_perms_T_2; // @[package.scala:81:59]
wire [13:0] _ae_array_T = misaligned ? eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8]
wire [13:0] _GEN_43 = {14{cmd_lrsc}}; // @[TLB.scala:570:33, :583:8]
wire [13:0] _ae_array_T_2; // @[TLB.scala:583:8]
assign _ae_array_T_2 = _GEN_43; // @[TLB.scala:583:8]
wire [13:0] _must_alloc_array_T_9; // @[TLB.scala:596:8]
assign _must_alloc_array_T_9 = _GEN_43; // @[TLB.scala:583:8, :596:8]
wire [13:0] ae_array = _ae_array_T | _ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8]
wire [13:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46]
wire [13:0] _ae_ld_array_T_1 = ae_array | _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}]
wire [13:0] ae_ld_array = cmd_read ? _ae_ld_array_T_1 : 14'h0; // @[TLB.scala:586:{24,44}]
wire [13:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37]
wire [13:0] _ae_st_array_T_1 = ae_array | _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}]
wire [13:0] _ae_st_array_T_2 = cmd_write_perms ? _ae_st_array_T_1 : 14'h0; // @[TLB.scala:577:35, :588:{8,35}]
wire [13:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26]
wire [13:0] _ae_st_array_T_4 = cmd_put_partial ? _ae_st_array_T_3 : 14'h0; // @[TLB.scala:573:41, :589:{8,26}]
wire [13:0] _ae_st_array_T_5 = _ae_st_array_T_2 | _ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8]
wire [13:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26]
wire [13:0] _ae_st_array_T_7 = cmd_amo_logical ? _ae_st_array_T_6 : 14'h0; // @[TLB.scala:571:40, :590:{8,26}]
wire [13:0] _ae_st_array_T_8 = _ae_st_array_T_5 | _ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8]
wire [13:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29]
wire [13:0] _ae_st_array_T_10 = cmd_amo_arithmetic ? _ae_st_array_T_9 : 14'h0; // @[TLB.scala:572:43, :591:{8,29}]
wire [13:0] ae_st_array = _ae_st_array_T_8 | _ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8]
wire [13:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26]
wire [13:0] _must_alloc_array_T_1 = cmd_put_partial ? _must_alloc_array_T : 14'h0; // @[TLB.scala:573:41, :593:{8,26}]
wire [13:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26]
wire [13:0] _must_alloc_array_T_3 = cmd_amo_logical ? _must_alloc_array_T_2 : 14'h0; // @[TLB.scala:571:40, :594:{8,26}]
wire [13:0] _must_alloc_array_T_4 = _must_alloc_array_T_1 | _must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8]
wire [13:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29]
wire [13:0] _must_alloc_array_T_6 = cmd_amo_arithmetic ? _must_alloc_array_T_5 : 14'h0; // @[TLB.scala:572:43, :595:{8,29}]
wire [13:0] _must_alloc_array_T_7 = _must_alloc_array_T_4 | _must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8]
wire [13:0] must_alloc_array = _must_alloc_array_T_7 | _must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8]
wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}]
wire [13:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73]
wire [13:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}]
wire [13:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 | ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}]
wire [13:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106]
wire [13:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}]
wire [13:0] pf_ld_array = cmd_read ? _pf_ld_array_T_6 : 14'h0; // @[TLB.scala:597:{24,104}]
wire [13:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44]
wire [13:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55]
wire [13:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}]
wire [13:0] _pf_st_array_T_3 = _pf_st_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}]
wire [13:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88]
wire [13:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}]
wire [13:0] pf_st_array = cmd_write_perms ? _pf_st_array_T_5 : 14'h0; // @[TLB.scala:577:35, :598:{24,86}]
wire [13:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25]
wire [13:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36]
wire [13:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}]
wire [13:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}]
wire [13:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69]
wire [13:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}]
wire [13:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100]
wire [13:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}]
wire [13:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81]
wire [13:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}]
wire [13:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64]
wire [13:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}]
wire _gpa_hits_hit_mask_T = vpn == 21'h0; // @[TLB.scala:335:30, :339:29, :606:73]
wire [11:0] _gpa_hits_hit_mask_T_2 = {12{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}]
wire [1:0] lo_lo = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45]
wire [1:0] lo_hi = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45]
wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:21:45]
wire [3:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18]
wire [1:0] hi_lo = {sector_hits_5, sector_hits_4}; // @[OneHot.scala:21:45]
wire [1:0] hi_hi = {sector_hits_7, sector_hits_6}; // @[OneHot.scala:21:45]
wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:21:45]
wire [3:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18]
wire [3:0] _T_33 = hi_1 | lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28]
wire [2:0] state_vec_0_touch_way_sized = {|hi_1, |hi_2, hi_2[1] | lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_vec_0_set_left_older_T = state_vec_0_touch_way_sized[2]; // @[package.scala:163:13]
wire state_vec_0_set_left_older = ~_state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire [1:0] _state_vec_0_T = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13]
wire [1:0] _state_vec_0_T_11 = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13]
wire _state_vec_0_set_left_older_T_1 = _state_vec_0_T[1]; // @[package.scala:163:13]
wire state_vec_0_set_left_older_1 = ~_state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}]
wire _state_vec_0_T_1 = _state_vec_0_T[0]; // @[package.scala:163:13]
wire _state_vec_0_T_5 = _state_vec_0_T[0]; // @[package.scala:163:13]
wire _state_vec_0_T_2 = _state_vec_0_T_1; // @[package.scala:163:13]
wire _state_vec_0_T_3 = ~_state_vec_0_T_2; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_4 = ~state_vec_0_set_left_older_1 & _state_vec_0_T_3; // @[Replacement.scala:196:33, :203:16, :218:7]
wire _state_vec_0_T_6 = _state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17]
wire _state_vec_0_T_7 = ~_state_vec_0_T_6; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_8 = state_vec_0_set_left_older_1 & _state_vec_0_T_7; // @[Replacement.scala:196:33, :206:16, :218:7]
wire [1:0] state_vec_0_hi = {state_vec_0_set_left_older_1, _state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_vec_0_T_9 = {state_vec_0_hi, _state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_vec_0_T_10 = state_vec_0_set_left_older ? 3'h0 : _state_vec_0_T_9; // @[Replacement.scala:196:33, :202:12, :203:16]
wire _state_vec_0_set_left_older_T_2 = _state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62]
wire state_vec_0_set_left_older_2 = ~_state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}]
wire _state_vec_0_T_12 = _state_vec_0_T_11[0]; // @[package.scala:163:13]
wire _state_vec_0_T_16 = _state_vec_0_T_11[0]; // @[package.scala:163:13]
wire _state_vec_0_T_13 = _state_vec_0_T_12; // @[package.scala:163:13]
wire _state_vec_0_T_14 = ~_state_vec_0_T_13; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_15 = ~state_vec_0_set_left_older_2 & _state_vec_0_T_14; // @[Replacement.scala:196:33, :203:16, :218:7]
wire _state_vec_0_T_17 = _state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17]
wire _state_vec_0_T_18 = ~_state_vec_0_T_17; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_19 = state_vec_0_set_left_older_2 & _state_vec_0_T_18; // @[Replacement.scala:196:33, :206:16, :218:7]
wire [1:0] state_vec_0_hi_1 = {state_vec_0_set_left_older_2, _state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_vec_0_T_20 = {state_vec_0_hi_1, _state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_vec_0_T_21 = state_vec_0_set_left_older ? _state_vec_0_T_20 : 3'h0; // @[Replacement.scala:196:33, :202:12, :206:16]
wire [3:0] state_vec_0_hi_2 = {state_vec_0_set_left_older, _state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_vec_0_T_22 = {state_vec_0_hi_2, _state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16]
wire [1:0] lo_3 = {superpage_hits_1, superpage_hits_0}; // @[OneHot.scala:21:45]
wire [1:0] lo_4 = lo_3; // @[OneHot.scala:21:45, :31:18]
wire [1:0] hi_3 = {superpage_hits_3, superpage_hits_2}; // @[OneHot.scala:21:45]
wire [1:0] hi_4 = hi_3; // @[OneHot.scala:21:45, :30:18]
wire [1:0] state_reg_touch_way_sized = {|hi_4, hi_4[1] | lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_reg_set_left_older_T = state_reg_touch_way_sized[1]; // @[package.scala:163:13]
wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire _state_reg_T = state_reg_touch_way_sized[0]; // @[package.scala:163:13]
wire _state_reg_T_4 = state_reg_touch_way_sized[0]; // @[package.scala:163:13]
wire _state_reg_T_1 = _state_reg_T; // @[package.scala:163:13]
wire _state_reg_T_2 = ~_state_reg_T_1; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_3 = ~state_reg_set_left_older & _state_reg_T_2; // @[Replacement.scala:196:33, :203:16, :218:7]
wire _state_reg_T_5 = _state_reg_T_4; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_6 = ~_state_reg_T_5; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_7 = state_reg_set_left_older & _state_reg_T_6; // @[Replacement.scala:196:33, :206:16, :218:7]
wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_8 = {state_reg_hi, _state_reg_T_7}; // @[Replacement.scala:202:12, :206:16]
wire [13:0] _io_resp_pf_ld_T_1 = pf_ld_array & 14'h2000; // @[TLB.scala:442:17, :597:24, :633:57]
wire _io_resp_pf_ld_T_2 = |_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}]
assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T_2; // @[TLB.scala:633:{41,65}]
assign io_resp_pf_ld_0 = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41]
wire [13:0] _io_resp_pf_st_T_1 = pf_st_array & 14'h2000; // @[TLB.scala:442:17, :598:24, :634:64]
wire _io_resp_pf_st_T_2 = |_io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}]
assign _io_resp_pf_st_T_3 = _io_resp_pf_st_T_2; // @[TLB.scala:634:{48,72}]
assign io_resp_pf_st_0 = _io_resp_pf_st_T_3; // @[TLB.scala:318:7, :634:48]
wire [13:0] _io_resp_pf_inst_T = pf_inst_array & 14'h2000; // @[TLB.scala:442:17, :599:67, :635:47]
wire _io_resp_pf_inst_T_1 = |_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}]
assign _io_resp_pf_inst_T_2 = _io_resp_pf_inst_T_1; // @[TLB.scala:635:{29,55}]
assign io_resp_pf_inst_0 = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29]
wire [13:0] _io_resp_ae_ld_T = ae_ld_array & 14'h2000; // @[TLB.scala:442:17, :586:24, :641:33]
assign _io_resp_ae_ld_T_1 = |_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}]
assign io_resp_ae_ld_0 = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41]
wire [13:0] _io_resp_ae_st_T = ae_st_array & 14'h2000; // @[TLB.scala:442:17, :590:53, :642:33]
assign _io_resp_ae_st_T_1 = |_io_resp_ae_st_T; // @[TLB.scala:642:{33,41}]
assign io_resp_ae_st_0 = _io_resp_ae_st_T_1; // @[TLB.scala:318:7, :642:41]
wire [13:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23]
wire [13:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & 14'h2000; // @[TLB.scala:442:17, :643:{23,33}]
assign _io_resp_ae_inst_T_2 = |_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}]
assign io_resp_ae_inst_0 = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41]
assign _io_resp_ma_ld_T = misaligned & cmd_read; // @[TLB.scala:550:77, :645:31]
assign io_resp_ma_ld_0 = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31]
assign _io_resp_ma_st_T = misaligned & cmd_write; // @[TLB.scala:550:77, :646:31]
assign io_resp_ma_st_0 = _io_resp_ma_st_T; // @[TLB.scala:318:7, :646:31]
wire [13:0] _io_resp_cacheable_T = c_array & 14'h2000; // @[TLB.scala:442:17, :537:20, :648:33]
assign _io_resp_cacheable_T_1 = |_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}]
assign io_resp_cacheable_0 = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41]
wire [13:0] _io_resp_must_alloc_T = must_alloc_array & 14'h2000; // @[TLB.scala:442:17, :595:46, :649:43]
assign _io_resp_must_alloc_T_1 = |_io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}]
assign io_resp_must_alloc_0 = _io_resp_must_alloc_T_1; // @[TLB.scala:318:7, :649:51]
wire [13:0] _io_resp_prefetchable_T = prefetchable_array & 14'h2000; // @[TLB.scala:442:17, :547:31, :650:47]
wire _io_resp_prefetchable_T_1 = |_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}]
assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}]
assign io_resp_prefetchable_0 = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59]
assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73]
assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23]
wire [21:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36]
wire [21:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}]
wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}]
assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8]
assign io_resp_gpa_0 = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8]
OptimizationBarrier_TLBEntryData mpu_ppn_barrier ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_mpu_ppn_WIRE_ppn), // @[TLB.scala:170:77]
.io_x_u (_mpu_ppn_WIRE_u), // @[TLB.scala:170:77]
.io_x_g (_mpu_ppn_WIRE_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_mpu_ppn_WIRE_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_mpu_ppn_WIRE_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_mpu_ppn_WIRE_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_mpu_ppn_WIRE_pf), // @[TLB.scala:170:77]
.io_x_gf (_mpu_ppn_WIRE_gf), // @[TLB.scala:170:77]
.io_x_sw (_mpu_ppn_WIRE_sw), // @[TLB.scala:170:77]
.io_x_sx (_mpu_ppn_WIRE_sx), // @[TLB.scala:170:77]
.io_x_sr (_mpu_ppn_WIRE_sr), // @[TLB.scala:170:77]
.io_x_hw (_mpu_ppn_WIRE_hw), // @[TLB.scala:170:77]
.io_x_hx (_mpu_ppn_WIRE_hx), // @[TLB.scala:170:77]
.io_x_hr (_mpu_ppn_WIRE_hr), // @[TLB.scala:170:77]
.io_x_pw (_mpu_ppn_WIRE_pw), // @[TLB.scala:170:77]
.io_x_px (_mpu_ppn_WIRE_px), // @[TLB.scala:170:77]
.io_x_pr (_mpu_ppn_WIRE_pr), // @[TLB.scala:170:77]
.io_x_ppp (_mpu_ppn_WIRE_ppp), // @[TLB.scala:170:77]
.io_x_pal (_mpu_ppn_WIRE_pal), // @[TLB.scala:170:77]
.io_x_paa (_mpu_ppn_WIRE_paa), // @[TLB.scala:170:77]
.io_x_eff (_mpu_ppn_WIRE_eff), // @[TLB.scala:170:77]
.io_x_c (_mpu_ppn_WIRE_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_mpu_ppn_WIRE_fragmented_superpage) // @[TLB.scala:170:77]
); // @[package.scala:267:25]
PMPChecker_s3 pmp ( // @[TLB.scala:416:19]
.clock (clock),
.reset (reset),
.io_prv (mpu_priv[1:0]), // @[TLB.scala:415:27, :420:14]
.io_pmp_0_cfg_l (io_ptw_pmp_0_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_0_cfg_a (io_ptw_pmp_0_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_0_cfg_x (io_ptw_pmp_0_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_0_cfg_w (io_ptw_pmp_0_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_0_cfg_r (io_ptw_pmp_0_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_0_addr (io_ptw_pmp_0_addr_0), // @[TLB.scala:318:7]
.io_pmp_0_mask (io_ptw_pmp_0_mask_0), // @[TLB.scala:318:7]
.io_pmp_1_cfg_l (io_ptw_pmp_1_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_1_cfg_a (io_ptw_pmp_1_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_1_cfg_x (io_ptw_pmp_1_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_1_cfg_w (io_ptw_pmp_1_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_1_cfg_r (io_ptw_pmp_1_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_1_addr (io_ptw_pmp_1_addr_0), // @[TLB.scala:318:7]
.io_pmp_1_mask (io_ptw_pmp_1_mask_0), // @[TLB.scala:318:7]
.io_pmp_2_cfg_l (io_ptw_pmp_2_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_2_cfg_a (io_ptw_pmp_2_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_2_cfg_x (io_ptw_pmp_2_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_2_cfg_w (io_ptw_pmp_2_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_2_cfg_r (io_ptw_pmp_2_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_2_addr (io_ptw_pmp_2_addr_0), // @[TLB.scala:318:7]
.io_pmp_2_mask (io_ptw_pmp_2_mask_0), // @[TLB.scala:318:7]
.io_pmp_3_cfg_l (io_ptw_pmp_3_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_3_cfg_a (io_ptw_pmp_3_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_3_cfg_x (io_ptw_pmp_3_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_3_cfg_w (io_ptw_pmp_3_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_3_cfg_r (io_ptw_pmp_3_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_3_addr (io_ptw_pmp_3_addr_0), // @[TLB.scala:318:7]
.io_pmp_3_mask (io_ptw_pmp_3_mask_0), // @[TLB.scala:318:7]
.io_pmp_4_cfg_l (io_ptw_pmp_4_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_4_cfg_a (io_ptw_pmp_4_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_4_cfg_x (io_ptw_pmp_4_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_4_cfg_w (io_ptw_pmp_4_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_4_cfg_r (io_ptw_pmp_4_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_4_addr (io_ptw_pmp_4_addr_0), // @[TLB.scala:318:7]
.io_pmp_4_mask (io_ptw_pmp_4_mask_0), // @[TLB.scala:318:7]
.io_pmp_5_cfg_l (io_ptw_pmp_5_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_5_cfg_a (io_ptw_pmp_5_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_5_cfg_x (io_ptw_pmp_5_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_5_cfg_w (io_ptw_pmp_5_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_5_cfg_r (io_ptw_pmp_5_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_5_addr (io_ptw_pmp_5_addr_0), // @[TLB.scala:318:7]
.io_pmp_5_mask (io_ptw_pmp_5_mask_0), // @[TLB.scala:318:7]
.io_pmp_6_cfg_l (io_ptw_pmp_6_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_6_cfg_a (io_ptw_pmp_6_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_6_cfg_x (io_ptw_pmp_6_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_6_cfg_w (io_ptw_pmp_6_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_6_cfg_r (io_ptw_pmp_6_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_6_addr (io_ptw_pmp_6_addr_0), // @[TLB.scala:318:7]
.io_pmp_6_mask (io_ptw_pmp_6_mask_0), // @[TLB.scala:318:7]
.io_pmp_7_cfg_l (io_ptw_pmp_7_cfg_l_0), // @[TLB.scala:318:7]
.io_pmp_7_cfg_a (io_ptw_pmp_7_cfg_a_0), // @[TLB.scala:318:7]
.io_pmp_7_cfg_x (io_ptw_pmp_7_cfg_x_0), // @[TLB.scala:318:7]
.io_pmp_7_cfg_w (io_ptw_pmp_7_cfg_w_0), // @[TLB.scala:318:7]
.io_pmp_7_cfg_r (io_ptw_pmp_7_cfg_r_0), // @[TLB.scala:318:7]
.io_pmp_7_addr (io_ptw_pmp_7_addr_0), // @[TLB.scala:318:7]
.io_pmp_7_mask (io_ptw_pmp_7_mask_0), // @[TLB.scala:318:7]
.io_addr (mpu_physaddr[31:0]), // @[TLB.scala:414:25, :417:15]
.io_size (io_req_bits_size_0), // @[TLB.scala:318:7]
.io_r (_pmp_io_r),
.io_w (_pmp_io_w),
.io_x (_pmp_io_x)
); // @[TLB.scala:416:19]
PMAChecker pma ( // @[TLB.scala:422:19]
.clock (clock),
.reset (reset),
.io_paddr (mpu_physaddr), // @[TLB.scala:414:25]
.io_resp_r (_pma_io_resp_r),
.io_resp_w (_pma_io_resp_w),
.io_resp_pp (_pma_io_resp_pp),
.io_resp_al (_pma_io_resp_al),
.io_resp_aa (_pma_io_resp_aa),
.io_resp_x (_pma_io_resp_x),
.io_resp_eff (_pma_io_resp_eff)
); // @[TLB.scala:422:19]
assign newEntry_ppp = _pma_io_resp_pp; // @[TLB.scala:422:19, :449:24]
assign newEntry_pal = _pma_io_resp_al; // @[TLB.scala:422:19, :449:24]
assign newEntry_paa = _pma_io_resp_aa; // @[TLB.scala:422:19, :449:24]
assign newEntry_eff = _pma_io_resp_eff; // @[TLB.scala:422:19, :449:24]
OptimizationBarrier_TLBEntryData_1 entries_barrier ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_io_y_u),
.io_y_ae_ptw (_entries_barrier_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_io_y_ae_stage2),
.io_y_pf (_entries_barrier_io_y_pf),
.io_y_gf (_entries_barrier_io_y_gf),
.io_y_sw (_entries_barrier_io_y_sw),
.io_y_sx (_entries_barrier_io_y_sx),
.io_y_sr (_entries_barrier_io_y_sr),
.io_y_hw (_entries_barrier_io_y_hw),
.io_y_hx (_entries_barrier_io_y_hx),
.io_y_hr (_entries_barrier_io_y_hr),
.io_y_pw (_entries_barrier_io_y_pw),
.io_y_px (_entries_barrier_io_y_px),
.io_y_pr (_entries_barrier_io_y_pr),
.io_y_ppp (_entries_barrier_io_y_ppp),
.io_y_pal (_entries_barrier_io_y_pal),
.io_y_paa (_entries_barrier_io_y_paa),
.io_y_eff (_entries_barrier_io_y_eff),
.io_y_c (_entries_barrier_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_2 entries_barrier_1 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_2_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_2_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_2_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_2_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_2_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_2_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_2_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_2_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_2_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_2_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_2_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_2_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_2_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_2_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_2_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_2_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_2_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_2_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_2_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_2_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_2_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_2_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_2_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_1_io_y_u),
.io_y_ae_ptw (_entries_barrier_1_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_1_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_1_io_y_ae_stage2),
.io_y_pf (_entries_barrier_1_io_y_pf),
.io_y_gf (_entries_barrier_1_io_y_gf),
.io_y_sw (_entries_barrier_1_io_y_sw),
.io_y_sx (_entries_barrier_1_io_y_sx),
.io_y_sr (_entries_barrier_1_io_y_sr),
.io_y_hw (_entries_barrier_1_io_y_hw),
.io_y_hx (_entries_barrier_1_io_y_hx),
.io_y_hr (_entries_barrier_1_io_y_hr),
.io_y_pw (_entries_barrier_1_io_y_pw),
.io_y_px (_entries_barrier_1_io_y_px),
.io_y_pr (_entries_barrier_1_io_y_pr),
.io_y_ppp (_entries_barrier_1_io_y_ppp),
.io_y_pal (_entries_barrier_1_io_y_pal),
.io_y_paa (_entries_barrier_1_io_y_paa),
.io_y_eff (_entries_barrier_1_io_y_eff),
.io_y_c (_entries_barrier_1_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_3 entries_barrier_2 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_4_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_4_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_4_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_4_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_4_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_4_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_4_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_4_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_4_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_4_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_4_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_4_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_4_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_4_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_4_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_4_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_4_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_4_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_4_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_4_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_4_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_4_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_4_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_2_io_y_u),
.io_y_ae_ptw (_entries_barrier_2_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_2_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_2_io_y_ae_stage2),
.io_y_pf (_entries_barrier_2_io_y_pf),
.io_y_gf (_entries_barrier_2_io_y_gf),
.io_y_sw (_entries_barrier_2_io_y_sw),
.io_y_sx (_entries_barrier_2_io_y_sx),
.io_y_sr (_entries_barrier_2_io_y_sr),
.io_y_hw (_entries_barrier_2_io_y_hw),
.io_y_hx (_entries_barrier_2_io_y_hx),
.io_y_hr (_entries_barrier_2_io_y_hr),
.io_y_pw (_entries_barrier_2_io_y_pw),
.io_y_px (_entries_barrier_2_io_y_px),
.io_y_pr (_entries_barrier_2_io_y_pr),
.io_y_ppp (_entries_barrier_2_io_y_ppp),
.io_y_pal (_entries_barrier_2_io_y_pal),
.io_y_paa (_entries_barrier_2_io_y_paa),
.io_y_eff (_entries_barrier_2_io_y_eff),
.io_y_c (_entries_barrier_2_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_4 entries_barrier_3 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_6_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_6_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_6_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_6_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_6_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_6_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_6_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_6_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_6_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_6_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_6_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_6_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_6_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_6_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_6_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_6_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_6_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_6_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_6_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_6_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_6_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_6_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_6_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_3_io_y_u),
.io_y_ae_ptw (_entries_barrier_3_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_3_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_3_io_y_ae_stage2),
.io_y_pf (_entries_barrier_3_io_y_pf),
.io_y_gf (_entries_barrier_3_io_y_gf),
.io_y_sw (_entries_barrier_3_io_y_sw),
.io_y_sx (_entries_barrier_3_io_y_sx),
.io_y_sr (_entries_barrier_3_io_y_sr),
.io_y_hw (_entries_barrier_3_io_y_hw),
.io_y_hx (_entries_barrier_3_io_y_hx),
.io_y_hr (_entries_barrier_3_io_y_hr),
.io_y_pw (_entries_barrier_3_io_y_pw),
.io_y_px (_entries_barrier_3_io_y_px),
.io_y_pr (_entries_barrier_3_io_y_pr),
.io_y_ppp (_entries_barrier_3_io_y_ppp),
.io_y_pal (_entries_barrier_3_io_y_pal),
.io_y_paa (_entries_barrier_3_io_y_paa),
.io_y_eff (_entries_barrier_3_io_y_eff),
.io_y_c (_entries_barrier_3_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_5 entries_barrier_4 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_8_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_8_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_8_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_8_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_8_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_8_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_8_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_8_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_8_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_8_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_8_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_8_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_8_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_8_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_8_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_8_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_8_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_8_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_8_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_8_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_8_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_8_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_8_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_4_io_y_u),
.io_y_ae_ptw (_entries_barrier_4_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_4_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_4_io_y_ae_stage2),
.io_y_pf (_entries_barrier_4_io_y_pf),
.io_y_gf (_entries_barrier_4_io_y_gf),
.io_y_sw (_entries_barrier_4_io_y_sw),
.io_y_sx (_entries_barrier_4_io_y_sx),
.io_y_sr (_entries_barrier_4_io_y_sr),
.io_y_hw (_entries_barrier_4_io_y_hw),
.io_y_hx (_entries_barrier_4_io_y_hx),
.io_y_hr (_entries_barrier_4_io_y_hr),
.io_y_pw (_entries_barrier_4_io_y_pw),
.io_y_px (_entries_barrier_4_io_y_px),
.io_y_pr (_entries_barrier_4_io_y_pr),
.io_y_ppp (_entries_barrier_4_io_y_ppp),
.io_y_pal (_entries_barrier_4_io_y_pal),
.io_y_paa (_entries_barrier_4_io_y_paa),
.io_y_eff (_entries_barrier_4_io_y_eff),
.io_y_c (_entries_barrier_4_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_6 entries_barrier_5 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_10_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_10_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_10_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_10_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_10_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_10_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_10_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_10_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_10_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_10_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_10_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_10_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_10_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_10_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_10_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_10_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_10_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_10_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_10_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_10_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_10_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_10_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_10_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_5_io_y_u),
.io_y_ae_ptw (_entries_barrier_5_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_5_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_5_io_y_ae_stage2),
.io_y_pf (_entries_barrier_5_io_y_pf),
.io_y_gf (_entries_barrier_5_io_y_gf),
.io_y_sw (_entries_barrier_5_io_y_sw),
.io_y_sx (_entries_barrier_5_io_y_sx),
.io_y_sr (_entries_barrier_5_io_y_sr),
.io_y_hw (_entries_barrier_5_io_y_hw),
.io_y_hx (_entries_barrier_5_io_y_hx),
.io_y_hr (_entries_barrier_5_io_y_hr),
.io_y_pw (_entries_barrier_5_io_y_pw),
.io_y_px (_entries_barrier_5_io_y_px),
.io_y_pr (_entries_barrier_5_io_y_pr),
.io_y_ppp (_entries_barrier_5_io_y_ppp),
.io_y_pal (_entries_barrier_5_io_y_pal),
.io_y_paa (_entries_barrier_5_io_y_paa),
.io_y_eff (_entries_barrier_5_io_y_eff),
.io_y_c (_entries_barrier_5_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_7 entries_barrier_6 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_12_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_12_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_12_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_12_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_12_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_12_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_12_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_12_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_12_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_12_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_12_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_12_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_12_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_12_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_12_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_12_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_12_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_12_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_12_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_12_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_12_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_12_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_12_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_6_io_y_u),
.io_y_ae_ptw (_entries_barrier_6_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_6_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_6_io_y_ae_stage2),
.io_y_pf (_entries_barrier_6_io_y_pf),
.io_y_gf (_entries_barrier_6_io_y_gf),
.io_y_sw (_entries_barrier_6_io_y_sw),
.io_y_sx (_entries_barrier_6_io_y_sx),
.io_y_sr (_entries_barrier_6_io_y_sr),
.io_y_hw (_entries_barrier_6_io_y_hw),
.io_y_hx (_entries_barrier_6_io_y_hx),
.io_y_hr (_entries_barrier_6_io_y_hr),
.io_y_pw (_entries_barrier_6_io_y_pw),
.io_y_px (_entries_barrier_6_io_y_px),
.io_y_pr (_entries_barrier_6_io_y_pr),
.io_y_ppp (_entries_barrier_6_io_y_ppp),
.io_y_pal (_entries_barrier_6_io_y_pal),
.io_y_paa (_entries_barrier_6_io_y_paa),
.io_y_eff (_entries_barrier_6_io_y_eff),
.io_y_c (_entries_barrier_6_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_8 entries_barrier_7 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_14_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_14_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_14_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_14_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_14_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_14_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_14_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_14_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_14_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_14_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_14_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_14_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_14_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_14_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_14_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_14_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_14_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_14_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_14_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_14_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_14_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_14_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_14_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_7_io_y_u),
.io_y_ae_ptw (_entries_barrier_7_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_7_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_7_io_y_ae_stage2),
.io_y_pf (_entries_barrier_7_io_y_pf),
.io_y_gf (_entries_barrier_7_io_y_gf),
.io_y_sw (_entries_barrier_7_io_y_sw),
.io_y_sx (_entries_barrier_7_io_y_sx),
.io_y_sr (_entries_barrier_7_io_y_sr),
.io_y_hw (_entries_barrier_7_io_y_hw),
.io_y_hx (_entries_barrier_7_io_y_hx),
.io_y_hr (_entries_barrier_7_io_y_hr),
.io_y_pw (_entries_barrier_7_io_y_pw),
.io_y_px (_entries_barrier_7_io_y_px),
.io_y_pr (_entries_barrier_7_io_y_pr),
.io_y_ppp (_entries_barrier_7_io_y_ppp),
.io_y_pal (_entries_barrier_7_io_y_pal),
.io_y_paa (_entries_barrier_7_io_y_paa),
.io_y_eff (_entries_barrier_7_io_y_eff),
.io_y_c (_entries_barrier_7_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_9 entries_barrier_8 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_16_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_16_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_16_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_16_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_16_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_16_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_16_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_16_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_16_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_16_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_16_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_16_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_16_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_16_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_16_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_16_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_16_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_16_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_16_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_16_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_16_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_16_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_16_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_8_io_y_u),
.io_y_ae_ptw (_entries_barrier_8_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_8_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_8_io_y_ae_stage2),
.io_y_pf (_entries_barrier_8_io_y_pf),
.io_y_gf (_entries_barrier_8_io_y_gf),
.io_y_sw (_entries_barrier_8_io_y_sw),
.io_y_sx (_entries_barrier_8_io_y_sx),
.io_y_sr (_entries_barrier_8_io_y_sr),
.io_y_hw (_entries_barrier_8_io_y_hw),
.io_y_hx (_entries_barrier_8_io_y_hx),
.io_y_hr (_entries_barrier_8_io_y_hr),
.io_y_pw (_entries_barrier_8_io_y_pw),
.io_y_px (_entries_barrier_8_io_y_px),
.io_y_pr (_entries_barrier_8_io_y_pr),
.io_y_ppp (_entries_barrier_8_io_y_ppp),
.io_y_pal (_entries_barrier_8_io_y_pal),
.io_y_paa (_entries_barrier_8_io_y_paa),
.io_y_eff (_entries_barrier_8_io_y_eff),
.io_y_c (_entries_barrier_8_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_10 entries_barrier_9 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_18_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_18_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_18_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_18_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_18_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_18_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_18_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_18_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_18_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_18_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_18_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_18_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_18_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_18_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_18_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_18_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_18_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_18_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_18_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_18_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_18_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_18_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_18_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_9_io_y_u),
.io_y_ae_ptw (_entries_barrier_9_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_9_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_9_io_y_ae_stage2),
.io_y_pf (_entries_barrier_9_io_y_pf),
.io_y_gf (_entries_barrier_9_io_y_gf),
.io_y_sw (_entries_barrier_9_io_y_sw),
.io_y_sx (_entries_barrier_9_io_y_sx),
.io_y_sr (_entries_barrier_9_io_y_sr),
.io_y_hw (_entries_barrier_9_io_y_hw),
.io_y_hx (_entries_barrier_9_io_y_hx),
.io_y_hr (_entries_barrier_9_io_y_hr),
.io_y_pw (_entries_barrier_9_io_y_pw),
.io_y_px (_entries_barrier_9_io_y_px),
.io_y_pr (_entries_barrier_9_io_y_pr),
.io_y_ppp (_entries_barrier_9_io_y_ppp),
.io_y_pal (_entries_barrier_9_io_y_pal),
.io_y_paa (_entries_barrier_9_io_y_paa),
.io_y_eff (_entries_barrier_9_io_y_eff),
.io_y_c (_entries_barrier_9_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_11 entries_barrier_10 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_20_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_20_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_20_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_20_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_20_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_20_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_20_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_20_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_20_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_20_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_20_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_20_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_20_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_20_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_20_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_20_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_20_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_20_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_20_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_20_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_20_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_20_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_20_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_10_io_y_u),
.io_y_ae_ptw (_entries_barrier_10_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_10_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_10_io_y_ae_stage2),
.io_y_pf (_entries_barrier_10_io_y_pf),
.io_y_gf (_entries_barrier_10_io_y_gf),
.io_y_sw (_entries_barrier_10_io_y_sw),
.io_y_sx (_entries_barrier_10_io_y_sx),
.io_y_sr (_entries_barrier_10_io_y_sr),
.io_y_hw (_entries_barrier_10_io_y_hw),
.io_y_hx (_entries_barrier_10_io_y_hx),
.io_y_hr (_entries_barrier_10_io_y_hr),
.io_y_pw (_entries_barrier_10_io_y_pw),
.io_y_px (_entries_barrier_10_io_y_px),
.io_y_pr (_entries_barrier_10_io_y_pr),
.io_y_ppp (_entries_barrier_10_io_y_ppp),
.io_y_pal (_entries_barrier_10_io_y_pal),
.io_y_paa (_entries_barrier_10_io_y_paa),
.io_y_eff (_entries_barrier_10_io_y_eff),
.io_y_c (_entries_barrier_10_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_12 entries_barrier_11 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_22_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_22_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_22_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_22_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_22_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_22_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_22_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_22_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_22_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_22_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_22_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_22_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_22_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_22_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_22_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_22_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_22_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_22_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_22_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_22_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_22_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_22_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_22_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_11_io_y_u),
.io_y_ae_ptw (_entries_barrier_11_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_11_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_11_io_y_ae_stage2),
.io_y_pf (_entries_barrier_11_io_y_pf),
.io_y_gf (_entries_barrier_11_io_y_gf),
.io_y_sw (_entries_barrier_11_io_y_sw),
.io_y_sx (_entries_barrier_11_io_y_sx),
.io_y_sr (_entries_barrier_11_io_y_sr),
.io_y_hw (_entries_barrier_11_io_y_hw),
.io_y_hx (_entries_barrier_11_io_y_hx),
.io_y_hr (_entries_barrier_11_io_y_hr),
.io_y_pw (_entries_barrier_11_io_y_pw),
.io_y_px (_entries_barrier_11_io_y_px),
.io_y_pr (_entries_barrier_11_io_y_pr),
.io_y_ppp (_entries_barrier_11_io_y_ppp),
.io_y_pal (_entries_barrier_11_io_y_pal),
.io_y_paa (_entries_barrier_11_io_y_paa),
.io_y_eff (_entries_barrier_11_io_y_eff),
.io_y_c (_entries_barrier_11_io_y_c)
); // @[package.scala:267:25]
OptimizationBarrier_TLBEntryData_13 entries_barrier_12 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_24_ppn), // @[TLB.scala:170:77]
.io_x_u (_entries_WIRE_24_u), // @[TLB.scala:170:77]
.io_x_g (_entries_WIRE_24_g), // @[TLB.scala:170:77]
.io_x_ae_ptw (_entries_WIRE_24_ae_ptw), // @[TLB.scala:170:77]
.io_x_ae_final (_entries_WIRE_24_ae_final), // @[TLB.scala:170:77]
.io_x_ae_stage2 (_entries_WIRE_24_ae_stage2), // @[TLB.scala:170:77]
.io_x_pf (_entries_WIRE_24_pf), // @[TLB.scala:170:77]
.io_x_gf (_entries_WIRE_24_gf), // @[TLB.scala:170:77]
.io_x_sw (_entries_WIRE_24_sw), // @[TLB.scala:170:77]
.io_x_sx (_entries_WIRE_24_sx), // @[TLB.scala:170:77]
.io_x_sr (_entries_WIRE_24_sr), // @[TLB.scala:170:77]
.io_x_hw (_entries_WIRE_24_hw), // @[TLB.scala:170:77]
.io_x_hx (_entries_WIRE_24_hx), // @[TLB.scala:170:77]
.io_x_hr (_entries_WIRE_24_hr), // @[TLB.scala:170:77]
.io_x_pw (_entries_WIRE_24_pw), // @[TLB.scala:170:77]
.io_x_px (_entries_WIRE_24_px), // @[TLB.scala:170:77]
.io_x_pr (_entries_WIRE_24_pr), // @[TLB.scala:170:77]
.io_x_ppp (_entries_WIRE_24_ppp), // @[TLB.scala:170:77]
.io_x_pal (_entries_WIRE_24_pal), // @[TLB.scala:170:77]
.io_x_paa (_entries_WIRE_24_paa), // @[TLB.scala:170:77]
.io_x_eff (_entries_WIRE_24_eff), // @[TLB.scala:170:77]
.io_x_c (_entries_WIRE_24_c), // @[TLB.scala:170:77]
.io_x_fragmented_superpage (_entries_WIRE_24_fragmented_superpage), // @[TLB.scala:170:77]
.io_y_u (_entries_barrier_12_io_y_u),
.io_y_ae_ptw (_entries_barrier_12_io_y_ae_ptw),
.io_y_ae_final (_entries_barrier_12_io_y_ae_final),
.io_y_ae_stage2 (_entries_barrier_12_io_y_ae_stage2),
.io_y_pf (_entries_barrier_12_io_y_pf),
.io_y_gf (_entries_barrier_12_io_y_gf),
.io_y_sw (_entries_barrier_12_io_y_sw),
.io_y_sx (_entries_barrier_12_io_y_sx),
.io_y_sr (_entries_barrier_12_io_y_sr),
.io_y_hw (_entries_barrier_12_io_y_hw),
.io_y_hx (_entries_barrier_12_io_y_hx),
.io_y_hr (_entries_barrier_12_io_y_hr)
); // @[package.scala:267:25]
assign io_resp_paddr = io_resp_paddr_0; // @[TLB.scala:318:7]
assign io_resp_gpa = io_resp_gpa_0; // @[TLB.scala:318:7]
assign io_resp_pf_ld = io_resp_pf_ld_0; // @[TLB.scala:318:7]
assign io_resp_pf_st = io_resp_pf_st_0; // @[TLB.scala:318:7]
assign io_resp_pf_inst = io_resp_pf_inst_0; // @[TLB.scala:318:7]
assign io_resp_ae_ld = io_resp_ae_ld_0; // @[TLB.scala:318:7]
assign io_resp_ae_st = io_resp_ae_st_0; // @[TLB.scala:318:7]
assign io_resp_ae_inst = io_resp_ae_inst_0; // @[TLB.scala:318:7]
assign io_resp_ma_ld = io_resp_ma_ld_0; // @[TLB.scala:318:7]
assign io_resp_ma_st = io_resp_ma_st_0; // @[TLB.scala:318:7]
assign io_resp_cacheable = io_resp_cacheable_0; // @[TLB.scala:318:7]
assign io_resp_must_alloc = io_resp_must_alloc_0; // @[TLB.scala:318:7]
assign io_resp_prefetchable = io_resp_prefetchable_0; // @[TLB.scala:318:7]
assign io_resp_size = io_resp_size_0; // @[TLB.scala:318:7]
assign io_resp_cmd = io_resp_cmd_0; // @[TLB.scala:318:7]
assign io_ptw_req_bits_bits_addr = io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7]
assign io_ptw_req_bits_bits_need_gpa = io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7]
assign io_ptw_req_bits_bits_vstage1 = io_ptw_req_bits_bits_vstage1_0; // @[TLB.scala:318:7]
assign io_ptw_req_bits_bits_stage2 = io_ptw_req_bits_bits_stage2_0; // @[TLB.scala:318:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
|
module TLBuffer_a29d64s10k1z3u_1( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [9:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [28:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [9:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [9:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [28:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [9:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [9:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [9:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [9:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [9:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [28:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_23 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a29d64s10k1z3u_1 nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a29d64s10k1z3u_1 nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util._
import FUConstants._
/**
* IO bundle to interact with Issue slot
*
* @param numWakeupPorts number of wakeup ports for the slot
*/
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val request_hp = Output(Bool())
val grant = Input(Bool())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted.
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz))))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W))))
val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue.
val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued.
val debug = {
val result = new Bundle {
val p1 = Bool()
val p2 = Bool()
val p3 = Bool()
val ppred = Bool()
val state = UInt(width=2.W)
}
Output(result)
}
}
/**
* Single issue slot. Holds a uop within the issue queue
*
* @param numWakeupPorts number of wakeup ports
*/
class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters)
extends BoomModule
with IssueUnitConstants
{
val io = IO(new IssueSlotIO(numWakeupPorts))
// slot invalid?
// slot is valid, holding 1 uop
// slot is valid, holds 2 uops (like a store)
def is_invalid = state === s_invalid
def is_valid = state =/= s_invalid
val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot)
val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot)
val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val state = RegInit(s_invalid)
val p1 = RegInit(false.B)
val p2 = RegInit(false.B)
val p3 = RegInit(false.B)
val ppred = RegInit(false.B)
// Poison if woken up by speculative load.
// Poison lasts 1 cycle (as ldMiss will come on the next cycle).
// SO if poisoned is true, set it to false!
val p1_poisoned = RegInit(false.B)
val p2_poisoned = RegInit(false.B)
p1_poisoned := false.B
p2_poisoned := false.B
val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
val slot_uop = RegInit(NullMicroOp)
val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
//-----------------------------------------------------------------------------
// next slot state computation
// compute the next state for THIS entry slot (in a collasping queue, the
// current uop may get moved elsewhere, and a new uop can enter
when (io.kill) {
state := s_invalid
} .elsewhen (io.in_uop.valid) {
state := io.in_uop.bits.iw_state
} .elsewhen (io.clear) {
state := s_invalid
} .otherwise {
state := next_state
}
//-----------------------------------------------------------------------------
// "update" state
// compute the next state for the micro-op in this slot. This micro-op may
// be moved elsewhere, so the "next_state" travels with it.
// defaults
next_state := state
next_uopc := slot_uop.uopc
next_lrs1_rtype := slot_uop.lrs1_rtype
next_lrs2_rtype := slot_uop.lrs2_rtype
when (io.kill) {
next_state := s_invalid
} .elsewhen ((io.grant && (state === s_valid_1)) ||
(io.grant && (state === s_valid_2) && p1 && p2 && ppred)) {
// try to issue this uop.
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_invalid
}
} .elsewhen (io.grant && (state === s_valid_2)) {
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_valid_1
when (p1) {
slot_uop.uopc := uopSTD
next_uopc := uopSTD
slot_uop.lrs1_rtype := RT_X
next_lrs1_rtype := RT_X
} .otherwise {
slot_uop.lrs2_rtype := RT_X
next_lrs2_rtype := RT_X
}
}
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.")
}
// Wakeup Compare Logic
// these signals are the "next_p*" for the current slot's micro-op.
// they are important for shifting the current slot_uop up to an other entry.
val next_p1 = WireInit(p1)
val next_p2 = WireInit(p2)
val next_p3 = WireInit(p3)
val next_ppred = WireInit(ppred)
when (io.in_uop.valid) {
p1 := !(io.in_uop.bits.prs1_busy)
p2 := !(io.in_uop.bits.prs2_busy)
p3 := !(io.in_uop.bits.prs3_busy)
ppred := !(io.in_uop.bits.ppred_busy)
}
when (io.ldspec_miss && next_p1_poisoned) {
assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!")
p1 := false.B
}
when (io.ldspec_miss && next_p2_poisoned) {
assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!")
p2 := false.B
}
for (i <- 0 until numWakeupPorts) {
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs1)) {
p1 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs2)) {
p2 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs3)) {
p3 := true.B
}
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) {
ppred := true.B
}
for (w <- 0 until memWidth) {
assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),
"Loads to x0 should never speculatively wakeup other instructions")
}
// TODO disable if FP IQ.
for (w <- 0 until memWidth) {
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs1 &&
next_uop.lrs1_rtype === RT_FIX) {
p1 := true.B
p1_poisoned := true.B
assert (!next_p1_poisoned)
}
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs2 &&
next_uop.lrs2_rtype === RT_FIX) {
p2 := true.B
p2_poisoned := true.B
assert (!next_p2_poisoned)
}
}
// Handle branch misspeculations
val next_br_mask = GetNewBrMask(io.brupdate, slot_uop)
// was this micro-op killed by a branch? if yes, we can't let it be valid if
// we compact it into an other entry
when (IsKilledByBranch(io.brupdate, slot_uop)) {
next_state := s_invalid
}
when (!io.in_uop.valid) {
slot_uop.br_mask := next_br_mask
}
//-------------------------------------------------------------
// Request Logic
io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill
val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr
io.request_hp := io.request && high_priority
when (state === s_valid_1) {
io.request := p1 && p2 && p3 && ppred && !io.kill
} .elsewhen (state === s_valid_2) {
io.request := (p1 || p2) && ppred && !io.kill
} .otherwise {
io.request := false.B
}
//assign outputs
io.valid := is_valid
io.uop := slot_uop
io.uop.iw_p1_poisoned := p1_poisoned
io.uop.iw_p2_poisoned := p2_poisoned
// micro-op will vacate due to grant.
val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred)
val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned)
io.will_be_valid := is_valid && !(may_vacate && !squash_grant)
io.out_uop := slot_uop
io.out_uop.iw_state := next_state
io.out_uop.uopc := next_uopc
io.out_uop.lrs1_rtype := next_lrs1_rtype
io.out_uop.lrs2_rtype := next_lrs2_rtype
io.out_uop.br_mask := next_br_mask
io.out_uop.prs1_busy := !p1
io.out_uop.prs2_busy := !p2
io.out_uop.prs3_busy := !p3
io.out_uop.ppred_busy := !ppred
io.out_uop.iw_p1_poisoned := p1_poisoned
io.out_uop.iw_p2_poisoned := p2_poisoned
when (state === s_valid_2) {
when (p1 && p2 && ppred) {
; // send out the entire instruction as one uop
} .elsewhen (p1 && ppred) {
io.uop.uopc := slot_uop.uopc
io.uop.lrs2_rtype := RT_X
} .elsewhen (p2 && ppred) {
io.uop.uopc := uopSTD
io.uop.lrs1_rtype := RT_X
}
}
// debug outputs
io.debug.p1 := p1
io.debug.p2 := p2
io.debug.p3 := p3
io.debug.ppred := ppred
io.debug.state := state
}
|
module IssueSlot_2( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29]
wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53]
wire squash_grant = 1'h0; // @[issue-slot.scala:261:37]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23]
assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17]
assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
package constellation.channel
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.util._
import constellation.noc.{HasNoCParams}
class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams {
val io = IO(new Bundle {
val in = Input(new Channel(cParam))
})
val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B }))
for (i <- 0 until cParam.srcSpeedup) {
val flit = io.in.flit(i)
when (flit.valid) {
when (flit.bits.head) {
in_flight(flit.bits.virt_channel_id) := true.B
assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken")
}
when (flit.bits.tail) {
in_flight(flit.bits.virt_channel_id) := false.B
}
}
val possibleFlows = cParam.possibleFlows
when (flit.valid && flit.bits.head) {
cParam match {
case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) =>
assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
}
}
}
File Types.scala:
package constellation.routing
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import constellation.noc.{HasNoCParams}
import constellation.channel.{Flit}
/** A representation for 1 specific virtual channel in wormhole routing
*
* @param src the source node
* @param vc ID for the virtual channel
* @param dst the destination node
* @param n_vc the number of virtual channels
*/
// BEGIN: ChannelRoutingInfo
case class ChannelRoutingInfo(
src: Int,
dst: Int,
vc: Int,
n_vc: Int
) {
// END: ChannelRoutingInfo
require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this")
require (!(src == -1 && dst == -1), s"Illegal $this")
require (vc < n_vc, s"Illegal $this")
val isIngress = src == -1
val isEgress = dst == -1
}
/** Represents the properties of a packet that are relevant for routing
* ingressId and egressId uniquely identify a flow, but vnet and dst are used here
* to simplify the implementation of routingrelations
*
* @param ingressId packet's source ingress point
* @param egressId packet's destination egress point
* @param vNet virtual subnetwork identifier
* @param dst packet's destination node ID
*/
// BEGIN: FlowRoutingInfo
case class FlowRoutingInfo(
ingressId: Int,
egressId: Int,
vNetId: Int,
ingressNode: Int,
ingressNodeId: Int,
egressNode: Int,
egressNodeId: Int,
fifo: Boolean
) {
// END: FlowRoutingInfo
def isFlow(f: FlowRoutingBundle): Bool = {
(f.ingress_node === ingressNode.U &&
f.egress_node === egressNode.U &&
f.ingress_node_id === ingressNodeId.U &&
f.egress_node_id === egressNodeId.U)
}
def asLiteral(b: FlowRoutingBundle): BigInt = {
Seq(
(vNetId , b.vnet_id),
(ingressNode , b.ingress_node),
(ingressNodeId , b.ingress_node_id),
(egressNode , b.egress_node),
(egressNodeId , b.egress_node_id)
).foldLeft(0)((l, t) => {
(l << t._2.getWidth) | t._1
})
}
}
class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams {
// Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination
// This simplifies the routing tables
val vnet_id = UInt(log2Ceil(nVirtualNetworks).W)
val ingress_node = UInt(log2Ceil(nNodes).W)
val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W)
val egress_node = UInt(log2Ceil(nNodes).W)
val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W)
}
|
module NoCMonitor_67( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46]
|
Generate the Verilog code corresponding to the following Chisel files.
File IngressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
class IngressUnit(
ingressNodeId: Int,
cParam: IngressChannelParams,
outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean,
combineSAST: Boolean,
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits)))
}
val io = IO(new IngressUnitIO)
val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2,
flow=combineRCVA))
assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))
route_buffer.io.enq.bits.head := io.in.bits.head
route_buffer.io.enq.bits.tail := io.in.bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
route_buffer.io.enq.bits.flow := DontCare
} else {
route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U
route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U
route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U
route_buffer.io.enq.bits.flow.egress_node := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNode.U)
)
route_buffer.io.enq.bits.flow.egress_node_id := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNodeId.U)
)
}
route_buffer.io.enq.bits.payload := io.in.bits.payload
route_buffer.io.enq.bits.virt_channel_id := DontCare
io.router_req.bits.src_virt_id := 0.U
io.router_req.bits.flow := route_buffer.io.enq.bits.flow
val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U
route_buffer.io.enq.valid := io.in.valid && (
io.router_req.ready || !io.in.bits.head || at_dest)
io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest
io.in.ready := route_buffer.io.enq.ready && (
io.router_req.ready || !io.in.bits.head || at_dest)
route_q.io.enq.valid := io.router_req.fire
route_q.io.enq.bits := io.router_resp
when (io.in.fire && io.in.bits.head && at_dest) {
route_q.io.enq.valid := true.B
route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (egressParams(o).egressId.U === io.in.bits.egress_id) {
route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B
}
}
}
assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))
val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams),
1, pipe=true))
vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits
io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel
io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow
io.vcalloc_req.bits.in_vc := 0.U
val head = route_buffer.io.deq.bits.head
val tail = route_buffer.io.deq.bits.tail
vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head)
)
io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid &&
head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready)
route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head) &&
(vcalloc_q.io.enq.ready || !head))
route_q.io.deq.ready := (route_buffer.io.deq.fire && tail)
vcalloc_q.io.enq.valid := io.vcalloc_req.fire
vcalloc_q.io.enq.bits := io.vcalloc_resp
assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))
io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel
io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail
val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail
io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire
val out_bundle = if (combineSAST) {
Wire(Valid(new SwitchBundle(outParams, egressParams)))
} else {
Reg(Valid(new SwitchBundle(outParams, egressParams)))
}
io.out(0) := out_bundle
out_bundle.valid := vcalloc_buffer.io.deq.fire
out_bundle.bits.flit := vcalloc_buffer.io.deq.bits
out_bundle.bits.flit.virt_channel_id := 0.U
val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq
out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh,
vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq)
io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready
io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready
// TODO: We should not generate input/ingress/output/egress units for untraversable channels
if (!cParam.traversable) {
io.in.ready := false.B
io.router_req.valid := false.B
io.router_req.bits := DontCare
io.vcalloc_req.valid := false.B
io.vcalloc_req.bits := DontCare
io.salloc_req.foreach(_.valid := false.B)
io.salloc_req.foreach(_.bits := DontCare)
io.out.foreach(_.valid := false.B)
io.out.foreach(_.bits := DontCare)
}
}
|
module IngressUnit_34( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [36:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [36:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [3:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire [36:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [36:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 4'h2; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 4'h4; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 4'h3; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 4'h8; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 4'h5; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 4'h6; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = io_in_bits_egress_id == 4'h7; // @[IngressUnit.scala:30:72]
wire [3:0] route_buffer_io_enq_bits_flow_egress_node = {1'h0, {3{_route_buffer_io_enq_bits_flow_egress_node_id_T_4}} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_6 ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_7 ? 3'h6 : 3'h0) | {_route_buffer_io_enq_bits_flow_egress_node_id_T_5, {2{_route_buffer_io_enq_bits_flow_egress_node_id_T_1}} | {_route_buffer_io_enq_bits_flow_egress_node_id_T_2, _route_buffer_io_enq_bits_flow_egress_node_id_T}}}; // @[Mux.scala:30:73]
wire _io_router_req_valid_T_1 = io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head; // @[IngressUnit.scala:26:28, :58:{38,67}]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
|
Generate the Verilog code corresponding to the following Chisel files.
File ResetCatchAndSync.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.{withClockAndReset, withReset}
/** Reset: asynchronous assert,
* synchronous de-assert
*
*/
class ResetCatchAndSync (sync: Int = 3) extends Module {
override def desiredName = s"ResetCatchAndSync_d${sync}"
val io = IO(new Bundle {
val sync_reset = Output(Bool())
val psd = Input(new PSDTestMode())
})
// Bypass both the resets to the flops themselves (to prevent DFT holes on
// those flops) and on the output of the synchronizer circuit (to control
// reset to any flops this circuit drives).
val post_psd_reset = Mux(io.psd.test_mode, io.psd.test_mode_reset, reset.asBool)
withReset(post_psd_reset) {
io.sync_reset := Mux(io.psd.test_mode, io.psd.test_mode_reset,
~AsyncResetSynchronizerShiftReg(true.B, sync))
}
}
object ResetCatchAndSync {
def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None,
psd: Option[PSDTestMode] = None): Bool = {
withClockAndReset(clk, rst) {
val catcher = Module (new ResetCatchAndSync(sync))
if (name.isDefined) {catcher.suggestName(name.get)}
catcher.io.psd <> psd.getOrElse(WireDefault(0.U.asTypeOf(new PSDTestMode())))
catcher.io.sync_reset
}
}
def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name))
def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name))
def apply(clk: Clock, rst: Bool, sync: Int, name: String, psd: PSDTestMode): Bool =
apply(clk, rst, sync, Some(name), Some(psd))
def apply(clk: Clock, rst: Bool, name: String, psd: PSDTestMode): Bool =
apply(clk, rst, name = Some(name), psd = Some(psd))
}
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
|
module ResetCatchAndSync_d3_4( // @[ResetCatchAndSync.scala:13:7]
input clock, // @[ResetCatchAndSync.scala:13:7]
input reset, // @[ResetCatchAndSync.scala:13:7]
output io_sync_reset // @[ResetCatchAndSync.scala:17:14]
);
wire _post_psd_reset_T = reset; // @[ResetCatchAndSync.scala:26:76]
wire io_psd_test_mode = 1'h0; // @[ResetCatchAndSync.scala:13:7, :17:14]
wire io_psd_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:13:7, :17:14]
wire _io_sync_reset_T_1; // @[ResetCatchAndSync.scala:28:25]
wire io_sync_reset_0; // @[ResetCatchAndSync.scala:13:7]
wire post_psd_reset = _post_psd_reset_T; // @[ResetCatchAndSync.scala:26:{27,76}]
wire _io_sync_reset_WIRE; // @[ShiftReg.scala:48:24]
wire _io_sync_reset_T = ~_io_sync_reset_WIRE; // @[ShiftReg.scala:48:24]
assign _io_sync_reset_T_1 = _io_sync_reset_T; // @[ResetCatchAndSync.scala:28:25, :29:7]
assign io_sync_reset_0 = _io_sync_reset_T_1; // @[ResetCatchAndSync.scala:13:7, :28:25]
AsyncResetSynchronizerShiftReg_w1_d3_i0_198 io_sync_reset_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (post_psd_reset), // @[ResetCatchAndSync.scala:26:27]
.io_q (_io_sync_reset_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_sync_reset = io_sync_reset_0; // @[ResetCatchAndSync.scala:13:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File DescribedSRAM.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
}
|
module rockettile_icache_tag_array_4( // @[DescribedSRAM.scala:17:26]
input [5:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [167:0] RW0_wdata,
output [167:0] RW0_rdata,
input [7:0] RW0_wmask
);
rockettile_icache_tag_array_ext rockettile_icache_tag_array_ext ( // @[DescribedSRAM.scala:17:26]
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
); // @[DescribedSRAM.scala:17:26]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
|
module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_15( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [55:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [55:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [31:0] _roundMask_T_5 = 32'hFFFF; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_4 = 32'hFFFF0000; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_10 = 32'hFFFF0000; // @[primitives.scala:77:20]
wire [23:0] _roundMask_T_13 = 24'hFFFF; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_14 = 32'hFFFF00; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_15 = 32'hFF00FF; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_20 = 32'hFF00FF00; // @[primitives.scala:77:20]
wire [27:0] _roundMask_T_23 = 28'hFF00FF; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_24 = 32'hFF00FF0; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_25 = 32'hF0F0F0F; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_30 = 32'hF0F0F0F0; // @[primitives.scala:77:20]
wire [29:0] _roundMask_T_33 = 30'hF0F0F0F; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_34 = 32'h3C3C3C3C; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_35 = 32'h33333333; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_40 = 32'hCCCCCCCC; // @[primitives.scala:77:20]
wire [30:0] _roundMask_T_43 = 31'h33333333; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_44 = 32'h66666666; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_45 = 32'h55555555; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_50 = 32'hAAAAAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_56 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_55 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_61 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_64 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_65 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_66 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_71 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_74 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_75 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_76 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_81 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_84 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_85 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_86 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_91 = 16'hAAAA; // @[primitives.scala:77:20]
wire [11:0] _expOut_T_4 = 12'hC31; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire [55:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [64:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53]
wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53]
wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53]
wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53]
wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53]
wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}]
wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}]
wire doShiftSigDown1 = adjustedSig[55]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [11:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [11:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [51:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [51:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [11:0] _roundMask_T = io_in_sExp_0[11:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [11:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[11]; // @[primitives.scala:52:21, :58:25]
wire [10:0] roundMask_lsbs = _roundMask_T_1[10:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[10]; // @[primitives.scala:58:25, :59:26]
wire [9:0] roundMask_lsbs_1 = roundMask_lsbs[9:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_6 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26]
wire [8:0] roundMask_lsbs_2 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26]
wire [8:0] roundMask_lsbs_6 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26]
wire roundMask_msb_3 = roundMask_lsbs_2[8]; // @[primitives.scala:58:25, :59:26]
wire [7:0] roundMask_lsbs_3 = roundMask_lsbs_2[7:0]; // @[primitives.scala:59:26]
wire roundMask_msb_4 = roundMask_lsbs_3[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_4 = roundMask_lsbs_3[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_5 = roundMask_lsbs_4[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_5 = roundMask_lsbs_4[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_5); // @[primitives.scala:59:26, :76:56]
wire [50:0] _roundMask_T_2 = roundMask_shift[63:13]; // @[primitives.scala:76:56, :78:22]
wire [31:0] _roundMask_T_3 = _roundMask_T_2[31:0]; // @[primitives.scala:77:20, :78:22]
wire [15:0] _roundMask_T_6 = _roundMask_T_3[31:16]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_7 = {16'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_8 = _roundMask_T_3[15:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_9 = {_roundMask_T_8, 16'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_11 = _roundMask_T_9 & 32'hFFFF0000; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [23:0] _roundMask_T_16 = _roundMask_T_12[31:8]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_17 = {8'h0, _roundMask_T_16 & 24'hFF00FF}; // @[primitives.scala:77:20]
wire [23:0] _roundMask_T_18 = _roundMask_T_12[23:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_19 = {_roundMask_T_18, 8'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_21 = _roundMask_T_19 & 32'hFF00FF00; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [27:0] _roundMask_T_26 = _roundMask_T_22[31:4]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_27 = {4'h0, _roundMask_T_26 & 28'hF0F0F0F}; // @[primitives.scala:77:20]
wire [27:0] _roundMask_T_28 = _roundMask_T_22[27:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_29 = {_roundMask_T_28, 4'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_31 = _roundMask_T_29 & 32'hF0F0F0F0; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [29:0] _roundMask_T_36 = _roundMask_T_32[31:2]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_37 = {2'h0, _roundMask_T_36 & 30'h33333333}; // @[primitives.scala:77:20]
wire [29:0] _roundMask_T_38 = _roundMask_T_32[29:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_39 = {_roundMask_T_38, 2'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_41 = _roundMask_T_39 & 32'hCCCCCCCC; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [30:0] _roundMask_T_46 = _roundMask_T_42[31:1]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_47 = {1'h0, _roundMask_T_46 & 31'h55555555}; // @[primitives.scala:77:20]
wire [30:0] _roundMask_T_48 = _roundMask_T_42[30:0]; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_49 = {_roundMask_T_48, 1'h0}; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_51 = _roundMask_T_49 & 32'hAAAAAAAA; // @[primitives.scala:77:20]
wire [31:0] _roundMask_T_52 = _roundMask_T_47 | _roundMask_T_51; // @[primitives.scala:77:20]
wire [18:0] _roundMask_T_53 = _roundMask_T_2[50:32]; // @[primitives.scala:77:20, :78:22]
wire [15:0] _roundMask_T_54 = _roundMask_T_53[15:0]; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_57 = _roundMask_T_54[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_58 = {8'h0, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_59 = _roundMask_T_54[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_60 = {_roundMask_T_59, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_62 = _roundMask_T_60 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_63 = _roundMask_T_58 | _roundMask_T_62; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_67 = _roundMask_T_63[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_68 = {4'h0, _roundMask_T_67 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_69 = _roundMask_T_63[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_70 = {_roundMask_T_69, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_72 = _roundMask_T_70 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_73 = _roundMask_T_68 | _roundMask_T_72; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_77 = _roundMask_T_73[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_78 = {2'h0, _roundMask_T_77 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_79 = _roundMask_T_73[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_80 = {_roundMask_T_79, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_82 = _roundMask_T_80 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_83 = _roundMask_T_78 | _roundMask_T_82; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_87 = _roundMask_T_83[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_88 = {1'h0, _roundMask_T_87 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_89 = _roundMask_T_83[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_90 = {_roundMask_T_89, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_92 = _roundMask_T_90 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_93 = _roundMask_T_88 | _roundMask_T_92; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_94 = _roundMask_T_53[18:16]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_95 = _roundMask_T_94[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_96 = _roundMask_T_95[0]; // @[primitives.scala:77:20]
wire _roundMask_T_97 = _roundMask_T_95[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_98 = {_roundMask_T_96, _roundMask_T_97}; // @[primitives.scala:77:20]
wire _roundMask_T_99 = _roundMask_T_94[2]; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_100 = {_roundMask_T_98, _roundMask_T_99}; // @[primitives.scala:77:20]
wire [18:0] _roundMask_T_101 = {_roundMask_T_93, _roundMask_T_100}; // @[primitives.scala:77:20]
wire [50:0] _roundMask_T_102 = {_roundMask_T_52, _roundMask_T_101}; // @[primitives.scala:77:20]
wire [50:0] _roundMask_T_103 = ~_roundMask_T_102; // @[primitives.scala:73:32, :77:20]
wire [50:0] _roundMask_T_104 = roundMask_msb_5 ? 51'h0 : _roundMask_T_103; // @[primitives.scala:58:25, :73:{21,32}]
wire [50:0] _roundMask_T_105 = ~_roundMask_T_104; // @[primitives.scala:73:{17,21}]
wire [50:0] _roundMask_T_106 = ~_roundMask_T_105; // @[primitives.scala:73:{17,32}]
wire [50:0] _roundMask_T_107 = roundMask_msb_4 ? 51'h0 : _roundMask_T_106; // @[primitives.scala:58:25, :73:{21,32}]
wire [50:0] _roundMask_T_108 = ~_roundMask_T_107; // @[primitives.scala:73:{17,21}]
wire [50:0] _roundMask_T_109 = ~_roundMask_T_108; // @[primitives.scala:73:{17,32}]
wire [50:0] _roundMask_T_110 = roundMask_msb_3 ? 51'h0 : _roundMask_T_109; // @[primitives.scala:58:25, :73:{21,32}]
wire [50:0] _roundMask_T_111 = ~_roundMask_T_110; // @[primitives.scala:73:{17,21}]
wire [50:0] _roundMask_T_112 = ~_roundMask_T_111; // @[primitives.scala:73:{17,32}]
wire [50:0] _roundMask_T_113 = roundMask_msb_2 ? 51'h0 : _roundMask_T_112; // @[primitives.scala:58:25, :73:{21,32}]
wire [50:0] _roundMask_T_114 = ~_roundMask_T_113; // @[primitives.scala:73:{17,21}]
wire [53:0] _roundMask_T_115 = {_roundMask_T_114, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire roundMask_msb_7 = roundMask_lsbs_6[8]; // @[primitives.scala:58:25, :59:26]
wire [7:0] roundMask_lsbs_7 = roundMask_lsbs_6[7:0]; // @[primitives.scala:59:26]
wire roundMask_msb_8 = roundMask_lsbs_7[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_8 = roundMask_lsbs_7[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_9 = roundMask_lsbs_8[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_9 = roundMask_lsbs_8[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_9); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_116 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_117 = _roundMask_T_116[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_118 = _roundMask_T_117[0]; // @[primitives.scala:77:20]
wire _roundMask_T_119 = _roundMask_T_117[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_120 = {_roundMask_T_118, _roundMask_T_119}; // @[primitives.scala:77:20]
wire _roundMask_T_121 = _roundMask_T_116[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_122 = {_roundMask_T_120, _roundMask_T_121}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_123 = roundMask_msb_9 ? _roundMask_T_122 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [2:0] _roundMask_T_124 = roundMask_msb_8 ? _roundMask_T_123 : 3'h0; // @[primitives.scala:58:25, :62:24]
wire [2:0] _roundMask_T_125 = roundMask_msb_7 ? _roundMask_T_124 : 3'h0; // @[primitives.scala:58:25, :62:24]
wire [2:0] _roundMask_T_126 = roundMask_msb_6 ? _roundMask_T_125 : 3'h0; // @[primitives.scala:58:25, :62:24]
wire [53:0] _roundMask_T_127 = roundMask_msb_1 ? _roundMask_T_115 : {51'h0, _roundMask_T_126}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [53:0] _roundMask_T_128 = roundMask_msb ? _roundMask_T_127 : 54'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [53:0] _roundMask_T_129 = {_roundMask_T_128[53:1], _roundMask_T_128[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [55:0] roundMask = {_roundMask_T_129, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [56:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [55:0] shiftedRoundMask = _shiftedRoundMask_T[56:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [55:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [55:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [55:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire [55:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38]
wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38]
assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38]
assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38]
wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32]
assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32]
wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}]
wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29]
wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29]
wire [55:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [53:0] _roundedSig_T_1 = _roundedSig_T[55:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [54:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 55'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [54:0] _roundedSig_T_6 = roundMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [54:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [54:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [54:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [55:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [55:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [53:0] _roundedSig_T_12 = _roundedSig_T_11[55:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42]
wire [54:0] _roundedSig_T_14 = roundPosMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [54:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}]
wire [54:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24]
wire [54:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[54:53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [13:0] sRoundedExp = {io_in_sExp_0[12], io_in_sExp_0} + {{11{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[11:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [51:0] _common_fractOut_T = roundedSig[52:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [51:0] _common_fractOut_T_1 = roundedSig[51:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[13:10]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 14'sh3CE; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}]
wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29]
wire _roundCarry_T = roundedSig[54]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[12:11]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire notNaN_isSpecialInfOut = io_infiniteExc_0 | io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60]
wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}]
wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42]
wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}]
wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [11:0] _expOut_T_1 = _expOut_T ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [11:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [11:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [11:0] _expOut_T_5 = pegMinNonzeroMagOut ? 12'hC31 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18]
wire [11:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}]
wire [11:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14]
wire [11:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 10'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18]
wire [11:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}]
wire [11:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14]
wire [11:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 9'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [11:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [11:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [11:0] _expOut_T_14 = pegMinNonzeroMagOut ? 12'h3CE : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16]
wire [11:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16]
wire [11:0] _expOut_T_16 = pegMaxFiniteMagOut ? 12'hBFF : 12'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16]
wire [11:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16]
wire [11:0] _expOut_T_18 = notNaN_isInfOut ? 12'hC00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [11:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [11:0] _expOut_T_20 = isNaNOut ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [11:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [51:0] _fractOut_T_2 = {isNaNOut, 51'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [51:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [51:0] _fractOut_T_4 = {52{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13]
wire [51:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13]
wire [12:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, io_infiniteExc_0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
|
module PE_313( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_57 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Transposer.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
trait Transposer[T <: Data] extends Module {
def dim: Int
def dataType: T
val io = IO(new Bundle {
val inRow = Flipped(Decoupled(Vec(dim, dataType)))
val outCol = Decoupled(Vec(dim, dataType))
})
}
class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
val sMoveUp :: sMoveLeft :: Nil = Enum(2)
val state = RegInit(sMoveUp)
val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1)
val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1)
io.outCol.valid := 0.U
io.inRow.ready := 0.U
switch(state) {
is(sMoveUp) {
io.inRow.ready := upCounter <= dim.U
io.outCol.valid := leftCounter > 0.U
when(io.inRow.fire) {
upCounter := upCounter + 1.U
}
when(upCounter === (dim-1).U) {
state := sMoveLeft
leftCounter := 0.U
}
when(io.outCol.fire) {
leftCounter := leftCounter - 1.U
}
}
is(sMoveLeft) {
io.inRow.ready := leftCounter <= dim.U // TODO: this is naive
io.outCol.valid := upCounter > 0.U
when(leftCounter === (dim-1).U) {
state := sMoveUp
}
when(io.inRow.fire) {
leftCounter := leftCounter + 1.U
upCounter := 0.U
}
when(io.outCol.fire) {
upCounter := upCounter - 1.U
}
}
}
// Propagate input from bottom row to top row systolically in the move up phase
// TODO: need to iterate over columns to connect Chisel values of type T
// Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?)
for (colIdx <- 0 until dim) {
regArray.foldRight(io.inRow.bits(colIdx)) {
case (regRow, prevReg) =>
when (state === sMoveUp) {
regRow(colIdx) := prevReg
}
regRow(colIdx)
}
}
// Propagate input from right side to left side systolically in the move left phase
for (rowIdx <- 0 until dim) {
regArrayT.foldRight(io.inRow.bits(rowIdx)) {
case (regCol, prevReg) =>
when (state === sMoveLeft) {
regCol(rowIdx) := prevReg
}
regCol(rowIdx)
}
}
// Pull from the left side or the top side based on the state
for (idx <- 0 until dim) {
when (state === sMoveUp) {
io.outCol.bits(idx) := regArray(0)(idx)
}.elsewhen(state === sMoveLeft) {
io.outCol.bits(idx) := regArrayT(0)(idx)
}.otherwise {
io.outCol.bits(idx) := DontCare
}
}
}
class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val LEFT_DIR = 0.U(1.W)
val UP_DIR = 1.U(1.W)
class PE extends Module {
val io = IO(new Bundle {
val inR = Input(dataType)
val inD = Input(dataType)
val outL = Output(dataType)
val outU = Output(dataType)
val dir = Input(UInt(1.W))
val en = Input(Bool())
})
val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en)
io.outU := reg
io.outL := reg
}
val pes = Seq.fill(dim,dim)(Module(new PE))
val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter
val dir = RegInit(LEFT_DIR)
// Wire up horizontal signals
for (row <- 0 until dim; col <- 0 until dim) {
val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL
pes(row)(col).io.inR := right_in
}
// Wire up vertical signals
for (row <- 0 until dim; col <- 0 until dim) {
val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU
pes(row)(col).io.inD := down_in
}
// Wire up global signals
pes.flatten.foreach(_.io.dir := dir)
pes.flatten.foreach(_.io.en := io.inRow.fire)
io.outCol.valid := true.B
io.inRow.ready := true.B
val left_out = VecInit(pes.transpose.head.map(_.io.outL))
val up_out = VecInit(pes.head.map(_.io.outU))
io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out)
when (io.inRow.fire) {
counter := wrappingAdd(counter, 1.U, dim)
}
when (counter === (dim-1).U && io.inRow.fire) {
dir := ~dir
}
}
class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
// state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise
val state = RegInit(0.U(1.W))
val countInc = io.inRow.fire || io.outCol.fire
val (countValue, countWrap) = Counter(countInc, dim)
io.inRow.ready := state === 0.U
io.outCol.valid := state === 1.U
for (i <- 0 until dim) {
for (j <- 0 until dim) {
when(countValue === i.U && io.inRow.fire) {
regArray(i)(j) := io.inRow.bits(j)
}
}
}
for (i <- 0 until dim) {
io.outCol.bits(i) := 0.U
for (j <- 0 until dim) {
when(countValue === j.U) {
io.outCol.bits(i) := regArrayT(j)(i)
}
}
}
when (io.inRow.fire && countWrap) {
state := 1.U
}
when (io.outCol.fire && countWrap) {
state := 0.U
}
assert(!(state === 0.U) || !io.outCol.fire)
assert(!(state === 1.U) || !io.inRow.fire)
}
|
module PE_100( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
|
module AsyncValidSync_75( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_92 io_out_sink_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
|
module AsyncValidSync_108( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_123 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File RecFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class
RecFNToRecFN(
inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int)
extends chisel3.RawModule
{
val io = IO(new Bundle {
val in = Input(Bits((inExpWidth + inSigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in);
if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
io.out := io.in<<(outSigWidth - inSigWidth)
io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W)
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
inExpWidth,
inSigWidth,
outExpWidth,
outSigWidth,
flRoundOpt_sigMSBitAlwaysZero
))
roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn)
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := rawIn
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
|
module RecFNToRecFN_73( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File FSESequenceToCodeConverter.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
import chisel3.{Printable}
import freechips.rocketchip.tile._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.rocket.{TLBConfig, HellaCacheArbiter}
import freechips.rocketchip.util.DecoupledHelper
import freechips.rocketchip.rocket.constants.MemoryOpConstants
import freechips.rocketchip.tilelink._
class FSESequenceToCodeConverterIO()(implicit p: Parameters) extends Bundle {
val src_stream = Flipped(new MemLoaderConsumerBundle)
val ll_consumer = new MemLoaderConsumerBundle
val ml_consumer = new MemLoaderConsumerBundle
val of_consumer = new MemLoaderConsumerBundle
}
class FSESequenceToCodeConverter()(implicit p: Parameters) extends Module {
val io = IO(new FSESequenceToCodeConverterIO())
val ll32 = io.src_stream.output_data(31, 0)
val ml32 = io.src_stream.output_data(63, 32)
val of32 = io.src_stream.output_data(95, 64)
val ll_seq_to_code = Module(new LLSeqToCode())
ll_seq_to_code.io.litlen := ll32
val ml_seq_to_code = Module(new MLSeqToCode())
ml_seq_to_code.io.mlbase := ml32
val of_seq_to_code = Module(new OFSeqToCode())
of_seq_to_code.io.ofbase := of32
val ll_buff = Module(new ZstdCompressorLitRotBuf)
val ml_buff = Module(new ZstdCompressorLitRotBuf)
val of_buff = Module(new ZstdCompressorLitRotBuf)
val split_input_fire = DecoupledHelper(
io.src_stream.output_valid,
io.src_stream.available_output_bytes >= 12.U,
ll_buff.io.memwrites_in.ready,
ml_buff.io.memwrites_in.ready,
of_buff.io.memwrites_in.ready)
io.src_stream.output_ready := split_input_fire.fire(io.src_stream.output_valid)
io.src_stream.user_consumed_bytes := 12.U
val end_of_message = io.src_stream.output_last_chunk && (io.src_stream.user_consumed_bytes === io.src_stream.available_output_bytes)
when (split_input_fire.fire && io.src_stream.output_last_chunk && io.src_stream.available_output_bytes <= 12.U) {
assert(io.src_stream.available_output_bytes === 12.U, "Available sequence bytes is not a multiple of 12")
}
ll_buff.io.memwrites_in.valid := split_input_fire.fire(ll_buff.io.memwrites_in.ready)
ll_buff.io.memwrites_in.bits.data := ll_seq_to_code.io.llcode
ll_buff.io.memwrites_in.bits.validbytes := 1.U
ll_buff.io.memwrites_in.bits.end_of_message := end_of_message
ml_buff.io.memwrites_in.valid := split_input_fire.fire(ml_buff.io.memwrites_in.ready)
ml_buff.io.memwrites_in.bits.data := ml_seq_to_code.io.mlcode
ml_buff.io.memwrites_in.bits.validbytes := 1.U
ml_buff.io.memwrites_in.bits.end_of_message := end_of_message
of_buff.io.memwrites_in.valid := split_input_fire.fire(of_buff.io.memwrites_in.ready)
of_buff.io.memwrites_in.bits.data := of_seq_to_code.io.ofcode
of_buff.io.memwrites_in.bits.validbytes := 1.U
of_buff.io.memwrites_in.bits.end_of_message := end_of_message
when (ll_buff.io.memwrites_in.fire) {
CompressAccelLogger.logInfo("ll32: %d ll8: %d\n", ll32, ll_seq_to_code.io.llcode)
}
when (ml_buff.io.memwrites_in.fire) {
CompressAccelLogger.logInfo("ml32: %d ml8: %d\n", ml32, ml_seq_to_code.io.mlcode)
}
when (of_buff.io.memwrites_in.fire) {
CompressAccelLogger.logInfo("of32: %d of8: %d\n", of32, of_seq_to_code.io.ofcode)
}
val nbseq = RegInit(0.U(64.W))
when (split_input_fire.fire) {
nbseq := nbseq + 1.U
}
val end_of_message_fired = RegInit(false.B)
when (split_input_fire.fire && end_of_message) {
end_of_message_fired := true.B
}
val SBUS_WIDTH = 32
val ll_done = RegInit(false.B)
val ml_done = RegInit(false.B)
val of_done = RegInit(false.B)
val ll_consumed_bytes = RegInit(0.U(64.W))
val ll_remaining_bytes = nbseq - ll_consumed_bytes
when (io.ll_consumer.output_valid && io.ll_consumer.output_ready) {
ll_consumed_bytes := ll_consumed_bytes + io.ll_consumer.user_consumed_bytes
when (io.ll_consumer.output_last_chunk && (io.ll_consumer.user_consumed_bytes === io.ll_consumer.available_output_bytes)) {
ll_done := true.B
}
}
io.ll_consumer <> ll_buff.io.consumer
io.ll_consumer.output_last_chunk := end_of_message_fired && (ll_remaining_bytes <= io.ll_consumer.user_consumed_bytes)
val ml_consumed_bytes = RegInit(0.U(64.W))
val ml_remaining_bytes = nbseq - ml_consumed_bytes
when (io.ml_consumer.output_valid && io.ml_consumer.output_ready) {
ml_consumed_bytes := ml_consumed_bytes + io.ml_consumer.user_consumed_bytes
when (io.ml_consumer.output_last_chunk && (io.ml_consumer.user_consumed_bytes === io.ml_consumer.available_output_bytes)) {
ml_done := true.B
}
}
io.ml_consumer <> ml_buff.io.consumer
io.ml_consumer.output_last_chunk := end_of_message_fired && (ml_remaining_bytes <= io.ml_consumer.user_consumed_bytes)
val of_consumed_bytes = RegInit(0.U(64.W))
val of_remaining_bytes = nbseq - of_consumed_bytes
when (io.of_consumer.output_valid && io.of_consumer.output_ready) {
of_consumed_bytes := of_consumed_bytes + io.of_consumer.user_consumed_bytes
when (io.of_consumer.output_last_chunk && (io.of_consumer.user_consumed_bytes === io.of_consumer.available_output_bytes)) {
of_done := true.B
}
}
io.of_consumer <> of_buff.io.consumer
io.of_consumer.output_last_chunk := end_of_message_fired && (of_remaining_bytes <= io.of_consumer.user_consumed_bytes)
when (ll_done && ml_done && of_done) {
nbseq := 0.U
end_of_message_fired := false.B
ll_done := false.B
ml_done := false.B
of_done := false.B
ll_consumed_bytes := 0.U
ml_consumed_bytes := 0.U
of_consumed_bytes := 0.U
}
}
class LLSeqToCode extends Module {
val io = IO(new Bundle {
val litlen = Input(UInt(32.W))
val llcode = Output(UInt(8.W))
})
val ll_deltaCode = 19.U
val ll_code = Wire(Vec(64, UInt(8.W)))
for (i <- 0 until 16) {
ll_code(i) := i.U
}
ll_code(16) := 16.U
ll_code(17) := 16.U
ll_code(18) := 17.U
ll_code(19) := 17.U
ll_code(20) := 18.U
ll_code(21) := 18.U
ll_code(22) := 19.U
ll_code(23) := 19.U
for (i <- 24 until 28) {
ll_code(i) := 20.U
}
for (i <- 28 until 32) {
ll_code(i) := 21.U
}
for (i <- 32 until 40) {
ll_code(i) := 22.U
}
for (i <- 40 until 48) {
ll_code(i) := 23.U
}
for (i <- 48 until 64) {
ll_code(i) := 24.U
}
io.llcode := Mux(io.litlen > 63.U,
BitOperations.BIT_highbit32(io.litlen) +& ll_deltaCode,
ll_code(io.litlen))
}
class OFSeqToCode extends Module {
val io = IO(new Bundle {
val ofbase = Input(UInt(32.W))
val ofcode = Output(UInt(8.W))
})
io.ofcode := BitOperations.BIT_highbit32(io.ofbase)
}
class MLSeqToCode extends Module {
val io = IO(new Bundle {
val mlbase = Input(UInt(32.W))
val mlcode = Output(UInt(8.W))
})
val ml_deltacode = 36.U
val ml_code = Wire(Vec(128, UInt(8.W)))
for (i <- 0 until 32) {
ml_code(i) := i.U
}
ml_code(32) := 32.U
ml_code(33) := 32.U
ml_code(34) := 33.U
ml_code(35) := 33.U
ml_code(36) := 34.U
ml_code(37) := 34.U
ml_code(38) := 35.U
ml_code(39) := 35.U
for (i <- 40 until 44) {
ml_code(i) := 36.U
}
for (i <- 44 until 48) {
ml_code(i) := 37.U
}
for (i <- 48 until 56) {
ml_code(i) := 38.U
}
for (i <- 56 until 64) {
ml_code(i) := 39.U
}
for (i <- 64 until 80) {
ml_code(i) := 40.U
}
for (i <- 80 until 96) {
ml_code(i) := 41.U
}
for (i <- 96 until 128) {
ml_code(i) := 42.U
}
io.mlcode := Mux(io.mlbase > 127.U,
BitOperations.BIT_highbit32(io.mlbase) +& ml_deltacode,
ml_code(io.mlbase))
}
File Common.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
import chisel3.{Printable}
import org.chipsalliance.cde.config._
class PtrInfo extends Bundle {
val ptr = UInt(64.W)
}
class DecompressPtrInfo extends Bundle {
val ip = UInt(64.W)
}
class StreamInfo extends Bundle {
val ip = UInt(64.W)
val isize = UInt(64.W)
}
class DstInfo extends Bundle {
val op = UInt(64.W)
val cmpflag = UInt(64.W)
}
class DecompressDstInfo extends Bundle {
val op = UInt(64.W)
val cmpflag = UInt(64.W)
}
class DstWithValInfo extends Bundle {
val op = UInt(64.W)
val cmpflag = UInt(64.W)
val cmpval = UInt(64.W)
}
class WriterBundle extends Bundle {
val data = UInt(256.W)
val validbytes = UInt(6.W)
val end_of_message = Bool()
}
class LoadInfoBundle extends Bundle {
val start_byte = UInt(5.W)
val end_byte = UInt(5.W)
}
class MemLoaderConsumerBundle extends Bundle {
val user_consumed_bytes = Input(UInt(log2Up(32+1).W))
val available_output_bytes = Output(UInt(log2Up(32+1).W))
val output_valid = Output(Bool())
val output_ready = Input(Bool())
val output_data = Output(UInt((32*8).W))
val output_last_chunk = Output(Bool())
}
class BufInfoBundle extends Bundle {
val len_bytes = UInt(64.W)
}
object BitOperations {
def BIT_highbit32(x: UInt): UInt = {
// add assertion about x width?
val highBit = 31.U - PriorityEncoder(Reverse(x))
highBit
}
}
|
module LLSeqToCode( // @[FSESequenceToCodeConverter.scala:150:7]
input clock, // @[FSESequenceToCodeConverter.scala:150:7]
input reset, // @[FSESequenceToCodeConverter.scala:150:7]
input [31:0] io_litlen, // @[FSESequenceToCodeConverter.scala:151:14]
output [7:0] io_llcode // @[FSESequenceToCodeConverter.scala:151:14]
);
wire [31:0] io_litlen_0 = io_litlen; // @[FSESequenceToCodeConverter.scala:150:7]
wire [63:0][7:0] _GEN = '{8'h18, 8'h18, 8'h18, 8'h18, 8'h18, 8'h18, 8'h18, 8'h18, 8'h18, 8'h18, 8'h18, 8'h18, 8'h18, 8'h18, 8'h18, 8'h18, 8'h17, 8'h17, 8'h17, 8'h17, 8'h17, 8'h17, 8'h17, 8'h17, 8'h16, 8'h16, 8'h16, 8'h16, 8'h16, 8'h16, 8'h16, 8'h16, 8'h15, 8'h15, 8'h15, 8'h15, 8'h14, 8'h14, 8'h14, 8'h14, 8'h13, 8'h13, 8'h12, 8'h12, 8'h11, 8'h11, 8'h10, 8'h10, 8'hF, 8'hE, 8'hD, 8'hC, 8'hB, 8'hA, 8'h9, 8'h8, 8'h7, 8'h6, 8'h5, 8'h4, 8'h3, 8'h2, 8'h1, 8'h0};
wire [7:0] ll_code_0 = 8'h0; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_1 = 8'h1; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_2 = 8'h2; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_3 = 8'h3; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_4 = 8'h4; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_5 = 8'h5; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_6 = 8'h6; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_7 = 8'h7; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_8 = 8'h8; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_9 = 8'h9; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_10 = 8'hA; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_11 = 8'hB; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_12 = 8'hC; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_13 = 8'hD; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_14 = 8'hE; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_15 = 8'hF; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_16 = 8'h10; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_17 = 8'h10; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_18 = 8'h11; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_19 = 8'h11; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_20 = 8'h12; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_21 = 8'h12; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_22 = 8'h13; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_23 = 8'h13; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_24 = 8'h14; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_25 = 8'h14; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_26 = 8'h14; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_27 = 8'h14; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_28 = 8'h15; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_29 = 8'h15; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_30 = 8'h15; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_31 = 8'h15; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_32 = 8'h16; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_33 = 8'h16; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_34 = 8'h16; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_35 = 8'h16; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_36 = 8'h16; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_37 = 8'h16; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_38 = 8'h16; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_39 = 8'h16; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_40 = 8'h17; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_41 = 8'h17; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_42 = 8'h17; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_43 = 8'h17; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_44 = 8'h17; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_45 = 8'h17; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_46 = 8'h17; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_47 = 8'h17; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_48 = 8'h18; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_49 = 8'h18; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_50 = 8'h18; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_51 = 8'h18; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_52 = 8'h18; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_53 = 8'h18; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_54 = 8'h18; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_55 = 8'h18; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_56 = 8'h18; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_57 = 8'h18; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_58 = 8'h18; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_59 = 8'h18; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_60 = 8'h18; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_61 = 8'h18; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_62 = 8'h18; // @[FSESequenceToCodeConverter.scala:158:21]
wire [7:0] ll_code_63 = 8'h18; // @[FSESequenceToCodeConverter.scala:158:21]
wire [31:0] _io_llcode_highBit_T_1 = 32'hFFFF; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T = 32'hFFFF0000; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_6 = 32'hFFFF0000; // @[Common.scala:66:49]
wire [23:0] _io_llcode_highBit_T_9 = 24'hFFFF; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_10 = 32'hFFFF00; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_11 = 32'hFF00FF; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_16 = 32'hFF00FF00; // @[Common.scala:66:49]
wire [27:0] _io_llcode_highBit_T_19 = 28'hFF00FF; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_20 = 32'hFF00FF0; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_21 = 32'hF0F0F0F; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_26 = 32'hF0F0F0F0; // @[Common.scala:66:49]
wire [29:0] _io_llcode_highBit_T_29 = 30'hF0F0F0F; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_30 = 32'h3C3C3C3C; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_31 = 32'h33333333; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_36 = 32'hCCCCCCCC; // @[Common.scala:66:49]
wire [30:0] _io_llcode_highBit_T_39 = 31'h33333333; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_40 = 32'h66666666; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_41 = 32'h55555555; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_46 = 32'hAAAAAAAA; // @[Common.scala:66:49]
wire [7:0] _io_llcode_T_3; // @[FSESequenceToCodeConverter.scala:187:19]
wire [7:0] io_llcode_0; // @[FSESequenceToCodeConverter.scala:150:7]
wire _io_llcode_T = |(io_litlen_0[31:6]); // @[FSESequenceToCodeConverter.scala:150:7, :187:30]
wire [15:0] _io_llcode_highBit_T_2 = io_litlen_0[31:16]; // @[FSESequenceToCodeConverter.scala:150:7]
wire [31:0] _io_llcode_highBit_T_3 = {16'h0, _io_llcode_highBit_T_2}; // @[Common.scala:66:49]
wire [15:0] _io_llcode_highBit_T_4 = io_litlen_0[15:0]; // @[FSESequenceToCodeConverter.scala:150:7]
wire [31:0] _io_llcode_highBit_T_5 = {_io_llcode_highBit_T_4, 16'h0}; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_7 = _io_llcode_highBit_T_5 & 32'hFFFF0000; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_8 = _io_llcode_highBit_T_3 | _io_llcode_highBit_T_7; // @[Common.scala:66:49]
wire [23:0] _io_llcode_highBit_T_12 = _io_llcode_highBit_T_8[31:8]; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_13 = {8'h0, _io_llcode_highBit_T_12 & 24'hFF00FF}; // @[Common.scala:66:49]
wire [23:0] _io_llcode_highBit_T_14 = _io_llcode_highBit_T_8[23:0]; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_15 = {_io_llcode_highBit_T_14, 8'h0}; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_17 = _io_llcode_highBit_T_15 & 32'hFF00FF00; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_18 = _io_llcode_highBit_T_13 | _io_llcode_highBit_T_17; // @[Common.scala:66:49]
wire [27:0] _io_llcode_highBit_T_22 = _io_llcode_highBit_T_18[31:4]; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_23 = {4'h0, _io_llcode_highBit_T_22 & 28'hF0F0F0F}; // @[Common.scala:66:49]
wire [27:0] _io_llcode_highBit_T_24 = _io_llcode_highBit_T_18[27:0]; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_25 = {_io_llcode_highBit_T_24, 4'h0}; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_27 = _io_llcode_highBit_T_25 & 32'hF0F0F0F0; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_28 = _io_llcode_highBit_T_23 | _io_llcode_highBit_T_27; // @[Common.scala:66:49]
wire [29:0] _io_llcode_highBit_T_32 = _io_llcode_highBit_T_28[31:2]; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_33 = {2'h0, _io_llcode_highBit_T_32 & 30'h33333333}; // @[Common.scala:66:49]
wire [29:0] _io_llcode_highBit_T_34 = _io_llcode_highBit_T_28[29:0]; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_35 = {_io_llcode_highBit_T_34, 2'h0}; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_37 = _io_llcode_highBit_T_35 & 32'hCCCCCCCC; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_38 = _io_llcode_highBit_T_33 | _io_llcode_highBit_T_37; // @[Common.scala:66:49]
wire [30:0] _io_llcode_highBit_T_42 = _io_llcode_highBit_T_38[31:1]; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_43 = {1'h0, _io_llcode_highBit_T_42 & 31'h55555555}; // @[Common.scala:66:49]
wire [30:0] _io_llcode_highBit_T_44 = _io_llcode_highBit_T_38[30:0]; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_45 = {_io_llcode_highBit_T_44, 1'h0}; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_47 = _io_llcode_highBit_T_45 & 32'hAAAAAAAA; // @[Common.scala:66:49]
wire [31:0] _io_llcode_highBit_T_48 = _io_llcode_highBit_T_43 | _io_llcode_highBit_T_47; // @[Common.scala:66:49]
wire _io_llcode_highBit_T_49 = _io_llcode_highBit_T_48[0]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_50 = _io_llcode_highBit_T_48[1]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_51 = _io_llcode_highBit_T_48[2]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_52 = _io_llcode_highBit_T_48[3]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_53 = _io_llcode_highBit_T_48[4]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_54 = _io_llcode_highBit_T_48[5]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_55 = _io_llcode_highBit_T_48[6]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_56 = _io_llcode_highBit_T_48[7]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_57 = _io_llcode_highBit_T_48[8]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_58 = _io_llcode_highBit_T_48[9]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_59 = _io_llcode_highBit_T_48[10]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_60 = _io_llcode_highBit_T_48[11]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_61 = _io_llcode_highBit_T_48[12]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_62 = _io_llcode_highBit_T_48[13]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_63 = _io_llcode_highBit_T_48[14]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_64 = _io_llcode_highBit_T_48[15]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_65 = _io_llcode_highBit_T_48[16]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_66 = _io_llcode_highBit_T_48[17]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_67 = _io_llcode_highBit_T_48[18]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_68 = _io_llcode_highBit_T_48[19]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_69 = _io_llcode_highBit_T_48[20]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_70 = _io_llcode_highBit_T_48[21]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_71 = _io_llcode_highBit_T_48[22]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_72 = _io_llcode_highBit_T_48[23]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_73 = _io_llcode_highBit_T_48[24]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_74 = _io_llcode_highBit_T_48[25]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_75 = _io_llcode_highBit_T_48[26]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_76 = _io_llcode_highBit_T_48[27]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_77 = _io_llcode_highBit_T_48[28]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_78 = _io_llcode_highBit_T_48[29]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_79 = _io_llcode_highBit_T_48[30]; // @[OneHot.scala:48:45]
wire _io_llcode_highBit_T_80 = _io_llcode_highBit_T_48[31]; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_81 = {4'hF, ~_io_llcode_highBit_T_79}; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_82 = _io_llcode_highBit_T_78 ? 5'h1D : _io_llcode_highBit_T_81; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_83 = _io_llcode_highBit_T_77 ? 5'h1C : _io_llcode_highBit_T_82; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_84 = _io_llcode_highBit_T_76 ? 5'h1B : _io_llcode_highBit_T_83; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_85 = _io_llcode_highBit_T_75 ? 5'h1A : _io_llcode_highBit_T_84; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_86 = _io_llcode_highBit_T_74 ? 5'h19 : _io_llcode_highBit_T_85; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_87 = _io_llcode_highBit_T_73 ? 5'h18 : _io_llcode_highBit_T_86; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_88 = _io_llcode_highBit_T_72 ? 5'h17 : _io_llcode_highBit_T_87; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_89 = _io_llcode_highBit_T_71 ? 5'h16 : _io_llcode_highBit_T_88; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_90 = _io_llcode_highBit_T_70 ? 5'h15 : _io_llcode_highBit_T_89; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_91 = _io_llcode_highBit_T_69 ? 5'h14 : _io_llcode_highBit_T_90; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_92 = _io_llcode_highBit_T_68 ? 5'h13 : _io_llcode_highBit_T_91; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_93 = _io_llcode_highBit_T_67 ? 5'h12 : _io_llcode_highBit_T_92; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_94 = _io_llcode_highBit_T_66 ? 5'h11 : _io_llcode_highBit_T_93; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_95 = _io_llcode_highBit_T_65 ? 5'h10 : _io_llcode_highBit_T_94; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_96 = _io_llcode_highBit_T_64 ? 5'hF : _io_llcode_highBit_T_95; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_97 = _io_llcode_highBit_T_63 ? 5'hE : _io_llcode_highBit_T_96; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_98 = _io_llcode_highBit_T_62 ? 5'hD : _io_llcode_highBit_T_97; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_99 = _io_llcode_highBit_T_61 ? 5'hC : _io_llcode_highBit_T_98; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_100 = _io_llcode_highBit_T_60 ? 5'hB : _io_llcode_highBit_T_99; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_101 = _io_llcode_highBit_T_59 ? 5'hA : _io_llcode_highBit_T_100; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_102 = _io_llcode_highBit_T_58 ? 5'h9 : _io_llcode_highBit_T_101; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_103 = _io_llcode_highBit_T_57 ? 5'h8 : _io_llcode_highBit_T_102; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_104 = _io_llcode_highBit_T_56 ? 5'h7 : _io_llcode_highBit_T_103; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_105 = _io_llcode_highBit_T_55 ? 5'h6 : _io_llcode_highBit_T_104; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_106 = _io_llcode_highBit_T_54 ? 5'h5 : _io_llcode_highBit_T_105; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_107 = _io_llcode_highBit_T_53 ? 5'h4 : _io_llcode_highBit_T_106; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_108 = _io_llcode_highBit_T_52 ? 5'h3 : _io_llcode_highBit_T_107; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_109 = _io_llcode_highBit_T_51 ? 5'h2 : _io_llcode_highBit_T_108; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_110 = _io_llcode_highBit_T_50 ? 5'h1 : _io_llcode_highBit_T_109; // @[OneHot.scala:48:45]
wire [4:0] _io_llcode_highBit_T_111 = _io_llcode_highBit_T_49 ? 5'h0 : _io_llcode_highBit_T_110; // @[OneHot.scala:48:45]
wire [5:0] _io_llcode_highBit_T_112 = 6'h1F - {1'h0, _io_llcode_highBit_T_111}; // @[Mux.scala:50:70]
wire [4:0] io_llcode_highBit = _io_llcode_highBit_T_112[4:0]; // @[Common.scala:66:24]
wire [5:0] _io_llcode_T_1 = {1'h0, io_llcode_highBit} + 6'h13; // @[FSESequenceToCodeConverter.scala:188:44]
wire [5:0] _io_llcode_T_2 = io_litlen_0[5:0]; // @[FSESequenceToCodeConverter.scala:150:7]
assign _io_llcode_T_3 = _io_llcode_T ? {2'h0, _io_llcode_T_1} : _GEN[_io_llcode_T_2]; // @[FSESequenceToCodeConverter.scala:187:{19,30}, :188:44]
assign io_llcode_0 = _io_llcode_T_3; // @[FSESequenceToCodeConverter.scala:150:7, :187:19]
assign io_llcode = io_llcode_0; // @[FSESequenceToCodeConverter.scala:150:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
|
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_120( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge)
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
|
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_34( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge)
|
Generate the Verilog code corresponding to the following Chisel files.
File Transposer.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
trait Transposer[T <: Data] extends Module {
def dim: Int
def dataType: T
val io = IO(new Bundle {
val inRow = Flipped(Decoupled(Vec(dim, dataType)))
val outCol = Decoupled(Vec(dim, dataType))
})
}
class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
val sMoveUp :: sMoveLeft :: Nil = Enum(2)
val state = RegInit(sMoveUp)
val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1)
val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1)
io.outCol.valid := 0.U
io.inRow.ready := 0.U
switch(state) {
is(sMoveUp) {
io.inRow.ready := upCounter <= dim.U
io.outCol.valid := leftCounter > 0.U
when(io.inRow.fire) {
upCounter := upCounter + 1.U
}
when(upCounter === (dim-1).U) {
state := sMoveLeft
leftCounter := 0.U
}
when(io.outCol.fire) {
leftCounter := leftCounter - 1.U
}
}
is(sMoveLeft) {
io.inRow.ready := leftCounter <= dim.U // TODO: this is naive
io.outCol.valid := upCounter > 0.U
when(leftCounter === (dim-1).U) {
state := sMoveUp
}
when(io.inRow.fire) {
leftCounter := leftCounter + 1.U
upCounter := 0.U
}
when(io.outCol.fire) {
upCounter := upCounter - 1.U
}
}
}
// Propagate input from bottom row to top row systolically in the move up phase
// TODO: need to iterate over columns to connect Chisel values of type T
// Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?)
for (colIdx <- 0 until dim) {
regArray.foldRight(io.inRow.bits(colIdx)) {
case (regRow, prevReg) =>
when (state === sMoveUp) {
regRow(colIdx) := prevReg
}
regRow(colIdx)
}
}
// Propagate input from right side to left side systolically in the move left phase
for (rowIdx <- 0 until dim) {
regArrayT.foldRight(io.inRow.bits(rowIdx)) {
case (regCol, prevReg) =>
when (state === sMoveLeft) {
regCol(rowIdx) := prevReg
}
regCol(rowIdx)
}
}
// Pull from the left side or the top side based on the state
for (idx <- 0 until dim) {
when (state === sMoveUp) {
io.outCol.bits(idx) := regArray(0)(idx)
}.elsewhen(state === sMoveLeft) {
io.outCol.bits(idx) := regArrayT(0)(idx)
}.otherwise {
io.outCol.bits(idx) := DontCare
}
}
}
class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val LEFT_DIR = 0.U(1.W)
val UP_DIR = 1.U(1.W)
class PE extends Module {
val io = IO(new Bundle {
val inR = Input(dataType)
val inD = Input(dataType)
val outL = Output(dataType)
val outU = Output(dataType)
val dir = Input(UInt(1.W))
val en = Input(Bool())
})
val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en)
io.outU := reg
io.outL := reg
}
val pes = Seq.fill(dim,dim)(Module(new PE))
val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter
val dir = RegInit(LEFT_DIR)
// Wire up horizontal signals
for (row <- 0 until dim; col <- 0 until dim) {
val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL
pes(row)(col).io.inR := right_in
}
// Wire up vertical signals
for (row <- 0 until dim; col <- 0 until dim) {
val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU
pes(row)(col).io.inD := down_in
}
// Wire up global signals
pes.flatten.foreach(_.io.dir := dir)
pes.flatten.foreach(_.io.en := io.inRow.fire)
io.outCol.valid := true.B
io.inRow.ready := true.B
val left_out = VecInit(pes.transpose.head.map(_.io.outL))
val up_out = VecInit(pes.head.map(_.io.outU))
io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out)
when (io.inRow.fire) {
counter := wrappingAdd(counter, 1.U, dim)
}
when (counter === (dim-1).U && io.inRow.fire) {
dir := ~dir
}
}
class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
// state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise
val state = RegInit(0.U(1.W))
val countInc = io.inRow.fire || io.outCol.fire
val (countValue, countWrap) = Counter(countInc, dim)
io.inRow.ready := state === 0.U
io.outCol.valid := state === 1.U
for (i <- 0 until dim) {
for (j <- 0 until dim) {
when(countValue === i.U && io.inRow.fire) {
regArray(i)(j) := io.inRow.bits(j)
}
}
}
for (i <- 0 until dim) {
io.outCol.bits(i) := 0.U
for (j <- 0 until dim) {
when(countValue === j.U) {
io.outCol.bits(i) := regArrayT(j)(i)
}
}
}
when (io.inRow.fire && countWrap) {
state := 1.U
}
when (io.outCol.fire && countWrap) {
state := 0.U
}
assert(!(state === 0.U) || !io.outCol.fire)
assert(!(state === 1.U) || !io.inRow.fire)
}
|
module PE_40( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLMonitor_40( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [6:0] io_in_b_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7]
wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7]
wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7]
wire [6:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7]
wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7]
wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7]
wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7]
wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_38 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_92 = 1'h1; // @[Parameters.scala:56:32]
wire mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29]
wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_31 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_38 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_111 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_113 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_117 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_119 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_123 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_125 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_129 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_131 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_139 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_146 = 1'h1; // @[Parameters.scala:56:32]
wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37]
wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire b_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7]
wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7]
wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7]
wire [15:0] mask_1 = 16'hFFFF; // @[Misc.scala:222:10]
wire [127:0] io_in_b_bits_data = 128'h0; // @[Monitor.scala:36:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38]
wire _legal_source_T_44 = 1'h0; // @[Mux.scala:30:73]
wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _mask_sizeOH_T_5 = 4'h4; // @[OneHot.scala:65:27]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [1:0] b_first_beats1 = 2'h0; // @[Edges.scala:221:14]
wire [1:0] b_first_count = 2'h0; // @[Edges.scala:234:25]
wire [1:0] mask_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] b_first_beats1_decode = 2'h3; // @[Edges.scala:220:59]
wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46]
wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46]
wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76]
wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76]
wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71]
wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71]
wire [7:0] mask_lo_1 = 8'hFF; // @[Misc.scala:222:10]
wire [7:0] mask_hi_1 = 8'hFF; // @[Misc.scala:222:10]
wire [3:0] mask_lo_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_lo_hi_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_hi_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_sizeOH_1 = 4'h5; // @[Misc.scala:202:81]
wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_66 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_67 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_68 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_69 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_70 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_71 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _legal_source_uncommonBits_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _legal_source_uncommonBits_T_2 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _legal_source_uncommonBits_T_3 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _legal_source_uncommonBits_T_4 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _legal_source_uncommonBits_T_5 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_72 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_73 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_74 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_75 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_76 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_77 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_12 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_78 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_79 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_80 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_81 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_82 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_83 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_84 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_85 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_86 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_87 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_88 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_89 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_90 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_91 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_92 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_93 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_94 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_95 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_96 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_97 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_98 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_99 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_100 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_101 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_102 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_103 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_104 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_105 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_106 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_107 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h44; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h46; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_29 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_36 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_30 = _source_ok_T_29 == 4'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_33 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_34 = _source_ok_T_32 & _source_ok_T_33; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_9 = _source_ok_T_34; // @[Parameters.scala:1138:31]
wire _source_ok_T_35 = io_in_a_bits_source_0 == 7'h38; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_35; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_37 = _source_ok_T_36 == 4'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_39 = _source_ok_T_37; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_40 = source_ok_uncommonBits_5 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_41 = _source_ok_T_39 & _source_ok_T_40; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_11 = _source_ok_T_41; // @[Parameters.scala:1138:31]
wire _source_ok_T_42 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_12 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire _source_ok_T_43 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_53 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [3:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0[2]; // @[Misc.scala:206:21]
wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_22 = _uncommonBits_T_22[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_23 = _uncommonBits_T_23[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_28 = _uncommonBits_T_28[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_35 = _uncommonBits_T_35[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_52 = _uncommonBits_T_52[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_58 = _uncommonBits_T_58[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_59 = _uncommonBits_T_59[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_64 = _uncommonBits_T_64[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_65 = _uncommonBits_T_65[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_54 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_54; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_61 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_67 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_73 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_56 = _source_ok_T_55 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_62 = _source_ok_T_61 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_66; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_68 = _source_ok_T_67 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_74 = _source_ok_T_73 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_78; // @[Parameters.scala:1138:31]
wire _source_ok_T_79 = io_in_d_bits_source_0 == 7'h44; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_79; // @[Parameters.scala:1138:31]
wire _source_ok_T_80 = io_in_d_bits_source_0 == 7'h46; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_80; // @[Parameters.scala:1138:31]
wire _source_ok_T_81 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_81; // @[Parameters.scala:1138:31]
wire _source_ok_T_82 = io_in_d_bits_source_0 == 7'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_82; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_90 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_84 = _source_ok_T_83 == 4'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_87 = source_ok_uncommonBits_10 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_88 = _source_ok_T_86 & _source_ok_T_87; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_9 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 7'h38; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_91 = _source_ok_T_90 == 4'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_93 = _source_ok_T_91; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_94 = source_ok_uncommonBits_11 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_95 = _source_ok_T_93 & _source_ok_T_94; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_11 = _source_ok_T_95; // @[Parameters.scala:1138:31]
wire _source_ok_T_96 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_12 = _source_ok_T_96; // @[Parameters.scala:1138:31]
wire _source_ok_T_97 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_106 = _source_ok_T_105 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_107 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46]
wire sink_ok = io_in_d_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :309:31]
wire _legal_source_T = io_in_b_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _legal_source_T_1 = io_in_b_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _legal_source_T_7 = io_in_b_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _legal_source_T_13 = io_in_b_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _legal_source_T_19 = io_in_b_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_69 = _uncommonBits_T_69[1:0]; // @[Parameters.scala:52:{29,56}]
wire _legal_source_T_25 = io_in_b_bits_source_0 == 7'h44; // @[Monitor.scala:36:7]
wire _legal_source_T_26 = io_in_b_bits_source_0 == 7'h46; // @[Monitor.scala:36:7]
wire _legal_source_T_27 = io_in_b_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _legal_source_T_28 = io_in_b_bits_source_0 == 7'h42; // @[Monitor.scala:36:7]
wire [2:0] uncommonBits_70 = _uncommonBits_T_70[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _legal_source_T_29 = io_in_b_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _legal_source_T_36 = io_in_b_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _legal_source_T_35 = io_in_b_bits_source_0 == 7'h38; // @[Monitor.scala:36:7]
wire [2:0] uncommonBits_71 = _uncommonBits_T_71[2:0]; // @[Parameters.scala:52:{29,56}]
wire _legal_source_T_42 = io_in_b_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46]
wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46]
wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40]
wire address_ok = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64]
wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7]
wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_4 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_5 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_6 = mask_sub_sub_2_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_7 = mask_sub_sub_3_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38]
wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38]
wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38]
wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38]
wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38]
wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38]
wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38]
wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38]
wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38]
wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38]
wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38]
wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38]
wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38]
wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38]
wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38]
wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38]
wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31]
wire [1:0] legal_source_uncommonBits = _legal_source_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire _legal_source_T_2 = _legal_source_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _legal_source_T_4 = _legal_source_T_2; // @[Parameters.scala:54:{32,67}]
wire _legal_source_T_6 = _legal_source_T_4; // @[Parameters.scala:54:67, :56:48]
wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31]
wire [1:0] legal_source_uncommonBits_1 = _legal_source_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _legal_source_T_8 = _legal_source_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _legal_source_T_10 = _legal_source_T_8; // @[Parameters.scala:54:{32,67}]
wire _legal_source_T_12 = _legal_source_T_10; // @[Parameters.scala:54:67, :56:48]
wire _legal_source_WIRE_2 = _legal_source_T_12; // @[Parameters.scala:1138:31]
wire [1:0] legal_source_uncommonBits_2 = _legal_source_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _legal_source_T_14 = _legal_source_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _legal_source_T_16 = _legal_source_T_14; // @[Parameters.scala:54:{32,67}]
wire _legal_source_T_18 = _legal_source_T_16; // @[Parameters.scala:54:67, :56:48]
wire _legal_source_WIRE_3 = _legal_source_T_18; // @[Parameters.scala:1138:31]
wire [1:0] legal_source_uncommonBits_3 = _legal_source_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _legal_source_T_20 = _legal_source_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _legal_source_T_22 = _legal_source_T_20; // @[Parameters.scala:54:{32,67}]
wire _legal_source_T_24 = _legal_source_T_22; // @[Parameters.scala:54:67, :56:48]
wire _legal_source_WIRE_4 = _legal_source_T_24; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_5 = _legal_source_T_25; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_6 = _legal_source_T_26; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_7 = _legal_source_T_27; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_8 = _legal_source_T_28; // @[Parameters.scala:1138:31]
wire [2:0] legal_source_uncommonBits_4 = _legal_source_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire _legal_source_T_30 = _legal_source_T_29 == 4'h6; // @[Parameters.scala:54:{10,32}]
wire _legal_source_T_32 = _legal_source_T_30; // @[Parameters.scala:54:{32,67}]
wire _legal_source_T_33 = legal_source_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _legal_source_T_34 = _legal_source_T_32 & _legal_source_T_33; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _legal_source_WIRE_9 = _legal_source_T_34; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_10 = _legal_source_T_35; // @[Parameters.scala:1138:31]
wire [2:0] legal_source_uncommonBits_5 = _legal_source_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire _legal_source_T_37 = _legal_source_T_36 == 4'h4; // @[Parameters.scala:54:{10,32}]
wire _legal_source_T_39 = _legal_source_T_37; // @[Parameters.scala:54:{32,67}]
wire _legal_source_T_40 = legal_source_uncommonBits_5 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _legal_source_T_41 = _legal_source_T_39 & _legal_source_T_40; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _legal_source_WIRE_11 = _legal_source_T_41; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_12 = _legal_source_T_42; // @[Parameters.scala:1138:31]
wire [4:0] _legal_source_T_43 = {_legal_source_WIRE_0, 4'h0}; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_56 = _legal_source_T_43; // @[Mux.scala:30:73]
wire [2:0] _legal_source_T_45 = {_legal_source_WIRE_2, 2'h0}; // @[Mux.scala:30:73]
wire [3:0] _legal_source_T_46 = {_legal_source_WIRE_3, 3'h0}; // @[Mux.scala:30:73]
wire [3:0] _legal_source_T_47 = _legal_source_WIRE_4 ? 4'hC : 4'h0; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_48 = _legal_source_WIRE_5 ? 7'h44 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_49 = _legal_source_WIRE_6 ? 7'h46 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_50 = {_legal_source_WIRE_7, 6'h0}; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_51 = _legal_source_WIRE_8 ? 7'h42 : 7'h0; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_52 = _legal_source_WIRE_9 ? 6'h30 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_53 = _legal_source_WIRE_10 ? 6'h38 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_54 = {_legal_source_WIRE_11, 5'h0}; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_55 = _legal_source_WIRE_12 ? 6'h28 : 6'h0; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_57 = {_legal_source_T_56[4:3], _legal_source_T_56[2:0] | _legal_source_T_45}; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_58 = {_legal_source_T_57[4], _legal_source_T_57[3:0] | _legal_source_T_46}; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_59 = {_legal_source_T_58[4], _legal_source_T_58[3:0] | _legal_source_T_47}; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_60 = {2'h0, _legal_source_T_59} | _legal_source_T_48; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_61 = _legal_source_T_60 | _legal_source_T_49; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_62 = _legal_source_T_61 | _legal_source_T_50; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_63 = _legal_source_T_62 | _legal_source_T_51; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_64 = {_legal_source_T_63[6], _legal_source_T_63[5:0] | _legal_source_T_52}; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_65 = {_legal_source_T_64[6], _legal_source_T_64[5:0] | _legal_source_T_53}; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_66 = {_legal_source_T_65[6], _legal_source_T_65[5:0] | _legal_source_T_54}; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_67 = {_legal_source_T_66[6], _legal_source_T_66[5:0] | _legal_source_T_55}; // @[Mux.scala:30:73]
wire [6:0] _legal_source_WIRE_1_0 = _legal_source_T_67; // @[Mux.scala:30:73]
wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73]
wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_74 = _uncommonBits_T_74[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_75 = _uncommonBits_T_75[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_77 = _uncommonBits_T_77[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_108 = io_in_c_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_0 = _source_ok_T_108; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_109 = io_in_c_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_115 = io_in_c_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_121 = io_in_c_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_127 = io_in_c_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_110 = _source_ok_T_109 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_112 = _source_ok_T_110; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_114 = _source_ok_T_112; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_1 = _source_ok_T_114; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_116 = _source_ok_T_115 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_118 = _source_ok_T_116; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_120 = _source_ok_T_118; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_2 = _source_ok_T_120; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_122 = _source_ok_T_121 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_124 = _source_ok_T_122; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_126 = _source_ok_T_124; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_3 = _source_ok_T_126; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_15 = _source_ok_uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_128 = _source_ok_T_127 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_130 = _source_ok_T_128; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_132 = _source_ok_T_130; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_4 = _source_ok_T_132; // @[Parameters.scala:1138:31]
wire _source_ok_T_133 = io_in_c_bits_source_0 == 7'h44; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_5 = _source_ok_T_133; // @[Parameters.scala:1138:31]
wire _source_ok_T_134 = io_in_c_bits_source_0 == 7'h46; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_6 = _source_ok_T_134; // @[Parameters.scala:1138:31]
wire _source_ok_T_135 = io_in_c_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_7 = _source_ok_T_135; // @[Parameters.scala:1138:31]
wire _source_ok_T_136 = io_in_c_bits_source_0 == 7'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_8 = _source_ok_T_136; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_16 = _source_ok_uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_137 = io_in_c_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_144 = io_in_c_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_138 = _source_ok_T_137 == 4'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_140 = _source_ok_T_138; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_141 = source_ok_uncommonBits_16 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_142 = _source_ok_T_140 & _source_ok_T_141; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_2_9 = _source_ok_T_142; // @[Parameters.scala:1138:31]
wire _source_ok_T_143 = io_in_c_bits_source_0 == 7'h38; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_10 = _source_ok_T_143; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_17 = _source_ok_uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_145 = _source_ok_T_144 == 4'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_147 = _source_ok_T_145; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_148 = source_ok_uncommonBits_17 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_149 = _source_ok_T_147 & _source_ok_T_148; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_2_11 = _source_ok_T_149; // @[Parameters.scala:1138:31]
wire _source_ok_T_150 = io_in_c_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_12 = _source_ok_T_150; // @[Parameters.scala:1138:31]
wire _source_ok_T_151 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_152 = _source_ok_T_151 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_153 = _source_ok_T_152 | _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_154 = _source_ok_T_153 | _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_155 = _source_ok_T_154 | _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_156 = _source_ok_T_155 | _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_157 = _source_ok_T_156 | _source_ok_WIRE_2_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_158 = _source_ok_T_157 | _source_ok_WIRE_2_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_159 = _source_ok_T_158 | _source_ok_WIRE_2_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_160 = _source_ok_T_159 | _source_ok_WIRE_2_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_161 = _source_ok_T_160 | _source_ok_WIRE_2_11; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_2 = _source_ok_T_161 | _source_ok_WIRE_2_12; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71]
assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71]
wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71]
assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71]
wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46]
wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46]
wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46]
wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40]
wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64]
wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_79 = _uncommonBits_T_79[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_80 = _uncommonBits_T_80[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_81 = _uncommonBits_T_81[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_82 = _uncommonBits_T_82[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_83 = _uncommonBits_T_83[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_84 = _uncommonBits_T_84[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_85 = _uncommonBits_T_85[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_86 = _uncommonBits_T_86[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_87 = _uncommonBits_T_87[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_88 = _uncommonBits_T_88[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_89 = _uncommonBits_T_89[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_90 = _uncommonBits_T_90[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_91 = _uncommonBits_T_91[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_92 = _uncommonBits_T_92[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_93 = _uncommonBits_T_93[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_94 = _uncommonBits_T_94[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_95 = _uncommonBits_T_95[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_96 = _uncommonBits_T_96[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_97 = _uncommonBits_T_97[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_98 = _uncommonBits_T_98[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_99 = _uncommonBits_T_99[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_100 = _uncommonBits_T_100[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_101 = _uncommonBits_T_101[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_102 = _uncommonBits_T_102[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_103 = _uncommonBits_T_103[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_104 = _uncommonBits_T_104[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_105 = _uncommonBits_T_105[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_106 = _uncommonBits_T_106[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_107 = _uncommonBits_T_107[2:0]; // @[Parameters.scala:52:{29,56}]
wire sink_ok_1 = io_in_e_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :367:31]
wire _T_2580 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2580; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2580; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [1:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [1:0] a_first_counter; // @[Edges.scala:229:27]
wire [2:0] _a_first_counter1_T = {1'h0, a_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] a_first_counter1 = _a_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_2654 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2654; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2654; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2654; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _T_2654; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [1:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T = {1'h0, d_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1 = _d_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35]
wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35]
reg [1:0] b_first_counter; // @[Edges.scala:229:27]
wire [2:0] _b_first_counter1_T = {1'h0, b_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] b_first_counter1 = _b_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire b_first = b_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _b_first_last_T = b_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] _b_first_counter_T = b_first ? 2'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [6:0] source_2; // @[Monitor.scala:413:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _T_2651 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35]
wire _c_first_T; // @[Decoupled.scala:51:35]
assign _c_first_T = _T_2651; // @[Decoupled.scala:51:35]
wire _c_first_T_1; // @[Decoupled.scala:51:35]
assign _c_first_T_1 = _T_2651; // @[Decoupled.scala:51:35]
wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [1:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [1:0] c_first_counter; // @[Edges.scala:229:27]
wire [2:0] _c_first_counter1_T = {1'h0, c_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] c_first_counter1 = _c_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire c_first = c_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T = c_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_1 = c_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [2:0] size_3; // @[Monitor.scala:517:22]
reg [6:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [70:0] inflight; // @[Monitor.scala:614:27]
reg [283:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [283:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [1:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [1:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [1:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [2:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] a_first_counter1_1 = _a_first_counter1_T_1[1:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [1:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46]
wire [1:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1_1 = _d_first_counter1_T_1[1:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [70:0] a_set; // @[Monitor.scala:626:34]
wire [70:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [283:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [283:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99]
wire [283:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [283:0] _a_opcode_lookup_T_6 = {280'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [283:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[283:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [283:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [283:0] _a_size_lookup_T_6 = {280'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [283:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[283:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_5 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[70:0] : 71'h0; // @[OneHot.scala:58:35]
wire _T_2506 = _T_2580 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2506 ? _a_set_T[70:0] : 71'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2506 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2506 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2506 ? _a_opcodes_set_T_1[283:0] : 284'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_2506 ? _a_sizes_set_T_1[283:0] : 284'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [70:0] d_clr; // @[Monitor.scala:664:34]
wire [70:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [283:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [283:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46]
wire _T_2552 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_8 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2552 & ~d_release_ack ? _d_clr_wo_ready_T[70:0] : 71'h0; // @[OneHot.scala:58:35]
wire _T_2521 = _T_2654 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2521 ? _d_clr_T[70:0] : 71'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2521 ? _d_opcodes_clr_T_5[283:0] : 284'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2521 ? _d_sizes_clr_T_5[283:0] : 284'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [70:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [70:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [70:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [283:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [283:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [283:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [283:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [283:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [283:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [70:0] inflight_1; // @[Monitor.scala:726:35]
reg [283:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
reg [283:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [1:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46]
wire [1:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [1:0] c_first_counter_1; // @[Edges.scala:229:27]
wire [2:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] c_first_counter1_1 = _c_first_counter1_T_1[1:0]; // @[Edges.scala:230:28]
wire c_first_1 = c_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T_2 = c_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_3 = c_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [1:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:4]; // @[package.scala:243:46]
wire [1:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1_2 = _d_first_counter1_T_2[1:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [70:0] c_set; // @[Monitor.scala:738:34]
wire [70:0] c_set_wo_ready; // @[Monitor.scala:739:34]
wire [283:0] c_opcodes_set; // @[Monitor.scala:740:34]
wire [283:0] c_sizes_set; // @[Monitor.scala:741:34]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [283:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [283:0] _c_opcode_lookup_T_6 = {280'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [283:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[283:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [283:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [283:0] _c_size_lookup_T_6 = {280'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [283:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[283:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40]
wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44]
wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7]
wire [127:0] _GEN_9 = 128'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T; // @[OneHot.scala:58:35]
assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35]
assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[70:0] : 71'h0; // @[OneHot.scala:58:35]
wire _T_2593 = _T_2651 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35]
assign c_set = _T_2593 ? _c_set_T[70:0] : 71'h0; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53]
wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}]
assign c_opcodes_set_interm = _T_2593 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]
wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51]
wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}]
assign c_sizes_set_interm = _T_2593 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]
wire [9:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79]
wire [9:0] _c_opcodes_set_T; // @[Monitor.scala:767:79]
assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T; // @[Monitor.scala:768:77]
assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77]
wire [1026:0] _c_opcodes_set_T_1 = {1023'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}]
assign c_opcodes_set = _T_2593 ? _c_opcodes_set_T_1[283:0] : 284'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]
wire [1026:0] _c_sizes_set_T_1 = {1023'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}]
assign c_sizes_set = _T_2593 ? _c_sizes_set_T_1[283:0] : 284'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]
wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47]
wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95]
wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}]
wire [70:0] d_clr_1; // @[Monitor.scala:774:34]
wire [70:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [283:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [283:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2624 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2624 & d_release_ack_1 ? _d_clr_wo_ready_T_1[70:0] : 71'h0; // @[OneHot.scala:58:35]
wire _T_2606 = _T_2654 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2606 ? _d_clr_T_1[70:0] : 71'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2606 ? _d_opcodes_clr_T_11[283:0] : 284'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2606 ? _d_sizes_clr_T_11[283:0] : 284'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}]
wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}]
wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}]
wire [70:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35]
wire [70:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [70:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [283:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43]
wire [283:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [283:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [283:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41]
wire [283:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [283:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26]
wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26]
reg [11:0] inflight_2; // @[Monitor.scala:828:27]
wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:4]; // @[package.scala:243:46]
wire [1:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1_3 = _d_first_counter1_T_3[1:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] d_set; // @[Monitor.scala:833:25]
wire _T_2660 = _T_2654 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35]
wire [15:0] _d_set_T = 16'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35]
assign d_set = _T_2660 ? _d_set_T[11:0] : 12'h0; // @[OneHot.scala:58:35]
wire [11:0] e_clr; // @[Monitor.scala:839:25]
wire [15:0] _e_clr_T = 16'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35]
assign e_clr = io_in_e_valid_0 ? _e_clr_T[11:0] : 12'h0; // @[OneHot.scala:58:35]
|
Generate the Verilog code corresponding to the following Chisel files.
File RouteComputer.scala:
package constellation.router
import chisel3._
import chisel3.util._
import chisel3.util.experimental.decode.{TruthTable, decoder}
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import freechips.rocketchip.rocket.DecodeLogic
import constellation.channel._
import constellation.routing.{FlowRoutingBundle, FlowRoutingInfo}
import constellation.noc.{HasNoCParams}
class RouteComputerReq(implicit val p: Parameters) extends Bundle with HasNoCParams {
val src_virt_id = UInt(virtualChannelBits.W)
val flow = new FlowRoutingBundle
}
class RouteComputerResp(
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle
with HasRouterOutputParams {
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
}
class RouteComputer(
val routerParams: RouterParams,
val inParams: Seq[ChannelParams],
val outParams: Seq[ChannelParams],
val ingressParams: Seq[IngressChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module
with HasRouterParams
with HasRouterInputParams
with HasRouterOutputParams
with HasNoCParams {
val io = IO(new Bundle {
val req = MixedVec(allInParams.map { u => Flipped(Decoupled(new RouteComputerReq)) })
val resp = MixedVec(allInParams.map { u => Output(new RouteComputerResp(outParams, egressParams)) })
})
(io.req zip io.resp).zipWithIndex.map { case ((req, resp), i) =>
req.ready := true.B
if (outParams.size == 0) {
assert(!req.valid)
resp.vc_sel := DontCare
} else {
def toUInt(t: (Int, FlowRoutingInfo)): UInt = {
val l2 = (BigInt(t._1) << req.bits.flow.vnet_id .getWidth) | t._2.vNetId
val l3 = ( l2 << req.bits.flow.ingress_node .getWidth) | t._2.ingressNode
val l4 = ( l3 << req.bits.flow.ingress_node_id.getWidth) | t._2.ingressNodeId
val l5 = ( l4 << req.bits.flow.egress_node .getWidth) | t._2.egressNode
val l6 = ( l5 << req.bits.flow.egress_node_id .getWidth) | t._2.egressNodeId
l6.U(req.bits.getWidth.W)
}
val flow = req.bits.flow
val table = allInParams(i).possibleFlows.toSeq.distinct.map { pI =>
allInParams(i).channelRoutingInfos.map { cI =>
var row: String = "b"
(0 until nOutputs).foreach { o =>
(0 until outParams(o).nVirtualChannels).foreach { outVId =>
row = row + (if (routingRelation(cI, outParams(o).channelRoutingInfos(outVId), pI)) "1" else "0")
}
}
((cI.vc, pI), row)
}
}.flatten
val addr = req.bits.asUInt
val width = outParams.map(_.nVirtualChannels).reduce(_+_)
val decoded = if (table.size > 0) {
val truthTable = TruthTable(
table.map { e => (BitPat(toUInt(e._1)), BitPat(e._2)) },
BitPat("b" + "?" * width)
)
Reverse(decoder(addr, truthTable))
} else {
0.U(width.W)
}
var idx = 0
(0 until nAllOutputs).foreach { o =>
if (o < nOutputs) {
(0 until outParams(o).nVirtualChannels).foreach { outVId =>
resp.vc_sel(o)(outVId) := decoded(idx)
idx += 1
}
} else {
resp.vc_sel(o)(0) := false.B
}
}
}
}
}
|
module RouteComputer_46( // @[RouteComputer.scala:29:7]
input [2:0] io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14]
input [2:0] io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14]
input [4:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14]
input [4:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14]
input [2:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14]
input [2:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14]
input [4:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14]
input [4:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_4, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_1_1 // @[RouteComputer.scala:40:14]
);
assign io_resp_1_vc_sel_0_4 = ~(io_req_1_bits_flow_egress_node_id[0]); // @[pla.scala:78:21]
assign io_resp_0_vc_sel_1_1 = io_req_0_bits_flow_egress_node_id[0]; // @[pla.scala:90:45]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Xbar.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
class IntXbar()(implicit p: Parameters) extends LazyModule
{
val intnode = new IntNexusNode(
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
sourceFn = { seq =>
IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map {
case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
}.flatten)
})
{
override def circuitIdentity = outputs == 1 && inputs == 1
}
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
override def desiredName = s"IntXbar_i${intnode.in.size}_o${intnode.out.size}"
val cat = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten
intnode.out.foreach { case (o, _) => o := cat }
}
}
class IntSyncXbar()(implicit p: Parameters) extends LazyModule
{
val intnode = new IntSyncNexusNode(
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
sourceFn = { seq =>
IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map {
case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
}.flatten)
})
{
override def circuitIdentity = outputs == 1 && inputs == 1
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncXbar_i${intnode.in.size}_o${intnode.out.size}"
val cat = intnode.in.map { case (i, e) => i.sync.take(e.source.num) }.flatten
intnode.out.foreach { case (o, _) => o.sync := cat }
}
}
object IntXbar {
def apply()(implicit p: Parameters): IntNode = {
val xbar = LazyModule(new IntXbar)
xbar.intnode
}
}
object IntSyncXbar {
def apply()(implicit p: Parameters): IntSyncNode = {
val xbar = LazyModule(new IntSyncXbar)
xbar.intnode
}
}
|
module IntXbar_i5_o2_1( // @[Xbar.scala:22:9]
input auto_anon_in_3_0, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_2_0, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_0, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_0, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_0, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_1, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_2, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_3, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_0, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_1, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_2, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_3 // @[LazyModuleImp.scala:107:25]
);
wire auto_anon_in_3_0_0 = auto_anon_in_3_0; // @[Xbar.scala:22:9]
wire auto_anon_in_2_0_0 = auto_anon_in_2_0; // @[Xbar.scala:22:9]
wire auto_anon_in_1_0_0 = auto_anon_in_1_0; // @[Xbar.scala:22:9]
wire auto_anon_in_0_0_0 = auto_anon_in_0_0; // @[Xbar.scala:22:9]
wire auto_anon_in_4_0 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_out_1_4 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_out_0_4 = 1'h0; // @[Xbar.scala:22:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire anonIn_4_0 = 1'h0; // @[MixedNode.scala:551:17]
wire anonOut_4 = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_4 = 1'h0; // @[MixedNode.scala:542:17]
wire anonIn_3_0 = auto_anon_in_3_0_0; // @[Xbar.scala:22:9]
wire anonIn_2_0 = auto_anon_in_2_0_0; // @[Xbar.scala:22:9]
wire anonIn_1_0 = auto_anon_in_1_0_0; // @[Xbar.scala:22:9]
wire anonIn_0 = auto_anon_in_0_0_0; // @[Xbar.scala:22:9]
wire x1_anonOut_0; // @[MixedNode.scala:542:17]
wire x1_anonOut_1; // @[MixedNode.scala:542:17]
wire x1_anonOut_2; // @[MixedNode.scala:542:17]
wire x1_anonOut_3; // @[MixedNode.scala:542:17]
wire anonOut_0; // @[MixedNode.scala:542:17]
wire anonOut_1; // @[MixedNode.scala:542:17]
wire anonOut_2; // @[MixedNode.scala:542:17]
wire anonOut_3; // @[MixedNode.scala:542:17]
wire auto_anon_out_1_0_0; // @[Xbar.scala:22:9]
wire auto_anon_out_1_1_0; // @[Xbar.scala:22:9]
wire auto_anon_out_1_2_0; // @[Xbar.scala:22:9]
wire auto_anon_out_1_3_0; // @[Xbar.scala:22:9]
wire auto_anon_out_0_0_0; // @[Xbar.scala:22:9]
wire auto_anon_out_0_1_0; // @[Xbar.scala:22:9]
wire auto_anon_out_0_2_0; // @[Xbar.scala:22:9]
wire auto_anon_out_0_3_0; // @[Xbar.scala:22:9]
assign anonOut_0 = anonIn_0; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_0 = anonIn_0; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_1 = anonIn_1_0; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_1 = anonIn_1_0; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_2 = anonIn_2_0; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_2 = anonIn_2_0; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_3 = anonIn_3_0; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_3 = anonIn_3_0; // @[MixedNode.scala:542:17, :551:17]
assign auto_anon_out_0_0_0 = anonOut_0; // @[Xbar.scala:22:9]
assign auto_anon_out_0_1_0 = anonOut_1; // @[Xbar.scala:22:9]
assign auto_anon_out_0_2_0 = anonOut_2; // @[Xbar.scala:22:9]
assign auto_anon_out_0_3_0 = anonOut_3; // @[Xbar.scala:22:9]
assign auto_anon_out_1_0_0 = x1_anonOut_0; // @[Xbar.scala:22:9]
assign auto_anon_out_1_1_0 = x1_anonOut_1; // @[Xbar.scala:22:9]
assign auto_anon_out_1_2_0 = x1_anonOut_2; // @[Xbar.scala:22:9]
assign auto_anon_out_1_3_0 = x1_anonOut_3; // @[Xbar.scala:22:9]
assign auto_anon_out_1_0 = auto_anon_out_1_0_0; // @[Xbar.scala:22:9]
assign auto_anon_out_1_1 = auto_anon_out_1_1_0; // @[Xbar.scala:22:9]
assign auto_anon_out_1_2 = auto_anon_out_1_2_0; // @[Xbar.scala:22:9]
assign auto_anon_out_1_3 = auto_anon_out_1_3_0; // @[Xbar.scala:22:9]
assign auto_anon_out_0_0 = auto_anon_out_0_0_0; // @[Xbar.scala:22:9]
assign auto_anon_out_0_1 = auto_anon_out_0_1_0; // @[Xbar.scala:22:9]
assign auto_anon_out_0_2 = auto_anon_out_0_2_0; // @[Xbar.scala:22:9]
assign auto_anon_out_0_3 = auto_anon_out_0_3_0; // @[Xbar.scala:22:9]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File SwitchAllocator.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])
(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val tail = Bool()
}
class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module {
val io = IO(new Bundle {
val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams))))
val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val chosen_oh = Vec(outN, Output(UInt(inN.W)))
})
val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) }
val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_|_))
val mask = RegInit(0.U(inN.W))
val choices = Wire(Vec(outN, UInt(inN.W)))
var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask))
for (i <- 0 until outN) {
choices(i) := sel | (sel >> inN)
sel = PriorityEncoderOH(unassigned & ~choices(i))
}
io.in.foreach(_.ready := false.B)
var chosens = 0.U(inN.W)
val in_tails = Cat(io.in.map(_.bits.tail).reverse)
for (i <- 0 until outN) {
val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse)
val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i))
io.chosen_oh(i) := chosen
io.out(i).valid := (in_valids & chosen).orR
io.out(i).bits := Mux1H(chosen, io.in.map(_.bits))
for (j <- 0 until inN) {
when (chosen(j) && io.out(i).ready) {
io.in(j).ready := true.B
}
}
chosens = chosens | chosen
when (io.out(i).fire) {
lock(i) := chosen & ~in_tails
}
}
when (io.out(0).fire) {
mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_|_)
} .otherwise {
mask := Mux(~mask === 0.U, 0.U, (mask << 1) | 1.U(1.W))
}
}
class SwitchAllocator(
val routerParams: RouterParams,
val inParams: Seq[ChannelParams],
val outParams: Seq[ChannelParams],
val ingressParams: Seq[IngressChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module
with HasRouterParams
with HasRouterInputParams
with HasRouterOutputParams {
val io = IO(new Bundle {
val req = MixedVec(allInParams.map(u =>
Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams))))))
val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))})
val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup,
MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) })
})
val nInputChannels = allInParams.map(_.nVirtualChannels).sum
val arbs = allOutParams.map { oP => Module(new SwitchArbiter(
allInParams.map(_.destSpeedup).reduce(_+_),
oP.srcSpeedup,
outParams,
egressParams
))}
arbs.foreach(_.io.out.foreach(_.ready := true.B))
var idx = 0
io.req.foreach(_.foreach { o =>
val fires = Wire(Vec(arbs.size, Bool()))
arbs.zipWithIndex.foreach { case (a,i) =>
a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_||_)
a.io.in(idx).bits := o.bits
fires(i) := a.io.in(idx).fire
}
o.ready := fires.reduce(_||_)
idx += 1
})
for (i <- 0 until nAllOutputs) {
for (j <- 0 until allOutParams(i).srcSpeedup) {
idx = 0
for (m <- 0 until nAllInputs) {
for (n <- 0 until allInParams(m).destSpeedup) {
io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid
idx += 1
}
}
}
}
io.credit_alloc.foreach(_.foreach(_.alloc := false.B))
io.credit_alloc.foreach(_.foreach(_.tail := false.B))
(arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) =>
for (j <- 0 until i.size) {
for (k <- 0 until a.io.out.size) {
when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) {
i(j).alloc := true.B
i(j).tail := a.io.out(k).bits.tail
}
}
}
}
}
|
module SwitchArbiter_16( // @[SwitchAllocator.scala:17:7]
input clock, // @[SwitchAllocator.scala:17:7]
input reset, // @[SwitchAllocator.scala:17:7]
output io_in_8_ready, // @[SwitchAllocator.scala:18:14]
input io_in_8_valid, // @[SwitchAllocator.scala:18:14]
input io_in_8_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14]
input io_in_8_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_8_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_8_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_9_ready, // @[SwitchAllocator.scala:18:14]
input io_in_9_valid, // @[SwitchAllocator.scala:18:14]
input io_in_9_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14]
input io_in_9_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_9_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_9_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_18_ready, // @[SwitchAllocator.scala:18:14]
input io_in_18_valid, // @[SwitchAllocator.scala:18:14]
input io_in_18_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14]
input io_in_18_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_18_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_18_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_19_ready, // @[SwitchAllocator.scala:18:14]
input io_in_19_valid, // @[SwitchAllocator.scala:18:14]
input io_in_19_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14]
input io_in_19_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_19_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_19_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_20_ready, // @[SwitchAllocator.scala:18:14]
input io_in_20_valid, // @[SwitchAllocator.scala:18:14]
input io_in_20_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14]
input io_in_20_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_20_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_20_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_21_ready, // @[SwitchAllocator.scala:18:14]
input io_in_21_valid, // @[SwitchAllocator.scala:18:14]
input io_in_21_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14]
input io_in_21_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_21_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_21_bits_tail, // @[SwitchAllocator.scala:18:14]
input io_out_0_ready, // @[SwitchAllocator.scala:18:14]
output io_out_0_valid, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14]
output [21:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14]
);
reg [21:0] lock_0; // @[SwitchAllocator.scala:24:38]
wire [21:0] unassigned = {io_in_21_valid, io_in_20_valid, io_in_19_valid, io_in_18_valid, 8'h0, io_in_9_valid, io_in_8_valid, 8'h0} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}]
reg [21:0] mask; // @[SwitchAllocator.scala:27:21]
wire [21:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}]
wire [43:0] sel = _sel_T_1[0] ? 44'h1 : _sel_T_1[1] ? 44'h2 : _sel_T_1[2] ? 44'h4 : _sel_T_1[3] ? 44'h8 : _sel_T_1[4] ? 44'h10 : _sel_T_1[5] ? 44'h20 : _sel_T_1[6] ? 44'h40 : _sel_T_1[7] ? 44'h80 : _sel_T_1[8] ? 44'h100 : _sel_T_1[9] ? 44'h200 : _sel_T_1[10] ? 44'h400 : _sel_T_1[11] ? 44'h800 : _sel_T_1[12] ? 44'h1000 : _sel_T_1[13] ? 44'h2000 : _sel_T_1[14] ? 44'h4000 : _sel_T_1[15] ? 44'h8000 : _sel_T_1[16] ? 44'h10000 : _sel_T_1[17] ? 44'h20000 : _sel_T_1[18] ? 44'h40000 : _sel_T_1[19] ? 44'h80000 : _sel_T_1[20] ? 44'h100000 : _sel_T_1[21] ? 44'h200000 : unassigned[0] ? 44'h400000 : unassigned[1] ? 44'h800000 : unassigned[2] ? 44'h1000000 : unassigned[3] ? 44'h2000000 : unassigned[4] ? 44'h4000000 : unassigned[5] ? 44'h8000000 : unassigned[6] ? 44'h10000000 : unassigned[7] ? 44'h20000000 : unassigned[8] ? 44'h40000000 : unassigned[9] ? 44'h80000000 : unassigned[10] ? 44'h100000000 : unassigned[11] ? 44'h200000000 : unassigned[12] ? 44'h400000000 : unassigned[13] ? 44'h800000000 : unassigned[14] ? 44'h1000000000 : unassigned[15] ? 44'h2000000000 : unassigned[16] ? 44'h4000000000 : unassigned[17] ? 44'h8000000000 : unassigned[18] ? 44'h10000000000 : unassigned[19] ? 44'h20000000000 : unassigned[20] ? 44'h40000000000 : {unassigned[21], 43'h0}; // @[OneHot.scala:85:71]
wire [13:0] _GEN = {io_in_21_valid, io_in_20_valid, io_in_19_valid, io_in_18_valid, 8'h0, io_in_9_valid, io_in_8_valid}; // @[SwitchAllocator.scala:41:24]
wire [13:0] _chosen_T_2 = _GEN & lock_0[21:8]; // @[SwitchAllocator.scala:24:38, :41:24, :42:33]
wire [21:0] chosen = (|{_chosen_T_2[13:10], _chosen_T_2[1:0]}) ? lock_0 : sel[21:0] | sel[43:22]; // @[Mux.scala:50:70]
wire [13:0] _io_out_0_valid_T = _GEN & chosen[21:8]; // @[SwitchAllocator.scala:41:24, :42:21, :44:35]
wire [5:0] _GEN_0 = {_io_out_0_valid_T[13:10], _io_out_0_valid_T[1:0]}; // @[SwitchAllocator.scala:44:35]
wire _GEN_1 = io_out_0_ready & (|_GEN_0); // @[Decoupled.scala:51:35]
wire [20:0] _GEN_2 = chosen[20:0] | chosen[21:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [19:0] _GEN_3 = _GEN_2[19:0] | chosen[21:2]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [18:0] _GEN_4 = _GEN_3[18:0] | chosen[21:3]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [17:0] _GEN_5 = _GEN_4[17:0] | chosen[21:4]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [16:0] _GEN_6 = _GEN_5[16:0] | chosen[21:5]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [15:0] _GEN_7 = _GEN_6[15:0] | chosen[21:6]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [14:0] _GEN_8 = _GEN_7[14:0] | chosen[21:7]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [13:0] _GEN_9 = _GEN_8[13:0] | chosen[21:8]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [12:0] _GEN_10 = _GEN_9[12:0] | chosen[21:9]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [11:0] _GEN_11 = _GEN_10[11:0] | chosen[21:10]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [10:0] _GEN_12 = _GEN_11[10:0] | chosen[21:11]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [9:0] _GEN_13 = _GEN_12[9:0] | chosen[21:12]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [8:0] _GEN_14 = _GEN_13[8:0] | chosen[21:13]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [7:0] _GEN_15 = _GEN_14[7:0] | chosen[21:14]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [6:0] _GEN_16 = _GEN_15[6:0] | chosen[21:15]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [5:0] _GEN_17 = _GEN_16[5:0] | chosen[21:16]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [4:0] _GEN_18 = _GEN_17[4:0] | chosen[21:17]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [3:0] _GEN_19 = _GEN_18[3:0] | chosen[21:18]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [2:0] _GEN_20 = _GEN_19[2:0] | chosen[21:19]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [1:0] _GEN_21 = _GEN_20[1:0] | chosen[21:20]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
always @(posedge clock) begin // @[SwitchAllocator.scala:17:7]
if (reset) begin // @[SwitchAllocator.scala:17:7]
lock_0 <= 22'h0; // @[SwitchAllocator.scala:24:38]
mask <= 22'h0; // @[SwitchAllocator.scala:27:21]
end
else begin // @[SwitchAllocator.scala:17:7]
if (_GEN_1) // @[Decoupled.scala:51:35]
lock_0 <= chosen & {~io_in_21_bits_tail, ~io_in_20_bits_tail, ~io_in_19_bits_tail, ~io_in_18_bits_tail, 8'hFF, ~io_in_9_bits_tail, ~io_in_8_bits_tail, 8'hFF}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}]
mask <= _GEN_1 ? {chosen[21], _GEN_2[20], _GEN_3[19], _GEN_4[18], _GEN_5[17], _GEN_6[16], _GEN_7[15], _GEN_8[14], _GEN_9[13], _GEN_10[12], _GEN_11[11], _GEN_12[10], _GEN_13[9], _GEN_14[8], _GEN_15[7], _GEN_16[6], _GEN_17[5], _GEN_18[4], _GEN_19[3], _GEN_20[2], _GEN_21[1], _GEN_21[0] | chosen[21]} : (&mask) ? 22'h0 : {mask[20:0], 1'h1}; // @[Decoupled.scala:51:35]
end
always @(posedge)
|
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property.cover
import scala.math.{min,max}
case class CacheParameters(
level: Int,
ways: Int,
sets: Int,
blockBytes: Int,
beatBytes: Int, // inner
hintsSkipProbe: Boolean)
{
require (ways > 0)
require (sets > 0)
require (blockBytes > 0 && isPow2(blockBytes))
require (beatBytes > 0 && isPow2(beatBytes))
require (blockBytes >= beatBytes)
val blocks = ways * sets
val sizeBytes = blocks * blockBytes
val blockBeats = blockBytes/beatBytes
}
case class InclusiveCachePortParameters(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e))
}
object InclusiveCachePortParameters
{
val none = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.none)
val full = InclusiveCachePortParameters(
a = BufferParams.default,
b = BufferParams.default,
c = BufferParams.default,
d = BufferParams.default,
e = BufferParams.default)
// This removes feed-through paths from C=>A and A=>C
val fullC = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.default,
d = BufferParams.none,
e = BufferParams.none)
val flowAD = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.flow,
e = BufferParams.none)
val flowAE = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.flow)
// For innerBuf:
// SinkA: no restrictions, flows into scheduler+putbuffer
// SourceB: no restrictions, flows out of scheduler
// sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore
// SourceD: no restrictions, flows out of bankedStore/regout
// SinkE: no restrictions, flows into scheduler
//
// ... so while none is possible, you probably want at least flowAC to cut ready
// from the scheduler delay and flowD to ease SourceD back-pressure
// For outerBufer:
// SourceA: must not be pipe, flows out of scheduler
// SinkB: no restrictions, flows into scheduler
// SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored
// SinkD: no restrictions, flows into scheduler & bankedStore
// SourceE: must not be pipe, flows out of scheduler
//
// ... AE take the channel ready into the scheduler, so you need at least flowAE
}
case class InclusiveCacheMicroParameters(
writeBytes: Int, // backing store update granularity
memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz)
portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes
dirReg: Boolean = false,
innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none
outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE
{
require (writeBytes > 0 && isPow2(writeBytes))
require (memCycles > 0)
require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant
}
case class InclusiveCacheControlParameters(
address: BigInt,
beatBytes: Int,
bankedControl: Boolean)
case class InclusiveCacheParameters(
cache: CacheParameters,
micro: InclusiveCacheMicroParameters,
control: Boolean,
inner: TLEdgeIn,
outer: TLEdgeOut)(implicit val p: Parameters)
{
require (cache.ways > 1)
require (cache.sets > 1 && isPow2(cache.sets))
require (micro.writeBytes <= inner.manager.beatBytes)
require (micro.writeBytes <= outer.manager.beatBytes)
require (inner.manager.beatBytes <= cache.blockBytes)
require (outer.manager.beatBytes <= cache.blockBytes)
// Require that all cached address ranges have contiguous blocks
outer.manager.managers.flatMap(_.address).foreach { a =>
require (a.alignment >= cache.blockBytes)
}
// If we are the first level cache, we do not need to support inner-BCE
val firstLevel = !inner.client.clients.exists(_.supports.probe)
// If we are the last level cache, we do not need to support outer-B
val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED)
require (lastLevel)
// Provision enough resources to achieve full throughput with missing single-beat accesses
val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro)
val secondary = max(mshrs, micro.memCycles - mshrs)
val putLists = micro.memCycles // allow every request to be single beat
val putBeats = max(2*cache.blockBeats, micro.memCycles)
val relLists = 2
val relBeats = relLists*cache.blockBeats
val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address))
val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_))
def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] =
if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail)
val addressMapping = bitOffsets(pickMask)
val addressBits = addressMapping.size
// println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}")
val allClients = inner.client.clients.size
val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size
val clientBits = max(1, clientBitsRaw)
val stateBits = 2
val wayBits = log2Ceil(cache.ways)
val setBits = log2Ceil(cache.sets)
val offsetBits = log2Ceil(cache.blockBytes)
val tagBits = addressBits - setBits - offsetBits
val putBits = log2Ceil(max(putLists, relLists))
require (tagBits > 0)
require (offsetBits > 0)
val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1
val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1
val innerMaskBits = inner.manager.beatBytes / micro.writeBytes
val outerMaskBits = outer.manager.beatBytes / micro.writeBytes
def clientBit(source: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse)
}
}
def clientSource(bit: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U))
}
}
def parseAddress(x: UInt): (UInt, UInt, UInt) = {
val offset = Cat(addressMapping.map(o => x(o,o)).reverse)
val set = offset >> offsetBits
val tag = set >> setBits
(tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0))
}
def widen(x: UInt, width: Int): UInt = {
val y = x | 0.U(width.W)
assert (y >> width === 0.U)
y(width-1, 0)
}
def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = {
val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits))
val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) }
addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) }
Cat(bits.reverse)
}
def restoreAddress(expanded: UInt): UInt = {
val missingBits = flatAddresses
.map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match
.groupBy(_._1)
.view
.mapValues(_.map(_._2))
val muxMask = AddressDecoder(missingBits.values.toList)
val mux = missingBits.toList.map { case (bits, addrs) =>
val widen = addrs.map(_.widen(~muxMask))
val matches = AddressSet
.unify(widen.distinct)
.map(_.contains(expanded))
.reduce(_ || _)
(matches, bits.U)
}
expanded | Mux1H(mux)
}
def dirReg[T <: Data](x: T, en: Bool = true.B): T = {
if (micro.dirReg) RegEnable(x, en) else x
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc)
}
object MetaData
{
val stateBits = 2
def INVALID: UInt = 0.U(stateBits.W) // way is empty
def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk
def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk
def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch
// Does a request need trunk?
def needT(opcode: UInt, param: UInt): Bool = {
!opcode(2) ||
(opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) ||
((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB)
}
// Does a request prove the client need not be probed?
def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = {
// Acquire(toB) and Get => is N, so no probe
// Acquire(*toT) => is N or B, but need T, so no probe
// Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client
// Put* => is N or B, so probe IS needed
opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B)
}
def isToN(param: UInt): Bool = {
param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN
}
def isToB(param: UInt): Bool = {
param === TLPermissions.TtoB || param === TLPermissions.BtoB
}
}
object InclusiveCacheParameters
{
val lfsrBits = 10
val L2ControlAddress = 0x2010000
val L2ControlSize = 0x1000
def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = {
// We need 2-3 normal MSHRs to cover the Directory latency
// To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs
max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats)
}
def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int =
// We need a dedicated MSHR for B+C each
2 + out_mshrs(cache, micro)
}
class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File InclusiveCache.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem.{SubsystemBankedCoherenceKey}
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
class InclusiveCache(
val cache: CacheParameters,
val micro: InclusiveCacheMicroParameters,
control: Option[InclusiveCacheControlParameters] = None
)(implicit p: Parameters)
extends LazyModule
{
val access = TransferSizes(1, cache.blockBytes)
val xfer = TransferSizes(cache.blockBytes, cache.blockBytes)
val atom = TransferSizes(1, cache.beatBytes)
var resourcesOpt: Option[ResourceBindings] = None
val device: SimpleDevice = new SimpleDevice("cache-controller", Seq("sifive,inclusivecache0", "cache")) {
def ofInt(x: Int) = Seq(ResourceInt(BigInt(x)))
override def describe(resources: ResourceBindings): Description = {
resourcesOpt = Some(resources)
val Description(name, mapping) = super.describe(resources)
// Find the outer caches
val outer = node.edges.out
.flatMap(_.manager.managers)
.filter(_.supportsAcquireB)
.flatMap(_.resources.headOption)
.map(_.owner.label)
.distinct
val nextlevel: Option[(String, Seq[ResourceValue])] =
if (outer.isEmpty) {
None
} else {
Some("next-level-cache" -> outer.map(l => ResourceReference(l)).toList)
}
val extra = Map(
"cache-level" -> ofInt(2),
"cache-unified" -> Nil,
"cache-size" -> ofInt(cache.sizeBytes * node.edges.in.size),
"cache-sets" -> ofInt(cache.sets * node.edges.in.size),
"cache-block-size" -> ofInt(cache.blockBytes),
"sifive,mshr-count" -> ofInt(InclusiveCacheParameters.all_mshrs(cache, micro)))
Description(name, mapping ++ extra ++ nextlevel)
}
}
val node: TLAdapterNode = TLAdapterNode(
clientFn = { _ => TLClientPortParameters(Seq(TLClientParameters(
name = s"L${cache.level} InclusiveCache",
sourceId = IdRange(0, InclusiveCacheParameters.out_mshrs(cache, micro)),
supportsProbe = xfer)))
},
managerFn = { m => TLManagerPortParameters(
managers = m.managers.map { m => m.copy(
regionType = if (m.regionType >= RegionType.UNCACHED) RegionType.CACHED else m.regionType,
resources = Resource(device, "caches") +: m.resources,
supportsAcquireB = xfer,
supportsAcquireT = if (m.supportsAcquireT) xfer else TransferSizes.none,
supportsArithmetic = if (m.supportsAcquireT) atom else TransferSizes.none,
supportsLogical = if (m.supportsAcquireT) atom else TransferSizes.none,
supportsGet = access,
supportsPutFull = if (m.supportsAcquireT) access else TransferSizes.none,
supportsPutPartial = if (m.supportsAcquireT) access else TransferSizes.none,
supportsHint = access,
alwaysGrantsT = false,
fifoId = None)
},
beatBytes = cache.beatBytes,
endSinkId = InclusiveCacheParameters.all_mshrs(cache, micro),
minLatency = 2)
})
val ctrls = control.map { c =>
val nCtrls = if (c.bankedControl) p(SubsystemBankedCoherenceKey).nBanks else 1
Seq.tabulate(nCtrls) { i => LazyModule(new InclusiveCacheControl(this,
c.copy(address = c.address + i * InclusiveCacheParameters.L2ControlSize))) }
}.getOrElse(Nil)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
// If you have a control port, you must have at least one cache port
require (ctrls.isEmpty || !node.edges.in.isEmpty)
// Extract the client IdRanges; must be the same on all ports!
val clientIds = node.edges.in.headOption.map(_.client.clients.map(_.sourceId).sortBy(_.start))
node.edges.in.foreach { e => require(e.client.clients.map(_.sourceId).sortBy(_.start) == clientIds.get) }
// Use the natural ordering of clients (just like in Directory)
node.edges.in.headOption.foreach { n =>
println(s"L${cache.level} InclusiveCache Client Map:")
n.client.clients.zipWithIndex.foreach { case (c,i) =>
println(s"\t${i} <= ${c.name}")
}
println("")
}
// Create the L2 Banks
val mods = (node.in zip node.out) map { case ((in, edgeIn), (out, edgeOut)) =>
edgeOut.manager.managers.foreach { m =>
require (m.supportsAcquireB.contains(xfer),
s"All managers behind the L2 must support acquireB($xfer) " +
s"but ${m.name} only supports (${m.supportsAcquireB})!")
if (m.supportsAcquireT) require (m.supportsAcquireT.contains(xfer),
s"Any probing managers behind the L2 must support acquireT($xfer) " +
s"but ${m.name} only supports (${m.supportsAcquireT})!")
}
val params = InclusiveCacheParameters(cache, micro, !ctrls.isEmpty, edgeIn, edgeOut)
val scheduler = Module(new InclusiveCacheBankScheduler(params)).suggestName("inclusive_cache_bank_sched")
scheduler.io.in <> in
out <> scheduler.io.out
scheduler.io.ways := DontCare
scheduler.io.divs := DontCare
// Tie down default values in case there is no controller
scheduler.io.req.valid := false.B
scheduler.io.req.bits.address := 0.U
scheduler.io.resp.ready := true.B
// Fix-up the missing addresses. We do this here so that the Scheduler can be
// deduplicated by Firrtl to make hierarchical place-and-route easier.
out.a.bits.address := params.restoreAddress(scheduler.io.out.a.bits.address)
in .b.bits.address := params.restoreAddress(scheduler.io.in .b.bits.address)
out.c.bits.address := params.restoreAddress(scheduler.io.out.c.bits.address)
scheduler
}
ctrls.foreach { ctrl =>
ctrl.module.io.flush_req.ready := false.B
ctrl.module.io.flush_resp := false.B
ctrl.module.io.flush_match := false.B
}
mods.zip(node.edges.in).zipWithIndex.foreach { case ((sched, edgeIn), i) =>
val ctrl = if (ctrls.size > 1) Some(ctrls(i)) else ctrls.headOption
ctrl.foreach { ctrl => {
val contained = edgeIn.manager.managers.flatMap(_.address)
.map(_.contains(ctrl.module.io.flush_req.bits)).reduce(_||_)
when (contained) { ctrl.module.io.flush_match := true.B }
sched.io.req.valid := contained && ctrl.module.io.flush_req.valid
sched.io.req.bits.address := ctrl.module.io.flush_req.bits
when (contained && sched.io.req.ready) { ctrl.module.io.flush_req.ready := true.B }
when (sched.io.resp.valid) { ctrl.module.io.flush_resp := true.B }
sched.io.resp.ready := true.B
}}
}
def json = s"""{"banks":[${mods.map(_.json).mkString(",")}]}"""
}
}
|
module InclusiveCache( // @[InclusiveCache.scala:108:9]
input clock, // @[InclusiveCache.scala:108:9]
input reset, // @[InclusiveCache.scala:108:9]
output auto_ctrls_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_ctrls_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_ctrls_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_ctrls_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_ctrls_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_ctrls_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_ctrls_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_ctrls_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_ctrls_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_ctrls_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_ctrls_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_ctrls_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_ctrls_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_ctrls_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_ctrls_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_ctrls_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire [31:0] _inclusive_cache_bank_sched_io_in_b_bits_address; // @[InclusiveCache.scala:137:29]
wire [31:0] _inclusive_cache_bank_sched_io_out_a_bits_address; // @[InclusiveCache.scala:137:29]
wire [31:0] _inclusive_cache_bank_sched_io_out_c_bits_address; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_io_req_ready; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_io_resp_valid; // @[InclusiveCache.scala:137:29]
wire _ctrls_io_flush_req_valid; // @[InclusiveCache.scala:103:43]
wire [63:0] _ctrls_io_flush_req_bits; // @[InclusiveCache.scala:103:43]
wire auto_ctrls_ctrl_in_a_valid_0 = auto_ctrls_ctrl_in_a_valid; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_ctrls_ctrl_in_a_bits_opcode_0 = auto_ctrls_ctrl_in_a_bits_opcode; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_ctrls_ctrl_in_a_bits_param_0 = auto_ctrls_ctrl_in_a_bits_param; // @[InclusiveCache.scala:108:9]
wire [1:0] auto_ctrls_ctrl_in_a_bits_size_0 = auto_ctrls_ctrl_in_a_bits_size; // @[InclusiveCache.scala:108:9]
wire [10:0] auto_ctrls_ctrl_in_a_bits_source_0 = auto_ctrls_ctrl_in_a_bits_source; // @[InclusiveCache.scala:108:9]
wire [25:0] auto_ctrls_ctrl_in_a_bits_address_0 = auto_ctrls_ctrl_in_a_bits_address; // @[InclusiveCache.scala:108:9]
wire [7:0] auto_ctrls_ctrl_in_a_bits_mask_0 = auto_ctrls_ctrl_in_a_bits_mask; // @[InclusiveCache.scala:108:9]
wire [63:0] auto_ctrls_ctrl_in_a_bits_data_0 = auto_ctrls_ctrl_in_a_bits_data; // @[InclusiveCache.scala:108:9]
wire auto_ctrls_ctrl_in_a_bits_corrupt_0 = auto_ctrls_ctrl_in_a_bits_corrupt; // @[InclusiveCache.scala:108:9]
wire auto_ctrls_ctrl_in_d_ready_0 = auto_ctrls_ctrl_in_d_ready; // @[InclusiveCache.scala:108:9]
wire auto_in_a_valid_0 = auto_in_a_valid; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[InclusiveCache.scala:108:9]
wire [5:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[InclusiveCache.scala:108:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[InclusiveCache.scala:108:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[InclusiveCache.scala:108:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[InclusiveCache.scala:108:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[InclusiveCache.scala:108:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[InclusiveCache.scala:108:9]
wire auto_in_c_valid_0 = auto_in_c_valid; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[InclusiveCache.scala:108:9]
wire [5:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[InclusiveCache.scala:108:9]
wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[InclusiveCache.scala:108:9]
wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[InclusiveCache.scala:108:9]
wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[InclusiveCache.scala:108:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[InclusiveCache.scala:108:9]
wire auto_in_e_valid_0 = auto_in_e_valid; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[InclusiveCache.scala:108:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[InclusiveCache.scala:108:9]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[InclusiveCache.scala:108:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[InclusiveCache.scala:108:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[InclusiveCache.scala:108:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[InclusiveCache.scala:108:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[InclusiveCache.scala:108:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[InclusiveCache.scala:108:9]
wire [32:0] _nodeOut_a_bits_address_mux_matches_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_address_mux_matches_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _nodeIn_b_bits_address_mux_matches_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _nodeIn_b_bits_address_mux_matches_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_address_mux_matches_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_address_mux_matches_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [7:0] auto_out_b_bits_mask = 8'h0; // @[InclusiveCache.scala:108:9, :137:29]
wire [7:0] nodeOut_b_bits_mask = 8'h0; // @[InclusiveCache.scala:108:9, :137:29]
wire [31:0] auto_out_b_bits_address = 32'h0; // @[InclusiveCache.scala:108:9, :137:29]
wire [31:0] nodeOut_b_bits_address = 32'h0; // @[InclusiveCache.scala:108:9, :137:29]
wire [2:0] auto_out_b_bits_opcode = 3'h0; // @[InclusiveCache.scala:108:9, :137:29]
wire [2:0] auto_out_b_bits_size = 3'h0; // @[InclusiveCache.scala:108:9, :137:29]
wire [2:0] auto_out_b_bits_source = 3'h0; // @[InclusiveCache.scala:108:9, :137:29]
wire [2:0] nodeOut_b_bits_opcode = 3'h0; // @[InclusiveCache.scala:108:9, :137:29]
wire [2:0] nodeOut_b_bits_size = 3'h0; // @[InclusiveCache.scala:108:9, :137:29]
wire [2:0] nodeOut_b_bits_source = 3'h0; // @[InclusiveCache.scala:108:9, :137:29]
wire auto_in_e_ready = 1'h1; // @[Nodes.scala:27:25]
wire auto_out_b_ready = 1'h1; // @[Nodes.scala:27:25]
wire auto_out_e_ready = 1'h1; // @[Nodes.scala:27:25]
wire nodeIn_e_ready = 1'h1; // @[Nodes.scala:27:25]
wire nodeOut_b_ready = 1'h1; // @[Nodes.scala:27:25]
wire nodeOut_e_ready = 1'h1; // @[Nodes.scala:27:25]
wire nodeOut_a_bits_address_mux_0_1 = 1'h1; // @[Nodes.scala:27:25]
wire nodeIn_b_bits_address_mux_0_1 = 1'h1; // @[Nodes.scala:27:25]
wire nodeOut_c_bits_address_mux_0_1 = 1'h1; // @[Nodes.scala:27:25]
wire [63:0] auto_in_b_bits_data = 64'h0; // @[Nodes.scala:27:25]
wire [63:0] auto_out_b_bits_data = 64'h0; // @[Nodes.scala:27:25]
wire [63:0] nodeIn_b_bits_data = 64'h0; // @[Nodes.scala:27:25]
wire [63:0] nodeOut_b_bits_data = 64'h0; // @[Nodes.scala:27:25]
wire [7:0] auto_in_b_bits_mask = 8'hFF; // @[Nodes.scala:27:25]
wire [7:0] nodeIn_b_bits_mask = 8'hFF; // @[Nodes.scala:27:25]
wire [5:0] auto_in_b_bits_source = 6'h21; // @[Nodes.scala:27:25]
wire [5:0] nodeIn_b_bits_source = 6'h21; // @[Nodes.scala:27:25]
wire [2:0] auto_in_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25]
wire [2:0] auto_in_b_bits_size = 3'h6; // @[Nodes.scala:27:25]
wire [2:0] nodeIn_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25]
wire [2:0] nodeIn_b_bits_size = 3'h6; // @[Nodes.scala:27:25]
wire auto_ctrls_ctrl_in_d_bits_sink = 1'h0; // @[Nodes.scala:27:25]
wire auto_ctrls_ctrl_in_d_bits_denied = 1'h0; // @[Nodes.scala:27:25]
wire auto_ctrls_ctrl_in_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25]
wire auto_in_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25]
wire auto_out_b_valid = 1'h0; // @[Nodes.scala:27:25]
wire auto_out_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25]
wire nodeIn_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25]
wire nodeOut_b_valid = 1'h0; // @[Nodes.scala:27:25]
wire nodeOut_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25]
wire [1:0] auto_ctrls_ctrl_in_d_bits_param = 2'h0; // @[InclusiveCache.scala:103:43, :108:9, :137:29]
wire [1:0] auto_out_b_bits_param = 2'h0; // @[InclusiveCache.scala:103:43, :108:9, :137:29]
wire [1:0] nodeOut_b_bits_param = 2'h0; // @[InclusiveCache.scala:103:43, :108:9, :137:29]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[InclusiveCache.scala:108:9]
wire [5:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[InclusiveCache.scala:108:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[InclusiveCache.scala:108:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[InclusiveCache.scala:108:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[InclusiveCache.scala:108:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[InclusiveCache.scala:108:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[InclusiveCache.scala:108:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_c_valid = auto_in_c_valid_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[InclusiveCache.scala:108:9]
wire [5:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[InclusiveCache.scala:108:9]
wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[InclusiveCache.scala:108:9]
wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[InclusiveCache.scala:108:9]
wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[InclusiveCache.scala:108:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[InclusiveCache.scala:108:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [5:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_e_valid = auto_in_e_valid_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[InclusiveCache.scala:108:9]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[InclusiveCache.scala:108:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[InclusiveCache.scala:108:9]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[InclusiveCache.scala:108:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[InclusiveCache.scala:108:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[InclusiveCache.scala:108:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[InclusiveCache.scala:108:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[InclusiveCache.scala:108:9]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_ctrls_ctrl_in_a_ready_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_ctrls_ctrl_in_d_bits_opcode_0; // @[InclusiveCache.scala:108:9]
wire [1:0] auto_ctrls_ctrl_in_d_bits_size_0; // @[InclusiveCache.scala:108:9]
wire [10:0] auto_ctrls_ctrl_in_d_bits_source_0; // @[InclusiveCache.scala:108:9]
wire [63:0] auto_ctrls_ctrl_in_d_bits_data_0; // @[InclusiveCache.scala:108:9]
wire auto_ctrls_ctrl_in_d_valid_0; // @[InclusiveCache.scala:108:9]
wire auto_in_a_ready_0; // @[InclusiveCache.scala:108:9]
wire [1:0] auto_in_b_bits_param_0; // @[InclusiveCache.scala:108:9]
wire [31:0] auto_in_b_bits_address_0; // @[InclusiveCache.scala:108:9]
wire auto_in_b_valid_0; // @[InclusiveCache.scala:108:9]
wire auto_in_c_ready_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[InclusiveCache.scala:108:9]
wire [1:0] auto_in_d_bits_param_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_in_d_bits_size_0; // @[InclusiveCache.scala:108:9]
wire [5:0] auto_in_d_bits_source_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_in_d_bits_sink_0; // @[InclusiveCache.scala:108:9]
wire auto_in_d_bits_denied_0; // @[InclusiveCache.scala:108:9]
wire [63:0] auto_in_d_bits_data_0; // @[InclusiveCache.scala:108:9]
wire auto_in_d_bits_corrupt_0; // @[InclusiveCache.scala:108:9]
wire auto_in_d_valid_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_a_bits_param_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_a_bits_size_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_a_bits_source_0; // @[InclusiveCache.scala:108:9]
wire [31:0] auto_out_a_bits_address_0; // @[InclusiveCache.scala:108:9]
wire [7:0] auto_out_a_bits_mask_0; // @[InclusiveCache.scala:108:9]
wire [63:0] auto_out_a_bits_data_0; // @[InclusiveCache.scala:108:9]
wire auto_out_a_bits_corrupt_0; // @[InclusiveCache.scala:108:9]
wire auto_out_a_valid_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_c_bits_opcode_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_c_bits_param_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_c_bits_size_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_c_bits_source_0; // @[InclusiveCache.scala:108:9]
wire [31:0] auto_out_c_bits_address_0; // @[InclusiveCache.scala:108:9]
wire [63:0] auto_out_c_bits_data_0; // @[InclusiveCache.scala:108:9]
wire auto_out_c_bits_corrupt_0; // @[InclusiveCache.scala:108:9]
wire auto_out_c_valid_0; // @[InclusiveCache.scala:108:9]
wire auto_out_d_ready_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_e_bits_sink_0; // @[InclusiveCache.scala:108:9]
wire auto_out_e_valid_0; // @[InclusiveCache.scala:108:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[InclusiveCache.scala:108:9]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[InclusiveCache.scala:108:9]
assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[InclusiveCache.scala:108:9]
wire [31:0] _nodeIn_b_bits_address_T; // @[Parameters.scala:248:14]
assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[InclusiveCache.scala:108:9]
assign auto_in_c_ready_0 = nodeIn_c_ready; // @[InclusiveCache.scala:108:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[InclusiveCache.scala:108:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[InclusiveCache.scala:108:9]
wire [31:0] _nodeOut_a_bits_address_T; // @[Parameters.scala:248:14]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[InclusiveCache.scala:108:9]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[InclusiveCache.scala:108:9]
wire [31:0] _nodeOut_c_bits_address_T; // @[Parameters.scala:248:14]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[InclusiveCache.scala:108:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[InclusiveCache.scala:108:9]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[InclusiveCache.scala:108:9]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[InclusiveCache.scala:108:9]
wire [31:0] _nodeOut_a_bits_address_mux_matches_T; // @[Parameters.scala:137:31]
wire [32:0] _nodeOut_a_bits_address_mux_matches_T_1 = {1'h0, _nodeOut_a_bits_address_mux_matches_T}; // @[Nodes.scala:27:25]
assign nodeOut_a_bits_address = _nodeOut_a_bits_address_T; // @[Parameters.scala:248:14]
wire [31:0] _nodeIn_b_bits_address_mux_matches_T; // @[Parameters.scala:137:31]
wire [32:0] _nodeIn_b_bits_address_mux_matches_T_1 = {1'h0, _nodeIn_b_bits_address_mux_matches_T}; // @[Nodes.scala:27:25]
assign nodeIn_b_bits_address = _nodeIn_b_bits_address_T; // @[Parameters.scala:248:14]
wire [31:0] _nodeOut_c_bits_address_mux_matches_T; // @[Parameters.scala:137:31]
wire [32:0] _nodeOut_c_bits_address_mux_matches_T_1 = {1'h0, _nodeOut_c_bits_address_mux_matches_T}; // @[Nodes.scala:27:25]
assign nodeOut_c_bits_address = _nodeOut_c_bits_address_T; // @[Parameters.scala:248:14]
wire [63:0] _contained_T = {_ctrls_io_flush_req_bits[63:32], _ctrls_io_flush_req_bits[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31]
wire [64:0] _contained_T_1 = {1'h0, _contained_T}; // @[Nodes.scala:27:25]
wire [64:0] _contained_T_2 = _contained_T_1 & 65'h1FFFFFFFFF0000000; // @[Parameters.scala:137:{41,46}]
wire [64:0] _contained_T_3 = _contained_T_2; // @[Parameters.scala:137:46]
wire _contained_T_4 = _contained_T_3 == 65'h0; // @[Parameters.scala:137:{46,59}]
wire [63:0] _contained_T_5 = {_ctrls_io_flush_req_bits[63:28], _ctrls_io_flush_req_bits[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [64:0] _contained_T_6 = {1'h0, _contained_T_5}; // @[Nodes.scala:27:25]
wire [64:0] _contained_T_7 = _contained_T_6 & 65'h1FFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [64:0] _contained_T_8 = _contained_T_7; // @[Parameters.scala:137:46]
wire _contained_T_9 = _contained_T_8 == 65'h0; // @[Parameters.scala:137:{46,59}]
wire contained = _contained_T_4 | _contained_T_9; // @[Parameters.scala:137:59]
wire _inclusive_cache_bank_sched_io_req_valid_T = contained & _ctrls_io_flush_req_valid; // @[InclusiveCache.scala:103:43, :169:67, :172:41]
InclusiveCacheControl ctrls ( // @[InclusiveCache.scala:103:43]
.clock (clock),
.reset (reset),
.auto_ctrl_in_a_ready (auto_ctrls_ctrl_in_a_ready_0),
.auto_ctrl_in_a_valid (auto_ctrls_ctrl_in_a_valid_0), // @[InclusiveCache.scala:108:9]
.auto_ctrl_in_a_bits_opcode (auto_ctrls_ctrl_in_a_bits_opcode_0), // @[InclusiveCache.scala:108:9]
.auto_ctrl_in_a_bits_param (auto_ctrls_ctrl_in_a_bits_param_0), // @[InclusiveCache.scala:108:9]
.auto_ctrl_in_a_bits_size (auto_ctrls_ctrl_in_a_bits_size_0), // @[InclusiveCache.scala:108:9]
.auto_ctrl_in_a_bits_source (auto_ctrls_ctrl_in_a_bits_source_0), // @[InclusiveCache.scala:108:9]
.auto_ctrl_in_a_bits_address (auto_ctrls_ctrl_in_a_bits_address_0), // @[InclusiveCache.scala:108:9]
.auto_ctrl_in_a_bits_mask (auto_ctrls_ctrl_in_a_bits_mask_0), // @[InclusiveCache.scala:108:9]
.auto_ctrl_in_a_bits_data (auto_ctrls_ctrl_in_a_bits_data_0), // @[InclusiveCache.scala:108:9]
.auto_ctrl_in_a_bits_corrupt (auto_ctrls_ctrl_in_a_bits_corrupt_0), // @[InclusiveCache.scala:108:9]
.auto_ctrl_in_d_ready (auto_ctrls_ctrl_in_d_ready_0), // @[InclusiveCache.scala:108:9]
.auto_ctrl_in_d_valid (auto_ctrls_ctrl_in_d_valid_0),
.auto_ctrl_in_d_bits_opcode (auto_ctrls_ctrl_in_d_bits_opcode_0),
.auto_ctrl_in_d_bits_size (auto_ctrls_ctrl_in_d_bits_size_0),
.auto_ctrl_in_d_bits_source (auto_ctrls_ctrl_in_d_bits_source_0),
.auto_ctrl_in_d_bits_data (auto_ctrls_ctrl_in_d_bits_data_0),
.io_flush_match (contained), // @[InclusiveCache.scala:169:67]
.io_flush_req_ready (contained & _inclusive_cache_bank_sched_io_req_ready), // @[InclusiveCache.scala:137:29, :169:67, :174:25]
.io_flush_req_valid (_ctrls_io_flush_req_valid),
.io_flush_req_bits (_ctrls_io_flush_req_bits),
.io_flush_resp (_inclusive_cache_bank_sched_io_resp_valid) // @[InclusiveCache.scala:137:29]
); // @[InclusiveCache.scala:103:43]
TLMonitor_34 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17]
.io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17]
.io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
InclusiveCacheBankScheduler inclusive_cache_bank_sched ( // @[InclusiveCache.scala:137:29]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready),
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_b_valid),
.io_in_b_bits_param (nodeIn_b_bits_param),
.io_in_b_bits_address (_inclusive_cache_bank_sched_io_in_b_bits_address),
.io_in_c_ready (nodeIn_c_ready),
.io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid),
.io_in_d_bits_opcode (nodeIn_d_bits_opcode),
.io_in_d_bits_param (nodeIn_d_bits_param),
.io_in_d_bits_size (nodeIn_d_bits_size),
.io_in_d_bits_source (nodeIn_d_bits_source),
.io_in_d_bits_sink (nodeIn_d_bits_sink),
.io_in_d_bits_denied (nodeIn_d_bits_denied),
.io_in_d_bits_data (nodeIn_d_bits_data),
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt),
.io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17]
.io_out_a_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_out_a_valid (nodeOut_a_valid),
.io_out_a_bits_opcode (nodeOut_a_bits_opcode),
.io_out_a_bits_param (nodeOut_a_bits_param),
.io_out_a_bits_size (nodeOut_a_bits_size),
.io_out_a_bits_source (nodeOut_a_bits_source),
.io_out_a_bits_address (_inclusive_cache_bank_sched_io_out_a_bits_address),
.io_out_a_bits_mask (nodeOut_a_bits_mask),
.io_out_a_bits_data (nodeOut_a_bits_data),
.io_out_a_bits_corrupt (nodeOut_a_bits_corrupt),
.io_out_c_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17]
.io_out_c_valid (nodeOut_c_valid),
.io_out_c_bits_opcode (nodeOut_c_bits_opcode),
.io_out_c_bits_param (nodeOut_c_bits_param),
.io_out_c_bits_size (nodeOut_c_bits_size),
.io_out_c_bits_source (nodeOut_c_bits_source),
.io_out_c_bits_address (_inclusive_cache_bank_sched_io_out_c_bits_address),
.io_out_c_bits_data (nodeOut_c_bits_data),
.io_out_c_bits_corrupt (nodeOut_c_bits_corrupt),
.io_out_d_ready (nodeOut_d_ready),
.io_out_d_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_out_d_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_out_d_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_out_d_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_out_d_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_out_d_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_out_d_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_out_d_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_out_d_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_out_e_valid (nodeOut_e_valid),
.io_out_e_bits_sink (nodeOut_e_bits_sink),
.io_req_ready (_inclusive_cache_bank_sched_io_req_ready),
.io_req_valid (_inclusive_cache_bank_sched_io_req_valid_T), // @[InclusiveCache.scala:172:41]
.io_req_bits_address (_ctrls_io_flush_req_bits[31:0]), // @[Parameters.scala:137:31]
.io_resp_valid (_inclusive_cache_bank_sched_io_resp_valid)
); // @[InclusiveCache.scala:137:29]
assign _nodeOut_a_bits_address_mux_matches_T = _inclusive_cache_bank_sched_io_out_a_bits_address; // @[Parameters.scala:137:31]
assign _nodeOut_a_bits_address_T = _inclusive_cache_bank_sched_io_out_a_bits_address; // @[Parameters.scala:248:14]
assign _nodeIn_b_bits_address_mux_matches_T = _inclusive_cache_bank_sched_io_in_b_bits_address; // @[Parameters.scala:137:31]
assign _nodeIn_b_bits_address_T = _inclusive_cache_bank_sched_io_in_b_bits_address; // @[Parameters.scala:248:14]
assign _nodeOut_c_bits_address_mux_matches_T = _inclusive_cache_bank_sched_io_out_c_bits_address; // @[Parameters.scala:137:31]
assign _nodeOut_c_bits_address_T = _inclusive_cache_bank_sched_io_out_c_bits_address; // @[Parameters.scala:248:14]
assign auto_ctrls_ctrl_in_a_ready = auto_ctrls_ctrl_in_a_ready_0; // @[InclusiveCache.scala:108:9]
assign auto_ctrls_ctrl_in_d_valid = auto_ctrls_ctrl_in_d_valid_0; // @[InclusiveCache.scala:108:9]
assign auto_ctrls_ctrl_in_d_bits_opcode = auto_ctrls_ctrl_in_d_bits_opcode_0; // @[InclusiveCache.scala:108:9]
assign auto_ctrls_ctrl_in_d_bits_size = auto_ctrls_ctrl_in_d_bits_size_0; // @[InclusiveCache.scala:108:9]
assign auto_ctrls_ctrl_in_d_bits_source = auto_ctrls_ctrl_in_d_bits_source_0; // @[InclusiveCache.scala:108:9]
assign auto_ctrls_ctrl_in_d_bits_data = auto_ctrls_ctrl_in_d_bits_data_0; // @[InclusiveCache.scala:108:9]
assign auto_in_a_ready = auto_in_a_ready_0; // @[InclusiveCache.scala:108:9]
assign auto_in_b_valid = auto_in_b_valid_0; // @[InclusiveCache.scala:108:9]
assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[InclusiveCache.scala:108:9]
assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[InclusiveCache.scala:108:9]
assign auto_in_c_ready = auto_in_c_ready_0; // @[InclusiveCache.scala:108:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[InclusiveCache.scala:108:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[InclusiveCache.scala:108:9]
assign auto_out_c_valid = auto_out_c_valid_0; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[InclusiveCache.scala:108:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[InclusiveCache.scala:108:9]
assign auto_out_e_valid = auto_out_e_valid_0; // @[InclusiveCache.scala:108:9]
assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[InclusiveCache.scala:108:9]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File SimpleHellaCacheIF.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Valid,Decoupled,Queue,log2Up,OHToUInt,UIntToOH,PriorityEncoderOH,Arbiter,RegEnable,Cat}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
/**
* This module buffers requests made by the SimpleHellaCacheIF in case they
* are nacked. Nacked requests must be replayed in order, and no other requests
* must be allowed to go through until the replayed requests are successfully
* completed.
*/
class SimpleHellaCacheIFReplayQueue(depth: Int)
(implicit val p: Parameters) extends Module
with HasL1HellaCacheParameters {
val io = IO(new Bundle {
val req = Flipped(Decoupled(new HellaCacheReq))
val nack = Flipped(Valid(Bits(coreParams.dcacheReqTagBits.W)))
val resp = Flipped(Valid(new HellaCacheResp))
val replay = Decoupled(new HellaCacheReq)
})
// Registers to store the sent request
// When a request is sent the first time,
// it is stored in one of the reqs registers
// and the corresponding inflight bit is set.
// The reqs register will be deallocated once the request is
// successfully completed.
val inflight = RegInit(0.U(depth.W))
val reqs = Reg(Vec(depth, new HellaCacheReq))
// The nack queue stores the index of nacked requests (in the reqs vector)
// in the order that they were nacked. A request is enqueued onto nackq
// when it is newly nacked (i.e. not a nack for a previous replay).
// The head of the nack queue will be replayed until it is
// successfully completed, at which time the request is dequeued.
// No new requests will be made or other replays attempted until the head
// of the nackq is successfully completed.
val nackq = Module(new Queue(UInt(log2Up(depth).W), depth))
val replaying = RegInit(false.B)
val next_inflight_onehot = PriorityEncoderOH(~inflight)
val next_inflight = OHToUInt(next_inflight_onehot)
val next_replay = nackq.io.deq.bits
val next_replay_onehot = UIntToOH(next_replay)
val next_replay_req = reqs(next_replay)
// Keep sending the head of the nack queue until it succeeds
io.replay.valid := nackq.io.deq.valid && !replaying
io.replay.bits := next_replay_req
// Don't allow new requests if there is are replays waiting
// or something being nacked.
io.req.ready := !inflight.andR && !nackq.io.deq.valid && !io.nack.valid
// Match on the tags to determine the index of nacks or responses
val nack_onehot = Cat(reqs.map(_.tag === io.nack.bits).reverse) & inflight
val resp_onehot = Cat(reqs.map(_.tag === io.resp.bits.tag).reverse) & inflight
val replay_complete = io.resp.valid && replaying && io.resp.bits.tag === next_replay_req.tag
val nack_head = io.nack.valid && nackq.io.deq.valid && io.nack.bits === next_replay_req.tag
// Enqueue to the nack queue if there is a nack that is not in response to
// the previous replay
nackq.io.enq.valid := io.nack.valid && !nack_head
nackq.io.enq.bits := OHToUInt(nack_onehot)
assert(!nackq.io.enq.valid || nackq.io.enq.ready,
"SimpleHellaCacheIF: ReplayQueue nack queue overflow")
// Dequeue from the nack queue if the last replay was successfully completed
nackq.io.deq.ready := replay_complete
assert(!nackq.io.deq.ready || nackq.io.deq.valid,
"SimpleHellaCacheIF: ReplayQueue nack queue underflow")
// Set inflight bit when a request is made
// Clear it when it is successfully completed
inflight := (inflight | Mux(io.req.fire, next_inflight_onehot, 0.U)) &
~Mux(io.resp.valid, resp_onehot, 0.U)
when (io.req.fire) {
reqs(next_inflight) := io.req.bits
}
// Only one replay outstanding at a time
when (io.replay.fire) { replaying := true.B }
when (nack_head || replay_complete) { replaying := false.B }
}
// exposes a sane decoupled request interface
class SimpleHellaCacheIF(implicit p: Parameters) extends Module
{
val io = IO(new Bundle {
val requestor = Flipped(new HellaCacheIO())
val cache = new HellaCacheIO
})
io <> DontCare
val replayq = Module(new SimpleHellaCacheIFReplayQueue(2))
val req_arb = Module(new Arbiter(new HellaCacheReq, 2))
val req_helper = DecoupledHelper(
req_arb.io.in(1).ready,
replayq.io.req.ready,
io.requestor.req.valid)
req_arb.io.in(0) <> replayq.io.replay
req_arb.io.in(1).valid := req_helper.fire(req_arb.io.in(1).ready)
req_arb.io.in(1).bits := io.requestor.req.bits
io.requestor.req.ready := req_helper.fire(io.requestor.req.valid)
replayq.io.req.valid := req_helper.fire(replayq.io.req.ready)
replayq.io.req.bits := io.requestor.req.bits
val s0_req_fire = io.cache.req.fire
val s1_req_fire = RegNext(s0_req_fire)
val s2_req_fire = RegNext(s1_req_fire)
val s1_req_tag = RegNext(io.cache.req.bits.tag)
val s2_req_tag = RegNext(s1_req_tag)
assert(!RegNext(io.cache.s2_nack) || !s2_req_fire || io.cache.s2_nack)
assert(!io.cache.s2_nack || !io.cache.req.ready)
io.cache.req <> req_arb.io.out
io.cache.s1_kill := false.B
io.cache.s1_data := RegEnable(req_arb.io.out.bits, s0_req_fire)
io.cache.s2_kill := false.B
replayq.io.nack.valid := io.cache.s2_nack && s2_req_fire
replayq.io.nack.bits := s2_req_tag
replayq.io.resp := io.cache.resp
io.requestor.resp := io.cache.resp
assert(!s2_req_fire || !io.cache.s2_xcpt.asUInt.orR, "SimpleHellaCacheIF exception")
}
|
module SimpleHellaCacheIF_3( // @[SimpleHellaCacheIF.scala:95:7]
input clock, // @[SimpleHellaCacheIF.scala:95:7]
input reset, // @[SimpleHellaCacheIF.scala:95:7]
output io_requestor_req_ready, // @[SimpleHellaCacheIF.scala:97:14]
input io_requestor_req_valid, // @[SimpleHellaCacheIF.scala:97:14]
input [39:0] io_requestor_req_bits_addr, // @[SimpleHellaCacheIF.scala:97:14]
input [7:0] io_requestor_req_bits_tag, // @[SimpleHellaCacheIF.scala:97:14]
input [1:0] io_requestor_req_bits_dprv, // @[SimpleHellaCacheIF.scala:97:14]
input io_requestor_req_bits_dv, // @[SimpleHellaCacheIF.scala:97:14]
output io_requestor_resp_valid, // @[SimpleHellaCacheIF.scala:97:14]
output [39:0] io_requestor_resp_bits_addr, // @[SimpleHellaCacheIF.scala:97:14]
output [7:0] io_requestor_resp_bits_tag, // @[SimpleHellaCacheIF.scala:97:14]
output [4:0] io_requestor_resp_bits_cmd, // @[SimpleHellaCacheIF.scala:97:14]
output [1:0] io_requestor_resp_bits_size, // @[SimpleHellaCacheIF.scala:97:14]
output io_requestor_resp_bits_signed, // @[SimpleHellaCacheIF.scala:97:14]
output [1:0] io_requestor_resp_bits_dprv, // @[SimpleHellaCacheIF.scala:97:14]
output io_requestor_resp_bits_dv, // @[SimpleHellaCacheIF.scala:97:14]
output [63:0] io_requestor_resp_bits_data, // @[SimpleHellaCacheIF.scala:97:14]
output [7:0] io_requestor_resp_bits_mask, // @[SimpleHellaCacheIF.scala:97:14]
output io_requestor_resp_bits_replay, // @[SimpleHellaCacheIF.scala:97:14]
output io_requestor_resp_bits_has_data, // @[SimpleHellaCacheIF.scala:97:14]
output [63:0] io_requestor_resp_bits_data_word_bypass, // @[SimpleHellaCacheIF.scala:97:14]
output [63:0] io_requestor_resp_bits_data_raw, // @[SimpleHellaCacheIF.scala:97:14]
output [63:0] io_requestor_resp_bits_store_data, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_req_ready, // @[SimpleHellaCacheIF.scala:97:14]
output io_cache_req_valid, // @[SimpleHellaCacheIF.scala:97:14]
output [39:0] io_cache_req_bits_addr, // @[SimpleHellaCacheIF.scala:97:14]
output [7:0] io_cache_req_bits_tag, // @[SimpleHellaCacheIF.scala:97:14]
output [1:0] io_cache_req_bits_dprv, // @[SimpleHellaCacheIF.scala:97:14]
output io_cache_req_bits_dv, // @[SimpleHellaCacheIF.scala:97:14]
output [63:0] io_cache_s1_data_data, // @[SimpleHellaCacheIF.scala:97:14]
output [7:0] io_cache_s1_data_mask, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_s2_nack, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_s2_nack_cause_raw, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_s2_uncached, // @[SimpleHellaCacheIF.scala:97:14]
input [31:0] io_cache_s2_paddr, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_resp_valid, // @[SimpleHellaCacheIF.scala:97:14]
input [39:0] io_cache_resp_bits_addr, // @[SimpleHellaCacheIF.scala:97:14]
input [7:0] io_cache_resp_bits_tag, // @[SimpleHellaCacheIF.scala:97:14]
input [4:0] io_cache_resp_bits_cmd, // @[SimpleHellaCacheIF.scala:97:14]
input [1:0] io_cache_resp_bits_size, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_resp_bits_signed, // @[SimpleHellaCacheIF.scala:97:14]
input [1:0] io_cache_resp_bits_dprv, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_resp_bits_dv, // @[SimpleHellaCacheIF.scala:97:14]
input [63:0] io_cache_resp_bits_data, // @[SimpleHellaCacheIF.scala:97:14]
input [7:0] io_cache_resp_bits_mask, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_resp_bits_replay, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_resp_bits_has_data, // @[SimpleHellaCacheIF.scala:97:14]
input [63:0] io_cache_resp_bits_data_word_bypass, // @[SimpleHellaCacheIF.scala:97:14]
input [63:0] io_cache_resp_bits_data_raw, // @[SimpleHellaCacheIF.scala:97:14]
input [63:0] io_cache_resp_bits_store_data, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_replay_next, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_s2_xcpt_ma_ld, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_s2_xcpt_ma_st, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_s2_xcpt_pf_ld, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_s2_xcpt_pf_st, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_s2_xcpt_ae_ld, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_s2_xcpt_ae_st, // @[SimpleHellaCacheIF.scala:97:14]
input [39:0] io_cache_s2_gpa, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_ordered, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_store_pending, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_perf_acquire, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_perf_release, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_perf_grant, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_perf_tlbMiss, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_perf_blocked, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_perf_canAcceptStoreThenLoad, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_perf_canAcceptStoreThenRMW, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_perf_canAcceptLoadThenLoad, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_perf_storeBufferEmptyAfterLoad, // @[SimpleHellaCacheIF.scala:97:14]
input io_cache_perf_storeBufferEmptyAfterStore // @[SimpleHellaCacheIF.scala:97:14]
);
wire _req_arb_io_in_0_ready; // @[SimpleHellaCacheIF.scala:104:23]
wire _req_arb_io_in_1_ready; // @[SimpleHellaCacheIF.scala:104:23]
wire [39:0] _req_arb_io_out_bits_addr; // @[SimpleHellaCacheIF.scala:104:23]
wire [7:0] _req_arb_io_out_bits_tag; // @[SimpleHellaCacheIF.scala:104:23]
wire [1:0] _req_arb_io_out_bits_dprv; // @[SimpleHellaCacheIF.scala:104:23]
wire _req_arb_io_out_bits_dv; // @[SimpleHellaCacheIF.scala:104:23]
wire _replayq_io_req_ready; // @[SimpleHellaCacheIF.scala:103:23]
wire _replayq_io_replay_valid; // @[SimpleHellaCacheIF.scala:103:23]
wire [39:0] _replayq_io_replay_bits_addr; // @[SimpleHellaCacheIF.scala:103:23]
wire [7:0] _replayq_io_replay_bits_tag; // @[SimpleHellaCacheIF.scala:103:23]
wire [1:0] _replayq_io_replay_bits_dprv; // @[SimpleHellaCacheIF.scala:103:23]
wire _replayq_io_replay_bits_dv; // @[SimpleHellaCacheIF.scala:103:23]
wire io_requestor_req_valid_0 = io_requestor_req_valid; // @[SimpleHellaCacheIF.scala:95:7]
wire [39:0] io_requestor_req_bits_addr_0 = io_requestor_req_bits_addr; // @[SimpleHellaCacheIF.scala:95:7]
wire [7:0] io_requestor_req_bits_tag_0 = io_requestor_req_bits_tag; // @[SimpleHellaCacheIF.scala:95:7]
wire [1:0] io_requestor_req_bits_dprv_0 = io_requestor_req_bits_dprv; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_req_bits_dv_0 = io_requestor_req_bits_dv; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_req_ready_0 = io_cache_req_ready; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_s2_nack_0 = io_cache_s2_nack; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_s2_nack_cause_raw_0 = io_cache_s2_nack_cause_raw; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_s2_uncached_0 = io_cache_s2_uncached; // @[SimpleHellaCacheIF.scala:95:7]
wire [31:0] io_cache_s2_paddr_0 = io_cache_s2_paddr; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_resp_valid_0 = io_cache_resp_valid; // @[SimpleHellaCacheIF.scala:95:7]
wire [39:0] io_cache_resp_bits_addr_0 = io_cache_resp_bits_addr; // @[SimpleHellaCacheIF.scala:95:7]
wire [7:0] io_cache_resp_bits_tag_0 = io_cache_resp_bits_tag; // @[SimpleHellaCacheIF.scala:95:7]
wire [4:0] io_cache_resp_bits_cmd_0 = io_cache_resp_bits_cmd; // @[SimpleHellaCacheIF.scala:95:7]
wire [1:0] io_cache_resp_bits_size_0 = io_cache_resp_bits_size; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_resp_bits_signed_0 = io_cache_resp_bits_signed; // @[SimpleHellaCacheIF.scala:95:7]
wire [1:0] io_cache_resp_bits_dprv_0 = io_cache_resp_bits_dprv; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_resp_bits_dv_0 = io_cache_resp_bits_dv; // @[SimpleHellaCacheIF.scala:95:7]
wire [63:0] io_cache_resp_bits_data_0 = io_cache_resp_bits_data; // @[SimpleHellaCacheIF.scala:95:7]
wire [7:0] io_cache_resp_bits_mask_0 = io_cache_resp_bits_mask; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_resp_bits_replay_0 = io_cache_resp_bits_replay; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_resp_bits_has_data_0 = io_cache_resp_bits_has_data; // @[SimpleHellaCacheIF.scala:95:7]
wire [63:0] io_cache_resp_bits_data_word_bypass_0 = io_cache_resp_bits_data_word_bypass; // @[SimpleHellaCacheIF.scala:95:7]
wire [63:0] io_cache_resp_bits_data_raw_0 = io_cache_resp_bits_data_raw; // @[SimpleHellaCacheIF.scala:95:7]
wire [63:0] io_cache_resp_bits_store_data_0 = io_cache_resp_bits_store_data; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_replay_next_0 = io_cache_replay_next; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_s2_xcpt_ma_ld_0 = io_cache_s2_xcpt_ma_ld; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_s2_xcpt_ma_st_0 = io_cache_s2_xcpt_ma_st; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_s2_xcpt_pf_ld_0 = io_cache_s2_xcpt_pf_ld; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_s2_xcpt_pf_st_0 = io_cache_s2_xcpt_pf_st; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_s2_xcpt_ae_ld_0 = io_cache_s2_xcpt_ae_ld; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_s2_xcpt_ae_st_0 = io_cache_s2_xcpt_ae_st; // @[SimpleHellaCacheIF.scala:95:7]
wire [39:0] io_cache_s2_gpa_0 = io_cache_s2_gpa; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_ordered_0 = io_cache_ordered; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_store_pending_0 = io_cache_store_pending; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_perf_acquire_0 = io_cache_perf_acquire; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_perf_release_0 = io_cache_perf_release; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_perf_grant_0 = io_cache_perf_grant; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_perf_tlbMiss_0 = io_cache_perf_tlbMiss; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_perf_blocked_0 = io_cache_perf_blocked; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_perf_canAcceptStoreThenLoad_0 = io_cache_perf_canAcceptStoreThenLoad; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_perf_canAcceptStoreThenRMW_0 = io_cache_perf_canAcceptStoreThenRMW; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_perf_canAcceptLoadThenLoad_0 = io_cache_perf_canAcceptLoadThenLoad; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_perf_storeBufferEmptyAfterLoad_0 = io_cache_perf_storeBufferEmptyAfterLoad; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_perf_storeBufferEmptyAfterStore_0 = io_cache_perf_storeBufferEmptyAfterStore; // @[SimpleHellaCacheIF.scala:95:7]
wire [4:0] io_requestor_req_bits_cmd = 5'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire [4:0] io_cache_req_bits_cmd = 5'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire [1:0] io_requestor_req_bits_size = 2'h3; // @[SimpleHellaCacheIF.scala:95:7]
wire [1:0] io_cache_req_bits_size = 2'h3; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_req_bits_signed = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_req_bits_phys = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_req_bits_no_resp = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_req_bits_no_alloc = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_req_bits_no_xcpt = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_s1_kill = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_s2_nack = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_s2_nack_cause_raw = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_s2_kill = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_s2_uncached = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_replay_next = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_s2_xcpt_ma_ld = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_s2_xcpt_ma_st = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_s2_xcpt_pf_ld = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_s2_xcpt_pf_st = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_s2_xcpt_gf_ld = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_s2_xcpt_gf_st = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_s2_xcpt_ae_ld = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_s2_xcpt_ae_st = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_s2_gpa_is_pte = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_ordered = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_store_pending = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_perf_acquire = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_perf_release = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_perf_grant = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_perf_tlbMiss = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_perf_blocked = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_perf_canAcceptStoreThenLoad = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_perf_canAcceptStoreThenRMW = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_perf_canAcceptLoadThenLoad = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_perf_storeBufferEmptyAfterLoad = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_perf_storeBufferEmptyAfterStore = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_keep_clock_enabled = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_clock_enabled = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_req_bits_signed = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_req_bits_phys = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_req_bits_no_resp = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_req_bits_no_alloc = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_req_bits_no_xcpt = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_s1_kill = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_s2_kill = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_s2_xcpt_gf_ld = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_s2_xcpt_gf_st = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_s2_gpa_is_pte = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_keep_clock_enabled = 1'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire [63:0] io_requestor_req_bits_data = 64'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire [63:0] io_requestor_s1_data_data = 64'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire [63:0] io_cache_req_bits_data = 64'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire [7:0] io_requestor_req_bits_mask = 8'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire [7:0] io_requestor_s1_data_mask = 8'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire [7:0] io_cache_req_bits_mask = 8'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_clock_enabled = 1'h1; // @[SimpleHellaCacheIF.scala:95:7]
wire [31:0] io_requestor_s2_paddr = 32'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire [39:0] io_requestor_s2_gpa = 40'h0; // @[SimpleHellaCacheIF.scala:95:7]
wire _io_requestor_req_ready_T; // @[Misc.scala:26:53]
wire io_requestor_resp_valid_0 = io_cache_resp_valid_0; // @[SimpleHellaCacheIF.scala:95:7]
wire [39:0] io_requestor_resp_bits_addr_0 = io_cache_resp_bits_addr_0; // @[SimpleHellaCacheIF.scala:95:7]
wire [7:0] io_requestor_resp_bits_tag_0 = io_cache_resp_bits_tag_0; // @[SimpleHellaCacheIF.scala:95:7]
wire [4:0] io_requestor_resp_bits_cmd_0 = io_cache_resp_bits_cmd_0; // @[SimpleHellaCacheIF.scala:95:7]
wire [1:0] io_requestor_resp_bits_size_0 = io_cache_resp_bits_size_0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_resp_bits_signed_0 = io_cache_resp_bits_signed_0; // @[SimpleHellaCacheIF.scala:95:7]
wire [1:0] io_requestor_resp_bits_dprv_0 = io_cache_resp_bits_dprv_0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_resp_bits_dv_0 = io_cache_resp_bits_dv_0; // @[SimpleHellaCacheIF.scala:95:7]
wire [63:0] io_requestor_resp_bits_data_0 = io_cache_resp_bits_data_0; // @[SimpleHellaCacheIF.scala:95:7]
wire [7:0] io_requestor_resp_bits_mask_0 = io_cache_resp_bits_mask_0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_resp_bits_replay_0 = io_cache_resp_bits_replay_0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_resp_bits_has_data_0 = io_cache_resp_bits_has_data_0; // @[SimpleHellaCacheIF.scala:95:7]
wire [63:0] io_requestor_resp_bits_data_word_bypass_0 = io_cache_resp_bits_data_word_bypass_0; // @[SimpleHellaCacheIF.scala:95:7]
wire [63:0] io_requestor_resp_bits_data_raw_0 = io_cache_resp_bits_data_raw_0; // @[SimpleHellaCacheIF.scala:95:7]
wire [63:0] io_requestor_resp_bits_store_data_0 = io_cache_resp_bits_store_data_0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_requestor_req_ready_0; // @[SimpleHellaCacheIF.scala:95:7]
wire [39:0] io_cache_req_bits_addr_0; // @[SimpleHellaCacheIF.scala:95:7]
wire [7:0] io_cache_req_bits_tag_0; // @[SimpleHellaCacheIF.scala:95:7]
wire [1:0] io_cache_req_bits_dprv_0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_req_bits_dv_0; // @[SimpleHellaCacheIF.scala:95:7]
wire io_cache_req_valid_0; // @[SimpleHellaCacheIF.scala:95:7]
wire [63:0] io_cache_s1_data_data_0; // @[SimpleHellaCacheIF.scala:95:7]
wire [7:0] io_cache_s1_data_mask_0; // @[SimpleHellaCacheIF.scala:95:7]
wire _req_arb_io_in_1_valid_T = _replayq_io_req_ready & io_requestor_req_valid_0; // @[Misc.scala:26:53]
assign _io_requestor_req_ready_T = _req_arb_io_in_1_ready & _replayq_io_req_ready; // @[Misc.scala:26:53]
assign io_requestor_req_ready_0 = _io_requestor_req_ready_T; // @[Misc.scala:26:53]
wire _replayq_io_req_valid_T = _req_arb_io_in_1_ready & io_requestor_req_valid_0; // @[Misc.scala:26:53]
wire s0_req_fire = io_cache_req_ready_0 & io_cache_req_valid_0; // @[Decoupled.scala:51:35]
reg s1_req_fire; // @[SimpleHellaCacheIF.scala:119:28]
reg s2_req_fire; // @[SimpleHellaCacheIF.scala:120:28]
reg [7:0] s1_req_tag; // @[SimpleHellaCacheIF.scala:121:27]
reg [7:0] s2_req_tag; // @[SimpleHellaCacheIF.scala:122:27]
reg REG; // @[SimpleHellaCacheIF.scala:124:18]
reg [39:0] io_cache_s1_data_r_addr; // @[SimpleHellaCacheIF.scala:129:32]
reg [7:0] io_cache_s1_data_r_tag; // @[SimpleHellaCacheIF.scala:129:32]
reg [4:0] io_cache_s1_data_r_cmd; // @[SimpleHellaCacheIF.scala:129:32]
reg [1:0] io_cache_s1_data_r_size; // @[SimpleHellaCacheIF.scala:129:32]
reg io_cache_s1_data_r_signed; // @[SimpleHellaCacheIF.scala:129:32]
reg [1:0] io_cache_s1_data_r_dprv; // @[SimpleHellaCacheIF.scala:129:32]
reg io_cache_s1_data_r_dv; // @[SimpleHellaCacheIF.scala:129:32]
reg io_cache_s1_data_r_phys; // @[SimpleHellaCacheIF.scala:129:32]
reg io_cache_s1_data_r_no_resp; // @[SimpleHellaCacheIF.scala:129:32]
reg io_cache_s1_data_r_no_alloc; // @[SimpleHellaCacheIF.scala:129:32]
reg io_cache_s1_data_r_no_xcpt; // @[SimpleHellaCacheIF.scala:129:32]
reg [63:0] io_cache_s1_data_r_data; // @[SimpleHellaCacheIF.scala:129:32]
assign io_cache_s1_data_data_0 = io_cache_s1_data_r_data; // @[SimpleHellaCacheIF.scala:95:7, :129:32]
reg [7:0] io_cache_s1_data_r_mask; // @[SimpleHellaCacheIF.scala:129:32]
assign io_cache_s1_data_mask_0 = io_cache_s1_data_r_mask; // @[SimpleHellaCacheIF.scala:95:7, :129:32]
wire _replayq_io_nack_valid_T = io_cache_s2_nack_0 & s2_req_fire; // @[SimpleHellaCacheIF.scala:95:7, :120:28, :132:45]
wire [3:0] lo = {2'h0, io_cache_s2_xcpt_ae_ld_0, io_cache_s2_xcpt_ae_st_0}; // @[SimpleHellaCacheIF.scala:95:7, :137:44]
wire [3:0] hi = {io_cache_s2_xcpt_ma_ld_0, io_cache_s2_xcpt_ma_st_0, io_cache_s2_xcpt_pf_ld_0, io_cache_s2_xcpt_pf_st_0}; // @[SimpleHellaCacheIF.scala:95:7, :137:44]
|
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
|
module MacUnit_237( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File IBuf.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Decoupled,log2Ceil,Cat,UIntToOH,Fill}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
class Instruction(implicit val p: Parameters) extends ParameterizedBundle with HasCoreParameters {
val xcpt0 = new FrontendExceptions // exceptions on first half of instruction
val xcpt1 = new FrontendExceptions // exceptions on second half of instruction
val replay = Bool()
val rvc = Bool()
val inst = new ExpandedInstruction
val raw = UInt(32.W)
require(coreInstBits == (if (usingCompressed) 16 else 32))
}
class IBuf(implicit p: Parameters) extends CoreModule {
val io = IO(new Bundle {
val imem = Flipped(Decoupled(new FrontendResp))
val kill = Input(Bool())
val pc = Output(UInt(vaddrBitsExtended.W))
val btb_resp = Output(new BTBResp())
val inst = Vec(retireWidth, Decoupled(new Instruction))
})
// This module is meant to be more general, but it's not there yet
require(decodeWidth == 1)
val n = fetchWidth - 1
val nBufValid = if (n == 0) 0.U else RegInit(init=0.U(log2Ceil(fetchWidth).W))
val buf = Reg(chiselTypeOf(io.imem.bits))
val ibufBTBResp = Reg(new BTBResp)
val pcWordMask = (coreInstBytes*fetchWidth-1).U(vaddrBitsExtended.W)
val pcWordBits = io.imem.bits.pc.extract(log2Ceil(fetchWidth*coreInstBytes)-1, log2Ceil(coreInstBytes))
val nReady = WireDefault(0.U(log2Ceil(fetchWidth+1).W))
val nIC = Mux(io.imem.bits.btb.taken, io.imem.bits.btb.bridx +& 1.U, fetchWidth.U) - pcWordBits
val nICReady = nReady - nBufValid
val nValid = Mux(io.imem.valid, nIC, 0.U) + nBufValid
io.imem.ready := io.inst(0).ready && nReady >= nBufValid && (nICReady >= nIC || n.U >= nIC - nICReady)
if (n > 0) {
when (io.inst(0).ready) {
nBufValid := Mux(nReady >== nBufValid, 0.U, nBufValid - nReady)
if (n > 1) when (nReady > 0.U && nReady < nBufValid) {
val shiftedBuf = shiftInsnRight(buf.data(n*coreInstBits-1, coreInstBits), (nReady-1.U)(log2Ceil(n-1)-1,0))
buf.data := Cat(buf.data(n*coreInstBits-1, (n-1)*coreInstBits), shiftedBuf((n-1)*coreInstBits-1, 0))
buf.pc := buf.pc & ~pcWordMask | (buf.pc + (nReady << log2Ceil(coreInstBytes))) & pcWordMask
}
when (io.imem.valid && nReady >= nBufValid && nICReady < nIC && n.U >= nIC - nICReady) {
val shamt = pcWordBits + nICReady
nBufValid := nIC - nICReady
buf := io.imem.bits
buf.data := shiftInsnRight(io.imem.bits.data, shamt)(n*coreInstBits-1,0)
buf.pc := io.imem.bits.pc & ~pcWordMask | (io.imem.bits.pc + (nICReady << log2Ceil(coreInstBytes))) & pcWordMask
ibufBTBResp := io.imem.bits.btb
}
}
when (io.kill) {
nBufValid := 0.U
}
}
val icShiftAmt = (fetchWidth.U + nBufValid - pcWordBits)(log2Ceil(fetchWidth), 0)
val icData = shiftInsnLeft(Cat(io.imem.bits.data, Fill(fetchWidth, io.imem.bits.data(coreInstBits-1, 0))), icShiftAmt)
.extract(3*fetchWidth*coreInstBits-1, 2*fetchWidth*coreInstBits)
val icMask = (~0.U((fetchWidth*coreInstBits).W) << (nBufValid << log2Ceil(coreInstBits)))(fetchWidth*coreInstBits-1,0)
val inst = icData & icMask | buf.data & ~icMask
val valid = (UIntToOH(nValid) - 1.U)(fetchWidth-1, 0)
val bufMask = UIntToOH(nBufValid) - 1.U
val xcpt = (0 until bufMask.getWidth).map(i => Mux(bufMask(i), buf.xcpt, io.imem.bits.xcpt))
val buf_replay = Mux(buf.replay, bufMask, 0.U)
val ic_replay = buf_replay | Mux(io.imem.bits.replay, valid & ~bufMask, 0.U)
assert(!io.imem.valid || !io.imem.bits.btb.taken || io.imem.bits.btb.bridx >= pcWordBits)
io.btb_resp := io.imem.bits.btb
io.pc := Mux(nBufValid > 0.U, buf.pc, io.imem.bits.pc)
expand(0, 0.U, inst)
def expand(i: Int, j: UInt, curInst: UInt): Unit = if (i < retireWidth) {
val exp = Module(new RVCExpander)
exp.io.in := curInst
io.inst(i).bits.inst := exp.io.out
io.inst(i).bits.raw := curInst
if (usingCompressed) {
val replay = ic_replay(j) || (!exp.io.rvc && ic_replay(j+1.U))
val full_insn = exp.io.rvc || valid(j+1.U) || buf_replay(j)
io.inst(i).valid := valid(j) && full_insn
io.inst(i).bits.xcpt0 := xcpt(j)
io.inst(i).bits.xcpt1 := Mux(exp.io.rvc, 0.U, xcpt(j+1.U).asUInt).asTypeOf(new FrontendExceptions)
io.inst(i).bits.replay := replay
io.inst(i).bits.rvc := exp.io.rvc
when ((bufMask(j) && exp.io.rvc) || bufMask(j+1.U)) { io.btb_resp := ibufBTBResp }
when (full_insn && ((i == 0).B || io.inst(i).ready)) { nReady := Mux(exp.io.rvc, j+1.U, j+2.U) }
expand(i+1, Mux(exp.io.rvc, j+1.U, j+2.U), Mux(exp.io.rvc, curInst >> 16, curInst >> 32))
} else {
when ((i == 0).B || io.inst(i).ready) { nReady := (i+1).U }
io.inst(i).valid := valid(i)
io.inst(i).bits.xcpt0 := xcpt(i)
io.inst(i).bits.xcpt1 := 0.U.asTypeOf(new FrontendExceptions)
io.inst(i).bits.replay := ic_replay(i)
io.inst(i).bits.rvc := false.B
expand(i+1, null, curInst >> 32)
}
}
def shiftInsnLeft(in: UInt, dist: UInt) = {
val r = in.getWidth/coreInstBits
require(in.getWidth % coreInstBits == 0)
val data = Cat(Fill((1 << (log2Ceil(r) + 1)) - r, in >> (r-1)*coreInstBits), in)
data << (dist << log2Ceil(coreInstBits))
}
def shiftInsnRight(in: UInt, dist: UInt) = {
val r = in.getWidth/coreInstBits
require(in.getWidth % coreInstBits == 0)
val data = Cat(Fill((1 << (log2Ceil(r) + 1)) - r, in >> (r-1)*coreInstBits), in)
data >> (dist << log2Ceil(coreInstBits))
}
}
|
module IBuf_4( // @[IBuf.scala:21:7]
input clock, // @[IBuf.scala:21:7]
input reset, // @[IBuf.scala:21:7]
output io_imem_ready, // @[IBuf.scala:22:14]
input io_imem_valid, // @[IBuf.scala:22:14]
input [1:0] io_imem_bits_btb_cfiType, // @[IBuf.scala:22:14]
input io_imem_bits_btb_taken, // @[IBuf.scala:22:14]
input [1:0] io_imem_bits_btb_mask, // @[IBuf.scala:22:14]
input io_imem_bits_btb_bridx, // @[IBuf.scala:22:14]
input [38:0] io_imem_bits_btb_target, // @[IBuf.scala:22:14]
input [4:0] io_imem_bits_btb_entry, // @[IBuf.scala:22:14]
input [7:0] io_imem_bits_btb_bht_history, // @[IBuf.scala:22:14]
input io_imem_bits_btb_bht_value, // @[IBuf.scala:22:14]
input [39:0] io_imem_bits_pc, // @[IBuf.scala:22:14]
input [31:0] io_imem_bits_data, // @[IBuf.scala:22:14]
input [1:0] io_imem_bits_mask, // @[IBuf.scala:22:14]
input io_imem_bits_xcpt_pf_inst, // @[IBuf.scala:22:14]
input io_imem_bits_xcpt_gf_inst, // @[IBuf.scala:22:14]
input io_imem_bits_xcpt_ae_inst, // @[IBuf.scala:22:14]
input io_imem_bits_replay, // @[IBuf.scala:22:14]
input io_kill, // @[IBuf.scala:22:14]
output [39:0] io_pc, // @[IBuf.scala:22:14]
output [1:0] io_btb_resp_cfiType, // @[IBuf.scala:22:14]
output io_btb_resp_taken, // @[IBuf.scala:22:14]
output [1:0] io_btb_resp_mask, // @[IBuf.scala:22:14]
output io_btb_resp_bridx, // @[IBuf.scala:22:14]
output [38:0] io_btb_resp_target, // @[IBuf.scala:22:14]
output [4:0] io_btb_resp_entry, // @[IBuf.scala:22:14]
output [7:0] io_btb_resp_bht_history, // @[IBuf.scala:22:14]
output io_btb_resp_bht_value, // @[IBuf.scala:22:14]
input io_inst_0_ready, // @[IBuf.scala:22:14]
output io_inst_0_valid, // @[IBuf.scala:22:14]
output io_inst_0_bits_xcpt0_pf_inst, // @[IBuf.scala:22:14]
output io_inst_0_bits_xcpt0_gf_inst, // @[IBuf.scala:22:14]
output io_inst_0_bits_xcpt0_ae_inst, // @[IBuf.scala:22:14]
output io_inst_0_bits_xcpt1_pf_inst, // @[IBuf.scala:22:14]
output io_inst_0_bits_xcpt1_gf_inst, // @[IBuf.scala:22:14]
output io_inst_0_bits_xcpt1_ae_inst, // @[IBuf.scala:22:14]
output io_inst_0_bits_replay, // @[IBuf.scala:22:14]
output io_inst_0_bits_rvc, // @[IBuf.scala:22:14]
output [31:0] io_inst_0_bits_inst_bits, // @[IBuf.scala:22:14]
output [4:0] io_inst_0_bits_inst_rd, // @[IBuf.scala:22:14]
output [4:0] io_inst_0_bits_inst_rs1, // @[IBuf.scala:22:14]
output [4:0] io_inst_0_bits_inst_rs2, // @[IBuf.scala:22:14]
output [4:0] io_inst_0_bits_inst_rs3, // @[IBuf.scala:22:14]
output [31:0] io_inst_0_bits_raw // @[IBuf.scala:22:14]
);
wire _exp_io_rvc; // @[IBuf.scala:86:21]
wire io_imem_valid_0 = io_imem_valid; // @[IBuf.scala:21:7]
wire [1:0] io_imem_bits_btb_cfiType_0 = io_imem_bits_btb_cfiType; // @[IBuf.scala:21:7]
wire io_imem_bits_btb_taken_0 = io_imem_bits_btb_taken; // @[IBuf.scala:21:7]
wire [1:0] io_imem_bits_btb_mask_0 = io_imem_bits_btb_mask; // @[IBuf.scala:21:7]
wire io_imem_bits_btb_bridx_0 = io_imem_bits_btb_bridx; // @[IBuf.scala:21:7]
wire [38:0] io_imem_bits_btb_target_0 = io_imem_bits_btb_target; // @[IBuf.scala:21:7]
wire [4:0] io_imem_bits_btb_entry_0 = io_imem_bits_btb_entry; // @[IBuf.scala:21:7]
wire [7:0] io_imem_bits_btb_bht_history_0 = io_imem_bits_btb_bht_history; // @[IBuf.scala:21:7]
wire io_imem_bits_btb_bht_value_0 = io_imem_bits_btb_bht_value; // @[IBuf.scala:21:7]
wire [39:0] io_imem_bits_pc_0 = io_imem_bits_pc; // @[IBuf.scala:21:7]
wire [31:0] io_imem_bits_data_0 = io_imem_bits_data; // @[IBuf.scala:21:7]
wire [1:0] io_imem_bits_mask_0 = io_imem_bits_mask; // @[IBuf.scala:21:7]
wire io_imem_bits_xcpt_pf_inst_0 = io_imem_bits_xcpt_pf_inst; // @[IBuf.scala:21:7]
wire io_imem_bits_xcpt_gf_inst_0 = io_imem_bits_xcpt_gf_inst; // @[IBuf.scala:21:7]
wire io_imem_bits_xcpt_ae_inst_0 = io_imem_bits_xcpt_ae_inst; // @[IBuf.scala:21:7]
wire io_imem_bits_replay_0 = io_imem_bits_replay; // @[IBuf.scala:21:7]
wire io_kill_0 = io_kill; // @[IBuf.scala:21:7]
wire io_inst_0_ready_0 = io_inst_0_ready; // @[IBuf.scala:21:7]
wire [1:0] _replay_T_3 = 2'h1; // @[IBuf.scala:92:63]
wire [1:0] _full_insn_T = 2'h1; // @[IBuf.scala:93:44]
wire [1:0] _io_inst_0_bits_xcpt1_T = 2'h1; // @[IBuf.scala:96:59]
wire [1:0] _nReady_T = 2'h1; // @[IBuf.scala:102:89]
wire [1:0] _nReady_T_3 = 2'h2; // @[IBuf.scala:102:96]
wire _replay_T_4 = 1'h1; // @[IBuf.scala:92:63]
wire _full_insn_T_1 = 1'h1; // @[IBuf.scala:93:44]
wire _io_inst_0_bits_xcpt1_T_1 = 1'h1; // @[IBuf.scala:96:59]
wire _io_inst_0_bits_xcpt1_T_2 = 1'h1; // @[package.scala:39:86]
wire _nReady_T_1 = 1'h1; // @[IBuf.scala:102:89]
wire _io_inst_0_bits_xcpt0_T = 1'h0; // @[package.scala:39:86]
wire [31:0] _icMask_T = 32'hFFFFFFFF; // @[IBuf.scala:71:17]
wire [39:0] _buf_pc_T = 40'hFFFFFFFFFC; // @[IBuf.scala:59:37]
wire [2:0] _nReady_T_2 = 3'h2; // @[IBuf.scala:102:96]
wire _io_imem_ready_T_7; // @[IBuf.scala:44:60]
wire [39:0] _io_pc_T_1; // @[IBuf.scala:82:15]
wire _io_inst_0_valid_T_2; // @[IBuf.scala:94:36]
wire _io_inst_0_bits_xcpt0_T_1_pf_inst; // @[package.scala:39:76]
wire _io_inst_0_bits_xcpt0_T_1_gf_inst; // @[package.scala:39:76]
wire _io_inst_0_bits_xcpt0_T_1_ae_inst; // @[package.scala:39:76]
wire _io_inst_0_bits_xcpt1_WIRE_pf_inst; // @[IBuf.scala:96:81]
wire _io_inst_0_bits_xcpt1_WIRE_gf_inst; // @[IBuf.scala:96:81]
wire _io_inst_0_bits_xcpt1_WIRE_ae_inst; // @[IBuf.scala:96:81]
wire replay; // @[IBuf.scala:92:33]
wire [31:0] inst; // @[IBuf.scala:72:30]
wire io_imem_ready_0; // @[IBuf.scala:21:7]
wire [7:0] io_btb_resp_bht_history_0; // @[IBuf.scala:21:7]
wire io_btb_resp_bht_value_0; // @[IBuf.scala:21:7]
wire [1:0] io_btb_resp_cfiType_0; // @[IBuf.scala:21:7]
wire io_btb_resp_taken_0; // @[IBuf.scala:21:7]
wire [1:0] io_btb_resp_mask_0; // @[IBuf.scala:21:7]
wire io_btb_resp_bridx_0; // @[IBuf.scala:21:7]
wire [38:0] io_btb_resp_target_0; // @[IBuf.scala:21:7]
wire [4:0] io_btb_resp_entry_0; // @[IBuf.scala:21:7]
wire io_inst_0_bits_xcpt0_pf_inst_0; // @[IBuf.scala:21:7]
wire io_inst_0_bits_xcpt0_gf_inst_0; // @[IBuf.scala:21:7]
wire io_inst_0_bits_xcpt0_ae_inst_0; // @[IBuf.scala:21:7]
wire io_inst_0_bits_xcpt1_pf_inst_0; // @[IBuf.scala:21:7]
wire io_inst_0_bits_xcpt1_gf_inst_0; // @[IBuf.scala:21:7]
wire io_inst_0_bits_xcpt1_ae_inst_0; // @[IBuf.scala:21:7]
wire [31:0] io_inst_0_bits_inst_bits_0; // @[IBuf.scala:21:7]
wire [4:0] io_inst_0_bits_inst_rd_0; // @[IBuf.scala:21:7]
wire [4:0] io_inst_0_bits_inst_rs1_0; // @[IBuf.scala:21:7]
wire [4:0] io_inst_0_bits_inst_rs2_0; // @[IBuf.scala:21:7]
wire [4:0] io_inst_0_bits_inst_rs3_0; // @[IBuf.scala:21:7]
wire io_inst_0_bits_replay_0; // @[IBuf.scala:21:7]
wire io_inst_0_bits_rvc_0; // @[IBuf.scala:21:7]
wire [31:0] io_inst_0_bits_raw_0; // @[IBuf.scala:21:7]
wire io_inst_0_valid_0; // @[IBuf.scala:21:7]
wire [39:0] io_pc_0; // @[IBuf.scala:21:7]
reg nBufValid; // @[IBuf.scala:34:47]
wire _io_pc_T = nBufValid; // @[IBuf.scala:34:47, :82:26]
reg [1:0] buf_btb_cfiType; // @[IBuf.scala:35:16]
reg buf_btb_taken; // @[IBuf.scala:35:16]
reg [1:0] buf_btb_mask; // @[IBuf.scala:35:16]
reg buf_btb_bridx; // @[IBuf.scala:35:16]
reg [38:0] buf_btb_target; // @[IBuf.scala:35:16]
reg [4:0] buf_btb_entry; // @[IBuf.scala:35:16]
reg [7:0] buf_btb_bht_history; // @[IBuf.scala:35:16]
reg buf_btb_bht_value; // @[IBuf.scala:35:16]
reg [39:0] buf_pc; // @[IBuf.scala:35:16]
reg [31:0] buf_data; // @[IBuf.scala:35:16]
reg [1:0] buf_mask; // @[IBuf.scala:35:16]
reg buf_xcpt_pf_inst; // @[IBuf.scala:35:16]
reg buf_xcpt_gf_inst; // @[IBuf.scala:35:16]
reg buf_xcpt_ae_inst; // @[IBuf.scala:35:16]
reg buf_replay; // @[IBuf.scala:35:16]
reg [1:0] ibufBTBResp_cfiType; // @[IBuf.scala:36:24]
reg ibufBTBResp_taken; // @[IBuf.scala:36:24]
reg [1:0] ibufBTBResp_mask; // @[IBuf.scala:36:24]
reg ibufBTBResp_bridx; // @[IBuf.scala:36:24]
reg [38:0] ibufBTBResp_target; // @[IBuf.scala:36:24]
reg [4:0] ibufBTBResp_entry; // @[IBuf.scala:36:24]
reg [7:0] ibufBTBResp_bht_history; // @[IBuf.scala:36:24]
reg ibufBTBResp_bht_value; // @[IBuf.scala:36:24]
wire pcWordBits = io_imem_bits_pc_0[1]; // @[package.scala:163:13]
wire [1:0] nReady; // @[IBuf.scala:40:27]
wire [1:0] _nIC_T = {1'h0, io_imem_bits_btb_bridx_0} + 2'h1; // @[IBuf.scala:21:7, :41:64]
wire [1:0] _nIC_T_1 = io_imem_bits_btb_taken_0 ? _nIC_T : 2'h2; // @[IBuf.scala:21:7, :41:{16,64}]
wire [2:0] _GEN = {2'h0, pcWordBits}; // @[package.scala:163:13]
wire [2:0] _nIC_T_2 = {1'h0, _nIC_T_1} - _GEN; // @[IBuf.scala:41:{16,86}]
wire [1:0] nIC = _nIC_T_2[1:0]; // @[IBuf.scala:41:86]
wire [2:0] _GEN_0 = {1'h0, nReady}; // @[IBuf.scala:40:27, :42:25]
wire [2:0] _GEN_1 = {2'h0, nBufValid}; // @[IBuf.scala:34:47, :42:25]
wire [2:0] _nICReady_T = _GEN_0 - _GEN_1; // @[IBuf.scala:42:25]
wire [1:0] nICReady = _nICReady_T[1:0]; // @[IBuf.scala:42:25]
wire [1:0] _nValid_T = io_imem_valid_0 ? nIC : 2'h0; // @[IBuf.scala:21:7, :41:86, :43:19]
wire [2:0] _nValid_T_1 = {1'h0, _nValid_T} + _GEN_1; // @[IBuf.scala:42:25, :43:{19,45}]
wire [1:0] nValid = _nValid_T_1[1:0]; // @[IBuf.scala:43:45]
wire [1:0] _GEN_2 = {1'h0, nBufValid}; // @[IBuf.scala:34:47, :44:47]
wire _T = nReady >= _GEN_2; // @[IBuf.scala:40:27, :44:47]
wire _io_imem_ready_T; // @[IBuf.scala:44:47]
assign _io_imem_ready_T = _T; // @[IBuf.scala:44:47]
wire _nBufValid_T; // @[package.scala:218:33]
assign _nBufValid_T = _T; // @[package.scala:218:33]
wire _io_imem_ready_T_1 = io_inst_0_ready_0 & _io_imem_ready_T; // @[IBuf.scala:21:7, :44:{37,47}]
wire _io_imem_ready_T_2 = nICReady >= nIC; // @[IBuf.scala:41:86, :42:25, :44:73]
wire [2:0] _GEN_3 = {1'h0, nICReady}; // @[IBuf.scala:42:25, :44:94]
wire [2:0] _T_4 = {1'h0, nIC} - _GEN_3; // @[IBuf.scala:41:86, :44:94]
wire [2:0] _io_imem_ready_T_3; // @[IBuf.scala:44:94]
assign _io_imem_ready_T_3 = _T_4; // @[IBuf.scala:44:94]
wire [2:0] _nBufValid_T_6; // @[IBuf.scala:56:26]
assign _nBufValid_T_6 = _T_4; // @[IBuf.scala:44:94, :56:26]
wire [1:0] _io_imem_ready_T_4 = _io_imem_ready_T_3[1:0]; // @[IBuf.scala:44:94]
wire _io_imem_ready_T_5 = ~(_io_imem_ready_T_4[1]); // @[IBuf.scala:44:{87,94}]
wire _io_imem_ready_T_6 = _io_imem_ready_T_2 | _io_imem_ready_T_5; // @[IBuf.scala:44:{73,80,87}]
assign _io_imem_ready_T_7 = _io_imem_ready_T_1 & _io_imem_ready_T_6; // @[IBuf.scala:44:{37,60,80}]
assign io_imem_ready_0 = _io_imem_ready_T_7; // @[IBuf.scala:21:7, :44:60]
wire _nBufValid_T_1 = ~nBufValid; // @[package.scala:218:43]
wire _nBufValid_T_2 = _nBufValid_T | _nBufValid_T_1; // @[package.scala:218:{33,38,43}]
wire [2:0] _nBufValid_T_3 = _GEN_1 - _GEN_0; // @[IBuf.scala:42:25, :48:61]
wire [1:0] _nBufValid_T_4 = _nBufValid_T_3[1:0]; // @[IBuf.scala:48:61]
wire [1:0] _nBufValid_T_5 = _nBufValid_T_2 ? 2'h0 : _nBufValid_T_4; // @[package.scala:218:38]
wire [2:0] _shamt_T = _GEN + _GEN_3; // @[IBuf.scala:41:86, :44:94, :55:32]
wire [1:0] shamt = _shamt_T[1:0]; // @[IBuf.scala:55:32]
wire [1:0] _nBufValid_T_7 = _nBufValid_T_6[1:0]; // @[IBuf.scala:56:26]
wire [15:0] _buf_data_data_T = io_imem_bits_data_0[31:16]; // @[IBuf.scala:21:7, :127:58]
wire [31:0] _buf_data_data_T_1 = {2{_buf_data_data_T}}; // @[IBuf.scala:127:{24,58}]
wire [63:0] buf_data_data = {_buf_data_data_T_1, io_imem_bits_data_0}; // @[IBuf.scala:21:7, :127:{19,24}]
wire [5:0] _buf_data_T = {shamt, 4'h0}; // @[IBuf.scala:55:32, :128:19]
wire [63:0] _buf_data_T_1 = buf_data_data >> _buf_data_T; // @[IBuf.scala:127:19, :128:{10,19}]
wire [15:0] _buf_data_T_2 = _buf_data_T_1[15:0]; // @[IBuf.scala:58:61, :128:10]
wire [39:0] _buf_pc_T_1 = io_imem_bits_pc_0 & 40'hFFFFFFFFFC; // @[IBuf.scala:21:7, :59:35]
wire [2:0] _buf_pc_T_2 = {nICReady, 1'h0}; // @[IBuf.scala:42:25, :59:80]
wire [40:0] _buf_pc_T_3 = {1'h0, io_imem_bits_pc_0} + {38'h0, _buf_pc_T_2}; // @[IBuf.scala:21:7, :59:{68,80}]
wire [39:0] _buf_pc_T_4 = _buf_pc_T_3[39:0]; // @[IBuf.scala:59:68]
wire [39:0] _buf_pc_T_5 = _buf_pc_T_4 & 40'h3; // @[IBuf.scala:59:{68,109}]
wire [39:0] _buf_pc_T_6 = _buf_pc_T_1 | _buf_pc_T_5; // @[IBuf.scala:59:{35,49,109}]
wire [2:0] _icShiftAmt_T = _GEN_1 + 3'h2; // @[IBuf.scala:42:25, :68:34]
wire [1:0] _icShiftAmt_T_1 = _icShiftAmt_T[1:0]; // @[IBuf.scala:68:34]
wire [2:0] _icShiftAmt_T_2 = {1'h0, _icShiftAmt_T_1} - _GEN; // @[IBuf.scala:41:86, :68:{34,46}]
wire [1:0] _icShiftAmt_T_3 = _icShiftAmt_T_2[1:0]; // @[IBuf.scala:68:46]
wire [1:0] icShiftAmt = _icShiftAmt_T_3; // @[IBuf.scala:68:{46,59}]
wire [15:0] _icData_T = io_imem_bits_data_0[15:0]; // @[IBuf.scala:21:7, :69:87]
wire [31:0] _icData_T_1 = {2{_icData_T}}; // @[IBuf.scala:69:{57,87}]
wire [63:0] _icData_T_2 = {io_imem_bits_data_0, _icData_T_1}; // @[IBuf.scala:21:7, :69:{33,57}]
wire [15:0] _icData_data_T = _icData_T_2[63:48]; // @[IBuf.scala:69:33, :120:58]
wire [31:0] _icData_data_T_1 = {2{_icData_data_T}}; // @[IBuf.scala:120:{24,58}]
wire [63:0] _icData_data_T_2 = {2{_icData_data_T_1}}; // @[IBuf.scala:120:24]
wire [127:0] icData_data = {_icData_data_T_2, _icData_T_2}; // @[IBuf.scala:69:33, :120:{19,24}]
wire [5:0] _icData_T_3 = {icShiftAmt, 4'h0}; // @[IBuf.scala:68:59, :121:19]
wire [190:0] _icData_T_4 = {63'h0, icData_data} << _icData_T_3; // @[IBuf.scala:120:19, :121:{10,19}]
wire [31:0] icData = _icData_T_4[95:64]; // @[package.scala:163:13]
wire [4:0] _icMask_T_1 = {nBufValid, 4'h0}; // @[IBuf.scala:34:47, :71:65]
wire [62:0] _icMask_T_2 = 63'hFFFFFFFF << _icMask_T_1; // @[IBuf.scala:71:{51,65}]
wire [31:0] icMask = _icMask_T_2[31:0]; // @[IBuf.scala:71:{51,92}]
wire [31:0] _inst_T = icData & icMask; // @[package.scala:163:13]
wire [31:0] _inst_T_1 = ~icMask; // @[IBuf.scala:71:92, :72:43]
wire [31:0] _inst_T_2 = buf_data & _inst_T_1; // @[IBuf.scala:35:16, :72:{41,43}]
assign inst = _inst_T | _inst_T_2; // @[IBuf.scala:72:{21,30,41}]
assign io_inst_0_bits_raw_0 = inst; // @[IBuf.scala:21:7, :72:30]
wire [3:0] _valid_T = 4'h1 << nValid; // @[OneHot.scala:58:35]
wire [4:0] _valid_T_1 = {1'h0, _valid_T} - 5'h1; // @[OneHot.scala:58:35]
wire [3:0] _valid_T_2 = _valid_T_1[3:0]; // @[IBuf.scala:74:33]
wire [1:0] valid = _valid_T_2[1:0]; // @[IBuf.scala:74:{33,39}]
wire [1:0] _io_inst_0_valid_T = valid; // @[IBuf.scala:74:39, :94:32]
wire [1:0] _bufMask_T = 2'h1 << _GEN_2; // @[OneHot.scala:58:35]
wire [2:0] _bufMask_T_1 = {1'h0, _bufMask_T} - 3'h1; // @[OneHot.scala:58:35]
wire [1:0] bufMask = _bufMask_T_1[1:0]; // @[IBuf.scala:75:37]
wire _xcpt_T = bufMask[0]; // @[IBuf.scala:75:37, :76:61]
wire xcpt_0_pf_inst = _xcpt_T ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}]
wire xcpt_0_gf_inst = _xcpt_T ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}]
wire xcpt_0_ae_inst = _xcpt_T ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}]
assign _io_inst_0_bits_xcpt0_T_1_pf_inst = xcpt_0_pf_inst; // @[package.scala:39:76]
assign _io_inst_0_bits_xcpt0_T_1_gf_inst = xcpt_0_gf_inst; // @[package.scala:39:76]
assign _io_inst_0_bits_xcpt0_T_1_ae_inst = xcpt_0_ae_inst; // @[package.scala:39:76]
wire _xcpt_T_1 = bufMask[1]; // @[IBuf.scala:75:37, :76:61]
wire xcpt_1_pf_inst = _xcpt_T_1 ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}]
wire xcpt_1_gf_inst = _xcpt_T_1 ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}]
wire xcpt_1_ae_inst = _xcpt_T_1 ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}]
wire _io_inst_0_bits_xcpt1_T_3_pf_inst = xcpt_1_pf_inst; // @[package.scala:39:76]
wire _io_inst_0_bits_xcpt1_T_3_gf_inst = xcpt_1_gf_inst; // @[package.scala:39:76]
wire _io_inst_0_bits_xcpt1_T_3_ae_inst = xcpt_1_ae_inst; // @[package.scala:39:76]
wire [1:0] buf_replay_0 = buf_replay ? bufMask : 2'h0; // @[IBuf.scala:35:16, :75:37, :77:23]
wire [1:0] _full_insn_T_5 = buf_replay_0; // @[IBuf.scala:77:23, :93:63]
wire [1:0] _ic_replay_T = ~bufMask; // @[IBuf.scala:75:37, :78:65]
wire [1:0] _ic_replay_T_1 = valid & _ic_replay_T; // @[IBuf.scala:74:39, :78:{63,65}]
wire [1:0] _ic_replay_T_2 = io_imem_bits_replay_0 ? _ic_replay_T_1 : 2'h0; // @[IBuf.scala:21:7, :78:{35,63}]
wire [1:0] ic_replay = buf_replay_0 | _ic_replay_T_2; // @[IBuf.scala:77:23, :78:{30,35}]
wire [1:0] _replay_T = ic_replay; // @[IBuf.scala:78:30, :92:29]
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLMonitor_51( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [11:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
|
module AsyncValidSync_81( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_81 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
|
module dataMems_394( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
|
module AsyncValidSync_20( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_32 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
|
module TLInterconnectCoupler_fbus_from_port_named_serial_tl_0_in( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
output auto_buffer_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_buffer_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_buffer_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_buffer_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_buffer_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_buffer_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_buffer_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_tl_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_buffer_in_a_valid_0 = auto_buffer_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_buffer_in_a_bits_opcode_0 = auto_buffer_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_buffer_in_a_bits_param_0 = auto_buffer_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_buffer_in_a_bits_size_0 = auto_buffer_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_buffer_in_a_bits_source_0 = auto_buffer_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_buffer_in_a_bits_address_0 = auto_buffer_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_buffer_in_a_bits_mask_0 = auto_buffer_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_buffer_in_a_bits_data_0 = auto_buffer_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_a_bits_corrupt_0 = auto_buffer_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_d_ready_0 = auto_buffer_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_a_ready_0 = auto_tl_out_a_ready; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_valid_0 = auto_tl_out_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_d_bits_opcode_0 = auto_tl_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_tl_out_d_bits_param_0 = auto_tl_out_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_tl_out_d_bits_size_0 = auto_tl_out_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_tl_out_d_bits_source_0 = auto_tl_out_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [6:0] auto_tl_out_d_bits_sink_0 = auto_tl_out_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_bits_denied_0 = auto_tl_out_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_out_d_bits_data_0 = auto_tl_out_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_bits_corrupt_0 = auto_tl_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire tlOut_a_ready = auto_tl_out_a_ready_0; // @[MixedNode.scala:542:17]
wire tlOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlOut_d_ready; // @[MixedNode.scala:542:17]
wire tlOut_d_valid = auto_tl_out_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_opcode = auto_tl_out_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] tlOut_d_bits_param = auto_tl_out_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] tlOut_d_bits_size = auto_tl_out_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [3:0] tlOut_d_bits_source = auto_tl_out_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [6:0] tlOut_d_bits_sink = auto_tl_out_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_denied = auto_tl_out_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_d_bits_data = auto_tl_out_d_bits_data_0; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_corrupt = auto_tl_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire auto_buffer_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_buffer_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_buffer_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_buffer_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_buffer_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [6:0] auto_buffer_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_buffer_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_tl_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_tl_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_tl_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
wire tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlIn_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_valid_0 = tlOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_opcode_0 = tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlIn_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_param_0 = tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlIn_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_size_0 = tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] tlIn_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_source_0 = tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlIn_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_address_0 = tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_mask_0 = tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlIn_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_data_0 = tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_corrupt_0 = tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_d_ready_0 = tlOut_d_ready; // @[MixedNode.scala:542:17]
wire tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlIn_d_bits_param = tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [6:0] tlIn_d_bits_sink = tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire tlIn_d_bits_denied = tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlIn_d_bits_corrupt = tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
TLBuffer_a32d64s4k7z4u buffer ( // @[Buffer.scala:75:28]
.clock (clock),
.reset (reset),
.auto_in_a_ready (auto_buffer_in_a_ready_0),
.auto_in_a_valid (auto_buffer_in_a_valid_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_opcode (auto_buffer_in_a_bits_opcode_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_param (auto_buffer_in_a_bits_param_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_size (auto_buffer_in_a_bits_size_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_source (auto_buffer_in_a_bits_source_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_address (auto_buffer_in_a_bits_address_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_mask (auto_buffer_in_a_bits_mask_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_data (auto_buffer_in_a_bits_data_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_corrupt (auto_buffer_in_a_bits_corrupt_0), // @[LazyModuleImp.scala:138:7]
.auto_in_d_ready (auto_buffer_in_d_ready_0), // @[LazyModuleImp.scala:138:7]
.auto_in_d_valid (auto_buffer_in_d_valid_0),
.auto_in_d_bits_opcode (auto_buffer_in_d_bits_opcode_0),
.auto_in_d_bits_param (auto_buffer_in_d_bits_param_0),
.auto_in_d_bits_size (auto_buffer_in_d_bits_size_0),
.auto_in_d_bits_source (auto_buffer_in_d_bits_source_0),
.auto_in_d_bits_sink (auto_buffer_in_d_bits_sink_0),
.auto_in_d_bits_denied (auto_buffer_in_d_bits_denied_0),
.auto_in_d_bits_data (auto_buffer_in_d_bits_data_0),
.auto_in_d_bits_corrupt (auto_buffer_in_d_bits_corrupt_0),
.auto_out_a_ready (tlIn_a_ready), // @[MixedNode.scala:551:17]
.auto_out_a_valid (tlIn_a_valid),
.auto_out_a_bits_opcode (tlIn_a_bits_opcode),
.auto_out_a_bits_param (tlIn_a_bits_param),
.auto_out_a_bits_size (tlIn_a_bits_size),
.auto_out_a_bits_source (tlIn_a_bits_source),
.auto_out_a_bits_address (tlIn_a_bits_address),
.auto_out_a_bits_mask (tlIn_a_bits_mask),
.auto_out_a_bits_data (tlIn_a_bits_data),
.auto_out_a_bits_corrupt (tlIn_a_bits_corrupt),
.auto_out_d_ready (tlIn_d_ready),
.auto_out_d_valid (tlIn_d_valid), // @[MixedNode.scala:551:17]
.auto_out_d_bits_opcode (tlIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_out_d_bits_param (tlIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_out_d_bits_size (tlIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_out_d_bits_source (tlIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_out_d_bits_sink (tlIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_out_d_bits_denied (tlIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_out_d_bits_data (tlIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_out_d_bits_corrupt (tlIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Buffer.scala:75:28]
assign auto_buffer_in_a_ready = auto_buffer_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_valid = auto_buffer_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_opcode = auto_buffer_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_param = auto_buffer_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_size = auto_buffer_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_source = auto_buffer_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_sink = auto_buffer_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_denied = auto_buffer_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_data = auto_buffer_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_corrupt = auto_buffer_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_valid = auto_tl_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_opcode = auto_tl_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_param = auto_tl_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_size = auto_tl_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_source = auto_tl_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_address = auto_tl_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_mask = auto_tl_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_data = auto_tl_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_corrupt = auto_tl_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_d_ready = auto_tl_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
|
module AsyncResetSynchronizerShiftReg_w4_d3_i0_24( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_230 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_231 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_232 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_233 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLMonitor_68( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7]
wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7]
wire [2:0] io_in_b_bits_opcode = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] io_in_b_bits_size = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] _mask_sizeOH_T_3 = 3'h0; // @[Misc.scala:202:34]
wire [2:0] b_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] b_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _b_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] b_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _b_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire io_in_b_valid = 1'h0; // @[Monitor.scala:36:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire _address_ok_T_4 = 1'h0; // @[Parameters.scala:137:59]
wire _address_ok_T_9 = 1'h0; // @[Parameters.scala:137:59]
wire _address_ok_WIRE_0 = 1'h0; // @[Parameters.scala:612:40]
wire _address_ok_WIRE_1 = 1'h0; // @[Parameters.scala:612:40]
wire address_ok = 1'h0; // @[Parameters.scala:636:64]
wire mask_sub_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:206:21]
wire mask_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire mask_sub_sub_bit_1 = 1'h0; // @[Misc.scala:210:26]
wire _mask_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:215:29]
wire mask_sub_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27]
wire _mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_sub_1_1_1 = 1'h0; // @[Misc.scala:215:29]
wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire mask_sub_bit_1 = 1'h0; // @[Misc.scala:210:26]
wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_0_1_1 = 1'h0; // @[Misc.scala:215:29]
wire mask_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27]
wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_1_1_1 = 1'h0; // @[Misc.scala:215:29]
wire mask_sub_2_2_1 = 1'h0; // @[Misc.scala:214:27]
wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_2_1_1 = 1'h0; // @[Misc.scala:215:29]
wire mask_sub_3_2_1 = 1'h0; // @[Misc.scala:214:27]
wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_3_1_1 = 1'h0; // @[Misc.scala:215:29]
wire mask_bit_1 = 1'h0; // @[Misc.scala:210:26]
wire mask_eq_9 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_9 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_9 = 1'h0; // @[Misc.scala:215:29]
wire mask_eq_10 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_10 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_10 = 1'h0; // @[Misc.scala:215:29]
wire mask_eq_11 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_11 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_11 = 1'h0; // @[Misc.scala:215:29]
wire mask_eq_12 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_12 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_12 = 1'h0; // @[Misc.scala:215:29]
wire mask_eq_13 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_13 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_13 = 1'h0; // @[Misc.scala:215:29]
wire mask_eq_14 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_14 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_14 = 1'h0; // @[Misc.scala:215:29]
wire mask_eq_15 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_15 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_15 = 1'h0; // @[Misc.scala:215:29]
wire _legal_source_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_12 = 1'h0; // @[Parameters.scala:54:10]
wire _b_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire _b_first_beats1_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire _b_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire b_first_done = 1'h0; // @[Edges.scala:233:22]
wire io_in_b_ready = 1'h1; // @[Monitor.scala:36:7]
wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire is_aligned_1 = 1'h1; // @[Edges.scala:21:24]
wire mask_sub_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20]
wire mask_sub_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27]
wire mask_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20]
wire mask_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27]
wire mask_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_nbit_1 = 1'h1; // @[Misc.scala:211:20]
wire mask_eq_8 = 1'h1; // @[Misc.scala:214:27]
wire _mask_acc_T_8 = 1'h1; // @[Misc.scala:215:38]
wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29]
wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _legal_source_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:56:48]
wire _legal_source_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire legal_source = 1'h1; // @[Monitor.scala:168:113]
wire _source_ok_T_13 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:54:67]
wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31]
wire b_first_beats1_opdata = 1'h1; // @[Edges.scala:97:28]
wire b_first = 1'h1; // @[Edges.scala:231:25]
wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire b_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] b_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _b_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [31:0] io_in_b_bits_address = 32'h0; // @[Monitor.scala:36:7]
wire [31:0] _is_aligned_T_1 = 32'h0; // @[Edges.scala:21:16]
wire [3:0] io_in_b_bits_source = 4'h0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_9 = 4'h0; // @[Parameters.scala:52:29]
wire [3:0] uncommonBits_9 = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] mask_hi_1 = 4'h0; // @[Misc.scala:222:10]
wire [3:0] _legal_source_uncommonBits_T = 4'h0; // @[Parameters.scala:52:29]
wire [3:0] legal_source_uncommonBits = 4'h0; // @[Parameters.scala:52:56]
wire [1:0] io_in_b_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h0; // @[OneHot.scala:64:49]
wire [1:0] mask_lo_hi_1 = 2'h0; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_1 = 2'h0; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_1 = 2'h0; // @[Misc.scala:222:10]
wire [7:0] io_in_b_bits_mask = 8'h0; // @[Monitor.scala:36:7]
wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] _mask_sizeOH_T_5 = 3'h1; // @[OneHot.scala:65:27]
wire [2:0] mask_sizeOH_1 = 3'h1; // @[Misc.scala:202:81]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [5:0] is_aligned_mask_1 = 6'h0; // @[package.scala:243:46]
wire [5:0] _b_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _is_aligned_mask_T_3 = 6'h3F; // @[package.scala:243:76]
wire [5:0] _b_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _is_aligned_mask_T_2 = 13'h3F; // @[package.scala:243:71]
wire [12:0] _b_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [7:0] mask_1 = 8'h1; // @[Misc.scala:222:10]
wire [3:0] _mask_sizeOH_T_4 = 4'h1; // @[OneHot.scala:65:12]
wire [3:0] mask_lo_1 = 4'h1; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_1 = 2'h1; // @[Misc.scala:222:10]
wire [32:0] _address_ok_T_6 = 33'h80000080; // @[Parameters.scala:137:41]
wire [32:0] _address_ok_T_7 = 33'h80000080; // @[Parameters.scala:137:46]
wire [32:0] _address_ok_T_8 = 33'h80000080; // @[Parameters.scala:137:46]
wire [31:0] _address_ok_T_5 = 32'h80000080; // @[Parameters.scala:137:31]
wire [32:0] _address_ok_T_1 = 33'h8000080; // @[Parameters.scala:137:41]
wire [32:0] _address_ok_T_2 = 33'h8000080; // @[Parameters.scala:137:46]
wire [32:0] _address_ok_T_3 = 33'h8000080; // @[Parameters.scala:137:46]
wire [31:0] _address_ok_T = 32'h8000080; // @[Parameters.scala:137:31]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_10 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_11 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_12 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_16 = source_ok_uncommonBits_2 < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_17 = _source_ok_T_16; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_2_0 = _source_ok_T_17; // @[Parameters.scala:1138:31]
wire [12:0] _GEN_0 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71]
assign _is_aligned_mask_T_4 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71]
assign _c_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _c_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46]
wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [27:0] _GEN_1 = io_in_c_bits_address_0[27:0] ^ 28'h8000080; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_1}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF01C0; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46]
wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000080; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F00001C0; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46]
wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40]
wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64]
wire [3:0] uncommonBits_10 = _uncommonBits_T_10; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_11 = _uncommonBits_T_11; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_12 = _uncommonBits_T_12; // @[Parameters.scala:52:{29,56}]
wire _T_1335 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1335; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1335; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1409 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1409; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1409; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1409; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _T_1409; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_2 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_2; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_2; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_2; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_9 = _GEN_2; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _T_1406 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35]
wire _c_first_T; // @[Decoupled.scala:51:35]
assign _c_first_T = _T_1406; // @[Decoupled.scala:51:35]
wire _c_first_T_1; // @[Decoupled.scala:51:35]
assign _c_first_T_1 = _T_1406; // @[Decoupled.scala:51:35]
wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [2:0] c_first_counter; // @[Edges.scala:229:27]
wire [3:0] _c_first_counter1_T = {1'h0, c_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] c_first_counter1 = _c_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire c_first = c_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T = c_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_1 = c_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [2:0] size_3; // @[Monitor.scala:517:22]
reg [3:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [9:0] a_set; // @[Monitor.scala:626:34]
wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [39:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_3 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_3; // @[Monitor.scala:637:69]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :641:65]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_3; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_3; // @[Monitor.scala:637:69, :681:99]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :750:67]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_3; // @[Monitor.scala:637:69, :790:101]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_3; // @[Monitor.scala:637:69, :791:99]
wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_4 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_1261 = _T_1335 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1261 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1261 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1261 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _GEN_5 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_5; // @[Monitor.scala:659:79]
wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_5; // @[Monitor.scala:659:79, :660:77]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1261 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1261 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [9:0] d_clr; // @[Monitor.scala:664:34]
wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_6 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_6; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_6; // @[Monitor.scala:673:46, :783:46]
wire _T_1307 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_7 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1307 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_1276 = _T_1409 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1276 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1276 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1276 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [2:0] c_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] c_first_counter1_1 = _c_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T_2 = c_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_3 = c_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [9:0] c_set; // @[Monitor.scala:738:34]
wire [9:0] c_set_wo_ready; // @[Monitor.scala:739:34]
wire [39:0] c_opcodes_set; // @[Monitor.scala:740:34]
wire [39:0] c_sizes_set; // @[Monitor.scala:741:34]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40]
wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44]
wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7]
wire [15:0] _GEN_8 = 16'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _c_set_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T; // @[OneHot.scala:58:35]
assign _c_set_T = _GEN_8; // @[OneHot.scala:58:35]
assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_1348 = _T_1406 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35]
assign c_set = _T_1348 ? _c_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53]
wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}]
assign c_opcodes_set_interm = _T_1348 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]
wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51]
wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}]
assign c_sizes_set_interm = _T_1348 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]
wire [6:0] _GEN_9 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79]
wire [6:0] _c_opcodes_set_T; // @[Monitor.scala:767:79]
assign _c_opcodes_set_T = _GEN_9; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T; // @[Monitor.scala:768:77]
assign _c_sizes_set_T = _GEN_9; // @[Monitor.scala:767:79, :768:77]
wire [130:0] _c_opcodes_set_T_1 = {127'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}]
assign c_opcodes_set = _T_1348 ? _c_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]
wire [130:0] _c_sizes_set_T_1 = {127'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}]
assign c_sizes_set = _T_1348 ? _c_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]
wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47]
wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95]
wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}]
wire [9:0] d_clr_1; // @[Monitor.scala:774:34]
wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1379 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1379 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_1361 = _T_1409 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1361 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1361 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1361 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}]
wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}]
wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}]
wire [9:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35]
wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43]
wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41]
wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26]
wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26]
reg [7:0] inflight_2; // @[Monitor.scala:828:27]
wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_3 = _d_first_counter1_T_3[2:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [7:0] d_set; // @[Monitor.scala:833:25]
wire _T_1415 = _T_1409 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35]
wire [7:0] _GEN_10 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _d_set_T = 8'h1 << _GEN_10; // @[OneHot.scala:58:35]
assign d_set = _T_1415 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35]
wire [7:0] e_clr; // @[Monitor.scala:839:25]
wire [7:0] _GEN_11 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _e_clr_T = 8'h1 << _GEN_11; // @[OneHot.scala:58:35]
assign e_clr = io_in_e_valid_0 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
|
module AsyncResetSynchronizerShiftReg_w1_d3_i0_75( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_115 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File loop.scala:
package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
import scala.math.min
case class BoomLoopPredictorParams(
nWays: Int = 4,
threshold: Int = 7
)
class LoopBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tagSz = 10
override val nSets = 16
class LoopMeta extends Bundle {
val s_cnt = UInt(10.W)
}
class LoopEntry extends Bundle {
val tag = UInt(tagSz.W)
val conf = UInt(3.W)
val age = UInt(3.W)
val p_cnt = UInt(10.W)
val s_cnt = UInt(10.W)
}
class LoopBranchPredictorColumn extends Module {
val io = IO(new Bundle {
val f2_req_valid = Input(Bool())
val f2_req_idx = Input(UInt())
val f3_req_fire = Input(Bool())
val f3_pred_in = Input(Bool())
val f3_pred = Output(Bool())
val f3_meta = Output(new LoopMeta)
val update_mispredict = Input(Bool())
val update_repair = Input(Bool())
val update_idx = Input(UInt())
val update_resolve_dir = Input(Bool())
val update_meta = Input(new LoopMeta)
})
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nSets).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nSets-1).U) { doing_reset := false.B }
val entries = Reg(Vec(nSets, new LoopEntry))
val f2_entry = WireInit(entries(io.f2_req_idx))
when (io.update_repair && io.update_idx === io.f2_req_idx) {
f2_entry.s_cnt := io.update_meta.s_cnt
} .elsewhen (io.update_mispredict && io.update_idx === io.f2_req_idx) {
f2_entry.s_cnt := 0.U
}
val f3_entry = RegNext(f2_entry)
val f3_scnt = Mux(io.update_repair && io.update_idx === RegNext(io.f2_req_idx),
io.update_meta.s_cnt,
f3_entry.s_cnt)
val f3_tag = RegNext(io.f2_req_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets)))
io.f3_pred := io.f3_pred_in
io.f3_meta.s_cnt := f3_scnt
when (f3_entry.tag === f3_tag) {
when (f3_scnt === f3_entry.p_cnt && f3_entry.conf === 7.U) {
io.f3_pred := !io.f3_pred_in
}
}
val f4_fire = RegNext(io.f3_req_fire)
val f4_entry = RegNext(f3_entry)
val f4_tag = RegNext(f3_tag)
val f4_scnt = RegNext(f3_scnt)
val f4_idx = RegNext(RegNext(io.f2_req_idx))
when (f4_fire) {
when (f4_entry.tag === f4_tag) {
when (f4_scnt === f4_entry.p_cnt && f4_entry.conf === 7.U) {
entries(f4_idx).age := 7.U
entries(f4_idx).s_cnt := 0.U
} .otherwise {
entries(f4_idx).s_cnt := f4_scnt + 1.U
entries(f4_idx).age := Mux(f4_entry.age === 7.U, 7.U, f4_entry.age + 1.U)
}
}
}
val entry = entries(io.update_idx)
val tag = io.update_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets))
val tag_match = entry.tag === tag
val ctr_match = entry.p_cnt === io.update_meta.s_cnt
val wentry = WireInit(entry)
when (io.update_mispredict && !doing_reset) {
// Learned, tag match -> decrement confidence
when (entry.conf === 7.U && tag_match) {
wentry.s_cnt := 0.U
wentry.conf := 0.U
// Learned, no tag match -> do nothing? Don't evict super-confident entries?
} .elsewhen (entry.conf === 7.U && !tag_match) {
// Confident, tag match, ctr_match -> increment confidence, reset counter
} .elsewhen (entry.conf =/= 0.U && tag_match && ctr_match) {
wentry.conf := entry.conf + 1.U
wentry.s_cnt := 0.U
// Confident, tag match, no ctr match -> zero confidence, reset counter, set previous counter
} .elsewhen (entry.conf =/= 0.U && tag_match && !ctr_match) {
wentry.conf := 0.U
wentry.s_cnt := 0.U
wentry.p_cnt := io.update_meta.s_cnt
// Confident, no tag match, age is 0 -> replace this entry with our own, set our age high to avoid ping-pong
} .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age === 0.U) {
wentry.tag := tag
wentry.conf := 1.U
wentry.s_cnt := 0.U
wentry.p_cnt := io.update_meta.s_cnt
// Confident, no tag match, age > 0 -> decrement age
} .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age =/= 0.U) {
wentry.age := entry.age - 1.U
// Unconfident, tag match, ctr match -> increment confidence
} .elsewhen (entry.conf === 0.U && tag_match && ctr_match) {
wentry.conf := 1.U
wentry.age := 7.U
wentry.s_cnt := 0.U
// Unconfident, tag match, no ctr match -> set previous counter
} .elsewhen (entry.conf === 0.U && tag_match && !ctr_match) {
wentry.p_cnt := io.update_meta.s_cnt
wentry.age := 7.U
wentry.s_cnt := 0.U
// Unconfident, no tag match -> set previous counter and tag
} .elsewhen (entry.conf === 0.U && !tag_match) {
wentry.tag := tag
wentry.conf := 1.U
wentry.age := 7.U
wentry.s_cnt := 0.U
wentry.p_cnt := io.update_meta.s_cnt
}
entries(io.update_idx) := wentry
} .elsewhen (io.update_repair && !doing_reset) {
when (tag_match && !(f4_fire && io.update_idx === f4_idx)) {
wentry.s_cnt := io.update_meta.s_cnt
entries(io.update_idx) := wentry
}
}
when (doing_reset) {
entries(reset_idx) := (0.U).asTypeOf(new LoopEntry)
}
}
val columns = Seq.fill(bankWidth) { Module(new LoopBranchPredictorColumn) }
val mems = Nil // TODO fix
val f3_meta = Wire(Vec(bankWidth, new LoopMeta))
override val metaSz = f3_meta.asUInt.getWidth
val update_meta = s1_update.bits.meta.asTypeOf(Vec(bankWidth, new LoopMeta))
for (w <- 0 until bankWidth) {
columns(w).io.f2_req_valid := s2_valid
columns(w).io.f2_req_idx := s2_idx
columns(w).io.f3_req_fire := (s3_valid && s3_mask(w) && io.f3_fire &&
RegNext(io.resp_in(0).f2(w).predicted_pc.valid && io.resp_in(0).f2(w).is_br))
columns(w).io.f3_pred_in := io.resp_in(0).f3(w).taken
io.resp.f3(w).taken := columns(w).io.f3_pred
columns(w).io.update_mispredict := (s1_update.valid &&
s1_update.bits.br_mask(w) &&
s1_update.bits.is_mispredict_update &&
s1_update.bits.cfi_mispredicted)
columns(w).io.update_repair := (s1_update.valid &&
s1_update.bits.br_mask(w) &&
s1_update.bits.is_repair_update)
columns(w).io.update_idx := s1_update_idx
columns(w).io.update_resolve_dir := s1_update.bits.cfi_taken
columns(w).io.update_meta := update_meta(w)
f3_meta(w) := columns(w).io.f3_meta
}
io.f3_meta := f3_meta.asUInt
}
|
module LoopBranchPredictorColumn_4( // @[loop.scala:39:9]
input clock, // @[loop.scala:39:9]
input reset, // @[loop.scala:39:9]
input io_f2_req_valid, // @[loop.scala:43:16]
input [35:0] io_f2_req_idx, // @[loop.scala:43:16]
input io_f3_req_fire, // @[loop.scala:43:16]
input io_f3_pred_in, // @[loop.scala:43:16]
output io_f3_pred, // @[loop.scala:43:16]
output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16]
input io_update_mispredict, // @[loop.scala:43:16]
input io_update_repair, // @[loop.scala:43:16]
input [35:0] io_update_idx, // @[loop.scala:43:16]
input io_update_resolve_dir, // @[loop.scala:43:16]
input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16]
);
wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9]
wire [35:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9]
wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9]
wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9]
wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9]
wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9]
wire [35:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9]
wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9]
wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9]
wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43]
wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43]
wire [35:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9]
wire [9:0] f3_scnt; // @[loop.scala:73:23]
wire [35:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9]
wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9]
wire io_f3_pred_0; // @[loop.scala:39:9]
reg doing_reset; // @[loop.scala:59:30]
reg [3:0] reset_idx; // @[loop.scala:60:28]
wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28]
wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28]
reg [9:0] entries_0_tag; // @[loop.scala:65:22]
reg [2:0] entries_0_conf; // @[loop.scala:65:22]
reg [2:0] entries_0_age; // @[loop.scala:65:22]
reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_1_tag; // @[loop.scala:65:22]
reg [2:0] entries_1_conf; // @[loop.scala:65:22]
reg [2:0] entries_1_age; // @[loop.scala:65:22]
reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_2_tag; // @[loop.scala:65:22]
reg [2:0] entries_2_conf; // @[loop.scala:65:22]
reg [2:0] entries_2_age; // @[loop.scala:65:22]
reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_3_tag; // @[loop.scala:65:22]
reg [2:0] entries_3_conf; // @[loop.scala:65:22]
reg [2:0] entries_3_age; // @[loop.scala:65:22]
reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_4_tag; // @[loop.scala:65:22]
reg [2:0] entries_4_conf; // @[loop.scala:65:22]
reg [2:0] entries_4_age; // @[loop.scala:65:22]
reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_5_tag; // @[loop.scala:65:22]
reg [2:0] entries_5_conf; // @[loop.scala:65:22]
reg [2:0] entries_5_age; // @[loop.scala:65:22]
reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_6_tag; // @[loop.scala:65:22]
reg [2:0] entries_6_conf; // @[loop.scala:65:22]
reg [2:0] entries_6_age; // @[loop.scala:65:22]
reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_7_tag; // @[loop.scala:65:22]
reg [2:0] entries_7_conf; // @[loop.scala:65:22]
reg [2:0] entries_7_age; // @[loop.scala:65:22]
reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_8_tag; // @[loop.scala:65:22]
reg [2:0] entries_8_conf; // @[loop.scala:65:22]
reg [2:0] entries_8_age; // @[loop.scala:65:22]
reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_9_tag; // @[loop.scala:65:22]
reg [2:0] entries_9_conf; // @[loop.scala:65:22]
reg [2:0] entries_9_age; // @[loop.scala:65:22]
reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_10_tag; // @[loop.scala:65:22]
reg [2:0] entries_10_conf; // @[loop.scala:65:22]
reg [2:0] entries_10_age; // @[loop.scala:65:22]
reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_11_tag; // @[loop.scala:65:22]
reg [2:0] entries_11_conf; // @[loop.scala:65:22]
reg [2:0] entries_11_age; // @[loop.scala:65:22]
reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_12_tag; // @[loop.scala:65:22]
reg [2:0] entries_12_conf; // @[loop.scala:65:22]
reg [2:0] entries_12_age; // @[loop.scala:65:22]
reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_13_tag; // @[loop.scala:65:22]
reg [2:0] entries_13_conf; // @[loop.scala:65:22]
reg [2:0] entries_13_age; // @[loop.scala:65:22]
reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_14_tag; // @[loop.scala:65:22]
reg [2:0] entries_14_conf; // @[loop.scala:65:22]
reg [2:0] entries_14_age; // @[loop.scala:65:22]
reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_15_tag; // @[loop.scala:65:22]
reg [2:0] entries_15_conf; // @[loop.scala:65:22]
reg [2:0] entries_15_age; // @[loop.scala:65:22]
reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22]
wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0];
wire [9:0] f2_entry_tag; // @[loop.scala:66:28]
wire [2:0] f2_entry_conf; // @[loop.scala:66:28]
wire [2:0] f2_entry_age; // @[loop.scala:66:28]
wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28]
wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28]
wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45]
assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22]
reg [9:0] f3_entry_tag; // @[loop.scala:72:27]
reg [2:0] f3_entry_conf; // @[loop.scala:72:27]
reg [2:0] f3_entry_age; // @[loop.scala:72:27]
reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27]
reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27]
reg [35:0] f3_scnt_REG; // @[loop.scala:73:69]
wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}]
wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}]
assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}]
assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23]
wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41]
reg [9:0] f3_tag; // @[loop.scala:76:27]
wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23]
assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}]
reg f4_fire; // @[loop.scala:88:27]
reg [9:0] f4_entry_tag; // @[loop.scala:89:27]
reg [2:0] f4_entry_conf; // @[loop.scala:89:27]
reg [2:0] f4_entry_age; // @[loop.scala:89:27]
reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27]
reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27]
reg [9:0] f4_tag; // @[loop.scala:90:27]
reg [9:0] f4_scnt; // @[loop.scala:91:27]
reg [35:0] f4_idx_REG; // @[loop.scala:92:35]
reg [35:0] f4_idx; // @[loop.scala:92:27]
wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44]
wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44]
wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53]
wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80]
wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80]
wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}]
wire [3:0] _entry_T_1 = _entry_T[3:0];
wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28]
wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31]
wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33]
wire [9:0] wentry_tag; // @[loop.scala:112:26]
wire [2:0] wentry_conf; // @[loop.scala:112:26]
wire [2:0] wentry_age; // @[loop.scala:112:26]
wire [9:0] wentry_p_cnt; // @[loop.scala:112:26]
wire [9:0] wentry_s_cnt; // @[loop.scala:112:26]
wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}]
wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}]
wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}]
wire _T_30 = (|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}]
wire [3:0] _wentry_conf_T = {1'h0, _GEN_0[_entry_T_1]} + 4'h1; // @[loop.scala:66:28, :102:80, :110:31, :126:36]
wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:126:36]
wire _T_34 = (|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}]
wire _T_39 = (|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}]
wire _T_44 = (|_GEN_0[_entry_T_1]) & ~tag_match & (|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}]
wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33]
wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33]
wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31]
wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}]
wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}]
wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39]
wire _GEN_4 = _T_47 | _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54]
wire _GEN_5 = _T_30 | _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75]
assign wentry_tag = ~_T_22 | _T_24 | _T_27 | _GEN_5 | ~(_T_39 | ~(_T_44 | _GEN_4 | ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}]
assign wentry_conf = _T_22 ? (_T_24 ? 3'h0 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_1 : _T_34 ? 3'h0 : _T_39 | ~(_T_44 | ~(_T_47 | ~(_T_51 | ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:22, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}]
wire _GEN_6 = _T_51 | _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22]
wire _GEN_7 = _T_34 | _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75]
assign wentry_age = ~_T_22 | _T_24 | _T_27 | _T_30 | _GEN_7 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 | _GEN_6 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22]
assign wentry_p_cnt = ~_T_22 | _T_24 | _T_27 | _T_30 | ~(_GEN_7 | ~(_T_44 | _T_47 | ~_GEN_6)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22]
wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35]
wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}]
assign wentry_s_cnt = _T_22 ? (_T_24 | ~(_T_27 | ~(_GEN_5 | _T_39 | ~(_T_44 | ~(_GEN_4 | _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22]
wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}]
wire _GEN_8 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68]
always @(posedge clock) begin // @[loop.scala:39:9]
if (reset) begin // @[loop.scala:39:9]
doing_reset <= 1'h1; // @[loop.scala:59:30]
reset_idx <= 4'h0; // @[loop.scala:60:28]
end
else begin // @[loop.scala:39:9]
doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}]
reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28]
end
if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_0_tag <= 10'h0; // @[loop.scala:65:22]
entries_0_conf <= 3'h0; // @[loop.scala:65:22]
entries_0_age <= 3'h0; // @[loop.scala:65:22]
entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33]
entries_0_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33]
entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33]
entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33]
entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26]
entries_1_tag <= 10'h0; // @[loop.scala:65:22]
entries_1_conf <= 3'h0; // @[loop.scala:65:22]
entries_1_age <= 3'h0; // @[loop.scala:65:22]
entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80]
entries_1_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80]
entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}]
entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80]
entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_2_tag <= 10'h0; // @[loop.scala:65:22]
entries_2_conf <= 3'h0; // @[loop.scala:65:22]
entries_2_age <= 3'h0; // @[loop.scala:65:22]
entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33]
entries_2_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33]
entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33]
entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33]
entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_3_tag <= 10'h0; // @[loop.scala:65:22]
entries_3_conf <= 3'h0; // @[loop.scala:65:22]
entries_3_age <= 3'h0; // @[loop.scala:65:22]
entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33]
entries_3_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33]
entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33]
entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33]
entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_4_tag <= 10'h0; // @[loop.scala:65:22]
entries_4_conf <= 3'h0; // @[loop.scala:65:22]
entries_4_age <= 3'h0; // @[loop.scala:65:22]
entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33]
entries_4_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33]
entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33]
entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33]
entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_5_tag <= 10'h0; // @[loop.scala:65:22]
entries_5_conf <= 3'h0; // @[loop.scala:65:22]
entries_5_age <= 3'h0; // @[loop.scala:65:22]
entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33]
entries_5_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33]
entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33]
entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33]
entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_6_tag <= 10'h0; // @[loop.scala:65:22]
entries_6_conf <= 3'h0; // @[loop.scala:65:22]
entries_6_age <= 3'h0; // @[loop.scala:65:22]
entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33]
entries_6_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33]
entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33]
entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33]
entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_7_tag <= 10'h0; // @[loop.scala:65:22]
entries_7_conf <= 3'h0; // @[loop.scala:65:22]
entries_7_age <= 3'h0; // @[loop.scala:65:22]
entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33]
entries_7_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33]
entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33]
entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33]
entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_8_tag <= 10'h0; // @[loop.scala:65:22]
entries_8_conf <= 3'h0; // @[loop.scala:65:22]
entries_8_age <= 3'h0; // @[loop.scala:65:22]
entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33]
entries_8_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33]
entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33]
entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33]
entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_9_tag <= 10'h0; // @[loop.scala:65:22]
entries_9_conf <= 3'h0; // @[loop.scala:65:22]
entries_9_age <= 3'h0; // @[loop.scala:65:22]
entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33]
entries_9_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33]
entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33]
entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33]
entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_10_tag <= 10'h0; // @[loop.scala:65:22]
entries_10_conf <= 3'h0; // @[loop.scala:65:22]
entries_10_age <= 3'h0; // @[loop.scala:65:22]
entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33]
entries_10_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33]
entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33]
entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33]
entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_11_tag <= 10'h0; // @[loop.scala:65:22]
entries_11_conf <= 3'h0; // @[loop.scala:65:22]
entries_11_age <= 3'h0; // @[loop.scala:65:22]
entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33]
entries_11_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33]
entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33]
entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33]
entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_12_tag <= 10'h0; // @[loop.scala:65:22]
entries_12_conf <= 3'h0; // @[loop.scala:65:22]
entries_12_age <= 3'h0; // @[loop.scala:65:22]
entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33]
entries_12_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33]
entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33]
entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33]
entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_13_tag <= 10'h0; // @[loop.scala:65:22]
entries_13_conf <= 3'h0; // @[loop.scala:65:22]
entries_13_age <= 3'h0; // @[loop.scala:65:22]
entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33]
entries_13_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33]
entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33]
entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33]
entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_14_tag <= 10'h0; // @[loop.scala:65:22]
entries_14_conf <= 3'h0; // @[loop.scala:65:22]
entries_14_age <= 3'h0; // @[loop.scala:65:22]
entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33]
entries_14_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33]
entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33]
entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33]
entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_15_tag <= 10'h0; // @[loop.scala:65:22]
entries_15_conf <= 3'h0; // @[loop.scala:65:22]
entries_15_age <= 3'h0; // @[loop.scala:65:22]
entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33]
entries_15_age <= 3'h7; // @[loop.scala:65:22]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33]
entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33]
entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33]
entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27]
f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27]
f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27]
f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27]
f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27]
f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69]
f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}]
f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27]
f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27]
f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27]
f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27]
f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27]
f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27]
f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27]
f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27]
f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35]
f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}]
always @(posedge)
assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9]
assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
|
module PlusArgTimeout_4( // @[PlusArg.scala:58:7]
input clock, // @[PlusArg.scala:58:7]
input reset, // @[PlusArg.scala:58:7]
input [31:0] io_count // @[PlusArg.scala:59:14]
);
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:62:19]
wire [31:0] io_count_0 = io_count; // @[PlusArg.scala:58:7]
|
Generate the Verilog code corresponding to the following Chisel files.
File tage.scala:
package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
}
|
module hi_us_15( // @[tage.scala:89:27]
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [6:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input [3:0] W0_mask
);
hi_us_ext hi_us_ext ( // @[tage.scala:89:27]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (1'h1), // @[tage.scala:89:27]
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
); // @[tage.scala:89:27]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
|
module AsyncValidSync_85( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_102 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLMonitor_24( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [515:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [255:0] _GEN_0 = {248'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [255:0] _GEN_3 = {248'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
|
module Tile_177( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_433 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File InputUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
import constellation.noc.{HasNoCParams}
class AbstractInputUnitIO(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams],
)(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val nodeId = cParam.destId
val router_req = Decoupled(new RouteComputerReq)
val router_resp = Input(new RouteComputerResp(outParams, egressParams))
val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams))
val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams))
val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))
val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams)))
val debug = Output(new Bundle {
val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
})
val block = Input(Bool())
}
abstract class AbstractInputUnit(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams {
val nodeId = cParam.destId
def io: AbstractInputUnitIO
}
class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module {
val nVirtualChannels = cParam.nVirtualChannels
val io = IO(new Bundle {
val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits))))
val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits)))
})
val useOutputQueues = cParam.useOutputQueues
val delims = if (useOutputQueues) {
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_)
} else {
// If no queuing, have to add an additional slot since head == tail implies empty
// TODO this should be fixed, should use all slots available
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_)
}
val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val ends = delims.tail.zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val fullSize = delims.last
// Ugly case. Use multiple queues
if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) {
require(useOutputQueues)
val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize)))
qs.zipWithIndex.foreach { case (q,i) =>
val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U)
q.io.enq.valid := sel.orR
q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head))
q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail))
q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload))
io.deq(i) <> q.io.deq
}
} else {
val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits))
val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val empty = (heads zip tails).map(t => t._1 === t._2)
val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) }
qs.foreach(_.io.enq.valid := false.B)
qs.foreach(_.io.enq.bits := DontCare)
val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id)
val flit = Wire(new BaseFlit(cParam.payloadBits))
val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B
flit.head := io.enq(0).bits.head
flit.tail := io.enq(0).bits.tail
flit.payload := io.enq(0).bits.payload
when (io.enq(0).valid && !direct_to_q) {
val tail = tails(io.enq(0).bits.virt_channel_id)
mem.write(tail, flit)
tails(io.enq(0).bits.virt_channel_id) := Mux(
tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(vc_sel, starts.map(_.U)),
tail + 1.U)
} .elsewhen (io.enq(0).valid && direct_to_q) {
for (i <- 0 until nVirtualChannels) {
when (io.enq(0).bits.virt_channel_id === i.U) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := flit
}
}
}
if (useOutputQueues) {
val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready }
val to_q_oh = PriorityEncoderOH(can_to_q)
val to_q = OHToUInt(to_q_oh)
when (can_to_q.orR) {
val head = Mux1H(to_q_oh, heads)
heads(to_q) := Mux(
head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(to_q_oh, starts.map(_.U)),
head + 1.U)
for (i <- 0 until nVirtualChannels) {
when (to_q_oh(i)) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := mem.read(head)
}
}
}
for (i <- 0 until nVirtualChannels) {
io.deq(i) <> qs(i).io.deq
}
} else {
qs.map(_.io.deq.ready := false.B)
val ready_sel = io.deq.map(_.ready)
val fire = io.deq.map(_.fire)
assert(PopCount(fire) <= 1.U)
val head = Mux1H(fire, heads)
when (fire.orR) {
val fire_idx = OHToUInt(fire)
heads(fire_idx) := Mux(
head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(fire, starts.map(_.U)),
head + 1.U)
}
val read_flit = mem.read(head)
for (i <- 0 until nVirtualChannels) {
io.deq(i).valid := !empty(i)
io.deq(i).bits := read_flit
}
}
}
}
class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean, combineSAST: Boolean
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
val nVirtualChannels = cParam.nVirtualChannels
val virtualChannelParams = cParam.virtualChannelParams
class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams]))
}
val io = IO(new InputUnitIO)
val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5)
class InputState extends Bundle {
val g = UInt(3.W)
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val flow = new FlowRoutingBundle
val fifo_deps = UInt(nVirtualChannels.W)
}
val input_buffer = Module(new InputBuffer(cParam))
for (i <- 0 until cParam.srcSpeedup) {
input_buffer.io.enq(i) := io.in.flit(i)
}
input_buffer.io.deq.foreach(_.ready := false.B)
val route_arbiter = Module(new Arbiter(
new RouteComputerReq, nVirtualChannels
))
io.router_req <> route_arbiter.io.out
val states = Reg(Vec(nVirtualChannels, new InputState))
val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_)
val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_)
if (anyFifo) {
val idle_mask = VecInit(states.map(_.g === g_i)).asUInt
for (s <- states)
for (i <- 0 until nVirtualChannels)
s.fifo_deps := s.fifo_deps & ~idle_mask
}
for (i <- 0 until cParam.srcSpeedup) {
when (io.in.flit(i).fire && io.in.flit(i).bits.head) {
val id = io.in.flit(i).bits.virt_channel_id
assert(id < nVirtualChannels.U)
assert(states(id).g === g_i)
val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U
states(id).g := Mux(at_dest, g_v, g_r)
states(id).vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (o.U === io.in.flit(i).bits.flow.egress_node_id) {
states(id).vc_sel(o+nOutputs)(0) := true.B
}
}
states(id).flow := io.in.flit(i).bits.flow
if (anyFifo) {
val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR
states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) =>
s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id
}).asUInt
}
}
}
(route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) =>
if (virtualChannelParams(idx).traversable) {
i.valid := s.g === g_r
i.bits.flow := s.flow
i.bits.src_virt_id := idx.U
when (i.fire) { s.g := g_v }
} else {
i.valid := false.B
i.bits := DontCare
}
}
when (io.router_req.fire) {
val id = io.router_req.bits.src_virt_id
assert(states(id).g === g_r)
states(id).g := g_v
for (i <- 0 until nVirtualChannels) {
when (i.U === id) {
states(i).vc_sel := io.router_resp.vc_sel
}
}
}
val mask = RegInit(0.U(nVirtualChannels.W))
val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams)))
val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool()))
val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask))
val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels)
// Prioritize incoming packetes
when (io.router_req.fire) {
mask := (1.U << io.router_req.bits.src_virt_id) - 1.U
} .elsewhen (vcalloc_vals.orR) {
mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) })
}
io.vcalloc_req.valid := vcalloc_vals.orR
io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs)
states.zipWithIndex.map { case (s,idx) =>
if (virtualChannelParams(idx).traversable) {
vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U
vcalloc_reqs(idx).in_vc := idx.U
vcalloc_reqs(idx).vc_sel := s.vc_sel
vcalloc_reqs(idx).flow := s.flow
when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a }
if (combineRCVA) {
when (route_arbiter.io.in(idx).fire) {
vcalloc_vals(idx) := true.B
vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel
}
}
} else {
vcalloc_vals(idx) := false.B
vcalloc_reqs(idx) := DontCare
}
}
io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready
when (io.vcalloc_req.fire) {
for (i <- 0 until nVirtualChannels) {
when (vcalloc_sel(i)) {
states(i).vc_sel := io.vcalloc_resp.vc_sel
states(i).g := g_a
if (!combineRCVA) {
assert(states(i).g === g_v)
}
}
}
}
val salloc_arb = Module(new SwitchArbiter(
nVirtualChannels,
cParam.destSpeedup,
outParams, egressParams
))
(states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) =>
if (virtualChannelParams(i).traversable) {
val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid
r.bits.vc_sel := s.vc_sel
val deq_tail = input_buffer.io.deq(i).bits.tail
r.bits.tail := deq_tail
when (r.fire && deq_tail) {
s.g := g_i
}
input_buffer.io.deq(i).ready := r.ready
} else {
r.valid := false.B
r.bits := DontCare
}
}
io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready))
io.salloc_req <> salloc_arb.io.out
when (io.block) {
salloc_arb.io.out.foreach(_.ready := false.B)
io.salloc_req.foreach(_.valid := false.B)
}
class OutBundle extends Bundle {
val valid = Bool()
val vid = UInt(virtualChannelBits.W)
val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W)
val flit = new Flit(cParam.payloadBits)
}
val salloc_outs = if (combineSAST) {
Wire(Vec(cParam.destSpeedup, new OutBundle))
} else {
Reg(Vec(cParam.destSpeedup, new OutBundle))
}
io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)),
salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
for (i <- 0 until cParam.destSpeedup) {
val salloc_out = salloc_outs(i)
salloc_out.valid := salloc_arb.io.out(i).fire
salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i))
val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel))
val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq
val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq)
when (salloc_arb.io.out(i).fire) {
salloc_out.out_vid := virt_channel
salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload))
salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head))
salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail))
salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow))
} .otherwise {
salloc_out.out_vid := DontCare
salloc_out.flit := DontCare
}
salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch
io.out(i).valid := salloc_out.valid
io.out(i).bits.flit := salloc_out.flit
io.out(i).bits.out_virt_channel := salloc_out.out_vid
}
def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = {
if (virtualChannelParams(srcV).traversable) {
outParams.zipWithIndex.map { case (oP, oI) =>
(0 until oP.nVirtualChannels).map { oV =>
var allow = false
virtualChannelParams(srcV).possibleFlows.foreach { pI =>
allow = allow || routingRelation(
cParam.channelRoutingInfos(srcV),
oP.channelRoutingInfos(oV),
pI
)
}
if (!allow)
sel(oI)(oV) := false.B
}
}
}
}
(0 until nVirtualChannels).map { i =>
if (!virtualChannelParams(i).traversable) states(i) := DontCare
filterVCSel(states(i).vc_sel, i)
}
when (reset.asBool) {
states.foreach(_.g := g_i)
}
}
|
module InputBuffer( // @[InputUnit.scala:49:7]
input clock, // @[InputUnit.scala:49:7]
input reset, // @[InputUnit.scala:49:7]
input io_enq_0_valid, // @[InputUnit.scala:51:14]
input io_enq_0_bits_head, // @[InputUnit.scala:51:14]
input io_enq_0_bits_tail, // @[InputUnit.scala:51:14]
input [72:0] io_enq_0_bits_payload, // @[InputUnit.scala:51:14]
input [3:0] io_enq_0_bits_virt_channel_id, // @[InputUnit.scala:51:14]
output io_deq_0_bits_head, // @[InputUnit.scala:51:14]
output io_deq_0_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_0_bits_payload, // @[InputUnit.scala:51:14]
output io_deq_1_bits_head, // @[InputUnit.scala:51:14]
output io_deq_1_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_1_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_2_ready, // @[InputUnit.scala:51:14]
output io_deq_2_valid, // @[InputUnit.scala:51:14]
output io_deq_2_bits_head, // @[InputUnit.scala:51:14]
output io_deq_2_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_2_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_3_ready, // @[InputUnit.scala:51:14]
output io_deq_3_valid, // @[InputUnit.scala:51:14]
output io_deq_3_bits_head, // @[InputUnit.scala:51:14]
output io_deq_3_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_3_bits_payload, // @[InputUnit.scala:51:14]
output io_deq_4_bits_head, // @[InputUnit.scala:51:14]
output io_deq_4_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_4_bits_payload, // @[InputUnit.scala:51:14]
output io_deq_5_bits_head, // @[InputUnit.scala:51:14]
output io_deq_5_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_5_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_6_ready, // @[InputUnit.scala:51:14]
output io_deq_6_valid, // @[InputUnit.scala:51:14]
output io_deq_6_bits_head, // @[InputUnit.scala:51:14]
output io_deq_6_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_6_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_7_ready, // @[InputUnit.scala:51:14]
output io_deq_7_valid, // @[InputUnit.scala:51:14]
output io_deq_7_bits_head, // @[InputUnit.scala:51:14]
output io_deq_7_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_7_bits_payload, // @[InputUnit.scala:51:14]
output io_deq_8_bits_head, // @[InputUnit.scala:51:14]
output io_deq_8_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_8_bits_payload, // @[InputUnit.scala:51:14]
output io_deq_9_bits_head, // @[InputUnit.scala:51:14]
output io_deq_9_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_9_bits_payload // @[InputUnit.scala:51:14]
);
wire _qs_9_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_8_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_7_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_6_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_5_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_4_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_3_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_2_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_1_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_0_io_enq_ready; // @[InputUnit.scala:90:49]
wire [74:0] _mem_ext_R0_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R1_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R2_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R3_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R4_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R5_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R6_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R7_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R8_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R9_data; // @[InputUnit.scala:85:18]
reg [3:0] heads_0; // @[InputUnit.scala:86:24]
reg [3:0] heads_1; // @[InputUnit.scala:86:24]
reg [3:0] heads_2; // @[InputUnit.scala:86:24]
reg [3:0] heads_3; // @[InputUnit.scala:86:24]
reg [3:0] heads_4; // @[InputUnit.scala:86:24]
reg [3:0] heads_5; // @[InputUnit.scala:86:24]
reg [3:0] heads_6; // @[InputUnit.scala:86:24]
reg [3:0] heads_7; // @[InputUnit.scala:86:24]
reg [3:0] heads_8; // @[InputUnit.scala:86:24]
reg [3:0] heads_9; // @[InputUnit.scala:86:24]
reg [3:0] tails_0; // @[InputUnit.scala:87:24]
reg [3:0] tails_1; // @[InputUnit.scala:87:24]
reg [3:0] tails_2; // @[InputUnit.scala:87:24]
reg [3:0] tails_3; // @[InputUnit.scala:87:24]
reg [3:0] tails_4; // @[InputUnit.scala:87:24]
reg [3:0] tails_5; // @[InputUnit.scala:87:24]
reg [3:0] tails_6; // @[InputUnit.scala:87:24]
reg [3:0] tails_7; // @[InputUnit.scala:87:24]
reg [3:0] tails_8; // @[InputUnit.scala:87:24]
reg [3:0] tails_9; // @[InputUnit.scala:87:24]
wire _tails_T_30 = io_enq_0_bits_virt_channel_id == 4'h0; // @[Mux.scala:32:36]
wire _tails_T_31 = io_enq_0_bits_virt_channel_id == 4'h1; // @[Mux.scala:32:36]
wire _tails_T_32 = io_enq_0_bits_virt_channel_id == 4'h2; // @[Mux.scala:32:36]
wire _tails_T_33 = io_enq_0_bits_virt_channel_id == 4'h3; // @[Mux.scala:32:36]
wire _tails_T_34 = io_enq_0_bits_virt_channel_id == 4'h4; // @[Mux.scala:32:36]
wire _tails_T_35 = io_enq_0_bits_virt_channel_id == 4'h5; // @[Mux.scala:32:36]
wire _tails_T_36 = io_enq_0_bits_virt_channel_id == 4'h6; // @[Mux.scala:32:36]
wire _tails_T_37 = io_enq_0_bits_virt_channel_id == 4'h7; // @[Mux.scala:32:36]
wire _tails_T_38 = io_enq_0_bits_virt_channel_id == 4'h8; // @[Mux.scala:32:36]
wire _tails_T_39 = io_enq_0_bits_virt_channel_id == 4'h9; // @[Mux.scala:32:36]
wire direct_to_q = (_tails_T_30 & _qs_0_io_enq_ready | _tails_T_31 & _qs_1_io_enq_ready | _tails_T_32 & _qs_2_io_enq_ready | _tails_T_33 & _qs_3_io_enq_ready | _tails_T_34 & _qs_4_io_enq_ready | _tails_T_35 & _qs_5_io_enq_ready | _tails_T_36 & _qs_6_io_enq_ready | _tails_T_37 & _qs_7_io_enq_ready | _tails_T_38 & _qs_8_io_enq_ready | _tails_T_39 & _qs_9_io_enq_ready) & (_tails_T_30 & heads_0 == tails_0 | _tails_T_31 & heads_1 == tails_1 | _tails_T_32 & heads_2 == tails_2 | _tails_T_33 & heads_3 == tails_3 | _tails_T_34 & heads_4 == tails_4 | _tails_T_35 & heads_5 == tails_5 | _tails_T_36 & heads_6 == tails_6 | _tails_T_37 & heads_7 == tails_7 | _tails_T_38 & heads_8 == tails_8 | _tails_T_39 & heads_9 == tails_9); // @[Mux.scala:30:73, :32:36]
wire mem_MPORT_en = io_enq_0_valid & ~direct_to_q; // @[InputUnit.scala:96:62, :100:{27,30}]
wire [15:0][3:0] _GEN = {{tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_9}, {tails_8}, {tails_7}, {tails_6}, {tails_5}, {tails_4}, {tails_3}, {tails_2}, {tails_1}, {tails_0}}; // @[InputUnit.scala:87:24, :102:16]
wire _GEN_0 = io_enq_0_bits_virt_channel_id == 4'h0; // @[InputUnit.scala:103:45]
wire _GEN_1 = io_enq_0_bits_virt_channel_id == 4'h1; // @[InputUnit.scala:103:45]
wire _GEN_2 = io_enq_0_bits_virt_channel_id == 4'h2; // @[InputUnit.scala:103:45]
wire _GEN_3 = io_enq_0_bits_virt_channel_id == 4'h3; // @[InputUnit.scala:103:45]
wire _GEN_4 = io_enq_0_bits_virt_channel_id == 4'h4; // @[InputUnit.scala:103:45]
wire _GEN_5 = io_enq_0_bits_virt_channel_id == 4'h5; // @[InputUnit.scala:103:45]
wire _GEN_6 = io_enq_0_bits_virt_channel_id == 4'h6; // @[InputUnit.scala:103:45]
wire _GEN_7 = io_enq_0_bits_virt_channel_id == 4'h7; // @[InputUnit.scala:103:45]
wire _GEN_8 = io_enq_0_bits_virt_channel_id == 4'h8; // @[InputUnit.scala:103:45]
wire _GEN_9 = io_enq_0_bits_virt_channel_id == 4'h9; // @[InputUnit.scala:103:45]
wire _GEN_10 = io_enq_0_valid & direct_to_q; // @[InputUnit.scala:96:62, :107:34]
wire can_to_q_0 = heads_0 != tails_0 & _qs_0_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_1 = heads_1 != tails_1 & _qs_1_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_2 = heads_2 != tails_2 & _qs_2_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_3 = heads_3 != tails_3 & _qs_3_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_4 = heads_4 != tails_4 & _qs_4_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_5 = heads_5 != tails_5 & _qs_5_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_6 = heads_6 != tails_6 & _qs_6_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_7 = heads_7 != tails_7 & _qs_7_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_8 = heads_8 != tails_8 & _qs_8_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_9 = heads_9 != tails_9 & _qs_9_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire [9:0] to_q_oh_enc = can_to_q_0 ? 10'h1 : can_to_q_1 ? 10'h2 : can_to_q_2 ? 10'h4 : can_to_q_3 ? 10'h8 : can_to_q_4 ? 10'h10 : can_to_q_5 ? 10'h20 : can_to_q_6 ? 10'h40 : can_to_q_7 ? 10'h80 : can_to_q_8 ? 10'h100 : {can_to_q_9, 9'h0}; // @[Mux.scala:50:70]
wire _GEN_11 = can_to_q_0 | can_to_q_1 | can_to_q_2 | can_to_q_3 | can_to_q_4 | can_to_q_5 | can_to_q_6 | can_to_q_7 | can_to_q_8 | can_to_q_9; // @[package.scala:81:59]
wire [3:0] head = (to_q_oh_enc[0] ? heads_0 : 4'h0) | (to_q_oh_enc[1] ? heads_1 : 4'h0) | (to_q_oh_enc[2] ? heads_2 : 4'h0) | (to_q_oh_enc[3] ? heads_3 : 4'h0) | (to_q_oh_enc[4] ? heads_4 : 4'h0) | (to_q_oh_enc[5] ? heads_5 : 4'h0) | (to_q_oh_enc[6] ? heads_6 : 4'h0) | (to_q_oh_enc[7] ? heads_7 : 4'h0) | (to_q_oh_enc[8] ? heads_8 : 4'h0) | (to_q_oh_enc[9] ? heads_9 : 4'h0); // @[OneHot.scala:83:30]
wire _GEN_12 = _GEN_11 & to_q_oh_enc[0]; // @[OneHot.scala:83:30]
wire _GEN_13 = _GEN_11 & to_q_oh_enc[1]; // @[OneHot.scala:83:30]
wire _GEN_14 = _GEN_11 & to_q_oh_enc[2]; // @[OneHot.scala:83:30]
wire _GEN_15 = _GEN_11 & to_q_oh_enc[3]; // @[OneHot.scala:83:30]
wire _GEN_16 = _GEN_11 & to_q_oh_enc[4]; // @[OneHot.scala:83:30]
wire _GEN_17 = _GEN_11 & to_q_oh_enc[5]; // @[OneHot.scala:83:30]
wire _GEN_18 = _GEN_11 & to_q_oh_enc[6]; // @[OneHot.scala:83:30]
wire _GEN_19 = _GEN_11 & to_q_oh_enc[7]; // @[OneHot.scala:83:30]
wire _GEN_20 = _GEN_11 & to_q_oh_enc[8]; // @[OneHot.scala:83:30]
wire _GEN_21 = _GEN_11 & to_q_oh_enc[9]; // @[OneHot.scala:83:30]
wire [3:0] _tails_T_61 = _GEN[io_enq_0_bits_virt_channel_id] == ({1'h0, {1'h0, {2{_tails_T_32}}} | {3{_tails_T_33}}} | (_tails_T_36 ? 4'hB : 4'h0) | {4{_tails_T_37}}) ? {_tails_T_36, _tails_T_33, 2'h0} | (_tails_T_37 ? 4'hC : 4'h0) : _GEN[io_enq_0_bits_virt_channel_id] + 4'h1; // @[Mux.scala:30:73, :32:36]
wire [6:0] _to_q_T_2 = {6'h0, to_q_oh_enc[9]} | to_q_oh_enc[7:1]; // @[OneHot.scala:31:18, :32:28]
wire [2:0] _to_q_T_4 = _to_q_T_2[6:4] | _to_q_T_2[2:0]; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _to_q_T_6 = _to_q_T_4[2] | _to_q_T_4[0]; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] to_q = {|(to_q_oh_enc[9:8]), |(_to_q_T_2[6:3]), |(_to_q_T_4[2:1]), _to_q_T_6}; // @[OneHot.scala:30:18, :32:{10,14,28}]
wire [3:0] _heads_T_41 = head == ({1'h0, {1'h0, {2{to_q_oh_enc[2]}}} | {3{to_q_oh_enc[3]}}} | (to_q_oh_enc[6] ? 4'hB : 4'h0) | {4{to_q_oh_enc[7]}}) ? {to_q_oh_enc[6], to_q_oh_enc[3], 2'h0} | (to_q_oh_enc[7] ? 4'hC : 4'h0) : head + 4'h1; // @[OneHot.scala:83:30]
always @(posedge clock) begin // @[InputUnit.scala:49:7]
if (reset) begin // @[InputUnit.scala:49:7]
heads_0 <= 4'h0; // @[InputUnit.scala:86:24]
heads_1 <= 4'h0; // @[InputUnit.scala:86:24]
heads_2 <= 4'h0; // @[InputUnit.scala:86:24]
heads_3 <= 4'h4; // @[InputUnit.scala:86:24]
heads_4 <= 4'h0; // @[InputUnit.scala:86:24]
heads_5 <= 4'h0; // @[InputUnit.scala:86:24]
heads_6 <= 4'h8; // @[InputUnit.scala:86:24]
heads_7 <= 4'hC; // @[InputUnit.scala:86:24]
heads_8 <= 4'h0; // @[InputUnit.scala:86:24]
heads_9 <= 4'h0; // @[InputUnit.scala:86:24]
tails_0 <= 4'h0; // @[InputUnit.scala:87:24]
tails_1 <= 4'h0; // @[InputUnit.scala:87:24]
tails_2 <= 4'h0; // @[InputUnit.scala:87:24]
tails_3 <= 4'h4; // @[InputUnit.scala:87:24]
tails_4 <= 4'h0; // @[InputUnit.scala:87:24]
tails_5 <= 4'h0; // @[InputUnit.scala:87:24]
tails_6 <= 4'h8; // @[InputUnit.scala:87:24]
tails_7 <= 4'hC; // @[InputUnit.scala:87:24]
tails_8 <= 4'h0; // @[InputUnit.scala:87:24]
tails_9 <= 4'h0; // @[InputUnit.scala:87:24]
end
else begin // @[InputUnit.scala:49:7]
if (_GEN_11 & {to_q_oh_enc[9:8], |(_to_q_T_2[6:3]), |(_to_q_T_4[2:1]), _to_q_T_6} == 5'h0) // @[OneHot.scala:30:18, :32:{10,14,28}]
heads_0 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h1) // @[OneHot.scala:32:10]
heads_1 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h2) // @[OneHot.scala:32:10]
heads_2 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h3) // @[OneHot.scala:32:10]
heads_3 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h4) // @[OneHot.scala:32:10]
heads_4 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h5) // @[OneHot.scala:32:10]
heads_5 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h6) // @[OneHot.scala:32:10]
heads_6 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h7) // @[OneHot.scala:32:10]
heads_7 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h8) // @[OneHot.scala:32:10]
heads_8 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h9) // @[OneHot.scala:32:10]
heads_9 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (mem_MPORT_en & _GEN_0) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_0 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_1) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_1 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_2) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_2 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_3) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_3 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_4) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_4 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_5) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_5 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_6) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_6 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_7) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_7 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_8) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_8 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_9) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_9 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
end
always @(posedge)
|
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
|
module Tile_224( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_480 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Scheduler.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy.AddressSet
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import chisel3.experimental.dataview._
class InclusiveCacheBankScheduler(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val in = Flipped(TLBundle(params.inner.bundle))
val out = TLBundle(params.outer.bundle)
// Way permissions
val ways = Flipped(Vec(params.allClients, UInt(params.cache.ways.W)))
val divs = Flipped(Vec(params.allClients, UInt((InclusiveCacheParameters.lfsrBits + 1).W)))
// Control port
val req = Flipped(Decoupled(new SinkXRequest(params)))
val resp = Decoupled(new SourceXRequest(params))
})
val sourceA = Module(new SourceA(params))
val sourceB = Module(new SourceB(params))
val sourceC = Module(new SourceC(params))
val sourceD = Module(new SourceD(params))
val sourceE = Module(new SourceE(params))
val sourceX = Module(new SourceX(params))
io.out.a <> sourceA.io.a
io.out.c <> sourceC.io.c
io.out.e <> sourceE.io.e
io.in.b <> sourceB.io.b
io.in.d <> sourceD.io.d
io.resp <> sourceX.io.x
val sinkA = Module(new SinkA(params))
val sinkC = Module(new SinkC(params))
val sinkD = Module(new SinkD(params))
val sinkE = Module(new SinkE(params))
val sinkX = Module(new SinkX(params))
sinkA.io.a <> io.in.a
sinkC.io.c <> io.in.c
sinkE.io.e <> io.in.e
sinkD.io.d <> io.out.d
sinkX.io.x <> io.req
io.out.b.ready := true.B // disconnected
val directory = Module(new Directory(params))
val bankedStore = Module(new BankedStore(params))
val requests = Module(new ListBuffer(ListBufferParameters(new QueuedRequest(params), 3*params.mshrs, params.secondary, false)))
val mshrs = Seq.fill(params.mshrs) { Module(new MSHR(params)) }
val abc_mshrs = mshrs.init.init
val bc_mshr = mshrs.init.last
val c_mshr = mshrs.last
val nestedwb = Wire(new NestedWriteback(params))
// Deliver messages from Sinks to MSHRs
mshrs.zipWithIndex.foreach { case (m, i) =>
m.io.sinkc.valid := sinkC.io.resp.valid && sinkC.io.resp.bits.set === m.io.status.bits.set
m.io.sinkd.valid := sinkD.io.resp.valid && sinkD.io.resp.bits.source === i.U
m.io.sinke.valid := sinkE.io.resp.valid && sinkE.io.resp.bits.sink === i.U
m.io.sinkc.bits := sinkC.io.resp.bits
m.io.sinkd.bits := sinkD.io.resp.bits
m.io.sinke.bits := sinkE.io.resp.bits
m.io.nestedwb := nestedwb
}
// If the pre-emption BC or C MSHR have a matching set, the normal MSHR must be blocked
val mshr_stall_abc = abc_mshrs.map { m =>
(bc_mshr.io.status.valid && m.io.status.bits.set === bc_mshr.io.status.bits.set) ||
( c_mshr.io.status.valid && m.io.status.bits.set === c_mshr.io.status.bits.set)
}
val mshr_stall_bc =
c_mshr.io.status.valid && bc_mshr.io.status.bits.set === c_mshr.io.status.bits.set
val mshr_stall_c = false.B
val mshr_stall = mshr_stall_abc :+ mshr_stall_bc :+ mshr_stall_c
val stall_abc = (mshr_stall_abc zip abc_mshrs) map { case (s, m) => s && m.io.status.valid }
if (!params.lastLevel || !params.firstLevel)
params.ccover(stall_abc.reduce(_||_), "SCHEDULER_ABC_INTERLOCK", "ABC MSHR interlocked due to pre-emption")
if (!params.lastLevel)
params.ccover(mshr_stall_bc && bc_mshr.io.status.valid, "SCHEDULER_BC_INTERLOCK", "BC MSHR interlocked due to pre-emption")
// Consider scheduling an MSHR only if all the resources it requires are available
val mshr_request = Cat((mshrs zip mshr_stall).map { case (m, s) =>
m.io.schedule.valid && !s &&
(sourceA.io.req.ready || !m.io.schedule.bits.a.valid) &&
(sourceB.io.req.ready || !m.io.schedule.bits.b.valid) &&
(sourceC.io.req.ready || !m.io.schedule.bits.c.valid) &&
(sourceD.io.req.ready || !m.io.schedule.bits.d.valid) &&
(sourceE.io.req.ready || !m.io.schedule.bits.e.valid) &&
(sourceX.io.req.ready || !m.io.schedule.bits.x.valid) &&
(directory.io.write.ready || !m.io.schedule.bits.dir.valid)
}.reverse)
// Round-robin arbitration of MSHRs
val robin_filter = RegInit(0.U(params.mshrs.W))
val robin_request = Cat(mshr_request, mshr_request & robin_filter)
val mshr_selectOH2 = ~(leftOR(robin_request) << 1) & robin_request
val mshr_selectOH = mshr_selectOH2(2*params.mshrs-1, params.mshrs) | mshr_selectOH2(params.mshrs-1, 0)
val mshr_select = OHToUInt(mshr_selectOH)
val schedule = Mux1H(mshr_selectOH, mshrs.map(_.io.schedule.bits))
val scheduleTag = Mux1H(mshr_selectOH, mshrs.map(_.io.status.bits.tag))
val scheduleSet = Mux1H(mshr_selectOH, mshrs.map(_.io.status.bits.set))
// When an MSHR wins the schedule, it has lowest priority next time
when (mshr_request.orR) { robin_filter := ~rightOR(mshr_selectOH) }
// Fill in which MSHR sends the request
schedule.a.bits.source := mshr_select
schedule.c.bits.source := Mux(schedule.c.bits.opcode(1), mshr_select, 0.U) // only set for Release[Data] not ProbeAck[Data]
schedule.d.bits.sink := mshr_select
sourceA.io.req.valid := schedule.a.valid
sourceB.io.req.valid := schedule.b.valid
sourceC.io.req.valid := schedule.c.valid
sourceD.io.req.valid := schedule.d.valid
sourceE.io.req.valid := schedule.e.valid
sourceX.io.req.valid := schedule.x.valid
sourceA.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.a.bits)) := schedule.a.bits
sourceB.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.b.bits)) := schedule.b.bits
sourceC.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.c.bits)) := schedule.c.bits
sourceD.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.d.bits)) := schedule.d.bits
sourceE.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.e.bits)) := schedule.e.bits
sourceX.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.x.bits)) := schedule.x.bits
directory.io.write.valid := schedule.dir.valid
directory.io.write.bits.viewAsSupertype(chiselTypeOf(schedule.dir.bits)) := schedule.dir.bits
// Forward meta-data changes from nested transaction completion
val select_c = mshr_selectOH(params.mshrs-1)
val select_bc = mshr_selectOH(params.mshrs-2)
nestedwb.set := Mux(select_c, c_mshr.io.status.bits.set, bc_mshr.io.status.bits.set)
nestedwb.tag := Mux(select_c, c_mshr.io.status.bits.tag, bc_mshr.io.status.bits.tag)
nestedwb.b_toN := select_bc && bc_mshr.io.schedule.bits.dir.valid && bc_mshr.io.schedule.bits.dir.bits.data.state === MetaData.INVALID
nestedwb.b_toB := select_bc && bc_mshr.io.schedule.bits.dir.valid && bc_mshr.io.schedule.bits.dir.bits.data.state === MetaData.BRANCH
nestedwb.b_clr_dirty := select_bc && bc_mshr.io.schedule.bits.dir.valid
nestedwb.c_set_dirty := select_c && c_mshr.io.schedule.bits.dir.valid && c_mshr.io.schedule.bits.dir.bits.data.dirty
// Pick highest priority request
val request = Wire(Decoupled(new FullRequest(params)))
request.valid := directory.io.ready && (sinkA.io.req.valid || sinkX.io.req.valid || sinkC.io.req.valid)
request.bits := Mux(sinkC.io.req.valid, sinkC.io.req.bits,
Mux(sinkX.io.req.valid, sinkX.io.req.bits, sinkA.io.req.bits))
sinkC.io.req.ready := directory.io.ready && request.ready
sinkX.io.req.ready := directory.io.ready && request.ready && !sinkC.io.req.valid
sinkA.io.req.ready := directory.io.ready && request.ready && !sinkC.io.req.valid && !sinkX.io.req.valid
// If no MSHR has been assigned to this set, we need to allocate one
val setMatches = Cat(mshrs.map { m => m.io.status.valid && m.io.status.bits.set === request.bits.set }.reverse)
val alloc = !setMatches.orR // NOTE: no matches also means no BC or C pre-emption on this set
// If a same-set MSHR says that requests of this type must be blocked (for bounded time), do it
val blockB = Mux1H(setMatches, mshrs.map(_.io.status.bits.blockB)) && request.bits.prio(1)
val blockC = Mux1H(setMatches, mshrs.map(_.io.status.bits.blockC)) && request.bits.prio(2)
// If a same-set MSHR says that requests of this type must be handled out-of-band, use special BC|C MSHR
// ... these special MSHRs interlock the MSHR that said it should be pre-empted.
val nestB = Mux1H(setMatches, mshrs.map(_.io.status.bits.nestB)) && request.bits.prio(1)
val nestC = Mux1H(setMatches, mshrs.map(_.io.status.bits.nestC)) && request.bits.prio(2)
// Prevent priority inversion; we may not queue to MSHRs beyond our level
val prioFilter = Cat(request.bits.prio(2), !request.bits.prio(0), ~0.U((params.mshrs-2).W))
val lowerMatches = setMatches & prioFilter
// If we match an MSHR <= our priority that neither blocks nor nests us, queue to it.
val queue = lowerMatches.orR && !nestB && !nestC && !blockB && !blockC
if (!params.lastLevel) {
params.ccover(request.valid && blockB, "SCHEDULER_BLOCKB", "Interlock B request while resolving set conflict")
params.ccover(request.valid && nestB, "SCHEDULER_NESTB", "Priority escalation from channel B")
}
if (!params.firstLevel) {
params.ccover(request.valid && blockC, "SCHEDULER_BLOCKC", "Interlock C request while resolving set conflict")
params.ccover(request.valid && nestC, "SCHEDULER_NESTC", "Priority escalation from channel C")
}
params.ccover(request.valid && queue, "SCHEDULER_SECONDARY", "Enqueue secondary miss")
// It might happen that lowerMatches has >1 bit if the two special MSHRs are in-use
// We want to Q to the highest matching priority MSHR.
val lowerMatches1 =
Mux(lowerMatches(params.mshrs-1), 1.U << (params.mshrs-1),
Mux(lowerMatches(params.mshrs-2), 1.U << (params.mshrs-2),
lowerMatches))
// If this goes to the scheduled MSHR, it may need to be bypassed
// Alternatively, the MSHR may be refilled from a request queued in the ListBuffer
val selected_requests = Cat(mshr_selectOH, mshr_selectOH, mshr_selectOH) & requests.io.valid
val a_pop = selected_requests((0 + 1) * params.mshrs - 1, 0 * params.mshrs).orR
val b_pop = selected_requests((1 + 1) * params.mshrs - 1, 1 * params.mshrs).orR
val c_pop = selected_requests((2 + 1) * params.mshrs - 1, 2 * params.mshrs).orR
val bypassMatches = (mshr_selectOH & lowerMatches1).orR &&
Mux(c_pop || request.bits.prio(2), !c_pop, Mux(b_pop || request.bits.prio(1), !b_pop, !a_pop))
val may_pop = a_pop || b_pop || c_pop
val bypass = request.valid && queue && bypassMatches
val will_reload = schedule.reload && (may_pop || bypass)
val will_pop = schedule.reload && may_pop && !bypass
params.ccover(mshr_selectOH.orR && bypass, "SCHEDULER_BYPASS", "Bypass new request directly to conflicting MSHR")
params.ccover(mshr_selectOH.orR && will_reload, "SCHEDULER_RELOAD", "Back-to-back service of two requests")
params.ccover(mshr_selectOH.orR && will_pop, "SCHEDULER_POP", "Service of a secondary miss")
// Repeat the above logic, but without the fan-in
mshrs.zipWithIndex.foreach { case (m, i) =>
val sel = mshr_selectOH(i)
m.io.schedule.ready := sel
val a_pop = requests.io.valid(params.mshrs * 0 + i)
val b_pop = requests.io.valid(params.mshrs * 1 + i)
val c_pop = requests.io.valid(params.mshrs * 2 + i)
val bypassMatches = lowerMatches1(i) &&
Mux(c_pop || request.bits.prio(2), !c_pop, Mux(b_pop || request.bits.prio(1), !b_pop, !a_pop))
val may_pop = a_pop || b_pop || c_pop
val bypass = request.valid && queue && bypassMatches
val will_reload = m.io.schedule.bits.reload && (may_pop || bypass)
m.io.allocate.bits.viewAsSupertype(chiselTypeOf(requests.io.data)) := Mux(bypass, WireInit(new QueuedRequest(params), init = request.bits), requests.io.data)
m.io.allocate.bits.set := m.io.status.bits.set
m.io.allocate.bits.repeat := m.io.allocate.bits.tag === m.io.status.bits.tag
m.io.allocate.valid := sel && will_reload
}
// Determine which of the queued requests to pop (supposing will_pop)
val prio_requests = ~(~requests.io.valid | (requests.io.valid >> params.mshrs) | (requests.io.valid >> 2*params.mshrs))
val pop_index = OHToUInt(Cat(mshr_selectOH, mshr_selectOH, mshr_selectOH) & prio_requests)
requests.io.pop.valid := will_pop
requests.io.pop.bits := pop_index
// Reload from the Directory if the next MSHR operation changes tags
val lb_tag_mismatch = scheduleTag =/= requests.io.data.tag
val mshr_uses_directory_assuming_no_bypass = schedule.reload && may_pop && lb_tag_mismatch
val mshr_uses_directory_for_lb = will_pop && lb_tag_mismatch
val mshr_uses_directory = will_reload && scheduleTag =/= Mux(bypass, request.bits.tag, requests.io.data.tag)
// Is there an MSHR free for this request?
val mshr_validOH = Cat(mshrs.map(_.io.status.valid).reverse)
val mshr_free = (~mshr_validOH & prioFilter).orR
// Fanout the request to the appropriate handler (if any)
val bypassQueue = schedule.reload && bypassMatches
val request_alloc_cases =
(alloc && !mshr_uses_directory_assuming_no_bypass && mshr_free) ||
(nestB && !mshr_uses_directory_assuming_no_bypass && !bc_mshr.io.status.valid && !c_mshr.io.status.valid) ||
(nestC && !mshr_uses_directory_assuming_no_bypass && !c_mshr.io.status.valid)
request.ready := request_alloc_cases || (queue && (bypassQueue || requests.io.push.ready))
val alloc_uses_directory = request.valid && request_alloc_cases
// When a request goes through, it will need to hit the Directory
directory.io.read.valid := mshr_uses_directory || alloc_uses_directory
directory.io.read.bits.set := Mux(mshr_uses_directory_for_lb, scheduleSet, request.bits.set)
directory.io.read.bits.tag := Mux(mshr_uses_directory_for_lb, requests.io.data.tag, request.bits.tag)
// Enqueue the request if not bypassed directly into an MSHR
requests.io.push.valid := request.valid && queue && !bypassQueue
requests.io.push.bits.data := request.bits
requests.io.push.bits.index := Mux1H(
request.bits.prio, Seq(
OHToUInt(lowerMatches1 << params.mshrs*0),
OHToUInt(lowerMatches1 << params.mshrs*1),
OHToUInt(lowerMatches1 << params.mshrs*2)))
val mshr_insertOH = ~(leftOR(~mshr_validOH) << 1) & ~mshr_validOH & prioFilter
(mshr_insertOH.asBools zip mshrs) map { case (s, m) =>
when (request.valid && alloc && s && !mshr_uses_directory_assuming_no_bypass) {
m.io.allocate.valid := true.B
m.io.allocate.bits.viewAsSupertype(chiselTypeOf(request.bits)) := request.bits
m.io.allocate.bits.repeat := false.B
}
}
when (request.valid && nestB && !bc_mshr.io.status.valid && !c_mshr.io.status.valid && !mshr_uses_directory_assuming_no_bypass) {
bc_mshr.io.allocate.valid := true.B
bc_mshr.io.allocate.bits.viewAsSupertype(chiselTypeOf(request.bits)) := request.bits
bc_mshr.io.allocate.bits.repeat := false.B
assert (!request.bits.prio(0))
}
bc_mshr.io.allocate.bits.prio(0) := false.B
when (request.valid && nestC && !c_mshr.io.status.valid && !mshr_uses_directory_assuming_no_bypass) {
c_mshr.io.allocate.valid := true.B
c_mshr.io.allocate.bits.viewAsSupertype(chiselTypeOf(request.bits)) := request.bits
c_mshr.io.allocate.bits.repeat := false.B
assert (!request.bits.prio(0))
assert (!request.bits.prio(1))
}
c_mshr.io.allocate.bits.prio(0) := false.B
c_mshr.io.allocate.bits.prio(1) := false.B
// Fanout the result of the Directory lookup
val dirTarget = Mux(alloc, mshr_insertOH, Mux(nestB,(BigInt(1) << (params.mshrs-2)).U,(BigInt(1) << (params.mshrs-1)).U))
val directoryFanout = params.dirReg(RegNext(Mux(mshr_uses_directory, mshr_selectOH, Mux(alloc_uses_directory, dirTarget, 0.U))))
mshrs.zipWithIndex.foreach { case (m, i) =>
m.io.directory.valid := directoryFanout(i)
m.io.directory.bits := directory.io.result.bits
}
// MSHR response meta-data fetch
sinkC.io.way :=
Mux(bc_mshr.io.status.valid && bc_mshr.io.status.bits.set === sinkC.io.set,
bc_mshr.io.status.bits.way,
Mux1H(abc_mshrs.map(m => m.io.status.valid && m.io.status.bits.set === sinkC.io.set),
abc_mshrs.map(_.io.status.bits.way)))
sinkD.io.way := VecInit(mshrs.map(_.io.status.bits.way))(sinkD.io.source)
sinkD.io.set := VecInit(mshrs.map(_.io.status.bits.set))(sinkD.io.source)
// Beat buffer connections between components
sinkA.io.pb_pop <> sourceD.io.pb_pop
sourceD.io.pb_beat := sinkA.io.pb_beat
sinkC.io.rel_pop <> sourceD.io.rel_pop
sourceD.io.rel_beat := sinkC.io.rel_beat
// BankedStore ports
bankedStore.io.sinkC_adr <> sinkC.io.bs_adr
bankedStore.io.sinkC_dat := sinkC.io.bs_dat
bankedStore.io.sinkD_adr <> sinkD.io.bs_adr
bankedStore.io.sinkD_dat := sinkD.io.bs_dat
bankedStore.io.sourceC_adr <> sourceC.io.bs_adr
bankedStore.io.sourceD_radr <> sourceD.io.bs_radr
bankedStore.io.sourceD_wadr <> sourceD.io.bs_wadr
bankedStore.io.sourceD_wdat := sourceD.io.bs_wdat
sourceC.io.bs_dat := bankedStore.io.sourceC_dat
sourceD.io.bs_rdat := bankedStore.io.sourceD_rdat
// SourceD data hazard interlock
sourceD.io.evict_req := sourceC.io.evict_req
sourceD.io.grant_req := sinkD .io.grant_req
sourceC.io.evict_safe := sourceD.io.evict_safe
sinkD .io.grant_safe := sourceD.io.grant_safe
private def afmt(x: AddressSet) = s"""{"base":${x.base},"mask":${x.mask}}"""
private def addresses = params.inner.manager.managers.flatMap(_.address).map(afmt _).mkString(",")
private def setBits = params.addressMapping.drop(params.offsetBits).take(params.setBits).mkString(",")
private def tagBits = params.addressMapping.drop(params.offsetBits + params.setBits).take(params.tagBits).mkString(",")
private def simple = s""""reset":"${reset.pathName}","tagBits":[${tagBits}],"setBits":[${setBits}],"blockBytes":${params.cache.blockBytes},"ways":${params.cache.ways}"""
def json: String = s"""{"addresses":[${addresses}],${simple},"directory":${directory.json},"subbanks":${bankedStore.json}}"""
}
|
module InclusiveCacheBankScheduler_4( // @[Scheduler.scala:27:7]
input clock, // @[Scheduler.scala:27:7]
input reset, // @[Scheduler.scala:27:7]
output io_in_a_ready, // @[Scheduler.scala:29:14]
input io_in_a_valid, // @[Scheduler.scala:29:14]
input [2:0] io_in_a_bits_opcode, // @[Scheduler.scala:29:14]
input [2:0] io_in_a_bits_param, // @[Scheduler.scala:29:14]
input [2:0] io_in_a_bits_size, // @[Scheduler.scala:29:14]
input [5:0] io_in_a_bits_source, // @[Scheduler.scala:29:14]
input [31:0] io_in_a_bits_address, // @[Scheduler.scala:29:14]
input [15:0] io_in_a_bits_mask, // @[Scheduler.scala:29:14]
input [127:0] io_in_a_bits_data, // @[Scheduler.scala:29:14]
input io_in_a_bits_corrupt, // @[Scheduler.scala:29:14]
input io_in_b_ready, // @[Scheduler.scala:29:14]
output io_in_b_valid, // @[Scheduler.scala:29:14]
output [1:0] io_in_b_bits_param, // @[Scheduler.scala:29:14]
output [31:0] io_in_b_bits_address, // @[Scheduler.scala:29:14]
output io_in_c_ready, // @[Scheduler.scala:29:14]
input io_in_c_valid, // @[Scheduler.scala:29:14]
input [2:0] io_in_c_bits_opcode, // @[Scheduler.scala:29:14]
input [2:0] io_in_c_bits_param, // @[Scheduler.scala:29:14]
input [2:0] io_in_c_bits_size, // @[Scheduler.scala:29:14]
input [5:0] io_in_c_bits_source, // @[Scheduler.scala:29:14]
input [31:0] io_in_c_bits_address, // @[Scheduler.scala:29:14]
input [127:0] io_in_c_bits_data, // @[Scheduler.scala:29:14]
input io_in_c_bits_corrupt, // @[Scheduler.scala:29:14]
input io_in_d_ready, // @[Scheduler.scala:29:14]
output io_in_d_valid, // @[Scheduler.scala:29:14]
output [2:0] io_in_d_bits_opcode, // @[Scheduler.scala:29:14]
output [1:0] io_in_d_bits_param, // @[Scheduler.scala:29:14]
output [2:0] io_in_d_bits_size, // @[Scheduler.scala:29:14]
output [5:0] io_in_d_bits_source, // @[Scheduler.scala:29:14]
output [3:0] io_in_d_bits_sink, // @[Scheduler.scala:29:14]
output io_in_d_bits_denied, // @[Scheduler.scala:29:14]
output [127:0] io_in_d_bits_data, // @[Scheduler.scala:29:14]
output io_in_d_bits_corrupt, // @[Scheduler.scala:29:14]
input io_in_e_valid, // @[Scheduler.scala:29:14]
input [3:0] io_in_e_bits_sink, // @[Scheduler.scala:29:14]
input io_out_a_ready, // @[Scheduler.scala:29:14]
output io_out_a_valid, // @[Scheduler.scala:29:14]
output [2:0] io_out_a_bits_opcode, // @[Scheduler.scala:29:14]
output [2:0] io_out_a_bits_param, // @[Scheduler.scala:29:14]
output [2:0] io_out_a_bits_size, // @[Scheduler.scala:29:14]
output [3:0] io_out_a_bits_source, // @[Scheduler.scala:29:14]
output [31:0] io_out_a_bits_address, // @[Scheduler.scala:29:14]
output [7:0] io_out_a_bits_mask, // @[Scheduler.scala:29:14]
output [63:0] io_out_a_bits_data, // @[Scheduler.scala:29:14]
output io_out_a_bits_corrupt, // @[Scheduler.scala:29:14]
input io_out_c_ready, // @[Scheduler.scala:29:14]
output io_out_c_valid, // @[Scheduler.scala:29:14]
output [2:0] io_out_c_bits_opcode, // @[Scheduler.scala:29:14]
output [2:0] io_out_c_bits_param, // @[Scheduler.scala:29:14]
output [2:0] io_out_c_bits_size, // @[Scheduler.scala:29:14]
output [3:0] io_out_c_bits_source, // @[Scheduler.scala:29:14]
output [31:0] io_out_c_bits_address, // @[Scheduler.scala:29:14]
output [63:0] io_out_c_bits_data, // @[Scheduler.scala:29:14]
output io_out_c_bits_corrupt, // @[Scheduler.scala:29:14]
output io_out_d_ready, // @[Scheduler.scala:29:14]
input io_out_d_valid, // @[Scheduler.scala:29:14]
input [2:0] io_out_d_bits_opcode, // @[Scheduler.scala:29:14]
input [1:0] io_out_d_bits_param, // @[Scheduler.scala:29:14]
input [2:0] io_out_d_bits_size, // @[Scheduler.scala:29:14]
input [3:0] io_out_d_bits_source, // @[Scheduler.scala:29:14]
input [2:0] io_out_d_bits_sink, // @[Scheduler.scala:29:14]
input io_out_d_bits_denied, // @[Scheduler.scala:29:14]
input [63:0] io_out_d_bits_data, // @[Scheduler.scala:29:14]
input io_out_d_bits_corrupt, // @[Scheduler.scala:29:14]
output io_out_e_valid, // @[Scheduler.scala:29:14]
output [2:0] io_out_e_bits_sink, // @[Scheduler.scala:29:14]
output io_req_ready, // @[Scheduler.scala:29:14]
input io_req_valid, // @[Scheduler.scala:29:14]
input [31:0] io_req_bits_address, // @[Scheduler.scala:29:14]
output io_resp_valid // @[Scheduler.scala:29:14]
);
wire [8:0] mshrs_11_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :295:103, :297:73]
wire [8:0] mshrs_10_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :287:131, :289:74]
wire [8:0] mshrs_9_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_8_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_7_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_6_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_5_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_4_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_3_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_2_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_1_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_0_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [5:0] request_bits_put; // @[Scheduler.scala:163:21]
wire [5:0] request_bits_offset; // @[Scheduler.scala:163:21]
wire [8:0] request_bits_tag; // @[Scheduler.scala:163:21]
wire [5:0] request_bits_source; // @[Scheduler.scala:163:21]
wire [2:0] request_bits_size; // @[Scheduler.scala:163:21]
wire [2:0] request_bits_param; // @[Scheduler.scala:163:21]
wire [2:0] request_bits_opcode; // @[Scheduler.scala:163:21]
wire request_bits_control; // @[Scheduler.scala:163:21]
wire request_bits_prio_2; // @[Scheduler.scala:163:21]
wire request_bits_prio_0; // @[Scheduler.scala:163:21]
wire _mshrs_11_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_11_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_11_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_11_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_11_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_11_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_11_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_11_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_11_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_11_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_11_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_11_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_11_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_11_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_11_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_11_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_11_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_11_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_11_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_10_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_10_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_10_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_10_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_10_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_10_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_10_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_10_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_10_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_10_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_10_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_10_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_10_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_10_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_10_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_10_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_10_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_10_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_9_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_9_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_9_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_9_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_9_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_9_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_9_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_9_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_9_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_9_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_9_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_9_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_9_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_9_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_9_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_9_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_9_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_9_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_9_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_9_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_8_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_8_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_8_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_8_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_8_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_8_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_8_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_8_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_8_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_8_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_8_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_8_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_8_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_8_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_8_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_8_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_8_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_8_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_8_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_8_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_7_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_7_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_7_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_7_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_7_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_7_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_7_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_7_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_7_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_7_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_7_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_7_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_7_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_7_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_7_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_7_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_7_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_7_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_7_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_7_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_6_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_6_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_6_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_6_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_6_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_6_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_6_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_6_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_6_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_6_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_6_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_6_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_6_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_6_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_6_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_6_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_6_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_6_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_5_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_5_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_5_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_5_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_5_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_5_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_5_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_5_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_5_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_5_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_5_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_5_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_5_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_5_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_5_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_5_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_5_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_5_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_4_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_4_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_4_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_4_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_4_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_4_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_4_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_4_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_4_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_4_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_4_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_4_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_4_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_4_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_4_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_4_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_4_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_4_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_4_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_3_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_3_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_3_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_3_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_3_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_3_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_3_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_3_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_3_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_3_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_3_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_3_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_3_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_3_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_3_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_3_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_3_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_3_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_3_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_2_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_2_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_2_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_2_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_2_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_2_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_2_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_2_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_2_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_2_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_2_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_2_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_2_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_2_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_2_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_2_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_2_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_2_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_2_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_1_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_1_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_1_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_1_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_1_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_1_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_1_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_1_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_1_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_1_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_1_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_1_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_1_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_1_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_1_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_1_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_1_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_1_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_1_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_0_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_0_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_0_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_0_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_0_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_0_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_0_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_0_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_0_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_0_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_0_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_0_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_0_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_0_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_0_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_0_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_0_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_0_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_0_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _requests_io_push_ready; // @[Scheduler.scala:70:24]
wire [35:0] _requests_io_valid; // @[Scheduler.scala:70:24]
wire _requests_io_data_prio_0; // @[Scheduler.scala:70:24]
wire _requests_io_data_prio_1; // @[Scheduler.scala:70:24]
wire _requests_io_data_prio_2; // @[Scheduler.scala:70:24]
wire _requests_io_data_control; // @[Scheduler.scala:70:24]
wire [2:0] _requests_io_data_opcode; // @[Scheduler.scala:70:24]
wire [2:0] _requests_io_data_param; // @[Scheduler.scala:70:24]
wire [2:0] _requests_io_data_size; // @[Scheduler.scala:70:24]
wire [5:0] _requests_io_data_source; // @[Scheduler.scala:70:24]
wire [8:0] _requests_io_data_tag; // @[Scheduler.scala:70:24]
wire [5:0] _requests_io_data_offset; // @[Scheduler.scala:70:24]
wire [5:0] _requests_io_data_put; // @[Scheduler.scala:70:24]
wire _bankedStore_io_sinkC_adr_ready; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sinkD_adr_ready; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sourceC_adr_ready; // @[Scheduler.scala:69:27]
wire [63:0] _bankedStore_io_sourceC_dat_data; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sourceD_radr_ready; // @[Scheduler.scala:69:27]
wire [127:0] _bankedStore_io_sourceD_rdat_data; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sourceD_wadr_ready; // @[Scheduler.scala:69:27]
wire _directory_io_write_ready; // @[Scheduler.scala:68:25]
wire _directory_io_result_bits_dirty; // @[Scheduler.scala:68:25]
wire [1:0] _directory_io_result_bits_state; // @[Scheduler.scala:68:25]
wire _directory_io_result_bits_clients; // @[Scheduler.scala:68:25]
wire [8:0] _directory_io_result_bits_tag; // @[Scheduler.scala:68:25]
wire _directory_io_result_bits_hit; // @[Scheduler.scala:68:25]
wire [3:0] _directory_io_result_bits_way; // @[Scheduler.scala:68:25]
wire _directory_io_ready; // @[Scheduler.scala:68:25]
wire _sinkX_io_req_valid; // @[Scheduler.scala:58:21]
wire [8:0] _sinkX_io_req_bits_tag; // @[Scheduler.scala:58:21]
wire [10:0] _sinkX_io_req_bits_set; // @[Scheduler.scala:58:21]
wire _sinkE_io_resp_valid; // @[Scheduler.scala:57:21]
wire [3:0] _sinkE_io_resp_bits_sink; // @[Scheduler.scala:57:21]
wire _sinkD_io_resp_valid; // @[Scheduler.scala:56:21]
wire _sinkD_io_resp_bits_last; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_resp_bits_opcode; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_resp_bits_param; // @[Scheduler.scala:56:21]
wire [3:0] _sinkD_io_resp_bits_source; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_resp_bits_sink; // @[Scheduler.scala:56:21]
wire _sinkD_io_resp_bits_denied; // @[Scheduler.scala:56:21]
wire [3:0] _sinkD_io_source; // @[Scheduler.scala:56:21]
wire _sinkD_io_bs_adr_valid; // @[Scheduler.scala:56:21]
wire _sinkD_io_bs_adr_bits_noop; // @[Scheduler.scala:56:21]
wire [3:0] _sinkD_io_bs_adr_bits_way; // @[Scheduler.scala:56:21]
wire [10:0] _sinkD_io_bs_adr_bits_set; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_bs_adr_bits_beat; // @[Scheduler.scala:56:21]
wire [63:0] _sinkD_io_bs_dat_data; // @[Scheduler.scala:56:21]
wire [10:0] _sinkD_io_grant_req_set; // @[Scheduler.scala:56:21]
wire [3:0] _sinkD_io_grant_req_way; // @[Scheduler.scala:56:21]
wire _sinkC_io_req_valid; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_req_bits_opcode; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_req_bits_param; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_req_bits_size; // @[Scheduler.scala:55:21]
wire [5:0] _sinkC_io_req_bits_source; // @[Scheduler.scala:55:21]
wire [8:0] _sinkC_io_req_bits_tag; // @[Scheduler.scala:55:21]
wire [5:0] _sinkC_io_req_bits_offset; // @[Scheduler.scala:55:21]
wire [5:0] _sinkC_io_req_bits_put; // @[Scheduler.scala:55:21]
wire [10:0] _sinkC_io_req_bits_set; // @[Scheduler.scala:55:21]
wire _sinkC_io_resp_valid; // @[Scheduler.scala:55:21]
wire _sinkC_io_resp_bits_last; // @[Scheduler.scala:55:21]
wire [10:0] _sinkC_io_resp_bits_set; // @[Scheduler.scala:55:21]
wire [8:0] _sinkC_io_resp_bits_tag; // @[Scheduler.scala:55:21]
wire [5:0] _sinkC_io_resp_bits_source; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_resp_bits_param; // @[Scheduler.scala:55:21]
wire _sinkC_io_resp_bits_data; // @[Scheduler.scala:55:21]
wire [10:0] _sinkC_io_set; // @[Scheduler.scala:55:21]
wire _sinkC_io_bs_adr_valid; // @[Scheduler.scala:55:21]
wire _sinkC_io_bs_adr_bits_noop; // @[Scheduler.scala:55:21]
wire [3:0] _sinkC_io_bs_adr_bits_way; // @[Scheduler.scala:55:21]
wire [10:0] _sinkC_io_bs_adr_bits_set; // @[Scheduler.scala:55:21]
wire [1:0] _sinkC_io_bs_adr_bits_beat; // @[Scheduler.scala:55:21]
wire [1:0] _sinkC_io_bs_adr_bits_mask; // @[Scheduler.scala:55:21]
wire [127:0] _sinkC_io_bs_dat_data; // @[Scheduler.scala:55:21]
wire _sinkC_io_rel_pop_ready; // @[Scheduler.scala:55:21]
wire [127:0] _sinkC_io_rel_beat_data; // @[Scheduler.scala:55:21]
wire _sinkC_io_rel_beat_corrupt; // @[Scheduler.scala:55:21]
wire _sinkA_io_req_valid; // @[Scheduler.scala:54:21]
wire [2:0] _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21]
wire [2:0] _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21]
wire [2:0] _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21]
wire [5:0] _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21]
wire [8:0] _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21]
wire [5:0] _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21]
wire [5:0] _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21]
wire [10:0] _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21]
wire _sinkA_io_pb_pop_ready; // @[Scheduler.scala:54:21]
wire [127:0] _sinkA_io_pb_beat_data; // @[Scheduler.scala:54:21]
wire [15:0] _sinkA_io_pb_beat_mask; // @[Scheduler.scala:54:21]
wire _sinkA_io_pb_beat_corrupt; // @[Scheduler.scala:54:21]
wire _sourceX_io_req_ready; // @[Scheduler.scala:45:23]
wire _sourceE_io_req_ready; // @[Scheduler.scala:44:23]
wire _sourceD_io_req_ready; // @[Scheduler.scala:43:23]
wire _sourceD_io_pb_pop_valid; // @[Scheduler.scala:43:23]
wire [5:0] _sourceD_io_pb_pop_bits_index; // @[Scheduler.scala:43:23]
wire _sourceD_io_pb_pop_bits_last; // @[Scheduler.scala:43:23]
wire _sourceD_io_rel_pop_valid; // @[Scheduler.scala:43:23]
wire [5:0] _sourceD_io_rel_pop_bits_index; // @[Scheduler.scala:43:23]
wire _sourceD_io_rel_pop_bits_last; // @[Scheduler.scala:43:23]
wire _sourceD_io_bs_radr_valid; // @[Scheduler.scala:43:23]
wire [3:0] _sourceD_io_bs_radr_bits_way; // @[Scheduler.scala:43:23]
wire [10:0] _sourceD_io_bs_radr_bits_set; // @[Scheduler.scala:43:23]
wire [1:0] _sourceD_io_bs_radr_bits_beat; // @[Scheduler.scala:43:23]
wire [1:0] _sourceD_io_bs_radr_bits_mask; // @[Scheduler.scala:43:23]
wire _sourceD_io_bs_wadr_valid; // @[Scheduler.scala:43:23]
wire [3:0] _sourceD_io_bs_wadr_bits_way; // @[Scheduler.scala:43:23]
wire [10:0] _sourceD_io_bs_wadr_bits_set; // @[Scheduler.scala:43:23]
wire [1:0] _sourceD_io_bs_wadr_bits_beat; // @[Scheduler.scala:43:23]
wire [1:0] _sourceD_io_bs_wadr_bits_mask; // @[Scheduler.scala:43:23]
wire [127:0] _sourceD_io_bs_wdat_data; // @[Scheduler.scala:43:23]
wire _sourceD_io_evict_safe; // @[Scheduler.scala:43:23]
wire _sourceD_io_grant_safe; // @[Scheduler.scala:43:23]
wire _sourceC_io_req_ready; // @[Scheduler.scala:42:23]
wire _sourceC_io_bs_adr_valid; // @[Scheduler.scala:42:23]
wire [3:0] _sourceC_io_bs_adr_bits_way; // @[Scheduler.scala:42:23]
wire [10:0] _sourceC_io_bs_adr_bits_set; // @[Scheduler.scala:42:23]
wire [2:0] _sourceC_io_bs_adr_bits_beat; // @[Scheduler.scala:42:23]
wire [10:0] _sourceC_io_evict_req_set; // @[Scheduler.scala:42:23]
wire [3:0] _sourceC_io_evict_req_way; // @[Scheduler.scala:42:23]
wire _sourceB_io_req_ready; // @[Scheduler.scala:41:23]
wire _sourceA_io_req_ready; // @[Scheduler.scala:40:23]
wire io_in_a_valid_0 = io_in_a_valid; // @[Scheduler.scala:27:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Scheduler.scala:27:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Scheduler.scala:27:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Scheduler.scala:27:7]
wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Scheduler.scala:27:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Scheduler.scala:27:7]
wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Scheduler.scala:27:7]
wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Scheduler.scala:27:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Scheduler.scala:27:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Scheduler.scala:27:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Scheduler.scala:27:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Scheduler.scala:27:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Scheduler.scala:27:7]
wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Scheduler.scala:27:7]
wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Scheduler.scala:27:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Scheduler.scala:27:7]
wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Scheduler.scala:27:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Scheduler.scala:27:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Scheduler.scala:27:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Scheduler.scala:27:7]
wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Scheduler.scala:27:7]
wire io_out_a_ready_0 = io_out_a_ready; // @[Scheduler.scala:27:7]
wire io_out_c_ready_0 = io_out_c_ready; // @[Scheduler.scala:27:7]
wire io_out_d_valid_0 = io_out_d_valid; // @[Scheduler.scala:27:7]
wire [2:0] io_out_d_bits_opcode_0 = io_out_d_bits_opcode; // @[Scheduler.scala:27:7]
wire [1:0] io_out_d_bits_param_0 = io_out_d_bits_param; // @[Scheduler.scala:27:7]
wire [2:0] io_out_d_bits_size_0 = io_out_d_bits_size; // @[Scheduler.scala:27:7]
wire [3:0] io_out_d_bits_source_0 = io_out_d_bits_source; // @[Scheduler.scala:27:7]
wire [2:0] io_out_d_bits_sink_0 = io_out_d_bits_sink; // @[Scheduler.scala:27:7]
wire io_out_d_bits_denied_0 = io_out_d_bits_denied; // @[Scheduler.scala:27:7]
wire [63:0] io_out_d_bits_data_0 = io_out_d_bits_data; // @[Scheduler.scala:27:7]
wire io_out_d_bits_corrupt_0 = io_out_d_bits_corrupt; // @[Scheduler.scala:27:7]
wire io_req_valid_0 = io_req_valid; // @[Scheduler.scala:27:7]
wire [31:0] io_req_bits_address_0 = io_req_bits_address; // @[Scheduler.scala:27:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7]
wire io_out_b_valid = 1'h0; // @[Scheduler.scala:27:7]
wire io_out_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7]
wire io_resp_bits_fail = 1'h0; // @[Scheduler.scala:27:7]
wire schedule_x_bits_fail = 1'h0; // @[Mux.scala:30:73]
wire _schedule_WIRE_11_bits_fail = 1'h0; // @[Mux.scala:30:73]
wire _schedule_WIRE_12_fail = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_196 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_197 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_198 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_199 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_200 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_201 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_202 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_203 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_204 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_205 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_206 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_207 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_208 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_209 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_210 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_211 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_212 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_213 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_214 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_215 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_216 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_217 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_218 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_WIRE_13 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_574 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_575 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_598 = 1'h0; // @[Mux.scala:30:73]
wire request_bits_prio_1 = 1'h0; // @[Scheduler.scala:163:21]
wire _request_bits_T_prio_1 = 1'h0; // @[Scheduler.scala:166:22]
wire _request_bits_T_prio_2 = 1'h0; // @[Scheduler.scala:166:22]
wire _request_bits_T_1_prio_1 = 1'h0; // @[Scheduler.scala:165:22]
wire blockB = 1'h0; // @[Scheduler.scala:175:70]
wire nestB = 1'h0; // @[Scheduler.scala:179:70]
wire _view__WIRE_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_1_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_2_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_3_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_4_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_5_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_6_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_7_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_8_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_9_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_10_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_11_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _request_alloc_cases_T_4 = 1'h0; // @[Scheduler.scala:259:13]
wire _request_alloc_cases_T_6 = 1'h0; // @[Scheduler.scala:259:56]
wire _request_alloc_cases_T_8 = 1'h0; // @[Scheduler.scala:259:84]
wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Scheduler.scala:27:7]
wire [2:0] io_in_b_bits_size = 3'h6; // @[Scheduler.scala:27:7]
wire [5:0] io_in_b_bits_source = 6'h28; // @[Scheduler.scala:27:7]
wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Scheduler.scala:27:7]
wire [127:0] io_in_b_bits_data = 128'h0; // @[Scheduler.scala:27:7]
wire io_in_e_ready = 1'h1; // @[Scheduler.scala:27:7]
wire io_out_b_ready = 1'h1; // @[Scheduler.scala:27:7]
wire io_out_e_ready = 1'h1; // @[Scheduler.scala:27:7]
wire io_resp_ready = 1'h1; // @[Scheduler.scala:27:7]
wire _mshr_request_T_253 = 1'h1; // @[Scheduler.scala:107:28]
wire _request_bits_T_prio_0 = 1'h1; // @[Scheduler.scala:166:22]
wire _queue_T_1 = 1'h1; // @[Scheduler.scala:185:35]
wire _queue_T_5 = 1'h1; // @[Scheduler.scala:185:55]
wire [2:0] io_out_b_bits_opcode = 3'h0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_b_bits_size = 3'h0; // @[Scheduler.scala:27:7]
wire [1:0] io_out_b_bits_param = 2'h0; // @[Scheduler.scala:27:7]
wire [3:0] io_out_b_bits_source = 4'h0; // @[Scheduler.scala:27:7]
wire [3:0] _schedule_WIRE_19_bits_sink = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_20_sink = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_334 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_335 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_336 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_337 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_338 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_339 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_340 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_341 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_342 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_343 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_344 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_345 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_346 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_347 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_348 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_349 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_350 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_351 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_352 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_353 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_354 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_355 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_356 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_23 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_38_bits_source = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_39_source = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_748 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_749 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_750 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_751 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_752 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_753 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_754 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_755 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_756 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_757 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_758 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_759 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_760 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_761 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_762 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_763 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_764 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_765 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_766 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_767 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_768 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_769 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_770 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_44 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_55_bits_source = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_56_source = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_978 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_979 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_980 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_981 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_982 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_983 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_984 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_985 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_986 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_987 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_988 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_989 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_990 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_991 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_992 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_993 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_994 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_995 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_996 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_997 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_998 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_999 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_1000 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_58 = 4'h0; // @[Mux.scala:30:73]
wire [31:0] io_out_b_bits_address = 32'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_out_b_bits_mask = 8'h0; // @[Scheduler.scala:27:7]
wire [63:0] io_out_b_bits_data = 64'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_0 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_1 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_2 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_3 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_4 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_5 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_6 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_7 = 16'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_0 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_1 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_2 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_3 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_4 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_5 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_6 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_7 = 11'h0; // @[Scheduler.scala:27:7]
wire [11:0] _lowerMatches1_T_1 = 12'h800; // @[Scheduler.scala:200:43]
wire [11:0] _dirTarget_T = 12'h800; // @[Scheduler.scala:306:48]
wire [4:0] _requests_io_push_bits_index_T_43 = 5'h0; // @[Mux.scala:30:73]
wire [9:0] _prioFilter_T_1 = 10'h3FF; // @[Scheduler.scala:182:69]
wire [10:0] _lowerMatches1_T_3 = 11'h400; // @[Scheduler.scala:201:43]
wire io_in_a_ready_0; // @[Scheduler.scala:27:7]
wire [1:0] io_in_b_bits_param_0; // @[Scheduler.scala:27:7]
wire [31:0] io_in_b_bits_address_0; // @[Scheduler.scala:27:7]
wire io_in_b_valid_0; // @[Scheduler.scala:27:7]
wire io_in_c_ready_0; // @[Scheduler.scala:27:7]
wire [2:0] io_in_d_bits_opcode_0; // @[Scheduler.scala:27:7]
wire [1:0] io_in_d_bits_param_0; // @[Scheduler.scala:27:7]
wire [2:0] io_in_d_bits_size_0; // @[Scheduler.scala:27:7]
wire [5:0] io_in_d_bits_source_0; // @[Scheduler.scala:27:7]
wire [3:0] io_in_d_bits_sink_0; // @[Scheduler.scala:27:7]
wire io_in_d_bits_denied_0; // @[Scheduler.scala:27:7]
wire [127:0] io_in_d_bits_data_0; // @[Scheduler.scala:27:7]
wire io_in_d_bits_corrupt_0; // @[Scheduler.scala:27:7]
wire io_in_d_valid_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_a_bits_opcode_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_a_bits_param_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_a_bits_size_0; // @[Scheduler.scala:27:7]
wire [3:0] io_out_a_bits_source_0; // @[Scheduler.scala:27:7]
wire [31:0] io_out_a_bits_address_0; // @[Scheduler.scala:27:7]
wire [7:0] io_out_a_bits_mask_0; // @[Scheduler.scala:27:7]
wire [63:0] io_out_a_bits_data_0; // @[Scheduler.scala:27:7]
wire io_out_a_bits_corrupt_0; // @[Scheduler.scala:27:7]
wire io_out_a_valid_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_c_bits_opcode_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_c_bits_param_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_c_bits_size_0; // @[Scheduler.scala:27:7]
wire [3:0] io_out_c_bits_source_0; // @[Scheduler.scala:27:7]
wire [31:0] io_out_c_bits_address_0; // @[Scheduler.scala:27:7]
wire [63:0] io_out_c_bits_data_0; // @[Scheduler.scala:27:7]
wire io_out_c_bits_corrupt_0; // @[Scheduler.scala:27:7]
wire io_out_c_valid_0; // @[Scheduler.scala:27:7]
wire io_out_d_ready_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_e_bits_sink_0; // @[Scheduler.scala:27:7]
wire io_out_e_valid_0; // @[Scheduler.scala:27:7]
wire io_req_ready_0; // @[Scheduler.scala:27:7]
wire io_resp_valid_0; // @[Scheduler.scala:27:7]
wire [10:0] _nestedwb_set_T; // @[Scheduler.scala:155:24]
wire [8:0] _nestedwb_tag_T; // @[Scheduler.scala:156:24]
wire _nestedwb_b_toN_T_2; // @[Scheduler.scala:157:75]
wire _nestedwb_b_toB_T_2; // @[Scheduler.scala:158:75]
wire _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:159:37]
wire _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:160:75]
wire [10:0] nestedwb_set; // @[Scheduler.scala:75:22]
wire [8:0] nestedwb_tag; // @[Scheduler.scala:75:22]
wire nestedwb_b_toN; // @[Scheduler.scala:75:22]
wire nestedwb_b_toB; // @[Scheduler.scala:75:22]
wire nestedwb_b_clr_dirty; // @[Scheduler.scala:75:22]
wire nestedwb_c_set_dirty; // @[Scheduler.scala:75:22]
wire _mshrs_0_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_0_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_0_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_0_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_0_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h0; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_0_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_0_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_0_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h0; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_0_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_0_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_1_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_1_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_1_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_1_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_1_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h1; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_1_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_1_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_1_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h1; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_1_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_1_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_2_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_2_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_2_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_2_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_2_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h2; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_2_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_2_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_2_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h2; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_2_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_2_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_3_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_3_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_3_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_3_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_3_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h3; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_3_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_3_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_3_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h3; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_3_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_3_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_4_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_4_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_4_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_4_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_4_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h4; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_4_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_4_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_4_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h4; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_4_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_4_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_5_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_5_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_5_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_5_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h5; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_5_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_5_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_5_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h5; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_5_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_5_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_6_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_6_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_6_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_6_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h6; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_6_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_6_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_6_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h6; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_6_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_6_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_7_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_7_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_7_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_7_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_7_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h7; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_7_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_7_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_7_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h7; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_7_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_7_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_8_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_8_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_8_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_8_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_8_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h8; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_8_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_8_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_8_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h8; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_8_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_8_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_9_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_9_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_9_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_9_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_9_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h9; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_9_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_9_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_9_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h9; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_9_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_9_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_10_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_10_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_10_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_10_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'hA; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_10_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_10_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_10_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'hA; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_10_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_10_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_11_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_11_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_11_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_11_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'hB; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_11_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_11_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_11_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'hB; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_11_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_11_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshr_stall_abc_T = _mshrs_0_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_1 = _mshrs_10_io_status_valid & _mshr_stall_abc_T; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_2 = _mshrs_0_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_3 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_2; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_0 = _mshr_stall_abc_T_1 | _mshr_stall_abc_T_3; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_4 = _mshrs_1_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_5 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_4; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_6 = _mshrs_1_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_7 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_6; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_1 = _mshr_stall_abc_T_5 | _mshr_stall_abc_T_7; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_8 = _mshrs_2_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_9 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_8; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_10 = _mshrs_2_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_11 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_10; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_2 = _mshr_stall_abc_T_9 | _mshr_stall_abc_T_11; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_12 = _mshrs_3_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_13 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_12; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_14 = _mshrs_3_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_15 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_14; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_3 = _mshr_stall_abc_T_13 | _mshr_stall_abc_T_15; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_16 = _mshrs_4_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_17 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_16; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_18 = _mshrs_4_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_19 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_18; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_4 = _mshr_stall_abc_T_17 | _mshr_stall_abc_T_19; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_20 = _mshrs_5_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_21 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_20; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_22 = _mshrs_5_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_23 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_22; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_5 = _mshr_stall_abc_T_21 | _mshr_stall_abc_T_23; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_24 = _mshrs_6_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_25 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_24; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_26 = _mshrs_6_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_27 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_26; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_6 = _mshr_stall_abc_T_25 | _mshr_stall_abc_T_27; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_28 = _mshrs_7_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_29 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_28; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_30 = _mshrs_7_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_31 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_30; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_7 = _mshr_stall_abc_T_29 | _mshr_stall_abc_T_31; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_32 = _mshrs_8_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_33 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_32; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_34 = _mshrs_8_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_35 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_34; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_8 = _mshr_stall_abc_T_33 | _mshr_stall_abc_T_35; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_36 = _mshrs_9_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_37 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_36; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_38 = _mshrs_9_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_39 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_38; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_9 = _mshr_stall_abc_T_37 | _mshr_stall_abc_T_39; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_bc_T = _mshrs_10_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :94:58]
wire mshr_stall_bc = _mshrs_11_io_status_valid & _mshr_stall_bc_T; // @[Scheduler.scala:71:46, :94:{28,58}]
wire stall_abc_0 = mshr_stall_abc_0 & _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_1 = mshr_stall_abc_1 & _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_2 = mshr_stall_abc_2 & _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_3 = mshr_stall_abc_3 & _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_4 = mshr_stall_abc_4 & _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_5 = mshr_stall_abc_5 & _mshrs_5_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_6 = mshr_stall_abc_6 & _mshrs_6_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_7 = mshr_stall_abc_7 & _mshrs_7_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_8 = mshr_stall_abc_8 & _mshrs_8_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_9 = mshr_stall_abc_9 & _mshrs_9_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire _mshr_request_T = ~mshr_stall_abc_0; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_1 = _mshrs_0_io_schedule_valid & _mshr_request_T; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_2 = ~_mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_3 = _sourceA_io_req_ready | _mshr_request_T_2; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_4 = _mshr_request_T_1 & _mshr_request_T_3; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_5 = ~_mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_6 = _sourceB_io_req_ready | _mshr_request_T_5; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_7 = _mshr_request_T_4 & _mshr_request_T_6; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_8 = ~_mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_9 = _sourceC_io_req_ready | _mshr_request_T_8; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_10 = _mshr_request_T_7 & _mshr_request_T_9; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_11 = ~_mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_12 = _sourceD_io_req_ready | _mshr_request_T_11; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_13 = _mshr_request_T_10 & _mshr_request_T_12; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_14 = ~_mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_15 = _sourceE_io_req_ready | _mshr_request_T_14; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_16 = _mshr_request_T_13 & _mshr_request_T_15; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_17 = ~_mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_18 = _sourceX_io_req_ready | _mshr_request_T_17; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_19 = _mshr_request_T_16 & _mshr_request_T_18; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_20 = ~_mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_21 = _directory_io_write_ready | _mshr_request_T_20; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_22 = _mshr_request_T_19 & _mshr_request_T_21; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_23 = ~mshr_stall_abc_1; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_24 = _mshrs_1_io_schedule_valid & _mshr_request_T_23; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_25 = ~_mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_26 = _sourceA_io_req_ready | _mshr_request_T_25; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_27 = _mshr_request_T_24 & _mshr_request_T_26; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_28 = ~_mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_29 = _sourceB_io_req_ready | _mshr_request_T_28; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_30 = _mshr_request_T_27 & _mshr_request_T_29; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_31 = ~_mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_32 = _sourceC_io_req_ready | _mshr_request_T_31; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_33 = _mshr_request_T_30 & _mshr_request_T_32; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_34 = ~_mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_35 = _sourceD_io_req_ready | _mshr_request_T_34; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_36 = _mshr_request_T_33 & _mshr_request_T_35; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_37 = ~_mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_38 = _sourceE_io_req_ready | _mshr_request_T_37; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_39 = _mshr_request_T_36 & _mshr_request_T_38; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_40 = ~_mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_41 = _sourceX_io_req_ready | _mshr_request_T_40; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_42 = _mshr_request_T_39 & _mshr_request_T_41; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_43 = ~_mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_44 = _directory_io_write_ready | _mshr_request_T_43; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_45 = _mshr_request_T_42 & _mshr_request_T_44; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_46 = ~mshr_stall_abc_2; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_47 = _mshrs_2_io_schedule_valid & _mshr_request_T_46; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_48 = ~_mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_49 = _sourceA_io_req_ready | _mshr_request_T_48; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_50 = _mshr_request_T_47 & _mshr_request_T_49; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_51 = ~_mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_52 = _sourceB_io_req_ready | _mshr_request_T_51; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_53 = _mshr_request_T_50 & _mshr_request_T_52; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_54 = ~_mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_55 = _sourceC_io_req_ready | _mshr_request_T_54; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_56 = _mshr_request_T_53 & _mshr_request_T_55; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_57 = ~_mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_58 = _sourceD_io_req_ready | _mshr_request_T_57; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_59 = _mshr_request_T_56 & _mshr_request_T_58; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_60 = ~_mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_61 = _sourceE_io_req_ready | _mshr_request_T_60; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_62 = _mshr_request_T_59 & _mshr_request_T_61; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_63 = ~_mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_64 = _sourceX_io_req_ready | _mshr_request_T_63; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_65 = _mshr_request_T_62 & _mshr_request_T_64; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_66 = ~_mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_67 = _directory_io_write_ready | _mshr_request_T_66; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_68 = _mshr_request_T_65 & _mshr_request_T_67; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_69 = ~mshr_stall_abc_3; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_70 = _mshrs_3_io_schedule_valid & _mshr_request_T_69; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_71 = ~_mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_72 = _sourceA_io_req_ready | _mshr_request_T_71; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_73 = _mshr_request_T_70 & _mshr_request_T_72; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_74 = ~_mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_75 = _sourceB_io_req_ready | _mshr_request_T_74; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_76 = _mshr_request_T_73 & _mshr_request_T_75; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_77 = ~_mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_78 = _sourceC_io_req_ready | _mshr_request_T_77; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_79 = _mshr_request_T_76 & _mshr_request_T_78; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_80 = ~_mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_81 = _sourceD_io_req_ready | _mshr_request_T_80; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_82 = _mshr_request_T_79 & _mshr_request_T_81; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_83 = ~_mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_84 = _sourceE_io_req_ready | _mshr_request_T_83; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_85 = _mshr_request_T_82 & _mshr_request_T_84; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_86 = ~_mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_87 = _sourceX_io_req_ready | _mshr_request_T_86; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_88 = _mshr_request_T_85 & _mshr_request_T_87; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_89 = ~_mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_90 = _directory_io_write_ready | _mshr_request_T_89; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_91 = _mshr_request_T_88 & _mshr_request_T_90; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_92 = ~mshr_stall_abc_4; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_93 = _mshrs_4_io_schedule_valid & _mshr_request_T_92; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_94 = ~_mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_95 = _sourceA_io_req_ready | _mshr_request_T_94; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_96 = _mshr_request_T_93 & _mshr_request_T_95; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_97 = ~_mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_98 = _sourceB_io_req_ready | _mshr_request_T_97; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_99 = _mshr_request_T_96 & _mshr_request_T_98; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_100 = ~_mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_101 = _sourceC_io_req_ready | _mshr_request_T_100; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_102 = _mshr_request_T_99 & _mshr_request_T_101; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_103 = ~_mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_104 = _sourceD_io_req_ready | _mshr_request_T_103; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_105 = _mshr_request_T_102 & _mshr_request_T_104; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_106 = ~_mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_107 = _sourceE_io_req_ready | _mshr_request_T_106; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_108 = _mshr_request_T_105 & _mshr_request_T_107; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_109 = ~_mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_110 = _sourceX_io_req_ready | _mshr_request_T_109; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_111 = _mshr_request_T_108 & _mshr_request_T_110; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_112 = ~_mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_113 = _directory_io_write_ready | _mshr_request_T_112; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_114 = _mshr_request_T_111 & _mshr_request_T_113; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_115 = ~mshr_stall_abc_5; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_116 = _mshrs_5_io_schedule_valid & _mshr_request_T_115; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_117 = ~_mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_118 = _sourceA_io_req_ready | _mshr_request_T_117; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_119 = _mshr_request_T_116 & _mshr_request_T_118; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_120 = ~_mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_121 = _sourceB_io_req_ready | _mshr_request_T_120; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_122 = _mshr_request_T_119 & _mshr_request_T_121; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_123 = ~_mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_124 = _sourceC_io_req_ready | _mshr_request_T_123; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_125 = _mshr_request_T_122 & _mshr_request_T_124; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_126 = ~_mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_127 = _sourceD_io_req_ready | _mshr_request_T_126; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_128 = _mshr_request_T_125 & _mshr_request_T_127; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_129 = ~_mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_130 = _sourceE_io_req_ready | _mshr_request_T_129; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_131 = _mshr_request_T_128 & _mshr_request_T_130; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_132 = ~_mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_133 = _sourceX_io_req_ready | _mshr_request_T_132; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_134 = _mshr_request_T_131 & _mshr_request_T_133; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_135 = ~_mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_136 = _directory_io_write_ready | _mshr_request_T_135; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_137 = _mshr_request_T_134 & _mshr_request_T_136; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_138 = ~mshr_stall_abc_6; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_139 = _mshrs_6_io_schedule_valid & _mshr_request_T_138; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_140 = ~_mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_141 = _sourceA_io_req_ready | _mshr_request_T_140; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_142 = _mshr_request_T_139 & _mshr_request_T_141; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_143 = ~_mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_144 = _sourceB_io_req_ready | _mshr_request_T_143; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_145 = _mshr_request_T_142 & _mshr_request_T_144; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_146 = ~_mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_147 = _sourceC_io_req_ready | _mshr_request_T_146; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_148 = _mshr_request_T_145 & _mshr_request_T_147; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_149 = ~_mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_150 = _sourceD_io_req_ready | _mshr_request_T_149; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_151 = _mshr_request_T_148 & _mshr_request_T_150; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_152 = ~_mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_153 = _sourceE_io_req_ready | _mshr_request_T_152; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_154 = _mshr_request_T_151 & _mshr_request_T_153; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_155 = ~_mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_156 = _sourceX_io_req_ready | _mshr_request_T_155; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_157 = _mshr_request_T_154 & _mshr_request_T_156; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_158 = ~_mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_159 = _directory_io_write_ready | _mshr_request_T_158; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_160 = _mshr_request_T_157 & _mshr_request_T_159; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_161 = ~mshr_stall_abc_7; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_162 = _mshrs_7_io_schedule_valid & _mshr_request_T_161; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_163 = ~_mshrs_7_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_164 = _sourceA_io_req_ready | _mshr_request_T_163; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_165 = _mshr_request_T_162 & _mshr_request_T_164; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_166 = ~_mshrs_7_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_167 = _sourceB_io_req_ready | _mshr_request_T_166; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_168 = _mshr_request_T_165 & _mshr_request_T_167; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_169 = ~_mshrs_7_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_170 = _sourceC_io_req_ready | _mshr_request_T_169; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_171 = _mshr_request_T_168 & _mshr_request_T_170; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_172 = ~_mshrs_7_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_173 = _sourceD_io_req_ready | _mshr_request_T_172; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_174 = _mshr_request_T_171 & _mshr_request_T_173; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_175 = ~_mshrs_7_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_176 = _sourceE_io_req_ready | _mshr_request_T_175; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_177 = _mshr_request_T_174 & _mshr_request_T_176; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_178 = ~_mshrs_7_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_179 = _sourceX_io_req_ready | _mshr_request_T_178; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_180 = _mshr_request_T_177 & _mshr_request_T_179; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_181 = ~_mshrs_7_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_182 = _directory_io_write_ready | _mshr_request_T_181; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_183 = _mshr_request_T_180 & _mshr_request_T_182; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_184 = ~mshr_stall_abc_8; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_185 = _mshrs_8_io_schedule_valid & _mshr_request_T_184; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_186 = ~_mshrs_8_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_187 = _sourceA_io_req_ready | _mshr_request_T_186; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_188 = _mshr_request_T_185 & _mshr_request_T_187; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_189 = ~_mshrs_8_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_190 = _sourceB_io_req_ready | _mshr_request_T_189; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_191 = _mshr_request_T_188 & _mshr_request_T_190; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_192 = ~_mshrs_8_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_193 = _sourceC_io_req_ready | _mshr_request_T_192; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_194 = _mshr_request_T_191 & _mshr_request_T_193; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_195 = ~_mshrs_8_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_196 = _sourceD_io_req_ready | _mshr_request_T_195; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_197 = _mshr_request_T_194 & _mshr_request_T_196; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_198 = ~_mshrs_8_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_199 = _sourceE_io_req_ready | _mshr_request_T_198; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_200 = _mshr_request_T_197 & _mshr_request_T_199; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_201 = ~_mshrs_8_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_202 = _sourceX_io_req_ready | _mshr_request_T_201; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_203 = _mshr_request_T_200 & _mshr_request_T_202; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_204 = ~_mshrs_8_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_205 = _directory_io_write_ready | _mshr_request_T_204; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_206 = _mshr_request_T_203 & _mshr_request_T_205; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_207 = ~mshr_stall_abc_9; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_208 = _mshrs_9_io_schedule_valid & _mshr_request_T_207; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_209 = ~_mshrs_9_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_210 = _sourceA_io_req_ready | _mshr_request_T_209; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_211 = _mshr_request_T_208 & _mshr_request_T_210; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_212 = ~_mshrs_9_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_213 = _sourceB_io_req_ready | _mshr_request_T_212; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_214 = _mshr_request_T_211 & _mshr_request_T_213; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_215 = ~_mshrs_9_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_216 = _sourceC_io_req_ready | _mshr_request_T_215; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_217 = _mshr_request_T_214 & _mshr_request_T_216; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_218 = ~_mshrs_9_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_219 = _sourceD_io_req_ready | _mshr_request_T_218; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_220 = _mshr_request_T_217 & _mshr_request_T_219; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_221 = ~_mshrs_9_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_222 = _sourceE_io_req_ready | _mshr_request_T_221; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_223 = _mshr_request_T_220 & _mshr_request_T_222; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_224 = ~_mshrs_9_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_225 = _sourceX_io_req_ready | _mshr_request_T_224; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_226 = _mshr_request_T_223 & _mshr_request_T_225; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_227 = ~_mshrs_9_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_228 = _directory_io_write_ready | _mshr_request_T_227; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_229 = _mshr_request_T_226 & _mshr_request_T_228; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_230 = ~mshr_stall_bc; // @[Scheduler.scala:94:28, :107:28]
wire _mshr_request_T_231 = _mshrs_10_io_schedule_valid & _mshr_request_T_230; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_232 = ~_mshrs_10_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_233 = _sourceA_io_req_ready | _mshr_request_T_232; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_234 = _mshr_request_T_231 & _mshr_request_T_233; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_235 = ~_mshrs_10_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_236 = _sourceB_io_req_ready | _mshr_request_T_235; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_237 = _mshr_request_T_234 & _mshr_request_T_236; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_238 = ~_mshrs_10_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_239 = _sourceC_io_req_ready | _mshr_request_T_238; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_240 = _mshr_request_T_237 & _mshr_request_T_239; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_241 = ~_mshrs_10_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_242 = _sourceD_io_req_ready | _mshr_request_T_241; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_243 = _mshr_request_T_240 & _mshr_request_T_242; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_244 = ~_mshrs_10_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_245 = _sourceE_io_req_ready | _mshr_request_T_244; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_246 = _mshr_request_T_243 & _mshr_request_T_245; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_247 = ~_mshrs_10_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_248 = _sourceX_io_req_ready | _mshr_request_T_247; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_249 = _mshr_request_T_246 & _mshr_request_T_248; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_250 = ~_mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_251 = _directory_io_write_ready | _mshr_request_T_250; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_252 = _mshr_request_T_249 & _mshr_request_T_251; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_255 = ~_mshrs_11_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_256 = _sourceA_io_req_ready | _mshr_request_T_255; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_254; // @[Scheduler.scala:107:25]
wire _mshr_request_T_257 = _mshr_request_T_254 & _mshr_request_T_256; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_258 = ~_mshrs_11_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_259 = _sourceB_io_req_ready | _mshr_request_T_258; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_260 = _mshr_request_T_257 & _mshr_request_T_259; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_261 = ~_mshrs_11_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_262 = _sourceC_io_req_ready | _mshr_request_T_261; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_263 = _mshr_request_T_260 & _mshr_request_T_262; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_264 = ~_mshrs_11_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_265 = _sourceD_io_req_ready | _mshr_request_T_264; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_266 = _mshr_request_T_263 & _mshr_request_T_265; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_267 = ~_mshrs_11_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_268 = _sourceE_io_req_ready | _mshr_request_T_267; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_269 = _mshr_request_T_266 & _mshr_request_T_268; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_270 = ~_mshrs_11_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_271 = _sourceX_io_req_ready | _mshr_request_T_270; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_272 = _mshr_request_T_269 & _mshr_request_T_271; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_273 = ~_mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_274 = _directory_io_write_ready | _mshr_request_T_273; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_275 = _mshr_request_T_272 & _mshr_request_T_274; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire [1:0] mshr_request_lo_lo_hi = {_mshr_request_T_68, _mshr_request_T_45}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_lo_lo = {mshr_request_lo_lo_hi, _mshr_request_T_22}; // @[Scheduler.scala:106:25, :113:61]
wire [1:0] mshr_request_lo_hi_hi = {_mshr_request_T_137, _mshr_request_T_114}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_lo_hi = {mshr_request_lo_hi_hi, _mshr_request_T_91}; // @[Scheduler.scala:106:25, :113:61]
wire [5:0] mshr_request_lo = {mshr_request_lo_hi, mshr_request_lo_lo}; // @[Scheduler.scala:106:25]
wire [1:0] mshr_request_hi_lo_hi = {_mshr_request_T_206, _mshr_request_T_183}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_hi_lo = {mshr_request_hi_lo_hi, _mshr_request_T_160}; // @[Scheduler.scala:106:25, :113:61]
wire [1:0] mshr_request_hi_hi_hi = {_mshr_request_T_275, _mshr_request_T_252}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_hi_hi = {mshr_request_hi_hi_hi, _mshr_request_T_229}; // @[Scheduler.scala:106:25, :113:61]
wire [5:0] mshr_request_hi = {mshr_request_hi_hi, mshr_request_hi_lo}; // @[Scheduler.scala:106:25]
wire [11:0] mshr_request = {mshr_request_hi, mshr_request_lo}; // @[Scheduler.scala:106:25]
reg [11:0] robin_filter; // @[Scheduler.scala:118:29]
wire [11:0] _robin_request_T = mshr_request & robin_filter; // @[Scheduler.scala:106:25, :118:29, :119:54]
wire [23:0] robin_request = {mshr_request, _robin_request_T}; // @[Scheduler.scala:106:25, :119:{26,54}]
wire [24:0] _mshr_selectOH2_T = {robin_request, 1'h0}; // @[package.scala:253:48]
wire [23:0] _mshr_selectOH2_T_1 = _mshr_selectOH2_T[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_2 = robin_request | _mshr_selectOH2_T_1; // @[package.scala:253:{43,53}]
wire [25:0] _mshr_selectOH2_T_3 = {_mshr_selectOH2_T_2, 2'h0}; // @[package.scala:253:{43,48}]
wire [23:0] _mshr_selectOH2_T_4 = _mshr_selectOH2_T_3[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_5 = _mshr_selectOH2_T_2 | _mshr_selectOH2_T_4; // @[package.scala:253:{43,53}]
wire [27:0] _mshr_selectOH2_T_6 = {_mshr_selectOH2_T_5, 4'h0}; // @[package.scala:253:{43,48}]
wire [23:0] _mshr_selectOH2_T_7 = _mshr_selectOH2_T_6[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_8 = _mshr_selectOH2_T_5 | _mshr_selectOH2_T_7; // @[package.scala:253:{43,53}]
wire [31:0] _mshr_selectOH2_T_9 = {_mshr_selectOH2_T_8, 8'h0}; // @[package.scala:253:{43,48}]
wire [23:0] _mshr_selectOH2_T_10 = _mshr_selectOH2_T_9[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_11 = _mshr_selectOH2_T_8 | _mshr_selectOH2_T_10; // @[package.scala:253:{43,53}]
wire [39:0] _mshr_selectOH2_T_12 = {_mshr_selectOH2_T_11, 16'h0}; // @[package.scala:253:{43,48}]
wire [23:0] _mshr_selectOH2_T_13 = _mshr_selectOH2_T_12[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_14 = _mshr_selectOH2_T_11 | _mshr_selectOH2_T_13; // @[package.scala:253:{43,53}]
wire [23:0] _mshr_selectOH2_T_15 = _mshr_selectOH2_T_14; // @[package.scala:253:43, :254:17]
wire [24:0] _mshr_selectOH2_T_16 = {_mshr_selectOH2_T_15, 1'h0}; // @[package.scala:254:17]
wire [24:0] _mshr_selectOH2_T_17 = ~_mshr_selectOH2_T_16; // @[Scheduler.scala:120:{24,48}]
wire [24:0] mshr_selectOH2 = {1'h0, _mshr_selectOH2_T_17[23:0] & robin_request}; // @[Scheduler.scala:119:26, :120:{24,54}]
wire [11:0] _mshr_selectOH_T = mshr_selectOH2[23:12]; // @[Scheduler.scala:120:54, :121:37]
wire [11:0] _mshr_selectOH_T_1 = mshr_selectOH2[11:0]; // @[Scheduler.scala:120:54, :121:86]
wire [11:0] mshr_selectOH = _mshr_selectOH_T | _mshr_selectOH_T_1; // @[Scheduler.scala:121:{37,70,86}]
wire [3:0] mshr_select_hi = mshr_selectOH[11:8]; // @[OneHot.scala:30:18]
wire [7:0] mshr_select_lo = mshr_selectOH[7:0]; // @[OneHot.scala:31:18]
wire _mshr_select_T = |mshr_select_hi; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _mshr_select_T_1 = {4'h0, mshr_select_hi} | mshr_select_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] mshr_select_hi_1 = _mshr_select_T_1[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] mshr_select_lo_1 = _mshr_select_T_1[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _mshr_select_T_2 = |mshr_select_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _mshr_select_T_3 = mshr_select_hi_1 | mshr_select_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] mshr_select_hi_2 = _mshr_select_T_3[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] mshr_select_lo_2 = _mshr_select_T_3[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _mshr_select_T_4 = |mshr_select_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _mshr_select_T_5 = mshr_select_hi_2 | mshr_select_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _mshr_select_T_6 = _mshr_select_T_5[1]; // @[OneHot.scala:32:28]
wire [1:0] _mshr_select_T_7 = {_mshr_select_T_4, _mshr_select_T_6}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _mshr_select_T_8 = {_mshr_select_T_2, _mshr_select_T_7}; // @[OneHot.scala:32:{10,14}]
wire [3:0] mshr_select = {_mshr_select_T, _mshr_select_T_8}; // @[OneHot.scala:32:{10,14}]
wire [3:0] schedule_a_bits_source = mshr_select; // @[OneHot.scala:32:10]
wire [3:0] schedule_d_bits_sink = mshr_select; // @[OneHot.scala:32:10]
wire _schedule_T = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire _scheduleTag_T = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire _scheduleSet_T = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire sel = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire _schedule_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire _scheduleTag_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire _scheduleSet_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire sel_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire _schedule_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire _scheduleTag_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire _scheduleSet_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire sel_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire _schedule_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire _scheduleTag_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire _scheduleSet_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire sel_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire _schedule_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire _scheduleTag_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire _scheduleSet_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire sel_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire _schedule_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire _scheduleTag_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire _scheduleSet_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire sel_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire _schedule_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire _scheduleTag_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire _scheduleSet_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire sel_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire _schedule_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36]
wire _scheduleTag_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36]
wire _scheduleSet_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36]
wire sel_7 = mshr_selectOH[7]; // @[Mux.scala:32:36]
wire _schedule_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36]
wire _scheduleTag_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36]
wire _scheduleSet_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36]
wire sel_8 = mshr_selectOH[8]; // @[Mux.scala:32:36]
wire _schedule_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36]
wire _scheduleTag_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36]
wire _scheduleSet_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36]
wire sel_9 = mshr_selectOH[9]; // @[Mux.scala:32:36]
wire _schedule_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire _scheduleTag_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire _scheduleSet_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire select_bc = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire sel_10 = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire _schedule_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire _scheduleTag_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire _scheduleSet_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire select_c = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire sel_11 = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire _schedule_WIRE_55_valid; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73]
wire _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73]
wire _schedule_WIRE_48_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73]
wire _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73]
wire _schedule_WIRE_38_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73]
wire [3:0] _schedule_c_bits_source_T_1; // @[Scheduler.scala:132:32]
wire [8:0] _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_valid; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73]
wire _schedule_WIRE_15_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73]
wire _schedule_WIRE_11_valid; // @[Mux.scala:30:73]
wire _schedule_WIRE_1_valid; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73]
wire _schedule_WIRE; // @[Mux.scala:30:73]
wire [8:0] schedule_a_bits_tag; // @[Mux.scala:30:73]
wire [10:0] schedule_a_bits_set; // @[Mux.scala:30:73]
wire [2:0] schedule_a_bits_param; // @[Mux.scala:30:73]
wire schedule_a_bits_block; // @[Mux.scala:30:73]
wire schedule_a_valid; // @[Mux.scala:30:73]
wire [2:0] schedule_b_bits_param; // @[Mux.scala:30:73]
wire [8:0] schedule_b_bits_tag; // @[Mux.scala:30:73]
wire [10:0] schedule_b_bits_set; // @[Mux.scala:30:73]
wire schedule_b_bits_clients; // @[Mux.scala:30:73]
wire schedule_b_valid; // @[Mux.scala:30:73]
wire [2:0] schedule_c_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] schedule_c_bits_param; // @[Mux.scala:30:73]
wire [3:0] schedule_c_bits_source; // @[Mux.scala:30:73]
wire [8:0] schedule_c_bits_tag; // @[Mux.scala:30:73]
wire [10:0] schedule_c_bits_set; // @[Mux.scala:30:73]
wire [3:0] schedule_c_bits_way; // @[Mux.scala:30:73]
wire schedule_c_bits_dirty; // @[Mux.scala:30:73]
wire schedule_c_valid; // @[Mux.scala:30:73]
wire schedule_d_bits_prio_0; // @[Mux.scala:30:73]
wire schedule_d_bits_prio_1; // @[Mux.scala:30:73]
wire schedule_d_bits_prio_2; // @[Mux.scala:30:73]
wire schedule_d_bits_control; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_param; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_size; // @[Mux.scala:30:73]
wire [5:0] schedule_d_bits_source; // @[Mux.scala:30:73]
wire [8:0] schedule_d_bits_tag; // @[Mux.scala:30:73]
wire [5:0] schedule_d_bits_offset; // @[Mux.scala:30:73]
wire [5:0] schedule_d_bits_put; // @[Mux.scala:30:73]
wire [10:0] schedule_d_bits_set; // @[Mux.scala:30:73]
wire [3:0] schedule_d_bits_way; // @[Mux.scala:30:73]
wire schedule_d_bits_bad; // @[Mux.scala:30:73]
wire schedule_d_valid; // @[Mux.scala:30:73]
wire [2:0] schedule_e_bits_sink; // @[Mux.scala:30:73]
wire schedule_e_valid; // @[Mux.scala:30:73]
wire schedule_x_valid; // @[Mux.scala:30:73]
wire schedule_dir_bits_data_dirty; // @[Mux.scala:30:73]
wire [1:0] schedule_dir_bits_data_state; // @[Mux.scala:30:73]
wire schedule_dir_bits_data_clients; // @[Mux.scala:30:73]
wire [8:0] schedule_dir_bits_data_tag; // @[Mux.scala:30:73]
wire [10:0] schedule_dir_bits_set; // @[Mux.scala:30:73]
wire [3:0] schedule_dir_bits_way; // @[Mux.scala:30:73]
wire schedule_dir_valid; // @[Mux.scala:30:73]
wire schedule_reload; // @[Mux.scala:30:73]
wire _schedule_T_12 = _schedule_T & _mshrs_0_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_13 = _schedule_T_1 & _mshrs_1_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_14 = _schedule_T_2 & _mshrs_2_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_15 = _schedule_T_3 & _mshrs_3_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_16 = _schedule_T_4 & _mshrs_4_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_17 = _schedule_T_5 & _mshrs_5_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_18 = _schedule_T_6 & _mshrs_6_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_19 = _schedule_T_7 & _mshrs_7_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_20 = _schedule_T_8 & _mshrs_8_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_21 = _schedule_T_9 & _mshrs_9_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_22 = _schedule_T_10 & _mshrs_10_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_23 = _schedule_T_11 & _mshrs_11_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_24 = _schedule_T_12 | _schedule_T_13; // @[Mux.scala:30:73]
wire _schedule_T_25 = _schedule_T_24 | _schedule_T_14; // @[Mux.scala:30:73]
wire _schedule_T_26 = _schedule_T_25 | _schedule_T_15; // @[Mux.scala:30:73]
wire _schedule_T_27 = _schedule_T_26 | _schedule_T_16; // @[Mux.scala:30:73]
wire _schedule_T_28 = _schedule_T_27 | _schedule_T_17; // @[Mux.scala:30:73]
wire _schedule_T_29 = _schedule_T_28 | _schedule_T_18; // @[Mux.scala:30:73]
wire _schedule_T_30 = _schedule_T_29 | _schedule_T_19; // @[Mux.scala:30:73]
wire _schedule_T_31 = _schedule_T_30 | _schedule_T_20; // @[Mux.scala:30:73]
wire _schedule_T_32 = _schedule_T_31 | _schedule_T_21; // @[Mux.scala:30:73]
wire _schedule_T_33 = _schedule_T_32 | _schedule_T_22; // @[Mux.scala:30:73]
wire _schedule_T_34 = _schedule_T_33 | _schedule_T_23; // @[Mux.scala:30:73]
assign _schedule_WIRE = _schedule_T_34; // @[Mux.scala:30:73]
assign schedule_reload = _schedule_WIRE; // @[Mux.scala:30:73]
wire _schedule_WIRE_10; // @[Mux.scala:30:73]
assign schedule_dir_valid = _schedule_WIRE_1_valid; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_2_set; // @[Mux.scala:30:73]
assign schedule_dir_bits_set = _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_2_way; // @[Mux.scala:30:73]
assign schedule_dir_bits_way = _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_dirty = _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_2_data_state; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_state = _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_clients = _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_tag = _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_9; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_set = _schedule_WIRE_2_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_8; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_way = _schedule_WIRE_2_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_3_dirty; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_dirty = _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_3_state; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_state = _schedule_WIRE_2_data_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_3_clients; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_clients = _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_3_tag; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_tag = _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73]
wire _schedule_WIRE_7; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_dirty = _schedule_WIRE_3_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_6; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_state = _schedule_WIRE_3_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_5; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_clients = _schedule_WIRE_3_clients; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_4; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_tag = _schedule_WIRE_3_tag; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_35 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_36 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_37 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_38 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_39 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_40 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_41 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_42 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_43 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_44 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_45 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_46 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_47 = _schedule_T_35 | _schedule_T_36; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_48 = _schedule_T_47 | _schedule_T_37; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_49 = _schedule_T_48 | _schedule_T_38; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_50 = _schedule_T_49 | _schedule_T_39; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_51 = _schedule_T_50 | _schedule_T_40; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_52 = _schedule_T_51 | _schedule_T_41; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_53 = _schedule_T_52 | _schedule_T_42; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_54 = _schedule_T_53 | _schedule_T_43; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_55 = _schedule_T_54 | _schedule_T_44; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_56 = _schedule_T_55 | _schedule_T_45; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_57 = _schedule_T_56 | _schedule_T_46; // @[Mux.scala:30:73]
assign _schedule_WIRE_4 = _schedule_T_57; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_tag = _schedule_WIRE_4; // @[Mux.scala:30:73]
wire _schedule_T_58 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_59 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_60 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_61 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_62 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_63 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_64 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_65 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_66 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_67 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_68 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_69 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_70 = _schedule_T_58 | _schedule_T_59; // @[Mux.scala:30:73]
wire _schedule_T_71 = _schedule_T_70 | _schedule_T_60; // @[Mux.scala:30:73]
wire _schedule_T_72 = _schedule_T_71 | _schedule_T_61; // @[Mux.scala:30:73]
wire _schedule_T_73 = _schedule_T_72 | _schedule_T_62; // @[Mux.scala:30:73]
wire _schedule_T_74 = _schedule_T_73 | _schedule_T_63; // @[Mux.scala:30:73]
wire _schedule_T_75 = _schedule_T_74 | _schedule_T_64; // @[Mux.scala:30:73]
wire _schedule_T_76 = _schedule_T_75 | _schedule_T_65; // @[Mux.scala:30:73]
wire _schedule_T_77 = _schedule_T_76 | _schedule_T_66; // @[Mux.scala:30:73]
wire _schedule_T_78 = _schedule_T_77 | _schedule_T_67; // @[Mux.scala:30:73]
wire _schedule_T_79 = _schedule_T_78 | _schedule_T_68; // @[Mux.scala:30:73]
wire _schedule_T_80 = _schedule_T_79 | _schedule_T_69; // @[Mux.scala:30:73]
assign _schedule_WIRE_5 = _schedule_T_80; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_clients = _schedule_WIRE_5; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_81 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_82 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_83 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_84 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_85 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_86 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_87 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_88 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_89 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_90 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_91 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_92 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_93 = _schedule_T_81 | _schedule_T_82; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_94 = _schedule_T_93 | _schedule_T_83; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_95 = _schedule_T_94 | _schedule_T_84; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_96 = _schedule_T_95 | _schedule_T_85; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_97 = _schedule_T_96 | _schedule_T_86; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_98 = _schedule_T_97 | _schedule_T_87; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_99 = _schedule_T_98 | _schedule_T_88; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_100 = _schedule_T_99 | _schedule_T_89; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_101 = _schedule_T_100 | _schedule_T_90; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_102 = _schedule_T_101 | _schedule_T_91; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_103 = _schedule_T_102 | _schedule_T_92; // @[Mux.scala:30:73]
assign _schedule_WIRE_6 = _schedule_T_103; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_state = _schedule_WIRE_6; // @[Mux.scala:30:73]
wire _schedule_T_104 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_105 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_106 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_107 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_108 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_109 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_110 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_111 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_112 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_113 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_114 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_115 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_116 = _schedule_T_104 | _schedule_T_105; // @[Mux.scala:30:73]
wire _schedule_T_117 = _schedule_T_116 | _schedule_T_106; // @[Mux.scala:30:73]
wire _schedule_T_118 = _schedule_T_117 | _schedule_T_107; // @[Mux.scala:30:73]
wire _schedule_T_119 = _schedule_T_118 | _schedule_T_108; // @[Mux.scala:30:73]
wire _schedule_T_120 = _schedule_T_119 | _schedule_T_109; // @[Mux.scala:30:73]
wire _schedule_T_121 = _schedule_T_120 | _schedule_T_110; // @[Mux.scala:30:73]
wire _schedule_T_122 = _schedule_T_121 | _schedule_T_111; // @[Mux.scala:30:73]
wire _schedule_T_123 = _schedule_T_122 | _schedule_T_112; // @[Mux.scala:30:73]
wire _schedule_T_124 = _schedule_T_123 | _schedule_T_113; // @[Mux.scala:30:73]
wire _schedule_T_125 = _schedule_T_124 | _schedule_T_114; // @[Mux.scala:30:73]
wire _schedule_T_126 = _schedule_T_125 | _schedule_T_115; // @[Mux.scala:30:73]
assign _schedule_WIRE_7 = _schedule_T_126; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_dirty = _schedule_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_127 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_128 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_129 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_130 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_131 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_132 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_133 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_134 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_135 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_136 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_137 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_138 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_139 = _schedule_T_127 | _schedule_T_128; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_140 = _schedule_T_139 | _schedule_T_129; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_141 = _schedule_T_140 | _schedule_T_130; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_142 = _schedule_T_141 | _schedule_T_131; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_143 = _schedule_T_142 | _schedule_T_132; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_144 = _schedule_T_143 | _schedule_T_133; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_145 = _schedule_T_144 | _schedule_T_134; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_146 = _schedule_T_145 | _schedule_T_135; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_147 = _schedule_T_146 | _schedule_T_136; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_148 = _schedule_T_147 | _schedule_T_137; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_149 = _schedule_T_148 | _schedule_T_138; // @[Mux.scala:30:73]
assign _schedule_WIRE_8 = _schedule_T_149; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_way = _schedule_WIRE_8; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_150 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_151 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_152 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_153 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_154 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_155 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_156 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_157 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_158 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_159 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_160 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_161 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_162 = _schedule_T_150 | _schedule_T_151; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_163 = _schedule_T_162 | _schedule_T_152; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_164 = _schedule_T_163 | _schedule_T_153; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_165 = _schedule_T_164 | _schedule_T_154; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_166 = _schedule_T_165 | _schedule_T_155; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_167 = _schedule_T_166 | _schedule_T_156; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_168 = _schedule_T_167 | _schedule_T_157; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_169 = _schedule_T_168 | _schedule_T_158; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_170 = _schedule_T_169 | _schedule_T_159; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_171 = _schedule_T_170 | _schedule_T_160; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_172 = _schedule_T_171 | _schedule_T_161; // @[Mux.scala:30:73]
assign _schedule_WIRE_9 = _schedule_T_172; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_set = _schedule_WIRE_9; // @[Mux.scala:30:73]
wire _schedule_T_173 = _schedule_T & _mshrs_0_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_174 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_175 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_176 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_177 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_178 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_179 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_180 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_181 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_182 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_183 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_184 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_185 = _schedule_T_173 | _schedule_T_174; // @[Mux.scala:30:73]
wire _schedule_T_186 = _schedule_T_185 | _schedule_T_175; // @[Mux.scala:30:73]
wire _schedule_T_187 = _schedule_T_186 | _schedule_T_176; // @[Mux.scala:30:73]
wire _schedule_T_188 = _schedule_T_187 | _schedule_T_177; // @[Mux.scala:30:73]
wire _schedule_T_189 = _schedule_T_188 | _schedule_T_178; // @[Mux.scala:30:73]
wire _schedule_T_190 = _schedule_T_189 | _schedule_T_179; // @[Mux.scala:30:73]
wire _schedule_T_191 = _schedule_T_190 | _schedule_T_180; // @[Mux.scala:30:73]
wire _schedule_T_192 = _schedule_T_191 | _schedule_T_181; // @[Mux.scala:30:73]
wire _schedule_T_193 = _schedule_T_192 | _schedule_T_182; // @[Mux.scala:30:73]
wire _schedule_T_194 = _schedule_T_193 | _schedule_T_183; // @[Mux.scala:30:73]
wire _schedule_T_195 = _schedule_T_194 | _schedule_T_184; // @[Mux.scala:30:73]
assign _schedule_WIRE_10 = _schedule_T_195; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_valid = _schedule_WIRE_10; // @[Mux.scala:30:73]
wire _schedule_WIRE_14; // @[Mux.scala:30:73]
assign schedule_x_valid = _schedule_WIRE_11_valid; // @[Mux.scala:30:73]
wire _schedule_T_219 = _schedule_T & _mshrs_0_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_220 = _schedule_T_1 & _mshrs_1_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_221 = _schedule_T_2 & _mshrs_2_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_222 = _schedule_T_3 & _mshrs_3_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_223 = _schedule_T_4 & _mshrs_4_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_224 = _schedule_T_5 & _mshrs_5_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_225 = _schedule_T_6 & _mshrs_6_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_226 = _schedule_T_7 & _mshrs_7_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_227 = _schedule_T_8 & _mshrs_8_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_228 = _schedule_T_9 & _mshrs_9_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_229 = _schedule_T_10 & _mshrs_10_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_230 = _schedule_T_11 & _mshrs_11_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_231 = _schedule_T_219 | _schedule_T_220; // @[Mux.scala:30:73]
wire _schedule_T_232 = _schedule_T_231 | _schedule_T_221; // @[Mux.scala:30:73]
wire _schedule_T_233 = _schedule_T_232 | _schedule_T_222; // @[Mux.scala:30:73]
wire _schedule_T_234 = _schedule_T_233 | _schedule_T_223; // @[Mux.scala:30:73]
wire _schedule_T_235 = _schedule_T_234 | _schedule_T_224; // @[Mux.scala:30:73]
wire _schedule_T_236 = _schedule_T_235 | _schedule_T_225; // @[Mux.scala:30:73]
wire _schedule_T_237 = _schedule_T_236 | _schedule_T_226; // @[Mux.scala:30:73]
wire _schedule_T_238 = _schedule_T_237 | _schedule_T_227; // @[Mux.scala:30:73]
wire _schedule_T_239 = _schedule_T_238 | _schedule_T_228; // @[Mux.scala:30:73]
wire _schedule_T_240 = _schedule_T_239 | _schedule_T_229; // @[Mux.scala:30:73]
wire _schedule_T_241 = _schedule_T_240 | _schedule_T_230; // @[Mux.scala:30:73]
assign _schedule_WIRE_14 = _schedule_T_241; // @[Mux.scala:30:73]
assign _schedule_WIRE_11_valid = _schedule_WIRE_14; // @[Mux.scala:30:73]
wire _schedule_WIRE_18; // @[Mux.scala:30:73]
assign schedule_e_valid = _schedule_WIRE_15_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_16_sink; // @[Mux.scala:30:73]
assign schedule_e_bits_sink = _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_17; // @[Mux.scala:30:73]
assign _schedule_WIRE_15_bits_sink = _schedule_WIRE_16_sink; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_242 = _schedule_T ? _mshrs_0_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_243 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_244 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_245 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_246 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_247 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_248 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_249 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_250 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_251 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_252 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_253 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_254 = _schedule_T_242 | _schedule_T_243; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_255 = _schedule_T_254 | _schedule_T_244; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_256 = _schedule_T_255 | _schedule_T_245; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_257 = _schedule_T_256 | _schedule_T_246; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_258 = _schedule_T_257 | _schedule_T_247; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_259 = _schedule_T_258 | _schedule_T_248; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_260 = _schedule_T_259 | _schedule_T_249; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_261 = _schedule_T_260 | _schedule_T_250; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_262 = _schedule_T_261 | _schedule_T_251; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_263 = _schedule_T_262 | _schedule_T_252; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_264 = _schedule_T_263 | _schedule_T_253; // @[Mux.scala:30:73]
assign _schedule_WIRE_17 = _schedule_T_264; // @[Mux.scala:30:73]
assign _schedule_WIRE_16_sink = _schedule_WIRE_17; // @[Mux.scala:30:73]
wire _schedule_T_265 = _schedule_T & _mshrs_0_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_266 = _schedule_T_1 & _mshrs_1_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_267 = _schedule_T_2 & _mshrs_2_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_268 = _schedule_T_3 & _mshrs_3_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_269 = _schedule_T_4 & _mshrs_4_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_270 = _schedule_T_5 & _mshrs_5_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_271 = _schedule_T_6 & _mshrs_6_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_272 = _schedule_T_7 & _mshrs_7_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_273 = _schedule_T_8 & _mshrs_8_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_274 = _schedule_T_9 & _mshrs_9_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_275 = _schedule_T_10 & _mshrs_10_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_276 = _schedule_T_11 & _mshrs_11_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_277 = _schedule_T_265 | _schedule_T_266; // @[Mux.scala:30:73]
wire _schedule_T_278 = _schedule_T_277 | _schedule_T_267; // @[Mux.scala:30:73]
wire _schedule_T_279 = _schedule_T_278 | _schedule_T_268; // @[Mux.scala:30:73]
wire _schedule_T_280 = _schedule_T_279 | _schedule_T_269; // @[Mux.scala:30:73]
wire _schedule_T_281 = _schedule_T_280 | _schedule_T_270; // @[Mux.scala:30:73]
wire _schedule_T_282 = _schedule_T_281 | _schedule_T_271; // @[Mux.scala:30:73]
wire _schedule_T_283 = _schedule_T_282 | _schedule_T_272; // @[Mux.scala:30:73]
wire _schedule_T_284 = _schedule_T_283 | _schedule_T_273; // @[Mux.scala:30:73]
wire _schedule_T_285 = _schedule_T_284 | _schedule_T_274; // @[Mux.scala:30:73]
wire _schedule_T_286 = _schedule_T_285 | _schedule_T_275; // @[Mux.scala:30:73]
wire _schedule_T_287 = _schedule_T_286 | _schedule_T_276; // @[Mux.scala:30:73]
assign _schedule_WIRE_18 = _schedule_T_287; // @[Mux.scala:30:73]
assign _schedule_WIRE_15_valid = _schedule_WIRE_18; // @[Mux.scala:30:73]
wire _schedule_WIRE_37; // @[Mux.scala:30:73]
assign schedule_d_valid = _schedule_WIRE_19_valid; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73]
assign schedule_d_bits_prio_0 = _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73]
assign schedule_d_bits_prio_1 = _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73]
assign schedule_d_bits_prio_2 = _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_control; // @[Mux.scala:30:73]
assign schedule_d_bits_control = _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_opcode; // @[Mux.scala:30:73]
assign schedule_d_bits_opcode = _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_param; // @[Mux.scala:30:73]
assign schedule_d_bits_param = _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_size; // @[Mux.scala:30:73]
assign schedule_d_bits_size = _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_20_source; // @[Mux.scala:30:73]
assign schedule_d_bits_source = _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_20_tag; // @[Mux.scala:30:73]
assign schedule_d_bits_tag = _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_20_offset; // @[Mux.scala:30:73]
assign schedule_d_bits_offset = _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_20_put; // @[Mux.scala:30:73]
assign schedule_d_bits_put = _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_20_set; // @[Mux.scala:30:73]
assign schedule_d_bits_set = _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_20_way; // @[Mux.scala:30:73]
assign schedule_d_bits_way = _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_bad; // @[Mux.scala:30:73]
assign schedule_d_bits_bad = _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73]
wire _schedule_WIRE_33_0; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_prio_0 = _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_33_1; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_prio_1 = _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_33_2; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_prio_2 = _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73]
wire _schedule_WIRE_32; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_control = _schedule_WIRE_20_control; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_31; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_opcode = _schedule_WIRE_20_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_30; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_param = _schedule_WIRE_20_param; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_29; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_size = _schedule_WIRE_20_size; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_28; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_source = _schedule_WIRE_20_source; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_27; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_tag = _schedule_WIRE_20_tag; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_26; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_offset = _schedule_WIRE_20_offset; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_25; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_put = _schedule_WIRE_20_put; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_24; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_set = _schedule_WIRE_20_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_22; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_way = _schedule_WIRE_20_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_21; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_bad = _schedule_WIRE_20_bad; // @[Mux.scala:30:73]
wire _schedule_T_288 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_289 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_290 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_291 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_292 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_293 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_294 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_295 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_296 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_297 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_298 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_299 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_300 = _schedule_T_288 | _schedule_T_289; // @[Mux.scala:30:73]
wire _schedule_T_301 = _schedule_T_300 | _schedule_T_290; // @[Mux.scala:30:73]
wire _schedule_T_302 = _schedule_T_301 | _schedule_T_291; // @[Mux.scala:30:73]
wire _schedule_T_303 = _schedule_T_302 | _schedule_T_292; // @[Mux.scala:30:73]
wire _schedule_T_304 = _schedule_T_303 | _schedule_T_293; // @[Mux.scala:30:73]
wire _schedule_T_305 = _schedule_T_304 | _schedule_T_294; // @[Mux.scala:30:73]
wire _schedule_T_306 = _schedule_T_305 | _schedule_T_295; // @[Mux.scala:30:73]
wire _schedule_T_307 = _schedule_T_306 | _schedule_T_296; // @[Mux.scala:30:73]
wire _schedule_T_308 = _schedule_T_307 | _schedule_T_297; // @[Mux.scala:30:73]
wire _schedule_T_309 = _schedule_T_308 | _schedule_T_298; // @[Mux.scala:30:73]
wire _schedule_T_310 = _schedule_T_309 | _schedule_T_299; // @[Mux.scala:30:73]
assign _schedule_WIRE_21 = _schedule_T_310; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_bad = _schedule_WIRE_21; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_311 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_312 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_313 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_314 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_315 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_316 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_317 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_318 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_319 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_320 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_321 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_322 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_323 = _schedule_T_311 | _schedule_T_312; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_324 = _schedule_T_323 | _schedule_T_313; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_325 = _schedule_T_324 | _schedule_T_314; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_326 = _schedule_T_325 | _schedule_T_315; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_327 = _schedule_T_326 | _schedule_T_316; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_328 = _schedule_T_327 | _schedule_T_317; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_329 = _schedule_T_328 | _schedule_T_318; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_330 = _schedule_T_329 | _schedule_T_319; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_331 = _schedule_T_330 | _schedule_T_320; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_332 = _schedule_T_331 | _schedule_T_321; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_333 = _schedule_T_332 | _schedule_T_322; // @[Mux.scala:30:73]
assign _schedule_WIRE_22 = _schedule_T_333; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_way = _schedule_WIRE_22; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_357 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_358 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_359 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_360 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_361 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_362 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_363 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_364 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_365 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_366 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_367 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_368 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_369 = _schedule_T_357 | _schedule_T_358; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_370 = _schedule_T_369 | _schedule_T_359; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_371 = _schedule_T_370 | _schedule_T_360; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_372 = _schedule_T_371 | _schedule_T_361; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_373 = _schedule_T_372 | _schedule_T_362; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_374 = _schedule_T_373 | _schedule_T_363; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_375 = _schedule_T_374 | _schedule_T_364; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_376 = _schedule_T_375 | _schedule_T_365; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_377 = _schedule_T_376 | _schedule_T_366; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_378 = _schedule_T_377 | _schedule_T_367; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_379 = _schedule_T_378 | _schedule_T_368; // @[Mux.scala:30:73]
assign _schedule_WIRE_24 = _schedule_T_379; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_set = _schedule_WIRE_24; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_380 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_381 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_382 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_383 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_384 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_385 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_386 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_387 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_388 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_389 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_390 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_391 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_392 = _schedule_T_380 | _schedule_T_381; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_393 = _schedule_T_392 | _schedule_T_382; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_394 = _schedule_T_393 | _schedule_T_383; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_395 = _schedule_T_394 | _schedule_T_384; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_396 = _schedule_T_395 | _schedule_T_385; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_397 = _schedule_T_396 | _schedule_T_386; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_398 = _schedule_T_397 | _schedule_T_387; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_399 = _schedule_T_398 | _schedule_T_388; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_400 = _schedule_T_399 | _schedule_T_389; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_401 = _schedule_T_400 | _schedule_T_390; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_402 = _schedule_T_401 | _schedule_T_391; // @[Mux.scala:30:73]
assign _schedule_WIRE_25 = _schedule_T_402; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_put = _schedule_WIRE_25; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_403 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_404 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_405 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_406 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_407 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_408 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_409 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_410 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_411 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_412 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_413 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_414 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_415 = _schedule_T_403 | _schedule_T_404; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_416 = _schedule_T_415 | _schedule_T_405; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_417 = _schedule_T_416 | _schedule_T_406; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_418 = _schedule_T_417 | _schedule_T_407; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_419 = _schedule_T_418 | _schedule_T_408; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_420 = _schedule_T_419 | _schedule_T_409; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_421 = _schedule_T_420 | _schedule_T_410; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_422 = _schedule_T_421 | _schedule_T_411; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_423 = _schedule_T_422 | _schedule_T_412; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_424 = _schedule_T_423 | _schedule_T_413; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_425 = _schedule_T_424 | _schedule_T_414; // @[Mux.scala:30:73]
assign _schedule_WIRE_26 = _schedule_T_425; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_offset = _schedule_WIRE_26; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_426 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_427 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_428 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_429 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_430 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_431 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_432 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_433 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_434 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_435 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_436 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_437 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_438 = _schedule_T_426 | _schedule_T_427; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_439 = _schedule_T_438 | _schedule_T_428; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_440 = _schedule_T_439 | _schedule_T_429; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_441 = _schedule_T_440 | _schedule_T_430; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_442 = _schedule_T_441 | _schedule_T_431; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_443 = _schedule_T_442 | _schedule_T_432; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_444 = _schedule_T_443 | _schedule_T_433; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_445 = _schedule_T_444 | _schedule_T_434; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_446 = _schedule_T_445 | _schedule_T_435; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_447 = _schedule_T_446 | _schedule_T_436; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_448 = _schedule_T_447 | _schedule_T_437; // @[Mux.scala:30:73]
assign _schedule_WIRE_27 = _schedule_T_448; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_tag = _schedule_WIRE_27; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_449 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_450 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_451 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_452 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_453 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_454 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_455 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_456 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_457 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_458 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_459 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_460 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_461 = _schedule_T_449 | _schedule_T_450; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_462 = _schedule_T_461 | _schedule_T_451; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_463 = _schedule_T_462 | _schedule_T_452; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_464 = _schedule_T_463 | _schedule_T_453; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_465 = _schedule_T_464 | _schedule_T_454; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_466 = _schedule_T_465 | _schedule_T_455; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_467 = _schedule_T_466 | _schedule_T_456; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_468 = _schedule_T_467 | _schedule_T_457; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_469 = _schedule_T_468 | _schedule_T_458; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_470 = _schedule_T_469 | _schedule_T_459; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_471 = _schedule_T_470 | _schedule_T_460; // @[Mux.scala:30:73]
assign _schedule_WIRE_28 = _schedule_T_471; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_source = _schedule_WIRE_28; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_472 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_473 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_474 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_475 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_476 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_477 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_478 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_479 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_480 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_481 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_482 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_483 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_484 = _schedule_T_472 | _schedule_T_473; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_485 = _schedule_T_484 | _schedule_T_474; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_486 = _schedule_T_485 | _schedule_T_475; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_487 = _schedule_T_486 | _schedule_T_476; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_488 = _schedule_T_487 | _schedule_T_477; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_489 = _schedule_T_488 | _schedule_T_478; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_490 = _schedule_T_489 | _schedule_T_479; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_491 = _schedule_T_490 | _schedule_T_480; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_492 = _schedule_T_491 | _schedule_T_481; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_493 = _schedule_T_492 | _schedule_T_482; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_494 = _schedule_T_493 | _schedule_T_483; // @[Mux.scala:30:73]
assign _schedule_WIRE_29 = _schedule_T_494; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_size = _schedule_WIRE_29; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_495 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_496 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_497 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_498 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_499 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_500 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_501 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_502 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_503 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_504 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_505 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_506 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_507 = _schedule_T_495 | _schedule_T_496; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_508 = _schedule_T_507 | _schedule_T_497; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_509 = _schedule_T_508 | _schedule_T_498; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_510 = _schedule_T_509 | _schedule_T_499; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_511 = _schedule_T_510 | _schedule_T_500; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_512 = _schedule_T_511 | _schedule_T_501; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_513 = _schedule_T_512 | _schedule_T_502; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_514 = _schedule_T_513 | _schedule_T_503; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_515 = _schedule_T_514 | _schedule_T_504; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_516 = _schedule_T_515 | _schedule_T_505; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_517 = _schedule_T_516 | _schedule_T_506; // @[Mux.scala:30:73]
assign _schedule_WIRE_30 = _schedule_T_517; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_param = _schedule_WIRE_30; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_518 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_519 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_520 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_521 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_522 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_523 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_524 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_525 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_526 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_527 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_528 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_529 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_530 = _schedule_T_518 | _schedule_T_519; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_531 = _schedule_T_530 | _schedule_T_520; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_532 = _schedule_T_531 | _schedule_T_521; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_533 = _schedule_T_532 | _schedule_T_522; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_534 = _schedule_T_533 | _schedule_T_523; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_535 = _schedule_T_534 | _schedule_T_524; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_536 = _schedule_T_535 | _schedule_T_525; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_537 = _schedule_T_536 | _schedule_T_526; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_538 = _schedule_T_537 | _schedule_T_527; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_539 = _schedule_T_538 | _schedule_T_528; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_540 = _schedule_T_539 | _schedule_T_529; // @[Mux.scala:30:73]
assign _schedule_WIRE_31 = _schedule_T_540; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_opcode = _schedule_WIRE_31; // @[Mux.scala:30:73]
wire _schedule_T_541 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_542 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_543 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_544 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_545 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_546 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_547 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_548 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_549 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_550 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_551 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_552 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_553 = _schedule_T_541 | _schedule_T_542; // @[Mux.scala:30:73]
wire _schedule_T_554 = _schedule_T_553 | _schedule_T_543; // @[Mux.scala:30:73]
wire _schedule_T_555 = _schedule_T_554 | _schedule_T_544; // @[Mux.scala:30:73]
wire _schedule_T_556 = _schedule_T_555 | _schedule_T_545; // @[Mux.scala:30:73]
wire _schedule_T_557 = _schedule_T_556 | _schedule_T_546; // @[Mux.scala:30:73]
wire _schedule_T_558 = _schedule_T_557 | _schedule_T_547; // @[Mux.scala:30:73]
wire _schedule_T_559 = _schedule_T_558 | _schedule_T_548; // @[Mux.scala:30:73]
wire _schedule_T_560 = _schedule_T_559 | _schedule_T_549; // @[Mux.scala:30:73]
wire _schedule_T_561 = _schedule_T_560 | _schedule_T_550; // @[Mux.scala:30:73]
wire _schedule_T_562 = _schedule_T_561 | _schedule_T_551; // @[Mux.scala:30:73]
wire _schedule_T_563 = _schedule_T_562 | _schedule_T_552; // @[Mux.scala:30:73]
assign _schedule_WIRE_32 = _schedule_T_563; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_control = _schedule_WIRE_32; // @[Mux.scala:30:73]
wire _schedule_WIRE_34; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_prio_0 = _schedule_WIRE_33_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_35; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_prio_1 = _schedule_WIRE_33_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_36; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_prio_2 = _schedule_WIRE_33_2; // @[Mux.scala:30:73]
wire _schedule_T_564 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_565 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_566 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_567 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_568 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_569 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_570 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_571 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_572 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_573 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_576 = _schedule_T_564 | _schedule_T_565; // @[Mux.scala:30:73]
wire _schedule_T_577 = _schedule_T_576 | _schedule_T_566; // @[Mux.scala:30:73]
wire _schedule_T_578 = _schedule_T_577 | _schedule_T_567; // @[Mux.scala:30:73]
wire _schedule_T_579 = _schedule_T_578 | _schedule_T_568; // @[Mux.scala:30:73]
wire _schedule_T_580 = _schedule_T_579 | _schedule_T_569; // @[Mux.scala:30:73]
wire _schedule_T_581 = _schedule_T_580 | _schedule_T_570; // @[Mux.scala:30:73]
wire _schedule_T_582 = _schedule_T_581 | _schedule_T_571; // @[Mux.scala:30:73]
wire _schedule_T_583 = _schedule_T_582 | _schedule_T_572; // @[Mux.scala:30:73]
wire _schedule_T_584 = _schedule_T_583 | _schedule_T_573; // @[Mux.scala:30:73]
wire _schedule_T_585 = _schedule_T_584; // @[Mux.scala:30:73]
wire _schedule_T_586 = _schedule_T_585; // @[Mux.scala:30:73]
assign _schedule_WIRE_34 = _schedule_T_586; // @[Mux.scala:30:73]
assign _schedule_WIRE_33_0 = _schedule_WIRE_34; // @[Mux.scala:30:73]
wire _schedule_T_587 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_588 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_589 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_590 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_591 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_592 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_593 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_594 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_595 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_596 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_597 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_599 = _schedule_T_587 | _schedule_T_588; // @[Mux.scala:30:73]
wire _schedule_T_600 = _schedule_T_599 | _schedule_T_589; // @[Mux.scala:30:73]
wire _schedule_T_601 = _schedule_T_600 | _schedule_T_590; // @[Mux.scala:30:73]
wire _schedule_T_602 = _schedule_T_601 | _schedule_T_591; // @[Mux.scala:30:73]
wire _schedule_T_603 = _schedule_T_602 | _schedule_T_592; // @[Mux.scala:30:73]
wire _schedule_T_604 = _schedule_T_603 | _schedule_T_593; // @[Mux.scala:30:73]
wire _schedule_T_605 = _schedule_T_604 | _schedule_T_594; // @[Mux.scala:30:73]
wire _schedule_T_606 = _schedule_T_605 | _schedule_T_595; // @[Mux.scala:30:73]
wire _schedule_T_607 = _schedule_T_606 | _schedule_T_596; // @[Mux.scala:30:73]
wire _schedule_T_608 = _schedule_T_607 | _schedule_T_597; // @[Mux.scala:30:73]
wire _schedule_T_609 = _schedule_T_608; // @[Mux.scala:30:73]
assign _schedule_WIRE_35 = _schedule_T_609; // @[Mux.scala:30:73]
assign _schedule_WIRE_33_1 = _schedule_WIRE_35; // @[Mux.scala:30:73]
wire _schedule_T_610 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_611 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_612 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_613 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_614 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_615 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_616 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_617 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_618 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_619 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_620 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_621 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_622 = _schedule_T_610 | _schedule_T_611; // @[Mux.scala:30:73]
wire _schedule_T_623 = _schedule_T_622 | _schedule_T_612; // @[Mux.scala:30:73]
wire _schedule_T_624 = _schedule_T_623 | _schedule_T_613; // @[Mux.scala:30:73]
wire _schedule_T_625 = _schedule_T_624 | _schedule_T_614; // @[Mux.scala:30:73]
wire _schedule_T_626 = _schedule_T_625 | _schedule_T_615; // @[Mux.scala:30:73]
wire _schedule_T_627 = _schedule_T_626 | _schedule_T_616; // @[Mux.scala:30:73]
wire _schedule_T_628 = _schedule_T_627 | _schedule_T_617; // @[Mux.scala:30:73]
wire _schedule_T_629 = _schedule_T_628 | _schedule_T_618; // @[Mux.scala:30:73]
wire _schedule_T_630 = _schedule_T_629 | _schedule_T_619; // @[Mux.scala:30:73]
wire _schedule_T_631 = _schedule_T_630 | _schedule_T_620; // @[Mux.scala:30:73]
wire _schedule_T_632 = _schedule_T_631 | _schedule_T_621; // @[Mux.scala:30:73]
assign _schedule_WIRE_36 = _schedule_T_632; // @[Mux.scala:30:73]
assign _schedule_WIRE_33_2 = _schedule_WIRE_36; // @[Mux.scala:30:73]
wire _schedule_T_633 = _schedule_T & _mshrs_0_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_634 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_635 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_636 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_637 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_638 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_639 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_640 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_641 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_642 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_643 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_644 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_645 = _schedule_T_633 | _schedule_T_634; // @[Mux.scala:30:73]
wire _schedule_T_646 = _schedule_T_645 | _schedule_T_635; // @[Mux.scala:30:73]
wire _schedule_T_647 = _schedule_T_646 | _schedule_T_636; // @[Mux.scala:30:73]
wire _schedule_T_648 = _schedule_T_647 | _schedule_T_637; // @[Mux.scala:30:73]
wire _schedule_T_649 = _schedule_T_648 | _schedule_T_638; // @[Mux.scala:30:73]
wire _schedule_T_650 = _schedule_T_649 | _schedule_T_639; // @[Mux.scala:30:73]
wire _schedule_T_651 = _schedule_T_650 | _schedule_T_640; // @[Mux.scala:30:73]
wire _schedule_T_652 = _schedule_T_651 | _schedule_T_641; // @[Mux.scala:30:73]
wire _schedule_T_653 = _schedule_T_652 | _schedule_T_642; // @[Mux.scala:30:73]
wire _schedule_T_654 = _schedule_T_653 | _schedule_T_643; // @[Mux.scala:30:73]
wire _schedule_T_655 = _schedule_T_654 | _schedule_T_644; // @[Mux.scala:30:73]
assign _schedule_WIRE_37 = _schedule_T_655; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_valid = _schedule_WIRE_37; // @[Mux.scala:30:73]
wire _schedule_WIRE_47; // @[Mux.scala:30:73]
assign schedule_c_valid = _schedule_WIRE_38_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_39_opcode; // @[Mux.scala:30:73]
assign schedule_c_bits_opcode = _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_39_param; // @[Mux.scala:30:73]
assign schedule_c_bits_param = _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_39_tag; // @[Mux.scala:30:73]
assign schedule_c_bits_tag = _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_39_set; // @[Mux.scala:30:73]
assign schedule_c_bits_set = _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_39_way; // @[Mux.scala:30:73]
assign schedule_c_bits_way = _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_39_dirty; // @[Mux.scala:30:73]
assign schedule_c_bits_dirty = _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_46; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_opcode = _schedule_WIRE_39_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_45; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_param = _schedule_WIRE_39_param; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_43; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_tag = _schedule_WIRE_39_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_42; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_set = _schedule_WIRE_39_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_41; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_way = _schedule_WIRE_39_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_40; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_dirty = _schedule_WIRE_39_dirty; // @[Mux.scala:30:73]
wire _schedule_T_656 = _schedule_T & _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_657 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_658 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_659 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_660 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_661 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_662 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_663 = _schedule_T_7 & _mshrs_7_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_664 = _schedule_T_8 & _mshrs_8_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_665 = _schedule_T_9 & _mshrs_9_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_666 = _schedule_T_10 & _mshrs_10_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_667 = _schedule_T_11 & _mshrs_11_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_668 = _schedule_T_656 | _schedule_T_657; // @[Mux.scala:30:73]
wire _schedule_T_669 = _schedule_T_668 | _schedule_T_658; // @[Mux.scala:30:73]
wire _schedule_T_670 = _schedule_T_669 | _schedule_T_659; // @[Mux.scala:30:73]
wire _schedule_T_671 = _schedule_T_670 | _schedule_T_660; // @[Mux.scala:30:73]
wire _schedule_T_672 = _schedule_T_671 | _schedule_T_661; // @[Mux.scala:30:73]
wire _schedule_T_673 = _schedule_T_672 | _schedule_T_662; // @[Mux.scala:30:73]
wire _schedule_T_674 = _schedule_T_673 | _schedule_T_663; // @[Mux.scala:30:73]
wire _schedule_T_675 = _schedule_T_674 | _schedule_T_664; // @[Mux.scala:30:73]
wire _schedule_T_676 = _schedule_T_675 | _schedule_T_665; // @[Mux.scala:30:73]
wire _schedule_T_677 = _schedule_T_676 | _schedule_T_666; // @[Mux.scala:30:73]
wire _schedule_T_678 = _schedule_T_677 | _schedule_T_667; // @[Mux.scala:30:73]
assign _schedule_WIRE_40 = _schedule_T_678; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_dirty = _schedule_WIRE_40; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_679 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_680 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_681 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_682 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_683 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_684 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_685 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_686 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_687 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_688 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_689 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_690 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_691 = _schedule_T_679 | _schedule_T_680; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_692 = _schedule_T_691 | _schedule_T_681; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_693 = _schedule_T_692 | _schedule_T_682; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_694 = _schedule_T_693 | _schedule_T_683; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_695 = _schedule_T_694 | _schedule_T_684; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_696 = _schedule_T_695 | _schedule_T_685; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_697 = _schedule_T_696 | _schedule_T_686; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_698 = _schedule_T_697 | _schedule_T_687; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_699 = _schedule_T_698 | _schedule_T_688; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_700 = _schedule_T_699 | _schedule_T_689; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_701 = _schedule_T_700 | _schedule_T_690; // @[Mux.scala:30:73]
assign _schedule_WIRE_41 = _schedule_T_701; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_way = _schedule_WIRE_41; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_702 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_703 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_704 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_705 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_706 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_707 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_708 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_709 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_710 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_711 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_712 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_713 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_714 = _schedule_T_702 | _schedule_T_703; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_715 = _schedule_T_714 | _schedule_T_704; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_716 = _schedule_T_715 | _schedule_T_705; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_717 = _schedule_T_716 | _schedule_T_706; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_718 = _schedule_T_717 | _schedule_T_707; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_719 = _schedule_T_718 | _schedule_T_708; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_720 = _schedule_T_719 | _schedule_T_709; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_721 = _schedule_T_720 | _schedule_T_710; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_722 = _schedule_T_721 | _schedule_T_711; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_723 = _schedule_T_722 | _schedule_T_712; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_724 = _schedule_T_723 | _schedule_T_713; // @[Mux.scala:30:73]
assign _schedule_WIRE_42 = _schedule_T_724; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_set = _schedule_WIRE_42; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_725 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_726 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_727 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_728 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_729 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_730 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_731 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_732 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_733 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_734 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_735 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_736 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_737 = _schedule_T_725 | _schedule_T_726; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_738 = _schedule_T_737 | _schedule_T_727; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_739 = _schedule_T_738 | _schedule_T_728; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_740 = _schedule_T_739 | _schedule_T_729; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_741 = _schedule_T_740 | _schedule_T_730; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_742 = _schedule_T_741 | _schedule_T_731; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_743 = _schedule_T_742 | _schedule_T_732; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_744 = _schedule_T_743 | _schedule_T_733; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_745 = _schedule_T_744 | _schedule_T_734; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_746 = _schedule_T_745 | _schedule_T_735; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_747 = _schedule_T_746 | _schedule_T_736; // @[Mux.scala:30:73]
assign _schedule_WIRE_43 = _schedule_T_747; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_tag = _schedule_WIRE_43; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_771 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_772 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_773 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_774 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_775 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_776 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_777 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_778 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_779 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_780 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_781 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_782 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_783 = _schedule_T_771 | _schedule_T_772; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_784 = _schedule_T_783 | _schedule_T_773; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_785 = _schedule_T_784 | _schedule_T_774; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_786 = _schedule_T_785 | _schedule_T_775; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_787 = _schedule_T_786 | _schedule_T_776; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_788 = _schedule_T_787 | _schedule_T_777; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_789 = _schedule_T_788 | _schedule_T_778; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_790 = _schedule_T_789 | _schedule_T_779; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_791 = _schedule_T_790 | _schedule_T_780; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_792 = _schedule_T_791 | _schedule_T_781; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_793 = _schedule_T_792 | _schedule_T_782; // @[Mux.scala:30:73]
assign _schedule_WIRE_45 = _schedule_T_793; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_param = _schedule_WIRE_45; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_794 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_795 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_796 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_797 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_798 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_799 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_800 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_801 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_802 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_803 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_804 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_805 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_806 = _schedule_T_794 | _schedule_T_795; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_807 = _schedule_T_806 | _schedule_T_796; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_808 = _schedule_T_807 | _schedule_T_797; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_809 = _schedule_T_808 | _schedule_T_798; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_810 = _schedule_T_809 | _schedule_T_799; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_811 = _schedule_T_810 | _schedule_T_800; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_812 = _schedule_T_811 | _schedule_T_801; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_813 = _schedule_T_812 | _schedule_T_802; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_814 = _schedule_T_813 | _schedule_T_803; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_815 = _schedule_T_814 | _schedule_T_804; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_816 = _schedule_T_815 | _schedule_T_805; // @[Mux.scala:30:73]
assign _schedule_WIRE_46 = _schedule_T_816; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_opcode = _schedule_WIRE_46; // @[Mux.scala:30:73]
wire _schedule_T_817 = _schedule_T & _mshrs_0_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_818 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_819 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_820 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_821 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_822 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_823 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_824 = _schedule_T_7 & _mshrs_7_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_825 = _schedule_T_8 & _mshrs_8_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_826 = _schedule_T_9 & _mshrs_9_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_827 = _schedule_T_10 & _mshrs_10_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_828 = _schedule_T_11 & _mshrs_11_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_829 = _schedule_T_817 | _schedule_T_818; // @[Mux.scala:30:73]
wire _schedule_T_830 = _schedule_T_829 | _schedule_T_819; // @[Mux.scala:30:73]
wire _schedule_T_831 = _schedule_T_830 | _schedule_T_820; // @[Mux.scala:30:73]
wire _schedule_T_832 = _schedule_T_831 | _schedule_T_821; // @[Mux.scala:30:73]
wire _schedule_T_833 = _schedule_T_832 | _schedule_T_822; // @[Mux.scala:30:73]
wire _schedule_T_834 = _schedule_T_833 | _schedule_T_823; // @[Mux.scala:30:73]
wire _schedule_T_835 = _schedule_T_834 | _schedule_T_824; // @[Mux.scala:30:73]
wire _schedule_T_836 = _schedule_T_835 | _schedule_T_825; // @[Mux.scala:30:73]
wire _schedule_T_837 = _schedule_T_836 | _schedule_T_826; // @[Mux.scala:30:73]
wire _schedule_T_838 = _schedule_T_837 | _schedule_T_827; // @[Mux.scala:30:73]
wire _schedule_T_839 = _schedule_T_838 | _schedule_T_828; // @[Mux.scala:30:73]
assign _schedule_WIRE_47 = _schedule_T_839; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_valid = _schedule_WIRE_47; // @[Mux.scala:30:73]
wire _schedule_WIRE_54; // @[Mux.scala:30:73]
assign schedule_b_valid = _schedule_WIRE_48_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_49_param; // @[Mux.scala:30:73]
assign schedule_b_bits_param = _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_49_tag; // @[Mux.scala:30:73]
assign schedule_b_bits_tag = _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_49_set; // @[Mux.scala:30:73]
assign schedule_b_bits_set = _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73]
wire _schedule_WIRE_49_clients; // @[Mux.scala:30:73]
assign schedule_b_bits_clients = _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_53; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_param = _schedule_WIRE_49_param; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_52; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_tag = _schedule_WIRE_49_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_51; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_set = _schedule_WIRE_49_set; // @[Mux.scala:30:73]
wire _schedule_WIRE_50; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_clients = _schedule_WIRE_49_clients; // @[Mux.scala:30:73]
wire _schedule_T_840 = _schedule_T & _mshrs_0_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_841 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_842 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_843 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_844 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_845 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_846 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_847 = _schedule_T_7 & _mshrs_7_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_848 = _schedule_T_8 & _mshrs_8_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_849 = _schedule_T_9 & _mshrs_9_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_850 = _schedule_T_10 & _mshrs_10_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_851 = _schedule_T_11 & _mshrs_11_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_852 = _schedule_T_840 | _schedule_T_841; // @[Mux.scala:30:73]
wire _schedule_T_853 = _schedule_T_852 | _schedule_T_842; // @[Mux.scala:30:73]
wire _schedule_T_854 = _schedule_T_853 | _schedule_T_843; // @[Mux.scala:30:73]
wire _schedule_T_855 = _schedule_T_854 | _schedule_T_844; // @[Mux.scala:30:73]
wire _schedule_T_856 = _schedule_T_855 | _schedule_T_845; // @[Mux.scala:30:73]
wire _schedule_T_857 = _schedule_T_856 | _schedule_T_846; // @[Mux.scala:30:73]
wire _schedule_T_858 = _schedule_T_857 | _schedule_T_847; // @[Mux.scala:30:73]
wire _schedule_T_859 = _schedule_T_858 | _schedule_T_848; // @[Mux.scala:30:73]
wire _schedule_T_860 = _schedule_T_859 | _schedule_T_849; // @[Mux.scala:30:73]
wire _schedule_T_861 = _schedule_T_860 | _schedule_T_850; // @[Mux.scala:30:73]
wire _schedule_T_862 = _schedule_T_861 | _schedule_T_851; // @[Mux.scala:30:73]
assign _schedule_WIRE_50 = _schedule_T_862; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_clients = _schedule_WIRE_50; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_863 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_864 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_865 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_866 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_867 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_868 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_869 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_870 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_871 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_872 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_873 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_874 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_875 = _schedule_T_863 | _schedule_T_864; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_876 = _schedule_T_875 | _schedule_T_865; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_877 = _schedule_T_876 | _schedule_T_866; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_878 = _schedule_T_877 | _schedule_T_867; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_879 = _schedule_T_878 | _schedule_T_868; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_880 = _schedule_T_879 | _schedule_T_869; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_881 = _schedule_T_880 | _schedule_T_870; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_882 = _schedule_T_881 | _schedule_T_871; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_883 = _schedule_T_882 | _schedule_T_872; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_884 = _schedule_T_883 | _schedule_T_873; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_885 = _schedule_T_884 | _schedule_T_874; // @[Mux.scala:30:73]
assign _schedule_WIRE_51 = _schedule_T_885; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_set = _schedule_WIRE_51; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_886 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_887 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_888 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_889 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_890 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_891 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_892 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_893 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_894 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_895 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_896 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_897 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_898 = _schedule_T_886 | _schedule_T_887; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_899 = _schedule_T_898 | _schedule_T_888; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_900 = _schedule_T_899 | _schedule_T_889; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_901 = _schedule_T_900 | _schedule_T_890; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_902 = _schedule_T_901 | _schedule_T_891; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_903 = _schedule_T_902 | _schedule_T_892; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_904 = _schedule_T_903 | _schedule_T_893; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_905 = _schedule_T_904 | _schedule_T_894; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_906 = _schedule_T_905 | _schedule_T_895; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_907 = _schedule_T_906 | _schedule_T_896; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_908 = _schedule_T_907 | _schedule_T_897; // @[Mux.scala:30:73]
assign _schedule_WIRE_52 = _schedule_T_908; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_tag = _schedule_WIRE_52; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_909 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_910 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_911 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_912 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_913 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_914 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_915 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_916 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_917 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_918 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_919 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_920 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_921 = _schedule_T_909 | _schedule_T_910; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_922 = _schedule_T_921 | _schedule_T_911; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_923 = _schedule_T_922 | _schedule_T_912; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_924 = _schedule_T_923 | _schedule_T_913; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_925 = _schedule_T_924 | _schedule_T_914; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_926 = _schedule_T_925 | _schedule_T_915; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_927 = _schedule_T_926 | _schedule_T_916; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_928 = _schedule_T_927 | _schedule_T_917; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_929 = _schedule_T_928 | _schedule_T_918; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_930 = _schedule_T_929 | _schedule_T_919; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_931 = _schedule_T_930 | _schedule_T_920; // @[Mux.scala:30:73]
assign _schedule_WIRE_53 = _schedule_T_931; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_param = _schedule_WIRE_53; // @[Mux.scala:30:73]
wire _schedule_T_932 = _schedule_T & _mshrs_0_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_933 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_934 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_935 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_936 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_937 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_938 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_939 = _schedule_T_7 & _mshrs_7_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_940 = _schedule_T_8 & _mshrs_8_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_941 = _schedule_T_9 & _mshrs_9_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_942 = _schedule_T_10 & _mshrs_10_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_943 = _schedule_T_11 & _mshrs_11_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_944 = _schedule_T_932 | _schedule_T_933; // @[Mux.scala:30:73]
wire _schedule_T_945 = _schedule_T_944 | _schedule_T_934; // @[Mux.scala:30:73]
wire _schedule_T_946 = _schedule_T_945 | _schedule_T_935; // @[Mux.scala:30:73]
wire _schedule_T_947 = _schedule_T_946 | _schedule_T_936; // @[Mux.scala:30:73]
wire _schedule_T_948 = _schedule_T_947 | _schedule_T_937; // @[Mux.scala:30:73]
wire _schedule_T_949 = _schedule_T_948 | _schedule_T_938; // @[Mux.scala:30:73]
wire _schedule_T_950 = _schedule_T_949 | _schedule_T_939; // @[Mux.scala:30:73]
wire _schedule_T_951 = _schedule_T_950 | _schedule_T_940; // @[Mux.scala:30:73]
wire _schedule_T_952 = _schedule_T_951 | _schedule_T_941; // @[Mux.scala:30:73]
wire _schedule_T_953 = _schedule_T_952 | _schedule_T_942; // @[Mux.scala:30:73]
wire _schedule_T_954 = _schedule_T_953 | _schedule_T_943; // @[Mux.scala:30:73]
assign _schedule_WIRE_54 = _schedule_T_954; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_valid = _schedule_WIRE_54; // @[Mux.scala:30:73]
wire _schedule_WIRE_62; // @[Mux.scala:30:73]
assign schedule_a_valid = _schedule_WIRE_55_valid; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_56_tag; // @[Mux.scala:30:73]
assign schedule_a_bits_tag = _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_56_set; // @[Mux.scala:30:73]
assign schedule_a_bits_set = _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_56_param; // @[Mux.scala:30:73]
assign schedule_a_bits_param = _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73]
wire _schedule_WIRE_56_block; // @[Mux.scala:30:73]
assign schedule_a_bits_block = _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_61; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_tag = _schedule_WIRE_56_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_60; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_set = _schedule_WIRE_56_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_59; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_param = _schedule_WIRE_56_param; // @[Mux.scala:30:73]
wire _schedule_WIRE_57; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_block = _schedule_WIRE_56_block; // @[Mux.scala:30:73]
wire _schedule_T_955 = _schedule_T & _mshrs_0_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_956 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_957 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_958 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_959 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_960 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_961 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_962 = _schedule_T_7 & _mshrs_7_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_963 = _schedule_T_8 & _mshrs_8_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_964 = _schedule_T_9 & _mshrs_9_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_965 = _schedule_T_10 & _mshrs_10_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_966 = _schedule_T_11 & _mshrs_11_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_967 = _schedule_T_955 | _schedule_T_956; // @[Mux.scala:30:73]
wire _schedule_T_968 = _schedule_T_967 | _schedule_T_957; // @[Mux.scala:30:73]
wire _schedule_T_969 = _schedule_T_968 | _schedule_T_958; // @[Mux.scala:30:73]
wire _schedule_T_970 = _schedule_T_969 | _schedule_T_959; // @[Mux.scala:30:73]
wire _schedule_T_971 = _schedule_T_970 | _schedule_T_960; // @[Mux.scala:30:73]
wire _schedule_T_972 = _schedule_T_971 | _schedule_T_961; // @[Mux.scala:30:73]
wire _schedule_T_973 = _schedule_T_972 | _schedule_T_962; // @[Mux.scala:30:73]
wire _schedule_T_974 = _schedule_T_973 | _schedule_T_963; // @[Mux.scala:30:73]
wire _schedule_T_975 = _schedule_T_974 | _schedule_T_964; // @[Mux.scala:30:73]
wire _schedule_T_976 = _schedule_T_975 | _schedule_T_965; // @[Mux.scala:30:73]
wire _schedule_T_977 = _schedule_T_976 | _schedule_T_966; // @[Mux.scala:30:73]
assign _schedule_WIRE_57 = _schedule_T_977; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_block = _schedule_WIRE_57; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1001 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1002 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1003 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1004 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1005 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1006 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1007 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1008 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1009 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1010 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1011 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1012 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1013 = _schedule_T_1001 | _schedule_T_1002; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1014 = _schedule_T_1013 | _schedule_T_1003; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1015 = _schedule_T_1014 | _schedule_T_1004; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1016 = _schedule_T_1015 | _schedule_T_1005; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1017 = _schedule_T_1016 | _schedule_T_1006; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1018 = _schedule_T_1017 | _schedule_T_1007; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1019 = _schedule_T_1018 | _schedule_T_1008; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1020 = _schedule_T_1019 | _schedule_T_1009; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1021 = _schedule_T_1020 | _schedule_T_1010; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1022 = _schedule_T_1021 | _schedule_T_1011; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1023 = _schedule_T_1022 | _schedule_T_1012; // @[Mux.scala:30:73]
assign _schedule_WIRE_59 = _schedule_T_1023; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_param = _schedule_WIRE_59; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1024 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1025 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1026 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1027 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1028 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1029 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1030 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1031 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1032 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1033 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1034 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1035 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1036 = _schedule_T_1024 | _schedule_T_1025; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1037 = _schedule_T_1036 | _schedule_T_1026; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1038 = _schedule_T_1037 | _schedule_T_1027; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1039 = _schedule_T_1038 | _schedule_T_1028; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1040 = _schedule_T_1039 | _schedule_T_1029; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1041 = _schedule_T_1040 | _schedule_T_1030; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1042 = _schedule_T_1041 | _schedule_T_1031; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1043 = _schedule_T_1042 | _schedule_T_1032; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1044 = _schedule_T_1043 | _schedule_T_1033; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1045 = _schedule_T_1044 | _schedule_T_1034; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1046 = _schedule_T_1045 | _schedule_T_1035; // @[Mux.scala:30:73]
assign _schedule_WIRE_60 = _schedule_T_1046; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_set = _schedule_WIRE_60; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1047 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1048 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1049 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1050 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1051 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1052 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1053 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1054 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1055 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1056 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1057 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1058 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1059 = _schedule_T_1047 | _schedule_T_1048; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1060 = _schedule_T_1059 | _schedule_T_1049; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1061 = _schedule_T_1060 | _schedule_T_1050; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1062 = _schedule_T_1061 | _schedule_T_1051; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1063 = _schedule_T_1062 | _schedule_T_1052; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1064 = _schedule_T_1063 | _schedule_T_1053; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1065 = _schedule_T_1064 | _schedule_T_1054; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1066 = _schedule_T_1065 | _schedule_T_1055; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1067 = _schedule_T_1066 | _schedule_T_1056; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1068 = _schedule_T_1067 | _schedule_T_1057; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1069 = _schedule_T_1068 | _schedule_T_1058; // @[Mux.scala:30:73]
assign _schedule_WIRE_61 = _schedule_T_1069; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_tag = _schedule_WIRE_61; // @[Mux.scala:30:73]
wire _schedule_T_1070 = _schedule_T & _mshrs_0_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1071 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1072 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1073 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1074 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1075 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1076 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1077 = _schedule_T_7 & _mshrs_7_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1078 = _schedule_T_8 & _mshrs_8_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1079 = _schedule_T_9 & _mshrs_9_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1080 = _schedule_T_10 & _mshrs_10_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1081 = _schedule_T_11 & _mshrs_11_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1082 = _schedule_T_1070 | _schedule_T_1071; // @[Mux.scala:30:73]
wire _schedule_T_1083 = _schedule_T_1082 | _schedule_T_1072; // @[Mux.scala:30:73]
wire _schedule_T_1084 = _schedule_T_1083 | _schedule_T_1073; // @[Mux.scala:30:73]
wire _schedule_T_1085 = _schedule_T_1084 | _schedule_T_1074; // @[Mux.scala:30:73]
wire _schedule_T_1086 = _schedule_T_1085 | _schedule_T_1075; // @[Mux.scala:30:73]
wire _schedule_T_1087 = _schedule_T_1086 | _schedule_T_1076; // @[Mux.scala:30:73]
wire _schedule_T_1088 = _schedule_T_1087 | _schedule_T_1077; // @[Mux.scala:30:73]
wire _schedule_T_1089 = _schedule_T_1088 | _schedule_T_1078; // @[Mux.scala:30:73]
wire _schedule_T_1090 = _schedule_T_1089 | _schedule_T_1079; // @[Mux.scala:30:73]
wire _schedule_T_1091 = _schedule_T_1090 | _schedule_T_1080; // @[Mux.scala:30:73]
wire _schedule_T_1092 = _schedule_T_1091 | _schedule_T_1081; // @[Mux.scala:30:73]
assign _schedule_WIRE_62 = _schedule_T_1092; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_valid = _schedule_WIRE_62; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_12 = _scheduleTag_T ? _mshrs_0_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_13 = _scheduleTag_T_1 ? _mshrs_1_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_14 = _scheduleTag_T_2 ? _mshrs_2_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_15 = _scheduleTag_T_3 ? _mshrs_3_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_16 = _scheduleTag_T_4 ? _mshrs_4_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_17 = _scheduleTag_T_5 ? _mshrs_5_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_18 = _scheduleTag_T_6 ? _mshrs_6_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_19 = _scheduleTag_T_7 ? _mshrs_7_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_20 = _scheduleTag_T_8 ? _mshrs_8_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_21 = _scheduleTag_T_9 ? _mshrs_9_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_22 = _scheduleTag_T_10 ? _mshrs_10_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_23 = _scheduleTag_T_11 ? _mshrs_11_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_24 = _scheduleTag_T_12 | _scheduleTag_T_13; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_25 = _scheduleTag_T_24 | _scheduleTag_T_14; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_26 = _scheduleTag_T_25 | _scheduleTag_T_15; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_27 = _scheduleTag_T_26 | _scheduleTag_T_16; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_28 = _scheduleTag_T_27 | _scheduleTag_T_17; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_29 = _scheduleTag_T_28 | _scheduleTag_T_18; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_30 = _scheduleTag_T_29 | _scheduleTag_T_19; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_31 = _scheduleTag_T_30 | _scheduleTag_T_20; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_32 = _scheduleTag_T_31 | _scheduleTag_T_21; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_33 = _scheduleTag_T_32 | _scheduleTag_T_22; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_34 = _scheduleTag_T_33 | _scheduleTag_T_23; // @[Mux.scala:30:73]
wire [8:0] scheduleTag = _scheduleTag_T_34; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_12 = _scheduleSet_T ? _mshrs_0_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_13 = _scheduleSet_T_1 ? _mshrs_1_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_14 = _scheduleSet_T_2 ? _mshrs_2_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_15 = _scheduleSet_T_3 ? _mshrs_3_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_16 = _scheduleSet_T_4 ? _mshrs_4_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_17 = _scheduleSet_T_5 ? _mshrs_5_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_18 = _scheduleSet_T_6 ? _mshrs_6_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_19 = _scheduleSet_T_7 ? _mshrs_7_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_20 = _scheduleSet_T_8 ? _mshrs_8_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_21 = _scheduleSet_T_9 ? _mshrs_9_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_22 = _scheduleSet_T_10 ? _mshrs_10_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_23 = _scheduleSet_T_11 ? _mshrs_11_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_24 = _scheduleSet_T_12 | _scheduleSet_T_13; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_25 = _scheduleSet_T_24 | _scheduleSet_T_14; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_26 = _scheduleSet_T_25 | _scheduleSet_T_15; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_27 = _scheduleSet_T_26 | _scheduleSet_T_16; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_28 = _scheduleSet_T_27 | _scheduleSet_T_17; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_29 = _scheduleSet_T_28 | _scheduleSet_T_18; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_30 = _scheduleSet_T_29 | _scheduleSet_T_19; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_31 = _scheduleSet_T_30 | _scheduleSet_T_20; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_32 = _scheduleSet_T_31 | _scheduleSet_T_21; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_33 = _scheduleSet_T_32 | _scheduleSet_T_22; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_34 = _scheduleSet_T_33 | _scheduleSet_T_23; // @[Mux.scala:30:73]
wire [10:0] scheduleSet = _scheduleSet_T_34; // @[Mux.scala:30:73]
wire [10:0] _robin_filter_T = mshr_selectOH[11:1]; // @[package.scala:262:48]
wire [11:0] _robin_filter_T_1 = {mshr_selectOH[11], mshr_selectOH[10:0] | _robin_filter_T}; // @[Mux.scala:32:36]
wire [9:0] _robin_filter_T_2 = _robin_filter_T_1[11:2]; // @[package.scala:262:{43,48}]
wire [11:0] _robin_filter_T_3 = {_robin_filter_T_1[11:10], _robin_filter_T_1[9:0] | _robin_filter_T_2}; // @[package.scala:262:{43,48}]
wire [7:0] _robin_filter_T_4 = _robin_filter_T_3[11:4]; // @[package.scala:262:{43,48}]
wire [11:0] _robin_filter_T_5 = {_robin_filter_T_3[11:8], _robin_filter_T_3[7:0] | _robin_filter_T_4}; // @[package.scala:262:{43,48}]
wire [3:0] _robin_filter_T_6 = _robin_filter_T_5[11:8]; // @[package.scala:262:{43,48}]
wire [11:0] _robin_filter_T_7 = {_robin_filter_T_5[11:4], _robin_filter_T_5[3:0] | _robin_filter_T_6}; // @[package.scala:262:{43,48}]
wire [11:0] _robin_filter_T_8 = _robin_filter_T_7; // @[package.scala:262:43, :263:17]
wire [11:0] _robin_filter_T_9 = ~_robin_filter_T_8; // @[package.scala:263:17]
wire _schedule_c_bits_source_T = schedule_c_bits_opcode[1]; // @[Mux.scala:30:73]
assign _schedule_c_bits_source_T_1 = _schedule_c_bits_source_T ? mshr_select : 4'h0; // @[OneHot.scala:32:10]
assign schedule_c_bits_source = _schedule_c_bits_source_T_1; // @[Mux.scala:30:73]
assign _nestedwb_set_T = select_c ? _mshrs_11_io_status_bits_set : _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :153:32, :155:24]
assign nestedwb_set = _nestedwb_set_T; // @[Scheduler.scala:75:22, :155:24]
assign _nestedwb_tag_T = select_c ? _mshrs_11_io_status_bits_tag : _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46, :153:32, :156:24]
assign nestedwb_tag = _nestedwb_tag_T; // @[Scheduler.scala:75:22, :156:24]
wire _GEN = select_bc & _mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :154:32, :157:37]
wire _nestedwb_b_toN_T; // @[Scheduler.scala:157:37]
assign _nestedwb_b_toN_T = _GEN; // @[Scheduler.scala:157:37]
wire _nestedwb_b_toB_T; // @[Scheduler.scala:158:37]
assign _nestedwb_b_toB_T = _GEN; // @[Scheduler.scala:157:37, :158:37]
assign _nestedwb_b_clr_dirty_T = _GEN; // @[Scheduler.scala:157:37, :159:37]
wire _nestedwb_b_toN_T_1 = _mshrs_10_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala:71:46, :157:123]
assign _nestedwb_b_toN_T_2 = _nestedwb_b_toN_T & _nestedwb_b_toN_T_1; // @[Scheduler.scala:157:{37,75,123}]
assign nestedwb_b_toN = _nestedwb_b_toN_T_2; // @[Scheduler.scala:75:22, :157:75]
wire _nestedwb_b_toB_T_1 = _mshrs_10_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala:71:46, :158:123]
assign _nestedwb_b_toB_T_2 = _nestedwb_b_toB_T & _nestedwb_b_toB_T_1; // @[Scheduler.scala:158:{37,75,123}]
assign nestedwb_b_toB = _nestedwb_b_toB_T_2; // @[Scheduler.scala:75:22, :158:75]
assign nestedwb_b_clr_dirty = _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:75:22, :159:37]
wire _nestedwb_c_set_dirty_T = select_c & _mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :153:32, :160:37]
assign _nestedwb_c_set_dirty_T_1 = _nestedwb_c_set_dirty_T & _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46, :160:{37,75}]
assign nestedwb_c_set_dirty = _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:75:22, :160:75]
wire _request_ready_T_2; // @[Scheduler.scala:261:40]
wire _request_valid_T_2; // @[Scheduler.scala:164:39]
wire _request_bits_T_1_prio_0; // @[Scheduler.scala:165:22]
wire _view__WIRE_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_1_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_2_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_3_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_4_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_5_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_6_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_7_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_8_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_9_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_10_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_11_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _request_bits_T_1_prio_2; // @[Scheduler.scala:165:22]
wire _request_bits_T_1_control; // @[Scheduler.scala:165:22]
wire _view__WIRE_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_1_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_2_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_3_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_4_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_5_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_6_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_7_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_8_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_9_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_10_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_11_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _request_bits_T_1_opcode; // @[Scheduler.scala:165:22]
wire _view__WIRE_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_1_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_2_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_3_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_4_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_5_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_6_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_7_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_8_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_9_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_10_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_11_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _request_bits_T_1_param; // @[Scheduler.scala:165:22]
wire [2:0] _view__WIRE_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_1_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_2_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_3_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_4_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_5_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_6_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_7_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_8_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_9_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_10_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_11_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _request_bits_T_1_size; // @[Scheduler.scala:165:22]
wire [2:0] _view__WIRE_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_1_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_2_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_3_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_4_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_5_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_6_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_7_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_8_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_9_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_10_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_11_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _request_bits_T_1_source; // @[Scheduler.scala:165:22]
wire [2:0] _view__WIRE_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_1_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_2_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_3_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_4_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_5_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_6_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_7_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_8_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_9_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_10_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_11_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _request_bits_T_1_tag; // @[Scheduler.scala:165:22]
wire [5:0] _view__WIRE_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_1_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_2_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_3_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_4_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_5_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_6_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_7_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_8_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_9_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_10_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_11_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _request_bits_T_1_offset; // @[Scheduler.scala:165:22]
wire [8:0] _view__WIRE_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_1_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_2_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_3_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_4_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_5_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_6_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_7_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_8_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_9_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_10_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_11_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _request_bits_T_1_put; // @[Scheduler.scala:165:22]
wire [5:0] _view__WIRE_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_1_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_2_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_3_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_4_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_5_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_6_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_7_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_8_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_9_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_10_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_11_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [10:0] _request_bits_T_1_set; // @[Scheduler.scala:165:22]
wire [5:0] _view__WIRE_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_1_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_2_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_3_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_4_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_5_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_6_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_7_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_8_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_9_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_10_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_11_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [10:0] request_bits_set; // @[Scheduler.scala:163:21]
wire request_ready; // @[Scheduler.scala:163:21]
wire request_valid; // @[Scheduler.scala:163:21]
wire _request_valid_T = _sinkA_io_req_valid | _sinkX_io_req_valid; // @[Scheduler.scala:54:21, :58:21, :164:62]
wire _request_valid_T_1 = _request_valid_T | _sinkC_io_req_valid; // @[Scheduler.scala:55:21, :164:{62,84}]
assign _request_valid_T_2 = _directory_io_ready & _request_valid_T_1; // @[Scheduler.scala:68:25, :164:{39,84}]
assign request_valid = _request_valid_T_2; // @[Scheduler.scala:163:21, :164:39]
wire [2:0] _request_bits_T_opcode = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [2:0] _request_bits_T_param = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [2:0] _request_bits_T_size = _sinkX_io_req_valid ? 3'h6 : _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [5:0] _request_bits_T_source = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [8:0] _request_bits_T_tag = _sinkX_io_req_valid ? _sinkX_io_req_bits_tag : _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [5:0] _request_bits_T_offset = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [5:0] _request_bits_T_put = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [10:0] _request_bits_T_set = _sinkX_io_req_valid ? _sinkX_io_req_bits_set : _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire _request_bits_T_control; // @[Scheduler.scala:166:22]
assign _request_bits_T_1_control = ~_sinkC_io_req_valid & _request_bits_T_control; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_opcode = _sinkC_io_req_valid ? _sinkC_io_req_bits_opcode : _request_bits_T_opcode; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_param = _sinkC_io_req_valid ? _sinkC_io_req_bits_param : _request_bits_T_param; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_size = _sinkC_io_req_valid ? _sinkC_io_req_bits_size : _request_bits_T_size; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_source = _sinkC_io_req_valid ? _sinkC_io_req_bits_source : _request_bits_T_source; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_tag = _sinkC_io_req_valid ? _sinkC_io_req_bits_tag : _request_bits_T_tag; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_offset = _sinkC_io_req_valid ? _sinkC_io_req_bits_offset : _request_bits_T_offset; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_put = _sinkC_io_req_valid ? _sinkC_io_req_bits_put : _request_bits_T_put; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_set = _sinkC_io_req_valid ? _sinkC_io_req_bits_set : _request_bits_T_set; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_prio_0 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22]
assign request_bits_prio_0 = _request_bits_T_1_prio_0; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_prio_2 = _request_bits_T_1_prio_2; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_control = _request_bits_T_1_control; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_opcode = _request_bits_T_1_opcode; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_param = _request_bits_T_1_param; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_size = _request_bits_T_1_size; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_source = _request_bits_T_1_source; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_tag = _request_bits_T_1_tag; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_offset = _request_bits_T_1_offset; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_put = _request_bits_T_1_put; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_set = _request_bits_T_1_set; // @[Scheduler.scala:163:21, :165:22]
wire _GEN_0 = _directory_io_ready & request_ready; // @[Scheduler.scala:68:25, :163:21, :167:44]
wire _sinkC_io_req_ready_T; // @[Scheduler.scala:167:44]
assign _sinkC_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44]
wire _sinkX_io_req_ready_T; // @[Scheduler.scala:168:44]
assign _sinkX_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :168:44]
wire _sinkA_io_req_ready_T; // @[Scheduler.scala:169:44]
assign _sinkA_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :169:44]
wire _sinkX_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :168:64]
wire _sinkX_io_req_ready_T_2 = _sinkX_io_req_ready_T & _sinkX_io_req_ready_T_1; // @[Scheduler.scala:168:{44,61,64}]
wire _sinkA_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :169:64]
wire _sinkA_io_req_ready_T_2 = _sinkA_io_req_ready_T & _sinkA_io_req_ready_T_1; // @[Scheduler.scala:169:{44,61,64}]
wire _sinkA_io_req_ready_T_3 = ~_sinkX_io_req_valid; // @[Scheduler.scala:58:21, :169:87]
wire _sinkA_io_req_ready_T_4 = _sinkA_io_req_ready_T_2 & _sinkA_io_req_ready_T_3; // @[Scheduler.scala:169:{61,84,87}]
wire _setMatches_T = _mshrs_0_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_1 = _mshrs_0_io_status_valid & _setMatches_T; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_2 = _mshrs_1_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_3 = _mshrs_1_io_status_valid & _setMatches_T_2; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_4 = _mshrs_2_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_5 = _mshrs_2_io_status_valid & _setMatches_T_4; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_6 = _mshrs_3_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_7 = _mshrs_3_io_status_valid & _setMatches_T_6; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_8 = _mshrs_4_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_9 = _mshrs_4_io_status_valid & _setMatches_T_8; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_10 = _mshrs_5_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_11 = _mshrs_5_io_status_valid & _setMatches_T_10; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_12 = _mshrs_6_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_13 = _mshrs_6_io_status_valid & _setMatches_T_12; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_14 = _mshrs_7_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_15 = _mshrs_7_io_status_valid & _setMatches_T_14; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_16 = _mshrs_8_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_17 = _mshrs_8_io_status_valid & _setMatches_T_16; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_18 = _mshrs_9_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_19 = _mshrs_9_io_status_valid & _setMatches_T_18; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_20 = _mshrs_10_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_21 = _mshrs_10_io_status_valid & _setMatches_T_20; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_22 = _mshrs_11_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_23 = _mshrs_11_io_status_valid & _setMatches_T_22; // @[Scheduler.scala:71:46, :172:{59,83}]
wire [1:0] setMatches_lo_lo_hi = {_setMatches_T_5, _setMatches_T_3}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_lo_lo = {setMatches_lo_lo_hi, _setMatches_T_1}; // @[Scheduler.scala:172:{23,59}]
wire [1:0] setMatches_lo_hi_hi = {_setMatches_T_11, _setMatches_T_9}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_lo_hi = {setMatches_lo_hi_hi, _setMatches_T_7}; // @[Scheduler.scala:172:{23,59}]
wire [5:0] setMatches_lo = {setMatches_lo_hi, setMatches_lo_lo}; // @[Scheduler.scala:172:23]
wire [1:0] setMatches_hi_lo_hi = {_setMatches_T_17, _setMatches_T_15}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_hi_lo = {setMatches_hi_lo_hi, _setMatches_T_13}; // @[Scheduler.scala:172:{23,59}]
wire [1:0] setMatches_hi_hi_hi = {_setMatches_T_23, _setMatches_T_21}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_hi_hi = {setMatches_hi_hi_hi, _setMatches_T_19}; // @[Scheduler.scala:172:{23,59}]
wire [5:0] setMatches_hi = {setMatches_hi_hi, setMatches_hi_lo}; // @[Scheduler.scala:172:23]
wire [11:0] setMatches = {setMatches_hi, setMatches_lo}; // @[Scheduler.scala:172:23]
wire _alloc_T = |setMatches; // @[Scheduler.scala:172:23, :173:27]
wire alloc = ~_alloc_T; // @[Scheduler.scala:173:{15,27}]
wire _blockB_T = setMatches[0]; // @[Mux.scala:32:36]
wire _blockC_T = setMatches[0]; // @[Mux.scala:32:36]
wire _nestB_T = setMatches[0]; // @[Mux.scala:32:36]
wire _nestC_T = setMatches[0]; // @[Mux.scala:32:36]
wire _blockB_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _blockC_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _nestB_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _nestC_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _blockB_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _blockC_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _nestB_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _nestC_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _blockB_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _blockC_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _nestB_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _nestC_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _blockB_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _blockC_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _nestB_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _nestC_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _blockB_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _blockC_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _nestB_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _nestC_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _blockB_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _blockC_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _nestB_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _nestC_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _blockB_T_7 = setMatches[7]; // @[Mux.scala:32:36]
wire _blockC_T_7 = setMatches[7]; // @[Mux.scala:32:36]
wire _nestB_T_7 = setMatches[7]; // @[Mux.scala:32:36]
wire _nestC_T_7 = setMatches[7]; // @[Mux.scala:32:36]
wire _blockB_T_8 = setMatches[8]; // @[Mux.scala:32:36]
wire _blockC_T_8 = setMatches[8]; // @[Mux.scala:32:36]
wire _nestB_T_8 = setMatches[8]; // @[Mux.scala:32:36]
wire _nestC_T_8 = setMatches[8]; // @[Mux.scala:32:36]
wire _blockB_T_9 = setMatches[9]; // @[Mux.scala:32:36]
wire _blockC_T_9 = setMatches[9]; // @[Mux.scala:32:36]
wire _nestB_T_9 = setMatches[9]; // @[Mux.scala:32:36]
wire _nestC_T_9 = setMatches[9]; // @[Mux.scala:32:36]
wire _blockB_T_10 = setMatches[10]; // @[Mux.scala:32:36]
wire _blockC_T_10 = setMatches[10]; // @[Mux.scala:32:36]
wire _nestB_T_10 = setMatches[10]; // @[Mux.scala:32:36]
wire _nestC_T_10 = setMatches[10]; // @[Mux.scala:32:36]
wire _blockB_T_11 = setMatches[11]; // @[Mux.scala:32:36]
wire _blockC_T_11 = setMatches[11]; // @[Mux.scala:32:36]
wire _nestB_T_11 = setMatches[11]; // @[Mux.scala:32:36]
wire _nestC_T_11 = setMatches[11]; // @[Mux.scala:32:36]
wire _blockB_T_12 = _blockB_T & _mshrs_0_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_13 = _blockB_T_1 & _mshrs_1_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_14 = _blockB_T_2 & _mshrs_2_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_15 = _blockB_T_3 & _mshrs_3_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_16 = _blockB_T_4 & _mshrs_4_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_17 = _blockB_T_5 & _mshrs_5_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_18 = _blockB_T_6 & _mshrs_6_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_19 = _blockB_T_7 & _mshrs_7_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_20 = _blockB_T_8 & _mshrs_8_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_21 = _blockB_T_9 & _mshrs_9_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_22 = _blockB_T_10 & _mshrs_10_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_23 = _blockB_T_11 & _mshrs_11_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_24 = _blockB_T_12 | _blockB_T_13; // @[Mux.scala:30:73]
wire _blockB_T_25 = _blockB_T_24 | _blockB_T_14; // @[Mux.scala:30:73]
wire _blockB_T_26 = _blockB_T_25 | _blockB_T_15; // @[Mux.scala:30:73]
wire _blockB_T_27 = _blockB_T_26 | _blockB_T_16; // @[Mux.scala:30:73]
wire _blockB_T_28 = _blockB_T_27 | _blockB_T_17; // @[Mux.scala:30:73]
wire _blockB_T_29 = _blockB_T_28 | _blockB_T_18; // @[Mux.scala:30:73]
wire _blockB_T_30 = _blockB_T_29 | _blockB_T_19; // @[Mux.scala:30:73]
wire _blockB_T_31 = _blockB_T_30 | _blockB_T_20; // @[Mux.scala:30:73]
wire _blockB_T_32 = _blockB_T_31 | _blockB_T_21; // @[Mux.scala:30:73]
wire _blockB_T_33 = _blockB_T_32 | _blockB_T_22; // @[Mux.scala:30:73]
wire _blockB_T_34 = _blockB_T_33 | _blockB_T_23; // @[Mux.scala:30:73]
wire _blockB_WIRE = _blockB_T_34; // @[Mux.scala:30:73]
wire _blockC_T_12 = _blockC_T & _mshrs_0_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_13 = _blockC_T_1 & _mshrs_1_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_14 = _blockC_T_2 & _mshrs_2_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_15 = _blockC_T_3 & _mshrs_3_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_16 = _blockC_T_4 & _mshrs_4_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_17 = _blockC_T_5 & _mshrs_5_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_18 = _blockC_T_6 & _mshrs_6_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_19 = _blockC_T_7 & _mshrs_7_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_20 = _blockC_T_8 & _mshrs_8_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_21 = _blockC_T_9 & _mshrs_9_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_22 = _blockC_T_10 & _mshrs_10_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_23 = _blockC_T_11 & _mshrs_11_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_24 = _blockC_T_12 | _blockC_T_13; // @[Mux.scala:30:73]
wire _blockC_T_25 = _blockC_T_24 | _blockC_T_14; // @[Mux.scala:30:73]
wire _blockC_T_26 = _blockC_T_25 | _blockC_T_15; // @[Mux.scala:30:73]
wire _blockC_T_27 = _blockC_T_26 | _blockC_T_16; // @[Mux.scala:30:73]
wire _blockC_T_28 = _blockC_T_27 | _blockC_T_17; // @[Mux.scala:30:73]
wire _blockC_T_29 = _blockC_T_28 | _blockC_T_18; // @[Mux.scala:30:73]
wire _blockC_T_30 = _blockC_T_29 | _blockC_T_19; // @[Mux.scala:30:73]
wire _blockC_T_31 = _blockC_T_30 | _blockC_T_20; // @[Mux.scala:30:73]
wire _blockC_T_32 = _blockC_T_31 | _blockC_T_21; // @[Mux.scala:30:73]
wire _blockC_T_33 = _blockC_T_32 | _blockC_T_22; // @[Mux.scala:30:73]
wire _blockC_T_34 = _blockC_T_33 | _blockC_T_23; // @[Mux.scala:30:73]
wire _blockC_WIRE = _blockC_T_34; // @[Mux.scala:30:73]
wire blockC = _blockC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73]
wire _nestB_T_12 = _nestB_T & _mshrs_0_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_13 = _nestB_T_1 & _mshrs_1_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_14 = _nestB_T_2 & _mshrs_2_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_15 = _nestB_T_3 & _mshrs_3_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_16 = _nestB_T_4 & _mshrs_4_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_17 = _nestB_T_5 & _mshrs_5_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_18 = _nestB_T_6 & _mshrs_6_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_19 = _nestB_T_7 & _mshrs_7_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_20 = _nestB_T_8 & _mshrs_8_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_21 = _nestB_T_9 & _mshrs_9_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_22 = _nestB_T_10 & _mshrs_10_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_23 = _nestB_T_11 & _mshrs_11_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_24 = _nestB_T_12 | _nestB_T_13; // @[Mux.scala:30:73]
wire _nestB_T_25 = _nestB_T_24 | _nestB_T_14; // @[Mux.scala:30:73]
wire _nestB_T_26 = _nestB_T_25 | _nestB_T_15; // @[Mux.scala:30:73]
wire _nestB_T_27 = _nestB_T_26 | _nestB_T_16; // @[Mux.scala:30:73]
wire _nestB_T_28 = _nestB_T_27 | _nestB_T_17; // @[Mux.scala:30:73]
wire _nestB_T_29 = _nestB_T_28 | _nestB_T_18; // @[Mux.scala:30:73]
wire _nestB_T_30 = _nestB_T_29 | _nestB_T_19; // @[Mux.scala:30:73]
wire _nestB_T_31 = _nestB_T_30 | _nestB_T_20; // @[Mux.scala:30:73]
wire _nestB_T_32 = _nestB_T_31 | _nestB_T_21; // @[Mux.scala:30:73]
wire _nestB_T_33 = _nestB_T_32 | _nestB_T_22; // @[Mux.scala:30:73]
wire _nestB_T_34 = _nestB_T_33 | _nestB_T_23; // @[Mux.scala:30:73]
wire _nestB_WIRE = _nestB_T_34; // @[Mux.scala:30:73]
wire _nestC_T_12 = _nestC_T & _mshrs_0_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_13 = _nestC_T_1 & _mshrs_1_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_14 = _nestC_T_2 & _mshrs_2_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_15 = _nestC_T_3 & _mshrs_3_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_16 = _nestC_T_4 & _mshrs_4_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_17 = _nestC_T_5 & _mshrs_5_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_18 = _nestC_T_6 & _mshrs_6_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_19 = _nestC_T_7 & _mshrs_7_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_20 = _nestC_T_8 & _mshrs_8_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_21 = _nestC_T_9 & _mshrs_9_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_22 = _nestC_T_10 & _mshrs_10_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_23 = _nestC_T_11 & _mshrs_11_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_24 = _nestC_T_12 | _nestC_T_13; // @[Mux.scala:30:73]
wire _nestC_T_25 = _nestC_T_24 | _nestC_T_14; // @[Mux.scala:30:73]
wire _nestC_T_26 = _nestC_T_25 | _nestC_T_15; // @[Mux.scala:30:73]
wire _nestC_T_27 = _nestC_T_26 | _nestC_T_16; // @[Mux.scala:30:73]
wire _nestC_T_28 = _nestC_T_27 | _nestC_T_17; // @[Mux.scala:30:73]
wire _nestC_T_29 = _nestC_T_28 | _nestC_T_18; // @[Mux.scala:30:73]
wire _nestC_T_30 = _nestC_T_29 | _nestC_T_19; // @[Mux.scala:30:73]
wire _nestC_T_31 = _nestC_T_30 | _nestC_T_20; // @[Mux.scala:30:73]
wire _nestC_T_32 = _nestC_T_31 | _nestC_T_21; // @[Mux.scala:30:73]
wire _nestC_T_33 = _nestC_T_32 | _nestC_T_22; // @[Mux.scala:30:73]
wire _nestC_T_34 = _nestC_T_33 | _nestC_T_23; // @[Mux.scala:30:73]
wire _nestC_WIRE = _nestC_T_34; // @[Mux.scala:30:73]
wire nestC = _nestC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73]
wire _prioFilter_T = ~request_bits_prio_0; // @[Scheduler.scala:163:21, :182:46]
wire [1:0] prioFilter_hi = {request_bits_prio_2, _prioFilter_T}; // @[Scheduler.scala:163:21, :182:{23,46}]
wire [11:0] prioFilter = {prioFilter_hi, 10'h3FF}; // @[Scheduler.scala:182:23]
wire [11:0] lowerMatches = setMatches & prioFilter; // @[Scheduler.scala:172:23, :182:23, :183:33]
wire _queue_T = |lowerMatches; // @[Scheduler.scala:183:33, :185:28]
wire _queue_T_2 = _queue_T; // @[Scheduler.scala:185:{28,32}]
wire _queue_T_3 = ~nestC; // @[Scheduler.scala:180:70, :185:45]
wire _queue_T_4 = _queue_T_2 & _queue_T_3; // @[Scheduler.scala:185:{32,42,45}]
wire _queue_T_6 = _queue_T_4; // @[Scheduler.scala:185:{42,52}]
wire _queue_T_7 = ~blockC; // @[Scheduler.scala:176:70, :185:66]
wire queue = _queue_T_6 & _queue_T_7; // @[Scheduler.scala:185:{52,63,66}]
wire _T_12 = request_valid & queue; // @[Scheduler.scala:163:21, :185:63, :195:31]
wire _bypass_T; // @[Scheduler.scala:213:30]
assign _bypass_T = _T_12; // @[Scheduler.scala:195:31, :213:30]
wire _bypass_T_1; // @[Scheduler.scala:231:32]
assign _bypass_T_1 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_2; // @[Scheduler.scala:231:32]
assign _bypass_T_2 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_3; // @[Scheduler.scala:231:32]
assign _bypass_T_3 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_4; // @[Scheduler.scala:231:32]
assign _bypass_T_4 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_5; // @[Scheduler.scala:231:32]
assign _bypass_T_5 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_6; // @[Scheduler.scala:231:32]
assign _bypass_T_6 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_7; // @[Scheduler.scala:231:32]
assign _bypass_T_7 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_8; // @[Scheduler.scala:231:32]
assign _bypass_T_8 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_9; // @[Scheduler.scala:231:32]
assign _bypass_T_9 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_10; // @[Scheduler.scala:231:32]
assign _bypass_T_10 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_11; // @[Scheduler.scala:231:32]
assign _bypass_T_11 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_12; // @[Scheduler.scala:231:32]
assign _bypass_T_12 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _requests_io_push_valid_T; // @[Scheduler.scala:270:43]
assign _requests_io_push_valid_T = _T_12; // @[Scheduler.scala:195:31, :270:43]
wire _lowerMatches1_T = lowerMatches[11]; // @[Scheduler.scala:183:33, :200:21]
wire _lowerMatches1_T_2 = lowerMatches[10]; // @[Scheduler.scala:183:33, :201:21]
wire [11:0] _lowerMatches1_T_4 = _lowerMatches1_T_2 ? 12'h400 : lowerMatches; // @[Scheduler.scala:183:33, :201:{8,21}]
wire [11:0] lowerMatches1 = _lowerMatches1_T ? 12'h800 : _lowerMatches1_T_4; // @[Scheduler.scala:200:{8,21}, :201:8]
wire [11:0] _requests_io_push_bits_index_T = lowerMatches1; // @[Scheduler.scala:200:8, :274:30]
wire [23:0] _GEN_1 = {2{mshr_selectOH}}; // @[Scheduler.scala:121:70, :206:30]
wire [23:0] selected_requests_hi; // @[Scheduler.scala:206:30]
assign selected_requests_hi = _GEN_1; // @[Scheduler.scala:206:30]
wire [23:0] pop_index_hi; // @[Scheduler.scala:241:31]
assign pop_index_hi = _GEN_1; // @[Scheduler.scala:206:30, :241:31]
wire [35:0] _selected_requests_T = {selected_requests_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :206:30]
wire [35:0] selected_requests = _selected_requests_T & _requests_io_valid; // @[Scheduler.scala:70:24, :206:{30,76}]
wire [11:0] _a_pop_T = selected_requests[11:0]; // @[Scheduler.scala:206:76, :207:32]
wire a_pop = |_a_pop_T; // @[Scheduler.scala:207:{32,79}]
wire [11:0] _b_pop_T = selected_requests[23:12]; // @[Scheduler.scala:206:76, :208:32]
wire b_pop = |_b_pop_T; // @[Scheduler.scala:208:{32,79}]
wire _bypassMatches_T_4 = b_pop; // @[Scheduler.scala:208:79, :211:76]
wire [11:0] _c_pop_T = selected_requests[35:24]; // @[Scheduler.scala:206:76, :209:32]
wire c_pop = |_c_pop_T; // @[Scheduler.scala:209:{32,79}]
wire [11:0] _bypassMatches_T = mshr_selectOH & lowerMatches1; // @[Scheduler.scala:121:70, :200:8, :210:38]
wire _bypassMatches_T_1 = |_bypassMatches_T; // @[Scheduler.scala:210:{38,55}]
wire _bypassMatches_T_2 = c_pop | request_bits_prio_2; // @[Scheduler.scala:163:21, :209:79, :211:33]
wire _bypassMatches_T_3 = ~c_pop; // @[Scheduler.scala:209:79, :211:58]
wire _bypassMatches_T_5 = ~b_pop; // @[Scheduler.scala:208:79, :211:101]
wire _bypassMatches_T_6 = ~a_pop; // @[Scheduler.scala:207:79, :211:109]
wire _bypassMatches_T_7 = _bypassMatches_T_4 ? _bypassMatches_T_5 : _bypassMatches_T_6; // @[Scheduler.scala:211:{69,76,101,109}]
wire _bypassMatches_T_8 = _bypassMatches_T_2 ? _bypassMatches_T_3 : _bypassMatches_T_7; // @[Scheduler.scala:211:{26,33,58,69}]
wire bypassMatches = _bypassMatches_T_1 & _bypassMatches_T_8; // @[Scheduler.scala:210:{55,59}, :211:26]
wire _may_pop_T = a_pop | b_pop; // @[Scheduler.scala:207:79, :208:79, :212:23]
wire may_pop = _may_pop_T | c_pop; // @[Scheduler.scala:209:79, :212:{23,32}]
wire bypass = _bypass_T & bypassMatches; // @[Scheduler.scala:210:59, :213:{30,39}]
wire _will_reload_T = may_pop | bypass; // @[Scheduler.scala:212:32, :213:39, :214:49]
wire will_reload = schedule_reload & _will_reload_T; // @[Mux.scala:30:73]
wire _GEN_2 = schedule_reload & may_pop; // @[Mux.scala:30:73]
wire _will_pop_T; // @[Scheduler.scala:215:34]
assign _will_pop_T = _GEN_2; // @[Scheduler.scala:215:34]
wire _mshr_uses_directory_assuming_no_bypass_T; // @[Scheduler.scala:247:64]
assign _mshr_uses_directory_assuming_no_bypass_T = _GEN_2; // @[Scheduler.scala:215:34, :247:64]
wire _will_pop_T_1 = ~bypass; // @[Scheduler.scala:213:39, :215:48]
wire will_pop = _will_pop_T & _will_pop_T_1; // @[Scheduler.scala:215:{34,45,48}]
wire a_pop_1 = _requests_io_valid[0]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_1 = _requests_io_valid[12]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_12 = b_pop_1; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_1 = _requests_io_valid[24]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_9 = lowerMatches1[0]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_10 = c_pop_1 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_11 = ~c_pop_1; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_13 = ~b_pop_1; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_14 = ~a_pop_1; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_15 = _bypassMatches_T_12 ? _bypassMatches_T_13 : _bypassMatches_T_14; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_16 = _bypassMatches_T_10 ? _bypassMatches_T_11 : _bypassMatches_T_15; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_1 = _bypassMatches_T_9 & _bypassMatches_T_16; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_1 = a_pop_1 | b_pop_1; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_1 = _may_pop_T_1 | c_pop_1; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_1 = _bypass_T_1 & bypassMatches_1; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_1 = may_pop_1 | bypass_1; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_1 = _mshrs_0_io_schedule_bits_reload & _will_reload_T_1; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_prio_0 = bypass_1 ? _view__WIRE_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_prio_1 = ~bypass_1 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_prio_2 = bypass_1 ? _view__WIRE_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_control = bypass_1 ? _view__WIRE_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_opcode = bypass_1 ? _view__WIRE_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_param = bypass_1 ? _view__WIRE_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_size = bypass_1 ? _view__WIRE_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_source = bypass_1 ? _view__WIRE_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_tag = bypass_1 ? _view__WIRE_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_offset = bypass_1 ? _view__WIRE_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_put = bypass_1 ? _view__WIRE_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_0_io_allocate_bits_repeat_T = mshrs_0_io_allocate_bits_tag == _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_0_io_allocate_valid_T = sel & will_reload_1; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_2 = _requests_io_valid[1]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_2 = _requests_io_valid[13]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_20 = b_pop_2; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_2 = _requests_io_valid[25]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_17 = lowerMatches1[1]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_18 = c_pop_2 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_19 = ~c_pop_2; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_21 = ~b_pop_2; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_22 = ~a_pop_2; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_23 = _bypassMatches_T_20 ? _bypassMatches_T_21 : _bypassMatches_T_22; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_24 = _bypassMatches_T_18 ? _bypassMatches_T_19 : _bypassMatches_T_23; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_2 = _bypassMatches_T_17 & _bypassMatches_T_24; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_2 = a_pop_2 | b_pop_2; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_2 = _may_pop_T_2 | c_pop_2; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_2 = _bypass_T_2 & bypassMatches_2; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_2 = may_pop_2 | bypass_2; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_2 = _mshrs_1_io_schedule_bits_reload & _will_reload_T_2; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_1_prio_0 = bypass_2 ? _view__WIRE_1_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_1_prio_1 = ~bypass_2 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_1_prio_2 = bypass_2 ? _view__WIRE_1_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_1_control = bypass_2 ? _view__WIRE_1_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_1_opcode = bypass_2 ? _view__WIRE_1_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_1_param = bypass_2 ? _view__WIRE_1_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_1_size = bypass_2 ? _view__WIRE_1_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_1_source = bypass_2 ? _view__WIRE_1_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_1_tag = bypass_2 ? _view__WIRE_1_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_1_offset = bypass_2 ? _view__WIRE_1_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_1_put = bypass_2 ? _view__WIRE_1_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_1_io_allocate_bits_repeat_T = mshrs_1_io_allocate_bits_tag == _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_1_io_allocate_valid_T = sel_1 & will_reload_2; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_3 = _requests_io_valid[2]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_3 = _requests_io_valid[14]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_28 = b_pop_3; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_3 = _requests_io_valid[26]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_25 = lowerMatches1[2]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_26 = c_pop_3 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_27 = ~c_pop_3; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_29 = ~b_pop_3; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_30 = ~a_pop_3; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_31 = _bypassMatches_T_28 ? _bypassMatches_T_29 : _bypassMatches_T_30; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_32 = _bypassMatches_T_26 ? _bypassMatches_T_27 : _bypassMatches_T_31; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_3 = _bypassMatches_T_25 & _bypassMatches_T_32; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_3 = a_pop_3 | b_pop_3; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_3 = _may_pop_T_3 | c_pop_3; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_3 = _bypass_T_3 & bypassMatches_3; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_3 = may_pop_3 | bypass_3; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_3 = _mshrs_2_io_schedule_bits_reload & _will_reload_T_3; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_2_prio_0 = bypass_3 ? _view__WIRE_2_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_2_prio_1 = ~bypass_3 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_2_prio_2 = bypass_3 ? _view__WIRE_2_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_2_control = bypass_3 ? _view__WIRE_2_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_2_opcode = bypass_3 ? _view__WIRE_2_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_2_param = bypass_3 ? _view__WIRE_2_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_2_size = bypass_3 ? _view__WIRE_2_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_2_source = bypass_3 ? _view__WIRE_2_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_2_tag = bypass_3 ? _view__WIRE_2_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_2_offset = bypass_3 ? _view__WIRE_2_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_2_put = bypass_3 ? _view__WIRE_2_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_2_io_allocate_bits_repeat_T = mshrs_2_io_allocate_bits_tag == _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_2_io_allocate_valid_T = sel_2 & will_reload_3; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_4 = _requests_io_valid[3]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_4 = _requests_io_valid[15]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_36 = b_pop_4; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_4 = _requests_io_valid[27]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_33 = lowerMatches1[3]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_34 = c_pop_4 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_35 = ~c_pop_4; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_37 = ~b_pop_4; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_38 = ~a_pop_4; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_39 = _bypassMatches_T_36 ? _bypassMatches_T_37 : _bypassMatches_T_38; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_40 = _bypassMatches_T_34 ? _bypassMatches_T_35 : _bypassMatches_T_39; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_4 = _bypassMatches_T_33 & _bypassMatches_T_40; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_4 = a_pop_4 | b_pop_4; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_4 = _may_pop_T_4 | c_pop_4; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_4 = _bypass_T_4 & bypassMatches_4; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_4 = may_pop_4 | bypass_4; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_4 = _mshrs_3_io_schedule_bits_reload & _will_reload_T_4; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_3_prio_0 = bypass_4 ? _view__WIRE_3_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_3_prio_1 = ~bypass_4 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_3_prio_2 = bypass_4 ? _view__WIRE_3_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_3_control = bypass_4 ? _view__WIRE_3_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_3_opcode = bypass_4 ? _view__WIRE_3_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_3_param = bypass_4 ? _view__WIRE_3_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_3_size = bypass_4 ? _view__WIRE_3_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_3_source = bypass_4 ? _view__WIRE_3_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_3_tag = bypass_4 ? _view__WIRE_3_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_3_offset = bypass_4 ? _view__WIRE_3_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_3_put = bypass_4 ? _view__WIRE_3_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_3_io_allocate_bits_repeat_T = mshrs_3_io_allocate_bits_tag == _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_3_io_allocate_valid_T = sel_3 & will_reload_4; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_5 = _requests_io_valid[4]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_5 = _requests_io_valid[16]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_44 = b_pop_5; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_5 = _requests_io_valid[28]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_41 = lowerMatches1[4]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_42 = c_pop_5 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_43 = ~c_pop_5; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_45 = ~b_pop_5; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_46 = ~a_pop_5; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_47 = _bypassMatches_T_44 ? _bypassMatches_T_45 : _bypassMatches_T_46; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_48 = _bypassMatches_T_42 ? _bypassMatches_T_43 : _bypassMatches_T_47; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_5 = _bypassMatches_T_41 & _bypassMatches_T_48; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_5 = a_pop_5 | b_pop_5; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_5 = _may_pop_T_5 | c_pop_5; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_5 = _bypass_T_5 & bypassMatches_5; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_5 = may_pop_5 | bypass_5; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_5 = _mshrs_4_io_schedule_bits_reload & _will_reload_T_5; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_4_prio_0 = bypass_5 ? _view__WIRE_4_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_4_prio_1 = ~bypass_5 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_4_prio_2 = bypass_5 ? _view__WIRE_4_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_4_control = bypass_5 ? _view__WIRE_4_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_4_opcode = bypass_5 ? _view__WIRE_4_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_4_param = bypass_5 ? _view__WIRE_4_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_4_size = bypass_5 ? _view__WIRE_4_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_4_source = bypass_5 ? _view__WIRE_4_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_4_tag = bypass_5 ? _view__WIRE_4_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_4_offset = bypass_5 ? _view__WIRE_4_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_4_put = bypass_5 ? _view__WIRE_4_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_4_io_allocate_bits_repeat_T = mshrs_4_io_allocate_bits_tag == _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_4_io_allocate_valid_T = sel_4 & will_reload_5; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_6 = _requests_io_valid[5]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_6 = _requests_io_valid[17]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_52 = b_pop_6; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_6 = _requests_io_valid[29]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_49 = lowerMatches1[5]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_50 = c_pop_6 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_51 = ~c_pop_6; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_53 = ~b_pop_6; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_54 = ~a_pop_6; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_55 = _bypassMatches_T_52 ? _bypassMatches_T_53 : _bypassMatches_T_54; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_56 = _bypassMatches_T_50 ? _bypassMatches_T_51 : _bypassMatches_T_55; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_6 = _bypassMatches_T_49 & _bypassMatches_T_56; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_6 = a_pop_6 | b_pop_6; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_6 = _may_pop_T_6 | c_pop_6; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_6 = _bypass_T_6 & bypassMatches_6; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_6 = may_pop_6 | bypass_6; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_6 = _mshrs_5_io_schedule_bits_reload & _will_reload_T_6; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_5_prio_0 = bypass_6 ? _view__WIRE_5_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_5_prio_1 = ~bypass_6 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_5_prio_2 = bypass_6 ? _view__WIRE_5_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_5_control = bypass_6 ? _view__WIRE_5_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_5_opcode = bypass_6 ? _view__WIRE_5_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_5_param = bypass_6 ? _view__WIRE_5_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_5_size = bypass_6 ? _view__WIRE_5_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_5_source = bypass_6 ? _view__WIRE_5_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_5_tag = bypass_6 ? _view__WIRE_5_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_5_offset = bypass_6 ? _view__WIRE_5_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_5_put = bypass_6 ? _view__WIRE_5_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_5_io_allocate_bits_repeat_T = mshrs_5_io_allocate_bits_tag == _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_5_io_allocate_valid_T = sel_5 & will_reload_6; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_7 = _requests_io_valid[6]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_7 = _requests_io_valid[18]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_60 = b_pop_7; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_7 = _requests_io_valid[30]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_57 = lowerMatches1[6]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_58 = c_pop_7 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_59 = ~c_pop_7; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_61 = ~b_pop_7; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_62 = ~a_pop_7; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_63 = _bypassMatches_T_60 ? _bypassMatches_T_61 : _bypassMatches_T_62; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_64 = _bypassMatches_T_58 ? _bypassMatches_T_59 : _bypassMatches_T_63; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_7 = _bypassMatches_T_57 & _bypassMatches_T_64; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_7 = a_pop_7 | b_pop_7; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_7 = _may_pop_T_7 | c_pop_7; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_7 = _bypass_T_7 & bypassMatches_7; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_7 = may_pop_7 | bypass_7; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_7 = _mshrs_6_io_schedule_bits_reload & _will_reload_T_7; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_6_prio_0 = bypass_7 ? _view__WIRE_6_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_6_prio_1 = ~bypass_7 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_6_prio_2 = bypass_7 ? _view__WIRE_6_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_6_control = bypass_7 ? _view__WIRE_6_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_6_opcode = bypass_7 ? _view__WIRE_6_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_6_param = bypass_7 ? _view__WIRE_6_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_6_size = bypass_7 ? _view__WIRE_6_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_6_source = bypass_7 ? _view__WIRE_6_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_6_tag = bypass_7 ? _view__WIRE_6_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_6_offset = bypass_7 ? _view__WIRE_6_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_6_put = bypass_7 ? _view__WIRE_6_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_6_io_allocate_bits_repeat_T = mshrs_6_io_allocate_bits_tag == _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_6_io_allocate_valid_T = sel_6 & will_reload_7; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_8 = _requests_io_valid[7]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_8 = _requests_io_valid[19]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_68 = b_pop_8; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_8 = _requests_io_valid[31]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_65 = lowerMatches1[7]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_66 = c_pop_8 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_67 = ~c_pop_8; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_69 = ~b_pop_8; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_70 = ~a_pop_8; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_71 = _bypassMatches_T_68 ? _bypassMatches_T_69 : _bypassMatches_T_70; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_72 = _bypassMatches_T_66 ? _bypassMatches_T_67 : _bypassMatches_T_71; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_8 = _bypassMatches_T_65 & _bypassMatches_T_72; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_8 = a_pop_8 | b_pop_8; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_8 = _may_pop_T_8 | c_pop_8; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_8 = _bypass_T_8 & bypassMatches_8; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_8 = may_pop_8 | bypass_8; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_8 = _mshrs_7_io_schedule_bits_reload & _will_reload_T_8; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_7_prio_0 = bypass_8 ? _view__WIRE_7_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_7_prio_1 = ~bypass_8 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_7_prio_2 = bypass_8 ? _view__WIRE_7_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_7_control = bypass_8 ? _view__WIRE_7_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_7_opcode = bypass_8 ? _view__WIRE_7_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_7_param = bypass_8 ? _view__WIRE_7_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_7_size = bypass_8 ? _view__WIRE_7_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_7_source = bypass_8 ? _view__WIRE_7_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_7_tag = bypass_8 ? _view__WIRE_7_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_7_offset = bypass_8 ? _view__WIRE_7_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_7_put = bypass_8 ? _view__WIRE_7_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_7_io_allocate_bits_repeat_T = mshrs_7_io_allocate_bits_tag == _mshrs_7_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_7_io_allocate_valid_T = sel_7 & will_reload_8; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_9 = _requests_io_valid[8]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_9 = _requests_io_valid[20]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_76 = b_pop_9; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_9 = _requests_io_valid[32]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_73 = lowerMatches1[8]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_74 = c_pop_9 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_75 = ~c_pop_9; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_77 = ~b_pop_9; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_78 = ~a_pop_9; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_79 = _bypassMatches_T_76 ? _bypassMatches_T_77 : _bypassMatches_T_78; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_80 = _bypassMatches_T_74 ? _bypassMatches_T_75 : _bypassMatches_T_79; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_9 = _bypassMatches_T_73 & _bypassMatches_T_80; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_9 = a_pop_9 | b_pop_9; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_9 = _may_pop_T_9 | c_pop_9; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_9 = _bypass_T_9 & bypassMatches_9; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_9 = may_pop_9 | bypass_9; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_9 = _mshrs_8_io_schedule_bits_reload & _will_reload_T_9; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_8_prio_0 = bypass_9 ? _view__WIRE_8_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_8_prio_1 = ~bypass_9 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_8_prio_2 = bypass_9 ? _view__WIRE_8_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_8_control = bypass_9 ? _view__WIRE_8_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_8_opcode = bypass_9 ? _view__WIRE_8_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_8_param = bypass_9 ? _view__WIRE_8_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_8_size = bypass_9 ? _view__WIRE_8_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_8_source = bypass_9 ? _view__WIRE_8_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_8_tag = bypass_9 ? _view__WIRE_8_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_8_offset = bypass_9 ? _view__WIRE_8_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_8_put = bypass_9 ? _view__WIRE_8_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_8_io_allocate_bits_repeat_T = mshrs_8_io_allocate_bits_tag == _mshrs_8_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_8_io_allocate_valid_T = sel_8 & will_reload_9; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_10 = _requests_io_valid[9]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_10 = _requests_io_valid[21]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_84 = b_pop_10; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_10 = _requests_io_valid[33]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_81 = lowerMatches1[9]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_82 = c_pop_10 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_83 = ~c_pop_10; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_85 = ~b_pop_10; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_86 = ~a_pop_10; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_87 = _bypassMatches_T_84 ? _bypassMatches_T_85 : _bypassMatches_T_86; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_88 = _bypassMatches_T_82 ? _bypassMatches_T_83 : _bypassMatches_T_87; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_10 = _bypassMatches_T_81 & _bypassMatches_T_88; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_10 = a_pop_10 | b_pop_10; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_10 = _may_pop_T_10 | c_pop_10; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_10 = _bypass_T_10 & bypassMatches_10; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_10 = may_pop_10 | bypass_10; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_10 = _mshrs_9_io_schedule_bits_reload & _will_reload_T_10; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_9_prio_0 = bypass_10 ? _view__WIRE_9_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_9_prio_1 = ~bypass_10 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_9_prio_2 = bypass_10 ? _view__WIRE_9_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_9_control = bypass_10 ? _view__WIRE_9_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_9_opcode = bypass_10 ? _view__WIRE_9_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_9_param = bypass_10 ? _view__WIRE_9_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_9_size = bypass_10 ? _view__WIRE_9_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_9_source = bypass_10 ? _view__WIRE_9_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_9_tag = bypass_10 ? _view__WIRE_9_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_9_offset = bypass_10 ? _view__WIRE_9_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_9_put = bypass_10 ? _view__WIRE_9_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_9_io_allocate_bits_repeat_T = mshrs_9_io_allocate_bits_tag == _mshrs_9_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_9_io_allocate_valid_T = sel_9 & will_reload_10; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_11 = _requests_io_valid[10]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_11 = _requests_io_valid[22]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_92 = b_pop_11; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_11 = _requests_io_valid[34]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_89 = lowerMatches1[10]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_90 = c_pop_11 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_91 = ~c_pop_11; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_93 = ~b_pop_11; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_94 = ~a_pop_11; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_95 = _bypassMatches_T_92 ? _bypassMatches_T_93 : _bypassMatches_T_94; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_96 = _bypassMatches_T_90 ? _bypassMatches_T_91 : _bypassMatches_T_95; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_11 = _bypassMatches_T_89 & _bypassMatches_T_96; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_11 = a_pop_11 | b_pop_11; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_11 = _may_pop_T_11 | c_pop_11; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_11 = _bypass_T_11 & bypassMatches_11; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_11 = may_pop_11 | bypass_11; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_11 = _mshrs_10_io_schedule_bits_reload & _will_reload_T_11; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_10_prio_0 = bypass_11 ? _view__WIRE_10_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_10_prio_1 = ~bypass_11 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_10_prio_2 = bypass_11 ? _view__WIRE_10_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_10_control = bypass_11 ? _view__WIRE_10_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_10_opcode = bypass_11 ? _view__WIRE_10_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_10_param = bypass_11 ? _view__WIRE_10_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_10_size = bypass_11 ? _view__WIRE_10_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_10_source = bypass_11 ? _view__WIRE_10_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_10_tag = bypass_11 ? _view__WIRE_10_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_10_offset = bypass_11 ? _view__WIRE_10_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_10_put = bypass_11 ? _view__WIRE_10_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_10_io_allocate_bits_repeat_T = mshrs_10_io_allocate_bits_tag == _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :287:131, :289:74]
wire _mshrs_10_io_allocate_valid_T = sel_10 & will_reload_11; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_12 = _requests_io_valid[11]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_12 = _requests_io_valid[23]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_100 = b_pop_12; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_12 = _requests_io_valid[35]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_97 = lowerMatches1[11]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_98 = c_pop_12 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_99 = ~c_pop_12; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_101 = ~b_pop_12; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_102 = ~a_pop_12; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_103 = _bypassMatches_T_100 ? _bypassMatches_T_101 : _bypassMatches_T_102; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_104 = _bypassMatches_T_98 ? _bypassMatches_T_99 : _bypassMatches_T_103; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_12 = _bypassMatches_T_97 & _bypassMatches_T_104; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_12 = a_pop_12 | b_pop_12; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_12 = _may_pop_T_12 | c_pop_12; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_12 = _bypass_T_12 & bypassMatches_12; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_12 = may_pop_12 | bypass_12; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_12 = _mshrs_11_io_schedule_bits_reload & _will_reload_T_12; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_11_prio_0 = bypass_12 ? _view__WIRE_11_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_11_prio_1 = ~bypass_12 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_11_prio_2 = bypass_12 ? _view__WIRE_11_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_11_control = bypass_12 ? _view__WIRE_11_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_11_opcode = bypass_12 ? _view__WIRE_11_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_11_param = bypass_12 ? _view__WIRE_11_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_11_size = bypass_12 ? _view__WIRE_11_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_11_source = bypass_12 ? _view__WIRE_11_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_11_tag = bypass_12 ? _view__WIRE_11_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_11_offset = bypass_12 ? _view__WIRE_11_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_11_put = bypass_12 ? _view__WIRE_11_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_11_io_allocate_bits_repeat_T = mshrs_11_io_allocate_bits_tag == _mshrs_11_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :295:103, :297:73]
wire _mshrs_11_io_allocate_valid_T = sel_11 & will_reload_12; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire [35:0] _prio_requests_T = ~_requests_io_valid; // @[Scheduler.scala:70:24, :240:25]
wire [23:0] _prio_requests_T_1 = _requests_io_valid[35:12]; // @[Scheduler.scala:70:24, :240:65]
wire [35:0] _prio_requests_T_2 = {_prio_requests_T[35:24], _prio_requests_T[23:0] | _prio_requests_T_1}; // @[Scheduler.scala:240:{25,44,65}]
wire [11:0] _prio_requests_T_3 = _requests_io_valid[35:24]; // @[Scheduler.scala:70:24, :240:103]
wire [35:0] _prio_requests_T_4 = {_prio_requests_T_2[35:12], _prio_requests_T_2[11:0] | _prio_requests_T_3}; // @[Scheduler.scala:240:{44,82,103}]
wire [35:0] prio_requests = ~_prio_requests_T_4; // @[Scheduler.scala:240:{23,82}]
wire [35:0] _pop_index_T = {pop_index_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :241:31]
wire [35:0] _pop_index_T_1 = _pop_index_T & prio_requests; // @[Scheduler.scala:240:23, :241:{31,77}]
wire [3:0] pop_index_hi_1 = _pop_index_T_1[35:32]; // @[OneHot.scala:30:18]
wire [31:0] pop_index_lo = _pop_index_T_1[31:0]; // @[OneHot.scala:31:18]
wire _pop_index_T_2 = |pop_index_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [31:0] _pop_index_T_3 = {28'h0, pop_index_hi_1} | pop_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [15:0] pop_index_hi_2 = _pop_index_T_3[31:16]; // @[OneHot.scala:30:18, :32:28]
wire [15:0] pop_index_lo_1 = _pop_index_T_3[15:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_4 = |pop_index_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _pop_index_T_5 = pop_index_hi_2 | pop_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] pop_index_hi_3 = _pop_index_T_5[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] pop_index_lo_2 = _pop_index_T_5[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_6 = |pop_index_hi_3; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _pop_index_T_7 = pop_index_hi_3 | pop_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] pop_index_hi_4 = _pop_index_T_7[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] pop_index_lo_3 = _pop_index_T_7[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_8 = |pop_index_hi_4; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _pop_index_T_9 = pop_index_hi_4 | pop_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] pop_index_hi_5 = _pop_index_T_9[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] pop_index_lo_4 = _pop_index_T_9[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_10 = |pop_index_hi_5; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _pop_index_T_11 = pop_index_hi_5 | pop_index_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _pop_index_T_12 = _pop_index_T_11[1]; // @[OneHot.scala:32:28]
wire [1:0] _pop_index_T_13 = {_pop_index_T_10, _pop_index_T_12}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _pop_index_T_14 = {_pop_index_T_8, _pop_index_T_13}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _pop_index_T_15 = {_pop_index_T_6, _pop_index_T_14}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _pop_index_T_16 = {_pop_index_T_4, _pop_index_T_15}; // @[OneHot.scala:32:{10,14}]
wire [5:0] pop_index = {_pop_index_T_2, _pop_index_T_16}; // @[OneHot.scala:32:{10,14}]
wire lb_tag_mismatch = scheduleTag != _requests_io_data_tag; // @[Mux.scala:30:73]
wire mshr_uses_directory_assuming_no_bypass = _mshr_uses_directory_assuming_no_bypass_T & lb_tag_mismatch; // @[Scheduler.scala:246:37, :247:{64,75}]
wire mshr_uses_directory_for_lb = will_pop & lb_tag_mismatch; // @[Scheduler.scala:215:45, :246:37, :248:45]
wire [8:0] _mshr_uses_directory_T = bypass ? request_bits_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :163:21, :213:39, :249:63]
wire _mshr_uses_directory_T_1 = scheduleTag != _mshr_uses_directory_T; // @[Mux.scala:30:73]
wire mshr_uses_directory = will_reload & _mshr_uses_directory_T_1; // @[Scheduler.scala:214:37, :249:{41,56}]
wire [1:0] mshr_validOH_lo_lo_hi = {_mshrs_2_io_status_valid, _mshrs_1_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_lo_lo = {mshr_validOH_lo_lo_hi, _mshrs_0_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [1:0] mshr_validOH_lo_hi_hi = {_mshrs_5_io_status_valid, _mshrs_4_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_lo_hi = {mshr_validOH_lo_hi_hi, _mshrs_3_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [5:0] mshr_validOH_lo = {mshr_validOH_lo_hi, mshr_validOH_lo_lo}; // @[Scheduler.scala:252:25]
wire [1:0] mshr_validOH_hi_lo_hi = {_mshrs_8_io_status_valid, _mshrs_7_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_hi_lo = {mshr_validOH_hi_lo_hi, _mshrs_6_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [1:0] mshr_validOH_hi_hi_hi = {_mshrs_11_io_status_valid, _mshrs_10_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_hi_hi = {mshr_validOH_hi_hi_hi, _mshrs_9_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [5:0] mshr_validOH_hi = {mshr_validOH_hi_hi, mshr_validOH_hi_lo}; // @[Scheduler.scala:252:25]
wire [11:0] mshr_validOH = {mshr_validOH_hi, mshr_validOH_lo}; // @[Scheduler.scala:252:25]
wire [11:0] _mshr_free_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20]
wire [11:0] _mshr_free_T_1 = _mshr_free_T & prioFilter; // @[Scheduler.scala:182:23, :253:{20,34}]
wire mshr_free = |_mshr_free_T_1; // @[Scheduler.scala:253:{34,48}]
wire bypassQueue = schedule_reload & bypassMatches; // @[Mux.scala:30:73]
wire _request_alloc_cases_T = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16]
wire _request_alloc_cases_T_1 = alloc & _request_alloc_cases_T; // @[Scheduler.scala:173:15, :258:{13,16}]
wire _request_alloc_cases_T_2 = _request_alloc_cases_T_1 & mshr_free; // @[Scheduler.scala:253:48, :258:{13,56}]
wire _request_alloc_cases_T_9 = _request_alloc_cases_T_2; // @[Scheduler.scala:258:{56,70}]
wire _request_alloc_cases_T_3 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :259:16]
wire _request_alloc_cases_T_5 = ~_mshrs_10_io_status_valid; // @[Scheduler.scala:71:46, :259:59]
wire _request_alloc_cases_T_7 = ~_mshrs_11_io_status_valid; // @[Scheduler.scala:71:46, :259:87]
wire _request_alloc_cases_T_10 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :260:16]
wire _request_alloc_cases_T_11 = nestC & _request_alloc_cases_T_10; // @[Scheduler.scala:180:70, :260:{13,16}]
wire _request_alloc_cases_T_12 = ~_mshrs_11_io_status_valid; // @[Scheduler.scala:71:46, :259:87, :260:59]
wire _request_alloc_cases_T_13 = _request_alloc_cases_T_11 & _request_alloc_cases_T_12; // @[Scheduler.scala:260:{13,56,59}]
wire request_alloc_cases = _request_alloc_cases_T_9 | _request_alloc_cases_T_13; // @[Scheduler.scala:258:70, :259:112, :260:56]
wire _request_ready_T = bypassQueue | _requests_io_push_ready; // @[Scheduler.scala:70:24, :256:37, :261:66]
wire _request_ready_T_1 = queue & _request_ready_T; // @[Scheduler.scala:185:63, :261:{50,66}]
assign _request_ready_T_2 = request_alloc_cases | _request_ready_T_1; // @[Scheduler.scala:259:112, :261:{40,50}]
assign request_ready = _request_ready_T_2; // @[Scheduler.scala:163:21, :261:40]
wire alloc_uses_directory = request_valid & request_alloc_cases; // @[Scheduler.scala:163:21, :259:112, :262:44]
wire _directory_io_read_valid_T = mshr_uses_directory | alloc_uses_directory; // @[Scheduler.scala:249:41, :262:44, :265:50]
wire [10:0] _directory_io_read_bits_set_T = mshr_uses_directory_for_lb ? scheduleSet : request_bits_set; // @[Mux.scala:30:73]
wire [8:0] _directory_io_read_bits_tag_T = mshr_uses_directory_for_lb ? _requests_io_data_tag : request_bits_tag; // @[Scheduler.scala:70:24, :163:21, :248:45, :267:36]
wire _requests_io_push_valid_T_1 = ~bypassQueue; // @[Scheduler.scala:256:37, :270:55]
wire _requests_io_push_valid_T_2 = _requests_io_push_valid_T & _requests_io_push_valid_T_1; // @[Scheduler.scala:270:{43,52,55}]
wire [3:0] requests_io_push_bits_index_hi = _requests_io_push_bits_index_T[11:8]; // @[OneHot.scala:30:18]
wire [7:0] requests_io_push_bits_index_lo = _requests_io_push_bits_index_T[7:0]; // @[OneHot.scala:31:18]
wire _requests_io_push_bits_index_T_1 = |requests_io_push_bits_index_hi; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _requests_io_push_bits_index_T_2 = {4'h0, requests_io_push_bits_index_hi} | requests_io_push_bits_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] requests_io_push_bits_index_hi_1 = _requests_io_push_bits_index_T_2[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] requests_io_push_bits_index_lo_1 = _requests_io_push_bits_index_T_2[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_3 = |requests_io_push_bits_index_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _requests_io_push_bits_index_T_4 = requests_io_push_bits_index_hi_1 | requests_io_push_bits_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] requests_io_push_bits_index_hi_2 = _requests_io_push_bits_index_T_4[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] requests_io_push_bits_index_lo_2 = _requests_io_push_bits_index_T_4[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_5 = |requests_io_push_bits_index_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _requests_io_push_bits_index_T_6 = requests_io_push_bits_index_hi_2 | requests_io_push_bits_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _requests_io_push_bits_index_T_7 = _requests_io_push_bits_index_T_6[1]; // @[OneHot.scala:32:28]
wire [1:0] _requests_io_push_bits_index_T_8 = {_requests_io_push_bits_index_T_5, _requests_io_push_bits_index_T_7}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _requests_io_push_bits_index_T_9 = {_requests_io_push_bits_index_T_3, _requests_io_push_bits_index_T_8}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_10 = {_requests_io_push_bits_index_T_1, _requests_io_push_bits_index_T_9}; // @[OneHot.scala:32:{10,14}]
wire [23:0] _requests_io_push_bits_index_T_11 = {lowerMatches1, 12'h0}; // @[Scheduler.scala:200:8, :275:30]
wire [7:0] requests_io_push_bits_index_hi_3 = _requests_io_push_bits_index_T_11[23:16]; // @[OneHot.scala:30:18]
wire [15:0] requests_io_push_bits_index_lo_3 = _requests_io_push_bits_index_T_11[15:0]; // @[OneHot.scala:31:18]
wire _requests_io_push_bits_index_T_12 = |requests_io_push_bits_index_hi_3; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _requests_io_push_bits_index_T_13 = {8'h0, requests_io_push_bits_index_hi_3} | requests_io_push_bits_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] requests_io_push_bits_index_hi_4 = _requests_io_push_bits_index_T_13[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] requests_io_push_bits_index_lo_4 = _requests_io_push_bits_index_T_13[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_14 = |requests_io_push_bits_index_hi_4; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _requests_io_push_bits_index_T_15 = requests_io_push_bits_index_hi_4 | requests_io_push_bits_index_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] requests_io_push_bits_index_hi_5 = _requests_io_push_bits_index_T_15[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] requests_io_push_bits_index_lo_5 = _requests_io_push_bits_index_T_15[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_16 = |requests_io_push_bits_index_hi_5; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _requests_io_push_bits_index_T_17 = requests_io_push_bits_index_hi_5 | requests_io_push_bits_index_lo_5; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] requests_io_push_bits_index_hi_6 = _requests_io_push_bits_index_T_17[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] requests_io_push_bits_index_lo_6 = _requests_io_push_bits_index_T_17[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_18 = |requests_io_push_bits_index_hi_6; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _requests_io_push_bits_index_T_19 = requests_io_push_bits_index_hi_6 | requests_io_push_bits_index_lo_6; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _requests_io_push_bits_index_T_20 = _requests_io_push_bits_index_T_19[1]; // @[OneHot.scala:32:28]
wire [1:0] _requests_io_push_bits_index_T_21 = {_requests_io_push_bits_index_T_18, _requests_io_push_bits_index_T_20}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _requests_io_push_bits_index_T_22 = {_requests_io_push_bits_index_T_16, _requests_io_push_bits_index_T_21}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_23 = {_requests_io_push_bits_index_T_14, _requests_io_push_bits_index_T_22}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _requests_io_push_bits_index_T_24 = {_requests_io_push_bits_index_T_12, _requests_io_push_bits_index_T_23}; // @[OneHot.scala:32:{10,14}]
wire [35:0] _requests_io_push_bits_index_T_25 = {lowerMatches1, 24'h0}; // @[Scheduler.scala:200:8, :276:30]
wire [3:0] requests_io_push_bits_index_hi_7 = _requests_io_push_bits_index_T_25[35:32]; // @[OneHot.scala:30:18]
wire [31:0] requests_io_push_bits_index_lo_7 = _requests_io_push_bits_index_T_25[31:0]; // @[OneHot.scala:31:18]
wire _requests_io_push_bits_index_T_26 = |requests_io_push_bits_index_hi_7; // @[OneHot.scala:30:18, :32:14]
wire [31:0] _requests_io_push_bits_index_T_27 = {28'h0, requests_io_push_bits_index_hi_7} | requests_io_push_bits_index_lo_7; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [15:0] requests_io_push_bits_index_hi_8 = _requests_io_push_bits_index_T_27[31:16]; // @[OneHot.scala:30:18, :32:28]
wire [15:0] requests_io_push_bits_index_lo_8 = _requests_io_push_bits_index_T_27[15:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_28 = |requests_io_push_bits_index_hi_8; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _requests_io_push_bits_index_T_29 = requests_io_push_bits_index_hi_8 | requests_io_push_bits_index_lo_8; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] requests_io_push_bits_index_hi_9 = _requests_io_push_bits_index_T_29[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] requests_io_push_bits_index_lo_9 = _requests_io_push_bits_index_T_29[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_30 = |requests_io_push_bits_index_hi_9; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _requests_io_push_bits_index_T_31 = requests_io_push_bits_index_hi_9 | requests_io_push_bits_index_lo_9; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] requests_io_push_bits_index_hi_10 = _requests_io_push_bits_index_T_31[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] requests_io_push_bits_index_lo_10 = _requests_io_push_bits_index_T_31[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_32 = |requests_io_push_bits_index_hi_10; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _requests_io_push_bits_index_T_33 = requests_io_push_bits_index_hi_10 | requests_io_push_bits_index_lo_10; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] requests_io_push_bits_index_hi_11 = _requests_io_push_bits_index_T_33[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] requests_io_push_bits_index_lo_11 = _requests_io_push_bits_index_T_33[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_34 = |requests_io_push_bits_index_hi_11; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _requests_io_push_bits_index_T_35 = requests_io_push_bits_index_hi_11 | requests_io_push_bits_index_lo_11; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _requests_io_push_bits_index_T_36 = _requests_io_push_bits_index_T_35[1]; // @[OneHot.scala:32:28]
wire [1:0] _requests_io_push_bits_index_T_37 = {_requests_io_push_bits_index_T_34, _requests_io_push_bits_index_T_36}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _requests_io_push_bits_index_T_38 = {_requests_io_push_bits_index_T_32, _requests_io_push_bits_index_T_37}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_39 = {_requests_io_push_bits_index_T_30, _requests_io_push_bits_index_T_38}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _requests_io_push_bits_index_T_40 = {_requests_io_push_bits_index_T_28, _requests_io_push_bits_index_T_39}; // @[OneHot.scala:32:{10,14}]
wire [5:0] _requests_io_push_bits_index_T_41 = {_requests_io_push_bits_index_T_26, _requests_io_push_bits_index_T_40}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_42 = request_bits_prio_0 ? _requests_io_push_bits_index_T_10 : 4'h0; // @[OneHot.scala:32:10]
wire [5:0] _requests_io_push_bits_index_T_44 = request_bits_prio_2 ? _requests_io_push_bits_index_T_41 : 6'h0; // @[OneHot.scala:32:10]
wire [4:0] _requests_io_push_bits_index_T_45 = {1'h0, _requests_io_push_bits_index_T_42}; // @[Mux.scala:30:73]
wire [5:0] _requests_io_push_bits_index_T_46 = {1'h0, _requests_io_push_bits_index_T_45} | _requests_io_push_bits_index_T_44; // @[Mux.scala:30:73]
wire [5:0] _requests_io_push_bits_index_WIRE = _requests_io_push_bits_index_T_46; // @[Mux.scala:30:73]
wire [11:0] _mshr_insertOH_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:32]
wire [12:0] _mshr_insertOH_T_1 = {_mshr_insertOH_T, 1'h0}; // @[package.scala:253:48]
wire [11:0] _mshr_insertOH_T_2 = _mshr_insertOH_T_1[11:0]; // @[package.scala:253:{48,53}]
wire [11:0] _mshr_insertOH_T_3 = _mshr_insertOH_T | _mshr_insertOH_T_2; // @[package.scala:253:{43,53}]
wire [13:0] _mshr_insertOH_T_4 = {_mshr_insertOH_T_3, 2'h0}; // @[package.scala:253:{43,48}]
wire [11:0] _mshr_insertOH_T_5 = _mshr_insertOH_T_4[11:0]; // @[package.scala:253:{48,53}]
wire [11:0] _mshr_insertOH_T_6 = _mshr_insertOH_T_3 | _mshr_insertOH_T_5; // @[package.scala:253:{43,53}]
wire [15:0] _mshr_insertOH_T_7 = {_mshr_insertOH_T_6, 4'h0}; // @[package.scala:253:{43,48}]
wire [11:0] _mshr_insertOH_T_8 = _mshr_insertOH_T_7[11:0]; // @[package.scala:253:{48,53}]
wire [11:0] _mshr_insertOH_T_9 = _mshr_insertOH_T_6 | _mshr_insertOH_T_8; // @[package.scala:253:{43,53}]
wire [19:0] _mshr_insertOH_T_10 = {_mshr_insertOH_T_9, 8'h0}; // @[package.scala:253:{43,48}]
wire [11:0] _mshr_insertOH_T_11 = _mshr_insertOH_T_10[11:0]; // @[package.scala:253:{48,53}]
wire [11:0] _mshr_insertOH_T_12 = _mshr_insertOH_T_9 | _mshr_insertOH_T_11; // @[package.scala:253:{43,53}]
wire [11:0] _mshr_insertOH_T_13 = _mshr_insertOH_T_12; // @[package.scala:253:43, :254:17]
wire [12:0] _mshr_insertOH_T_14 = {_mshr_insertOH_T_13, 1'h0}; // @[package.scala:254:17]
wire [12:0] _mshr_insertOH_T_15 = ~_mshr_insertOH_T_14; // @[Scheduler.scala:278:{23,47}]
wire [11:0] _mshr_insertOH_T_16 = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:55]
wire [12:0] _mshr_insertOH_T_17 = {1'h0, _mshr_insertOH_T_15[11:0] & _mshr_insertOH_T_16}; // @[Scheduler.scala:278:{23,53,55}]
wire [12:0] mshr_insertOH = {1'h0, _mshr_insertOH_T_17[11:0] & prioFilter}; // @[Scheduler.scala:182:23, :278:{53,69}]
wire _T_76 = request_valid & alloc; // @[Scheduler.scala:163:21, :173:15, :280:25]
wire _T_35 = _T_76 & mshr_insertOH[0] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_0_io_allocate_bits_tag = _T_35 ? request_bits_tag : _view__T_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_39 = _T_76 & mshr_insertOH[1] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_1_io_allocate_bits_tag = _T_39 ? request_bits_tag : _view__T_1_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_43 = _T_76 & mshr_insertOH[2] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_2_io_allocate_bits_tag = _T_43 ? request_bits_tag : _view__T_2_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_47 = _T_76 & mshr_insertOH[3] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_3_io_allocate_bits_tag = _T_47 ? request_bits_tag : _view__T_3_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_51 = _T_76 & mshr_insertOH[4] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_4_io_allocate_bits_tag = _T_51 ? request_bits_tag : _view__T_4_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_55 = _T_76 & mshr_insertOH[5] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_5_io_allocate_bits_tag = _T_55 ? request_bits_tag : _view__T_5_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_59 = _T_76 & mshr_insertOH[6] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_6_io_allocate_bits_tag = _T_59 ? request_bits_tag : _view__T_6_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_63 = _T_76 & mshr_insertOH[7] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_7_io_allocate_bits_tag = _T_63 ? request_bits_tag : _view__T_7_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_67 = _T_76 & mshr_insertOH[8] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_8_io_allocate_bits_tag = _T_67 ? request_bits_tag : _view__T_8_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_71 = _T_76 & mshr_insertOH[9] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_9_io_allocate_bits_tag = _T_71 ? request_bits_tag : _view__T_9_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_75 = _T_76 & mshr_insertOH[10] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_10_io_allocate_bits_tag = _T_75 ? request_bits_tag : _view__T_10_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70, :287:131, :289:74]
wire _T_95 = request_valid & nestC & ~_mshrs_11_io_status_valid & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:71:46, :163:21, :180:70, :193:33, :247:75, :258:16, :259:87, :295:{32,59}]
wire _GEN_3 = _T_95 | _T_76 & mshr_insertOH[11] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:193:33, :236:25, :247:75, :258:16, :278:69, :279:18, :280:{25,34,39,83}, :281:27, :295:{32,59,103}, :296:30]
assign mshrs_11_io_allocate_bits_tag = _GEN_3 ? request_bits_tag : _view__T_11_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :236:25, :280:83, :281:27, :282:70, :295:103, :296:30, :297:73]
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Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLMonitor_42( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52]
wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79]
wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77]
wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35]
wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34]
wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34]
wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34]
wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [27:0] _is_aligned_T = {25'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [1039:0] a_set; // @[Monitor.scala:626:34]
wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1039:0] d_clr; // @[Monitor.scala:664:34]
wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [1039:0] d_clr_1; // @[Monitor.scala:774:34]
wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113]
wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util._
import FUConstants._
/**
* IO bundle to interact with Issue slot
*
* @param numWakeupPorts number of wakeup ports for the slot
*/
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val request_hp = Output(Bool())
val grant = Input(Bool())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted.
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz))))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W))))
val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue.
val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued.
val debug = {
val result = new Bundle {
val p1 = Bool()
val p2 = Bool()
val p3 = Bool()
val ppred = Bool()
val state = UInt(width=2.W)
}
Output(result)
}
}
/**
* Single issue slot. Holds a uop within the issue queue
*
* @param numWakeupPorts number of wakeup ports
*/
class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters)
extends BoomModule
with IssueUnitConstants
{
val io = IO(new IssueSlotIO(numWakeupPorts))
// slot invalid?
// slot is valid, holding 1 uop
// slot is valid, holds 2 uops (like a store)
def is_invalid = state === s_invalid
def is_valid = state =/= s_invalid
val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot)
val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot)
val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val state = RegInit(s_invalid)
val p1 = RegInit(false.B)
val p2 = RegInit(false.B)
val p3 = RegInit(false.B)
val ppred = RegInit(false.B)
// Poison if woken up by speculative load.
// Poison lasts 1 cycle (as ldMiss will come on the next cycle).
// SO if poisoned is true, set it to false!
val p1_poisoned = RegInit(false.B)
val p2_poisoned = RegInit(false.B)
p1_poisoned := false.B
p2_poisoned := false.B
val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
val slot_uop = RegInit(NullMicroOp)
val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
//-----------------------------------------------------------------------------
// next slot state computation
// compute the next state for THIS entry slot (in a collasping queue, the
// current uop may get moved elsewhere, and a new uop can enter
when (io.kill) {
state := s_invalid
} .elsewhen (io.in_uop.valid) {
state := io.in_uop.bits.iw_state
} .elsewhen (io.clear) {
state := s_invalid
} .otherwise {
state := next_state
}
//-----------------------------------------------------------------------------
// "update" state
// compute the next state for the micro-op in this slot. This micro-op may
// be moved elsewhere, so the "next_state" travels with it.
// defaults
next_state := state
next_uopc := slot_uop.uopc
next_lrs1_rtype := slot_uop.lrs1_rtype
next_lrs2_rtype := slot_uop.lrs2_rtype
when (io.kill) {
next_state := s_invalid
} .elsewhen ((io.grant && (state === s_valid_1)) ||
(io.grant && (state === s_valid_2) && p1 && p2 && ppred)) {
// try to issue this uop.
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_invalid
}
} .elsewhen (io.grant && (state === s_valid_2)) {
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_valid_1
when (p1) {
slot_uop.uopc := uopSTD
next_uopc := uopSTD
slot_uop.lrs1_rtype := RT_X
next_lrs1_rtype := RT_X
} .otherwise {
slot_uop.lrs2_rtype := RT_X
next_lrs2_rtype := RT_X
}
}
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.")
}
// Wakeup Compare Logic
// these signals are the "next_p*" for the current slot's micro-op.
// they are important for shifting the current slot_uop up to an other entry.
val next_p1 = WireInit(p1)
val next_p2 = WireInit(p2)
val next_p3 = WireInit(p3)
val next_ppred = WireInit(ppred)
when (io.in_uop.valid) {
p1 := !(io.in_uop.bits.prs1_busy)
p2 := !(io.in_uop.bits.prs2_busy)
p3 := !(io.in_uop.bits.prs3_busy)
ppred := !(io.in_uop.bits.ppred_busy)
}
when (io.ldspec_miss && next_p1_poisoned) {
assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!")
p1 := false.B
}
when (io.ldspec_miss && next_p2_poisoned) {
assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!")
p2 := false.B
}
for (i <- 0 until numWakeupPorts) {
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs1)) {
p1 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs2)) {
p2 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs3)) {
p3 := true.B
}
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) {
ppred := true.B
}
for (w <- 0 until memWidth) {
assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),
"Loads to x0 should never speculatively wakeup other instructions")
}
// TODO disable if FP IQ.
for (w <- 0 until memWidth) {
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs1 &&
next_uop.lrs1_rtype === RT_FIX) {
p1 := true.B
p1_poisoned := true.B
assert (!next_p1_poisoned)
}
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs2 &&
next_uop.lrs2_rtype === RT_FIX) {
p2 := true.B
p2_poisoned := true.B
assert (!next_p2_poisoned)
}
}
// Handle branch misspeculations
val next_br_mask = GetNewBrMask(io.brupdate, slot_uop)
// was this micro-op killed by a branch? if yes, we can't let it be valid if
// we compact it into an other entry
when (IsKilledByBranch(io.brupdate, slot_uop)) {
next_state := s_invalid
}
when (!io.in_uop.valid) {
slot_uop.br_mask := next_br_mask
}
//-------------------------------------------------------------
// Request Logic
io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill
val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr
io.request_hp := io.request && high_priority
when (state === s_valid_1) {
io.request := p1 && p2 && p3 && ppred && !io.kill
} .elsewhen (state === s_valid_2) {
io.request := (p1 || p2) && ppred && !io.kill
} .otherwise {
io.request := false.B
}
//assign outputs
io.valid := is_valid
io.uop := slot_uop
io.uop.iw_p1_poisoned := p1_poisoned
io.uop.iw_p2_poisoned := p2_poisoned
// micro-op will vacate due to grant.
val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred)
val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned)
io.will_be_valid := is_valid && !(may_vacate && !squash_grant)
io.out_uop := slot_uop
io.out_uop.iw_state := next_state
io.out_uop.uopc := next_uopc
io.out_uop.lrs1_rtype := next_lrs1_rtype
io.out_uop.lrs2_rtype := next_lrs2_rtype
io.out_uop.br_mask := next_br_mask
io.out_uop.prs1_busy := !p1
io.out_uop.prs2_busy := !p2
io.out_uop.prs3_busy := !p3
io.out_uop.ppred_busy := !ppred
io.out_uop.iw_p1_poisoned := p1_poisoned
io.out_uop.iw_p2_poisoned := p2_poisoned
when (state === s_valid_2) {
when (p1 && p2 && ppred) {
; // send out the entire instruction as one uop
} .elsewhen (p1 && ppred) {
io.uop.uopc := slot_uop.uopc
io.uop.lrs2_rtype := RT_X
} .elsewhen (p2 && ppred) {
io.uop.uopc := uopSTD
io.uop.lrs1_rtype := RT_X
}
}
// debug outputs
io.debug.p1 := p1
io.debug.p2 := p2
io.debug.p3 := p3
io.debug.ppred := ppred
io.debug.state := state
}
|
module IssueSlot_4( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29]
wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53]
wire squash_grant = 1'h0; // @[issue-slot.scala:261:37]
wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [5:0] io_spec_ld_wakeup_0_bits = 6'h0; // @[issue-slot.scala:69:7]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [7:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23]
assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17]
assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
|
Generate the Verilog code corresponding to the following Chisel files.
File Scheduler.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy.AddressSet
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import chisel3.experimental.dataview._
class InclusiveCacheBankScheduler(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val in = Flipped(TLBundle(params.inner.bundle))
val out = TLBundle(params.outer.bundle)
// Way permissions
val ways = Flipped(Vec(params.allClients, UInt(params.cache.ways.W)))
val divs = Flipped(Vec(params.allClients, UInt((InclusiveCacheParameters.lfsrBits + 1).W)))
// Control port
val req = Flipped(Decoupled(new SinkXRequest(params)))
val resp = Decoupled(new SourceXRequest(params))
})
val sourceA = Module(new SourceA(params))
val sourceB = Module(new SourceB(params))
val sourceC = Module(new SourceC(params))
val sourceD = Module(new SourceD(params))
val sourceE = Module(new SourceE(params))
val sourceX = Module(new SourceX(params))
io.out.a <> sourceA.io.a
io.out.c <> sourceC.io.c
io.out.e <> sourceE.io.e
io.in.b <> sourceB.io.b
io.in.d <> sourceD.io.d
io.resp <> sourceX.io.x
val sinkA = Module(new SinkA(params))
val sinkC = Module(new SinkC(params))
val sinkD = Module(new SinkD(params))
val sinkE = Module(new SinkE(params))
val sinkX = Module(new SinkX(params))
sinkA.io.a <> io.in.a
sinkC.io.c <> io.in.c
sinkE.io.e <> io.in.e
sinkD.io.d <> io.out.d
sinkX.io.x <> io.req
io.out.b.ready := true.B // disconnected
val directory = Module(new Directory(params))
val bankedStore = Module(new BankedStore(params))
val requests = Module(new ListBuffer(ListBufferParameters(new QueuedRequest(params), 3*params.mshrs, params.secondary, false)))
val mshrs = Seq.fill(params.mshrs) { Module(new MSHR(params)) }
val abc_mshrs = mshrs.init.init
val bc_mshr = mshrs.init.last
val c_mshr = mshrs.last
val nestedwb = Wire(new NestedWriteback(params))
// Deliver messages from Sinks to MSHRs
mshrs.zipWithIndex.foreach { case (m, i) =>
m.io.sinkc.valid := sinkC.io.resp.valid && sinkC.io.resp.bits.set === m.io.status.bits.set
m.io.sinkd.valid := sinkD.io.resp.valid && sinkD.io.resp.bits.source === i.U
m.io.sinke.valid := sinkE.io.resp.valid && sinkE.io.resp.bits.sink === i.U
m.io.sinkc.bits := sinkC.io.resp.bits
m.io.sinkd.bits := sinkD.io.resp.bits
m.io.sinke.bits := sinkE.io.resp.bits
m.io.nestedwb := nestedwb
}
// If the pre-emption BC or C MSHR have a matching set, the normal MSHR must be blocked
val mshr_stall_abc = abc_mshrs.map { m =>
(bc_mshr.io.status.valid && m.io.status.bits.set === bc_mshr.io.status.bits.set) ||
( c_mshr.io.status.valid && m.io.status.bits.set === c_mshr.io.status.bits.set)
}
val mshr_stall_bc =
c_mshr.io.status.valid && bc_mshr.io.status.bits.set === c_mshr.io.status.bits.set
val mshr_stall_c = false.B
val mshr_stall = mshr_stall_abc :+ mshr_stall_bc :+ mshr_stall_c
val stall_abc = (mshr_stall_abc zip abc_mshrs) map { case (s, m) => s && m.io.status.valid }
if (!params.lastLevel || !params.firstLevel)
params.ccover(stall_abc.reduce(_||_), "SCHEDULER_ABC_INTERLOCK", "ABC MSHR interlocked due to pre-emption")
if (!params.lastLevel)
params.ccover(mshr_stall_bc && bc_mshr.io.status.valid, "SCHEDULER_BC_INTERLOCK", "BC MSHR interlocked due to pre-emption")
// Consider scheduling an MSHR only if all the resources it requires are available
val mshr_request = Cat((mshrs zip mshr_stall).map { case (m, s) =>
m.io.schedule.valid && !s &&
(sourceA.io.req.ready || !m.io.schedule.bits.a.valid) &&
(sourceB.io.req.ready || !m.io.schedule.bits.b.valid) &&
(sourceC.io.req.ready || !m.io.schedule.bits.c.valid) &&
(sourceD.io.req.ready || !m.io.schedule.bits.d.valid) &&
(sourceE.io.req.ready || !m.io.schedule.bits.e.valid) &&
(sourceX.io.req.ready || !m.io.schedule.bits.x.valid) &&
(directory.io.write.ready || !m.io.schedule.bits.dir.valid)
}.reverse)
// Round-robin arbitration of MSHRs
val robin_filter = RegInit(0.U(params.mshrs.W))
val robin_request = Cat(mshr_request, mshr_request & robin_filter)
val mshr_selectOH2 = ~(leftOR(robin_request) << 1) & robin_request
val mshr_selectOH = mshr_selectOH2(2*params.mshrs-1, params.mshrs) | mshr_selectOH2(params.mshrs-1, 0)
val mshr_select = OHToUInt(mshr_selectOH)
val schedule = Mux1H(mshr_selectOH, mshrs.map(_.io.schedule.bits))
val scheduleTag = Mux1H(mshr_selectOH, mshrs.map(_.io.status.bits.tag))
val scheduleSet = Mux1H(mshr_selectOH, mshrs.map(_.io.status.bits.set))
// When an MSHR wins the schedule, it has lowest priority next time
when (mshr_request.orR) { robin_filter := ~rightOR(mshr_selectOH) }
// Fill in which MSHR sends the request
schedule.a.bits.source := mshr_select
schedule.c.bits.source := Mux(schedule.c.bits.opcode(1), mshr_select, 0.U) // only set for Release[Data] not ProbeAck[Data]
schedule.d.bits.sink := mshr_select
sourceA.io.req.valid := schedule.a.valid
sourceB.io.req.valid := schedule.b.valid
sourceC.io.req.valid := schedule.c.valid
sourceD.io.req.valid := schedule.d.valid
sourceE.io.req.valid := schedule.e.valid
sourceX.io.req.valid := schedule.x.valid
sourceA.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.a.bits)) := schedule.a.bits
sourceB.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.b.bits)) := schedule.b.bits
sourceC.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.c.bits)) := schedule.c.bits
sourceD.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.d.bits)) := schedule.d.bits
sourceE.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.e.bits)) := schedule.e.bits
sourceX.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.x.bits)) := schedule.x.bits
directory.io.write.valid := schedule.dir.valid
directory.io.write.bits.viewAsSupertype(chiselTypeOf(schedule.dir.bits)) := schedule.dir.bits
// Forward meta-data changes from nested transaction completion
val select_c = mshr_selectOH(params.mshrs-1)
val select_bc = mshr_selectOH(params.mshrs-2)
nestedwb.set := Mux(select_c, c_mshr.io.status.bits.set, bc_mshr.io.status.bits.set)
nestedwb.tag := Mux(select_c, c_mshr.io.status.bits.tag, bc_mshr.io.status.bits.tag)
nestedwb.b_toN := select_bc && bc_mshr.io.schedule.bits.dir.valid && bc_mshr.io.schedule.bits.dir.bits.data.state === MetaData.INVALID
nestedwb.b_toB := select_bc && bc_mshr.io.schedule.bits.dir.valid && bc_mshr.io.schedule.bits.dir.bits.data.state === MetaData.BRANCH
nestedwb.b_clr_dirty := select_bc && bc_mshr.io.schedule.bits.dir.valid
nestedwb.c_set_dirty := select_c && c_mshr.io.schedule.bits.dir.valid && c_mshr.io.schedule.bits.dir.bits.data.dirty
// Pick highest priority request
val request = Wire(Decoupled(new FullRequest(params)))
request.valid := directory.io.ready && (sinkA.io.req.valid || sinkX.io.req.valid || sinkC.io.req.valid)
request.bits := Mux(sinkC.io.req.valid, sinkC.io.req.bits,
Mux(sinkX.io.req.valid, sinkX.io.req.bits, sinkA.io.req.bits))
sinkC.io.req.ready := directory.io.ready && request.ready
sinkX.io.req.ready := directory.io.ready && request.ready && !sinkC.io.req.valid
sinkA.io.req.ready := directory.io.ready && request.ready && !sinkC.io.req.valid && !sinkX.io.req.valid
// If no MSHR has been assigned to this set, we need to allocate one
val setMatches = Cat(mshrs.map { m => m.io.status.valid && m.io.status.bits.set === request.bits.set }.reverse)
val alloc = !setMatches.orR // NOTE: no matches also means no BC or C pre-emption on this set
// If a same-set MSHR says that requests of this type must be blocked (for bounded time), do it
val blockB = Mux1H(setMatches, mshrs.map(_.io.status.bits.blockB)) && request.bits.prio(1)
val blockC = Mux1H(setMatches, mshrs.map(_.io.status.bits.blockC)) && request.bits.prio(2)
// If a same-set MSHR says that requests of this type must be handled out-of-band, use special BC|C MSHR
// ... these special MSHRs interlock the MSHR that said it should be pre-empted.
val nestB = Mux1H(setMatches, mshrs.map(_.io.status.bits.nestB)) && request.bits.prio(1)
val nestC = Mux1H(setMatches, mshrs.map(_.io.status.bits.nestC)) && request.bits.prio(2)
// Prevent priority inversion; we may not queue to MSHRs beyond our level
val prioFilter = Cat(request.bits.prio(2), !request.bits.prio(0), ~0.U((params.mshrs-2).W))
val lowerMatches = setMatches & prioFilter
// If we match an MSHR <= our priority that neither blocks nor nests us, queue to it.
val queue = lowerMatches.orR && !nestB && !nestC && !blockB && !blockC
if (!params.lastLevel) {
params.ccover(request.valid && blockB, "SCHEDULER_BLOCKB", "Interlock B request while resolving set conflict")
params.ccover(request.valid && nestB, "SCHEDULER_NESTB", "Priority escalation from channel B")
}
if (!params.firstLevel) {
params.ccover(request.valid && blockC, "SCHEDULER_BLOCKC", "Interlock C request while resolving set conflict")
params.ccover(request.valid && nestC, "SCHEDULER_NESTC", "Priority escalation from channel C")
}
params.ccover(request.valid && queue, "SCHEDULER_SECONDARY", "Enqueue secondary miss")
// It might happen that lowerMatches has >1 bit if the two special MSHRs are in-use
// We want to Q to the highest matching priority MSHR.
val lowerMatches1 =
Mux(lowerMatches(params.mshrs-1), 1.U << (params.mshrs-1),
Mux(lowerMatches(params.mshrs-2), 1.U << (params.mshrs-2),
lowerMatches))
// If this goes to the scheduled MSHR, it may need to be bypassed
// Alternatively, the MSHR may be refilled from a request queued in the ListBuffer
val selected_requests = Cat(mshr_selectOH, mshr_selectOH, mshr_selectOH) & requests.io.valid
val a_pop = selected_requests((0 + 1) * params.mshrs - 1, 0 * params.mshrs).orR
val b_pop = selected_requests((1 + 1) * params.mshrs - 1, 1 * params.mshrs).orR
val c_pop = selected_requests((2 + 1) * params.mshrs - 1, 2 * params.mshrs).orR
val bypassMatches = (mshr_selectOH & lowerMatches1).orR &&
Mux(c_pop || request.bits.prio(2), !c_pop, Mux(b_pop || request.bits.prio(1), !b_pop, !a_pop))
val may_pop = a_pop || b_pop || c_pop
val bypass = request.valid && queue && bypassMatches
val will_reload = schedule.reload && (may_pop || bypass)
val will_pop = schedule.reload && may_pop && !bypass
params.ccover(mshr_selectOH.orR && bypass, "SCHEDULER_BYPASS", "Bypass new request directly to conflicting MSHR")
params.ccover(mshr_selectOH.orR && will_reload, "SCHEDULER_RELOAD", "Back-to-back service of two requests")
params.ccover(mshr_selectOH.orR && will_pop, "SCHEDULER_POP", "Service of a secondary miss")
// Repeat the above logic, but without the fan-in
mshrs.zipWithIndex.foreach { case (m, i) =>
val sel = mshr_selectOH(i)
m.io.schedule.ready := sel
val a_pop = requests.io.valid(params.mshrs * 0 + i)
val b_pop = requests.io.valid(params.mshrs * 1 + i)
val c_pop = requests.io.valid(params.mshrs * 2 + i)
val bypassMatches = lowerMatches1(i) &&
Mux(c_pop || request.bits.prio(2), !c_pop, Mux(b_pop || request.bits.prio(1), !b_pop, !a_pop))
val may_pop = a_pop || b_pop || c_pop
val bypass = request.valid && queue && bypassMatches
val will_reload = m.io.schedule.bits.reload && (may_pop || bypass)
m.io.allocate.bits.viewAsSupertype(chiselTypeOf(requests.io.data)) := Mux(bypass, WireInit(new QueuedRequest(params), init = request.bits), requests.io.data)
m.io.allocate.bits.set := m.io.status.bits.set
m.io.allocate.bits.repeat := m.io.allocate.bits.tag === m.io.status.bits.tag
m.io.allocate.valid := sel && will_reload
}
// Determine which of the queued requests to pop (supposing will_pop)
val prio_requests = ~(~requests.io.valid | (requests.io.valid >> params.mshrs) | (requests.io.valid >> 2*params.mshrs))
val pop_index = OHToUInt(Cat(mshr_selectOH, mshr_selectOH, mshr_selectOH) & prio_requests)
requests.io.pop.valid := will_pop
requests.io.pop.bits := pop_index
// Reload from the Directory if the next MSHR operation changes tags
val lb_tag_mismatch = scheduleTag =/= requests.io.data.tag
val mshr_uses_directory_assuming_no_bypass = schedule.reload && may_pop && lb_tag_mismatch
val mshr_uses_directory_for_lb = will_pop && lb_tag_mismatch
val mshr_uses_directory = will_reload && scheduleTag =/= Mux(bypass, request.bits.tag, requests.io.data.tag)
// Is there an MSHR free for this request?
val mshr_validOH = Cat(mshrs.map(_.io.status.valid).reverse)
val mshr_free = (~mshr_validOH & prioFilter).orR
// Fanout the request to the appropriate handler (if any)
val bypassQueue = schedule.reload && bypassMatches
val request_alloc_cases =
(alloc && !mshr_uses_directory_assuming_no_bypass && mshr_free) ||
(nestB && !mshr_uses_directory_assuming_no_bypass && !bc_mshr.io.status.valid && !c_mshr.io.status.valid) ||
(nestC && !mshr_uses_directory_assuming_no_bypass && !c_mshr.io.status.valid)
request.ready := request_alloc_cases || (queue && (bypassQueue || requests.io.push.ready))
val alloc_uses_directory = request.valid && request_alloc_cases
// When a request goes through, it will need to hit the Directory
directory.io.read.valid := mshr_uses_directory || alloc_uses_directory
directory.io.read.bits.set := Mux(mshr_uses_directory_for_lb, scheduleSet, request.bits.set)
directory.io.read.bits.tag := Mux(mshr_uses_directory_for_lb, requests.io.data.tag, request.bits.tag)
// Enqueue the request if not bypassed directly into an MSHR
requests.io.push.valid := request.valid && queue && !bypassQueue
requests.io.push.bits.data := request.bits
requests.io.push.bits.index := Mux1H(
request.bits.prio, Seq(
OHToUInt(lowerMatches1 << params.mshrs*0),
OHToUInt(lowerMatches1 << params.mshrs*1),
OHToUInt(lowerMatches1 << params.mshrs*2)))
val mshr_insertOH = ~(leftOR(~mshr_validOH) << 1) & ~mshr_validOH & prioFilter
(mshr_insertOH.asBools zip mshrs) map { case (s, m) =>
when (request.valid && alloc && s && !mshr_uses_directory_assuming_no_bypass) {
m.io.allocate.valid := true.B
m.io.allocate.bits.viewAsSupertype(chiselTypeOf(request.bits)) := request.bits
m.io.allocate.bits.repeat := false.B
}
}
when (request.valid && nestB && !bc_mshr.io.status.valid && !c_mshr.io.status.valid && !mshr_uses_directory_assuming_no_bypass) {
bc_mshr.io.allocate.valid := true.B
bc_mshr.io.allocate.bits.viewAsSupertype(chiselTypeOf(request.bits)) := request.bits
bc_mshr.io.allocate.bits.repeat := false.B
assert (!request.bits.prio(0))
}
bc_mshr.io.allocate.bits.prio(0) := false.B
when (request.valid && nestC && !c_mshr.io.status.valid && !mshr_uses_directory_assuming_no_bypass) {
c_mshr.io.allocate.valid := true.B
c_mshr.io.allocate.bits.viewAsSupertype(chiselTypeOf(request.bits)) := request.bits
c_mshr.io.allocate.bits.repeat := false.B
assert (!request.bits.prio(0))
assert (!request.bits.prio(1))
}
c_mshr.io.allocate.bits.prio(0) := false.B
c_mshr.io.allocate.bits.prio(1) := false.B
// Fanout the result of the Directory lookup
val dirTarget = Mux(alloc, mshr_insertOH, Mux(nestB,(BigInt(1) << (params.mshrs-2)).U,(BigInt(1) << (params.mshrs-1)).U))
val directoryFanout = params.dirReg(RegNext(Mux(mshr_uses_directory, mshr_selectOH, Mux(alloc_uses_directory, dirTarget, 0.U))))
mshrs.zipWithIndex.foreach { case (m, i) =>
m.io.directory.valid := directoryFanout(i)
m.io.directory.bits := directory.io.result.bits
}
// MSHR response meta-data fetch
sinkC.io.way :=
Mux(bc_mshr.io.status.valid && bc_mshr.io.status.bits.set === sinkC.io.set,
bc_mshr.io.status.bits.way,
Mux1H(abc_mshrs.map(m => m.io.status.valid && m.io.status.bits.set === sinkC.io.set),
abc_mshrs.map(_.io.status.bits.way)))
sinkD.io.way := VecInit(mshrs.map(_.io.status.bits.way))(sinkD.io.source)
sinkD.io.set := VecInit(mshrs.map(_.io.status.bits.set))(sinkD.io.source)
// Beat buffer connections between components
sinkA.io.pb_pop <> sourceD.io.pb_pop
sourceD.io.pb_beat := sinkA.io.pb_beat
sinkC.io.rel_pop <> sourceD.io.rel_pop
sourceD.io.rel_beat := sinkC.io.rel_beat
// BankedStore ports
bankedStore.io.sinkC_adr <> sinkC.io.bs_adr
bankedStore.io.sinkC_dat := sinkC.io.bs_dat
bankedStore.io.sinkD_adr <> sinkD.io.bs_adr
bankedStore.io.sinkD_dat := sinkD.io.bs_dat
bankedStore.io.sourceC_adr <> sourceC.io.bs_adr
bankedStore.io.sourceD_radr <> sourceD.io.bs_radr
bankedStore.io.sourceD_wadr <> sourceD.io.bs_wadr
bankedStore.io.sourceD_wdat := sourceD.io.bs_wdat
sourceC.io.bs_dat := bankedStore.io.sourceC_dat
sourceD.io.bs_rdat := bankedStore.io.sourceD_rdat
// SourceD data hazard interlock
sourceD.io.evict_req := sourceC.io.evict_req
sourceD.io.grant_req := sinkD .io.grant_req
sourceC.io.evict_safe := sourceD.io.evict_safe
sinkD .io.grant_safe := sourceD.io.grant_safe
private def afmt(x: AddressSet) = s"""{"base":${x.base},"mask":${x.mask}}"""
private def addresses = params.inner.manager.managers.flatMap(_.address).map(afmt _).mkString(",")
private def setBits = params.addressMapping.drop(params.offsetBits).take(params.setBits).mkString(",")
private def tagBits = params.addressMapping.drop(params.offsetBits + params.setBits).take(params.tagBits).mkString(",")
private def simple = s""""reset":"${reset.pathName}","tagBits":[${tagBits}],"setBits":[${setBits}],"blockBytes":${params.cache.blockBytes},"ways":${params.cache.ways}"""
def json: String = s"""{"addresses":[${addresses}],${simple},"directory":${directory.json},"subbanks":${bankedStore.json}}"""
}
|
module InclusiveCacheBankScheduler( // @[Scheduler.scala:27:7]
input clock, // @[Scheduler.scala:27:7]
input reset, // @[Scheduler.scala:27:7]
output io_in_a_ready, // @[Scheduler.scala:29:14]
input io_in_a_valid, // @[Scheduler.scala:29:14]
input [2:0] io_in_a_bits_opcode, // @[Scheduler.scala:29:14]
input [2:0] io_in_a_bits_param, // @[Scheduler.scala:29:14]
input [2:0] io_in_a_bits_size, // @[Scheduler.scala:29:14]
input [8:0] io_in_a_bits_source, // @[Scheduler.scala:29:14]
input [31:0] io_in_a_bits_address, // @[Scheduler.scala:29:14]
input [7:0] io_in_a_bits_mask, // @[Scheduler.scala:29:14]
input [63:0] io_in_a_bits_data, // @[Scheduler.scala:29:14]
input io_in_a_bits_corrupt, // @[Scheduler.scala:29:14]
input io_in_b_ready, // @[Scheduler.scala:29:14]
output io_in_b_valid, // @[Scheduler.scala:29:14]
output [1:0] io_in_b_bits_param, // @[Scheduler.scala:29:14]
output [31:0] io_in_b_bits_address, // @[Scheduler.scala:29:14]
output io_in_c_ready, // @[Scheduler.scala:29:14]
input io_in_c_valid, // @[Scheduler.scala:29:14]
input [2:0] io_in_c_bits_opcode, // @[Scheduler.scala:29:14]
input [2:0] io_in_c_bits_param, // @[Scheduler.scala:29:14]
input [2:0] io_in_c_bits_size, // @[Scheduler.scala:29:14]
input [8:0] io_in_c_bits_source, // @[Scheduler.scala:29:14]
input [31:0] io_in_c_bits_address, // @[Scheduler.scala:29:14]
input [63:0] io_in_c_bits_data, // @[Scheduler.scala:29:14]
input io_in_c_bits_corrupt, // @[Scheduler.scala:29:14]
input io_in_d_ready, // @[Scheduler.scala:29:14]
output io_in_d_valid, // @[Scheduler.scala:29:14]
output [2:0] io_in_d_bits_opcode, // @[Scheduler.scala:29:14]
output [1:0] io_in_d_bits_param, // @[Scheduler.scala:29:14]
output [2:0] io_in_d_bits_size, // @[Scheduler.scala:29:14]
output [8:0] io_in_d_bits_source, // @[Scheduler.scala:29:14]
output [2:0] io_in_d_bits_sink, // @[Scheduler.scala:29:14]
output io_in_d_bits_denied, // @[Scheduler.scala:29:14]
output [63:0] io_in_d_bits_data, // @[Scheduler.scala:29:14]
output io_in_d_bits_corrupt, // @[Scheduler.scala:29:14]
input io_in_e_valid, // @[Scheduler.scala:29:14]
input [2:0] io_in_e_bits_sink, // @[Scheduler.scala:29:14]
input io_out_a_ready, // @[Scheduler.scala:29:14]
output io_out_a_valid, // @[Scheduler.scala:29:14]
output [2:0] io_out_a_bits_opcode, // @[Scheduler.scala:29:14]
output [2:0] io_out_a_bits_param, // @[Scheduler.scala:29:14]
output [2:0] io_out_a_bits_size, // @[Scheduler.scala:29:14]
output [2:0] io_out_a_bits_source, // @[Scheduler.scala:29:14]
output [31:0] io_out_a_bits_address, // @[Scheduler.scala:29:14]
output [7:0] io_out_a_bits_mask, // @[Scheduler.scala:29:14]
output [63:0] io_out_a_bits_data, // @[Scheduler.scala:29:14]
output io_out_a_bits_corrupt, // @[Scheduler.scala:29:14]
input io_out_c_ready, // @[Scheduler.scala:29:14]
output io_out_c_valid, // @[Scheduler.scala:29:14]
output [2:0] io_out_c_bits_opcode, // @[Scheduler.scala:29:14]
output [2:0] io_out_c_bits_param, // @[Scheduler.scala:29:14]
output [2:0] io_out_c_bits_size, // @[Scheduler.scala:29:14]
output [2:0] io_out_c_bits_source, // @[Scheduler.scala:29:14]
output [31:0] io_out_c_bits_address, // @[Scheduler.scala:29:14]
output [63:0] io_out_c_bits_data, // @[Scheduler.scala:29:14]
output io_out_c_bits_corrupt, // @[Scheduler.scala:29:14]
output io_out_d_ready, // @[Scheduler.scala:29:14]
input io_out_d_valid, // @[Scheduler.scala:29:14]
input [2:0] io_out_d_bits_opcode, // @[Scheduler.scala:29:14]
input [1:0] io_out_d_bits_param, // @[Scheduler.scala:29:14]
input [2:0] io_out_d_bits_size, // @[Scheduler.scala:29:14]
input [2:0] io_out_d_bits_source, // @[Scheduler.scala:29:14]
input [2:0] io_out_d_bits_sink, // @[Scheduler.scala:29:14]
input io_out_d_bits_denied, // @[Scheduler.scala:29:14]
input [63:0] io_out_d_bits_data, // @[Scheduler.scala:29:14]
input io_out_d_bits_corrupt, // @[Scheduler.scala:29:14]
output io_out_e_valid, // @[Scheduler.scala:29:14]
output [2:0] io_out_e_bits_sink, // @[Scheduler.scala:29:14]
output io_req_ready, // @[Scheduler.scala:29:14]
input io_req_valid, // @[Scheduler.scala:29:14]
input [31:0] io_req_bits_address, // @[Scheduler.scala:29:14]
output io_resp_valid // @[Scheduler.scala:29:14]
);
wire [12:0] mshrs_6_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :295:103, :297:73]
wire [12:0] mshrs_5_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :287:131, :289:74]
wire [12:0] mshrs_4_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_3_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_2_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_1_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_0_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [5:0] request_bits_put; // @[Scheduler.scala:163:21]
wire [5:0] request_bits_offset; // @[Scheduler.scala:163:21]
wire [12:0] request_bits_tag; // @[Scheduler.scala:163:21]
wire [8:0] request_bits_source; // @[Scheduler.scala:163:21]
wire [2:0] request_bits_size; // @[Scheduler.scala:163:21]
wire [2:0] request_bits_param; // @[Scheduler.scala:163:21]
wire [2:0] request_bits_opcode; // @[Scheduler.scala:163:21]
wire request_bits_control; // @[Scheduler.scala:163:21]
wire request_bits_prio_2; // @[Scheduler.scala:163:21]
wire request_bits_prio_0; // @[Scheduler.scala:163:21]
wire _mshrs_6_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_6_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_6_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_6_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_6_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_6_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_6_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_6_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_6_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_6_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_6_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_6_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_6_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_6_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_6_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_5_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_5_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_5_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_5_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_5_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_5_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_5_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_5_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_5_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_5_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_5_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_5_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_5_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_5_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_4_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_4_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_4_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_4_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_4_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_4_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_4_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_4_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_4_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_4_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_4_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_4_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_4_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_4_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_4_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_3_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_3_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_3_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_3_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_3_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_3_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_3_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_3_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_3_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_3_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_3_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_3_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_3_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_3_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_3_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_2_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_2_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_2_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_2_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_2_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_2_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_2_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_2_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_2_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_2_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_2_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_2_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_2_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_2_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_2_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_1_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_1_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_1_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_1_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_1_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_1_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_1_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_1_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_1_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_1_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_1_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_1_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_1_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_1_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_1_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_0_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_0_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_0_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_0_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_0_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_0_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_0_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_0_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_0_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_0_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_0_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_0_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_0_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_0_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_0_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _requests_io_push_ready; // @[Scheduler.scala:70:24]
wire [20:0] _requests_io_valid; // @[Scheduler.scala:70:24]
wire _requests_io_data_prio_0; // @[Scheduler.scala:70:24]
wire _requests_io_data_prio_1; // @[Scheduler.scala:70:24]
wire _requests_io_data_prio_2; // @[Scheduler.scala:70:24]
wire _requests_io_data_control; // @[Scheduler.scala:70:24]
wire [2:0] _requests_io_data_opcode; // @[Scheduler.scala:70:24]
wire [2:0] _requests_io_data_param; // @[Scheduler.scala:70:24]
wire [2:0] _requests_io_data_size; // @[Scheduler.scala:70:24]
wire [8:0] _requests_io_data_source; // @[Scheduler.scala:70:24]
wire [12:0] _requests_io_data_tag; // @[Scheduler.scala:70:24]
wire [5:0] _requests_io_data_offset; // @[Scheduler.scala:70:24]
wire [5:0] _requests_io_data_put; // @[Scheduler.scala:70:24]
wire _bankedStore_io_sinkC_adr_ready; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sinkD_adr_ready; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sourceC_adr_ready; // @[Scheduler.scala:69:27]
wire [63:0] _bankedStore_io_sourceC_dat_data; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sourceD_radr_ready; // @[Scheduler.scala:69:27]
wire [63:0] _bankedStore_io_sourceD_rdat_data; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sourceD_wadr_ready; // @[Scheduler.scala:69:27]
wire _directory_io_write_ready; // @[Scheduler.scala:68:25]
wire _directory_io_result_bits_dirty; // @[Scheduler.scala:68:25]
wire [1:0] _directory_io_result_bits_state; // @[Scheduler.scala:68:25]
wire _directory_io_result_bits_clients; // @[Scheduler.scala:68:25]
wire [12:0] _directory_io_result_bits_tag; // @[Scheduler.scala:68:25]
wire _directory_io_result_bits_hit; // @[Scheduler.scala:68:25]
wire [2:0] _directory_io_result_bits_way; // @[Scheduler.scala:68:25]
wire _directory_io_ready; // @[Scheduler.scala:68:25]
wire _sinkX_io_req_valid; // @[Scheduler.scala:58:21]
wire [12:0] _sinkX_io_req_bits_tag; // @[Scheduler.scala:58:21]
wire [9:0] _sinkX_io_req_bits_set; // @[Scheduler.scala:58:21]
wire _sinkE_io_resp_valid; // @[Scheduler.scala:57:21]
wire [2:0] _sinkE_io_resp_bits_sink; // @[Scheduler.scala:57:21]
wire _sinkD_io_resp_valid; // @[Scheduler.scala:56:21]
wire _sinkD_io_resp_bits_last; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_resp_bits_opcode; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_resp_bits_param; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_resp_bits_source; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_resp_bits_sink; // @[Scheduler.scala:56:21]
wire _sinkD_io_resp_bits_denied; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_source; // @[Scheduler.scala:56:21]
wire _sinkD_io_bs_adr_valid; // @[Scheduler.scala:56:21]
wire _sinkD_io_bs_adr_bits_noop; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_bs_adr_bits_way; // @[Scheduler.scala:56:21]
wire [9:0] _sinkD_io_bs_adr_bits_set; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_bs_adr_bits_beat; // @[Scheduler.scala:56:21]
wire [63:0] _sinkD_io_bs_dat_data; // @[Scheduler.scala:56:21]
wire [9:0] _sinkD_io_grant_req_set; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_grant_req_way; // @[Scheduler.scala:56:21]
wire _sinkC_io_req_valid; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_req_bits_opcode; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_req_bits_param; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_req_bits_size; // @[Scheduler.scala:55:21]
wire [8:0] _sinkC_io_req_bits_source; // @[Scheduler.scala:55:21]
wire [12:0] _sinkC_io_req_bits_tag; // @[Scheduler.scala:55:21]
wire [5:0] _sinkC_io_req_bits_offset; // @[Scheduler.scala:55:21]
wire [5:0] _sinkC_io_req_bits_put; // @[Scheduler.scala:55:21]
wire [9:0] _sinkC_io_req_bits_set; // @[Scheduler.scala:55:21]
wire _sinkC_io_resp_valid; // @[Scheduler.scala:55:21]
wire _sinkC_io_resp_bits_last; // @[Scheduler.scala:55:21]
wire [9:0] _sinkC_io_resp_bits_set; // @[Scheduler.scala:55:21]
wire [12:0] _sinkC_io_resp_bits_tag; // @[Scheduler.scala:55:21]
wire [8:0] _sinkC_io_resp_bits_source; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_resp_bits_param; // @[Scheduler.scala:55:21]
wire _sinkC_io_resp_bits_data; // @[Scheduler.scala:55:21]
wire [9:0] _sinkC_io_set; // @[Scheduler.scala:55:21]
wire _sinkC_io_bs_adr_valid; // @[Scheduler.scala:55:21]
wire _sinkC_io_bs_adr_bits_noop; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_bs_adr_bits_way; // @[Scheduler.scala:55:21]
wire [9:0] _sinkC_io_bs_adr_bits_set; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_bs_adr_bits_beat; // @[Scheduler.scala:55:21]
wire _sinkC_io_bs_adr_bits_mask; // @[Scheduler.scala:55:21]
wire [63:0] _sinkC_io_bs_dat_data; // @[Scheduler.scala:55:21]
wire _sinkC_io_rel_pop_ready; // @[Scheduler.scala:55:21]
wire [63:0] _sinkC_io_rel_beat_data; // @[Scheduler.scala:55:21]
wire _sinkC_io_rel_beat_corrupt; // @[Scheduler.scala:55:21]
wire _sinkA_io_req_valid; // @[Scheduler.scala:54:21]
wire [2:0] _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21]
wire [2:0] _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21]
wire [2:0] _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21]
wire [8:0] _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21]
wire [12:0] _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21]
wire [5:0] _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21]
wire [5:0] _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21]
wire [9:0] _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21]
wire _sinkA_io_pb_pop_ready; // @[Scheduler.scala:54:21]
wire [63:0] _sinkA_io_pb_beat_data; // @[Scheduler.scala:54:21]
wire [7:0] _sinkA_io_pb_beat_mask; // @[Scheduler.scala:54:21]
wire _sinkA_io_pb_beat_corrupt; // @[Scheduler.scala:54:21]
wire _sourceX_io_req_ready; // @[Scheduler.scala:45:23]
wire _sourceE_io_req_ready; // @[Scheduler.scala:44:23]
wire _sourceD_io_req_ready; // @[Scheduler.scala:43:23]
wire _sourceD_io_pb_pop_valid; // @[Scheduler.scala:43:23]
wire [5:0] _sourceD_io_pb_pop_bits_index; // @[Scheduler.scala:43:23]
wire _sourceD_io_pb_pop_bits_last; // @[Scheduler.scala:43:23]
wire _sourceD_io_rel_pop_valid; // @[Scheduler.scala:43:23]
wire [5:0] _sourceD_io_rel_pop_bits_index; // @[Scheduler.scala:43:23]
wire _sourceD_io_rel_pop_bits_last; // @[Scheduler.scala:43:23]
wire _sourceD_io_bs_radr_valid; // @[Scheduler.scala:43:23]
wire [2:0] _sourceD_io_bs_radr_bits_way; // @[Scheduler.scala:43:23]
wire [9:0] _sourceD_io_bs_radr_bits_set; // @[Scheduler.scala:43:23]
wire [2:0] _sourceD_io_bs_radr_bits_beat; // @[Scheduler.scala:43:23]
wire _sourceD_io_bs_radr_bits_mask; // @[Scheduler.scala:43:23]
wire _sourceD_io_bs_wadr_valid; // @[Scheduler.scala:43:23]
wire [2:0] _sourceD_io_bs_wadr_bits_way; // @[Scheduler.scala:43:23]
wire [9:0] _sourceD_io_bs_wadr_bits_set; // @[Scheduler.scala:43:23]
wire [2:0] _sourceD_io_bs_wadr_bits_beat; // @[Scheduler.scala:43:23]
wire _sourceD_io_bs_wadr_bits_mask; // @[Scheduler.scala:43:23]
wire [63:0] _sourceD_io_bs_wdat_data; // @[Scheduler.scala:43:23]
wire _sourceD_io_evict_safe; // @[Scheduler.scala:43:23]
wire _sourceD_io_grant_safe; // @[Scheduler.scala:43:23]
wire _sourceC_io_req_ready; // @[Scheduler.scala:42:23]
wire _sourceC_io_bs_adr_valid; // @[Scheduler.scala:42:23]
wire [2:0] _sourceC_io_bs_adr_bits_way; // @[Scheduler.scala:42:23]
wire [9:0] _sourceC_io_bs_adr_bits_set; // @[Scheduler.scala:42:23]
wire [2:0] _sourceC_io_bs_adr_bits_beat; // @[Scheduler.scala:42:23]
wire [9:0] _sourceC_io_evict_req_set; // @[Scheduler.scala:42:23]
wire [2:0] _sourceC_io_evict_req_way; // @[Scheduler.scala:42:23]
wire _sourceB_io_req_ready; // @[Scheduler.scala:41:23]
wire _sourceA_io_req_ready; // @[Scheduler.scala:40:23]
wire io_in_a_valid_0 = io_in_a_valid; // @[Scheduler.scala:27:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Scheduler.scala:27:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Scheduler.scala:27:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Scheduler.scala:27:7]
wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Scheduler.scala:27:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Scheduler.scala:27:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Scheduler.scala:27:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Scheduler.scala:27:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Scheduler.scala:27:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Scheduler.scala:27:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Scheduler.scala:27:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Scheduler.scala:27:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Scheduler.scala:27:7]
wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Scheduler.scala:27:7]
wire [8:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Scheduler.scala:27:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Scheduler.scala:27:7]
wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Scheduler.scala:27:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Scheduler.scala:27:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Scheduler.scala:27:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Scheduler.scala:27:7]
wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Scheduler.scala:27:7]
wire io_out_a_ready_0 = io_out_a_ready; // @[Scheduler.scala:27:7]
wire io_out_c_ready_0 = io_out_c_ready; // @[Scheduler.scala:27:7]
wire io_out_d_valid_0 = io_out_d_valid; // @[Scheduler.scala:27:7]
wire [2:0] io_out_d_bits_opcode_0 = io_out_d_bits_opcode; // @[Scheduler.scala:27:7]
wire [1:0] io_out_d_bits_param_0 = io_out_d_bits_param; // @[Scheduler.scala:27:7]
wire [2:0] io_out_d_bits_size_0 = io_out_d_bits_size; // @[Scheduler.scala:27:7]
wire [2:0] io_out_d_bits_source_0 = io_out_d_bits_source; // @[Scheduler.scala:27:7]
wire [2:0] io_out_d_bits_sink_0 = io_out_d_bits_sink; // @[Scheduler.scala:27:7]
wire io_out_d_bits_denied_0 = io_out_d_bits_denied; // @[Scheduler.scala:27:7]
wire [63:0] io_out_d_bits_data_0 = io_out_d_bits_data; // @[Scheduler.scala:27:7]
wire io_out_d_bits_corrupt_0 = io_out_d_bits_corrupt; // @[Scheduler.scala:27:7]
wire io_req_valid_0 = io_req_valid; // @[Scheduler.scala:27:7]
wire [31:0] io_req_bits_address_0 = io_req_bits_address; // @[Scheduler.scala:27:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7]
wire io_out_b_valid = 1'h0; // @[Scheduler.scala:27:7]
wire io_out_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7]
wire io_resp_bits_fail = 1'h0; // @[Scheduler.scala:27:7]
wire schedule_x_bits_fail = 1'h0; // @[Mux.scala:30:73]
wire _schedule_WIRE_11_bits_fail = 1'h0; // @[Mux.scala:30:73]
wire _schedule_WIRE_12_fail = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_111 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_112 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_113 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_114 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_115 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_116 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_117 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_118 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_119 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_120 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_121 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_122 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_123 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_WIRE_13 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_324 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_325 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_338 = 1'h0; // @[Mux.scala:30:73]
wire request_bits_prio_1 = 1'h0; // @[Scheduler.scala:163:21]
wire _request_bits_T_prio_1 = 1'h0; // @[Scheduler.scala:166:22]
wire _request_bits_T_prio_2 = 1'h0; // @[Scheduler.scala:166:22]
wire _request_bits_T_1_prio_1 = 1'h0; // @[Scheduler.scala:165:22]
wire blockB = 1'h0; // @[Scheduler.scala:175:70]
wire nestB = 1'h0; // @[Scheduler.scala:179:70]
wire _view__WIRE_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_1_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_2_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_3_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_4_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_5_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_6_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _request_alloc_cases_T_4 = 1'h0; // @[Scheduler.scala:259:13]
wire _request_alloc_cases_T_6 = 1'h0; // @[Scheduler.scala:259:56]
wire _request_alloc_cases_T_8 = 1'h0; // @[Scheduler.scala:259:84]
wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Scheduler.scala:27:7]
wire [2:0] io_in_b_bits_size = 3'h6; // @[Scheduler.scala:27:7]
wire [8:0] io_in_b_bits_source = 9'h1E0; // @[Scheduler.scala:27:7]
wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Scheduler.scala:27:7]
wire [63:0] io_in_b_bits_data = 64'h0; // @[Scheduler.scala:27:7]
wire [63:0] io_out_b_bits_data = 64'h0; // @[Scheduler.scala:27:7]
wire io_in_e_ready = 1'h1; // @[Scheduler.scala:27:7]
wire io_out_b_ready = 1'h1; // @[Scheduler.scala:27:7]
wire io_out_e_ready = 1'h1; // @[Scheduler.scala:27:7]
wire io_resp_ready = 1'h1; // @[Scheduler.scala:27:7]
wire _mshr_request_T_138 = 1'h1; // @[Scheduler.scala:107:28]
wire _request_bits_T_prio_0 = 1'h1; // @[Scheduler.scala:166:22]
wire _queue_T_1 = 1'h1; // @[Scheduler.scala:185:35]
wire _queue_T_5 = 1'h1; // @[Scheduler.scala:185:55]
wire [2:0] io_out_b_bits_opcode = 3'h0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_b_bits_size = 3'h0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_b_bits_source = 3'h0; // @[Scheduler.scala:27:7]
wire [2:0] _schedule_WIRE_19_bits_sink = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_sink = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_189 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_190 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_191 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_192 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_193 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_194 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_195 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_196 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_197 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_198 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_199 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_200 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_201 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_23 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_38_bits_source = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_39_source = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_423 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_424 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_425 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_426 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_427 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_428 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_429 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_430 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_431 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_432 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_433 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_434 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_435 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_44 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_55_bits_source = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_56_source = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_553 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_554 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_555 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_556 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_557 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_558 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_559 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_560 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_561 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_562 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_563 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_564 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_565 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_58 = 3'h0; // @[Mux.scala:30:73]
wire [1:0] io_out_b_bits_param = 2'h0; // @[Scheduler.scala:27:7]
wire [31:0] io_out_b_bits_address = 32'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_out_b_bits_mask = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_0 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_1 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_2 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_3 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_4 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_5 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_6 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_7 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_8 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_9 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_10 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_11 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_12 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_13 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_14 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_15 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_16 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_17 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_18 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_19 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_20 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_21 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_22 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_23 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_24 = 8'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_0 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_1 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_2 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_3 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_4 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_5 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_6 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_7 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_8 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_9 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_10 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_11 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_12 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_13 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_14 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_15 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_16 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_17 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_18 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_19 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_20 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_21 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_22 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_23 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_24 = 11'h0; // @[Scheduler.scala:27:7]
wire [6:0] _lowerMatches1_T_1 = 7'h40; // @[Scheduler.scala:200:43]
wire [6:0] _dirTarget_T = 7'h40; // @[Scheduler.scala:306:48]
wire [3:0] _requests_io_push_bits_index_T_34 = 4'h0; // @[Mux.scala:30:73]
wire [4:0] _prioFilter_T_1 = 5'h1F; // @[Scheduler.scala:182:69]
wire [5:0] _lowerMatches1_T_3 = 6'h20; // @[Scheduler.scala:201:43]
wire io_in_a_ready_0; // @[Scheduler.scala:27:7]
wire [1:0] io_in_b_bits_param_0; // @[Scheduler.scala:27:7]
wire [31:0] io_in_b_bits_address_0; // @[Scheduler.scala:27:7]
wire io_in_b_valid_0; // @[Scheduler.scala:27:7]
wire io_in_c_ready_0; // @[Scheduler.scala:27:7]
wire [2:0] io_in_d_bits_opcode_0; // @[Scheduler.scala:27:7]
wire [1:0] io_in_d_bits_param_0; // @[Scheduler.scala:27:7]
wire [2:0] io_in_d_bits_size_0; // @[Scheduler.scala:27:7]
wire [8:0] io_in_d_bits_source_0; // @[Scheduler.scala:27:7]
wire [2:0] io_in_d_bits_sink_0; // @[Scheduler.scala:27:7]
wire io_in_d_bits_denied_0; // @[Scheduler.scala:27:7]
wire [63:0] io_in_d_bits_data_0; // @[Scheduler.scala:27:7]
wire io_in_d_bits_corrupt_0; // @[Scheduler.scala:27:7]
wire io_in_d_valid_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_a_bits_opcode_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_a_bits_param_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_a_bits_size_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_a_bits_source_0; // @[Scheduler.scala:27:7]
wire [31:0] io_out_a_bits_address_0; // @[Scheduler.scala:27:7]
wire [7:0] io_out_a_bits_mask_0; // @[Scheduler.scala:27:7]
wire [63:0] io_out_a_bits_data_0; // @[Scheduler.scala:27:7]
wire io_out_a_bits_corrupt_0; // @[Scheduler.scala:27:7]
wire io_out_a_valid_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_c_bits_opcode_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_c_bits_param_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_c_bits_size_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_c_bits_source_0; // @[Scheduler.scala:27:7]
wire [31:0] io_out_c_bits_address_0; // @[Scheduler.scala:27:7]
wire [63:0] io_out_c_bits_data_0; // @[Scheduler.scala:27:7]
wire io_out_c_bits_corrupt_0; // @[Scheduler.scala:27:7]
wire io_out_c_valid_0; // @[Scheduler.scala:27:7]
wire io_out_d_ready_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_e_bits_sink_0; // @[Scheduler.scala:27:7]
wire io_out_e_valid_0; // @[Scheduler.scala:27:7]
wire io_req_ready_0; // @[Scheduler.scala:27:7]
wire io_resp_valid_0; // @[Scheduler.scala:27:7]
wire [9:0] _nestedwb_set_T; // @[Scheduler.scala:155:24]
wire [12:0] _nestedwb_tag_T; // @[Scheduler.scala:156:24]
wire _nestedwb_b_toN_T_2; // @[Scheduler.scala:157:75]
wire _nestedwb_b_toB_T_2; // @[Scheduler.scala:158:75]
wire _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:159:37]
wire _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:160:75]
wire [9:0] nestedwb_set; // @[Scheduler.scala:75:22]
wire [12:0] nestedwb_tag; // @[Scheduler.scala:75:22]
wire nestedwb_b_toN; // @[Scheduler.scala:75:22]
wire nestedwb_b_toB; // @[Scheduler.scala:75:22]
wire nestedwb_b_clr_dirty; // @[Scheduler.scala:75:22]
wire nestedwb_c_set_dirty; // @[Scheduler.scala:75:22]
wire _mshrs_0_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_0_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_0_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_0_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_0_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h0; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_0_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_0_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_0_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h0; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_0_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_0_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_1_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_1_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_1_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_1_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_1_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h1; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_1_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_1_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_1_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h1; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_1_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_1_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_2_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_2_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_2_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_2_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_2_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h2; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_2_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_2_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_2_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h2; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_2_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_2_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_3_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_3_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_3_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_3_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_3_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h3; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_3_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_3_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_3_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h3; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_3_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_3_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_4_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_4_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_4_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_4_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_4_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h4; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_4_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_4_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_4_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h4; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_4_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_4_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_5_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_5_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_5_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_5_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h5; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_5_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_5_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_5_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h5; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_5_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_5_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_6_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_6_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_6_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_6_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 3'h6; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_6_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_6_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_6_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 3'h6; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_6_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_6_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshr_stall_abc_T = _mshrs_0_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_1 = _mshrs_5_io_status_valid & _mshr_stall_abc_T; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_2 = _mshrs_0_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_3 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_2; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_0 = _mshr_stall_abc_T_1 | _mshr_stall_abc_T_3; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_4 = _mshrs_1_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_5 = _mshrs_5_io_status_valid & _mshr_stall_abc_T_4; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_6 = _mshrs_1_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_7 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_6; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_1 = _mshr_stall_abc_T_5 | _mshr_stall_abc_T_7; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_8 = _mshrs_2_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_9 = _mshrs_5_io_status_valid & _mshr_stall_abc_T_8; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_10 = _mshrs_2_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_11 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_10; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_2 = _mshr_stall_abc_T_9 | _mshr_stall_abc_T_11; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_12 = _mshrs_3_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_13 = _mshrs_5_io_status_valid & _mshr_stall_abc_T_12; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_14 = _mshrs_3_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_15 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_14; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_3 = _mshr_stall_abc_T_13 | _mshr_stall_abc_T_15; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_16 = _mshrs_4_io_status_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_17 = _mshrs_5_io_status_valid & _mshr_stall_abc_T_16; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_18 = _mshrs_4_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_19 = _mshrs_6_io_status_valid & _mshr_stall_abc_T_18; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_4 = _mshr_stall_abc_T_17 | _mshr_stall_abc_T_19; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_bc_T = _mshrs_5_io_status_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46, :94:58]
wire mshr_stall_bc = _mshrs_6_io_status_valid & _mshr_stall_bc_T; // @[Scheduler.scala:71:46, :94:{28,58}]
wire stall_abc_0 = mshr_stall_abc_0 & _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_1 = mshr_stall_abc_1 & _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_2 = mshr_stall_abc_2 & _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_3 = mshr_stall_abc_3 & _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_4 = mshr_stall_abc_4 & _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire _mshr_request_T = ~mshr_stall_abc_0; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_1 = _mshrs_0_io_schedule_valid & _mshr_request_T; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_2 = ~_mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_3 = _sourceA_io_req_ready | _mshr_request_T_2; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_4 = _mshr_request_T_1 & _mshr_request_T_3; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_5 = ~_mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_6 = _sourceB_io_req_ready | _mshr_request_T_5; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_7 = _mshr_request_T_4 & _mshr_request_T_6; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_8 = ~_mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_9 = _sourceC_io_req_ready | _mshr_request_T_8; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_10 = _mshr_request_T_7 & _mshr_request_T_9; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_11 = ~_mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_12 = _sourceD_io_req_ready | _mshr_request_T_11; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_13 = _mshr_request_T_10 & _mshr_request_T_12; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_14 = ~_mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_15 = _sourceE_io_req_ready | _mshr_request_T_14; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_16 = _mshr_request_T_13 & _mshr_request_T_15; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_17 = ~_mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_18 = _sourceX_io_req_ready | _mshr_request_T_17; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_19 = _mshr_request_T_16 & _mshr_request_T_18; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_20 = ~_mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_21 = _directory_io_write_ready | _mshr_request_T_20; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_22 = _mshr_request_T_19 & _mshr_request_T_21; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_23 = ~mshr_stall_abc_1; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_24 = _mshrs_1_io_schedule_valid & _mshr_request_T_23; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_25 = ~_mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_26 = _sourceA_io_req_ready | _mshr_request_T_25; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_27 = _mshr_request_T_24 & _mshr_request_T_26; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_28 = ~_mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_29 = _sourceB_io_req_ready | _mshr_request_T_28; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_30 = _mshr_request_T_27 & _mshr_request_T_29; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_31 = ~_mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_32 = _sourceC_io_req_ready | _mshr_request_T_31; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_33 = _mshr_request_T_30 & _mshr_request_T_32; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_34 = ~_mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_35 = _sourceD_io_req_ready | _mshr_request_T_34; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_36 = _mshr_request_T_33 & _mshr_request_T_35; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_37 = ~_mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_38 = _sourceE_io_req_ready | _mshr_request_T_37; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_39 = _mshr_request_T_36 & _mshr_request_T_38; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_40 = ~_mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_41 = _sourceX_io_req_ready | _mshr_request_T_40; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_42 = _mshr_request_T_39 & _mshr_request_T_41; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_43 = ~_mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_44 = _directory_io_write_ready | _mshr_request_T_43; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_45 = _mshr_request_T_42 & _mshr_request_T_44; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_46 = ~mshr_stall_abc_2; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_47 = _mshrs_2_io_schedule_valid & _mshr_request_T_46; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_48 = ~_mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_49 = _sourceA_io_req_ready | _mshr_request_T_48; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_50 = _mshr_request_T_47 & _mshr_request_T_49; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_51 = ~_mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_52 = _sourceB_io_req_ready | _mshr_request_T_51; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_53 = _mshr_request_T_50 & _mshr_request_T_52; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_54 = ~_mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_55 = _sourceC_io_req_ready | _mshr_request_T_54; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_56 = _mshr_request_T_53 & _mshr_request_T_55; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_57 = ~_mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_58 = _sourceD_io_req_ready | _mshr_request_T_57; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_59 = _mshr_request_T_56 & _mshr_request_T_58; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_60 = ~_mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_61 = _sourceE_io_req_ready | _mshr_request_T_60; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_62 = _mshr_request_T_59 & _mshr_request_T_61; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_63 = ~_mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_64 = _sourceX_io_req_ready | _mshr_request_T_63; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_65 = _mshr_request_T_62 & _mshr_request_T_64; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_66 = ~_mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_67 = _directory_io_write_ready | _mshr_request_T_66; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_68 = _mshr_request_T_65 & _mshr_request_T_67; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_69 = ~mshr_stall_abc_3; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_70 = _mshrs_3_io_schedule_valid & _mshr_request_T_69; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_71 = ~_mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_72 = _sourceA_io_req_ready | _mshr_request_T_71; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_73 = _mshr_request_T_70 & _mshr_request_T_72; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_74 = ~_mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_75 = _sourceB_io_req_ready | _mshr_request_T_74; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_76 = _mshr_request_T_73 & _mshr_request_T_75; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_77 = ~_mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_78 = _sourceC_io_req_ready | _mshr_request_T_77; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_79 = _mshr_request_T_76 & _mshr_request_T_78; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_80 = ~_mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_81 = _sourceD_io_req_ready | _mshr_request_T_80; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_82 = _mshr_request_T_79 & _mshr_request_T_81; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_83 = ~_mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_84 = _sourceE_io_req_ready | _mshr_request_T_83; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_85 = _mshr_request_T_82 & _mshr_request_T_84; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_86 = ~_mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_87 = _sourceX_io_req_ready | _mshr_request_T_86; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_88 = _mshr_request_T_85 & _mshr_request_T_87; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_89 = ~_mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_90 = _directory_io_write_ready | _mshr_request_T_89; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_91 = _mshr_request_T_88 & _mshr_request_T_90; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_92 = ~mshr_stall_abc_4; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_93 = _mshrs_4_io_schedule_valid & _mshr_request_T_92; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_94 = ~_mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_95 = _sourceA_io_req_ready | _mshr_request_T_94; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_96 = _mshr_request_T_93 & _mshr_request_T_95; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_97 = ~_mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_98 = _sourceB_io_req_ready | _mshr_request_T_97; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_99 = _mshr_request_T_96 & _mshr_request_T_98; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_100 = ~_mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_101 = _sourceC_io_req_ready | _mshr_request_T_100; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_102 = _mshr_request_T_99 & _mshr_request_T_101; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_103 = ~_mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_104 = _sourceD_io_req_ready | _mshr_request_T_103; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_105 = _mshr_request_T_102 & _mshr_request_T_104; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_106 = ~_mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_107 = _sourceE_io_req_ready | _mshr_request_T_106; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_108 = _mshr_request_T_105 & _mshr_request_T_107; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_109 = ~_mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_110 = _sourceX_io_req_ready | _mshr_request_T_109; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_111 = _mshr_request_T_108 & _mshr_request_T_110; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_112 = ~_mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_113 = _directory_io_write_ready | _mshr_request_T_112; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_114 = _mshr_request_T_111 & _mshr_request_T_113; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_115 = ~mshr_stall_bc; // @[Scheduler.scala:94:28, :107:28]
wire _mshr_request_T_116 = _mshrs_5_io_schedule_valid & _mshr_request_T_115; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_117 = ~_mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_118 = _sourceA_io_req_ready | _mshr_request_T_117; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_119 = _mshr_request_T_116 & _mshr_request_T_118; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_120 = ~_mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_121 = _sourceB_io_req_ready | _mshr_request_T_120; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_122 = _mshr_request_T_119 & _mshr_request_T_121; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_123 = ~_mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_124 = _sourceC_io_req_ready | _mshr_request_T_123; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_125 = _mshr_request_T_122 & _mshr_request_T_124; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_126 = ~_mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_127 = _sourceD_io_req_ready | _mshr_request_T_126; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_128 = _mshr_request_T_125 & _mshr_request_T_127; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_129 = ~_mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_130 = _sourceE_io_req_ready | _mshr_request_T_129; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_131 = _mshr_request_T_128 & _mshr_request_T_130; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_132 = ~_mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_133 = _sourceX_io_req_ready | _mshr_request_T_132; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_134 = _mshr_request_T_131 & _mshr_request_T_133; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_135 = ~_mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_136 = _directory_io_write_ready | _mshr_request_T_135; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_137 = _mshr_request_T_134 & _mshr_request_T_136; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_140 = ~_mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_141 = _sourceA_io_req_ready | _mshr_request_T_140; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_139; // @[Scheduler.scala:107:25]
wire _mshr_request_T_142 = _mshr_request_T_139 & _mshr_request_T_141; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_143 = ~_mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_144 = _sourceB_io_req_ready | _mshr_request_T_143; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_145 = _mshr_request_T_142 & _mshr_request_T_144; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_146 = ~_mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_147 = _sourceC_io_req_ready | _mshr_request_T_146; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_148 = _mshr_request_T_145 & _mshr_request_T_147; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_149 = ~_mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_150 = _sourceD_io_req_ready | _mshr_request_T_149; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_151 = _mshr_request_T_148 & _mshr_request_T_150; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_152 = ~_mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_153 = _sourceE_io_req_ready | _mshr_request_T_152; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_154 = _mshr_request_T_151 & _mshr_request_T_153; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_155 = ~_mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_156 = _sourceX_io_req_ready | _mshr_request_T_155; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_157 = _mshr_request_T_154 & _mshr_request_T_156; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_158 = ~_mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_159 = _directory_io_write_ready | _mshr_request_T_158; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_160 = _mshr_request_T_157 & _mshr_request_T_159; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire [1:0] mshr_request_lo_hi = {_mshr_request_T_68, _mshr_request_T_45}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_lo = {mshr_request_lo_hi, _mshr_request_T_22}; // @[Scheduler.scala:106:25, :113:61]
wire [1:0] mshr_request_hi_lo = {_mshr_request_T_114, _mshr_request_T_91}; // @[Scheduler.scala:106:25, :113:61]
wire [1:0] mshr_request_hi_hi = {_mshr_request_T_160, _mshr_request_T_137}; // @[Scheduler.scala:106:25, :113:61]
wire [3:0] mshr_request_hi = {mshr_request_hi_hi, mshr_request_hi_lo}; // @[Scheduler.scala:106:25]
wire [6:0] mshr_request = {mshr_request_hi, mshr_request_lo}; // @[Scheduler.scala:106:25]
reg [6:0] robin_filter; // @[Scheduler.scala:118:29]
wire [6:0] _robin_request_T = mshr_request & robin_filter; // @[Scheduler.scala:106:25, :118:29, :119:54]
wire [13:0] robin_request = {mshr_request, _robin_request_T}; // @[Scheduler.scala:106:25, :119:{26,54}]
wire [14:0] _mshr_selectOH2_T = {robin_request, 1'h0}; // @[package.scala:253:48]
wire [13:0] _mshr_selectOH2_T_1 = _mshr_selectOH2_T[13:0]; // @[package.scala:253:{48,53}]
wire [13:0] _mshr_selectOH2_T_2 = robin_request | _mshr_selectOH2_T_1; // @[package.scala:253:{43,53}]
wire [15:0] _mshr_selectOH2_T_3 = {_mshr_selectOH2_T_2, 2'h0}; // @[package.scala:253:{43,48}]
wire [13:0] _mshr_selectOH2_T_4 = _mshr_selectOH2_T_3[13:0]; // @[package.scala:253:{48,53}]
wire [13:0] _mshr_selectOH2_T_5 = _mshr_selectOH2_T_2 | _mshr_selectOH2_T_4; // @[package.scala:253:{43,53}]
wire [17:0] _mshr_selectOH2_T_6 = {_mshr_selectOH2_T_5, 4'h0}; // @[package.scala:253:{43,48}]
wire [13:0] _mshr_selectOH2_T_7 = _mshr_selectOH2_T_6[13:0]; // @[package.scala:253:{48,53}]
wire [13:0] _mshr_selectOH2_T_8 = _mshr_selectOH2_T_5 | _mshr_selectOH2_T_7; // @[package.scala:253:{43,53}]
wire [21:0] _mshr_selectOH2_T_9 = {_mshr_selectOH2_T_8, 8'h0}; // @[package.scala:253:{43,48}]
wire [13:0] _mshr_selectOH2_T_10 = _mshr_selectOH2_T_9[13:0]; // @[package.scala:253:{48,53}]
wire [13:0] _mshr_selectOH2_T_11 = _mshr_selectOH2_T_8 | _mshr_selectOH2_T_10; // @[package.scala:253:{43,53}]
wire [13:0] _mshr_selectOH2_T_12 = _mshr_selectOH2_T_11; // @[package.scala:253:43, :254:17]
wire [14:0] _mshr_selectOH2_T_13 = {_mshr_selectOH2_T_12, 1'h0}; // @[package.scala:254:17]
wire [14:0] _mshr_selectOH2_T_14 = ~_mshr_selectOH2_T_13; // @[Scheduler.scala:120:{24,48}]
wire [14:0] mshr_selectOH2 = {1'h0, _mshr_selectOH2_T_14[13:0] & robin_request}; // @[Scheduler.scala:119:26, :120:{24,54}]
wire [6:0] _mshr_selectOH_T = mshr_selectOH2[13:7]; // @[Scheduler.scala:120:54, :121:37]
wire [6:0] _mshr_selectOH_T_1 = mshr_selectOH2[6:0]; // @[Scheduler.scala:120:54, :121:86]
wire [6:0] mshr_selectOH = _mshr_selectOH_T | _mshr_selectOH_T_1; // @[Scheduler.scala:121:{37,70,86}]
wire [2:0] mshr_select_hi = mshr_selectOH[6:4]; // @[OneHot.scala:30:18]
wire [3:0] mshr_select_lo = mshr_selectOH[3:0]; // @[OneHot.scala:31:18]
wire _mshr_select_T = |mshr_select_hi; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _mshr_select_T_1 = {1'h0, mshr_select_hi} | mshr_select_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] mshr_select_hi_1 = _mshr_select_T_1[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] mshr_select_lo_1 = _mshr_select_T_1[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _mshr_select_T_2 = |mshr_select_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _mshr_select_T_3 = mshr_select_hi_1 | mshr_select_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _mshr_select_T_4 = _mshr_select_T_3[1]; // @[OneHot.scala:32:28]
wire [1:0] _mshr_select_T_5 = {_mshr_select_T_2, _mshr_select_T_4}; // @[OneHot.scala:32:{10,14}]
wire [2:0] mshr_select = {_mshr_select_T, _mshr_select_T_5}; // @[OneHot.scala:32:{10,14}]
wire [2:0] schedule_a_bits_source = mshr_select; // @[OneHot.scala:32:10]
wire [2:0] schedule_d_bits_sink = mshr_select; // @[OneHot.scala:32:10]
wire _schedule_T = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire _scheduleTag_T = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire _scheduleSet_T = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire sel = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire _schedule_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire _scheduleTag_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire _scheduleSet_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire sel_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire _schedule_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire _scheduleTag_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire _scheduleSet_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire sel_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire _schedule_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire _scheduleTag_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire _scheduleSet_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire sel_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire _schedule_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire _scheduleTag_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire _scheduleSet_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire sel_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire _schedule_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire _scheduleTag_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire _scheduleSet_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire select_bc = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire sel_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire _schedule_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire _scheduleTag_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire _scheduleSet_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire select_c = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire sel_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire _schedule_WIRE_55_valid; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73]
wire _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73]
wire _schedule_WIRE_48_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73]
wire _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73]
wire _schedule_WIRE_38_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73]
wire [2:0] _schedule_c_bits_source_T_1; // @[Scheduler.scala:132:32]
wire [12:0] _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_valid; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73]
wire _schedule_WIRE_15_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73]
wire _schedule_WIRE_11_valid; // @[Mux.scala:30:73]
wire _schedule_WIRE_1_valid; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73]
wire _schedule_WIRE; // @[Mux.scala:30:73]
wire [12:0] schedule_a_bits_tag; // @[Mux.scala:30:73]
wire [9:0] schedule_a_bits_set; // @[Mux.scala:30:73]
wire [2:0] schedule_a_bits_param; // @[Mux.scala:30:73]
wire schedule_a_bits_block; // @[Mux.scala:30:73]
wire schedule_a_valid; // @[Mux.scala:30:73]
wire [2:0] schedule_b_bits_param; // @[Mux.scala:30:73]
wire [12:0] schedule_b_bits_tag; // @[Mux.scala:30:73]
wire [9:0] schedule_b_bits_set; // @[Mux.scala:30:73]
wire schedule_b_bits_clients; // @[Mux.scala:30:73]
wire schedule_b_valid; // @[Mux.scala:30:73]
wire [2:0] schedule_c_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] schedule_c_bits_param; // @[Mux.scala:30:73]
wire [2:0] schedule_c_bits_source; // @[Mux.scala:30:73]
wire [12:0] schedule_c_bits_tag; // @[Mux.scala:30:73]
wire [9:0] schedule_c_bits_set; // @[Mux.scala:30:73]
wire [2:0] schedule_c_bits_way; // @[Mux.scala:30:73]
wire schedule_c_bits_dirty; // @[Mux.scala:30:73]
wire schedule_c_valid; // @[Mux.scala:30:73]
wire schedule_d_bits_prio_0; // @[Mux.scala:30:73]
wire schedule_d_bits_prio_1; // @[Mux.scala:30:73]
wire schedule_d_bits_prio_2; // @[Mux.scala:30:73]
wire schedule_d_bits_control; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_param; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_size; // @[Mux.scala:30:73]
wire [8:0] schedule_d_bits_source; // @[Mux.scala:30:73]
wire [12:0] schedule_d_bits_tag; // @[Mux.scala:30:73]
wire [5:0] schedule_d_bits_offset; // @[Mux.scala:30:73]
wire [5:0] schedule_d_bits_put; // @[Mux.scala:30:73]
wire [9:0] schedule_d_bits_set; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_way; // @[Mux.scala:30:73]
wire schedule_d_bits_bad; // @[Mux.scala:30:73]
wire schedule_d_valid; // @[Mux.scala:30:73]
wire [2:0] schedule_e_bits_sink; // @[Mux.scala:30:73]
wire schedule_e_valid; // @[Mux.scala:30:73]
wire schedule_x_valid; // @[Mux.scala:30:73]
wire schedule_dir_bits_data_dirty; // @[Mux.scala:30:73]
wire [1:0] schedule_dir_bits_data_state; // @[Mux.scala:30:73]
wire schedule_dir_bits_data_clients; // @[Mux.scala:30:73]
wire [12:0] schedule_dir_bits_data_tag; // @[Mux.scala:30:73]
wire [9:0] schedule_dir_bits_set; // @[Mux.scala:30:73]
wire [2:0] schedule_dir_bits_way; // @[Mux.scala:30:73]
wire schedule_dir_valid; // @[Mux.scala:30:73]
wire schedule_reload; // @[Mux.scala:30:73]
wire _schedule_T_7 = _schedule_T & _mshrs_0_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_8 = _schedule_T_1 & _mshrs_1_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_9 = _schedule_T_2 & _mshrs_2_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_10 = _schedule_T_3 & _mshrs_3_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_11 = _schedule_T_4 & _mshrs_4_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_12 = _schedule_T_5 & _mshrs_5_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_13 = _schedule_T_6 & _mshrs_6_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_14 = _schedule_T_7 | _schedule_T_8; // @[Mux.scala:30:73]
wire _schedule_T_15 = _schedule_T_14 | _schedule_T_9; // @[Mux.scala:30:73]
wire _schedule_T_16 = _schedule_T_15 | _schedule_T_10; // @[Mux.scala:30:73]
wire _schedule_T_17 = _schedule_T_16 | _schedule_T_11; // @[Mux.scala:30:73]
wire _schedule_T_18 = _schedule_T_17 | _schedule_T_12; // @[Mux.scala:30:73]
wire _schedule_T_19 = _schedule_T_18 | _schedule_T_13; // @[Mux.scala:30:73]
assign _schedule_WIRE = _schedule_T_19; // @[Mux.scala:30:73]
assign schedule_reload = _schedule_WIRE; // @[Mux.scala:30:73]
wire _schedule_WIRE_10; // @[Mux.scala:30:73]
assign schedule_dir_valid = _schedule_WIRE_1_valid; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_2_set; // @[Mux.scala:30:73]
assign schedule_dir_bits_set = _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_2_way; // @[Mux.scala:30:73]
assign schedule_dir_bits_way = _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_dirty = _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_2_data_state; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_state = _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_clients = _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_tag = _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_9; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_set = _schedule_WIRE_2_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_8; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_way = _schedule_WIRE_2_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_3_dirty; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_dirty = _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_3_state; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_state = _schedule_WIRE_2_data_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_3_clients; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_clients = _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_3_tag; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_tag = _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73]
wire _schedule_WIRE_7; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_dirty = _schedule_WIRE_3_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_6; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_state = _schedule_WIRE_3_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_5; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_clients = _schedule_WIRE_3_clients; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_4; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_tag = _schedule_WIRE_3_tag; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_20 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_21 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_22 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_23 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_24 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_25 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_26 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_27 = _schedule_T_20 | _schedule_T_21; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_28 = _schedule_T_27 | _schedule_T_22; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_29 = _schedule_T_28 | _schedule_T_23; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_30 = _schedule_T_29 | _schedule_T_24; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_31 = _schedule_T_30 | _schedule_T_25; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_32 = _schedule_T_31 | _schedule_T_26; // @[Mux.scala:30:73]
assign _schedule_WIRE_4 = _schedule_T_32; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_tag = _schedule_WIRE_4; // @[Mux.scala:30:73]
wire _schedule_T_33 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_34 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_35 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_36 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_37 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_38 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_39 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_40 = _schedule_T_33 | _schedule_T_34; // @[Mux.scala:30:73]
wire _schedule_T_41 = _schedule_T_40 | _schedule_T_35; // @[Mux.scala:30:73]
wire _schedule_T_42 = _schedule_T_41 | _schedule_T_36; // @[Mux.scala:30:73]
wire _schedule_T_43 = _schedule_T_42 | _schedule_T_37; // @[Mux.scala:30:73]
wire _schedule_T_44 = _schedule_T_43 | _schedule_T_38; // @[Mux.scala:30:73]
wire _schedule_T_45 = _schedule_T_44 | _schedule_T_39; // @[Mux.scala:30:73]
assign _schedule_WIRE_5 = _schedule_T_45; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_clients = _schedule_WIRE_5; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_46 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_47 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_48 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_49 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_50 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_51 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_52 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_53 = _schedule_T_46 | _schedule_T_47; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_54 = _schedule_T_53 | _schedule_T_48; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_55 = _schedule_T_54 | _schedule_T_49; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_56 = _schedule_T_55 | _schedule_T_50; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_57 = _schedule_T_56 | _schedule_T_51; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_58 = _schedule_T_57 | _schedule_T_52; // @[Mux.scala:30:73]
assign _schedule_WIRE_6 = _schedule_T_58; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_state = _schedule_WIRE_6; // @[Mux.scala:30:73]
wire _schedule_T_59 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_60 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_61 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_62 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_63 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_64 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_65 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_66 = _schedule_T_59 | _schedule_T_60; // @[Mux.scala:30:73]
wire _schedule_T_67 = _schedule_T_66 | _schedule_T_61; // @[Mux.scala:30:73]
wire _schedule_T_68 = _schedule_T_67 | _schedule_T_62; // @[Mux.scala:30:73]
wire _schedule_T_69 = _schedule_T_68 | _schedule_T_63; // @[Mux.scala:30:73]
wire _schedule_T_70 = _schedule_T_69 | _schedule_T_64; // @[Mux.scala:30:73]
wire _schedule_T_71 = _schedule_T_70 | _schedule_T_65; // @[Mux.scala:30:73]
assign _schedule_WIRE_7 = _schedule_T_71; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_dirty = _schedule_WIRE_7; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_72 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_73 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_74 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_75 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_76 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_77 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_78 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_79 = _schedule_T_72 | _schedule_T_73; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_80 = _schedule_T_79 | _schedule_T_74; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_81 = _schedule_T_80 | _schedule_T_75; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_82 = _schedule_T_81 | _schedule_T_76; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_83 = _schedule_T_82 | _schedule_T_77; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_84 = _schedule_T_83 | _schedule_T_78; // @[Mux.scala:30:73]
assign _schedule_WIRE_8 = _schedule_T_84; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_way = _schedule_WIRE_8; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_85 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_86 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_87 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_88 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_89 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_90 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_91 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_92 = _schedule_T_85 | _schedule_T_86; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_93 = _schedule_T_92 | _schedule_T_87; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_94 = _schedule_T_93 | _schedule_T_88; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_95 = _schedule_T_94 | _schedule_T_89; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_96 = _schedule_T_95 | _schedule_T_90; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_97 = _schedule_T_96 | _schedule_T_91; // @[Mux.scala:30:73]
assign _schedule_WIRE_9 = _schedule_T_97; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_set = _schedule_WIRE_9; // @[Mux.scala:30:73]
wire _schedule_T_98 = _schedule_T & _mshrs_0_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_99 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_100 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_101 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_102 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_103 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_104 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_105 = _schedule_T_98 | _schedule_T_99; // @[Mux.scala:30:73]
wire _schedule_T_106 = _schedule_T_105 | _schedule_T_100; // @[Mux.scala:30:73]
wire _schedule_T_107 = _schedule_T_106 | _schedule_T_101; // @[Mux.scala:30:73]
wire _schedule_T_108 = _schedule_T_107 | _schedule_T_102; // @[Mux.scala:30:73]
wire _schedule_T_109 = _schedule_T_108 | _schedule_T_103; // @[Mux.scala:30:73]
wire _schedule_T_110 = _schedule_T_109 | _schedule_T_104; // @[Mux.scala:30:73]
assign _schedule_WIRE_10 = _schedule_T_110; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_valid = _schedule_WIRE_10; // @[Mux.scala:30:73]
wire _schedule_WIRE_14; // @[Mux.scala:30:73]
assign schedule_x_valid = _schedule_WIRE_11_valid; // @[Mux.scala:30:73]
wire _schedule_T_124 = _schedule_T & _mshrs_0_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_125 = _schedule_T_1 & _mshrs_1_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_126 = _schedule_T_2 & _mshrs_2_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_127 = _schedule_T_3 & _mshrs_3_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_128 = _schedule_T_4 & _mshrs_4_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_129 = _schedule_T_5 & _mshrs_5_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_130 = _schedule_T_6 & _mshrs_6_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_131 = _schedule_T_124 | _schedule_T_125; // @[Mux.scala:30:73]
wire _schedule_T_132 = _schedule_T_131 | _schedule_T_126; // @[Mux.scala:30:73]
wire _schedule_T_133 = _schedule_T_132 | _schedule_T_127; // @[Mux.scala:30:73]
wire _schedule_T_134 = _schedule_T_133 | _schedule_T_128; // @[Mux.scala:30:73]
wire _schedule_T_135 = _schedule_T_134 | _schedule_T_129; // @[Mux.scala:30:73]
wire _schedule_T_136 = _schedule_T_135 | _schedule_T_130; // @[Mux.scala:30:73]
assign _schedule_WIRE_14 = _schedule_T_136; // @[Mux.scala:30:73]
assign _schedule_WIRE_11_valid = _schedule_WIRE_14; // @[Mux.scala:30:73]
wire _schedule_WIRE_18; // @[Mux.scala:30:73]
assign schedule_e_valid = _schedule_WIRE_15_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_16_sink; // @[Mux.scala:30:73]
assign schedule_e_bits_sink = _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_17; // @[Mux.scala:30:73]
assign _schedule_WIRE_15_bits_sink = _schedule_WIRE_16_sink; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_137 = _schedule_T ? _mshrs_0_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_138 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_139 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_140 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_141 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_142 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_143 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_144 = _schedule_T_137 | _schedule_T_138; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_145 = _schedule_T_144 | _schedule_T_139; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_146 = _schedule_T_145 | _schedule_T_140; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_147 = _schedule_T_146 | _schedule_T_141; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_148 = _schedule_T_147 | _schedule_T_142; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_149 = _schedule_T_148 | _schedule_T_143; // @[Mux.scala:30:73]
assign _schedule_WIRE_17 = _schedule_T_149; // @[Mux.scala:30:73]
assign _schedule_WIRE_16_sink = _schedule_WIRE_17; // @[Mux.scala:30:73]
wire _schedule_T_150 = _schedule_T & _mshrs_0_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_151 = _schedule_T_1 & _mshrs_1_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_152 = _schedule_T_2 & _mshrs_2_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_153 = _schedule_T_3 & _mshrs_3_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_154 = _schedule_T_4 & _mshrs_4_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_155 = _schedule_T_5 & _mshrs_5_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_156 = _schedule_T_6 & _mshrs_6_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_157 = _schedule_T_150 | _schedule_T_151; // @[Mux.scala:30:73]
wire _schedule_T_158 = _schedule_T_157 | _schedule_T_152; // @[Mux.scala:30:73]
wire _schedule_T_159 = _schedule_T_158 | _schedule_T_153; // @[Mux.scala:30:73]
wire _schedule_T_160 = _schedule_T_159 | _schedule_T_154; // @[Mux.scala:30:73]
wire _schedule_T_161 = _schedule_T_160 | _schedule_T_155; // @[Mux.scala:30:73]
wire _schedule_T_162 = _schedule_T_161 | _schedule_T_156; // @[Mux.scala:30:73]
assign _schedule_WIRE_18 = _schedule_T_162; // @[Mux.scala:30:73]
assign _schedule_WIRE_15_valid = _schedule_WIRE_18; // @[Mux.scala:30:73]
wire _schedule_WIRE_37; // @[Mux.scala:30:73]
assign schedule_d_valid = _schedule_WIRE_19_valid; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73]
assign schedule_d_bits_prio_0 = _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73]
assign schedule_d_bits_prio_1 = _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73]
assign schedule_d_bits_prio_2 = _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_control; // @[Mux.scala:30:73]
assign schedule_d_bits_control = _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_opcode; // @[Mux.scala:30:73]
assign schedule_d_bits_opcode = _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_param; // @[Mux.scala:30:73]
assign schedule_d_bits_param = _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_size; // @[Mux.scala:30:73]
assign schedule_d_bits_size = _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_20_source; // @[Mux.scala:30:73]
assign schedule_d_bits_source = _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_20_tag; // @[Mux.scala:30:73]
assign schedule_d_bits_tag = _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_20_offset; // @[Mux.scala:30:73]
assign schedule_d_bits_offset = _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_20_put; // @[Mux.scala:30:73]
assign schedule_d_bits_put = _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_20_set; // @[Mux.scala:30:73]
assign schedule_d_bits_set = _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_way; // @[Mux.scala:30:73]
assign schedule_d_bits_way = _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_bad; // @[Mux.scala:30:73]
assign schedule_d_bits_bad = _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73]
wire _schedule_WIRE_33_0; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_prio_0 = _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_33_1; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_prio_1 = _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_33_2; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_prio_2 = _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73]
wire _schedule_WIRE_32; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_control = _schedule_WIRE_20_control; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_31; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_opcode = _schedule_WIRE_20_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_30; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_param = _schedule_WIRE_20_param; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_29; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_size = _schedule_WIRE_20_size; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_28; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_source = _schedule_WIRE_20_source; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_27; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_tag = _schedule_WIRE_20_tag; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_26; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_offset = _schedule_WIRE_20_offset; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_25; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_put = _schedule_WIRE_20_put; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_24; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_set = _schedule_WIRE_20_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_22; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_way = _schedule_WIRE_20_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_21; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_bad = _schedule_WIRE_20_bad; // @[Mux.scala:30:73]
wire _schedule_T_163 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_164 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_165 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_166 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_167 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_168 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_169 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_170 = _schedule_T_163 | _schedule_T_164; // @[Mux.scala:30:73]
wire _schedule_T_171 = _schedule_T_170 | _schedule_T_165; // @[Mux.scala:30:73]
wire _schedule_T_172 = _schedule_T_171 | _schedule_T_166; // @[Mux.scala:30:73]
wire _schedule_T_173 = _schedule_T_172 | _schedule_T_167; // @[Mux.scala:30:73]
wire _schedule_T_174 = _schedule_T_173 | _schedule_T_168; // @[Mux.scala:30:73]
wire _schedule_T_175 = _schedule_T_174 | _schedule_T_169; // @[Mux.scala:30:73]
assign _schedule_WIRE_21 = _schedule_T_175; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_bad = _schedule_WIRE_21; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_176 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_177 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_178 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_179 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_180 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_181 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_182 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_183 = _schedule_T_176 | _schedule_T_177; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_184 = _schedule_T_183 | _schedule_T_178; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_185 = _schedule_T_184 | _schedule_T_179; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_186 = _schedule_T_185 | _schedule_T_180; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_187 = _schedule_T_186 | _schedule_T_181; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_188 = _schedule_T_187 | _schedule_T_182; // @[Mux.scala:30:73]
assign _schedule_WIRE_22 = _schedule_T_188; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_way = _schedule_WIRE_22; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_202 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_203 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_204 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_205 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_206 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_207 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_208 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_209 = _schedule_T_202 | _schedule_T_203; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_210 = _schedule_T_209 | _schedule_T_204; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_211 = _schedule_T_210 | _schedule_T_205; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_212 = _schedule_T_211 | _schedule_T_206; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_213 = _schedule_T_212 | _schedule_T_207; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_214 = _schedule_T_213 | _schedule_T_208; // @[Mux.scala:30:73]
assign _schedule_WIRE_24 = _schedule_T_214; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_set = _schedule_WIRE_24; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_215 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_216 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_217 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_218 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_219 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_220 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_221 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_222 = _schedule_T_215 | _schedule_T_216; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_223 = _schedule_T_222 | _schedule_T_217; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_224 = _schedule_T_223 | _schedule_T_218; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_225 = _schedule_T_224 | _schedule_T_219; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_226 = _schedule_T_225 | _schedule_T_220; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_227 = _schedule_T_226 | _schedule_T_221; // @[Mux.scala:30:73]
assign _schedule_WIRE_25 = _schedule_T_227; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_put = _schedule_WIRE_25; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_228 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_229 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_230 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_231 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_232 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_233 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_234 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_235 = _schedule_T_228 | _schedule_T_229; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_236 = _schedule_T_235 | _schedule_T_230; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_237 = _schedule_T_236 | _schedule_T_231; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_238 = _schedule_T_237 | _schedule_T_232; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_239 = _schedule_T_238 | _schedule_T_233; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_240 = _schedule_T_239 | _schedule_T_234; // @[Mux.scala:30:73]
assign _schedule_WIRE_26 = _schedule_T_240; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_offset = _schedule_WIRE_26; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_241 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_242 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_243 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_244 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_245 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_246 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_247 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_248 = _schedule_T_241 | _schedule_T_242; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_249 = _schedule_T_248 | _schedule_T_243; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_250 = _schedule_T_249 | _schedule_T_244; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_251 = _schedule_T_250 | _schedule_T_245; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_252 = _schedule_T_251 | _schedule_T_246; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_253 = _schedule_T_252 | _schedule_T_247; // @[Mux.scala:30:73]
assign _schedule_WIRE_27 = _schedule_T_253; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_tag = _schedule_WIRE_27; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_254 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_source : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_255 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_source : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_256 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_source : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_257 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_source : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_258 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_source : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_259 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_source : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_260 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_source : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_261 = _schedule_T_254 | _schedule_T_255; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_262 = _schedule_T_261 | _schedule_T_256; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_263 = _schedule_T_262 | _schedule_T_257; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_264 = _schedule_T_263 | _schedule_T_258; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_265 = _schedule_T_264 | _schedule_T_259; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_266 = _schedule_T_265 | _schedule_T_260; // @[Mux.scala:30:73]
assign _schedule_WIRE_28 = _schedule_T_266; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_source = _schedule_WIRE_28; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_267 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_268 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_269 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_270 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_271 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_272 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_273 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_274 = _schedule_T_267 | _schedule_T_268; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_275 = _schedule_T_274 | _schedule_T_269; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_276 = _schedule_T_275 | _schedule_T_270; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_277 = _schedule_T_276 | _schedule_T_271; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_278 = _schedule_T_277 | _schedule_T_272; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_279 = _schedule_T_278 | _schedule_T_273; // @[Mux.scala:30:73]
assign _schedule_WIRE_29 = _schedule_T_279; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_size = _schedule_WIRE_29; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_280 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_281 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_282 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_283 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_284 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_285 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_286 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_287 = _schedule_T_280 | _schedule_T_281; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_288 = _schedule_T_287 | _schedule_T_282; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_289 = _schedule_T_288 | _schedule_T_283; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_290 = _schedule_T_289 | _schedule_T_284; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_291 = _schedule_T_290 | _schedule_T_285; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_292 = _schedule_T_291 | _schedule_T_286; // @[Mux.scala:30:73]
assign _schedule_WIRE_30 = _schedule_T_292; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_param = _schedule_WIRE_30; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_293 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_294 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_295 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_296 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_297 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_298 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_299 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_300 = _schedule_T_293 | _schedule_T_294; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_301 = _schedule_T_300 | _schedule_T_295; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_302 = _schedule_T_301 | _schedule_T_296; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_303 = _schedule_T_302 | _schedule_T_297; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_304 = _schedule_T_303 | _schedule_T_298; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_305 = _schedule_T_304 | _schedule_T_299; // @[Mux.scala:30:73]
assign _schedule_WIRE_31 = _schedule_T_305; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_opcode = _schedule_WIRE_31; // @[Mux.scala:30:73]
wire _schedule_T_306 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_307 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_308 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_309 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_310 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_311 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_312 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_313 = _schedule_T_306 | _schedule_T_307; // @[Mux.scala:30:73]
wire _schedule_T_314 = _schedule_T_313 | _schedule_T_308; // @[Mux.scala:30:73]
wire _schedule_T_315 = _schedule_T_314 | _schedule_T_309; // @[Mux.scala:30:73]
wire _schedule_T_316 = _schedule_T_315 | _schedule_T_310; // @[Mux.scala:30:73]
wire _schedule_T_317 = _schedule_T_316 | _schedule_T_311; // @[Mux.scala:30:73]
wire _schedule_T_318 = _schedule_T_317 | _schedule_T_312; // @[Mux.scala:30:73]
assign _schedule_WIRE_32 = _schedule_T_318; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_control = _schedule_WIRE_32; // @[Mux.scala:30:73]
wire _schedule_WIRE_34; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_prio_0 = _schedule_WIRE_33_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_35; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_prio_1 = _schedule_WIRE_33_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_36; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_prio_2 = _schedule_WIRE_33_2; // @[Mux.scala:30:73]
wire _schedule_T_319 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_320 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_321 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_322 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_323 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_326 = _schedule_T_319 | _schedule_T_320; // @[Mux.scala:30:73]
wire _schedule_T_327 = _schedule_T_326 | _schedule_T_321; // @[Mux.scala:30:73]
wire _schedule_T_328 = _schedule_T_327 | _schedule_T_322; // @[Mux.scala:30:73]
wire _schedule_T_329 = _schedule_T_328 | _schedule_T_323; // @[Mux.scala:30:73]
wire _schedule_T_330 = _schedule_T_329; // @[Mux.scala:30:73]
wire _schedule_T_331 = _schedule_T_330; // @[Mux.scala:30:73]
assign _schedule_WIRE_34 = _schedule_T_331; // @[Mux.scala:30:73]
assign _schedule_WIRE_33_0 = _schedule_WIRE_34; // @[Mux.scala:30:73]
wire _schedule_T_332 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_333 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_334 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_335 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_336 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_337 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_339 = _schedule_T_332 | _schedule_T_333; // @[Mux.scala:30:73]
wire _schedule_T_340 = _schedule_T_339 | _schedule_T_334; // @[Mux.scala:30:73]
wire _schedule_T_341 = _schedule_T_340 | _schedule_T_335; // @[Mux.scala:30:73]
wire _schedule_T_342 = _schedule_T_341 | _schedule_T_336; // @[Mux.scala:30:73]
wire _schedule_T_343 = _schedule_T_342 | _schedule_T_337; // @[Mux.scala:30:73]
wire _schedule_T_344 = _schedule_T_343; // @[Mux.scala:30:73]
assign _schedule_WIRE_35 = _schedule_T_344; // @[Mux.scala:30:73]
assign _schedule_WIRE_33_1 = _schedule_WIRE_35; // @[Mux.scala:30:73]
wire _schedule_T_345 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_346 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_347 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_348 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_349 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_350 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_351 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_352 = _schedule_T_345 | _schedule_T_346; // @[Mux.scala:30:73]
wire _schedule_T_353 = _schedule_T_352 | _schedule_T_347; // @[Mux.scala:30:73]
wire _schedule_T_354 = _schedule_T_353 | _schedule_T_348; // @[Mux.scala:30:73]
wire _schedule_T_355 = _schedule_T_354 | _schedule_T_349; // @[Mux.scala:30:73]
wire _schedule_T_356 = _schedule_T_355 | _schedule_T_350; // @[Mux.scala:30:73]
wire _schedule_T_357 = _schedule_T_356 | _schedule_T_351; // @[Mux.scala:30:73]
assign _schedule_WIRE_36 = _schedule_T_357; // @[Mux.scala:30:73]
assign _schedule_WIRE_33_2 = _schedule_WIRE_36; // @[Mux.scala:30:73]
wire _schedule_T_358 = _schedule_T & _mshrs_0_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_359 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_360 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_361 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_362 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_363 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_364 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_365 = _schedule_T_358 | _schedule_T_359; // @[Mux.scala:30:73]
wire _schedule_T_366 = _schedule_T_365 | _schedule_T_360; // @[Mux.scala:30:73]
wire _schedule_T_367 = _schedule_T_366 | _schedule_T_361; // @[Mux.scala:30:73]
wire _schedule_T_368 = _schedule_T_367 | _schedule_T_362; // @[Mux.scala:30:73]
wire _schedule_T_369 = _schedule_T_368 | _schedule_T_363; // @[Mux.scala:30:73]
wire _schedule_T_370 = _schedule_T_369 | _schedule_T_364; // @[Mux.scala:30:73]
assign _schedule_WIRE_37 = _schedule_T_370; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_valid = _schedule_WIRE_37; // @[Mux.scala:30:73]
wire _schedule_WIRE_47; // @[Mux.scala:30:73]
assign schedule_c_valid = _schedule_WIRE_38_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_39_opcode; // @[Mux.scala:30:73]
assign schedule_c_bits_opcode = _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_39_param; // @[Mux.scala:30:73]
assign schedule_c_bits_param = _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_39_tag; // @[Mux.scala:30:73]
assign schedule_c_bits_tag = _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_39_set; // @[Mux.scala:30:73]
assign schedule_c_bits_set = _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_39_way; // @[Mux.scala:30:73]
assign schedule_c_bits_way = _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_39_dirty; // @[Mux.scala:30:73]
assign schedule_c_bits_dirty = _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_46; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_opcode = _schedule_WIRE_39_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_45; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_param = _schedule_WIRE_39_param; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_43; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_tag = _schedule_WIRE_39_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_42; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_set = _schedule_WIRE_39_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_41; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_way = _schedule_WIRE_39_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_40; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_dirty = _schedule_WIRE_39_dirty; // @[Mux.scala:30:73]
wire _schedule_T_371 = _schedule_T & _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_372 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_373 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_374 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_375 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_376 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_377 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_378 = _schedule_T_371 | _schedule_T_372; // @[Mux.scala:30:73]
wire _schedule_T_379 = _schedule_T_378 | _schedule_T_373; // @[Mux.scala:30:73]
wire _schedule_T_380 = _schedule_T_379 | _schedule_T_374; // @[Mux.scala:30:73]
wire _schedule_T_381 = _schedule_T_380 | _schedule_T_375; // @[Mux.scala:30:73]
wire _schedule_T_382 = _schedule_T_381 | _schedule_T_376; // @[Mux.scala:30:73]
wire _schedule_T_383 = _schedule_T_382 | _schedule_T_377; // @[Mux.scala:30:73]
assign _schedule_WIRE_40 = _schedule_T_383; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_dirty = _schedule_WIRE_40; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_384 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_385 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_386 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_387 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_388 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_389 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_390 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_391 = _schedule_T_384 | _schedule_T_385; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_392 = _schedule_T_391 | _schedule_T_386; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_393 = _schedule_T_392 | _schedule_T_387; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_394 = _schedule_T_393 | _schedule_T_388; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_395 = _schedule_T_394 | _schedule_T_389; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_396 = _schedule_T_395 | _schedule_T_390; // @[Mux.scala:30:73]
assign _schedule_WIRE_41 = _schedule_T_396; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_way = _schedule_WIRE_41; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_397 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_398 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_399 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_400 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_401 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_402 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_403 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_404 = _schedule_T_397 | _schedule_T_398; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_405 = _schedule_T_404 | _schedule_T_399; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_406 = _schedule_T_405 | _schedule_T_400; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_407 = _schedule_T_406 | _schedule_T_401; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_408 = _schedule_T_407 | _schedule_T_402; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_409 = _schedule_T_408 | _schedule_T_403; // @[Mux.scala:30:73]
assign _schedule_WIRE_42 = _schedule_T_409; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_set = _schedule_WIRE_42; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_410 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_411 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_412 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_413 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_414 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_415 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_416 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_417 = _schedule_T_410 | _schedule_T_411; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_418 = _schedule_T_417 | _schedule_T_412; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_419 = _schedule_T_418 | _schedule_T_413; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_420 = _schedule_T_419 | _schedule_T_414; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_421 = _schedule_T_420 | _schedule_T_415; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_422 = _schedule_T_421 | _schedule_T_416; // @[Mux.scala:30:73]
assign _schedule_WIRE_43 = _schedule_T_422; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_tag = _schedule_WIRE_43; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_436 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_437 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_438 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_439 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_440 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_441 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_442 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_443 = _schedule_T_436 | _schedule_T_437; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_444 = _schedule_T_443 | _schedule_T_438; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_445 = _schedule_T_444 | _schedule_T_439; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_446 = _schedule_T_445 | _schedule_T_440; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_447 = _schedule_T_446 | _schedule_T_441; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_448 = _schedule_T_447 | _schedule_T_442; // @[Mux.scala:30:73]
assign _schedule_WIRE_45 = _schedule_T_448; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_param = _schedule_WIRE_45; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_449 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_450 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_451 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_452 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_453 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_454 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_455 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_456 = _schedule_T_449 | _schedule_T_450; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_457 = _schedule_T_456 | _schedule_T_451; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_458 = _schedule_T_457 | _schedule_T_452; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_459 = _schedule_T_458 | _schedule_T_453; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_460 = _schedule_T_459 | _schedule_T_454; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_461 = _schedule_T_460 | _schedule_T_455; // @[Mux.scala:30:73]
assign _schedule_WIRE_46 = _schedule_T_461; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_opcode = _schedule_WIRE_46; // @[Mux.scala:30:73]
wire _schedule_T_462 = _schedule_T & _mshrs_0_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_463 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_464 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_465 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_466 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_467 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_468 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_469 = _schedule_T_462 | _schedule_T_463; // @[Mux.scala:30:73]
wire _schedule_T_470 = _schedule_T_469 | _schedule_T_464; // @[Mux.scala:30:73]
wire _schedule_T_471 = _schedule_T_470 | _schedule_T_465; // @[Mux.scala:30:73]
wire _schedule_T_472 = _schedule_T_471 | _schedule_T_466; // @[Mux.scala:30:73]
wire _schedule_T_473 = _schedule_T_472 | _schedule_T_467; // @[Mux.scala:30:73]
wire _schedule_T_474 = _schedule_T_473 | _schedule_T_468; // @[Mux.scala:30:73]
assign _schedule_WIRE_47 = _schedule_T_474; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_valid = _schedule_WIRE_47; // @[Mux.scala:30:73]
wire _schedule_WIRE_54; // @[Mux.scala:30:73]
assign schedule_b_valid = _schedule_WIRE_48_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_49_param; // @[Mux.scala:30:73]
assign schedule_b_bits_param = _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_49_tag; // @[Mux.scala:30:73]
assign schedule_b_bits_tag = _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_49_set; // @[Mux.scala:30:73]
assign schedule_b_bits_set = _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73]
wire _schedule_WIRE_49_clients; // @[Mux.scala:30:73]
assign schedule_b_bits_clients = _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_53; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_param = _schedule_WIRE_49_param; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_52; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_tag = _schedule_WIRE_49_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_51; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_set = _schedule_WIRE_49_set; // @[Mux.scala:30:73]
wire _schedule_WIRE_50; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_clients = _schedule_WIRE_49_clients; // @[Mux.scala:30:73]
wire _schedule_T_475 = _schedule_T & _mshrs_0_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_476 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_477 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_478 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_479 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_480 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_481 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_482 = _schedule_T_475 | _schedule_T_476; // @[Mux.scala:30:73]
wire _schedule_T_483 = _schedule_T_482 | _schedule_T_477; // @[Mux.scala:30:73]
wire _schedule_T_484 = _schedule_T_483 | _schedule_T_478; // @[Mux.scala:30:73]
wire _schedule_T_485 = _schedule_T_484 | _schedule_T_479; // @[Mux.scala:30:73]
wire _schedule_T_486 = _schedule_T_485 | _schedule_T_480; // @[Mux.scala:30:73]
wire _schedule_T_487 = _schedule_T_486 | _schedule_T_481; // @[Mux.scala:30:73]
assign _schedule_WIRE_50 = _schedule_T_487; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_clients = _schedule_WIRE_50; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_488 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_489 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_490 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_491 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_492 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_493 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_494 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_495 = _schedule_T_488 | _schedule_T_489; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_496 = _schedule_T_495 | _schedule_T_490; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_497 = _schedule_T_496 | _schedule_T_491; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_498 = _schedule_T_497 | _schedule_T_492; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_499 = _schedule_T_498 | _schedule_T_493; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_500 = _schedule_T_499 | _schedule_T_494; // @[Mux.scala:30:73]
assign _schedule_WIRE_51 = _schedule_T_500; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_set = _schedule_WIRE_51; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_501 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_502 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_503 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_504 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_505 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_506 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_507 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_508 = _schedule_T_501 | _schedule_T_502; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_509 = _schedule_T_508 | _schedule_T_503; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_510 = _schedule_T_509 | _schedule_T_504; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_511 = _schedule_T_510 | _schedule_T_505; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_512 = _schedule_T_511 | _schedule_T_506; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_513 = _schedule_T_512 | _schedule_T_507; // @[Mux.scala:30:73]
assign _schedule_WIRE_52 = _schedule_T_513; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_tag = _schedule_WIRE_52; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_514 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_515 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_516 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_517 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_518 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_519 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_520 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_521 = _schedule_T_514 | _schedule_T_515; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_522 = _schedule_T_521 | _schedule_T_516; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_523 = _schedule_T_522 | _schedule_T_517; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_524 = _schedule_T_523 | _schedule_T_518; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_525 = _schedule_T_524 | _schedule_T_519; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_526 = _schedule_T_525 | _schedule_T_520; // @[Mux.scala:30:73]
assign _schedule_WIRE_53 = _schedule_T_526; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_param = _schedule_WIRE_53; // @[Mux.scala:30:73]
wire _schedule_T_527 = _schedule_T & _mshrs_0_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_528 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_529 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_530 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_531 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_532 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_533 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_534 = _schedule_T_527 | _schedule_T_528; // @[Mux.scala:30:73]
wire _schedule_T_535 = _schedule_T_534 | _schedule_T_529; // @[Mux.scala:30:73]
wire _schedule_T_536 = _schedule_T_535 | _schedule_T_530; // @[Mux.scala:30:73]
wire _schedule_T_537 = _schedule_T_536 | _schedule_T_531; // @[Mux.scala:30:73]
wire _schedule_T_538 = _schedule_T_537 | _schedule_T_532; // @[Mux.scala:30:73]
wire _schedule_T_539 = _schedule_T_538 | _schedule_T_533; // @[Mux.scala:30:73]
assign _schedule_WIRE_54 = _schedule_T_539; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_valid = _schedule_WIRE_54; // @[Mux.scala:30:73]
wire _schedule_WIRE_62; // @[Mux.scala:30:73]
assign schedule_a_valid = _schedule_WIRE_55_valid; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_56_tag; // @[Mux.scala:30:73]
assign schedule_a_bits_tag = _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_56_set; // @[Mux.scala:30:73]
assign schedule_a_bits_set = _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_56_param; // @[Mux.scala:30:73]
assign schedule_a_bits_param = _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73]
wire _schedule_WIRE_56_block; // @[Mux.scala:30:73]
assign schedule_a_bits_block = _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_61; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_tag = _schedule_WIRE_56_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_60; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_set = _schedule_WIRE_56_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_59; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_param = _schedule_WIRE_56_param; // @[Mux.scala:30:73]
wire _schedule_WIRE_57; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_block = _schedule_WIRE_56_block; // @[Mux.scala:30:73]
wire _schedule_T_540 = _schedule_T & _mshrs_0_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_541 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_542 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_543 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_544 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_545 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_546 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_547 = _schedule_T_540 | _schedule_T_541; // @[Mux.scala:30:73]
wire _schedule_T_548 = _schedule_T_547 | _schedule_T_542; // @[Mux.scala:30:73]
wire _schedule_T_549 = _schedule_T_548 | _schedule_T_543; // @[Mux.scala:30:73]
wire _schedule_T_550 = _schedule_T_549 | _schedule_T_544; // @[Mux.scala:30:73]
wire _schedule_T_551 = _schedule_T_550 | _schedule_T_545; // @[Mux.scala:30:73]
wire _schedule_T_552 = _schedule_T_551 | _schedule_T_546; // @[Mux.scala:30:73]
assign _schedule_WIRE_57 = _schedule_T_552; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_block = _schedule_WIRE_57; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_566 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_567 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_568 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_569 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_570 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_571 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_572 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_573 = _schedule_T_566 | _schedule_T_567; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_574 = _schedule_T_573 | _schedule_T_568; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_575 = _schedule_T_574 | _schedule_T_569; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_576 = _schedule_T_575 | _schedule_T_570; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_577 = _schedule_T_576 | _schedule_T_571; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_578 = _schedule_T_577 | _schedule_T_572; // @[Mux.scala:30:73]
assign _schedule_WIRE_59 = _schedule_T_578; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_param = _schedule_WIRE_59; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_579 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_580 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_581 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_582 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_583 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_584 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_585 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_586 = _schedule_T_579 | _schedule_T_580; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_587 = _schedule_T_586 | _schedule_T_581; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_588 = _schedule_T_587 | _schedule_T_582; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_589 = _schedule_T_588 | _schedule_T_583; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_590 = _schedule_T_589 | _schedule_T_584; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_591 = _schedule_T_590 | _schedule_T_585; // @[Mux.scala:30:73]
assign _schedule_WIRE_60 = _schedule_T_591; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_set = _schedule_WIRE_60; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_592 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_593 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_594 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_595 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_596 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_597 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_598 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_599 = _schedule_T_592 | _schedule_T_593; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_600 = _schedule_T_599 | _schedule_T_594; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_601 = _schedule_T_600 | _schedule_T_595; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_602 = _schedule_T_601 | _schedule_T_596; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_603 = _schedule_T_602 | _schedule_T_597; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_604 = _schedule_T_603 | _schedule_T_598; // @[Mux.scala:30:73]
assign _schedule_WIRE_61 = _schedule_T_604; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_tag = _schedule_WIRE_61; // @[Mux.scala:30:73]
wire _schedule_T_605 = _schedule_T & _mshrs_0_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_606 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_607 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_608 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_609 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_610 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_611 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_612 = _schedule_T_605 | _schedule_T_606; // @[Mux.scala:30:73]
wire _schedule_T_613 = _schedule_T_612 | _schedule_T_607; // @[Mux.scala:30:73]
wire _schedule_T_614 = _schedule_T_613 | _schedule_T_608; // @[Mux.scala:30:73]
wire _schedule_T_615 = _schedule_T_614 | _schedule_T_609; // @[Mux.scala:30:73]
wire _schedule_T_616 = _schedule_T_615 | _schedule_T_610; // @[Mux.scala:30:73]
wire _schedule_T_617 = _schedule_T_616 | _schedule_T_611; // @[Mux.scala:30:73]
assign _schedule_WIRE_62 = _schedule_T_617; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_valid = _schedule_WIRE_62; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_7 = _scheduleTag_T ? _mshrs_0_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_8 = _scheduleTag_T_1 ? _mshrs_1_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_9 = _scheduleTag_T_2 ? _mshrs_2_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_10 = _scheduleTag_T_3 ? _mshrs_3_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_11 = _scheduleTag_T_4 ? _mshrs_4_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_12 = _scheduleTag_T_5 ? _mshrs_5_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_13 = _scheduleTag_T_6 ? _mshrs_6_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_14 = _scheduleTag_T_7 | _scheduleTag_T_8; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_15 = _scheduleTag_T_14 | _scheduleTag_T_9; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_16 = _scheduleTag_T_15 | _scheduleTag_T_10; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_17 = _scheduleTag_T_16 | _scheduleTag_T_11; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_18 = _scheduleTag_T_17 | _scheduleTag_T_12; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_19 = _scheduleTag_T_18 | _scheduleTag_T_13; // @[Mux.scala:30:73]
wire [12:0] scheduleTag = _scheduleTag_T_19; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_7 = _scheduleSet_T ? _mshrs_0_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_8 = _scheduleSet_T_1 ? _mshrs_1_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_9 = _scheduleSet_T_2 ? _mshrs_2_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_10 = _scheduleSet_T_3 ? _mshrs_3_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_11 = _scheduleSet_T_4 ? _mshrs_4_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_12 = _scheduleSet_T_5 ? _mshrs_5_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_13 = _scheduleSet_T_6 ? _mshrs_6_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_14 = _scheduleSet_T_7 | _scheduleSet_T_8; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_15 = _scheduleSet_T_14 | _scheduleSet_T_9; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_16 = _scheduleSet_T_15 | _scheduleSet_T_10; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_17 = _scheduleSet_T_16 | _scheduleSet_T_11; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_18 = _scheduleSet_T_17 | _scheduleSet_T_12; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_19 = _scheduleSet_T_18 | _scheduleSet_T_13; // @[Mux.scala:30:73]
wire [9:0] scheduleSet = _scheduleSet_T_19; // @[Mux.scala:30:73]
wire [5:0] _robin_filter_T = mshr_selectOH[6:1]; // @[package.scala:262:48]
wire [6:0] _robin_filter_T_1 = {mshr_selectOH[6], mshr_selectOH[5:0] | _robin_filter_T}; // @[Mux.scala:32:36]
wire [4:0] _robin_filter_T_2 = _robin_filter_T_1[6:2]; // @[package.scala:262:{43,48}]
wire [6:0] _robin_filter_T_3 = {_robin_filter_T_1[6:5], _robin_filter_T_1[4:0] | _robin_filter_T_2}; // @[package.scala:262:{43,48}]
wire [2:0] _robin_filter_T_4 = _robin_filter_T_3[6:4]; // @[package.scala:262:{43,48}]
wire [6:0] _robin_filter_T_5 = {_robin_filter_T_3[6:3], _robin_filter_T_3[2:0] | _robin_filter_T_4}; // @[package.scala:262:{43,48}]
wire [6:0] _robin_filter_T_6 = _robin_filter_T_5; // @[package.scala:262:43, :263:17]
wire [6:0] _robin_filter_T_7 = ~_robin_filter_T_6; // @[package.scala:263:17]
wire _schedule_c_bits_source_T = schedule_c_bits_opcode[1]; // @[Mux.scala:30:73]
assign _schedule_c_bits_source_T_1 = _schedule_c_bits_source_T ? mshr_select : 3'h0; // @[OneHot.scala:32:10]
assign schedule_c_bits_source = _schedule_c_bits_source_T_1; // @[Mux.scala:30:73]
assign _nestedwb_set_T = select_c ? _mshrs_6_io_status_bits_set : _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46, :153:32, :155:24]
assign nestedwb_set = _nestedwb_set_T; // @[Scheduler.scala:75:22, :155:24]
assign _nestedwb_tag_T = select_c ? _mshrs_6_io_status_bits_tag : _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46, :153:32, :156:24]
assign nestedwb_tag = _nestedwb_tag_T; // @[Scheduler.scala:75:22, :156:24]
wire _GEN = select_bc & _mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :154:32, :157:37]
wire _nestedwb_b_toN_T; // @[Scheduler.scala:157:37]
assign _nestedwb_b_toN_T = _GEN; // @[Scheduler.scala:157:37]
wire _nestedwb_b_toB_T; // @[Scheduler.scala:158:37]
assign _nestedwb_b_toB_T = _GEN; // @[Scheduler.scala:157:37, :158:37]
assign _nestedwb_b_clr_dirty_T = _GEN; // @[Scheduler.scala:157:37, :159:37]
wire _nestedwb_b_toN_T_1 = _mshrs_5_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala:71:46, :157:123]
assign _nestedwb_b_toN_T_2 = _nestedwb_b_toN_T & _nestedwb_b_toN_T_1; // @[Scheduler.scala:157:{37,75,123}]
assign nestedwb_b_toN = _nestedwb_b_toN_T_2; // @[Scheduler.scala:75:22, :157:75]
wire _nestedwb_b_toB_T_1 = _mshrs_5_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala:71:46, :158:123]
assign _nestedwb_b_toB_T_2 = _nestedwb_b_toB_T & _nestedwb_b_toB_T_1; // @[Scheduler.scala:158:{37,75,123}]
assign nestedwb_b_toB = _nestedwb_b_toB_T_2; // @[Scheduler.scala:75:22, :158:75]
assign nestedwb_b_clr_dirty = _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:75:22, :159:37]
wire _nestedwb_c_set_dirty_T = select_c & _mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :153:32, :160:37]
assign _nestedwb_c_set_dirty_T_1 = _nestedwb_c_set_dirty_T & _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46, :160:{37,75}]
assign nestedwb_c_set_dirty = _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:75:22, :160:75]
wire _request_ready_T_2; // @[Scheduler.scala:261:40]
wire _request_valid_T_2; // @[Scheduler.scala:164:39]
wire _request_bits_T_1_prio_0; // @[Scheduler.scala:165:22]
wire _view__WIRE_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_1_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_2_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_3_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_4_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_5_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_6_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _request_bits_T_1_prio_2; // @[Scheduler.scala:165:22]
wire _request_bits_T_1_control; // @[Scheduler.scala:165:22]
wire _view__WIRE_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_1_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_2_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_3_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_4_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_5_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_6_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _request_bits_T_1_opcode; // @[Scheduler.scala:165:22]
wire _view__WIRE_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_1_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_2_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_3_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_4_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_5_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_6_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _request_bits_T_1_param; // @[Scheduler.scala:165:22]
wire [2:0] _view__WIRE_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_1_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_2_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_3_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_4_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_5_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_6_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _request_bits_T_1_size; // @[Scheduler.scala:165:22]
wire [2:0] _view__WIRE_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_1_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_2_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_3_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_4_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_5_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_6_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _request_bits_T_1_source; // @[Scheduler.scala:165:22]
wire [2:0] _view__WIRE_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_1_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_2_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_3_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_4_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_5_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_6_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _request_bits_T_1_tag; // @[Scheduler.scala:165:22]
wire [8:0] _view__WIRE_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_1_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_2_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_3_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_4_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_5_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_6_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _request_bits_T_1_offset; // @[Scheduler.scala:165:22]
wire [12:0] _view__WIRE_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_1_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_2_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_3_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_4_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_5_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_6_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _request_bits_T_1_put; // @[Scheduler.scala:165:22]
wire [5:0] _view__WIRE_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_1_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_2_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_3_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_4_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_5_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_6_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [9:0] _request_bits_T_1_set; // @[Scheduler.scala:165:22]
wire [5:0] _view__WIRE_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_1_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_2_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_3_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_4_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_5_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_6_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [9:0] request_bits_set; // @[Scheduler.scala:163:21]
wire request_ready; // @[Scheduler.scala:163:21]
wire request_valid; // @[Scheduler.scala:163:21]
wire _request_valid_T = _sinkA_io_req_valid | _sinkX_io_req_valid; // @[Scheduler.scala:54:21, :58:21, :164:62]
wire _request_valid_T_1 = _request_valid_T | _sinkC_io_req_valid; // @[Scheduler.scala:55:21, :164:{62,84}]
assign _request_valid_T_2 = _directory_io_ready & _request_valid_T_1; // @[Scheduler.scala:68:25, :164:{39,84}]
assign request_valid = _request_valid_T_2; // @[Scheduler.scala:163:21, :164:39]
wire [2:0] _request_bits_T_opcode = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [2:0] _request_bits_T_param = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [2:0] _request_bits_T_size = _sinkX_io_req_valid ? 3'h6 : _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [8:0] _request_bits_T_source = _sinkX_io_req_valid ? 9'h0 : _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [12:0] _request_bits_T_tag = _sinkX_io_req_valid ? _sinkX_io_req_bits_tag : _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [5:0] _request_bits_T_offset = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [5:0] _request_bits_T_put = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [9:0] _request_bits_T_set = _sinkX_io_req_valid ? _sinkX_io_req_bits_set : _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire _request_bits_T_control; // @[Scheduler.scala:166:22]
assign _request_bits_T_1_control = ~_sinkC_io_req_valid & _request_bits_T_control; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_opcode = _sinkC_io_req_valid ? _sinkC_io_req_bits_opcode : _request_bits_T_opcode; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_param = _sinkC_io_req_valid ? _sinkC_io_req_bits_param : _request_bits_T_param; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_size = _sinkC_io_req_valid ? _sinkC_io_req_bits_size : _request_bits_T_size; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_source = _sinkC_io_req_valid ? _sinkC_io_req_bits_source : _request_bits_T_source; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_tag = _sinkC_io_req_valid ? _sinkC_io_req_bits_tag : _request_bits_T_tag; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_offset = _sinkC_io_req_valid ? _sinkC_io_req_bits_offset : _request_bits_T_offset; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_put = _sinkC_io_req_valid ? _sinkC_io_req_bits_put : _request_bits_T_put; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_set = _sinkC_io_req_valid ? _sinkC_io_req_bits_set : _request_bits_T_set; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_prio_0 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22]
assign request_bits_prio_0 = _request_bits_T_1_prio_0; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_prio_2 = _request_bits_T_1_prio_2; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_control = _request_bits_T_1_control; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_opcode = _request_bits_T_1_opcode; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_param = _request_bits_T_1_param; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_size = _request_bits_T_1_size; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_source = _request_bits_T_1_source; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_tag = _request_bits_T_1_tag; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_offset = _request_bits_T_1_offset; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_put = _request_bits_T_1_put; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_set = _request_bits_T_1_set; // @[Scheduler.scala:163:21, :165:22]
wire _GEN_0 = _directory_io_ready & request_ready; // @[Scheduler.scala:68:25, :163:21, :167:44]
wire _sinkC_io_req_ready_T; // @[Scheduler.scala:167:44]
assign _sinkC_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44]
wire _sinkX_io_req_ready_T; // @[Scheduler.scala:168:44]
assign _sinkX_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :168:44]
wire _sinkA_io_req_ready_T; // @[Scheduler.scala:169:44]
assign _sinkA_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :169:44]
wire _sinkX_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :168:64]
wire _sinkX_io_req_ready_T_2 = _sinkX_io_req_ready_T & _sinkX_io_req_ready_T_1; // @[Scheduler.scala:168:{44,61,64}]
wire _sinkA_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :169:64]
wire _sinkA_io_req_ready_T_2 = _sinkA_io_req_ready_T & _sinkA_io_req_ready_T_1; // @[Scheduler.scala:169:{44,61,64}]
wire _sinkA_io_req_ready_T_3 = ~_sinkX_io_req_valid; // @[Scheduler.scala:58:21, :169:87]
wire _sinkA_io_req_ready_T_4 = _sinkA_io_req_ready_T_2 & _sinkA_io_req_ready_T_3; // @[Scheduler.scala:169:{61,84,87}]
wire _setMatches_T = _mshrs_0_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_1 = _mshrs_0_io_status_valid & _setMatches_T; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_2 = _mshrs_1_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_3 = _mshrs_1_io_status_valid & _setMatches_T_2; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_4 = _mshrs_2_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_5 = _mshrs_2_io_status_valid & _setMatches_T_4; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_6 = _mshrs_3_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_7 = _mshrs_3_io_status_valid & _setMatches_T_6; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_8 = _mshrs_4_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_9 = _mshrs_4_io_status_valid & _setMatches_T_8; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_10 = _mshrs_5_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_11 = _mshrs_5_io_status_valid & _setMatches_T_10; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_12 = _mshrs_6_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_13 = _mshrs_6_io_status_valid & _setMatches_T_12; // @[Scheduler.scala:71:46, :172:{59,83}]
wire [1:0] setMatches_lo_hi = {_setMatches_T_5, _setMatches_T_3}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_lo = {setMatches_lo_hi, _setMatches_T_1}; // @[Scheduler.scala:172:{23,59}]
wire [1:0] setMatches_hi_lo = {_setMatches_T_9, _setMatches_T_7}; // @[Scheduler.scala:172:{23,59}]
wire [1:0] setMatches_hi_hi = {_setMatches_T_13, _setMatches_T_11}; // @[Scheduler.scala:172:{23,59}]
wire [3:0] setMatches_hi = {setMatches_hi_hi, setMatches_hi_lo}; // @[Scheduler.scala:172:23]
wire [6:0] setMatches = {setMatches_hi, setMatches_lo}; // @[Scheduler.scala:172:23]
wire _alloc_T = |setMatches; // @[Scheduler.scala:172:23, :173:27]
wire alloc = ~_alloc_T; // @[Scheduler.scala:173:{15,27}]
wire _blockB_T = setMatches[0]; // @[Mux.scala:32:36]
wire _blockC_T = setMatches[0]; // @[Mux.scala:32:36]
wire _nestB_T = setMatches[0]; // @[Mux.scala:32:36]
wire _nestC_T = setMatches[0]; // @[Mux.scala:32:36]
wire _blockB_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _blockC_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _nestB_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _nestC_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _blockB_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _blockC_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _nestB_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _nestC_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _blockB_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _blockC_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _nestB_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _nestC_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _blockB_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _blockC_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _nestB_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _nestC_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _blockB_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _blockC_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _nestB_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _nestC_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _blockB_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _blockC_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _nestB_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _nestC_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _blockB_T_7 = _blockB_T & _mshrs_0_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_8 = _blockB_T_1 & _mshrs_1_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_9 = _blockB_T_2 & _mshrs_2_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_10 = _blockB_T_3 & _mshrs_3_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_11 = _blockB_T_4 & _mshrs_4_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_12 = _blockB_T_5 & _mshrs_5_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_13 = _blockB_T_6 & _mshrs_6_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_14 = _blockB_T_7 | _blockB_T_8; // @[Mux.scala:30:73]
wire _blockB_T_15 = _blockB_T_14 | _blockB_T_9; // @[Mux.scala:30:73]
wire _blockB_T_16 = _blockB_T_15 | _blockB_T_10; // @[Mux.scala:30:73]
wire _blockB_T_17 = _blockB_T_16 | _blockB_T_11; // @[Mux.scala:30:73]
wire _blockB_T_18 = _blockB_T_17 | _blockB_T_12; // @[Mux.scala:30:73]
wire _blockB_T_19 = _blockB_T_18 | _blockB_T_13; // @[Mux.scala:30:73]
wire _blockB_WIRE = _blockB_T_19; // @[Mux.scala:30:73]
wire _blockC_T_7 = _blockC_T & _mshrs_0_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_8 = _blockC_T_1 & _mshrs_1_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_9 = _blockC_T_2 & _mshrs_2_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_10 = _blockC_T_3 & _mshrs_3_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_11 = _blockC_T_4 & _mshrs_4_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_12 = _blockC_T_5 & _mshrs_5_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_13 = _blockC_T_6 & _mshrs_6_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_14 = _blockC_T_7 | _blockC_T_8; // @[Mux.scala:30:73]
wire _blockC_T_15 = _blockC_T_14 | _blockC_T_9; // @[Mux.scala:30:73]
wire _blockC_T_16 = _blockC_T_15 | _blockC_T_10; // @[Mux.scala:30:73]
wire _blockC_T_17 = _blockC_T_16 | _blockC_T_11; // @[Mux.scala:30:73]
wire _blockC_T_18 = _blockC_T_17 | _blockC_T_12; // @[Mux.scala:30:73]
wire _blockC_T_19 = _blockC_T_18 | _blockC_T_13; // @[Mux.scala:30:73]
wire _blockC_WIRE = _blockC_T_19; // @[Mux.scala:30:73]
wire blockC = _blockC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73]
wire _nestB_T_7 = _nestB_T & _mshrs_0_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_8 = _nestB_T_1 & _mshrs_1_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_9 = _nestB_T_2 & _mshrs_2_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_10 = _nestB_T_3 & _mshrs_3_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_11 = _nestB_T_4 & _mshrs_4_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_12 = _nestB_T_5 & _mshrs_5_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_13 = _nestB_T_6 & _mshrs_6_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_14 = _nestB_T_7 | _nestB_T_8; // @[Mux.scala:30:73]
wire _nestB_T_15 = _nestB_T_14 | _nestB_T_9; // @[Mux.scala:30:73]
wire _nestB_T_16 = _nestB_T_15 | _nestB_T_10; // @[Mux.scala:30:73]
wire _nestB_T_17 = _nestB_T_16 | _nestB_T_11; // @[Mux.scala:30:73]
wire _nestB_T_18 = _nestB_T_17 | _nestB_T_12; // @[Mux.scala:30:73]
wire _nestB_T_19 = _nestB_T_18 | _nestB_T_13; // @[Mux.scala:30:73]
wire _nestB_WIRE = _nestB_T_19; // @[Mux.scala:30:73]
wire _nestC_T_7 = _nestC_T & _mshrs_0_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_8 = _nestC_T_1 & _mshrs_1_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_9 = _nestC_T_2 & _mshrs_2_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_10 = _nestC_T_3 & _mshrs_3_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_11 = _nestC_T_4 & _mshrs_4_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_12 = _nestC_T_5 & _mshrs_5_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_13 = _nestC_T_6 & _mshrs_6_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_14 = _nestC_T_7 | _nestC_T_8; // @[Mux.scala:30:73]
wire _nestC_T_15 = _nestC_T_14 | _nestC_T_9; // @[Mux.scala:30:73]
wire _nestC_T_16 = _nestC_T_15 | _nestC_T_10; // @[Mux.scala:30:73]
wire _nestC_T_17 = _nestC_T_16 | _nestC_T_11; // @[Mux.scala:30:73]
wire _nestC_T_18 = _nestC_T_17 | _nestC_T_12; // @[Mux.scala:30:73]
wire _nestC_T_19 = _nestC_T_18 | _nestC_T_13; // @[Mux.scala:30:73]
wire _nestC_WIRE = _nestC_T_19; // @[Mux.scala:30:73]
wire nestC = _nestC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73]
wire _prioFilter_T = ~request_bits_prio_0; // @[Scheduler.scala:163:21, :182:46]
wire [1:0] prioFilter_hi = {request_bits_prio_2, _prioFilter_T}; // @[Scheduler.scala:163:21, :182:{23,46}]
wire [6:0] prioFilter = {prioFilter_hi, 5'h1F}; // @[Scheduler.scala:182:23]
wire [6:0] lowerMatches = setMatches & prioFilter; // @[Scheduler.scala:172:23, :182:23, :183:33]
wire _queue_T = |lowerMatches; // @[Scheduler.scala:183:33, :185:28]
wire _queue_T_2 = _queue_T; // @[Scheduler.scala:185:{28,32}]
wire _queue_T_3 = ~nestC; // @[Scheduler.scala:180:70, :185:45]
wire _queue_T_4 = _queue_T_2 & _queue_T_3; // @[Scheduler.scala:185:{32,42,45}]
wire _queue_T_6 = _queue_T_4; // @[Scheduler.scala:185:{42,52}]
wire _queue_T_7 = ~blockC; // @[Scheduler.scala:176:70, :185:66]
wire queue = _queue_T_6 & _queue_T_7; // @[Scheduler.scala:185:{52,63,66}]
wire _T_7 = request_valid & queue; // @[Scheduler.scala:163:21, :185:63, :195:31]
wire _bypass_T; // @[Scheduler.scala:213:30]
assign _bypass_T = _T_7; // @[Scheduler.scala:195:31, :213:30]
wire _bypass_T_1; // @[Scheduler.scala:231:32]
assign _bypass_T_1 = _T_7; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_2; // @[Scheduler.scala:231:32]
assign _bypass_T_2 = _T_7; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_3; // @[Scheduler.scala:231:32]
assign _bypass_T_3 = _T_7; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_4; // @[Scheduler.scala:231:32]
assign _bypass_T_4 = _T_7; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_5; // @[Scheduler.scala:231:32]
assign _bypass_T_5 = _T_7; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_6; // @[Scheduler.scala:231:32]
assign _bypass_T_6 = _T_7; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_7; // @[Scheduler.scala:231:32]
assign _bypass_T_7 = _T_7; // @[Scheduler.scala:195:31, :231:32]
wire _requests_io_push_valid_T; // @[Scheduler.scala:270:43]
assign _requests_io_push_valid_T = _T_7; // @[Scheduler.scala:195:31, :270:43]
wire _lowerMatches1_T = lowerMatches[6]; // @[Scheduler.scala:183:33, :200:21]
wire _lowerMatches1_T_2 = lowerMatches[5]; // @[Scheduler.scala:183:33, :201:21]
wire [6:0] _lowerMatches1_T_4 = _lowerMatches1_T_2 ? 7'h20 : lowerMatches; // @[Scheduler.scala:183:33, :201:{8,21}]
wire [6:0] lowerMatches1 = _lowerMatches1_T ? 7'h40 : _lowerMatches1_T_4; // @[Scheduler.scala:200:{8,21}, :201:8]
wire [6:0] _requests_io_push_bits_index_T = lowerMatches1; // @[Scheduler.scala:200:8, :274:30]
wire [13:0] _GEN_1 = {2{mshr_selectOH}}; // @[Scheduler.scala:121:70, :206:30]
wire [13:0] selected_requests_hi; // @[Scheduler.scala:206:30]
assign selected_requests_hi = _GEN_1; // @[Scheduler.scala:206:30]
wire [13:0] pop_index_hi; // @[Scheduler.scala:241:31]
assign pop_index_hi = _GEN_1; // @[Scheduler.scala:206:30, :241:31]
wire [20:0] _selected_requests_T = {selected_requests_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :206:30]
wire [20:0] selected_requests = _selected_requests_T & _requests_io_valid; // @[Scheduler.scala:70:24, :206:{30,76}]
wire [6:0] _a_pop_T = selected_requests[6:0]; // @[Scheduler.scala:206:76, :207:32]
wire a_pop = |_a_pop_T; // @[Scheduler.scala:207:{32,79}]
wire [6:0] _b_pop_T = selected_requests[13:7]; // @[Scheduler.scala:206:76, :208:32]
wire b_pop = |_b_pop_T; // @[Scheduler.scala:208:{32,79}]
wire _bypassMatches_T_4 = b_pop; // @[Scheduler.scala:208:79, :211:76]
wire [6:0] _c_pop_T = selected_requests[20:14]; // @[Scheduler.scala:206:76, :209:32]
wire c_pop = |_c_pop_T; // @[Scheduler.scala:209:{32,79}]
wire [6:0] _bypassMatches_T = mshr_selectOH & lowerMatches1; // @[Scheduler.scala:121:70, :200:8, :210:38]
wire _bypassMatches_T_1 = |_bypassMatches_T; // @[Scheduler.scala:210:{38,55}]
wire _bypassMatches_T_2 = c_pop | request_bits_prio_2; // @[Scheduler.scala:163:21, :209:79, :211:33]
wire _bypassMatches_T_3 = ~c_pop; // @[Scheduler.scala:209:79, :211:58]
wire _bypassMatches_T_5 = ~b_pop; // @[Scheduler.scala:208:79, :211:101]
wire _bypassMatches_T_6 = ~a_pop; // @[Scheduler.scala:207:79, :211:109]
wire _bypassMatches_T_7 = _bypassMatches_T_4 ? _bypassMatches_T_5 : _bypassMatches_T_6; // @[Scheduler.scala:211:{69,76,101,109}]
wire _bypassMatches_T_8 = _bypassMatches_T_2 ? _bypassMatches_T_3 : _bypassMatches_T_7; // @[Scheduler.scala:211:{26,33,58,69}]
wire bypassMatches = _bypassMatches_T_1 & _bypassMatches_T_8; // @[Scheduler.scala:210:{55,59}, :211:26]
wire _may_pop_T = a_pop | b_pop; // @[Scheduler.scala:207:79, :208:79, :212:23]
wire may_pop = _may_pop_T | c_pop; // @[Scheduler.scala:209:79, :212:{23,32}]
wire bypass = _bypass_T & bypassMatches; // @[Scheduler.scala:210:59, :213:{30,39}]
wire _will_reload_T = may_pop | bypass; // @[Scheduler.scala:212:32, :213:39, :214:49]
wire will_reload = schedule_reload & _will_reload_T; // @[Mux.scala:30:73]
wire _GEN_2 = schedule_reload & may_pop; // @[Mux.scala:30:73]
wire _will_pop_T; // @[Scheduler.scala:215:34]
assign _will_pop_T = _GEN_2; // @[Scheduler.scala:215:34]
wire _mshr_uses_directory_assuming_no_bypass_T; // @[Scheduler.scala:247:64]
assign _mshr_uses_directory_assuming_no_bypass_T = _GEN_2; // @[Scheduler.scala:215:34, :247:64]
wire _will_pop_T_1 = ~bypass; // @[Scheduler.scala:213:39, :215:48]
wire will_pop = _will_pop_T & _will_pop_T_1; // @[Scheduler.scala:215:{34,45,48}]
wire a_pop_1 = _requests_io_valid[0]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_1 = _requests_io_valid[7]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_12 = b_pop_1; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_1 = _requests_io_valid[14]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_9 = lowerMatches1[0]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_10 = c_pop_1 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_11 = ~c_pop_1; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_13 = ~b_pop_1; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_14 = ~a_pop_1; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_15 = _bypassMatches_T_12 ? _bypassMatches_T_13 : _bypassMatches_T_14; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_16 = _bypassMatches_T_10 ? _bypassMatches_T_11 : _bypassMatches_T_15; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_1 = _bypassMatches_T_9 & _bypassMatches_T_16; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_1 = a_pop_1 | b_pop_1; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_1 = _may_pop_T_1 | c_pop_1; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_1 = _bypass_T_1 & bypassMatches_1; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_1 = may_pop_1 | bypass_1; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_1 = _mshrs_0_io_schedule_bits_reload & _will_reload_T_1; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_prio_0 = bypass_1 ? _view__WIRE_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_prio_1 = ~bypass_1 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_prio_2 = bypass_1 ? _view__WIRE_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_control = bypass_1 ? _view__WIRE_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_opcode = bypass_1 ? _view__WIRE_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_param = bypass_1 ? _view__WIRE_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_size = bypass_1 ? _view__WIRE_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_source = bypass_1 ? _view__WIRE_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_tag = bypass_1 ? _view__WIRE_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_offset = bypass_1 ? _view__WIRE_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_put = bypass_1 ? _view__WIRE_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_0_io_allocate_bits_repeat_T = mshrs_0_io_allocate_bits_tag == _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_0_io_allocate_valid_T = sel & will_reload_1; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_2 = _requests_io_valid[1]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_2 = _requests_io_valid[8]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_20 = b_pop_2; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_2 = _requests_io_valid[15]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_17 = lowerMatches1[1]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_18 = c_pop_2 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_19 = ~c_pop_2; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_21 = ~b_pop_2; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_22 = ~a_pop_2; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_23 = _bypassMatches_T_20 ? _bypassMatches_T_21 : _bypassMatches_T_22; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_24 = _bypassMatches_T_18 ? _bypassMatches_T_19 : _bypassMatches_T_23; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_2 = _bypassMatches_T_17 & _bypassMatches_T_24; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_2 = a_pop_2 | b_pop_2; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_2 = _may_pop_T_2 | c_pop_2; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_2 = _bypass_T_2 & bypassMatches_2; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_2 = may_pop_2 | bypass_2; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_2 = _mshrs_1_io_schedule_bits_reload & _will_reload_T_2; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_1_prio_0 = bypass_2 ? _view__WIRE_1_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_1_prio_1 = ~bypass_2 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_1_prio_2 = bypass_2 ? _view__WIRE_1_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_1_control = bypass_2 ? _view__WIRE_1_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_1_opcode = bypass_2 ? _view__WIRE_1_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_1_param = bypass_2 ? _view__WIRE_1_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_1_size = bypass_2 ? _view__WIRE_1_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_1_source = bypass_2 ? _view__WIRE_1_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_1_tag = bypass_2 ? _view__WIRE_1_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_1_offset = bypass_2 ? _view__WIRE_1_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_1_put = bypass_2 ? _view__WIRE_1_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_1_io_allocate_bits_repeat_T = mshrs_1_io_allocate_bits_tag == _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_1_io_allocate_valid_T = sel_1 & will_reload_2; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_3 = _requests_io_valid[2]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_3 = _requests_io_valid[9]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_28 = b_pop_3; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_3 = _requests_io_valid[16]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_25 = lowerMatches1[2]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_26 = c_pop_3 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_27 = ~c_pop_3; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_29 = ~b_pop_3; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_30 = ~a_pop_3; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_31 = _bypassMatches_T_28 ? _bypassMatches_T_29 : _bypassMatches_T_30; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_32 = _bypassMatches_T_26 ? _bypassMatches_T_27 : _bypassMatches_T_31; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_3 = _bypassMatches_T_25 & _bypassMatches_T_32; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_3 = a_pop_3 | b_pop_3; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_3 = _may_pop_T_3 | c_pop_3; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_3 = _bypass_T_3 & bypassMatches_3; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_3 = may_pop_3 | bypass_3; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_3 = _mshrs_2_io_schedule_bits_reload & _will_reload_T_3; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_2_prio_0 = bypass_3 ? _view__WIRE_2_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_2_prio_1 = ~bypass_3 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_2_prio_2 = bypass_3 ? _view__WIRE_2_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_2_control = bypass_3 ? _view__WIRE_2_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_2_opcode = bypass_3 ? _view__WIRE_2_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_2_param = bypass_3 ? _view__WIRE_2_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_2_size = bypass_3 ? _view__WIRE_2_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_2_source = bypass_3 ? _view__WIRE_2_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_2_tag = bypass_3 ? _view__WIRE_2_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_2_offset = bypass_3 ? _view__WIRE_2_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_2_put = bypass_3 ? _view__WIRE_2_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_2_io_allocate_bits_repeat_T = mshrs_2_io_allocate_bits_tag == _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_2_io_allocate_valid_T = sel_2 & will_reload_3; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_4 = _requests_io_valid[3]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_4 = _requests_io_valid[10]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_36 = b_pop_4; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_4 = _requests_io_valid[17]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_33 = lowerMatches1[3]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_34 = c_pop_4 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_35 = ~c_pop_4; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_37 = ~b_pop_4; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_38 = ~a_pop_4; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_39 = _bypassMatches_T_36 ? _bypassMatches_T_37 : _bypassMatches_T_38; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_40 = _bypassMatches_T_34 ? _bypassMatches_T_35 : _bypassMatches_T_39; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_4 = _bypassMatches_T_33 & _bypassMatches_T_40; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_4 = a_pop_4 | b_pop_4; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_4 = _may_pop_T_4 | c_pop_4; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_4 = _bypass_T_4 & bypassMatches_4; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_4 = may_pop_4 | bypass_4; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_4 = _mshrs_3_io_schedule_bits_reload & _will_reload_T_4; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_3_prio_0 = bypass_4 ? _view__WIRE_3_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_3_prio_1 = ~bypass_4 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_3_prio_2 = bypass_4 ? _view__WIRE_3_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_3_control = bypass_4 ? _view__WIRE_3_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_3_opcode = bypass_4 ? _view__WIRE_3_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_3_param = bypass_4 ? _view__WIRE_3_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_3_size = bypass_4 ? _view__WIRE_3_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_3_source = bypass_4 ? _view__WIRE_3_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_3_tag = bypass_4 ? _view__WIRE_3_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_3_offset = bypass_4 ? _view__WIRE_3_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_3_put = bypass_4 ? _view__WIRE_3_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_3_io_allocate_bits_repeat_T = mshrs_3_io_allocate_bits_tag == _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_3_io_allocate_valid_T = sel_3 & will_reload_4; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_5 = _requests_io_valid[4]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_5 = _requests_io_valid[11]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_44 = b_pop_5; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_5 = _requests_io_valid[18]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_41 = lowerMatches1[4]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_42 = c_pop_5 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_43 = ~c_pop_5; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_45 = ~b_pop_5; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_46 = ~a_pop_5; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_47 = _bypassMatches_T_44 ? _bypassMatches_T_45 : _bypassMatches_T_46; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_48 = _bypassMatches_T_42 ? _bypassMatches_T_43 : _bypassMatches_T_47; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_5 = _bypassMatches_T_41 & _bypassMatches_T_48; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_5 = a_pop_5 | b_pop_5; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_5 = _may_pop_T_5 | c_pop_5; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_5 = _bypass_T_5 & bypassMatches_5; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_5 = may_pop_5 | bypass_5; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_5 = _mshrs_4_io_schedule_bits_reload & _will_reload_T_5; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_4_prio_0 = bypass_5 ? _view__WIRE_4_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_4_prio_1 = ~bypass_5 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_4_prio_2 = bypass_5 ? _view__WIRE_4_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_4_control = bypass_5 ? _view__WIRE_4_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_4_opcode = bypass_5 ? _view__WIRE_4_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_4_param = bypass_5 ? _view__WIRE_4_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_4_size = bypass_5 ? _view__WIRE_4_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_4_source = bypass_5 ? _view__WIRE_4_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_4_tag = bypass_5 ? _view__WIRE_4_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_4_offset = bypass_5 ? _view__WIRE_4_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_4_put = bypass_5 ? _view__WIRE_4_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_4_io_allocate_bits_repeat_T = mshrs_4_io_allocate_bits_tag == _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_4_io_allocate_valid_T = sel_4 & will_reload_5; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_6 = _requests_io_valid[5]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_6 = _requests_io_valid[12]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_52 = b_pop_6; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_6 = _requests_io_valid[19]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_49 = lowerMatches1[5]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_50 = c_pop_6 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_51 = ~c_pop_6; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_53 = ~b_pop_6; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_54 = ~a_pop_6; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_55 = _bypassMatches_T_52 ? _bypassMatches_T_53 : _bypassMatches_T_54; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_56 = _bypassMatches_T_50 ? _bypassMatches_T_51 : _bypassMatches_T_55; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_6 = _bypassMatches_T_49 & _bypassMatches_T_56; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_6 = a_pop_6 | b_pop_6; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_6 = _may_pop_T_6 | c_pop_6; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_6 = _bypass_T_6 & bypassMatches_6; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_6 = may_pop_6 | bypass_6; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_6 = _mshrs_5_io_schedule_bits_reload & _will_reload_T_6; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_5_prio_0 = bypass_6 ? _view__WIRE_5_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_5_prio_1 = ~bypass_6 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_5_prio_2 = bypass_6 ? _view__WIRE_5_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_5_control = bypass_6 ? _view__WIRE_5_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_5_opcode = bypass_6 ? _view__WIRE_5_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_5_param = bypass_6 ? _view__WIRE_5_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_5_size = bypass_6 ? _view__WIRE_5_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_5_source = bypass_6 ? _view__WIRE_5_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_5_tag = bypass_6 ? _view__WIRE_5_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_5_offset = bypass_6 ? _view__WIRE_5_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_5_put = bypass_6 ? _view__WIRE_5_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_5_io_allocate_bits_repeat_T = mshrs_5_io_allocate_bits_tag == _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :287:131, :289:74]
wire _mshrs_5_io_allocate_valid_T = sel_5 & will_reload_6; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_7 = _requests_io_valid[6]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_7 = _requests_io_valid[13]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_60 = b_pop_7; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_7 = _requests_io_valid[20]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_57 = lowerMatches1[6]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_58 = c_pop_7 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_59 = ~c_pop_7; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_61 = ~b_pop_7; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_62 = ~a_pop_7; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_63 = _bypassMatches_T_60 ? _bypassMatches_T_61 : _bypassMatches_T_62; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_64 = _bypassMatches_T_58 ? _bypassMatches_T_59 : _bypassMatches_T_63; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_7 = _bypassMatches_T_57 & _bypassMatches_T_64; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_7 = a_pop_7 | b_pop_7; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_7 = _may_pop_T_7 | c_pop_7; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_7 = _bypass_T_7 & bypassMatches_7; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_7 = may_pop_7 | bypass_7; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_7 = _mshrs_6_io_schedule_bits_reload & _will_reload_T_7; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_6_prio_0 = bypass_7 ? _view__WIRE_6_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_6_prio_1 = ~bypass_7 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_6_prio_2 = bypass_7 ? _view__WIRE_6_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_6_control = bypass_7 ? _view__WIRE_6_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_6_opcode = bypass_7 ? _view__WIRE_6_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_6_param = bypass_7 ? _view__WIRE_6_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_6_size = bypass_7 ? _view__WIRE_6_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_6_source = bypass_7 ? _view__WIRE_6_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_6_tag = bypass_7 ? _view__WIRE_6_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_6_offset = bypass_7 ? _view__WIRE_6_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_6_put = bypass_7 ? _view__WIRE_6_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_6_io_allocate_bits_repeat_T = mshrs_6_io_allocate_bits_tag == _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :295:103, :297:73]
wire _mshrs_6_io_allocate_valid_T = sel_6 & will_reload_7; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire [20:0] _prio_requests_T = ~_requests_io_valid; // @[Scheduler.scala:70:24, :240:25]
wire [13:0] _prio_requests_T_1 = _requests_io_valid[20:7]; // @[Scheduler.scala:70:24, :240:65]
wire [20:0] _prio_requests_T_2 = {_prio_requests_T[20:14], _prio_requests_T[13:0] | _prio_requests_T_1}; // @[Scheduler.scala:240:{25,44,65}]
wire [6:0] _prio_requests_T_3 = _requests_io_valid[20:14]; // @[Scheduler.scala:70:24, :240:103]
wire [20:0] _prio_requests_T_4 = {_prio_requests_T_2[20:7], _prio_requests_T_2[6:0] | _prio_requests_T_3}; // @[Scheduler.scala:240:{44,82,103}]
wire [20:0] prio_requests = ~_prio_requests_T_4; // @[Scheduler.scala:240:{23,82}]
wire [20:0] _pop_index_T = {pop_index_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :241:31]
wire [20:0] _pop_index_T_1 = _pop_index_T & prio_requests; // @[Scheduler.scala:240:23, :241:{31,77}]
wire [4:0] pop_index_hi_1 = _pop_index_T_1[20:16]; // @[OneHot.scala:30:18]
wire [15:0] pop_index_lo = _pop_index_T_1[15:0]; // @[OneHot.scala:31:18]
wire _pop_index_T_2 = |pop_index_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _pop_index_T_3 = {11'h0, pop_index_hi_1} | pop_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] pop_index_hi_2 = _pop_index_T_3[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] pop_index_lo_1 = _pop_index_T_3[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_4 = |pop_index_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _pop_index_T_5 = pop_index_hi_2 | pop_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] pop_index_hi_3 = _pop_index_T_5[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] pop_index_lo_2 = _pop_index_T_5[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_6 = |pop_index_hi_3; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _pop_index_T_7 = pop_index_hi_3 | pop_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] pop_index_hi_4 = _pop_index_T_7[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] pop_index_lo_3 = _pop_index_T_7[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_8 = |pop_index_hi_4; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _pop_index_T_9 = pop_index_hi_4 | pop_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _pop_index_T_10 = _pop_index_T_9[1]; // @[OneHot.scala:32:28]
wire [1:0] _pop_index_T_11 = {_pop_index_T_8, _pop_index_T_10}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _pop_index_T_12 = {_pop_index_T_6, _pop_index_T_11}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _pop_index_T_13 = {_pop_index_T_4, _pop_index_T_12}; // @[OneHot.scala:32:{10,14}]
wire [4:0] pop_index = {_pop_index_T_2, _pop_index_T_13}; // @[OneHot.scala:32:{10,14}]
wire lb_tag_mismatch = scheduleTag != _requests_io_data_tag; // @[Mux.scala:30:73]
wire mshr_uses_directory_assuming_no_bypass = _mshr_uses_directory_assuming_no_bypass_T & lb_tag_mismatch; // @[Scheduler.scala:246:37, :247:{64,75}]
wire mshr_uses_directory_for_lb = will_pop & lb_tag_mismatch; // @[Scheduler.scala:215:45, :246:37, :248:45]
wire [12:0] _mshr_uses_directory_T = bypass ? request_bits_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :163:21, :213:39, :249:63]
wire _mshr_uses_directory_T_1 = scheduleTag != _mshr_uses_directory_T; // @[Mux.scala:30:73]
wire mshr_uses_directory = will_reload & _mshr_uses_directory_T_1; // @[Scheduler.scala:214:37, :249:{41,56}]
wire [1:0] mshr_validOH_lo_hi = {_mshrs_2_io_status_valid, _mshrs_1_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_lo = {mshr_validOH_lo_hi, _mshrs_0_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [1:0] mshr_validOH_hi_lo = {_mshrs_4_io_status_valid, _mshrs_3_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [1:0] mshr_validOH_hi_hi = {_mshrs_6_io_status_valid, _mshrs_5_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [3:0] mshr_validOH_hi = {mshr_validOH_hi_hi, mshr_validOH_hi_lo}; // @[Scheduler.scala:252:25]
wire [6:0] mshr_validOH = {mshr_validOH_hi, mshr_validOH_lo}; // @[Scheduler.scala:252:25]
wire [6:0] _mshr_free_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20]
wire [6:0] _mshr_free_T_1 = _mshr_free_T & prioFilter; // @[Scheduler.scala:182:23, :253:{20,34}]
wire mshr_free = |_mshr_free_T_1; // @[Scheduler.scala:253:{34,48}]
wire bypassQueue = schedule_reload & bypassMatches; // @[Mux.scala:30:73]
wire _request_alloc_cases_T = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16]
wire _request_alloc_cases_T_1 = alloc & _request_alloc_cases_T; // @[Scheduler.scala:173:15, :258:{13,16}]
wire _request_alloc_cases_T_2 = _request_alloc_cases_T_1 & mshr_free; // @[Scheduler.scala:253:48, :258:{13,56}]
wire _request_alloc_cases_T_9 = _request_alloc_cases_T_2; // @[Scheduler.scala:258:{56,70}]
wire _request_alloc_cases_T_3 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :259:16]
wire _request_alloc_cases_T_5 = ~_mshrs_5_io_status_valid; // @[Scheduler.scala:71:46, :259:59]
wire _request_alloc_cases_T_7 = ~_mshrs_6_io_status_valid; // @[Scheduler.scala:71:46, :259:87]
wire _request_alloc_cases_T_10 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :260:16]
wire _request_alloc_cases_T_11 = nestC & _request_alloc_cases_T_10; // @[Scheduler.scala:180:70, :260:{13,16}]
wire _request_alloc_cases_T_12 = ~_mshrs_6_io_status_valid; // @[Scheduler.scala:71:46, :259:87, :260:59]
wire _request_alloc_cases_T_13 = _request_alloc_cases_T_11 & _request_alloc_cases_T_12; // @[Scheduler.scala:260:{13,56,59}]
wire request_alloc_cases = _request_alloc_cases_T_9 | _request_alloc_cases_T_13; // @[Scheduler.scala:258:70, :259:112, :260:56]
wire _request_ready_T = bypassQueue | _requests_io_push_ready; // @[Scheduler.scala:70:24, :256:37, :261:66]
wire _request_ready_T_1 = queue & _request_ready_T; // @[Scheduler.scala:185:63, :261:{50,66}]
assign _request_ready_T_2 = request_alloc_cases | _request_ready_T_1; // @[Scheduler.scala:259:112, :261:{40,50}]
assign request_ready = _request_ready_T_2; // @[Scheduler.scala:163:21, :261:40]
wire alloc_uses_directory = request_valid & request_alloc_cases; // @[Scheduler.scala:163:21, :259:112, :262:44]
wire _directory_io_read_valid_T = mshr_uses_directory | alloc_uses_directory; // @[Scheduler.scala:249:41, :262:44, :265:50]
wire [9:0] _directory_io_read_bits_set_T = mshr_uses_directory_for_lb ? scheduleSet : request_bits_set; // @[Mux.scala:30:73]
wire [12:0] _directory_io_read_bits_tag_T = mshr_uses_directory_for_lb ? _requests_io_data_tag : request_bits_tag; // @[Scheduler.scala:70:24, :163:21, :248:45, :267:36]
wire _requests_io_push_valid_T_1 = ~bypassQueue; // @[Scheduler.scala:256:37, :270:55]
wire _requests_io_push_valid_T_2 = _requests_io_push_valid_T & _requests_io_push_valid_T_1; // @[Scheduler.scala:270:{43,52,55}]
wire [2:0] requests_io_push_bits_index_hi = _requests_io_push_bits_index_T[6:4]; // @[OneHot.scala:30:18]
wire [3:0] requests_io_push_bits_index_lo = _requests_io_push_bits_index_T[3:0]; // @[OneHot.scala:31:18]
wire _requests_io_push_bits_index_T_1 = |requests_io_push_bits_index_hi; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _requests_io_push_bits_index_T_2 = {1'h0, requests_io_push_bits_index_hi} | requests_io_push_bits_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] requests_io_push_bits_index_hi_1 = _requests_io_push_bits_index_T_2[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] requests_io_push_bits_index_lo_1 = _requests_io_push_bits_index_T_2[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_3 = |requests_io_push_bits_index_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _requests_io_push_bits_index_T_4 = requests_io_push_bits_index_hi_1 | requests_io_push_bits_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _requests_io_push_bits_index_T_5 = _requests_io_push_bits_index_T_4[1]; // @[OneHot.scala:32:28]
wire [1:0] _requests_io_push_bits_index_T_6 = {_requests_io_push_bits_index_T_3, _requests_io_push_bits_index_T_5}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _requests_io_push_bits_index_T_7 = {_requests_io_push_bits_index_T_1, _requests_io_push_bits_index_T_6}; // @[OneHot.scala:32:{10,14}]
wire [13:0] _requests_io_push_bits_index_T_8 = {lowerMatches1, 7'h0}; // @[Scheduler.scala:200:8, :275:30]
wire [5:0] requests_io_push_bits_index_hi_2 = _requests_io_push_bits_index_T_8[13:8]; // @[OneHot.scala:30:18]
wire [7:0] requests_io_push_bits_index_lo_2 = _requests_io_push_bits_index_T_8[7:0]; // @[OneHot.scala:31:18]
wire _requests_io_push_bits_index_T_9 = |requests_io_push_bits_index_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _requests_io_push_bits_index_T_10 = {2'h0, requests_io_push_bits_index_hi_2} | requests_io_push_bits_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] requests_io_push_bits_index_hi_3 = _requests_io_push_bits_index_T_10[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] requests_io_push_bits_index_lo_3 = _requests_io_push_bits_index_T_10[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_11 = |requests_io_push_bits_index_hi_3; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _requests_io_push_bits_index_T_12 = requests_io_push_bits_index_hi_3 | requests_io_push_bits_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] requests_io_push_bits_index_hi_4 = _requests_io_push_bits_index_T_12[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] requests_io_push_bits_index_lo_4 = _requests_io_push_bits_index_T_12[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_13 = |requests_io_push_bits_index_hi_4; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _requests_io_push_bits_index_T_14 = requests_io_push_bits_index_hi_4 | requests_io_push_bits_index_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _requests_io_push_bits_index_T_15 = _requests_io_push_bits_index_T_14[1]; // @[OneHot.scala:32:28]
wire [1:0] _requests_io_push_bits_index_T_16 = {_requests_io_push_bits_index_T_13, _requests_io_push_bits_index_T_15}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _requests_io_push_bits_index_T_17 = {_requests_io_push_bits_index_T_11, _requests_io_push_bits_index_T_16}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_18 = {_requests_io_push_bits_index_T_9, _requests_io_push_bits_index_T_17}; // @[OneHot.scala:32:{10,14}]
wire [20:0] _requests_io_push_bits_index_T_19 = {lowerMatches1, 14'h0}; // @[Scheduler.scala:200:8, :276:30]
wire [4:0] requests_io_push_bits_index_hi_5 = _requests_io_push_bits_index_T_19[20:16]; // @[OneHot.scala:30:18]
wire [15:0] requests_io_push_bits_index_lo_5 = _requests_io_push_bits_index_T_19[15:0]; // @[OneHot.scala:31:18]
wire _requests_io_push_bits_index_T_20 = |requests_io_push_bits_index_hi_5; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _requests_io_push_bits_index_T_21 = {11'h0, requests_io_push_bits_index_hi_5} | requests_io_push_bits_index_lo_5; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] requests_io_push_bits_index_hi_6 = _requests_io_push_bits_index_T_21[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] requests_io_push_bits_index_lo_6 = _requests_io_push_bits_index_T_21[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_22 = |requests_io_push_bits_index_hi_6; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _requests_io_push_bits_index_T_23 = requests_io_push_bits_index_hi_6 | requests_io_push_bits_index_lo_6; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] requests_io_push_bits_index_hi_7 = _requests_io_push_bits_index_T_23[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] requests_io_push_bits_index_lo_7 = _requests_io_push_bits_index_T_23[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_24 = |requests_io_push_bits_index_hi_7; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _requests_io_push_bits_index_T_25 = requests_io_push_bits_index_hi_7 | requests_io_push_bits_index_lo_7; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] requests_io_push_bits_index_hi_8 = _requests_io_push_bits_index_T_25[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] requests_io_push_bits_index_lo_8 = _requests_io_push_bits_index_T_25[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_26 = |requests_io_push_bits_index_hi_8; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _requests_io_push_bits_index_T_27 = requests_io_push_bits_index_hi_8 | requests_io_push_bits_index_lo_8; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _requests_io_push_bits_index_T_28 = _requests_io_push_bits_index_T_27[1]; // @[OneHot.scala:32:28]
wire [1:0] _requests_io_push_bits_index_T_29 = {_requests_io_push_bits_index_T_26, _requests_io_push_bits_index_T_28}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _requests_io_push_bits_index_T_30 = {_requests_io_push_bits_index_T_24, _requests_io_push_bits_index_T_29}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_31 = {_requests_io_push_bits_index_T_22, _requests_io_push_bits_index_T_30}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _requests_io_push_bits_index_T_32 = {_requests_io_push_bits_index_T_20, _requests_io_push_bits_index_T_31}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _requests_io_push_bits_index_T_33 = request_bits_prio_0 ? _requests_io_push_bits_index_T_7 : 3'h0; // @[OneHot.scala:32:10]
wire [4:0] _requests_io_push_bits_index_T_35 = request_bits_prio_2 ? _requests_io_push_bits_index_T_32 : 5'h0; // @[OneHot.scala:32:10]
wire [3:0] _requests_io_push_bits_index_T_36 = {1'h0, _requests_io_push_bits_index_T_33}; // @[Mux.scala:30:73]
wire [4:0] _requests_io_push_bits_index_T_37 = {1'h0, _requests_io_push_bits_index_T_36} | _requests_io_push_bits_index_T_35; // @[Mux.scala:30:73]
wire [4:0] _requests_io_push_bits_index_WIRE = _requests_io_push_bits_index_T_37; // @[Mux.scala:30:73]
wire [6:0] _mshr_insertOH_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:32]
wire [7:0] _mshr_insertOH_T_1 = {_mshr_insertOH_T, 1'h0}; // @[package.scala:253:48]
wire [6:0] _mshr_insertOH_T_2 = _mshr_insertOH_T_1[6:0]; // @[package.scala:253:{48,53}]
wire [6:0] _mshr_insertOH_T_3 = _mshr_insertOH_T | _mshr_insertOH_T_2; // @[package.scala:253:{43,53}]
wire [8:0] _mshr_insertOH_T_4 = {_mshr_insertOH_T_3, 2'h0}; // @[package.scala:253:{43,48}]
wire [6:0] _mshr_insertOH_T_5 = _mshr_insertOH_T_4[6:0]; // @[package.scala:253:{48,53}]
wire [6:0] _mshr_insertOH_T_6 = _mshr_insertOH_T_3 | _mshr_insertOH_T_5; // @[package.scala:253:{43,53}]
wire [10:0] _mshr_insertOH_T_7 = {_mshr_insertOH_T_6, 4'h0}; // @[package.scala:253:{43,48}]
wire [6:0] _mshr_insertOH_T_8 = _mshr_insertOH_T_7[6:0]; // @[package.scala:253:{48,53}]
wire [6:0] _mshr_insertOH_T_9 = _mshr_insertOH_T_6 | _mshr_insertOH_T_8; // @[package.scala:253:{43,53}]
wire [6:0] _mshr_insertOH_T_10 = _mshr_insertOH_T_9; // @[package.scala:253:43, :254:17]
wire [7:0] _mshr_insertOH_T_11 = {_mshr_insertOH_T_10, 1'h0}; // @[package.scala:254:17]
wire [7:0] _mshr_insertOH_T_12 = ~_mshr_insertOH_T_11; // @[Scheduler.scala:278:{23,47}]
wire [6:0] _mshr_insertOH_T_13 = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:55]
wire [7:0] _mshr_insertOH_T_14 = {1'h0, _mshr_insertOH_T_12[6:0] & _mshr_insertOH_T_13}; // @[Scheduler.scala:278:{23,53,55}]
wire [7:0] mshr_insertOH = {1'h0, _mshr_insertOH_T_14[6:0] & prioFilter}; // @[Scheduler.scala:182:23, :278:{53,69}]
wire _T_46 = request_valid & alloc; // @[Scheduler.scala:163:21, :173:15, :280:25]
wire _T_25 = _T_46 & mshr_insertOH[0] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_0_io_allocate_bits_tag = _T_25 ? request_bits_tag : _view__T_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_29 = _T_46 & mshr_insertOH[1] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_1_io_allocate_bits_tag = _T_29 ? request_bits_tag : _view__T_1_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_33 = _T_46 & mshr_insertOH[2] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_2_io_allocate_bits_tag = _T_33 ? request_bits_tag : _view__T_2_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_37 = _T_46 & mshr_insertOH[3] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_3_io_allocate_bits_tag = _T_37 ? request_bits_tag : _view__T_3_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_41 = _T_46 & mshr_insertOH[4] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_4_io_allocate_bits_tag = _T_41 ? request_bits_tag : _view__T_4_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_45 = _T_46 & mshr_insertOH[5] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_5_io_allocate_bits_tag = _T_45 ? request_bits_tag : _view__T_5_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70, :287:131, :289:74]
wire _T_65 = request_valid & nestC & ~_mshrs_6_io_status_valid & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:71:46, :163:21, :180:70, :193:33, :247:75, :258:16, :259:87, :295:{32,59}]
wire _GEN_3 = _T_65 | _T_46 & mshr_insertOH[6] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:193:33, :236:25, :247:75, :258:16, :278:69, :279:18, :280:{25,34,39,83}, :281:27, :295:{32,59,103}, :296:30]
assign mshrs_6_io_allocate_bits_tag = _GEN_3 ? request_bits_tag : _view__T_6_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :236:25, :280:83, :281:27, :282:70, :295:103, :296:30, :297:73]
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Generate the Verilog code corresponding to the following Chisel files.
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File UserYanker.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
import chisel3.util.{Queue, QueueIO, UIntToOH}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
import freechips.rocketchip.util.BundleMap
/** This adapter prunes all user bit fields of the echo type from request messages,
* storing them in queues and echoing them back when matching response messages are received.
*
* It also optionally rate limits the number of transactions that can be in flight simultaneously
* per FIFO domain / A[W|R]ID.
*
* @param capMaxFlight is an optional maximum number of transactions that can be in flight per A[W|R]ID.
*/
class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) extends LazyModule
{
val node = AXI4AdapterNode(
masterFn = { mp => mp.copy(
masters = mp.masters.map { m => m.copy(
maxFlight = (m.maxFlight, capMaxFlight) match {
case (Some(x), Some(y)) => Some(x min y)
case (Some(x), None) => Some(x)
case (None, Some(y)) => Some(y)
case (None, None) => None })},
echoFields = Nil)},
slaveFn = { sp => sp })
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
// Which fields are we stripping?
val echoFields = edgeIn.master.echoFields
val need_bypass = edgeOut.slave.minLatency < 1
edgeOut.master.masters.foreach { m =>
require (m.maxFlight.isDefined, "UserYanker needs a flight cap on each ID")
}
def queue(id: Int) = {
val depth = edgeOut.master.masters.find(_.id.contains(id)).flatMap(_.maxFlight).getOrElse(0)
if (depth == 0) {
Wire(new QueueIO(BundleMap(echoFields), 1)) // unused ID => undefined value
} else {
Module(new Queue(BundleMap(echoFields), depth, flow=need_bypass)).io
}
}
val rqueues = Seq.tabulate(edgeIn.master.endId) { i => queue(i) }
val wqueues = Seq.tabulate(edgeIn.master.endId) { i => queue(i) }
val arid = in.ar.bits.id
val ar_ready = VecInit(rqueues.map(_.enq.ready))(arid)
in .ar.ready := out.ar.ready && ar_ready
out.ar.valid := in .ar.valid && ar_ready
Connectable.waiveUnmatched(out.ar.bits, in.ar.bits) match {
case (lhs, rhs) => lhs :<= rhs
}
val rid = out.r.bits.id
val r_valid = VecInit(rqueues.map(_.deq.valid))(rid)
val r_bits = VecInit(rqueues.map(_.deq.bits))(rid)
assert (!out.r.valid || r_valid) // Q must be ready faster than the response
Connectable.waiveUnmatched(in.r, out.r) match {
case (lhs, rhs) => lhs :<>= rhs
}
in.r.bits.echo :<= r_bits
val arsel = UIntToOH(arid, edgeIn.master.endId).asBools
val rsel = UIntToOH(rid, edgeIn.master.endId).asBools
(rqueues zip (arsel zip rsel)) foreach { case (q, (ar, r)) =>
q.deq.ready := out.r .valid && in .r .ready && r && out.r.bits.last
q.deq.valid := DontCare
q.deq.bits := DontCare
q.enq.valid := in .ar.valid && out.ar.ready && ar
q.enq.ready := DontCare
q.enq.bits :<>= in.ar.bits.echo
q.count := DontCare
}
val awid = in.aw.bits.id
val aw_ready = VecInit(wqueues.map(_.enq.ready))(awid)
in .aw.ready := out.aw.ready && aw_ready
out.aw.valid := in .aw.valid && aw_ready
Connectable.waiveUnmatched(out.aw.bits, in.aw.bits) match {
case (lhs, rhs) => lhs :<>= rhs
}
val bid = out.b.bits.id
val b_valid = VecInit(wqueues.map(_.deq.valid))(bid)
val b_bits = VecInit(wqueues.map(_.deq.bits))(bid)
assert (!out.b.valid || b_valid) // Q must be ready faster than the response
Connectable.waiveUnmatched(in.b, out.b) match {
case (lhs, rhs) => lhs :<>= rhs
}
in.b.bits.echo :<>= b_bits
val awsel = UIntToOH(awid, edgeIn.master.endId).asBools
val bsel = UIntToOH(bid, edgeIn.master.endId).asBools
(wqueues zip (awsel zip bsel)) foreach { case (q, (aw, b)) =>
q.deq.ready := out.b .valid && in .b .ready && b
q.deq.valid := DontCare
q.deq.bits := DontCare
q.enq.valid := in .aw.valid && out.aw.ready && aw
q.enq.ready := DontCare
q.enq.bits :<>= in.aw.bits.echo
q.count := DontCare
}
out.w :<>= in.w
}
}
}
object AXI4UserYanker
{
def apply(capMaxFlight: Option[Int] = None)(implicit p: Parameters): AXI4Node =
{
val axi4yank = LazyModule(new AXI4UserYanker(capMaxFlight))
axi4yank.node
}
}
|
module AXI4UserYanker( // @[UserYanker.scala:36:9]
input clock, // @[UserYanker.scala:36:9]
input reset, // @[UserYanker.scala:36:9]
output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_aw_bits_len, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_aw_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_aw_bits_burst, // @[LazyModuleImp.scala:107:25]
input auto_in_aw_bits_lock, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_cache, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_aw_bits_prot, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_qos, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_in_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_aw_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25]
output auto_in_w_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_w_valid, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25]
input auto_in_w_bits_last, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_resp, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_in_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25]
output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_ar_bits_len, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_ar_bits_burst, // @[LazyModuleImp.scala:107:25]
input auto_in_ar_bits_lock, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_cache, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_ar_bits_prot, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_qos, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_in_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_ar_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25]
input auto_in_r_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_r_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_r_bits_resp, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_in_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_r_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25]
output auto_in_r_bits_last, // @[LazyModuleImp.scala:107:25]
input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25]
input auto_out_w_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_w_valid, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25]
output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25]
input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25]
output auto_out_r_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_r_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25]
input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25]
);
wire _Queue3_BundleMap_11_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_11_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue3_BundleMap_11_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue3_BundleMap_11_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue3_BundleMap_11_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_10_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_10_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue3_BundleMap_10_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue3_BundleMap_10_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue3_BundleMap_10_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_9_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_9_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue3_BundleMap_9_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue3_BundleMap_9_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue3_BundleMap_9_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_8_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_8_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue3_BundleMap_8_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue3_BundleMap_8_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue3_BundleMap_8_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_7_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_7_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue3_BundleMap_7_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue3_BundleMap_7_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue3_BundleMap_7_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_6_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_6_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue3_BundleMap_6_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue3_BundleMap_6_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue3_BundleMap_6_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_19_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_19_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue4_BundleMap_19_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue4_BundleMap_19_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue4_BundleMap_19_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_18_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_18_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue4_BundleMap_18_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue4_BundleMap_18_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue4_BundleMap_18_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_17_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_17_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue4_BundleMap_17_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue4_BundleMap_17_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue4_BundleMap_17_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_16_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_16_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue4_BundleMap_16_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue4_BundleMap_16_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue4_BundleMap_16_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_15_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_15_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue4_BundleMap_15_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue4_BundleMap_15_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue4_BundleMap_15_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_14_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_14_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue4_BundleMap_14_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue4_BundleMap_14_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue4_BundleMap_14_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_13_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_13_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue4_BundleMap_13_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue4_BundleMap_13_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue4_BundleMap_13_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_12_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_12_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue4_BundleMap_12_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue4_BundleMap_12_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue4_BundleMap_12_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_11_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_11_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue4_BundleMap_11_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue4_BundleMap_11_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue4_BundleMap_11_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_10_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_10_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue4_BundleMap_10_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue4_BundleMap_10_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue4_BundleMap_10_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_5_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_5_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue3_BundleMap_5_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue3_BundleMap_5_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue3_BundleMap_5_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_4_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_4_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue3_BundleMap_4_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue3_BundleMap_4_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue3_BundleMap_4_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_3_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_3_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue3_BundleMap_3_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue3_BundleMap_3_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue3_BundleMap_3_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_2_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_2_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue3_BundleMap_2_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue3_BundleMap_2_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue3_BundleMap_2_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_1_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_1_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue3_BundleMap_1_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue3_BundleMap_1_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue3_BundleMap_1_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue3_BundleMap_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue3_BundleMap_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue3_BundleMap_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue3_BundleMap_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_9_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_9_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue4_BundleMap_9_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue4_BundleMap_9_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue4_BundleMap_9_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_8_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_8_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue4_BundleMap_8_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue4_BundleMap_8_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue4_BundleMap_8_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_7_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_7_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue4_BundleMap_7_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue4_BundleMap_7_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue4_BundleMap_7_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_6_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_6_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue4_BundleMap_6_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue4_BundleMap_6_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue4_BundleMap_6_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_5_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_5_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue4_BundleMap_5_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue4_BundleMap_5_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue4_BundleMap_5_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_4_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_4_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue4_BundleMap_4_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue4_BundleMap_4_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue4_BundleMap_4_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_3_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_3_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue4_BundleMap_3_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue4_BundleMap_3_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue4_BundleMap_3_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_2_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_2_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue4_BundleMap_2_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue4_BundleMap_2_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue4_BundleMap_2_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_1_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_1_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue4_BundleMap_1_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue4_BundleMap_1_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue4_BundleMap_1_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_io_enq_ready; // @[UserYanker.scala:51:17]
wire _Queue4_BundleMap_io_deq_valid; // @[UserYanker.scala:51:17]
wire [3:0] _Queue4_BundleMap_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17]
wire [5:0] _Queue4_BundleMap_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17]
wire [1:0] _Queue4_BundleMap_io_deq_bits_extra_id; // @[UserYanker.scala:51:17]
wire [15:0] _GEN = {{_Queue3_BundleMap_5_io_enq_ready}, {_Queue3_BundleMap_4_io_enq_ready}, {_Queue3_BundleMap_3_io_enq_ready}, {_Queue3_BundleMap_2_io_enq_ready}, {_Queue3_BundleMap_1_io_enq_ready}, {_Queue3_BundleMap_io_enq_ready}, {_Queue4_BundleMap_9_io_enq_ready}, {_Queue4_BundleMap_8_io_enq_ready}, {_Queue4_BundleMap_7_io_enq_ready}, {_Queue4_BundleMap_6_io_enq_ready}, {_Queue4_BundleMap_5_io_enq_ready}, {_Queue4_BundleMap_4_io_enq_ready}, {_Queue4_BundleMap_3_io_enq_ready}, {_Queue4_BundleMap_2_io_enq_ready}, {_Queue4_BundleMap_1_io_enq_ready}, {_Queue4_BundleMap_io_enq_ready}}; // @[UserYanker.scala:51:17, :60:36]
wire [15:0][3:0] _GEN_0 = {{_Queue3_BundleMap_5_io_deq_bits_tl_state_size}, {_Queue3_BundleMap_4_io_deq_bits_tl_state_size}, {_Queue3_BundleMap_3_io_deq_bits_tl_state_size}, {_Queue3_BundleMap_2_io_deq_bits_tl_state_size}, {_Queue3_BundleMap_1_io_deq_bits_tl_state_size}, {_Queue3_BundleMap_io_deq_bits_tl_state_size}, {_Queue4_BundleMap_9_io_deq_bits_tl_state_size}, {_Queue4_BundleMap_8_io_deq_bits_tl_state_size}, {_Queue4_BundleMap_7_io_deq_bits_tl_state_size}, {_Queue4_BundleMap_6_io_deq_bits_tl_state_size}, {_Queue4_BundleMap_5_io_deq_bits_tl_state_size}, {_Queue4_BundleMap_4_io_deq_bits_tl_state_size}, {_Queue4_BundleMap_3_io_deq_bits_tl_state_size}, {_Queue4_BundleMap_2_io_deq_bits_tl_state_size}, {_Queue4_BundleMap_1_io_deq_bits_tl_state_size}, {_Queue4_BundleMap_io_deq_bits_tl_state_size}}; // @[UserYanker.scala:51:17, :73:22]
wire [15:0][5:0] _GEN_1 = {{_Queue3_BundleMap_5_io_deq_bits_tl_state_source}, {_Queue3_BundleMap_4_io_deq_bits_tl_state_source}, {_Queue3_BundleMap_3_io_deq_bits_tl_state_source}, {_Queue3_BundleMap_2_io_deq_bits_tl_state_source}, {_Queue3_BundleMap_1_io_deq_bits_tl_state_source}, {_Queue3_BundleMap_io_deq_bits_tl_state_source}, {_Queue4_BundleMap_9_io_deq_bits_tl_state_source}, {_Queue4_BundleMap_8_io_deq_bits_tl_state_source}, {_Queue4_BundleMap_7_io_deq_bits_tl_state_source}, {_Queue4_BundleMap_6_io_deq_bits_tl_state_source}, {_Queue4_BundleMap_5_io_deq_bits_tl_state_source}, {_Queue4_BundleMap_4_io_deq_bits_tl_state_source}, {_Queue4_BundleMap_3_io_deq_bits_tl_state_source}, {_Queue4_BundleMap_2_io_deq_bits_tl_state_source}, {_Queue4_BundleMap_1_io_deq_bits_tl_state_source}, {_Queue4_BundleMap_io_deq_bits_tl_state_source}}; // @[UserYanker.scala:51:17, :73:22]
wire [15:0][1:0] _GEN_2 = {{_Queue3_BundleMap_5_io_deq_bits_extra_id}, {_Queue3_BundleMap_4_io_deq_bits_extra_id}, {_Queue3_BundleMap_3_io_deq_bits_extra_id}, {_Queue3_BundleMap_2_io_deq_bits_extra_id}, {_Queue3_BundleMap_1_io_deq_bits_extra_id}, {_Queue3_BundleMap_io_deq_bits_extra_id}, {_Queue4_BundleMap_9_io_deq_bits_extra_id}, {_Queue4_BundleMap_8_io_deq_bits_extra_id}, {_Queue4_BundleMap_7_io_deq_bits_extra_id}, {_Queue4_BundleMap_6_io_deq_bits_extra_id}, {_Queue4_BundleMap_5_io_deq_bits_extra_id}, {_Queue4_BundleMap_4_io_deq_bits_extra_id}, {_Queue4_BundleMap_3_io_deq_bits_extra_id}, {_Queue4_BundleMap_2_io_deq_bits_extra_id}, {_Queue4_BundleMap_1_io_deq_bits_extra_id}, {_Queue4_BundleMap_io_deq_bits_extra_id}}; // @[UserYanker.scala:51:17, :73:22]
wire _GEN_3 = auto_out_r_valid & auto_in_r_ready; // @[UserYanker.scala:78:37]
wire _GEN_4 = auto_in_ar_valid & auto_out_ar_ready; // @[UserYanker.scala:81:37]
wire [15:0] _GEN_5 = {{_Queue3_BundleMap_11_io_enq_ready}, {_Queue3_BundleMap_10_io_enq_ready}, {_Queue3_BundleMap_9_io_enq_ready}, {_Queue3_BundleMap_8_io_enq_ready}, {_Queue3_BundleMap_7_io_enq_ready}, {_Queue3_BundleMap_6_io_enq_ready}, {_Queue4_BundleMap_19_io_enq_ready}, {_Queue4_BundleMap_18_io_enq_ready}, {_Queue4_BundleMap_17_io_enq_ready}, {_Queue4_BundleMap_16_io_enq_ready}, {_Queue4_BundleMap_15_io_enq_ready}, {_Queue4_BundleMap_14_io_enq_ready}, {_Queue4_BundleMap_13_io_enq_ready}, {_Queue4_BundleMap_12_io_enq_ready}, {_Queue4_BundleMap_11_io_enq_ready}, {_Queue4_BundleMap_10_io_enq_ready}}; // @[UserYanker.scala:51:17, :89:36]
|
Generate the Verilog code corresponding to the following Chisel files.
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File NoC.scala:
package constellation.noc
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody}
import freechips.rocketchip.util.ElaborationArtefacts
import freechips.rocketchip.prci._
import constellation.router._
import constellation.channel._
import constellation.routing.{RoutingRelation, ChannelRoutingInfo}
import constellation.topology.{PhysicalTopology, UnidirectionalLine}
class NoCTerminalIO(
val ingressParams: Seq[IngressChannelParams],
val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle {
val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) })
val egress = MixedVec(egressParams.map { u => new EgressChannel(u) })
}
class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule {
override def shouldBeInlined = nocParams.inlineNoC
val internalParams = InternalNoCParams(nocParams)
val allChannelParams = internalParams.channelParams
val allIngressParams = internalParams.ingressParams
val allEgressParams = internalParams.egressParams
val allRouterParams = internalParams.routerParams
val iP = p.alterPartial({ case InternalNoCKey => internalParams })
val nNodes = nocParams.topology.nNodes
val nocName = nocParams.nocName
val skipValidationChecks = nocParams.skipValidationChecks
val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) }
val router_sink_domains = Seq.tabulate(nNodes) { i =>
val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters(
name = Some(s"${nocName}_router_$i")
)))
router_sink_domain.clockNode := clockSourceNodes(i)
router_sink_domain
}
val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) {
val inParams = allChannelParams.filter(_.destId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val outParams = allChannelParams.filter(_.srcId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val ingressParams = allIngressParams.filter(_.destId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val egressParams = allEgressParams.filter(_.srcId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val noIn = inParams.size + ingressParams.size == 0
val noOut = outParams.size + egressParams.size == 0
if (noIn || noOut) {
println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated")
None
} else {
Some(LazyModule(new Router(
routerParams = allRouterParams(i),
preDiplomaticInParams = inParams,
preDiplomaticIngressParams = ingressParams,
outDests = outParams.map(_.destId),
egressIds = egressParams.map(_.egressId)
)(iP)))
}
}}.flatten
val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) }
val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) }
// Generate channels between routers diplomatically
Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) {
val routerI = routers.find(_.nodeId == i)
val routerJ = routers.find(_.nodeId == j)
if (routerI.isDefined && routerJ.isDefined) {
val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j)
val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i)
require (sourceNodes.size == destNodes.size)
(sourceNodes zip destNodes).foreach { case (src, dst) =>
val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get
router_sink_domains(j) {
implicit val p: Parameters = iP
(dst
:= ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits)
:= channelParam.channelGen(p)(src)
)
}
}
}
}}
// Generate terminal channels diplomatically
routers.foreach { dst => router_sink_domains(dst.nodeId) {
implicit val p: Parameters = iP
dst.ingressNodes.foreach(n => {
val ingressId = n.destParams.ingressId
require(dst.payloadBits <= allIngressParams(ingressId).payloadBits)
(n
:= IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits)
:= ingressNodes(ingressId)
)
})
dst.egressNodes.foreach(n => {
val egressId = n.egressId
require(dst.payloadBits <= allEgressParams(egressId).payloadBits)
(egressNodes(egressId)
:= EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits)
:= n
)
})
}}
val debugNodes = routers.map { r =>
val sink = BundleBridgeSink[DebugBundle]()
sink := r.debugNode
sink
}
val ctrlNodes = if (nocParams.hasCtrl) {
(0 until nNodes).map { i =>
routers.find(_.nodeId == i).map { r =>
val sink = BundleBridgeSink[RouterCtrlBundle]()
sink := r.ctrlNode.get
sink
}
}
} else {
Nil
}
println(s"Constellation: $nocName Finished parameter validation")
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
println(s"Constellation: $nocName Starting NoC RTL generation")
val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) {
val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters())))
val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil
})
(io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l }
(io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r }
(io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r }
if (nocParams.hasCtrl) {
ctrlNodes.zipWithIndex.map { case (c,i) =>
if (c.isDefined) {
io.router_ctrl(i) <> c.get.in(0)._1
} else {
io.router_ctrl(i) <> DontCare
}
}
}
// TODO: These assume a single clock-domain across the entire noc
val debug_va_stall_ctr = RegInit(0.U(64.W))
val debug_sa_stall_ctr = RegInit(0.U(64.W))
val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr
debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_)
debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_)
dontTouch(debug_va_stall_ctr)
dontTouch(debug_sa_stall_ctr)
dontTouch(debug_any_stall_ctr)
def prepend(s: String) = Seq(nocName, s).mkString(".")
ElaborationArtefacts.add(prepend("noc.graphml"), graphML)
val adjList = routers.map { r =>
val outs = r.outParams.map(o => s"${o.destId}").mkString(" ")
val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ")
val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}")
(Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n")
}.mkString("\n")
ElaborationArtefacts.add(prepend("noc.adjlist"), adjList)
val xys = routers.map(r => {
val n = r.nodeId
val ids = (Seq(r.nodeId.toString)
++ r.egressParams.map(e => s"e${e.egressId}")
++ r.ingressParams.map(i => s"i${i.ingressId}")
)
val plotter = nocParams.topology.plotter
val coords = (Seq(plotter.node(r.nodeId))
++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) }
++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) }
)
(ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n")
}).mkString("\n")
ElaborationArtefacts.add(prepend("noc.xy"), xys)
val edgeProps = routers.map { r =>
val outs = r.outParams.map { o =>
(Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
val egresses = r.egressParams.map { e =>
(Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
val ingresses = r.ingressParams.map { i =>
(Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
(outs ++ egresses ++ ingresses).mkString("\n")
}.mkString("\n")
ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps)
println(s"Constellation: $nocName Finished NoC RTL generation")
}
}
|
module test_router_27ClockSinkDomain( // @[ClockDomain.scala:14:9]
output [4:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [21:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25]
input [21:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [21:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25]
input [21:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [21:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25]
output [21:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [21:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25]
output [21:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
Router_22 routers ( // @[NoC.scala:67:22]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),
.auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1),
.auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),
.auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1),
.auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid),
.auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head),
.auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail),
.auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload),
.auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return),
.auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free),
.auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid),
.auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head),
.auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail),
.auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload),
.auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return),
.auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free),
.auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid),
.auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head),
.auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail),
.auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload),
.auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return),
.auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free),
.auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid),
.auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head),
.auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail),
.auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload),
.auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return),
.auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free)
); // @[NoC.scala:67:22]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File RecFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class
RecFNToRecFN(
inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int)
extends chisel3.RawModule
{
val io = IO(new Bundle {
val in = Input(Bits((inExpWidth + inSigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in);
if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
io.out := io.in<<(outSigWidth - inSigWidth)
io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W)
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
inExpWidth,
inSigWidth,
outExpWidth,
outSigWidth,
flRoundOpt_sigMSBitAlwaysZero
))
roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn)
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := rawIn
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
File common.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of
the University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
object consts {
/*------------------------------------------------------------------------
| For rounding to integer values, rounding mode 'odd' rounds to minimum
| magnitude instead, same as 'minMag'.
*------------------------------------------------------------------------*/
def round_near_even = "b000".U(3.W)
def round_minMag = "b001".U(3.W)
def round_min = "b010".U(3.W)
def round_max = "b011".U(3.W)
def round_near_maxMag = "b100".U(3.W)
def round_odd = "b110".U(3.W)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def tininess_beforeRounding = 0.U
def tininess_afterRounding = 1.U
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def flRoundOpt_sigMSBitAlwaysZero = 1
def flRoundOpt_subnormsAlwaysExact = 2
def flRoundOpt_neverUnderflows = 4
def flRoundOpt_neverOverflows = 8
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def divSqrtOpt_twoBitsPerCycle = 16
}
class RawFloat(val expWidth: Int, val sigWidth: Int) extends Bundle
{
val isNaN: Bool = Bool() // overrides all other fields
val isInf: Bool = Bool() // overrides 'isZero', 'sExp', and 'sig'
val isZero: Bool = Bool() // overrides 'sExp' and 'sig'
val sign: Bool = Bool()
val sExp: SInt = SInt((expWidth + 2).W)
val sig: UInt = UInt((sigWidth + 1).W) // 2 m.s. bits cannot both be 0
}
//*** CHANGE THIS INTO A '.isSigNaN' METHOD OF THE 'RawFloat' CLASS:
object isSigNaNRawFloat
{
def apply(in: RawFloat): Bool = in.isNaN && !in.sig(in.sigWidth - 2)
}
|
module RecFNToRecFN_6( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [64:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h0; // @[RecFNToRecFN.scala:44:5]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16, :72:19]
wire [64:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _roundAnyRawFNToRecFN_io_invalidExc_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _roundAnyRawFNToRecFN_io_invalidExc_T_1 = ~_roundAnyRawFNToRecFN_io_invalidExc_T; // @[common.scala:82:{49,56}]
wire _roundAnyRawFNToRecFN_io_invalidExc_T_2 = rawIn_isNaN & _roundAnyRawFNToRecFN_io_invalidExc_T_1; // @[rawFloatFromRecFN.scala:55:23]
RoundAnyRawFNToRecFN_ie8_is24_oe11_os53_1 roundAnyRawFNToRecFN ( // @[RecFNToRecFN.scala:72:19]
.io_invalidExc (_roundAnyRawFNToRecFN_io_invalidExc_T_2), // @[common.scala:82:46]
.io_in_isNaN (rawIn_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_in_isInf (rawIn_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_in_isZero (rawIn_isZero_0), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sign (rawIn_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sExp (rawIn_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sig (rawIn_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[RecFNToRecFN.scala:72:19]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
|
module RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_9( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [7:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [32:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [7:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [32:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [24:0] _roundMask_T = 25'h0; // @[RoundAnyRawFNToRecFN.scala:153:36]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [26:0] roundMask = 27'h3; // @[RoundAnyRawFNToRecFN.scala:153:55]
wire [27:0] _shiftedRoundMask_T = 28'h3; // @[RoundAnyRawFNToRecFN.scala:162:41]
wire [26:0] shiftedRoundMask = 27'h1; // @[RoundAnyRawFNToRecFN.scala:162:53]
wire [26:0] _roundPosMask_T = 27'h7FFFFFE; // @[RoundAnyRawFNToRecFN.scala:163:28]
wire [26:0] roundPosMask = 27'h2; // @[RoundAnyRawFNToRecFN.scala:163:46]
wire [26:0] _roundedSig_T_10 = 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:180:32]
wire [25:0] _roundedSig_T_6 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67]
wire [25:0] _roundedSig_T_14 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67]
wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:265:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:277:16]
wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:278:16]
wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13]
wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23]
wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53]
wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38]
wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:22]
wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:36]
wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:33]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29]
wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42]
wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30]
wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29]
wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34]
wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49]
wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32]
wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45]
wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32]
wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32]
wire _fractOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :280:22]
wire signOut = io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :250:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire [9:0] _sAdjustedExp_T = {{2{io_in_sExp_0[7]}}, io_in_sExp_0} + 10'hC0; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25]
wire [8:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[8:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14]
wire [9:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}]
wire [25:0] _adjustedSig_T = io_in_sig_0[32:7]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23]
wire [6:0] _adjustedSig_T_1 = io_in_sig_0[6:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26]
wire _adjustedSig_T_2 = |_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}]
wire [26:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [26:0] _roundPosBit_T = adjustedSig & 27'h2; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67]
wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49]
wire [26:0] _anyRoundExtra_T = adjustedSig & 27'h1; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
assign _common_inexact_T = anyRound; // @[RoundAnyRawFNToRecFN.scala:166:36, :230:49]
wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31]
wire [26:0] _roundedSig_T = adjustedSig | 27'h3; // @[RoundAnyRawFNToRecFN.scala:116:66, :153:55, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}, :177:35, :181:67]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_7 = {25'h0, _roundedSig_T_5}; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_11 = adjustedSig & 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {sAdjustedExp[9], sAdjustedExp} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:31, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61]
wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}]
wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{61,64}]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = _inexact_T; // @[RoundAnyRawFNToRecFN.scala:240:{28,43}]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_13 = _expOut_T_10; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_19 = _expOut_T_17; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15]
wire [8:0] expOut = _expOut_T_19; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73]
wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? 23'h0 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16, :284:13]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
assign _io_exceptionFlags_T_3 = {4'h0, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
|
module MacUnit_205( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Transposer.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
trait Transposer[T <: Data] extends Module {
def dim: Int
def dataType: T
val io = IO(new Bundle {
val inRow = Flipped(Decoupled(Vec(dim, dataType)))
val outCol = Decoupled(Vec(dim, dataType))
})
}
class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
val sMoveUp :: sMoveLeft :: Nil = Enum(2)
val state = RegInit(sMoveUp)
val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1)
val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1)
io.outCol.valid := 0.U
io.inRow.ready := 0.U
switch(state) {
is(sMoveUp) {
io.inRow.ready := upCounter <= dim.U
io.outCol.valid := leftCounter > 0.U
when(io.inRow.fire) {
upCounter := upCounter + 1.U
}
when(upCounter === (dim-1).U) {
state := sMoveLeft
leftCounter := 0.U
}
when(io.outCol.fire) {
leftCounter := leftCounter - 1.U
}
}
is(sMoveLeft) {
io.inRow.ready := leftCounter <= dim.U // TODO: this is naive
io.outCol.valid := upCounter > 0.U
when(leftCounter === (dim-1).U) {
state := sMoveUp
}
when(io.inRow.fire) {
leftCounter := leftCounter + 1.U
upCounter := 0.U
}
when(io.outCol.fire) {
upCounter := upCounter - 1.U
}
}
}
// Propagate input from bottom row to top row systolically in the move up phase
// TODO: need to iterate over columns to connect Chisel values of type T
// Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?)
for (colIdx <- 0 until dim) {
regArray.foldRight(io.inRow.bits(colIdx)) {
case (regRow, prevReg) =>
when (state === sMoveUp) {
regRow(colIdx) := prevReg
}
regRow(colIdx)
}
}
// Propagate input from right side to left side systolically in the move left phase
for (rowIdx <- 0 until dim) {
regArrayT.foldRight(io.inRow.bits(rowIdx)) {
case (regCol, prevReg) =>
when (state === sMoveLeft) {
regCol(rowIdx) := prevReg
}
regCol(rowIdx)
}
}
// Pull from the left side or the top side based on the state
for (idx <- 0 until dim) {
when (state === sMoveUp) {
io.outCol.bits(idx) := regArray(0)(idx)
}.elsewhen(state === sMoveLeft) {
io.outCol.bits(idx) := regArrayT(0)(idx)
}.otherwise {
io.outCol.bits(idx) := DontCare
}
}
}
class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val LEFT_DIR = 0.U(1.W)
val UP_DIR = 1.U(1.W)
class PE extends Module {
val io = IO(new Bundle {
val inR = Input(dataType)
val inD = Input(dataType)
val outL = Output(dataType)
val outU = Output(dataType)
val dir = Input(UInt(1.W))
val en = Input(Bool())
})
val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en)
io.outU := reg
io.outL := reg
}
val pes = Seq.fill(dim,dim)(Module(new PE))
val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter
val dir = RegInit(LEFT_DIR)
// Wire up horizontal signals
for (row <- 0 until dim; col <- 0 until dim) {
val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL
pes(row)(col).io.inR := right_in
}
// Wire up vertical signals
for (row <- 0 until dim; col <- 0 until dim) {
val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU
pes(row)(col).io.inD := down_in
}
// Wire up global signals
pes.flatten.foreach(_.io.dir := dir)
pes.flatten.foreach(_.io.en := io.inRow.fire)
io.outCol.valid := true.B
io.inRow.ready := true.B
val left_out = VecInit(pes.transpose.head.map(_.io.outL))
val up_out = VecInit(pes.head.map(_.io.outU))
io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out)
when (io.inRow.fire) {
counter := wrappingAdd(counter, 1.U, dim)
}
when (counter === (dim-1).U && io.inRow.fire) {
dir := ~dir
}
}
class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
// state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise
val state = RegInit(0.U(1.W))
val countInc = io.inRow.fire || io.outCol.fire
val (countValue, countWrap) = Counter(countInc, dim)
io.inRow.ready := state === 0.U
io.outCol.valid := state === 1.U
for (i <- 0 until dim) {
for (j <- 0 until dim) {
when(countValue === i.U && io.inRow.fire) {
regArray(i)(j) := io.inRow.bits(j)
}
}
}
for (i <- 0 until dim) {
io.outCol.bits(i) := 0.U
for (j <- 0 until dim) {
when(countValue === j.U) {
io.outCol.bits(i) := regArrayT(j)(i)
}
}
}
when (io.inRow.fire && countWrap) {
state := 1.U
}
when (io.outCol.fire && countWrap) {
state := 0.U
}
assert(!(state === 0.U) || !io.outCol.fire)
assert(!(state === 1.U) || !io.inRow.fire)
}
|
module PE_159( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util._
import FUConstants._
/**
* IO bundle to interact with Issue slot
*
* @param numWakeupPorts number of wakeup ports for the slot
*/
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val request_hp = Output(Bool())
val grant = Input(Bool())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted.
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz))))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W))))
val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue.
val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued.
val debug = {
val result = new Bundle {
val p1 = Bool()
val p2 = Bool()
val p3 = Bool()
val ppred = Bool()
val state = UInt(width=2.W)
}
Output(result)
}
}
/**
* Single issue slot. Holds a uop within the issue queue
*
* @param numWakeupPorts number of wakeup ports
*/
class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters)
extends BoomModule
with IssueUnitConstants
{
val io = IO(new IssueSlotIO(numWakeupPorts))
// slot invalid?
// slot is valid, holding 1 uop
// slot is valid, holds 2 uops (like a store)
def is_invalid = state === s_invalid
def is_valid = state =/= s_invalid
val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot)
val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot)
val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val state = RegInit(s_invalid)
val p1 = RegInit(false.B)
val p2 = RegInit(false.B)
val p3 = RegInit(false.B)
val ppred = RegInit(false.B)
// Poison if woken up by speculative load.
// Poison lasts 1 cycle (as ldMiss will come on the next cycle).
// SO if poisoned is true, set it to false!
val p1_poisoned = RegInit(false.B)
val p2_poisoned = RegInit(false.B)
p1_poisoned := false.B
p2_poisoned := false.B
val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
val slot_uop = RegInit(NullMicroOp)
val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
//-----------------------------------------------------------------------------
// next slot state computation
// compute the next state for THIS entry slot (in a collasping queue, the
// current uop may get moved elsewhere, and a new uop can enter
when (io.kill) {
state := s_invalid
} .elsewhen (io.in_uop.valid) {
state := io.in_uop.bits.iw_state
} .elsewhen (io.clear) {
state := s_invalid
} .otherwise {
state := next_state
}
//-----------------------------------------------------------------------------
// "update" state
// compute the next state for the micro-op in this slot. This micro-op may
// be moved elsewhere, so the "next_state" travels with it.
// defaults
next_state := state
next_uopc := slot_uop.uopc
next_lrs1_rtype := slot_uop.lrs1_rtype
next_lrs2_rtype := slot_uop.lrs2_rtype
when (io.kill) {
next_state := s_invalid
} .elsewhen ((io.grant && (state === s_valid_1)) ||
(io.grant && (state === s_valid_2) && p1 && p2 && ppred)) {
// try to issue this uop.
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_invalid
}
} .elsewhen (io.grant && (state === s_valid_2)) {
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_valid_1
when (p1) {
slot_uop.uopc := uopSTD
next_uopc := uopSTD
slot_uop.lrs1_rtype := RT_X
next_lrs1_rtype := RT_X
} .otherwise {
slot_uop.lrs2_rtype := RT_X
next_lrs2_rtype := RT_X
}
}
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.")
}
// Wakeup Compare Logic
// these signals are the "next_p*" for the current slot's micro-op.
// they are important for shifting the current slot_uop up to an other entry.
val next_p1 = WireInit(p1)
val next_p2 = WireInit(p2)
val next_p3 = WireInit(p3)
val next_ppred = WireInit(ppred)
when (io.in_uop.valid) {
p1 := !(io.in_uop.bits.prs1_busy)
p2 := !(io.in_uop.bits.prs2_busy)
p3 := !(io.in_uop.bits.prs3_busy)
ppred := !(io.in_uop.bits.ppred_busy)
}
when (io.ldspec_miss && next_p1_poisoned) {
assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!")
p1 := false.B
}
when (io.ldspec_miss && next_p2_poisoned) {
assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!")
p2 := false.B
}
for (i <- 0 until numWakeupPorts) {
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs1)) {
p1 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs2)) {
p2 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs3)) {
p3 := true.B
}
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) {
ppred := true.B
}
for (w <- 0 until memWidth) {
assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),
"Loads to x0 should never speculatively wakeup other instructions")
}
// TODO disable if FP IQ.
for (w <- 0 until memWidth) {
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs1 &&
next_uop.lrs1_rtype === RT_FIX) {
p1 := true.B
p1_poisoned := true.B
assert (!next_p1_poisoned)
}
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs2 &&
next_uop.lrs2_rtype === RT_FIX) {
p2 := true.B
p2_poisoned := true.B
assert (!next_p2_poisoned)
}
}
// Handle branch misspeculations
val next_br_mask = GetNewBrMask(io.brupdate, slot_uop)
// was this micro-op killed by a branch? if yes, we can't let it be valid if
// we compact it into an other entry
when (IsKilledByBranch(io.brupdate, slot_uop)) {
next_state := s_invalid
}
when (!io.in_uop.valid) {
slot_uop.br_mask := next_br_mask
}
//-------------------------------------------------------------
// Request Logic
io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill
val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr
io.request_hp := io.request && high_priority
when (state === s_valid_1) {
io.request := p1 && p2 && p3 && ppred && !io.kill
} .elsewhen (state === s_valid_2) {
io.request := (p1 || p2) && ppred && !io.kill
} .otherwise {
io.request := false.B
}
//assign outputs
io.valid := is_valid
io.uop := slot_uop
io.uop.iw_p1_poisoned := p1_poisoned
io.uop.iw_p2_poisoned := p2_poisoned
// micro-op will vacate due to grant.
val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred)
val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned)
io.will_be_valid := is_valid && !(may_vacate && !squash_grant)
io.out_uop := slot_uop
io.out_uop.iw_state := next_state
io.out_uop.uopc := next_uopc
io.out_uop.lrs1_rtype := next_lrs1_rtype
io.out_uop.lrs2_rtype := next_lrs2_rtype
io.out_uop.br_mask := next_br_mask
io.out_uop.prs1_busy := !p1
io.out_uop.prs2_busy := !p2
io.out_uop.prs3_busy := !p3
io.out_uop.ppred_busy := !ppred
io.out_uop.iw_p1_poisoned := p1_poisoned
io.out_uop.iw_p2_poisoned := p2_poisoned
when (state === s_valid_2) {
when (p1 && p2 && ppred) {
; // send out the entire instruction as one uop
} .elsewhen (p1 && ppred) {
io.uop.uopc := slot_uop.uopc
io.uop.lrs2_rtype := RT_X
} .elsewhen (p2 && ppred) {
io.uop.uopc := uopSTD
io.uop.lrs1_rtype := RT_X
}
}
// debug outputs
io.debug.p1 := p1
io.debug.p2 := p2
io.debug.p3 := p3
io.debug.ppred := ppred
io.debug.state := state
}
|
module IssueSlot_15( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [5:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [5:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [5:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [5:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ppred = 4'h0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_ppred = 4'h0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ppred = 4'h0; // @[issue-slot.scala:69:7]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] next_uop_ppred = 4'h0; // @[issue-slot.scala:103:21]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy = 1'h0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy = 1'h0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire next_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:103:21]
wire next_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:103:21]
wire next_uop_prs3_busy = 1'h0; // @[issue-slot.scala:103:21]
wire next_uop_ppred_busy = 1'h0; // @[issue-slot.scala:103:21]
wire _p3_T = 1'h1; // @[issue-slot.scala:171:11]
wire _ppred_T = 1'h1; // @[issue-slot.scala:172:14]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [7:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = ~io_in_uop_valid_0 & p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = ~io_in_uop_valid_0 & p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :99:29, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_61 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_69 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
|
module RoundRawFNToRecFN_e8_s24_34( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_34 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File AtomicAutomata.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rocketchip.util.leftOR
import scala.math.{min,max}
// Ensures that all downstream RW managers support Atomic operations.
// If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream.
class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule
{
require (concurrency >= 1)
val node = TLAdapterNode(
managerFn = { case mp => mp.v1copy(managers = mp.managers.map { m =>
val ourSupport = TransferSizes(1, mp.beatBytes)
def widen(x: TransferSizes) = if (passthrough && x.min <= 2*mp.beatBytes) TransferSizes(1, max(mp.beatBytes, x.max)) else ourSupport
val canDoit = m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport)
// Blow up if there are devices to which we cannot add Atomics, because their R|W are too inflexible
require (!m.supportsPutFull || !m.supportsGet || canDoit, s"${m.name} has $ourSupport, needed PutFull(${m.supportsPutFull}) or Get(${m.supportsGet})")
m.v1copy(
supportsArithmetic = if (!arithmetic || !canDoit) m.supportsArithmetic else widen(m.supportsArithmetic),
supportsLogical = if (!logical || !canDoit) m.supportsLogical else widen(m.supportsLogical),
mayDenyGet = m.mayDenyGet || m.mayDenyPut)
})})
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val managers = edgeOut.manager.managers
val beatBytes = edgeOut.manager.beatBytes
// To which managers are we adding atomic support?
val ourSupport = TransferSizes(1, beatBytes)
val managersNeedingHelp = managers.filter { m =>
m.supportsPutFull.contains(ourSupport) &&
m.supportsGet.contains(ourSupport) &&
((logical && !m.supportsLogical .contains(ourSupport)) ||
(arithmetic && !m.supportsArithmetic.contains(ourSupport)) ||
!passthrough) // we will do atomics for everyone we can
}
// Managers that need help with atomics must necessarily have this node as the root of a tree in the node graph.
// (But they must also ensure no sideband operations can get between the read and write.)
val violations = managersNeedingHelp.flatMap(_.findTreeViolation()).map { node => (node.name, node.inputs.map(_._1.name)) }
require(violations.isEmpty,
s"AtomicAutomata can only help nodes for which it is at the root of a diplomatic node tree," +
"but the following violations were found:\n" +
violations.map(v => s"(${v._1} has parents ${v._2})").mkString("\n"))
// We cannot add atomics to a non-FIFO manager
managersNeedingHelp foreach { m => require (m.fifoId.isDefined) }
// We need to preserve FIFO semantics across FIFO domains, not managers
// Suppose you have Put(42) Atomic(+1) both inflight; valid results: 42 or 43
// If we allow Put(42) Get() Put(+1) concurrent; valid results: 42 43 OR undef
// Making non-FIFO work requires waiting for all Acks to come back (=> use FIFOFixer)
val domainsNeedingHelp = managersNeedingHelp.map(_.fifoId.get).distinct
// Don't overprovision the CAM
val camSize = min(domainsNeedingHelp.size, concurrency)
// Compact the fifoIds to only those we care about
def camFifoId(m: TLSlaveParameters) = m.fifoId.map(id => max(0, domainsNeedingHelp.indexOf(id))).getOrElse(0)
// CAM entry state machine
val FREE = 0.U // unused waiting on Atomic from A
val GET = 3.U // Get sent down A waiting on AccessDataAck from D
val AMO = 2.U // AccessDataAck sent up D waiting for A availability
val ACK = 1.U // Put sent down A waiting for PutAck from D
val params = TLAtomicAutomata.CAMParams(out.a.bits.params, domainsNeedingHelp.size)
// Do we need to do anything at all?
if (camSize > 0) {
val initval = Wire(new TLAtomicAutomata.CAM_S(params))
initval.state := FREE
val cam_s = RegInit(VecInit.fill(camSize)(initval))
val cam_a = Reg(Vec(camSize, new TLAtomicAutomata.CAM_A(params)))
val cam_d = Reg(Vec(camSize, new TLAtomicAutomata.CAM_D(params)))
val cam_free = cam_s.map(_.state === FREE)
val cam_amo = cam_s.map(_.state === AMO)
val cam_abusy = cam_s.map(e => e.state === GET || e.state === AMO) // A is blocked
val cam_dmatch = cam_s.map(e => e.state =/= FREE) // D should inspect these entries
// Can the manager already handle this message?
val a_address = edgeIn.address(in.a.bits)
val a_size = edgeIn.size(in.a.bits)
val a_canLogical = passthrough.B && edgeOut.manager.supportsLogicalFast (a_address, a_size)
val a_canArithmetic = passthrough.B && edgeOut.manager.supportsArithmeticFast(a_address, a_size)
val a_isLogical = in.a.bits.opcode === TLMessages.LogicalData
val a_isArithmetic = in.a.bits.opcode === TLMessages.ArithmeticData
val a_isSupported = Mux(a_isLogical, a_canLogical, Mux(a_isArithmetic, a_canArithmetic, true.B))
// Must we do a Put?
val a_cam_any_put = cam_amo.reduce(_ || _)
val a_cam_por_put = cam_amo.scanLeft(false.B)(_||_).init
val a_cam_sel_put = (cam_amo zip a_cam_por_put) map { case (a, b) => a && !b }
val a_cam_a = PriorityMux(cam_amo, cam_a)
val a_cam_d = PriorityMux(cam_amo, cam_d)
val a_a = a_cam_a.bits.data
val a_d = a_cam_d.data
// Does the A request conflict with an inflight AMO?
val a_fifoId = edgeOut.manager.fastProperty(a_address, camFifoId _, (i:Int) => i.U)
val a_cam_busy = (cam_abusy zip cam_a.map(_.fifoId === a_fifoId)) map { case (a,b) => a&&b } reduce (_||_)
// (Where) are we are allocating in the CAM?
val a_cam_any_free = cam_free.reduce(_ || _)
val a_cam_por_free = cam_free.scanLeft(false.B)(_||_).init
val a_cam_sel_free = (cam_free zip a_cam_por_free) map { case (a,b) => a && !b }
// Logical AMO
val indexes = Seq.tabulate(beatBytes*8) { i => Cat(a_a(i,i), a_d(i,i)) }
val logic_out = Cat(indexes.map(x => a_cam_a.lut(x).asUInt).reverse)
// Arithmetic AMO
val unsigned = a_cam_a.bits.param(1)
val take_max = a_cam_a.bits.param(0)
val adder = a_cam_a.bits.param(2)
val mask = a_cam_a.bits.mask
val signSel = ~(~mask | (mask >> 1))
val signbits_a = Cat(Seq.tabulate(beatBytes) { i => a_a(8*i+7,8*i+7) } .reverse)
val signbits_d = Cat(Seq.tabulate(beatBytes) { i => a_d(8*i+7,8*i+7) } .reverse)
// Move the selected sign bit into the first byte position it will extend
val signbit_a = ((signbits_a & signSel) << 1)(beatBytes-1, 0)
val signbit_d = ((signbits_d & signSel) << 1)(beatBytes-1, 0)
val signext_a = FillInterleaved(8, leftOR(signbit_a))
val signext_d = FillInterleaved(8, leftOR(signbit_d))
// NOTE: sign-extension does not change the relative ordering in EITHER unsigned or signed arithmetic
val wide_mask = FillInterleaved(8, mask)
val a_a_ext = (a_a & wide_mask) | signext_a
val a_d_ext = (a_d & wide_mask) | signext_d
val a_d_inv = Mux(adder, a_d_ext, ~a_d_ext)
val adder_out = a_a_ext + a_d_inv
val h = 8*beatBytes-1 // now sign-extended; use biggest bit
val a_bigger_uneq = unsigned === a_a_ext(h) // result if high bits are unequal
val a_bigger = Mux(a_a_ext(h) === a_d_ext(h), !adder_out(h), a_bigger_uneq)
val pick_a = take_max === a_bigger
val arith_out = Mux(adder, adder_out, Mux(pick_a, a_a, a_d))
// AMO result data
val amo_data =
if (!logical) arith_out else
if (!arithmetic) logic_out else
Mux(a_cam_a.bits.opcode(0), logic_out, arith_out)
// Potentially mutate the message from inner
val source_i = Wire(chiselTypeOf(in.a))
val a_allow = !a_cam_busy && (a_isSupported || a_cam_any_free)
in.a.ready := source_i.ready && a_allow
source_i.valid := in.a.valid && a_allow
source_i.bits := in.a.bits
when (!a_isSupported) { // minimal mux difference
source_i.bits.opcode := TLMessages.Get
source_i.bits.param := 0.U
}
// Potentially take the message from the CAM
val source_c = Wire(chiselTypeOf(in.a))
source_c.valid := a_cam_any_put
source_c.bits := edgeOut.Put(
fromSource = a_cam_a.bits.source,
toAddress = edgeIn.address(a_cam_a.bits),
lgSize = a_cam_a.bits.size,
data = amo_data,
corrupt = a_cam_a.bits.corrupt || a_cam_d.corrupt)._2
source_c.bits.user :<= a_cam_a.bits.user
source_c.bits.echo :<= a_cam_a.bits.echo
// Finishing an AMO from the CAM has highest priority
TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (0.U, source_c), (edgeOut.numBeats1(in.a.bits), source_i))
// Capture the A state into the CAM
when (source_i.fire && !a_isSupported) {
(a_cam_sel_free zip cam_a) foreach { case (en, r) =>
when (en) {
r.fifoId := a_fifoId
r.bits := in.a.bits
r.lut := MuxLookup(in.a.bits.param(1, 0), 0.U(4.W))(Array(
TLAtomics.AND -> 0x8.U,
TLAtomics.OR -> 0xe.U,
TLAtomics.XOR -> 0x6.U,
TLAtomics.SWAP -> 0xc.U))
}
}
(a_cam_sel_free zip cam_s) foreach { case (en, r) =>
when (en) {
r.state := GET
}
}
}
// Advance the put state
when (source_c.fire) {
(a_cam_sel_put zip cam_s) foreach { case (en, r) =>
when (en) {
r.state := ACK
}
}
}
// We need to deal with a potential D response in the same cycle as the A request
val d_first = edgeOut.first(out.d)
val d_cam_sel_raw = cam_a.map(_.bits.source === in.d.bits.source)
val d_cam_sel_match = (d_cam_sel_raw zip cam_dmatch) map { case (a,b) => a&&b }
val d_cam_data = Mux1H(d_cam_sel_match, cam_d.map(_.data))
val d_cam_denied = Mux1H(d_cam_sel_match, cam_d.map(_.denied))
val d_cam_corrupt = Mux1H(d_cam_sel_match, cam_d.map(_.corrupt))
val d_cam_sel_bypass = if (edgeOut.manager.minLatency > 0) false.B else
out.d.bits.source === in.a.bits.source && in.a.valid && !a_isSupported
val d_cam_sel = (a_cam_sel_free zip d_cam_sel_match) map { case (a,d) => Mux(d_cam_sel_bypass, a, d) }
val d_cam_sel_any = d_cam_sel_bypass || d_cam_sel_match.reduce(_ || _)
val d_ackd = out.d.bits.opcode === TLMessages.AccessAckData
val d_ack = out.d.bits.opcode === TLMessages.AccessAck
when (out.d.fire && d_first) {
(d_cam_sel zip cam_d) foreach { case (en, r) =>
when (en && d_ackd) {
r.data := out.d.bits.data
r.denied := out.d.bits.denied
r.corrupt := out.d.bits.corrupt
}
}
(d_cam_sel zip cam_s) foreach { case (en, r) =>
when (en) {
// Note: it is important that this comes AFTER the := GET, so we can go FREE=>GET=>AMO in one cycle
r.state := Mux(d_ackd, AMO, FREE)
}
}
}
val d_drop = d_first && d_ackd && d_cam_sel_any
val d_replace = d_first && d_ack && d_cam_sel_match.reduce(_ || _)
in.d.valid := out.d.valid && !d_drop
out.d.ready := in.d.ready || d_drop
in.d.bits := out.d.bits
when (d_replace) { // minimal muxes
in.d.bits.opcode := TLMessages.AccessAckData
in.d.bits.data := d_cam_data
in.d.bits.corrupt := d_cam_corrupt || out.d.bits.denied
in.d.bits.denied := d_cam_denied || out.d.bits.denied
}
} else {
out.a.valid := in.a.valid
in.a.ready := out.a.ready
out.a.bits := in.a.bits
in.d.valid := out.d.valid
out.d.ready := in.d.ready
in.d.bits := out.d.bits
}
if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
in.b.valid := out.b.valid
out.b.ready := in.b.ready
in.b.bits := out.b.bits
out.c.valid := in.c.valid
in.c.ready := out.c.ready
out.c.bits := in.c.bits
out.e.valid := in.e.valid
in.e.ready := out.e.ready
out.e.bits := in.e.bits
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLAtomicAutomata
{
def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough) {
override lazy val desiredName = (Seq("TLAtomicAutomata") ++ nameSuffix).mkString("_")
})
atomics.node
}
case class CAMParams(a: TLBundleParameters, domainsNeedingHelp: Int)
class CAM_S(val params: CAMParams) extends Bundle {
val state = UInt(2.W)
}
class CAM_A(val params: CAMParams) extends Bundle {
val bits = new TLBundleA(params.a)
val fifoId = UInt(log2Up(params.domainsNeedingHelp).W)
val lut = UInt(4.W)
}
class CAM_D(val params: CAMParams) extends Bundle {
val data = UInt(params.a.dataBits.W)
val denied = Bool()
val corrupt = Bool()
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("AtomicAutomata"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
// Confirm that the AtomicAutomata combines read + write errors
import TLMessages._
val test = new RequestPattern({a: TLBundleA =>
val doesA = a.opcode === ArithmeticData || a.opcode === LogicalData
val doesR = a.opcode === Get || doesA
val doesW = a.opcode === PutFullData || a.opcode === PutPartialData || doesA
(doesR && RequestPattern.overlaps(Seq(AddressSet(0x08, ~0x08)))(a)) ||
(doesW && RequestPattern.overlaps(Seq(AddressSet(0x10, ~0x10)))(a))
})
(ram.node
:= TLErrorEvaluator(test)
:= TLFragmenter(4, 256)
:= TLDelayer(0.1)
:= TLAtomicAutomata()
:= TLDelayer(0.1)
:= TLErrorEvaluator(test, testOn=true, testOff=true)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMAtomicAutomataTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMAtomicAutomata(txns)).module)
io.finished := dut.io.finished
dut.io.start := io.start
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File Arbiter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
object TLArbiter
{
// (valids, select) => readys
type Policy = (Integer, UInt, Bool) => UInt
val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0)
val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width))
val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else {
val valid = valids(width-1, 0)
assert (valid === valids)
val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0))
val filter = Cat(valid & ~mask, valid)
val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width)
val readys = ~((unready >> width) & unready(width-1, 0))
when (select && valid.orR) {
mask := leftOR(readys & valid, width)
}
readys(width-1, 0)
}
def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = {
apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = {
if (sources.isEmpty) {
sink.bits := DontCare
} else if (sources.size == 1) {
sink :<>= sources.head._2
} else {
val pairs = sources.toList
val beatsIn = pairs.map(_._1)
val sourcesIn = pairs.map(_._2)
// The number of beats which remain to be sent
val beatsLeft = RegInit(0.U)
val idle = beatsLeft === 0.U
val latch = idle && sink.ready // winner (if any) claims sink
// Who wants access to the sink?
val valids = sourcesIn.map(_.valid)
// Arbitrate amongst the requests
val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools)
// Which request wins arbitration?
val winner = VecInit((readys zip valids) map { case (r,v) => r&&v })
// Confirm the policy works properly
require (readys.size == valids.size)
// Never two winners
val prefixOR = winner.scanLeft(false.B)(_||_).init
assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})
// If there was any request, there is a winner
assert (!valids.reduce(_||_) || winner.reduce(_||_))
// Track remaining beats
val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) }
val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats
beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire)
// The one-hot source granted access in the previous cycle
val state = RegInit(VecInit(Seq.fill(sources.size)(false.B)))
val muxState = Mux(idle, winner, state)
state := muxState
val allowed = Mux(idle, readys, state)
(sourcesIn zip allowed) foreach { case (s, r) =>
s.ready := sink.ready && r
}
sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids))
sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits))
}
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
abstract class DecoupledArbiterTest(
policy: TLArbiter.Policy,
txns: Int,
timeout: Int,
val numSources: Int,
beatsLeftFromIdx: Int => UInt)
(implicit p: Parameters) extends UnitTest(timeout)
{
val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W))))
dontTouch(sources.suggestName("sources"))
val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W)))
dontTouch(sink.suggestName("sink"))
val count = RegInit(0.U(log2Ceil(txns).W))
val lfsr = LFSR(16, true.B)
sources.zipWithIndex.map { case (z, i) => z.bits := i.U }
TLArbiter(policy)(sink, sources.zipWithIndex.map {
case (z, i) => (beatsLeftFromIdx(i), z)
}:_*)
count := count + 1.U
io.finished := count >= txns.U
}
/** This tests that when a specific pattern of source valids are driven,
* a new index from amongst that pattern is always selected,
* unless one of those sources takes multiple beats,
* in which case the same index should be selected until the arbiter goes idle.
*/
class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false)
(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U)
{
val lastWinner = RegInit((numSources+1).U)
val beatsLeft = RegInit(0.U(log2Ceil(numSources).W))
val first = lastWinner > numSources.U
val valid = lfsr(0)
val ready = lfsr(15)
sink.ready := ready
sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way
case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid)
}
when (sink.fire) {
if (print) { printf("TestRobin: %d\n", sink.bits) }
when (beatsLeft === 0.U) {
assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.")
lastWinner := sink.bits
beatsLeft := sink.bits
} .otherwise {
assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats")
beatsLeft := beatsLeft - 1.U
}
}
if (print) {
when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) }
}
}
/** This tests that the lowest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertLowest(id: Int): Unit = {
when (sources(id).valid) {
assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) }
}
/** This tests that the highest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertHighest(id: Int): Unit = {
when (sources(id).valid) {
assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) }
}
|
module TLAtomicAutomata_cbus( // @[AtomicAutomata.scala:36:9]
input clock, // @[AtomicAutomata.scala:36:9]
input reset, // @[AtomicAutomata.scala:36:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire source_i_ready; // @[Arbiter.scala:94:31]
reg [1:0] cam_s_0_state; // @[AtomicAutomata.scala:82:28]
reg [2:0] cam_a_0_bits_opcode; // @[AtomicAutomata.scala:83:24]
reg [2:0] cam_a_0_bits_param; // @[AtomicAutomata.scala:83:24]
reg [3:0] cam_a_0_bits_size; // @[AtomicAutomata.scala:83:24]
reg [6:0] cam_a_0_bits_source; // @[AtomicAutomata.scala:83:24]
reg [28:0] cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24]
reg [7:0] cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24]
reg [63:0] cam_a_0_bits_data; // @[AtomicAutomata.scala:83:24]
reg cam_a_0_bits_corrupt; // @[AtomicAutomata.scala:83:24]
reg [3:0] cam_a_0_lut; // @[AtomicAutomata.scala:83:24]
reg [63:0] cam_d_0_data; // @[AtomicAutomata.scala:84:24]
reg cam_d_0_denied; // @[AtomicAutomata.scala:84:24]
reg cam_d_0_corrupt; // @[AtomicAutomata.scala:84:24]
wire cam_free_0 = cam_s_0_state == 2'h0; // @[AtomicAutomata.scala:82:28, :86:44]
wire winner_0 = cam_s_0_state == 2'h2; // @[AtomicAutomata.scala:82:28, :87:44]
wire _a_canArithmetic_T_3 = auto_in_a_bits_size < 4'h4; // @[Parameters.scala:92:38]
wire [4:0] _GEN = {auto_in_a_bits_address[28:27], auto_in_a_bits_address[25], auto_in_a_bits_address[16], ~(auto_in_a_bits_address[12])}; // @[Parameters.scala:137:{31,41,46}]
wire [4:0] _GEN_0 = {auto_in_a_bits_address[28:27] ^ 2'h2, auto_in_a_bits_address[25], auto_in_a_bits_address[16], auto_in_a_bits_address[12]}; // @[Parameters.scala:137:{31,41,46}]
wire a_isSupported = auto_in_a_bits_opcode == 3'h3 ? _a_canArithmetic_T_3 & (~(|_GEN) | ~(|_GEN_0)) : auto_in_a_bits_opcode != 3'h2 | _a_canArithmetic_T_3 & (~(|_GEN) | ~(|_GEN_0)); // @[Parameters.scala:684:54, :685:42]
wire [3:0] _logic_out_T = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[0], cam_d_0_data[0]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_2 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[1], cam_d_0_data[1]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_4 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[2], cam_d_0_data[2]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_6 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[3], cam_d_0_data[3]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_8 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[4], cam_d_0_data[4]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_10 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[5], cam_d_0_data[5]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_12 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[6], cam_d_0_data[6]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_14 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[7], cam_d_0_data[7]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_16 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[8], cam_d_0_data[8]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_18 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[9], cam_d_0_data[9]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_20 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[10], cam_d_0_data[10]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_22 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[11], cam_d_0_data[11]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_24 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[12], cam_d_0_data[12]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_26 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[13], cam_d_0_data[13]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_28 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[14], cam_d_0_data[14]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_30 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[15], cam_d_0_data[15]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_32 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[16], cam_d_0_data[16]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_34 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[17], cam_d_0_data[17]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_36 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[18], cam_d_0_data[18]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_38 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[19], cam_d_0_data[19]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_40 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[20], cam_d_0_data[20]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_42 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[21], cam_d_0_data[21]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_44 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[22], cam_d_0_data[22]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_46 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[23], cam_d_0_data[23]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_48 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[24], cam_d_0_data[24]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_50 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[25], cam_d_0_data[25]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_52 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[26], cam_d_0_data[26]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_54 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[27], cam_d_0_data[27]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_56 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[28], cam_d_0_data[28]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_58 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[29], cam_d_0_data[29]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_60 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[30], cam_d_0_data[30]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_62 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[31], cam_d_0_data[31]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_64 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[32], cam_d_0_data[32]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_66 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[33], cam_d_0_data[33]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_68 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[34], cam_d_0_data[34]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_70 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[35], cam_d_0_data[35]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_72 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[36], cam_d_0_data[36]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_74 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[37], cam_d_0_data[37]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_76 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[38], cam_d_0_data[38]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_78 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[39], cam_d_0_data[39]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_80 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[40], cam_d_0_data[40]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_82 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[41], cam_d_0_data[41]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_84 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[42], cam_d_0_data[42]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_86 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[43], cam_d_0_data[43]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_88 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[44], cam_d_0_data[44]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_90 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[45], cam_d_0_data[45]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_92 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[46], cam_d_0_data[46]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_94 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[47], cam_d_0_data[47]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_96 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[48], cam_d_0_data[48]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_98 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[49], cam_d_0_data[49]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_100 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[50], cam_d_0_data[50]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_102 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[51], cam_d_0_data[51]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_104 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[52], cam_d_0_data[52]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_106 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[53], cam_d_0_data[53]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_108 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[54], cam_d_0_data[54]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_110 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[55], cam_d_0_data[55]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_112 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[56], cam_d_0_data[56]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_114 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[57], cam_d_0_data[57]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_116 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[58], cam_d_0_data[58]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_118 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[59], cam_d_0_data[59]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_120 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[60], cam_d_0_data[60]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_122 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[61], cam_d_0_data[61]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_124 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[62], cam_d_0_data[62]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_126 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[63], cam_d_0_data[63]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [6:0] _GEN_1 = ~(cam_a_0_bits_mask[6:0]) | cam_a_0_bits_mask[7:1]; // @[AtomicAutomata.scala:83:24, :127:{25,31,39}]
wire [6:0] _signbit_a_T = {cam_a_0_bits_data[55], cam_a_0_bits_data[47], cam_a_0_bits_data[39], cam_a_0_bits_data[31], cam_a_0_bits_data[23], cam_a_0_bits_data[15], cam_a_0_bits_data[7]} & ~_GEN_1; // @[AtomicAutomata.scala:83:24, :119:63, :127:{23,31}, :128:29, :131:38]
wire [6:0] _signbit_d_T = {cam_d_0_data[55], cam_d_0_data[47], cam_d_0_data[39], cam_d_0_data[31], cam_d_0_data[23], cam_d_0_data[15], cam_d_0_data[7]} & ~_GEN_1; // @[AtomicAutomata.scala:84:24, :119:73, :127:{23,31}, :129:29, :132:38]
wire [5:0] _GEN_2 = _signbit_a_T[6:1] | _signbit_a_T[5:0]; // @[package.scala:253:{43,53}]
wire [3:0] _GEN_3 = _GEN_2[5:2] | _GEN_2[3:0]; // @[package.scala:253:{43,53}]
wire _signext_a_T_13 = _GEN_2[1] | _signbit_a_T[0]; // @[package.scala:253:43]
wire [5:0] _GEN_4 = _signbit_d_T[6:1] | _signbit_d_T[5:0]; // @[package.scala:253:{43,53}]
wire [3:0] _GEN_5 = _GEN_4[5:2] | _GEN_4[3:0]; // @[package.scala:253:{43,53}]
wire _signext_d_T_13 = _GEN_4[1] | _signbit_d_T[0]; // @[package.scala:253:43]
wire [63:0] wide_mask = {{8{cam_a_0_bits_mask[7]}}, {8{cam_a_0_bits_mask[6]}}, {8{cam_a_0_bits_mask[5]}}, {8{cam_a_0_bits_mask[4]}}, {8{cam_a_0_bits_mask[3]}}, {8{cam_a_0_bits_mask[2]}}, {8{cam_a_0_bits_mask[1]}}, {8{cam_a_0_bits_mask[0]}}}; // @[AtomicAutomata.scala:83:24, :136:40]
wire [63:0] a_a_ext = cam_a_0_bits_data & wide_mask | {{8{_GEN_3[3] | _signext_a_T_13}}, {8{_GEN_3[2] | _GEN_2[0]}}, {8{_GEN_3[1] | _signbit_a_T[0]}}, {8{_GEN_3[0]}}, {8{_signext_a_T_13}}, {8{_GEN_2[0]}}, {8{_signbit_a_T[0]}}, 8'h0}; // @[package.scala:253:43]
wire [63:0] a_d_ext = cam_d_0_data & wide_mask | {{8{_GEN_5[3] | _signext_d_T_13}}, {8{_GEN_5[2] | _GEN_4[0]}}, {8{_GEN_5[1] | _signbit_d_T[0]}}, {8{_GEN_5[0]}}, {8{_signext_d_T_13}}, {8{_GEN_4[0]}}, {8{_signbit_d_T[0]}}, 8'h0}; // @[package.scala:253:43]
wire [63:0] _adder_out_T = a_a_ext + ({64{~(cam_a_0_bits_param[2])}} ^ a_d_ext); // @[AtomicAutomata.scala:83:24, :125:39, :137:41, :138:41, :139:26, :140:33]
wire a_allow = ~((&cam_s_0_state) | winner_0) & (a_isSupported | cam_free_0); // @[AtomicAutomata.scala:82:28, :86:44, :87:44, :88:{49,57}, :98:32, :155:{23,35,53}]
wire nodeIn_a_ready = source_i_ready & a_allow; // @[AtomicAutomata.scala:155:35, :156:38]
wire source_i_valid = auto_in_a_valid & a_allow; // @[AtomicAutomata.scala:155:35, :157:38]
wire source_c_bits_a_mask_sub_sub_sub_0_1 = cam_a_0_bits_size > 4'h2; // @[Misc.scala:206:21]
wire source_c_bits_a_mask_sub_sub_size = cam_a_0_bits_size[1:0] == 2'h2; // @[OneHot.scala:64:49]
wire source_c_bits_a_mask_sub_sub_0_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | source_c_bits_a_mask_sub_sub_size & ~(cam_a_0_bits_address[2]); // @[Misc.scala:206:21, :209:26, :210:26, :211:20, :215:{29,38}]
wire source_c_bits_a_mask_sub_sub_1_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | source_c_bits_a_mask_sub_sub_size & cam_a_0_bits_address[2]; // @[Misc.scala:206:21, :209:26, :210:26, :215:{29,38}]
wire source_c_bits_a_mask_sub_size = cam_a_0_bits_size[1:0] == 2'h1; // @[OneHot.scala:64:49]
wire source_c_bits_a_mask_sub_0_2 = ~(cam_a_0_bits_address[2]) & ~(cam_a_0_bits_address[1]); // @[Misc.scala:210:26, :211:20, :214:27]
wire source_c_bits_a_mask_sub_0_1 = source_c_bits_a_mask_sub_sub_0_1 | source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire source_c_bits_a_mask_sub_1_2 = ~(cam_a_0_bits_address[2]) & cam_a_0_bits_address[1]; // @[Misc.scala:210:26, :211:20, :214:27]
wire source_c_bits_a_mask_sub_1_1 = source_c_bits_a_mask_sub_sub_0_1 | source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire source_c_bits_a_mask_sub_2_2 = cam_a_0_bits_address[2] & ~(cam_a_0_bits_address[1]); // @[Misc.scala:210:26, :211:20, :214:27]
wire source_c_bits_a_mask_sub_2_1 = source_c_bits_a_mask_sub_sub_1_1 | source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire source_c_bits_a_mask_sub_3_2 = cam_a_0_bits_address[2] & cam_a_0_bits_address[1]; // @[Misc.scala:210:26, :214:27]
wire source_c_bits_a_mask_sub_3_1 = source_c_bits_a_mask_sub_sub_1_1 | source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire winner_1 = ~winner_0 & source_i_valid; // @[AtomicAutomata.scala:87:44, :157:38]
wire _nodeOut_a_valid_T = winner_0 | source_i_valid; // @[AtomicAutomata.scala:87:44, :157:38]
|
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Replacement.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import freechips.rocketchip.util.property.cover
abstract class ReplacementPolicy {
def nBits: Int
def perSet: Boolean
def way: UInt
def miss: Unit
def hit: Unit
def access(touch_way: UInt): Unit
def access(touch_ways: Seq[Valid[UInt]]): Unit
def state_read: UInt
def get_next_state(state: UInt, touch_way: UInt): UInt
def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = {
touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev))
}
def get_replace_way(state: UInt): UInt
}
object ReplacementPolicy {
def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match {
case "random" => new RandomReplacement(n_ways)
case "lru" => new TrueLRU(n_ways)
case "plru" => new PseudoLRU(n_ways)
case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t")
}
}
class RandomReplacement(n_ways: Int) extends ReplacementPolicy {
private val replace = Wire(Bool())
replace := false.B
def nBits = 16
def perSet = false
private val lfsr = LFSR(nBits, replace)
def state_read = WireDefault(lfsr)
def way = Random(n_ways, lfsr)
def miss = replace := true.B
def hit = {}
def access(touch_way: UInt) = {}
def access(touch_ways: Seq[Valid[UInt]]) = {}
def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare
def get_replace_way(state: UInt) = way
}
abstract class SeqReplacementPolicy {
def access(set: UInt): Unit
def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit
def way: UInt
}
abstract class SetAssocReplacementPolicy {
def access(set: UInt, touch_way: UInt): Unit
def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit
def way(set: UInt): UInt
}
class SeqRandom(n_ways: Int) extends SeqReplacementPolicy {
val logic = new RandomReplacement(n_ways)
def access(set: UInt) = { }
def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = {
when (valid && !hit) { logic.miss }
}
def way = logic.way
}
class TrueLRU(n_ways: Int) extends ReplacementPolicy {
// True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others.
// The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits):
// [5] - 3 more recent than 2
// [4] - 3 more recent than 1
// [3] - 2 more recent than 1
// [2] - 3 more recent than 0
// [1] - 2 more recent than 0
// [0] - 1 more recent than 0
def nBits = (n_ways * (n_ways-1)) / 2
def perSet = true
private val state_reg = RegInit(0.U(nBits.W))
def state_read = WireDefault(state_reg)
private def extractMRUVec(state: UInt): Seq[UInt] = {
// Extract per-way information about which higher-indexed ways are more recently used
val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W)))
var lsb = 0
for (i <- 0 until n_ways-1) {
moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W))
lsb = lsb + (n_ways - i - 1)
}
moreRecentVec
}
def get_next_state(state: UInt, touch_way: UInt): UInt = {
val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W)))
val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix
val wayDec = UIntToOH(touch_way, n_ways)
// Compute next value of triangular matrix
// set the touched way as more recent than every other way
nextState.zipWithIndex.map { case (e, i) =>
e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) | wayDec)
}
nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1
}
def access(touch_way: UInt): Unit = {
state_reg := get_next_state(state_reg, touch_way)
}
def access(touch_ways: Seq[Valid[UInt]]): Unit = {
when (touch_ways.map(_.valid).orR) {
state_reg := get_next_state(state_reg, touch_ways)
}
for (i <- 1 until touch_ways.size) {
cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous")
}
}
def get_replace_way(state: UInt): UInt = {
val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix
// For each way, determine if all other ways are more recent
val mruWayDec = (0 until n_ways).map { i =>
val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR)
val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _))
upperMoreRecent && lowerMoreRecent
}
OHToUInt(mruWayDec)
}
def way = get_replace_way(state_reg)
def miss = access(way)
def hit = {}
@deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05")
def replace: UInt = way
}
class PseudoLRU(n_ways: Int) extends ReplacementPolicy {
// Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU
//
//
// - bits storage example for 4-way PLRU binary tree:
// bit[2]: ways 3+2 older than ways 1+0
// / \
// bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0
//
//
// - bits storage example for 3-way PLRU binary tree:
// bit[1]: way 2 older than ways 1+0
// \
// bit[0]: way 1 older than way 0
//
//
// - bits storage example for 8-way PLRU binary tree:
// bit[6]: ways 7-4 older than ways 3-0
// / \
// bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0
// / \ / \
// bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0
def nBits = n_ways - 1
def perSet = true
private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W))
def state_read = WireDefault(state_reg)
def access(touch_way: UInt): Unit = {
state_reg := get_next_state(state_reg, touch_way)
}
def access(touch_ways: Seq[Valid[UInt]]): Unit = {
when (touch_ways.map(_.valid).orR) {
state_reg := get_next_state(state_reg, touch_ways)
}
for (i <- 1 until touch_ways.size) {
cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous")
}
}
/** @param state state_reg bits for this sub-tree
* @param touch_way touched way encoded value bits for this sub-tree
* @param tree_nways number of ways in this sub-tree
*/
def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = {
require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways")
require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways")
if (tree_nways > 2) {
// we are at a branching node in the tree, so recurse
val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree
val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree
val set_left_older = !touch_way(log2Ceil(tree_nways)-1)
val left_subtree_state = state.extract(tree_nways-3, right_nways-1)
val right_subtree_state = state(right_nways-2, 0)
if (left_nways > 1) {
// we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees
Cat(set_left_older,
Mux(set_left_older,
left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree
get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer
Mux(set_left_older,
get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer
right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree
} else {
// we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree
Cat(set_left_older,
Mux(set_left_older,
get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer
right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree
}
} else if (tree_nways == 2) {
// we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value
!touch_way(0)
} else { // tree_nways <= 1
// we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires)
0.U(1.W)
}
}
def get_next_state(state: UInt, touch_way: UInt): UInt = {
val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways))
else touch_way.extract(log2Ceil(n_ways)-1,0)
get_next_state(state, touch_way_sized, n_ways)
}
/** @param state state_reg bits for this sub-tree
* @param tree_nways number of ways in this sub-tree
*/
def get_replace_way(state: UInt, tree_nways: Int): UInt = {
require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways")
// this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb
if (tree_nways > 2) {
// we are at a branching node in the tree, so recurse
val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree
val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree
val left_subtree_older = state(tree_nways-2)
val left_subtree_state = state.extract(tree_nways-3, right_nways-1)
val right_subtree_state = state(right_nways-2, 0)
if (left_nways > 1) {
// we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees
Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value
Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right
get_replace_way(left_subtree_state, left_nways), // recurse left
get_replace_way(right_subtree_state, right_nways))) // recurse right
} else {
// we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree
Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value
Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right
0.U(1.W),
get_replace_way(right_subtree_state, right_nways))) // recurse right
}
} else if (tree_nways == 2) {
// we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value
state(0)
} else { // tree_nways <= 1
// we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value
0.U(1.W)
}
}
def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways)
def way = get_replace_way(state_reg)
def miss = access(way)
def hit = {}
}
class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy {
val logic = new PseudoLRU(n_ways)
val state = SyncReadMem(n_sets, UInt(logic.nBits.W))
val current_state = Wire(UInt(logic.nBits.W))
val next_state = Wire(UInt(logic.nBits.W))
val plru_way = logic.get_replace_way(current_state)
def access(set: UInt) = {
current_state := state.read(set)
}
def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = {
val update_way = Mux(hit, way, plru_way)
next_state := logic.get_next_state(current_state, update_way)
when (valid) { state.write(set, next_state) }
}
def way = plru_way
}
class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy {
val logic = policy.toLowerCase match {
case "plru" => new PseudoLRU(n_ways)
case "lru" => new TrueLRU(n_ways)
case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t")
}
val state_vec =
if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line
else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W))))
def access(set: UInt, touch_way: UInt) = {
state_vec(set) := logic.get_next_state(state_vec(set), touch_way)
}
def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = {
require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways")
for (set <- 0 until n_sets) {
val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) =>
Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)}
when (set_touch_ways.map(_.valid).orR) {
state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways)
}
}
}
def way(set: UInt) = logic.get_replace_way(state_vec(set))
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) {
val plru = new PseudoLRU(n_ways)
// step
io.finished := RegNext(true.B, false.B)
val get_replace_ways = (0 until (1 << (n_ways-1))).map(state =>
plru.get_replace_way(state = state.U((n_ways-1).W)))
val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way =>
plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W))))
n_ways match {
case 2 => {
assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0))
assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1))
assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0))
assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1))
assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0))
assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1))
}
case 3 => {
assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0))
assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1))
assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2))
assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3))
assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0))
assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1))
assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2))
assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0))
assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1))
assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2))
assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0))
assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1))
assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2))
assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0))
assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1))
assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2))
}
case 4 => {
assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0))
assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1))
assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2))
assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3))
assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4))
assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5))
assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6))
assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7))
assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0))
assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1))
assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2))
assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3))
assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0))
assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1))
assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2))
assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3))
assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0))
assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1))
assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2))
assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3))
assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0))
assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1))
assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2))
assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3))
assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0))
assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1))
assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2))
assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3))
assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0))
assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1))
assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2))
assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3))
assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0))
assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1))
assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2))
assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3))
assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0))
assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1))
assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2))
assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3))
}
case 5 => {
assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0))
assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1))
assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2))
assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3))
assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4))
assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5))
assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6))
assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7))
assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8))
assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9))
assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10))
assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11))
assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12))
assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13))
assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14))
assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15))
assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0))
assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1))
assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2))
assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3))
assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4))
assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0))
assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1))
assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2))
assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3))
assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4))
assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0))
assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1))
assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2))
assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3))
assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4))
assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0))
assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1))
assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2))
assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3))
assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4))
assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0))
assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1))
assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2))
assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3))
assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4))
assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0))
assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1))
assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2))
assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3))
assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4))
assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0))
assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1))
assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2))
assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3))
assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4))
assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0))
assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1))
assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2))
assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3))
assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4))
assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0))
assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1))
assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2))
assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3))
assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4))
assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0))
assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1))
assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2))
assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3))
assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4))
assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0))
assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1))
assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2))
assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3))
assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4))
assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0))
assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1))
assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2))
assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3))
assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4))
assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0))
assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1))
assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2))
assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3))
assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4))
assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0))
assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1))
assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2))
assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3))
assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4))
assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0))
assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1))
assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2))
assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3))
assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4))
assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0))
assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1))
assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2))
assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3))
assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4))
}
case 6 => {
assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0))
assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1))
assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2))
assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3))
assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4))
assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5))
assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6))
assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7))
assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8))
assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9))
assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10))
assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11))
assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12))
assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13))
assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14))
assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15))
assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16))
assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17))
assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18))
assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19))
assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20))
assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21))
assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22))
assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23))
assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24))
assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25))
assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26))
assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27))
assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28))
assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29))
assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30))
assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31))
}
case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways")
}
}
File Consts.scala:
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket.constants
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
trait ScalarOpConstants {
val SZ_BR = 3
def BR_X = BitPat("b???")
def BR_EQ = 0.U(3.W)
def BR_NE = 1.U(3.W)
def BR_J = 2.U(3.W)
def BR_N = 3.U(3.W)
def BR_LT = 4.U(3.W)
def BR_GE = 5.U(3.W)
def BR_LTU = 6.U(3.W)
def BR_GEU = 7.U(3.W)
def A1_X = BitPat("b??")
def A1_ZERO = 0.U(2.W)
def A1_RS1 = 1.U(2.W)
def A1_PC = 2.U(2.W)
def A1_RS1SHL = 3.U(2.W)
def IMM_X = BitPat("b???")
def IMM_S = 0.U(3.W)
def IMM_SB = 1.U(3.W)
def IMM_U = 2.U(3.W)
def IMM_UJ = 3.U(3.W)
def IMM_I = 4.U(3.W)
def IMM_Z = 5.U(3.W)
def A2_X = BitPat("b???")
def A2_ZERO = 0.U(3.W)
def A2_SIZE = 1.U(3.W)
def A2_RS2 = 2.U(3.W)
def A2_IMM = 3.U(3.W)
def A2_RS2OH = 4.U(3.W)
def A2_IMMOH = 5.U(3.W)
def X = BitPat("b?")
def N = BitPat("b0")
def Y = BitPat("b1")
val SZ_DW = 1
def DW_X = X
def DW_32 = false.B
def DW_64 = true.B
def DW_XPR = DW_64
}
trait MemoryOpConstants {
val NUM_XA_OPS = 9
val M_SZ = 5
def M_X = BitPat("b?????");
def M_XRD = "b00000".U; // int load
def M_XWR = "b00001".U; // int store
def M_PFR = "b00010".U; // prefetch with intent to read
def M_PFW = "b00011".U; // prefetch with intent to write
def M_XA_SWAP = "b00100".U
def M_FLUSH_ALL = "b00101".U // flush all lines
def M_XLR = "b00110".U
def M_XSC = "b00111".U
def M_XA_ADD = "b01000".U
def M_XA_XOR = "b01001".U
def M_XA_OR = "b01010".U
def M_XA_AND = "b01011".U
def M_XA_MIN = "b01100".U
def M_XA_MAX = "b01101".U
def M_XA_MINU = "b01110".U
def M_XA_MAXU = "b01111".U
def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions
def M_PWR = "b10001".U // partial (masked) store
def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions
def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions
def M_SFENCE = "b10100".U // SFENCE.VMA
def M_HFENCEV = "b10101".U // HFENCE.VVMA
def M_HFENCEG = "b10110".U // HFENCE.GVMA
def M_WOK = "b10111".U // check write permissions but don't perform a write
def M_HLVX = "b10000".U // HLVX instruction
def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND)
def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU)
def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd)
def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW
def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd)
def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd)
def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
}
File TLB.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.devices.debug.DebugModuleKey
import freechips.rocketchip.diplomacy.RegionType
import freechips.rocketchip.subsystem.CacheBlockBytes
import freechips.rocketchip.tile.{CoreModule, CoreBundle}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.{OptimizationBarrier, SetAssocLRU, PseudoLRU, PopCountAtLeast, property}
import freechips.rocketchip.util.BooleanToAugmentedBoolean
import freechips.rocketchip.util.IntToAugmentedInt
import freechips.rocketchip.util.UIntToAugmentedUInt
import freechips.rocketchip.util.UIntIsOneOf
import freechips.rocketchip.util.SeqToAugmentedSeq
import freechips.rocketchip.util.SeqBoolBitwiseOps
case object ASIdBits extends Field[Int](0)
case object VMIdBits extends Field[Int](0)
/** =SFENCE=
* rs1 rs2
* {{{
* 0 0 -> flush All
* 0 1 -> flush by ASID
* 1 1 -> flush by ADDR
* 1 0 -> flush by ADDR and ASID
* }}}
* {{{
* If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces.
* If rs1=x0 and rs2!=x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see Section 4.3.1) are not ordered.
* If rs1!=x0 and rs2=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for all address spaces.
* If rs1!=x0 and rs2!=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered.
* }}}
*/
class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) {
val rs1 = Bool()
val rs2 = Bool()
val addr = UInt(vaddrBits.W)
val asid = UInt((asIdBits max 1).W) // TODO zero-width
val hv = Bool()
val hg = Bool()
}
class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) {
/** request address from CPU. */
val vaddr = UInt(vaddrBitsExtended.W)
/** don't lookup TLB, bypass vaddr as paddr */
val passthrough = Bool()
/** granularity */
val size = UInt(log2Ceil(lgMaxSize + 1).W)
/** memory command. */
val cmd = Bits(M_SZ.W)
val prv = UInt(PRV.SZ.W)
/** virtualization mode */
val v = Bool()
}
class TLBExceptions extends Bundle {
val ld = Bool()
val st = Bool()
val inst = Bool()
}
class TLBResp(lgMaxSize: Int = 3)(implicit p: Parameters) extends CoreBundle()(p) {
// lookup responses
val miss = Bool()
/** physical address */
val paddr = UInt(paddrBits.W)
val gpa = UInt(vaddrBitsExtended.W)
val gpa_is_pte = Bool()
/** page fault exception */
val pf = new TLBExceptions
/** guest page fault exception */
val gf = new TLBExceptions
/** access exception */
val ae = new TLBExceptions
/** misaligned access exception */
val ma = new TLBExceptions
/** if this address is cacheable */
val cacheable = Bool()
/** if caches must allocate this address */
val must_alloc = Bool()
/** if this address is prefetchable for caches*/
val prefetchable = Bool()
/** size/cmd of request that generated this response*/
val size = UInt(log2Ceil(lgMaxSize + 1).W)
val cmd = UInt(M_SZ.W)
}
class TLBEntryData(implicit p: Parameters) extends CoreBundle()(p) {
val ppn = UInt(ppnBits.W)
/** pte.u user */
val u = Bool()
/** pte.g global */
val g = Bool()
/** access exception.
* D$ -> PTW -> TLB AE
* Alignment failed.
*/
val ae_ptw = Bool()
val ae_final = Bool()
val ae_stage2 = Bool()
/** page fault */
val pf = Bool()
/** guest page fault */
val gf = Bool()
/** supervisor write */
val sw = Bool()
/** supervisor execute */
val sx = Bool()
/** supervisor read */
val sr = Bool()
/** hypervisor write */
val hw = Bool()
/** hypervisor excute */
val hx = Bool()
/** hypervisor read */
val hr = Bool()
/** prot_w */
val pw = Bool()
/** prot_x */
val px = Bool()
/** prot_r */
val pr = Bool()
/** PutPartial */
val ppp = Bool()
/** AMO logical */
val pal = Bool()
/** AMO arithmetic */
val paa = Bool()
/** get/put effects */
val eff = Bool()
/** cacheable */
val c = Bool()
/** fragmented_superpage support */
val fragmented_superpage = Bool()
}
/** basic cell for TLB data */
class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boolean)(implicit p: Parameters) extends CoreBundle()(p) {
require(nSectors == 1 || !superpage)
require(!superpageOnly || superpage)
val level = UInt(log2Ceil(pgLevels).W)
/** use vpn as tag */
val tag_vpn = UInt(vpnBits.W)
/** tag in vitualization mode */
val tag_v = Bool()
/** entry data */
val data = Vec(nSectors, UInt(new TLBEntryData().getWidth.W))
/** valid bit */
val valid = Vec(nSectors, Bool())
/** returns all entry data in this entry */
def entry_data = data.map(_.asTypeOf(new TLBEntryData))
/** returns the index of sector */
private def sectorIdx(vpn: UInt) = vpn.extract(nSectors.log2-1, 0)
/** returns the entry data matched with this vpn*/
def getData(vpn: UInt) = OptimizationBarrier(data(sectorIdx(vpn)).asTypeOf(new TLBEntryData))
/** returns whether a sector hits */
def sectorHit(vpn: UInt, virtual: Bool) = valid.orR && sectorTagMatch(vpn, virtual)
/** returns whether tag matches vpn */
def sectorTagMatch(vpn: UInt, virtual: Bool) = (((tag_vpn ^ vpn) >> nSectors.log2) === 0.U) && (tag_v === virtual)
/** returns hit signal */
def hit(vpn: UInt, virtual: Bool): Bool = {
if (superpage && usingVM) {
var tagMatch = valid.head && (tag_v === virtual)
for (j <- 0 until pgLevels) {
val base = (pgLevels - 1 - j) * pgLevelBits
val n = pgLevelBits + (if (j == 0) hypervisorExtraAddrBits else 0)
val ignore = level < j.U || (superpageOnly && j == pgLevels - 1).B
tagMatch = tagMatch && (ignore || (tag_vpn ^ vpn)(base + n - 1, base) === 0.U)
}
tagMatch
} else {
val idx = sectorIdx(vpn)
valid(idx) && sectorTagMatch(vpn, virtual)
}
}
/** returns the ppn of the input TLBEntryData */
def ppn(vpn: UInt, data: TLBEntryData) = {
val supervisorVPNBits = pgLevels * pgLevelBits
if (superpage && usingVM) {
var res = data.ppn >> pgLevelBits*(pgLevels - 1)
for (j <- 1 until pgLevels) {
val ignore = level < j.U || (superpageOnly && j == pgLevels - 1).B
res = Cat(res, (Mux(ignore, vpn, 0.U) | data.ppn)(supervisorVPNBits - j*pgLevelBits - 1, supervisorVPNBits - (j + 1)*pgLevelBits))
}
res
} else {
data.ppn
}
}
/** does the refill
*
* find the target entry with vpn tag
* and replace the target entry with the input entry data
*/
def insert(vpn: UInt, virtual: Bool, level: UInt, entry: TLBEntryData): Unit = {
this.tag_vpn := vpn
this.tag_v := virtual
this.level := level.extract(log2Ceil(pgLevels - superpageOnly.toInt)-1, 0)
val idx = sectorIdx(vpn)
valid(idx) := true.B
data(idx) := entry.asUInt
}
def invalidate(): Unit = { valid.foreach(_ := false.B) }
def invalidate(virtual: Bool): Unit = {
for ((v, e) <- valid zip entry_data)
when (tag_v === virtual) { v := false.B }
}
def invalidateVPN(vpn: UInt, virtual: Bool): Unit = {
if (superpage) {
when (hit(vpn, virtual)) { invalidate() }
} else {
when (sectorTagMatch(vpn, virtual)) {
for (((v, e), i) <- (valid zip entry_data).zipWithIndex)
when (tag_v === virtual && i.U === sectorIdx(vpn)) { v := false.B }
}
}
// For fragmented superpage mappings, we assume the worst (largest)
// case, and zap entries whose most-significant VPNs match
when (((tag_vpn ^ vpn) >> (pgLevelBits * (pgLevels - 1))) === 0.U) {
for ((v, e) <- valid zip entry_data)
when (tag_v === virtual && e.fragmented_superpage) { v := false.B }
}
}
def invalidateNonGlobal(virtual: Bool): Unit = {
for ((v, e) <- valid zip entry_data)
when (tag_v === virtual && !e.g) { v := false.B }
}
}
/** TLB config
*
* @param nSets the number of sets of PTE, follow [[ICacheParams.nSets]]
* @param nWays the total number of wayss of PTE, follow [[ICacheParams.nWays]]
* @param nSectors the number of ways in a single PTE TLBEntry
* @param nSuperpageEntries the number of SuperpageEntries
*/
case class TLBConfig(
nSets: Int,
nWays: Int,
nSectors: Int = 4,
nSuperpageEntries: Int = 4)
/** =Overview=
* [[TLB]] is a TLB template which contains PMA logic and PMP checker.
*
* TLB caches PTE and accelerates the address translation process.
* When tlb miss happens, ask PTW(L2TLB) for Page Table Walk.
* Perform PMP and PMA check during the translation and throw exception if there were any.
*
* ==Cache Structure==
* - Sectored Entry (PTE)
* - set-associative or direct-mapped
* - nsets = [[TLBConfig.nSets]]
* - nways = [[TLBConfig.nWays]] / [[TLBConfig.nSectors]]
* - PTEEntry( sectors = [[TLBConfig.nSectors]] )
* - LRU(if set-associative)
*
* - Superpage Entry(superpage PTE)
* - fully associative
* - nsets = [[TLBConfig.nSuperpageEntries]]
* - PTEEntry(sectors = 1)
* - PseudoLRU
*
* - Special Entry(PTE across PMP)
* - nsets = 1
* - PTEEntry(sectors = 1)
*
* ==Address structure==
* {{{
* |vaddr |
* |ppn/vpn | pgIndex |
* | | |
* | |nSets |nSector | |}}}
*
* ==State Machine==
* {{{
* s_ready: ready to accept request from CPU.
* s_request: when L1TLB(this) miss, send request to PTW(L2TLB), .
* s_wait: wait for PTW to refill L1TLB.
* s_wait_invalidate: L1TLB is waiting for respond from PTW, but L1TLB will invalidate respond from PTW.}}}
*
* ==PMP==
* pmp check
* - special_entry: always check
* - other entry: check on refill
*
* ==Note==
* PMA consume diplomacy parameter generate physical memory address checking logic
*
* Boom use Rocket ITLB, and its own DTLB.
*
* Accelerators:{{{
* sha3: DTLB
* gemmini: DTLB
* hwacha: DTLB*2+ITLB}}}
* @param instruction true for ITLB, false for DTLB
* @param lgMaxSize @todo seems granularity
* @param cfg [[TLBConfig]]
* @param edge collect SoC metadata.
*/
class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
override def desiredName = if (instruction) "ITLB" else "DTLB"
val io = IO(new Bundle {
/** request from Core */
val req = Flipped(Decoupled(new TLBReq(lgMaxSize)))
/** response to Core */
val resp = Output(new TLBResp(lgMaxSize))
/** SFence Input */
val sfence = Flipped(Valid(new SFenceReq))
/** IO to PTW */
val ptw = new TLBPTWIO
/** suppress a TLB refill, one cycle after a miss */
val kill = Input(Bool())
})
io.ptw.customCSRs := DontCare
val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits)
val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits)
/** index for sectored_Entry */
val memIdx = vpn.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2)
/** TLB Entry */
val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nWays / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false))))
/** Superpage Entry */
val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new TLBEntry(1, true, true)))
/** Special Entry
*
* If PMP granularity is less than page size, thus need additional "special" entry manage PMP.
*/
val special_entry = (!pageGranularityPMPs).option(Reg(new TLBEntry(1, true, false)))
def ordinary_entries = sectored_entries(memIdx) ++ superpage_entries
def all_entries = ordinary_entries ++ special_entry
def all_real_entries = sectored_entries.flatten ++ superpage_entries ++ special_entry
val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4)
val state = RegInit(s_ready)
// use vpn as refill_tag
val r_refill_tag = Reg(UInt(vpnBits.W))
val r_superpage_repl_addr = Reg(UInt(log2Ceil(superpage_entries.size).W))
val r_sectored_repl_addr = Reg(UInt(log2Ceil(sectored_entries.head.size).W))
val r_sectored_hit = Reg(Valid(UInt(log2Ceil(sectored_entries.head.size).W)))
val r_superpage_hit = Reg(Valid(UInt(log2Ceil(superpage_entries.size).W)))
val r_vstage1_en = Reg(Bool())
val r_stage2_en = Reg(Bool())
val r_need_gpa = Reg(Bool())
val r_gpa_valid = Reg(Bool())
val r_gpa = Reg(UInt(vaddrBits.W))
val r_gpa_vpn = Reg(UInt(vpnBits.W))
val r_gpa_is_pte = Reg(Bool())
/** privilege mode */
val priv = io.req.bits.prv
val priv_v = usingHypervisor.B && io.req.bits.v
val priv_s = priv(0)
// user mode and supervisor mode
val priv_uses_vm = priv <= PRV.S.U
val satp = Mux(priv_v, io.ptw.vsatp, io.ptw.ptbr)
val stage1_en = usingVM.B && satp.mode(satp.mode.getWidth-1)
/** VS-stage translation enable */
val vstage1_en = usingHypervisor.B && priv_v && io.ptw.vsatp.mode(io.ptw.vsatp.mode.getWidth-1)
/** G-stage translation enable */
val stage2_en = usingHypervisor.B && priv_v && io.ptw.hgatp.mode(io.ptw.hgatp.mode.getWidth-1)
/** Enable Virtual Memory when:
* 1. statically configured
* 1. satp highest bits enabled
* i. RV32:
* - 0 -> Bare
* - 1 -> SV32
* i. RV64:
* - 0000 -> Bare
* - 1000 -> SV39
* - 1001 -> SV48
* - 1010 -> SV57
* - 1011 -> SV64
* 1. In virtualization mode, vsatp highest bits enabled
* 1. priv mode in U and S.
* 1. in H & M mode, disable VM.
* 1. no passthrough(micro-arch defined.)
*
* @see RV-priv spec 4.1.11 Supervisor Address Translation and Protection (satp) Register
* @see RV-priv spec 8.2.18 Virtual Supervisor Address Translation and Protection Register (vsatp)
*/
val vm_enabled = (stage1_en || stage2_en) && priv_uses_vm && !io.req.bits.passthrough
// flush guest entries on vsatp.MODE Bare <-> SvXX transitions
val v_entries_use_stage1 = RegInit(false.B)
val vsatp_mode_mismatch = priv_v && (vstage1_en =/= v_entries_use_stage1) && !io.req.bits.passthrough
// share a single physical memory attribute checker (unshare if critical path)
val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0)
/** refill signal */
val do_refill = usingVM.B && io.ptw.resp.valid
/** sfence invalidate refill */
val invalidate_refill = state.isOneOf(s_request /* don't care */, s_wait_invalidate) || io.sfence.valid
// PMP
val mpu_ppn = Mux(do_refill, refill_ppn,
Mux(vm_enabled && special_entry.nonEmpty.B, special_entry.map(e => e.ppn(vpn, e.getData(vpn))).getOrElse(0.U), io.req.bits.vaddr >> pgIdxBits))
val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0))
val mpu_priv = Mux[UInt](usingVM.B && (do_refill || io.req.bits.passthrough /* PTW */), PRV.S.U, Cat(io.ptw.status.debug, priv))
val pmp = Module(new PMPChecker(lgMaxSize))
pmp.io.addr := mpu_physaddr
pmp.io.size := io.req.bits.size
pmp.io.pmp := (io.ptw.pmp: Seq[PMP])
pmp.io.prv := mpu_priv
val pma = Module(new PMAChecker(edge.manager)(p))
pma.io.paddr := mpu_physaddr
// todo: using DataScratchpad doesn't support cacheable.
val cacheable = pma.io.resp.cacheable && (instruction || !usingDataScratchpad).B
val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits, 1 << lgMaxSize)(mpu_physaddr).homogeneous
// In M mode, if access DM address(debug module program buffer)
val deny_access_to_debug = mpu_priv <= PRV.M.U && p(DebugModuleKey).map(dmp => dmp.address.contains(mpu_physaddr)).getOrElse(false.B)
val prot_r = pma.io.resp.r && !deny_access_to_debug && pmp.io.r
val prot_w = pma.io.resp.w && !deny_access_to_debug && pmp.io.w
val prot_pp = pma.io.resp.pp
val prot_al = pma.io.resp.al
val prot_aa = pma.io.resp.aa
val prot_x = pma.io.resp.x && !deny_access_to_debug && pmp.io.x
val prot_eff = pma.io.resp.eff
// hit check
val sector_hits = sectored_entries(memIdx).map(_.sectorHit(vpn, priv_v))
val superpage_hits = superpage_entries.map(_.hit(vpn, priv_v))
val hitsVec = all_entries.map(vm_enabled && _.hit(vpn, priv_v))
val real_hits = hitsVec.asUInt
val hits = Cat(!vm_enabled, real_hits)
// use ptw response to refill
// permission bit arrays
when (do_refill) {
val pte = io.ptw.resp.bits.pte
val refill_v = r_vstage1_en || r_stage2_en
val newEntry = Wire(new TLBEntryData)
newEntry.ppn := pte.ppn
newEntry.c := cacheable
newEntry.u := pte.u
newEntry.g := pte.g && pte.v
newEntry.ae_ptw := io.ptw.resp.bits.ae_ptw
newEntry.ae_final := io.ptw.resp.bits.ae_final
newEntry.ae_stage2 := io.ptw.resp.bits.ae_final && io.ptw.resp.bits.gpa_is_pte && r_stage2_en
newEntry.pf := io.ptw.resp.bits.pf
newEntry.gf := io.ptw.resp.bits.gf
newEntry.hr := io.ptw.resp.bits.hr
newEntry.hw := io.ptw.resp.bits.hw
newEntry.hx := io.ptw.resp.bits.hx
newEntry.sr := pte.sr()
newEntry.sw := pte.sw()
newEntry.sx := pte.sx()
newEntry.pr := prot_r
newEntry.pw := prot_w
newEntry.px := prot_x
newEntry.ppp := prot_pp
newEntry.pal := prot_al
newEntry.paa := prot_aa
newEntry.eff := prot_eff
newEntry.fragmented_superpage := io.ptw.resp.bits.fragmented_superpage
// refill special_entry
when (special_entry.nonEmpty.B && !io.ptw.resp.bits.homogeneous) {
special_entry.foreach(_.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry))
}.elsewhen (io.ptw.resp.bits.level < (pgLevels-1).U) {
val waddr = Mux(r_superpage_hit.valid && usingHypervisor.B, r_superpage_hit.bits, r_superpage_repl_addr)
for ((e, i) <- superpage_entries.zipWithIndex) when (r_superpage_repl_addr === i.U) {
e.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry)
when (invalidate_refill) { e.invalidate() }
}
// refill sectored_hit
}.otherwise {
val r_memIdx = r_refill_tag.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2)
val waddr = Mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr)
for ((e, i) <- sectored_entries(r_memIdx).zipWithIndex) when (waddr === i.U) {
when (!r_sectored_hit.valid) { e.invalidate() }
e.insert(r_refill_tag, refill_v, 0.U, newEntry)
when (invalidate_refill) { e.invalidate() }
}
}
r_gpa_valid := io.ptw.resp.bits.gpa.valid
r_gpa := io.ptw.resp.bits.gpa.bits
r_gpa_is_pte := io.ptw.resp.bits.gpa_is_pte
}
// get all entries data.
val entries = all_entries.map(_.getData(vpn))
val normal_entries = entries.take(ordinary_entries.size)
// parallel query PPN from [[all_entries]], if VM not enabled return VPN instead
val ppn = Mux1H(hitsVec :+ !vm_enabled, (all_entries zip entries).map{ case (entry, data) => entry.ppn(vpn, data) } :+ vpn(ppnBits-1, 0))
val nPhysicalEntries = 1 + special_entry.size
// generally PTW misaligned load exception.
val ptw_ae_array = Cat(false.B, entries.map(_.ae_ptw).asUInt)
val final_ae_array = Cat(false.B, entries.map(_.ae_final).asUInt)
val ptw_pf_array = Cat(false.B, entries.map(_.pf).asUInt)
val ptw_gf_array = Cat(false.B, entries.map(_.gf).asUInt)
val sum = Mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum)
// if in hypervisor/machine mode, cannot read/write user entries.
// if in superviosr/user mode, "If the SUM bit in the sstatus register is set, supervisor mode software may also access pages with U=1.(from spec)"
val priv_rw_ok = Mux(!priv_s || sum, entries.map(_.u).asUInt, 0.U) | Mux(priv_s, ~entries.map(_.u).asUInt, 0.U)
// if in hypervisor/machine mode, other than user pages, all pages are executable.
// if in superviosr/user mode, only user page can execute.
val priv_x_ok = Mux(priv_s, ~entries.map(_.u).asUInt, entries.map(_.u).asUInt)
val stage1_bypass = Fill(entries.size, usingHypervisor.B) & (Fill(entries.size, !stage1_en) | entries.map(_.ae_stage2).asUInt)
val mxr = io.ptw.status.mxr | Mux(priv_v, io.ptw.gstatus.mxr, false.B)
// "The vsstatus field MXR, which makes execute-only pages readable, only overrides VS-stage page protection.(from spec)"
val r_array = Cat(true.B, (priv_rw_ok & (entries.map(_.sr).asUInt | Mux(mxr, entries.map(_.sx).asUInt, 0.U))) | stage1_bypass)
val w_array = Cat(true.B, (priv_rw_ok & entries.map(_.sw).asUInt) | stage1_bypass)
val x_array = Cat(true.B, (priv_x_ok & entries.map(_.sx).asUInt) | stage1_bypass)
val stage2_bypass = Fill(entries.size, !stage2_en)
val hr_array = Cat(true.B, entries.map(_.hr).asUInt | Mux(io.ptw.status.mxr, entries.map(_.hx).asUInt, 0.U) | stage2_bypass)
val hw_array = Cat(true.B, entries.map(_.hw).asUInt | stage2_bypass)
val hx_array = Cat(true.B, entries.map(_.hx).asUInt | stage2_bypass)
// These array is for each TLB entries.
// user mode can read: PMA OK, TLB OK, AE OK
val pr_array = Cat(Fill(nPhysicalEntries, prot_r), normal_entries.map(_.pr).asUInt) & ~(ptw_ae_array | final_ae_array)
// user mode can write: PMA OK, TLB OK, AE OK
val pw_array = Cat(Fill(nPhysicalEntries, prot_w), normal_entries.map(_.pw).asUInt) & ~(ptw_ae_array | final_ae_array)
// user mode can write: PMA OK, TLB OK, AE OK
val px_array = Cat(Fill(nPhysicalEntries, prot_x), normal_entries.map(_.px).asUInt) & ~(ptw_ae_array | final_ae_array)
// put effect
val eff_array = Cat(Fill(nPhysicalEntries, prot_eff), normal_entries.map(_.eff).asUInt)
// cacheable
val c_array = Cat(Fill(nPhysicalEntries, cacheable), normal_entries.map(_.c).asUInt)
// put partial
val ppp_array = Cat(Fill(nPhysicalEntries, prot_pp), normal_entries.map(_.ppp).asUInt)
// atomic arithmetic
val paa_array = Cat(Fill(nPhysicalEntries, prot_aa), normal_entries.map(_.paa).asUInt)
// atomic logic
val pal_array = Cat(Fill(nPhysicalEntries, prot_al), normal_entries.map(_.pal).asUInt)
val ppp_array_if_cached = ppp_array | c_array
val paa_array_if_cached = paa_array | (if(usingAtomicsInCache) c_array else 0.U)
val pal_array_if_cached = pal_array | (if(usingAtomicsInCache) c_array else 0.U)
val prefetchable_array = Cat((cacheable && homogeneous) << (nPhysicalEntries-1), normal_entries.map(_.c).asUInt)
// vaddr misaligned: vaddr[1:0]=b00
val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1.U)).orR
def badVA(guestPA: Boolean): Bool = {
val additionalPgLevels = (if (guestPA) io.ptw.hgatp else satp).additionalPgLevels
val extraBits = if (guestPA) hypervisorExtraAddrBits else 0
val signed = !guestPA
val nPgLevelChoices = pgLevels - minPgLevels + 1
val minVAddrBits = pgIdxBits + minPgLevels * pgLevelBits + extraBits
(for (i <- 0 until nPgLevelChoices) yield {
val mask = ((BigInt(1) << vaddrBitsExtended) - (BigInt(1) << (minVAddrBits + i * pgLevelBits - signed.toInt))).U
val maskedVAddr = io.req.bits.vaddr & mask
additionalPgLevels === i.U && !(maskedVAddr === 0.U || signed.B && maskedVAddr === mask)
}).orR
}
val bad_gpa =
if (!usingHypervisor) false.B
else vm_enabled && !stage1_en && badVA(true)
val bad_va =
if (!usingVM || (minPgLevels == pgLevels && vaddrBits == vaddrBitsExtended)) false.B
else vm_enabled && stage1_en && badVA(false)
val cmd_lrsc = usingAtomics.B && io.req.bits.cmd.isOneOf(M_XLR, M_XSC)
val cmd_amo_logical = usingAtomics.B && isAMOLogical(io.req.bits.cmd)
val cmd_amo_arithmetic = usingAtomics.B && isAMOArithmetic(io.req.bits.cmd)
val cmd_put_partial = io.req.bits.cmd === M_PWR
val cmd_read = isRead(io.req.bits.cmd)
val cmd_readx = usingHypervisor.B && io.req.bits.cmd === M_HLVX
val cmd_write = isWrite(io.req.bits.cmd)
val cmd_write_perms = cmd_write ||
io.req.bits.cmd.isOneOf(M_FLUSH_ALL, M_WOK) // not a write, but needs write permissions
val lrscAllowed = Mux((usingDataScratchpad || usingAtomicsOnlyForIO).B, 0.U, c_array)
val ae_array =
Mux(misaligned, eff_array, 0.U) |
Mux(cmd_lrsc, ~lrscAllowed, 0.U)
// access exception needs SoC information from PMA
val ae_ld_array = Mux(cmd_read, ae_array | ~pr_array, 0.U)
val ae_st_array =
Mux(cmd_write_perms, ae_array | ~pw_array, 0.U) |
Mux(cmd_put_partial, ~ppp_array_if_cached, 0.U) |
Mux(cmd_amo_logical, ~pal_array_if_cached, 0.U) |
Mux(cmd_amo_arithmetic, ~paa_array_if_cached, 0.U)
val must_alloc_array =
Mux(cmd_put_partial, ~ppp_array, 0.U) |
Mux(cmd_amo_logical, ~pal_array, 0.U) |
Mux(cmd_amo_arithmetic, ~paa_array, 0.U) |
Mux(cmd_lrsc, ~0.U(pal_array.getWidth.W), 0.U)
val pf_ld_array = Mux(cmd_read, ((~Mux(cmd_readx, x_array, r_array) & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array, 0.U)
val pf_st_array = Mux(cmd_write_perms, ((~w_array & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array, 0.U)
val pf_inst_array = ((~x_array & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array
val gf_ld_array = Mux(priv_v && cmd_read, (~Mux(cmd_readx, hx_array, hr_array) | ptw_gf_array) & ~ptw_ae_array, 0.U)
val gf_st_array = Mux(priv_v && cmd_write_perms, (~hw_array | ptw_gf_array) & ~ptw_ae_array, 0.U)
val gf_inst_array = Mux(priv_v, (~hx_array | ptw_gf_array) & ~ptw_ae_array, 0.U)
val gpa_hits = {
val need_gpa_mask = if (instruction) gf_inst_array else gf_ld_array | gf_st_array
val hit_mask = Fill(ordinary_entries.size, r_gpa_valid && r_gpa_vpn === vpn) | Fill(all_entries.size, !vstage1_en)
hit_mask | ~need_gpa_mask(all_entries.size-1, 0)
}
val tlb_hit_if_not_gpa_miss = real_hits.orR
val tlb_hit = (real_hits & gpa_hits).orR
// leads to s_request
val tlb_miss = vm_enabled && !vsatp_mode_mismatch && !bad_va && !tlb_hit
val sectored_plru = new SetAssocLRU(cfg.nSets, sectored_entries.head.size, "plru")
val superpage_plru = new PseudoLRU(superpage_entries.size)
when (io.req.valid && vm_enabled) {
// replace
when (sector_hits.orR) { sectored_plru.access(memIdx, OHToUInt(sector_hits)) }
when (superpage_hits.orR) { superpage_plru.access(OHToUInt(superpage_hits)) }
}
// Superpages create the possibility that two entries in the TLB may match.
// This corresponds to a software bug, but we can't return complete garbage;
// we must return either the old translation or the new translation. This
// isn't compatible with the Mux1H approach. So, flush the TLB and report
// a miss on duplicate entries.
val multipleHits = PopCountAtLeast(real_hits, 2)
// only pull up req.ready when this is s_ready state.
io.req.ready := state === s_ready
// page fault
io.resp.pf.ld := (bad_va && cmd_read) || (pf_ld_array & hits).orR
io.resp.pf.st := (bad_va && cmd_write_perms) || (pf_st_array & hits).orR
io.resp.pf.inst := bad_va || (pf_inst_array & hits).orR
// guest page fault
io.resp.gf.ld := (bad_gpa && cmd_read) || (gf_ld_array & hits).orR
io.resp.gf.st := (bad_gpa && cmd_write_perms) || (gf_st_array & hits).orR
io.resp.gf.inst := bad_gpa || (gf_inst_array & hits).orR
// access exception
io.resp.ae.ld := (ae_ld_array & hits).orR
io.resp.ae.st := (ae_st_array & hits).orR
io.resp.ae.inst := (~px_array & hits).orR
// misaligned
io.resp.ma.ld := misaligned && cmd_read
io.resp.ma.st := misaligned && cmd_write
io.resp.ma.inst := false.B // this is up to the pipeline to figure out
io.resp.cacheable := (c_array & hits).orR
io.resp.must_alloc := (must_alloc_array & hits).orR
io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB || m.supportsHint).B
io.resp.miss := do_refill || vsatp_mode_mismatch || tlb_miss || multipleHits
io.resp.paddr := Cat(ppn, io.req.bits.vaddr(pgIdxBits-1, 0))
io.resp.size := io.req.bits.size
io.resp.cmd := io.req.bits.cmd
io.resp.gpa_is_pte := vstage1_en && r_gpa_is_pte
io.resp.gpa := {
val page = Mux(!vstage1_en, Cat(bad_gpa, vpn), r_gpa >> pgIdxBits)
val offset = Mux(io.resp.gpa_is_pte, r_gpa(pgIdxBits-1, 0), io.req.bits.vaddr(pgIdxBits-1, 0))
Cat(page, offset)
}
io.ptw.req.valid := state === s_request
io.ptw.req.bits.valid := !io.kill
io.ptw.req.bits.bits.addr := r_refill_tag
io.ptw.req.bits.bits.vstage1 := r_vstage1_en
io.ptw.req.bits.bits.stage2 := r_stage2_en
io.ptw.req.bits.bits.need_gpa := r_need_gpa
if (usingVM) {
when(io.ptw.req.fire && io.ptw.req.bits.valid) {
r_gpa_valid := false.B
r_gpa_vpn := r_refill_tag
}
val sfence = io.sfence.valid
// this is [[s_ready]]
// handle miss/hit at the first cycle.
// if miss, request PTW(L2TLB).
when (io.req.fire && tlb_miss) {
state := s_request
r_refill_tag := vpn
r_need_gpa := tlb_hit_if_not_gpa_miss
r_vstage1_en := vstage1_en
r_stage2_en := stage2_en
r_superpage_repl_addr := replacementEntry(superpage_entries, superpage_plru.way)
r_sectored_repl_addr := replacementEntry(sectored_entries(memIdx), sectored_plru.way(memIdx))
r_sectored_hit.valid := sector_hits.orR
r_sectored_hit.bits := OHToUInt(sector_hits)
r_superpage_hit.valid := superpage_hits.orR
r_superpage_hit.bits := OHToUInt(superpage_hits)
}
// Handle SFENCE.VMA when send request to PTW.
// SFENCE.VMA io.ptw.req.ready kill
// ? ? 1
// 0 0 0
// 0 1 0 -> s_wait
// 1 0 0 -> s_wait_invalidate
// 1 0 0 -> s_ready
when (state === s_request) {
// SFENCE.VMA will kill TLB entries based on rs1 and rs2. It will take 1 cycle.
when (sfence) { state := s_ready }
// here should be io.ptw.req.fire, but assert(io.ptw.req.ready === true.B)
// fire -> s_wait
when (io.ptw.req.ready) { state := Mux(sfence, s_wait_invalidate, s_wait) }
// If CPU kills request(frontend.s2_redirect)
when (io.kill) { state := s_ready }
}
// sfence in refill will results in invalidate
when (state === s_wait && sfence) {
state := s_wait_invalidate
}
// after CPU acquire response, go back to s_ready.
when (io.ptw.resp.valid) {
state := s_ready
}
// SFENCE processing logic.
when (sfence) {
assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn)
for (e <- all_real_entries) {
val hv = usingHypervisor.B && io.sfence.bits.hv
val hg = usingHypervisor.B && io.sfence.bits.hg
when (!hg && io.sfence.bits.rs1) { e.invalidateVPN(vpn, hv) }
.elsewhen (!hg && io.sfence.bits.rs2) { e.invalidateNonGlobal(hv) }
.otherwise { e.invalidate(hv || hg) }
}
}
when(io.req.fire && vsatp_mode_mismatch) {
all_real_entries.foreach(_.invalidate(true.B))
v_entries_use_stage1 := vstage1_en
}
when (multipleHits || reset.asBool) {
all_real_entries.foreach(_.invalidate())
}
ccover(io.ptw.req.fire, "MISS", "TLB miss")
ccover(io.ptw.req.valid && !io.ptw.req.ready, "PTW_STALL", "TLB miss, but PTW busy")
ccover(state === s_wait_invalidate, "SFENCE_DURING_REFILL", "flush TLB during TLB refill")
ccover(sfence && !io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_ALL", "flush TLB")
ccover(sfence && !io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_ASID", "flush TLB ASID")
ccover(sfence && io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_LINE", "flush TLB line")
ccover(sfence && io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_LINE_ASID", "flush TLB line/ASID")
ccover(multipleHits, "MULTIPLE_HITS", "Two matching translations in TLB")
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"${if (instruction) "I" else "D"}TLB_$label", "MemorySystem;;" + desc)
/** Decides which entry to be replaced
*
* If there is a invalid entry, replace it with priorityencoder;
* if not, replace the alt entry
*
* @return mask for TLBEntry replacement
*/
def replacementEntry(set: Seq[TLBEntry], alt: UInt) = {
val valids = set.map(_.valid.orR).asUInt
Mux(valids.andR, alt, PriorityEncoder(~valids))
}
}
File TLBPermissions.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder}
import freechips.rocketchip.tilelink.TLManagerParameters
case class TLBPermissions(
homogeneous: Bool, // if false, the below are undefined
r: Bool, // readable
w: Bool, // writeable
x: Bool, // executable
c: Bool, // cacheable
a: Bool, // arithmetic ops
l: Bool) // logical ops
object TLBPageLookup
{
private case class TLBFixedPermissions(
e: Boolean, // get-/put-effects
r: Boolean, // readable
w: Boolean, // writeable
x: Boolean, // executable
c: Boolean, // cacheable
a: Boolean, // arithmetic ops
l: Boolean) { // logical ops
val useful = r || w || x || c || a || l
}
private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = {
val permissions = managers.map { m =>
(m.address, TLBFixedPermissions(
e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType,
r = m.supportsGet || m.supportsAcquireB, // if cached, never uses Get
w = m.supportsPutFull || m.supportsAcquireT, // if cached, never uses Put
x = m.executable,
c = m.supportsAcquireB,
a = m.supportsArithmetic,
l = m.supportsLogical))
}
permissions
.filter(_._2.useful) // get rid of no-permission devices
.groupBy(_._2) // group by permission type
.mapValues(seq =>
AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions
.toMap
}
// Unmapped memory is considered to be inhomogeneous
def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = {
require (isPow2(xLen) && xLen >= 8)
require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8)
require (isPow2(pageSize) && pageSize >= cacheBlockBytes)
val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes)
val allSizes = TransferSizes(1, maxRequestBytes)
val amoSizes = TransferSizes(4, xLen/8)
val permissions = managers.foreach { m =>
require (!m.supportsGet || m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}")
require (!m.supportsPutFull || m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}")
require (!m.supportsPutPartial || m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}")
require (!m.supportsAcquireB || m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}")
require (!m.supportsAcquireT || m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}")
require (!m.supportsLogical || m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}")
require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}")
require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)")
}
val grouped = groupRegions(managers)
.mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough
def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = {
val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) }
val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList)
// Find the minimal bits needed to distinguish between yes and no
val decisionMask = AddressDecoder(Seq(yes, no))
def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct)
val (yesf, nof) = (simplify(yes), simplify(no))
if (yesf.size < no.size) {
(x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ || _)
} else {
(x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ || _)
}
}
// Derive simplified property circuits (don't care when !homo)
val rfn = lowCostProperty(_.r)
val wfn = lowCostProperty(_.w)
val xfn = lowCostProperty(_.x)
val cfn = lowCostProperty(_.c)
val afn = lowCostProperty(_.a)
val lfn = lowCostProperty(_.l)
val homo = AddressSet.unify(grouped.values.flatten.toList)
(x: UInt) => TLBPermissions(
homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ || _),
r = rfn(x),
w = wfn(x),
x = xfn(x),
c = cfn(x),
a = afn(x),
l = lfn(x))
}
// Are all pageSize intervals of mapped regions homogeneous?
def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = {
groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize))
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File PTW.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch}
import chisel3.withClock
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.subsystem.CacheBlockBytes
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
import scala.collection.mutable.ListBuffer
/** PTE request from TLB to PTW
*
* TLB send a PTE request to PTW when L1TLB miss
*/
class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
val addr = UInt(vpnBits.W)
val need_gpa = Bool()
val vstage1 = Bool()
val stage2 = Bool()
}
/** PTE info from L2TLB to TLB
*
* containing: target PTE, exceptions, two-satge tanslation info
*/
class PTWResp(implicit p: Parameters) extends CoreBundle()(p) {
/** ptw access exception */
val ae_ptw = Bool()
/** final access exception */
val ae_final = Bool()
/** page fault */
val pf = Bool()
/** guest page fault */
val gf = Bool()
/** hypervisor read */
val hr = Bool()
/** hypervisor write */
val hw = Bool()
/** hypervisor execute */
val hx = Bool()
/** PTE to refill L1TLB
*
* source: L2TLB
*/
val pte = new PTE
/** pte pglevel */
val level = UInt(log2Ceil(pgLevels).W)
/** fragmented_superpage support */
val fragmented_superpage = Bool()
/** homogeneous for both pma and pmp */
val homogeneous = Bool()
val gpa = Valid(UInt(vaddrBits.W))
val gpa_is_pte = Bool()
}
/** IO between TLB and PTW
*
* PTW receives :
* - PTE request
* - CSRs info
* - pmp results from PMP(in TLB)
*/
class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
val req = Decoupled(Valid(new PTWReq))
val resp = Flipped(Valid(new PTWResp))
val ptbr = Input(new PTBR())
val hgatp = Input(new PTBR())
val vsatp = Input(new PTBR())
val status = Input(new MStatus())
val hstatus = Input(new HStatus())
val gstatus = Input(new MStatus())
val pmp = Input(Vec(nPMPs, new PMP))
val customCSRs = Flipped(coreParams.customCSRs)
}
/** PTW performance statistics */
class PTWPerfEvents extends Bundle {
val l2miss = Bool()
val l2hit = Bool()
val pte_miss = Bool()
val pte_hit = Bool()
}
/** Datapath IO between PTW and Core
*
* PTW receives CSRs info, pmp checks, sfence instruction info
*
* PTW sends its performance statistics to core
*/
class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
val ptbr = Input(new PTBR())
val hgatp = Input(new PTBR())
val vsatp = Input(new PTBR())
val sfence = Flipped(Valid(new SFenceReq))
val status = Input(new MStatus())
val hstatus = Input(new HStatus())
val gstatus = Input(new MStatus())
val pmp = Input(Vec(nPMPs, new PMP))
val perf = Output(new PTWPerfEvents())
val customCSRs = Flipped(coreParams.customCSRs)
/** enable clock generated by ptw */
val clock_enabled = Output(Bool())
}
/** PTE template for transmission
*
* contains useful methods to check PTE attributes
* @see RV-priv spec 4.3.1 for pgae table entry format
*/
class PTE(implicit p: Parameters) extends CoreBundle()(p) {
val reserved_for_future = UInt(10.W)
val ppn = UInt(44.W)
val reserved_for_software = Bits(2.W)
/** dirty bit */
val d = Bool()
/** access bit */
val a = Bool()
/** global mapping */
val g = Bool()
/** user mode accessible */
val u = Bool()
/** whether the page is executable */
val x = Bool()
/** whether the page is writable */
val w = Bool()
/** whether the page is readable */
val r = Bool()
/** valid bit */
val v = Bool()
/** return true if find a pointer to next level page table */
def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U
/** return true if find a leaf PTE */
def leaf(dummy: Int = 0) = v && (r || (x && !w)) && a
/** user read */
def ur(dummy: Int = 0) = sr() && u
/** user write*/
def uw(dummy: Int = 0) = sw() && u
/** user execute */
def ux(dummy: Int = 0) = sx() && u
/** supervisor read */
def sr(dummy: Int = 0) = leaf() && r
/** supervisor write */
def sw(dummy: Int = 0) = leaf() && w && d
/** supervisor execute */
def sx(dummy: Int = 0) = leaf() && x
/** full permission: writable and executable in user mode */
def isFullPerm(dummy: Int = 0) = uw() && ux()
}
/** L2TLB PTE template
*
* contains tag bits
* @param nSets number of sets in L2TLB
* @see RV-priv spec 4.3.1 for page table entry format
*/
class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
val idxBits = log2Ceil(nSets)
val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0)
val tag = UInt(tagBits.W)
val ppn = UInt(ppnBits.W)
/** dirty bit */
val d = Bool()
/** access bit */
val a = Bool()
/** user mode accessible */
val u = Bool()
/** whether the page is executable */
val x = Bool()
/** whether the page is writable */
val w = Bool()
/** whether the page is readable */
val r = Bool()
}
/** PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC)
*
* It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb.
* Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process.
*
* ==Structure==
* - l2tlb : for leaf PTEs
* - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]]))
* - PLRU
* - pte_cache: for non-leaf PTEs
* - set-associative
* - LRU
* - s2_pte_cache: for non-leaf PTEs in 2-stage translation
* - set-associative
* - PLRU
*
* l2tlb Pipeline: 3 stage
* {{{
* stage 0 : read
* stage 1 : decode
* stage 2 : hit check
* }}}
* ==State Machine==
* s_ready: ready to reveive request from TLB
* s_req: request mem; pte_cache hit judge
* s_wait1: deal with l2tlb error
* s_wait2: final hit judge
* s_wait3: receive mem response
* s_fragment_superpage: for superpage PTE
*
* @note l2tlb hit happens in s_req or s_wait1
* @see RV-priv spec 4.3-4.6 for Virtual-Memory System
* @see RV-priv spec 8.5 for Two-Stage Address Translation
* @todo details in two-stage translation
*/
class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
val io = IO(new Bundle {
/** to n TLB */
val requestor = Flipped(Vec(n, new TLBPTWIO))
/** to HellaCache */
val mem = new HellaCacheIO
/** to Core
*
* contains CSRs info and performance statistics
*/
val dpath = new DatapathPTWIO
})
val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8)
val state = RegInit(s_ready)
val l2_refill_wire = Wire(Bool())
/** Arbiter to arbite request from n TLB */
val arb = Module(new Arbiter(Valid(new PTWReq), n))
// use TLB req as arbitor's input
arb.io.in <> io.requestor.map(_.req)
// receive req only when s_ready and not in refill
arb.io.out.ready := (state === s_ready) && !l2_refill_wire
val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B)))
val clock_en = state =/= s_ready || l2_refill_wire || arb.io.out.valid || io.dpath.sfence.valid || io.dpath.customCSRs.disableDCacheClockGate
io.dpath.clock_enabled := usingVM.B && clock_en
val gated_clock =
if (!usingVM || !tileParams.dcache.get.clockGate) clock
else ClockGate(clock, clock_en, "ptw_clock_gate")
withClock (gated_clock) { // entering gated-clock domain
val invalidated = Reg(Bool())
/** current PTE level
* {{{
* 0 <= count <= pgLevel-1
* count = pgLevel - 1 : leaf PTE
* count < pgLevel - 1 : non-leaf PTE
* }}}
*/
val count = Reg(UInt(log2Ceil(pgLevels).W))
val resp_ae_ptw = Reg(Bool())
val resp_ae_final = Reg(Bool())
val resp_pf = Reg(Bool())
val resp_gf = Reg(Bool())
val resp_hr = Reg(Bool())
val resp_hw = Reg(Bool())
val resp_hx = Reg(Bool())
val resp_fragmented_superpage = Reg(Bool())
/** tlb request */
val r_req = Reg(new PTWReq)
/** current selected way in arbitor */
val r_req_dest = Reg(Bits())
// to respond to L1TLB : l2_hit
// to construct mem.req.addr
val r_pte = Reg(new PTE)
val r_hgatp = Reg(new PTBR)
// 2-stage pageLevel
val aux_count = Reg(UInt(log2Ceil(pgLevels).W))
/** pte for 2-stage translation */
val aux_pte = Reg(new PTE)
val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case
val stage2 = Reg(Bool())
val stage2_final = Reg(Bool())
val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr)
val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels
/** 2-stage translation both enable */
val do_both_stages = r_req.vstage1 && r_req.stage2
val max_count = count max aux_count
val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr)
val mem_resp_valid = RegNext(io.mem.resp.valid)
val mem_resp_data = RegNext(io.mem.resp.bits.data)
io.mem.uncached_resp.map { resp =>
assert(!(resp.valid && io.mem.resp.valid))
resp.ready := true.B
when (resp.valid) {
mem_resp_valid := true.B
mem_resp_data := resp.bits.data
}
}
// construct pte from mem.resp
val (pte, invalid_paddr, invalid_gpa) = {
val tmp = mem_resp_data.asTypeOf(new PTE())
val res = WireDefault(tmp)
res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0))
when (tmp.r || tmp.w || tmp.x) {
// for superpage mappings, make sure PPN LSBs are zero
for (i <- 0 until pgLevels-1)
when (count <= i.U && tmp.ppn((pgLevels-1-i)*pgLevelBits-1, (pgLevels-2-i)*pgLevelBits) =/= 0.U) { res.v := false.B }
}
(res,
Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U),
do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn))
}
// find non-leaf PTE, need traverse
val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U
/** address send to mem for enquerry */
val pte_addr = if (!usingVM) 0.U else {
val vpn_idxs = (0 until pgLevels).map { i =>
val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0)
(vpn >> (pgLevels - i - 1) * pgLevelBits)(width - 1, 0)
}
val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U)
val vpn_idx = vpn_idxs(count) & mask
val raw_pte_addr = ((r_pte.ppn << pgLevelBits) | vpn_idx) << log2Ceil(xLen / 8)
val size = if (usingHypervisor) vaddrBits else paddrBits
//use r_pte.ppn as page table base address
//use vpn slice as offset
raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0)
}
/** stage2_pte_cache input addr */
val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else {
val vpn_idxs = (0 until pgLevels - 1).map { i =>
(r_req.addr >> (pgLevels - i - 1) * pgLevelBits)(pgLevelBits - 1, 0)
}
val vpn_idx = vpn_idxs(aux_count)
val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8)
raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0)
}
def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = {
(pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBits*i), r_req.addr(((pgLevelBits*i) min vpnBits)-1, 0).padTo(pgLevelBits*i)))
}
/** PTECache caches non-leaf PTE
* @param s2 true: 2-stage address translation
*/
def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) {
(false.B, 0.U)
} else {
val plru = new PseudoLRU(coreParams.nPTECacheEntries)
val valid = RegInit(0.U(coreParams.nPTECacheEntries.W))
val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W)))
// not include full pte, only ppn
val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W)))
val can_hit =
if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final
else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2)
val can_refill =
if (s2) do_both_stages && !stage2 && !stage2_final
else can_hit
val tag =
if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits))
else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits))
val hits = tags.map(_ === tag).asUInt & valid
val hit = hits.orR && can_hit
// refill with mem response
when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) {
val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid))
valid := valid | UIntToOH(r)
tags(r) := tag
data(r) := pte.ppn
plru.access(r)
}
// replace
when (hit && state === s_req) { plru.access(OHToUInt(hits)) }
when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 || usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U }
val lcount = if (s2) aux_count else count
for (i <- 0 until pgLevels-1) {
ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i")
}
(hit, Mux1H(hits, data))
}
// generate pte_cache
val (pte_cache_hit, pte_cache_data) = makePTECache(false)
// generate pte_cache with 2-stage translation
val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true)
// pte_cache hit or 2-stage pte_cache hit
val pte_hit = RegNext(false.B)
io.dpath.perf.pte_miss := false.B
io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit
assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)),
"PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event")
// l2_refill happens when find the leaf pte
val l2_refill = RegNext(false.B)
l2_refill_wire := l2_refill
io.dpath.perf.l2miss := false.B
io.dpath.perf.l2hit := false.B
// l2tlb
val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else {
val code = new ParityCode
require(isPow2(coreParams.nL2TLBEntries))
require(isPow2(coreParams.nL2TLBWays))
require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays)
val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays
require(isPow2(nL2TLBSets))
val idxBits = log2Ceil(nL2TLBSets)
val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru")
val ram = DescribedSRAM(
name = "l2_tlb_ram",
desc = "L2 TLB",
size = nL2TLBSets,
data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W))
)
val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W)))
val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W))))
// use r_req to construct tag
val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits)
/** the valid vec for the selected set(including n ways) */
val r_valid_vec = valid.map(_(r_idx)).asUInt
val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W))
val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W))
r_valid_vec_q := r_valid_vec
// replacement way
r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U)
// refill with r_pte(leaf pte)
when (l2_refill && !invalidated) {
val entry = Wire(new L2TLBEntry(nL2TLBSets))
entry.ppn := r_pte.ppn
entry.d := r_pte.d
entry.a := r_pte.a
entry.u := r_pte.u
entry.x := r_pte.x
entry.w := r_pte.w
entry.r := r_pte.r
entry.tag := r_tag
// if all the way are valid, use plru to select one way to be replaced,
// otherwise use PriorityEncoderOH to select one
val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W)
ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools)
val mask = UIntToOH(r_idx)
for (way <- 0 until coreParams.nL2TLBWays) {
when (wmask(way)) {
valid(way) := valid(way) | mask
g(way) := Mux(r_pte.g, g(way) | mask, g(way) & ~mask)
}
}
}
// sfence happens
when (io.dpath.sfence.valid) {
val hg = usingHypervisor.B && io.dpath.sfence.bits.hg
for (way <- 0 until coreParams.nL2TLBWays) {
valid(way) :=
Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)),
Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way),
0.U))
}
}
val s0_valid = !l2_refill && arb.io.out.fire
val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa
val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid)
val s2_valid = RegNext(s1_valid)
// read from tlb idx
val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid)
val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid)))
val s2_valid_vec = RegEnable(r_valid_vec, s1_valid)
val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid)
val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR
when (s2_valid && s2_error) { valid.foreach { _ := 0.U }}
// decode
val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets)))
val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag))
val s2_hit = s2_valid && s2_hit_vec.orR
io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR)
io.dpath.perf.l2hit := s2_hit
when (s2_hit) {
l2_plru.access(r_idx, OHToUInt(s2_hit_vec))
assert((PopCount(s2_hit_vec) === 1.U) || s2_error, "L2 TLB multi-hit")
}
val s2_pte = Wire(new PTE)
val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec)
s2_pte.ppn := s2_hit_entry.ppn
s2_pte.d := s2_hit_entry.d
s2_pte.a := s2_hit_entry.a
s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec)
s2_pte.u := s2_hit_entry.u
s2_pte.x := s2_hit_entry.x
s2_pte.w := s2_hit_entry.w
s2_pte.r := s2_hit_entry.r
s2_pte.v := true.B
s2_pte.reserved_for_future := 0.U
s2_pte.reserved_for_software := 0.U
for (way <- 0 until coreParams.nL2TLBWays) {
ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way")
}
(s2_hit, s2_error, s2_pte, Some(ram))
}
// if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk
invalidated := io.dpath.sfence.valid || (invalidated && state =/= s_ready)
// mem request
io.mem.keep_clock_enabled := false.B
io.mem.req.valid := state === s_req || state === s_dummy1
io.mem.req.bits.phys := true.B
io.mem.req.bits.cmd := M_XRD
io.mem.req.bits.size := log2Ceil(xLen/8).U
io.mem.req.bits.signed := false.B
io.mem.req.bits.addr := pte_addr
io.mem.req.bits.idx.foreach(_ := pte_addr)
io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition
io.mem.req.bits.dv := do_both_stages && !stage2
io.mem.req.bits.tag := DontCare
io.mem.req.bits.no_resp := false.B
io.mem.req.bits.no_alloc := DontCare
io.mem.req.bits.no_xcpt := DontCare
io.mem.req.bits.data := DontCare
io.mem.req.bits.mask := DontCare
io.mem.s1_kill := l2_hit || (state =/= s_wait1) || resp_gf
io.mem.s1_data := DontCare
io.mem.s2_kill := false.B
val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits)
require(!usingHypervisor || pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}")
val pmaPgLevelHomogeneous = (0 until pgLevels) map { i =>
val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) * pgLevelBits))
if (pageGranularityPMPs && i == pgLevels - 1) {
require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned")
true.B
} else {
TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous
}
}
val pmaHomogeneous = pmaPgLevelHomogeneous(count)
val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count)
val homogeneous = pmaHomogeneous && pmpHomogeneous
// response to tlb
for (i <- 0 until io.requestor.size) {
io.requestor(i).resp.valid := resp_valid(i)
io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw
io.requestor(i).resp.bits.ae_final := resp_ae_final
io.requestor(i).resp.bits.pf := resp_pf
io.requestor(i).resp.bits.gf := resp_gf
io.requestor(i).resp.bits.hr := resp_hr
io.requestor(i).resp.bits.hw := resp_hw
io.requestor(i).resp.bits.hx := resp_hx
io.requestor(i).resp.bits.pte := r_pte
io.requestor(i).resp.bits.level := max_count
io.requestor(i).resp.bits.homogeneous := homogeneous || pageGranularityPMPs.B
io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B
io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa
io.requestor(i).resp.bits.gpa.bits :=
Cat(Mux(!stage2_final || !r_req.vstage1 || aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff)
io.requestor(i).resp.bits.gpa_is_pte := !stage2_final
io.requestor(i).ptbr := io.dpath.ptbr
io.requestor(i).hgatp := io.dpath.hgatp
io.requestor(i).vsatp := io.dpath.vsatp
io.requestor(i).customCSRs <> io.dpath.customCSRs
io.requestor(i).status := io.dpath.status
io.requestor(i).hstatus := io.dpath.hstatus
io.requestor(i).gstatus := io.dpath.gstatus
io.requestor(i).pmp := io.dpath.pmp
}
// control state machine
val next_state = WireDefault(state)
state := OptimizationBarrier(next_state)
val do_switch = WireDefault(false.B)
switch (state) {
is (s_ready) {
when (arb.io.out.fire) {
val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels
val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels
val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels
val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr)
r_req := arb.io.out.bits.bits
r_req_dest := arb.io.chosen
next_state := Mux(arb.io.out.bits.valid, s_req, s_ready)
stage2 := arb.io.out.bits.bits.stage2
stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1
count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count)
aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U)
aux_pte.ppn := aux_ppn
aux_pte.reserved_for_future := 0.U
resp_ae_ptw := false.B
resp_ae_final := false.B
resp_pf := false.B
resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2
resp_hr := true.B
resp_hw := true.B
resp_hx := true.B
resp_fragmented_superpage := false.B
r_hgatp := io.dpath.hgatp
assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2)
}
}
is (s_req) {
when(stage2 && count === r_hgatp_initial_count) {
gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr)
}
// pte_cache hit
when (stage2_pte_cache_hit) {
aux_count := aux_count + 1.U
aux_pte.ppn := stage2_pte_cache_data
aux_pte.reserved_for_future := 0.U
pte_hit := true.B
}.elsewhen (pte_cache_hit) {
count := count + 1.U
pte_hit := true.B
}.otherwise {
next_state := Mux(io.mem.req.ready, s_wait1, s_req)
}
when(resp_gf) {
next_state := s_ready
resp_valid(r_req_dest) := true.B
}
}
is (s_wait1) {
// This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below
next_state := Mux(l2_hit, s_req, s_wait2)
}
is (s_wait2) {
next_state := s_wait3
io.dpath.perf.pte_miss := count < (pgLevels-1).U
when (io.mem.s2_xcpt.ae.ld) {
resp_ae_ptw := true.B
next_state := s_ready
resp_valid(r_req_dest) := true.B
}
}
is (s_fragment_superpage) {
next_state := s_ready
resp_valid(r_req_dest) := true.B
when (!homogeneous) {
count := (pgLevels-1).U
resp_fragmented_superpage := true.B
}
when (do_both_stages) {
resp_fragmented_superpage := true.B
}
}
}
val merged_pte = {
val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)*pgLevelBits)).U)
val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U))
val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), aux_pte.ppn((pgLevels-i-1)*pgLevelBits-1,0))) :+ pte.ppn
val stage1_ppn = stage1_ppns(count)
makePTE(stage1_ppn & superpage_mask, aux_pte)
}
r_pte := OptimizationBarrier(
// l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB
Mux(l2_hit && !l2_error && !resp_gf, l2_pte,
// S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp
Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte),
// pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem
Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte),
// 2-stage translation
Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte),
// when mem respond, store mem.resp.pte
Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte),
// fragment_superpage
Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte),
// when tlb request come->request mem, use root address in satp(or vsatp,hgatp)
Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)),
r_pte))))))))
when (l2_hit && !l2_error && !resp_gf) {
assert(state === s_req || state === s_wait1)
next_state := s_ready
resp_valid(r_req_dest) := true.B
count := (pgLevels-1).U
}
when (mem_resp_valid) {
assert(state === s_wait3)
next_state := s_req
when (traverse) {
when (do_both_stages && !stage2) { do_switch := true.B }
count := count + 1.U
}.otherwise {
val gf = (stage2 && !stage2_final && !pte.ur()) || (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa)
val ae = pte.v && invalid_paddr
val pf = pte.v && pte.reserved_for_future =/= 0.U
val success = pte.v && !ae && !pf && !gf
when (do_both_stages && !stage2_final && success) {
when (stage2) {
stage2 := false.B
count := aux_count
}.otherwise {
stage2_final := true.B
do_switch := true.B
}
}.otherwise {
// find a leaf pte, start l2 refill
l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa &&
(!r_req.vstage1 && !r_req.stage2 ||
do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm())
count := max_count
when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages || aux_count === (pgLevels-1).U))) {
next_state := s_fragment_superpage
}.otherwise {
next_state := s_ready
resp_valid(r_req_dest) := true.B
}
resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table()
resp_ae_final := ae && pte.leaf()
resp_pf := pf && !stage2
resp_gf := gf || (pf && stage2)
resp_hr := !stage2 || (!pf && !gf && pte.ur())
resp_hw := !stage2 || (!pf && !gf && pte.uw())
resp_hx := !stage2 || (!pf && !gf && pte.ux())
}
}
}
when (io.mem.s2_nack) {
assert(state === s_wait2)
next_state := s_req
}
when (do_switch) {
aux_count := Mux(traverse, count + 1.U, count)
count := r_hgatp_initial_count
aux_pte := Mux(traverse, pte, {
val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), r_req.addr(((pgLevels-i-1)*pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)*pgLevelBits))) :+ pte.ppn
makePTE(s1_ppns(count), pte)
})
stage2 := true.B
}
for (i <- 0 until pgLevels) {
val leaf = mem_resp_valid && !traverse && count === i.U
ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i")
ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i")
ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i")
ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i")
ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i")
if (i != pgLevels-1)
ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i")
}
ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep")
ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access")
ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table")
} // leaving gated-clock domain
private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc)
/** Relace PTE.ppn with ppn */
private def makePTE(ppn: UInt, default: PTE) = {
val pte = WireDefault(default)
pte.ppn := ppn
pte
}
/** use hgatp and vpn to construct a new ppn */
private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = {
val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels
val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)*pgLevelBits))
val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count))
val pte = WireDefault(default)
pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs)
pte
}
/** use hgatp and vpn to check for gpa out of range */
private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = {
val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels
val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)*pgLevelBits)+maxHypervisorExtraAddrBits))
idxs.extract(count) =/= 0.U
}
}
/** Mix-ins for constructing tiles that might have a PTW */
trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile =>
val module: CanHavePTWModule
var nPTWPorts = 1
nDCachePorts += usingPTW.toInt
}
trait CanHavePTWModule extends HasHellaCacheModule {
val outer: CanHavePTW
val ptwPorts = ListBuffer(outer.dcache.module.io.ptw)
val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p))
ptw.io.mem <> DontCare
if (outer.usingPTW) {
dcachePorts += ptw.io.mem
}
}
|
module DTLB_8( // @[TLB.scala:318:7]
input clock, // @[TLB.scala:318:7]
input reset, // @[TLB.scala:318:7]
output io_req_ready, // @[TLB.scala:320:14]
input io_req_valid, // @[TLB.scala:320:14]
input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14]
input io_req_bits_passthrough, // @[TLB.scala:320:14]
input [1:0] io_req_bits_size, // @[TLB.scala:320:14]
input [4:0] io_req_bits_cmd, // @[TLB.scala:320:14]
input [1:0] io_req_bits_prv, // @[TLB.scala:320:14]
input io_req_bits_v, // @[TLB.scala:320:14]
output io_resp_miss, // @[TLB.scala:320:14]
output [31:0] io_resp_paddr, // @[TLB.scala:320:14]
output [39:0] io_resp_gpa, // @[TLB.scala:320:14]
output io_resp_pf_ld, // @[TLB.scala:320:14]
output io_resp_pf_st, // @[TLB.scala:320:14]
output io_resp_pf_inst, // @[TLB.scala:320:14]
output io_resp_ae_ld, // @[TLB.scala:320:14]
output io_resp_ae_st, // @[TLB.scala:320:14]
output io_resp_ae_inst, // @[TLB.scala:320:14]
output io_resp_ma_ld, // @[TLB.scala:320:14]
output io_resp_ma_st, // @[TLB.scala:320:14]
output io_resp_cacheable, // @[TLB.scala:320:14]
output io_resp_must_alloc, // @[TLB.scala:320:14]
output io_resp_prefetchable, // @[TLB.scala:320:14]
output [1:0] io_resp_size, // @[TLB.scala:320:14]
output [4:0] io_resp_cmd, // @[TLB.scala:320:14]
input io_sfence_valid, // @[TLB.scala:320:14]
input io_sfence_bits_rs1, // @[TLB.scala:320:14]
input io_sfence_bits_rs2, // @[TLB.scala:320:14]
input [38:0] io_sfence_bits_addr, // @[TLB.scala:320:14]
input io_sfence_bits_asid, // @[TLB.scala:320:14]
input io_sfence_bits_hv, // @[TLB.scala:320:14]
input io_sfence_bits_hg, // @[TLB.scala:320:14]
input io_ptw_req_ready, // @[TLB.scala:320:14]
output io_ptw_req_valid, // @[TLB.scala:320:14]
output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14]
output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14]
input io_ptw_resp_valid, // @[TLB.scala:320:14]
input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14]
input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pf, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gf, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hr, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hw, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hx, // @[TLB.scala:320:14]
input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14]
input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14]
input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14]
input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14]
input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14]
input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14]
input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14]
input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14]
input io_ptw_status_debug, // @[TLB.scala:320:14]
input io_ptw_status_cease, // @[TLB.scala:320:14]
input io_ptw_status_wfi, // @[TLB.scala:320:14]
input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14]
input io_ptw_status_dv, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14]
input io_ptw_status_v, // @[TLB.scala:320:14]
input io_ptw_status_sd, // @[TLB.scala:320:14]
input io_ptw_status_mpv, // @[TLB.scala:320:14]
input io_ptw_status_gva, // @[TLB.scala:320:14]
input io_ptw_status_tsr, // @[TLB.scala:320:14]
input io_ptw_status_tw, // @[TLB.scala:320:14]
input io_ptw_status_tvm, // @[TLB.scala:320:14]
input io_ptw_status_mxr, // @[TLB.scala:320:14]
input io_ptw_status_sum, // @[TLB.scala:320:14]
input io_ptw_status_mprv, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14]
input io_ptw_status_spp, // @[TLB.scala:320:14]
input io_ptw_status_mpie, // @[TLB.scala:320:14]
input io_ptw_status_spie, // @[TLB.scala:320:14]
input io_ptw_status_mie, // @[TLB.scala:320:14]
input io_ptw_status_sie, // @[TLB.scala:320:14]
input io_ptw_hstatus_spvp, // @[TLB.scala:320:14]
input io_ptw_hstatus_spv, // @[TLB.scala:320:14]
input io_ptw_hstatus_gva, // @[TLB.scala:320:14]
input io_ptw_gstatus_debug, // @[TLB.scala:320:14]
input io_ptw_gstatus_cease, // @[TLB.scala:320:14]
input io_ptw_gstatus_wfi, // @[TLB.scala:320:14]
input [31:0] io_ptw_gstatus_isa, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_dprv, // @[TLB.scala:320:14]
input io_ptw_gstatus_dv, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_prv, // @[TLB.scala:320:14]
input io_ptw_gstatus_v, // @[TLB.scala:320:14]
input io_ptw_gstatus_sd, // @[TLB.scala:320:14]
input [22:0] io_ptw_gstatus_zero2, // @[TLB.scala:320:14]
input io_ptw_gstatus_mpv, // @[TLB.scala:320:14]
input io_ptw_gstatus_gva, // @[TLB.scala:320:14]
input io_ptw_gstatus_mbe, // @[TLB.scala:320:14]
input io_ptw_gstatus_sbe, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_sxl, // @[TLB.scala:320:14]
input [7:0] io_ptw_gstatus_zero1, // @[TLB.scala:320:14]
input io_ptw_gstatus_tsr, // @[TLB.scala:320:14]
input io_ptw_gstatus_tw, // @[TLB.scala:320:14]
input io_ptw_gstatus_tvm, // @[TLB.scala:320:14]
input io_ptw_gstatus_mxr, // @[TLB.scala:320:14]
input io_ptw_gstatus_sum, // @[TLB.scala:320:14]
input io_ptw_gstatus_mprv, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_fs, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_mpp, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_vs, // @[TLB.scala:320:14]
input io_ptw_gstatus_spp, // @[TLB.scala:320:14]
input io_ptw_gstatus_mpie, // @[TLB.scala:320:14]
input io_ptw_gstatus_ube, // @[TLB.scala:320:14]
input io_ptw_gstatus_spie, // @[TLB.scala:320:14]
input io_ptw_gstatus_upie, // @[TLB.scala:320:14]
input io_ptw_gstatus_mie, // @[TLB.scala:320:14]
input io_ptw_gstatus_hie, // @[TLB.scala:320:14]
input io_ptw_gstatus_sie, // @[TLB.scala:320:14]
input io_ptw_gstatus_uie, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_0_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_0_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_0_value, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_1_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_1_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_1_value, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_2_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_2_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_2_value, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_3_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_3_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_3_value // @[TLB.scala:320:14]
);
wire [19:0] _entries_barrier_12_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hr; // @[package.scala:267:25]
wire [19:0] _entries_barrier_11_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_10_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_9_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_8_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_7_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_6_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_io_y_c; // @[package.scala:267:25]
wire _pma_io_resp_r; // @[TLB.scala:422:19]
wire _pma_io_resp_w; // @[TLB.scala:422:19]
wire _pma_io_resp_pp; // @[TLB.scala:422:19]
wire _pma_io_resp_al; // @[TLB.scala:422:19]
wire _pma_io_resp_aa; // @[TLB.scala:422:19]
wire _pma_io_resp_x; // @[TLB.scala:422:19]
wire _pma_io_resp_eff; // @[TLB.scala:422:19]
wire _pmp_io_r; // @[TLB.scala:416:19]
wire _pmp_io_w; // @[TLB.scala:416:19]
wire _pmp_io_x; // @[TLB.scala:416:19]
wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25]
wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7]
wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7]
wire io_req_bits_passthrough_0 = io_req_bits_passthrough; // @[TLB.scala:318:7]
wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[TLB.scala:318:7]
wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[TLB.scala:318:7]
wire [1:0] io_req_bits_prv_0 = io_req_bits_prv; // @[TLB.scala:318:7]
wire io_req_bits_v_0 = io_req_bits_v; // @[TLB.scala:318:7]
wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7]
wire io_sfence_bits_rs1_0 = io_sfence_bits_rs1; // @[TLB.scala:318:7]
wire io_sfence_bits_rs2_0 = io_sfence_bits_rs2; // @[TLB.scala:318:7]
wire [38:0] io_sfence_bits_addr_0 = io_sfence_bits_addr; // @[TLB.scala:318:7]
wire io_sfence_bits_asid_0 = io_sfence_bits_asid; // @[TLB.scala:318:7]
wire io_sfence_bits_hv_0 = io_sfence_bits_hv; // @[TLB.scala:318:7]
wire io_sfence_bits_hg_0 = io_sfence_bits_hg; // @[TLB.scala:318:7]
wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7]
wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7]
wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7]
wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7]
wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7]
wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7]
wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7]
wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7]
wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7]
wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7]
wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7]
wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7]
wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7]
wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7]
wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7]
wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7]
wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7]
wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7]
wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7]
wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7]
wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7]
wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7]
wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7]
wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7]
wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7]
wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[TLB.scala:318:7]
wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[TLB.scala:318:7]
wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[TLB.scala:318:7]
wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[TLB.scala:318:7]
wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[TLB.scala:318:7]
wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[TLB.scala:318:7]
wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[TLB.scala:318:7]
wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[TLB.scala:318:7]
wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sd_0 = io_ptw_gstatus_sd; // @[TLB.scala:318:7]
wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[TLB.scala:318:7]
wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[TLB.scala:318:7]
wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[TLB.scala:318:7]
wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[TLB.scala:318:7]
wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[TLB.scala:318:7]
wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7]
wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_mbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_sbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_ube = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_upie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_hie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_uie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[TLB.scala:318:7]
wire io_kill = 1'h0; // @[TLB.scala:318:7]
wire priv_v = 1'h0; // @[TLB.scala:369:34]
wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38]
wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68]
wire vstage1_en = 1'h0; // @[TLB.scala:376:48]
wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38]
wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68]
wire stage2_en = 1'h0; // @[TLB.scala:378:48]
wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52]
wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37]
wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78]
wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34]
wire _superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire _superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire _superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34]
wire refill_v = 1'h0; // @[TLB.scala:448:33]
wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24]
wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24]
wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84]
wire _waddr_T = 1'h0; // @[TLB.scala:477:45]
wire _mxr_T = 1'h0; // @[TLB.scala:518:36]
wire cmd_readx = 1'h0; // @[TLB.scala:575:37]
wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32]
wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32]
wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37]
wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29]
wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66]
wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42]
wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29]
wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73]
wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49]
wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56]
wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30]
wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36]
wire hv = 1'h0; // @[TLB.scala:721:36]
wire hg = 1'h0; // @[TLB.scala:722:36]
wire hv_1 = 1'h0; // @[TLB.scala:721:36]
wire hg_1 = 1'h0; // @[TLB.scala:722:36]
wire hv_2 = 1'h0; // @[TLB.scala:721:36]
wire hg_2 = 1'h0; // @[TLB.scala:722:36]
wire hv_3 = 1'h0; // @[TLB.scala:721:36]
wire hg_3 = 1'h0; // @[TLB.scala:722:36]
wire hv_4 = 1'h0; // @[TLB.scala:721:36]
wire hg_4 = 1'h0; // @[TLB.scala:722:36]
wire hv_5 = 1'h0; // @[TLB.scala:721:36]
wire hg_5 = 1'h0; // @[TLB.scala:722:36]
wire hv_6 = 1'h0; // @[TLB.scala:721:36]
wire hg_6 = 1'h0; // @[TLB.scala:722:36]
wire hv_7 = 1'h0; // @[TLB.scala:721:36]
wire hg_7 = 1'h0; // @[TLB.scala:722:36]
wire hv_8 = 1'h0; // @[TLB.scala:721:36]
wire hg_8 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T = 1'h0; // @[TLB.scala:182:28]
wire ignore = 1'h0; // @[TLB.scala:182:34]
wire hv_9 = 1'h0; // @[TLB.scala:721:36]
wire hg_9 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire hv_10 = 1'h0; // @[TLB.scala:721:36]
wire hg_10 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire hv_11 = 1'h0; // @[TLB.scala:721:36]
wire hg_11 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire hv_12 = 1'h0; // @[TLB.scala:721:36]
wire hg_12 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_12 = 1'h0; // @[TLB.scala:182:28]
wire ignore_12 = 1'h0; // @[TLB.scala:182:34]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7]
wire [15:0] satp_asid = 16'h0; // @[TLB.scala:373:17]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[TLB.scala:318:7]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_xs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7]
wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22]
wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40]
wire superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40]
wire superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40]
wire superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40]
wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34]
wire ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34]
wire ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34]
wire ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34]
wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42]
wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26]
wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107]
wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32]
wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20]
wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28]
wire ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire [1:0] io_ptw_status_sxl = 2'h2; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_uxl = 2'h2; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[TLB.scala:318:7]
wire [13:0] _gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46]
wire [13:0] gf_ld_array = 14'h0; // @[TLB.scala:600:24]
wire [13:0] _gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53]
wire [13:0] gf_st_array = 14'h0; // @[TLB.scala:601:24]
wire [13:0] _gf_inst_array_T = 14'h0; // @[TLB.scala:602:36]
wire [13:0] gf_inst_array = 14'h0; // @[TLB.scala:602:26]
wire [13:0] gpa_hits_need_gpa_mask = 14'h0; // @[TLB.scala:605:73]
wire [13:0] _io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58]
wire [13:0] _io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65]
wire [13:0] _io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48]
wire [6:0] _state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25]
wire [12:0] stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27]
wire [12:0] _hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111]
wire [12:0] _hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55]
wire [12:0] _hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55]
wire [12:0] _gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88]
wire [12:0] gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82]
wire [12:0] _gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16]
wire [12:0] gpa_hits = 13'h1FFF; // @[TLB.scala:607:14]
wire [12:0] _stage1_bypass_T = 13'h0; // @[TLB.scala:517:27]
wire [12:0] stage1_bypass = 13'h0; // @[TLB.scala:517:61]
wire [12:0] _gpa_hits_T = 13'h0; // @[TLB.scala:607:30]
wire [13:0] hr_array = 14'h3FFF; // @[TLB.scala:524:21]
wire [13:0] hw_array = 14'h3FFF; // @[TLB.scala:525:21]
wire [13:0] hx_array = 14'h3FFF; // @[TLB.scala:526:21]
wire [13:0] _must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19]
wire [13:0] _gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50]
wire _io_req_ready_T; // @[TLB.scala:631:25]
wire [1:0] io_resp_size_0 = io_req_bits_size_0; // @[TLB.scala:318:7]
wire [4:0] io_resp_cmd_0 = io_req_bits_cmd_0; // @[TLB.scala:318:7]
wire _io_resp_miss_T_2; // @[TLB.scala:651:64]
wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23]
wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8]
wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41]
wire _io_resp_pf_st_T_3; // @[TLB.scala:634:48]
wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29]
wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41]
wire _io_resp_ae_st_T_1; // @[TLB.scala:642:41]
wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41]
wire _io_resp_ma_ld_T; // @[TLB.scala:645:31]
wire _io_resp_ma_st_T; // @[TLB.scala:646:31]
wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41]
wire _io_resp_must_alloc_T_1; // @[TLB.scala:649:51]
wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59]
wire _io_ptw_req_valid_T; // @[TLB.scala:662:29]
wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29]
wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24]
wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13]
wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17]
wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17]
wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31]
wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16]
wire io_req_ready_0; // @[TLB.scala:318:7]
wire io_resp_pf_ld_0; // @[TLB.scala:318:7]
wire io_resp_pf_st_0; // @[TLB.scala:318:7]
wire io_resp_pf_inst_0; // @[TLB.scala:318:7]
wire io_resp_ae_ld_0; // @[TLB.scala:318:7]
wire io_resp_ae_st_0; // @[TLB.scala:318:7]
wire io_resp_ae_inst_0; // @[TLB.scala:318:7]
wire io_resp_ma_ld_0; // @[TLB.scala:318:7]
wire io_resp_ma_st_0; // @[TLB.scala:318:7]
wire io_resp_miss_0; // @[TLB.scala:318:7]
wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7]
wire [39:0] io_resp_gpa_0; // @[TLB.scala:318:7]
wire io_resp_cacheable_0; // @[TLB.scala:318:7]
wire io_resp_must_alloc_0; // @[TLB.scala:318:7]
wire io_resp_prefetchable_0; // @[TLB.scala:318:7]
wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7]
wire io_ptw_req_valid_0; // @[TLB.scala:318:7]
wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30]
wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] _ppn_T_13 = vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] _ppn_T_21 = vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] _ppn_T_29 = vpn; // @[TLB.scala:198:28, :335:30]
reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_4_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_4_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_4_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_5_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_5_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_5_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_6_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_6_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_6_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_7_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_7_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_7_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_3; // @[TLB.scala:339:29]
reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_0_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_17 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_0_valid_0; // @[TLB.scala:341:30]
reg [1:0] superpage_entries_1_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_1_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_1_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_1_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_19 = superpage_entries_1_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_1_valid_0; // @[TLB.scala:341:30]
reg [1:0] superpage_entries_2_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_2_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_2_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_2_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_21 = superpage_entries_2_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_2_valid_0; // @[TLB.scala:341:30]
reg [1:0] superpage_entries_3_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_3_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_3_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_3_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_23 = superpage_entries_3_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_3_valid_0; // @[TLB.scala:341:30]
reg [1:0] special_entry_level; // @[TLB.scala:346:56]
reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56]
reg special_entry_tag_v; // @[TLB.scala:346:56]
reg [41:0] special_entry_data_0; // @[TLB.scala:346:56]
wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56]
wire [41:0] _entries_WIRE_25 = special_entry_data_0; // @[TLB.scala:170:77, :346:56]
reg special_entry_valid_0; // @[TLB.scala:346:56]
reg [1:0] state; // @[TLB.scala:352:22]
reg [26:0] r_refill_tag; // @[TLB.scala:354:25]
assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25]
reg [1:0] r_superpage_repl_addr; // @[TLB.scala:355:34]
wire [1:0] waddr = r_superpage_repl_addr; // @[TLB.scala:355:34, :477:22]
reg [2:0] r_sectored_repl_addr; // @[TLB.scala:356:33]
reg r_sectored_hit_valid; // @[TLB.scala:357:27]
reg [2:0] r_sectored_hit_bits; // @[TLB.scala:357:27]
reg r_superpage_hit_valid; // @[TLB.scala:358:28]
reg [1:0] r_superpage_hit_bits; // @[TLB.scala:358:28]
reg r_need_gpa; // @[TLB.scala:361:23]
assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23]
reg r_gpa_valid; // @[TLB.scala:362:24]
reg [38:0] r_gpa; // @[TLB.scala:363:18]
reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22]
reg r_gpa_is_pte; // @[TLB.scala:365:25]
wire priv_s = io_req_bits_prv_0[0]; // @[TLB.scala:318:7, :370:20]
wire priv_uses_vm = ~(io_req_bits_prv_0[1]); // @[TLB.scala:318:7, :372:27]
wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41]
wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}]
wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31]
wire _vm_enabled_T_1 = _vm_enabled_T & priv_uses_vm; // @[TLB.scala:372:27, :399:{31,45}]
wire _vm_enabled_T_2 = ~io_req_bits_passthrough_0; // @[TLB.scala:318:7, :399:64]
wire vm_enabled = _vm_enabled_T_1 & _vm_enabled_T_2; // @[TLB.scala:399:{45,61,64}]
wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32]
wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29]
wire _vsatp_mode_mismatch_T_2 = ~io_req_bits_passthrough_0; // @[TLB.scala:318:7, :399:64, :403:81]
wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44]
wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24]
wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29]
wire _T_51 = state == 2'h1; // @[package.scala:16:47]
wire _invalidate_refill_T; // @[package.scala:16:47]
assign _invalidate_refill_T = _T_51; // @[package.scala:16:47]
assign _io_ptw_req_valid_T = _T_51; // @[package.scala:16:47]
wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47]
wire _invalidate_refill_T_2 = _invalidate_refill_T | _invalidate_refill_T_1; // @[package.scala:16:47, :81:59]
wire invalidate_refill = _invalidate_refill_T_2 | io_sfence_valid_0; // @[package.scala:81:59]
wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77]
wire _mpu_ppn_T_22; // @[TLB.scala:170:77]
wire _mpu_ppn_T_21; // @[TLB.scala:170:77]
wire _mpu_ppn_T_20; // @[TLB.scala:170:77]
wire _mpu_ppn_T_19; // @[TLB.scala:170:77]
wire _mpu_ppn_T_18; // @[TLB.scala:170:77]
wire _mpu_ppn_T_17; // @[TLB.scala:170:77]
wire _mpu_ppn_T_16; // @[TLB.scala:170:77]
wire _mpu_ppn_T_15; // @[TLB.scala:170:77]
wire _mpu_ppn_T_14; // @[TLB.scala:170:77]
wire _mpu_ppn_T_13; // @[TLB.scala:170:77]
wire _mpu_ppn_T_12; // @[TLB.scala:170:77]
wire _mpu_ppn_T_11; // @[TLB.scala:170:77]
wire _mpu_ppn_T_10; // @[TLB.scala:170:77]
wire _mpu_ppn_T_9; // @[TLB.scala:170:77]
wire _mpu_ppn_T_8; // @[TLB.scala:170:77]
wire _mpu_ppn_T_7; // @[TLB.scala:170:77]
wire _mpu_ppn_T_6; // @[TLB.scala:170:77]
wire _mpu_ppn_T_5; // @[TLB.scala:170:77]
wire _mpu_ppn_T_4; // @[TLB.scala:170:77]
wire _mpu_ppn_T_3; // @[TLB.scala:170:77]
wire _mpu_ppn_T_2; // @[TLB.scala:170:77]
wire _mpu_ppn_T_1; // @[TLB.scala:170:77]
assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77]
assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77]
assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77]
assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77]
assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77]
assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77]
assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77]
assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77]
assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77]
assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77]
assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77]
assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77]
assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77]
assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77]
assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77]
assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77]
assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77]
assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77]
assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77]
assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77]
assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77]
assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77]
assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77]
wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25]
wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56]
wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28]
assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28]
wire _hitsVec_ignore_T_13; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28]
wire _ppn_ignore_T_8; // @[TLB.scala:197:28]
assign _ppn_ignore_T_8 = _GEN; // @[TLB.scala:197:28]
wire _ignore_T_13; // @[TLB.scala:182:28]
assign _ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28]
wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}]
wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}]
wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56]
wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}]
wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}]
wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146]
wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}]
wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20]
wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52]
wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46]
wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82]
wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}]
wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25]
wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25]
wire _mpu_priv_T = do_refill | io_req_bits_passthrough_0; // @[TLB.scala:318:7, :408:29, :415:52]
wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}]
wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, io_req_bits_prv_0}; // @[TLB.scala:318:7, :415:103]
wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}]
wire cacheable; // @[TLB.scala:425:41]
wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24]
wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46]
wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65]
wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31]
assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31]
assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46]
wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31]
assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31]
assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31]
assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31]
assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31]
assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46]
wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46]
wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46]
wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46]
wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31]
assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31]
assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31]
assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46]
wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46]
wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46]
wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15]
wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31]
assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31]
assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31]
assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46]
wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_51 = _homogeneous_T_50 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_52 = _homogeneous_T_51 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_53 = _homogeneous_T_52 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_54 = _homogeneous_T_53 | _homogeneous_T_24; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_55 = _homogeneous_T_54 | _homogeneous_T_29; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_56 = _homogeneous_T_55 | _homogeneous_T_34; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_57 = _homogeneous_T_56 | _homogeneous_T_39; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_58 = _homogeneous_T_57 | _homogeneous_T_44; // @[TLBPermissions.scala:101:65]
wire homogeneous = _homogeneous_T_58 | _homogeneous_T_49; // @[TLBPermissions.scala:101:65]
wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46]
wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}]
wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46]
wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46]
wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46]
wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46]
wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46]
wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_93 = _homogeneous_T_92 | _homogeneous_T_76; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_94 = _homogeneous_T_93 | _homogeneous_T_81; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_95 = _homogeneous_T_94 | _homogeneous_T_86; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_96 = _homogeneous_T_95 | _homogeneous_T_91; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46]
wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46]
wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_108 = _homogeneous_T_107 | _homogeneous_T_106; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46]
wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}]
wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46]
wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}]
wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39]
wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46]
wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}]
wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33]
wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}]
wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}]
wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24]
wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33]
wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}]
wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}]
wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24]
wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33]
wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}]
wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}]
wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24]
wire _GEN_4 = sectored_entries_0_0_valid_0 | sectored_entries_0_0_valid_1; // @[package.scala:81:59]
wire _sector_hits_T; // @[package.scala:81:59]
assign _sector_hits_T = _GEN_4; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T = _GEN_4; // @[package.scala:81:59]
wire _sector_hits_T_1 = _sector_hits_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_2 = _sector_hits_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59]
wire [26:0] _T_176 = sectored_entries_0_0_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_3; // @[TLB.scala:174:61]
assign _sector_hits_T_3 = _T_176; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T; // @[TLB.scala:174:61]
assign _hitsVec_T = _T_176; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_4 = _sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_5 = _sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_6 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_7 = _sector_hits_T_5 & _sector_hits_T_6; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_0 = _sector_hits_T_2 & _sector_hits_T_7; // @[package.scala:81:59]
wire _GEN_5 = sectored_entries_0_1_valid_0 | sectored_entries_0_1_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_8; // @[package.scala:81:59]
assign _sector_hits_T_8 = _GEN_5; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_3; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_3 = _GEN_5; // @[package.scala:81:59]
wire _sector_hits_T_9 = _sector_hits_T_8 | sectored_entries_0_1_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_10 = _sector_hits_T_9 | sectored_entries_0_1_valid_3; // @[package.scala:81:59]
wire [26:0] _T_597 = sectored_entries_0_1_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_11; // @[TLB.scala:174:61]
assign _sector_hits_T_11 = _T_597; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61]
assign _hitsVec_T_6 = _T_597; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_12 = _sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_13 = _sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_14 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_15 = _sector_hits_T_13 & _sector_hits_T_14; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_1 = _sector_hits_T_10 & _sector_hits_T_15; // @[package.scala:81:59]
wire _GEN_6 = sectored_entries_0_2_valid_0 | sectored_entries_0_2_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_16; // @[package.scala:81:59]
assign _sector_hits_T_16 = _GEN_6; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_6; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_6 = _GEN_6; // @[package.scala:81:59]
wire _sector_hits_T_17 = _sector_hits_T_16 | sectored_entries_0_2_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_18 = _sector_hits_T_17 | sectored_entries_0_2_valid_3; // @[package.scala:81:59]
wire [26:0] _T_1018 = sectored_entries_0_2_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_19; // @[TLB.scala:174:61]
assign _sector_hits_T_19 = _T_1018; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61]
assign _hitsVec_T_12 = _T_1018; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_20 = _sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_21 = _sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_22 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_23 = _sector_hits_T_21 & _sector_hits_T_22; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_2 = _sector_hits_T_18 & _sector_hits_T_23; // @[package.scala:81:59]
wire _GEN_7 = sectored_entries_0_3_valid_0 | sectored_entries_0_3_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_24; // @[package.scala:81:59]
assign _sector_hits_T_24 = _GEN_7; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_9; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_9 = _GEN_7; // @[package.scala:81:59]
wire _sector_hits_T_25 = _sector_hits_T_24 | sectored_entries_0_3_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_26 = _sector_hits_T_25 | sectored_entries_0_3_valid_3; // @[package.scala:81:59]
wire [26:0] _T_1439 = sectored_entries_0_3_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_27; // @[TLB.scala:174:61]
assign _sector_hits_T_27 = _T_1439; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61]
assign _hitsVec_T_18 = _T_1439; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_28 = _sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_29 = _sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_30 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_31 = _sector_hits_T_29 & _sector_hits_T_30; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_3 = _sector_hits_T_26 & _sector_hits_T_31; // @[package.scala:81:59]
wire _GEN_8 = sectored_entries_0_4_valid_0 | sectored_entries_0_4_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_32; // @[package.scala:81:59]
assign _sector_hits_T_32 = _GEN_8; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_12; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_12 = _GEN_8; // @[package.scala:81:59]
wire _sector_hits_T_33 = _sector_hits_T_32 | sectored_entries_0_4_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_34 = _sector_hits_T_33 | sectored_entries_0_4_valid_3; // @[package.scala:81:59]
wire [26:0] _T_1860 = sectored_entries_0_4_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_35; // @[TLB.scala:174:61]
assign _sector_hits_T_35 = _T_1860; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_24; // @[TLB.scala:174:61]
assign _hitsVec_T_24 = _T_1860; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_36 = _sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_37 = _sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_38 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_39 = _sector_hits_T_37 & _sector_hits_T_38; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_4 = _sector_hits_T_34 & _sector_hits_T_39; // @[package.scala:81:59]
wire _GEN_9 = sectored_entries_0_5_valid_0 | sectored_entries_0_5_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_40; // @[package.scala:81:59]
assign _sector_hits_T_40 = _GEN_9; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_15; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_15 = _GEN_9; // @[package.scala:81:59]
wire _sector_hits_T_41 = _sector_hits_T_40 | sectored_entries_0_5_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_42 = _sector_hits_T_41 | sectored_entries_0_5_valid_3; // @[package.scala:81:59]
wire [26:0] _T_2281 = sectored_entries_0_5_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_43; // @[TLB.scala:174:61]
assign _sector_hits_T_43 = _T_2281; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_30; // @[TLB.scala:174:61]
assign _hitsVec_T_30 = _T_2281; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_44 = _sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_45 = _sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_46 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_47 = _sector_hits_T_45 & _sector_hits_T_46; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_5 = _sector_hits_T_42 & _sector_hits_T_47; // @[package.scala:81:59]
wire _GEN_10 = sectored_entries_0_6_valid_0 | sectored_entries_0_6_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_48; // @[package.scala:81:59]
assign _sector_hits_T_48 = _GEN_10; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_18; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_18 = _GEN_10; // @[package.scala:81:59]
wire _sector_hits_T_49 = _sector_hits_T_48 | sectored_entries_0_6_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_50 = _sector_hits_T_49 | sectored_entries_0_6_valid_3; // @[package.scala:81:59]
wire [26:0] _T_2702 = sectored_entries_0_6_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_51; // @[TLB.scala:174:61]
assign _sector_hits_T_51 = _T_2702; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_36; // @[TLB.scala:174:61]
assign _hitsVec_T_36 = _T_2702; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_52 = _sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_53 = _sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_54 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_55 = _sector_hits_T_53 & _sector_hits_T_54; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_6 = _sector_hits_T_50 & _sector_hits_T_55; // @[package.scala:81:59]
wire _GEN_11 = sectored_entries_0_7_valid_0 | sectored_entries_0_7_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_56; // @[package.scala:81:59]
assign _sector_hits_T_56 = _GEN_11; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_21; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_21 = _GEN_11; // @[package.scala:81:59]
wire _sector_hits_T_57 = _sector_hits_T_56 | sectored_entries_0_7_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_58 = _sector_hits_T_57 | sectored_entries_0_7_valid_3; // @[package.scala:81:59]
wire [26:0] _T_3123 = sectored_entries_0_7_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_59; // @[TLB.scala:174:61]
assign _sector_hits_T_59 = _T_3123; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_42; // @[TLB.scala:174:61]
assign _hitsVec_T_42 = _T_3123; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_60 = _sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_61 = _sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_62 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_63 = _sector_hits_T_61 & _sector_hits_T_62; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_7 = _sector_hits_T_58 & _sector_hits_T_63; // @[package.scala:81:59]
wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3446 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52]
assign _superpage_hits_T = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52]
assign _superpage_hits_T_5 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52]
assign _superpage_hits_T_10 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_48; // @[TLB.scala:183:52]
assign _hitsVec_T_48 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_53; // @[TLB.scala:183:52]
assign _hitsVec_T_53 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_58; // @[TLB.scala:183:52]
assign _hitsVec_T_58 = _T_3446; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_12 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28]
wire _ppn_ignore_T; // @[TLB.scala:197:28]
assign _ppn_ignore_T = _GEN_12; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_1; // @[TLB.scala:182:28]
assign _ignore_T_1 = _GEN_12; // @[TLB.scala:182:28]
wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_8 = superpage_hits_ignore_1 | _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}]
wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch_1 = superpage_entries_1_valid_0 & _superpage_hits_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3544 = superpage_entries_1_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T_14; // @[TLB.scala:183:52]
assign _superpage_hits_T_14 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_19; // @[TLB.scala:183:52]
assign _superpage_hits_T_19 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_24; // @[TLB.scala:183:52]
assign _superpage_hits_T_24 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_63; // @[TLB.scala:183:52]
assign _hitsVec_T_63 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_68; // @[TLB.scala:183:52]
assign _hitsVec_T_68 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_73; // @[TLB.scala:183:52]
assign _hitsVec_T_73 = _T_3544; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_15 = _superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_16 = _superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_17 = _superpage_hits_T_16; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_18 = superpage_hits_tagMatch_1 & _superpage_hits_T_17; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_13 = superpage_entries_1_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_4; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28]
wire _ppn_ignore_T_2; // @[TLB.scala:197:28]
assign _ppn_ignore_T_2 = _GEN_13; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_4; // @[TLB.scala:182:28]
assign _ignore_T_4 = _GEN_13; // @[TLB.scala:182:28]
wire superpage_hits_ignore_4 = _superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_20 = _superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_21 = _superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_22 = superpage_hits_ignore_4 | _superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_23 = _superpage_hits_T_18 & _superpage_hits_T_22; // @[TLB.scala:183:{29,40}]
wire superpage_hits_1 = _superpage_hits_T_23; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_25 = _superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_26 = _superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch_2 = superpage_entries_2_valid_0 & _superpage_hits_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3642 = superpage_entries_2_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T_28; // @[TLB.scala:183:52]
assign _superpage_hits_T_28 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_33; // @[TLB.scala:183:52]
assign _superpage_hits_T_33 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_38; // @[TLB.scala:183:52]
assign _superpage_hits_T_38 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_78; // @[TLB.scala:183:52]
assign _hitsVec_T_78 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_83; // @[TLB.scala:183:52]
assign _hitsVec_T_83 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_88; // @[TLB.scala:183:52]
assign _hitsVec_T_88 = _T_3642; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_29 = _superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_30 = _superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_31 = _superpage_hits_T_30; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_32 = superpage_hits_tagMatch_2 & _superpage_hits_T_31; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_14 = superpage_entries_2_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_7; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_7; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28]
wire _ppn_ignore_T_4; // @[TLB.scala:197:28]
assign _ppn_ignore_T_4 = _GEN_14; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_7; // @[TLB.scala:182:28]
assign _ignore_T_7 = _GEN_14; // @[TLB.scala:182:28]
wire superpage_hits_ignore_7 = _superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_34 = _superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_35 = _superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_36 = superpage_hits_ignore_7 | _superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_37 = _superpage_hits_T_32 & _superpage_hits_T_36; // @[TLB.scala:183:{29,40}]
wire superpage_hits_2 = _superpage_hits_T_37; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_39 = _superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_40 = _superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch_3 = superpage_entries_3_valid_0 & _superpage_hits_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3740 = superpage_entries_3_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T_42; // @[TLB.scala:183:52]
assign _superpage_hits_T_42 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_47; // @[TLB.scala:183:52]
assign _superpage_hits_T_47 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_52; // @[TLB.scala:183:52]
assign _superpage_hits_T_52 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_93; // @[TLB.scala:183:52]
assign _hitsVec_T_93 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_98; // @[TLB.scala:183:52]
assign _hitsVec_T_98 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_103; // @[TLB.scala:183:52]
assign _hitsVec_T_103 = _T_3740; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_43 = _superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_44 = _superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_45 = _superpage_hits_T_44; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_46 = superpage_hits_tagMatch_3 & _superpage_hits_T_45; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_15 = superpage_entries_3_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_10; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_10; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28]
wire _ppn_ignore_T_6; // @[TLB.scala:197:28]
assign _ppn_ignore_T_6 = _GEN_15; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_10; // @[TLB.scala:182:28]
assign _ignore_T_10 = _GEN_15; // @[TLB.scala:182:28]
wire superpage_hits_ignore_10 = _superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_48 = _superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_49 = _superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_50 = superpage_hits_ignore_10 | _superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_51 = _superpage_hits_T_46 & _superpage_hits_T_50; // @[TLB.scala:183:{29,40}]
wire superpage_hits_3 = _superpage_hits_T_51; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_53 = _superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_54 = _superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [1:0] hitsVec_idx = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_1 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_2 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_3 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_4 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_5 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_6 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_7 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_24 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_48 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_72 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_96 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_120 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_144 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_168 = vpn[1:0]; // @[package.scala:163:13]
wire [24:0] _hitsVec_T_1 = _hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_2 = _hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_3 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_16 = {{sectored_entries_0_0_valid_3}, {sectored_entries_0_0_valid_2}, {sectored_entries_0_0_valid_1}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_5 = _GEN_16[hitsVec_idx] & _hitsVec_T_4; // @[package.scala:163:13]
wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_7 = _hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_8 = _hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_9 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_17 = {{sectored_entries_0_1_valid_3}, {sectored_entries_0_1_valid_2}, {sectored_entries_0_1_valid_1}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_11 = _GEN_17[hitsVec_idx_1] & _hitsVec_T_10; // @[package.scala:163:13]
wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_13 = _hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_14 = _hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_15 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_18 = {{sectored_entries_0_2_valid_3}, {sectored_entries_0_2_valid_2}, {sectored_entries_0_2_valid_1}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_17 = _GEN_18[hitsVec_idx_2] & _hitsVec_T_16; // @[package.scala:163:13]
wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_19 = _hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_20 = _hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_21 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_19 = {{sectored_entries_0_3_valid_3}, {sectored_entries_0_3_valid_2}, {sectored_entries_0_3_valid_1}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_23 = _GEN_19[hitsVec_idx_3] & _hitsVec_T_22; // @[package.scala:163:13]
wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_25 = _hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_26 = _hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_27 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_28 = _hitsVec_T_26 & _hitsVec_T_27; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_20 = {{sectored_entries_0_4_valid_3}, {sectored_entries_0_4_valid_2}, {sectored_entries_0_4_valid_1}, {sectored_entries_0_4_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_29 = _GEN_20[hitsVec_idx_4] & _hitsVec_T_28; // @[package.scala:163:13]
wire hitsVec_4 = vm_enabled & _hitsVec_T_29; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_31 = _hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_32 = _hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_33 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_34 = _hitsVec_T_32 & _hitsVec_T_33; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_21 = {{sectored_entries_0_5_valid_3}, {sectored_entries_0_5_valid_2}, {sectored_entries_0_5_valid_1}, {sectored_entries_0_5_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_35 = _GEN_21[hitsVec_idx_5] & _hitsVec_T_34; // @[package.scala:163:13]
wire hitsVec_5 = vm_enabled & _hitsVec_T_35; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_37 = _hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_38 = _hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_39 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_40 = _hitsVec_T_38 & _hitsVec_T_39; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_22 = {{sectored_entries_0_6_valid_3}, {sectored_entries_0_6_valid_2}, {sectored_entries_0_6_valid_1}, {sectored_entries_0_6_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_41 = _GEN_22[hitsVec_idx_6] & _hitsVec_T_40; // @[package.scala:163:13]
wire hitsVec_6 = vm_enabled & _hitsVec_T_41; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_43 = _hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_44 = _hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_45 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_46 = _hitsVec_T_44 & _hitsVec_T_45; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_23 = {{sectored_entries_0_7_valid_3}, {sectored_entries_0_7_valid_2}, {sectored_entries_0_7_valid_1}, {sectored_entries_0_7_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_47 = _GEN_23[hitsVec_idx_7] & _hitsVec_T_46; // @[package.scala:163:13]
wire hitsVec_7 = vm_enabled & _hitsVec_T_47; // @[TLB.scala:188:18, :399:61, :440:44]
wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_49 = _hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_50 = _hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_51 = _hitsVec_T_50; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_52 = hitsVec_tagMatch & _hitsVec_T_51; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_54 = _hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_55 = _hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_56 = hitsVec_ignore_1 | _hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_57 = _hitsVec_T_52 & _hitsVec_T_56; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_62 = _hitsVec_T_57; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_59 = _hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_60 = _hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_8 = vm_enabled & _hitsVec_T_62; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch_1 = superpage_entries_1_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_64 = _hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_65 = _hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_66 = _hitsVec_T_65; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_67 = hitsVec_tagMatch_1 & _hitsVec_T_66; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_69 = _hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_70 = _hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_71 = hitsVec_ignore_4 | _hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_72 = _hitsVec_T_67 & _hitsVec_T_71; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_77 = _hitsVec_T_72; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_74 = _hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_75 = _hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_9 = vm_enabled & _hitsVec_T_77; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch_2 = superpage_entries_2_valid_0 & _hitsVec_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_79 = _hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_80 = _hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_81 = _hitsVec_T_80; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_82 = hitsVec_tagMatch_2 & _hitsVec_T_81; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_7 = _hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_84 = _hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_85 = _hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_86 = hitsVec_ignore_7 | _hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_87 = _hitsVec_T_82 & _hitsVec_T_86; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_92 = _hitsVec_T_87; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_89 = _hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_90 = _hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_10 = vm_enabled & _hitsVec_T_92; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch_3 = superpage_entries_3_valid_0 & _hitsVec_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_94 = _hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_95 = _hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_96 = _hitsVec_T_95; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_97 = hitsVec_tagMatch_3 & _hitsVec_T_96; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_10 = _hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_99 = _hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_100 = _hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_101 = hitsVec_ignore_10 | _hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_102 = _hitsVec_T_97 & _hitsVec_T_101; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_107 = _hitsVec_T_102; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_104 = _hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_105 = _hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_11 = vm_enabled & _hitsVec_T_107; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_4 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56]
wire hitsVec_tagMatch_4 = special_entry_valid_0 & _hitsVec_tagMatch_T_4; // @[TLB.scala:178:{33,43}, :346:56]
wire [26:0] _T_3838 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56]
wire [26:0] _hitsVec_T_108; // @[TLB.scala:183:52]
assign _hitsVec_T_108 = _T_3838; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_113; // @[TLB.scala:183:52]
assign _hitsVec_T_113 = _T_3838; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_118; // @[TLB.scala:183:52]
assign _hitsVec_T_118 = _T_3838; // @[TLB.scala:183:52]
wire [8:0] _hitsVec_T_109 = _hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_110 = _hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_111 = _hitsVec_T_110; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_112 = hitsVec_tagMatch_4 & _hitsVec_T_111; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_13 = _hitsVec_ignore_T_13; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_114 = _hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_115 = _hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_116 = hitsVec_ignore_13 | _hitsVec_T_115; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_117 = _hitsVec_T_112 & _hitsVec_T_116; // @[TLB.scala:183:{29,40}]
wire _hitsVec_ignore_T_14 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56]
wire hitsVec_ignore_14 = _hitsVec_ignore_T_14; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_119 = _hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_120 = _hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_121 = hitsVec_ignore_14 | _hitsVec_T_120; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_122 = _hitsVec_T_117 & _hitsVec_T_121; // @[TLB.scala:183:{29,40}]
wire hitsVec_12 = vm_enabled & _hitsVec_T_122; // @[TLB.scala:183:29, :399:61, :440:44]
wire [1:0] real_hits_lo_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27]
wire [2:0] real_hits_lo_lo = {real_hits_lo_lo_hi, hitsVec_0}; // @[package.scala:45:27]
wire [1:0] real_hits_lo_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27]
wire [2:0] real_hits_lo_hi = {real_hits_lo_hi_hi, hitsVec_3}; // @[package.scala:45:27]
wire [5:0] real_hits_lo = {real_hits_lo_hi, real_hits_lo_lo}; // @[package.scala:45:27]
wire [1:0] real_hits_hi_lo_hi = {hitsVec_8, hitsVec_7}; // @[package.scala:45:27]
wire [2:0] real_hits_hi_lo = {real_hits_hi_lo_hi, hitsVec_6}; // @[package.scala:45:27]
wire [1:0] real_hits_hi_hi_lo = {hitsVec_10, hitsVec_9}; // @[package.scala:45:27]
wire [1:0] real_hits_hi_hi_hi = {hitsVec_12, hitsVec_11}; // @[package.scala:45:27]
wire [3:0] real_hits_hi_hi = {real_hits_hi_hi_hi, real_hits_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] real_hits_hi = {real_hits_hi_hi, real_hits_hi_lo}; // @[package.scala:45:27]
wire [12:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27]
wire [12:0] _tlb_hit_T = real_hits; // @[package.scala:45:27]
wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18]
wire [13:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27]
wire _newEntry_g_T; // @[TLB.scala:453:25]
wire _newEntry_sw_T_6; // @[PTW.scala:151:40]
wire _newEntry_sx_T_5; // @[PTW.scala:153:35]
wire _newEntry_sr_T_5; // @[PTW.scala:149:35]
wire newEntry_g; // @[TLB.scala:449:24]
wire newEntry_sw; // @[TLB.scala:449:24]
wire newEntry_sx; // @[TLB.scala:449:24]
wire newEntry_sr; // @[TLB.scala:449:24]
wire newEntry_ppp; // @[TLB.scala:449:24]
wire newEntry_pal; // @[TLB.scala:449:24]
wire newEntry_paa; // @[TLB.scala:449:24]
wire newEntry_eff; // @[TLB.scala:449:24]
assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25]
assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25]
wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53]
wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7]
wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sr_T_1; // @[TLB.scala:318:7]
wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7]
wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7]
assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24]
wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7]
wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sw_T_1; // @[TLB.scala:318:7]
wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7]
wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7]
assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24]
wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7]
wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sx_T_1; // @[TLB.scala:318:7]
wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7]
wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7]
assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24]
wire [1:0] _GEN_24 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] _GEN_25 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_26 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [1:0] _GEN_27 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_28 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [1:0] _GEN_29 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_30 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [20:0] _GEN_31 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24]
wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_0_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_1_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_2_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_3_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_4_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_5_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_6_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_7_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24]
wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_lo_lo_hi = {superpage_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_lo_hi_lo = {superpage_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_1_data_0_lo_hi_hi = {superpage_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_hi_lo_lo = {superpage_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_1_data_0_hi_lo_hi = {superpage_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_hi_hi_lo = {superpage_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_1_data_0_hi_hi_hi = {superpage_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_lo_lo_hi = {superpage_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_lo_hi_lo = {superpage_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_2_data_0_lo_hi_hi = {superpage_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_hi_lo_lo = {superpage_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_2_data_0_hi_lo_hi = {superpage_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_hi_hi_lo = {superpage_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_2_data_0_hi_hi_hi = {superpage_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_lo_lo_hi = {superpage_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_lo_hi_lo = {superpage_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_3_data_0_lo_hi_hi = {superpage_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_hi_lo_lo = {superpage_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_3_data_0_hi_lo_hi = {superpage_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_hi_hi_lo = {superpage_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_3_data_0_hi_hi_hi = {superpage_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22]
wire [1:0] idx = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_1 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_2 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_3 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_4 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_5 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_6 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_7 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [2:0] sectored_entries_0_0_data_lo_lo_hi = {sectored_entries_0_0_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_0_data_lo_lo = {sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_lo_hi_lo = {sectored_entries_0_0_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_0_data_lo_hi_hi = {sectored_entries_0_0_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_0_data_lo_hi = {sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_0_data_lo = {sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_hi_lo_lo = {sectored_entries_0_0_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_0_data_hi_lo_hi = {sectored_entries_0_0_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_0_data_hi_lo = {sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_hi_hi_lo = {sectored_entries_0_0_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_0_data_hi_hi_hi = {sectored_entries_0_0_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_0_data_hi_hi = {sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_0_data_hi = {sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_0_data_T = {sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_lo_lo_hi = {sectored_entries_0_1_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_1_data_lo_lo = {sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_lo_hi_lo = {sectored_entries_0_1_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_1_data_lo_hi_hi = {sectored_entries_0_1_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_1_data_lo_hi = {sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_1_data_lo = {sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_hi_lo_lo = {sectored_entries_0_1_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_1_data_hi_lo_hi = {sectored_entries_0_1_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_1_data_hi_lo = {sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_hi_hi_lo = {sectored_entries_0_1_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_1_data_hi_hi_hi = {sectored_entries_0_1_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_1_data_hi_hi = {sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_1_data_hi = {sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_1_data_T = {sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_lo_lo_hi = {sectored_entries_0_2_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_2_data_lo_lo = {sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_lo_hi_lo = {sectored_entries_0_2_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_2_data_lo_hi_hi = {sectored_entries_0_2_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_2_data_lo_hi = {sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_2_data_lo = {sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_hi_lo_lo = {sectored_entries_0_2_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_2_data_hi_lo_hi = {sectored_entries_0_2_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_2_data_hi_lo = {sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_hi_hi_lo = {sectored_entries_0_2_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_2_data_hi_hi_hi = {sectored_entries_0_2_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_2_data_hi_hi = {sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_2_data_hi = {sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_2_data_T = {sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_lo_lo_hi = {sectored_entries_0_3_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_3_data_lo_lo = {sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_lo_hi_lo = {sectored_entries_0_3_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_3_data_lo_hi_hi = {sectored_entries_0_3_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_3_data_lo_hi = {sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_3_data_lo = {sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_hi_lo_lo = {sectored_entries_0_3_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_3_data_hi_lo_hi = {sectored_entries_0_3_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_3_data_hi_lo = {sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_hi_hi_lo = {sectored_entries_0_3_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_3_data_hi_hi_hi = {sectored_entries_0_3_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_3_data_hi_hi = {sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_3_data_hi = {sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_3_data_T = {sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_lo_lo_hi = {sectored_entries_0_4_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_4_data_lo_lo = {sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_lo_hi_lo = {sectored_entries_0_4_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_4_data_lo_hi_hi = {sectored_entries_0_4_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_4_data_lo_hi = {sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_4_data_lo = {sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_hi_lo_lo = {sectored_entries_0_4_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_4_data_hi_lo_hi = {sectored_entries_0_4_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_4_data_hi_lo = {sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_hi_hi_lo = {sectored_entries_0_4_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_4_data_hi_hi_hi = {sectored_entries_0_4_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_4_data_hi_hi = {sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_4_data_hi = {sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_4_data_T = {sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_lo_lo_hi = {sectored_entries_0_5_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_5_data_lo_lo = {sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_lo_hi_lo = {sectored_entries_0_5_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_5_data_lo_hi_hi = {sectored_entries_0_5_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_5_data_lo_hi = {sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_5_data_lo = {sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_hi_lo_lo = {sectored_entries_0_5_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_5_data_hi_lo_hi = {sectored_entries_0_5_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_5_data_hi_lo = {sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_hi_hi_lo = {sectored_entries_0_5_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_5_data_hi_hi_hi = {sectored_entries_0_5_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_5_data_hi_hi = {sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_5_data_hi = {sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_5_data_T = {sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_lo_lo_hi = {sectored_entries_0_6_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_6_data_lo_lo = {sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_lo_hi_lo = {sectored_entries_0_6_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_6_data_lo_hi_hi = {sectored_entries_0_6_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_6_data_lo_hi = {sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_6_data_lo = {sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_hi_lo_lo = {sectored_entries_0_6_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_6_data_hi_lo_hi = {sectored_entries_0_6_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_6_data_hi_lo = {sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_hi_hi_lo = {sectored_entries_0_6_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_6_data_hi_hi_hi = {sectored_entries_0_6_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_6_data_hi_hi = {sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_6_data_hi = {sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_6_data_T = {sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_lo_lo_hi = {sectored_entries_0_7_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_7_data_lo_lo = {sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_lo_hi_lo = {sectored_entries_0_7_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_7_data_lo_hi_hi = {sectored_entries_0_7_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_7_data_lo_hi = {sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_7_data_lo = {sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_hi_lo_lo = {sectored_entries_0_7_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_7_data_hi_lo_hi = {sectored_entries_0_7_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_7_data_hi_lo = {sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_hi_hi_lo = {sectored_entries_0_7_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_7_data_hi_hi_hi = {sectored_entries_0_7_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_7_data_hi_hi = {sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_7_data_hi = {sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_7_data_T = {sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24]
wire [19:0] _entries_T_23; // @[TLB.scala:170:77]
wire _entries_T_22; // @[TLB.scala:170:77]
wire _entries_T_21; // @[TLB.scala:170:77]
wire _entries_T_20; // @[TLB.scala:170:77]
wire _entries_T_19; // @[TLB.scala:170:77]
wire _entries_T_18; // @[TLB.scala:170:77]
wire _entries_T_17; // @[TLB.scala:170:77]
wire _entries_T_16; // @[TLB.scala:170:77]
wire _entries_T_15; // @[TLB.scala:170:77]
wire _entries_T_14; // @[TLB.scala:170:77]
wire _entries_T_13; // @[TLB.scala:170:77]
wire _entries_T_12; // @[TLB.scala:170:77]
wire _entries_T_11; // @[TLB.scala:170:77]
wire _entries_T_10; // @[TLB.scala:170:77]
wire _entries_T_9; // @[TLB.scala:170:77]
wire _entries_T_8; // @[TLB.scala:170:77]
wire _entries_T_7; // @[TLB.scala:170:77]
wire _entries_T_6; // @[TLB.scala:170:77]
wire _entries_T_5; // @[TLB.scala:170:77]
wire _entries_T_4; // @[TLB.scala:170:77]
wire _entries_T_3; // @[TLB.scala:170:77]
wire _entries_T_2; // @[TLB.scala:170:77]
wire _entries_T_1; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_32 = {{sectored_entries_0_0_data_3}, {sectored_entries_0_0_data_2}, {sectored_entries_0_0_data_1}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_1 = _GEN_32[_entries_T]; // @[package.scala:163:13]
assign _entries_T_1 = _entries_WIRE_1[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[TLB.scala:170:77]
assign _entries_T_2 = _entries_WIRE_1[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_c = _entries_T_2; // @[TLB.scala:170:77]
assign _entries_T_3 = _entries_WIRE_1[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_eff = _entries_T_3; // @[TLB.scala:170:77]
assign _entries_T_4 = _entries_WIRE_1[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_paa = _entries_T_4; // @[TLB.scala:170:77]
assign _entries_T_5 = _entries_WIRE_1[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_pal = _entries_T_5; // @[TLB.scala:170:77]
assign _entries_T_6 = _entries_WIRE_1[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_ppp = _entries_T_6; // @[TLB.scala:170:77]
assign _entries_T_7 = _entries_WIRE_1[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_pr = _entries_T_7; // @[TLB.scala:170:77]
assign _entries_T_8 = _entries_WIRE_1[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_px = _entries_T_8; // @[TLB.scala:170:77]
assign _entries_T_9 = _entries_WIRE_1[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_pw = _entries_T_9; // @[TLB.scala:170:77]
assign _entries_T_10 = _entries_WIRE_1[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_hr = _entries_T_10; // @[TLB.scala:170:77]
assign _entries_T_11 = _entries_WIRE_1[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_hx = _entries_T_11; // @[TLB.scala:170:77]
assign _entries_T_12 = _entries_WIRE_1[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_hw = _entries_T_12; // @[TLB.scala:170:77]
assign _entries_T_13 = _entries_WIRE_1[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_sr = _entries_T_13; // @[TLB.scala:170:77]
assign _entries_T_14 = _entries_WIRE_1[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_sx = _entries_T_14; // @[TLB.scala:170:77]
assign _entries_T_15 = _entries_WIRE_1[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_sw = _entries_T_15; // @[TLB.scala:170:77]
assign _entries_T_16 = _entries_WIRE_1[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_gf = _entries_T_16; // @[TLB.scala:170:77]
assign _entries_T_17 = _entries_WIRE_1[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_pf = _entries_T_17; // @[TLB.scala:170:77]
assign _entries_T_18 = _entries_WIRE_1[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_stage2 = _entries_T_18; // @[TLB.scala:170:77]
assign _entries_T_19 = _entries_WIRE_1[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_final = _entries_T_19; // @[TLB.scala:170:77]
assign _entries_T_20 = _entries_WIRE_1[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_ptw = _entries_T_20; // @[TLB.scala:170:77]
assign _entries_T_21 = _entries_WIRE_1[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_g = _entries_T_21; // @[TLB.scala:170:77]
assign _entries_T_22 = _entries_WIRE_1[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_u = _entries_T_22; // @[TLB.scala:170:77]
assign _entries_T_23 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_ppn = _entries_T_23; // @[TLB.scala:170:77]
wire [19:0] _entries_T_47; // @[TLB.scala:170:77]
wire _entries_T_46; // @[TLB.scala:170:77]
wire _entries_T_45; // @[TLB.scala:170:77]
wire _entries_T_44; // @[TLB.scala:170:77]
wire _entries_T_43; // @[TLB.scala:170:77]
wire _entries_T_42; // @[TLB.scala:170:77]
wire _entries_T_41; // @[TLB.scala:170:77]
wire _entries_T_40; // @[TLB.scala:170:77]
wire _entries_T_39; // @[TLB.scala:170:77]
wire _entries_T_38; // @[TLB.scala:170:77]
wire _entries_T_37; // @[TLB.scala:170:77]
wire _entries_T_36; // @[TLB.scala:170:77]
wire _entries_T_35; // @[TLB.scala:170:77]
wire _entries_T_34; // @[TLB.scala:170:77]
wire _entries_T_33; // @[TLB.scala:170:77]
wire _entries_T_32; // @[TLB.scala:170:77]
wire _entries_T_31; // @[TLB.scala:170:77]
wire _entries_T_30; // @[TLB.scala:170:77]
wire _entries_T_29; // @[TLB.scala:170:77]
wire _entries_T_28; // @[TLB.scala:170:77]
wire _entries_T_27; // @[TLB.scala:170:77]
wire _entries_T_26; // @[TLB.scala:170:77]
wire _entries_T_25; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_33 = {{sectored_entries_0_1_data_3}, {sectored_entries_0_1_data_2}, {sectored_entries_0_1_data_1}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_3 = _GEN_33[_entries_T_24]; // @[package.scala:163:13]
assign _entries_T_25 = _entries_WIRE_3[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_fragmented_superpage = _entries_T_25; // @[TLB.scala:170:77]
assign _entries_T_26 = _entries_WIRE_3[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_c = _entries_T_26; // @[TLB.scala:170:77]
assign _entries_T_27 = _entries_WIRE_3[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_eff = _entries_T_27; // @[TLB.scala:170:77]
assign _entries_T_28 = _entries_WIRE_3[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_paa = _entries_T_28; // @[TLB.scala:170:77]
assign _entries_T_29 = _entries_WIRE_3[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pal = _entries_T_29; // @[TLB.scala:170:77]
assign _entries_T_30 = _entries_WIRE_3[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ppp = _entries_T_30; // @[TLB.scala:170:77]
assign _entries_T_31 = _entries_WIRE_3[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pr = _entries_T_31; // @[TLB.scala:170:77]
assign _entries_T_32 = _entries_WIRE_3[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_px = _entries_T_32; // @[TLB.scala:170:77]
assign _entries_T_33 = _entries_WIRE_3[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pw = _entries_T_33; // @[TLB.scala:170:77]
assign _entries_T_34 = _entries_WIRE_3[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hr = _entries_T_34; // @[TLB.scala:170:77]
assign _entries_T_35 = _entries_WIRE_3[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hx = _entries_T_35; // @[TLB.scala:170:77]
assign _entries_T_36 = _entries_WIRE_3[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hw = _entries_T_36; // @[TLB.scala:170:77]
assign _entries_T_37 = _entries_WIRE_3[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sr = _entries_T_37; // @[TLB.scala:170:77]
assign _entries_T_38 = _entries_WIRE_3[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sx = _entries_T_38; // @[TLB.scala:170:77]
assign _entries_T_39 = _entries_WIRE_3[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sw = _entries_T_39; // @[TLB.scala:170:77]
assign _entries_T_40 = _entries_WIRE_3[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_gf = _entries_T_40; // @[TLB.scala:170:77]
assign _entries_T_41 = _entries_WIRE_3[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pf = _entries_T_41; // @[TLB.scala:170:77]
assign _entries_T_42 = _entries_WIRE_3[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_stage2 = _entries_T_42; // @[TLB.scala:170:77]
assign _entries_T_43 = _entries_WIRE_3[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_final = _entries_T_43; // @[TLB.scala:170:77]
assign _entries_T_44 = _entries_WIRE_3[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_ptw = _entries_T_44; // @[TLB.scala:170:77]
assign _entries_T_45 = _entries_WIRE_3[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_g = _entries_T_45; // @[TLB.scala:170:77]
assign _entries_T_46 = _entries_WIRE_3[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_u = _entries_T_46; // @[TLB.scala:170:77]
assign _entries_T_47 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_2_ppn = _entries_T_47; // @[TLB.scala:170:77]
wire [19:0] _entries_T_71; // @[TLB.scala:170:77]
wire _entries_T_70; // @[TLB.scala:170:77]
wire _entries_T_69; // @[TLB.scala:170:77]
wire _entries_T_68; // @[TLB.scala:170:77]
wire _entries_T_67; // @[TLB.scala:170:77]
wire _entries_T_66; // @[TLB.scala:170:77]
wire _entries_T_65; // @[TLB.scala:170:77]
wire _entries_T_64; // @[TLB.scala:170:77]
wire _entries_T_63; // @[TLB.scala:170:77]
wire _entries_T_62; // @[TLB.scala:170:77]
wire _entries_T_61; // @[TLB.scala:170:77]
wire _entries_T_60; // @[TLB.scala:170:77]
wire _entries_T_59; // @[TLB.scala:170:77]
wire _entries_T_58; // @[TLB.scala:170:77]
wire _entries_T_57; // @[TLB.scala:170:77]
wire _entries_T_56; // @[TLB.scala:170:77]
wire _entries_T_55; // @[TLB.scala:170:77]
wire _entries_T_54; // @[TLB.scala:170:77]
wire _entries_T_53; // @[TLB.scala:170:77]
wire _entries_T_52; // @[TLB.scala:170:77]
wire _entries_T_51; // @[TLB.scala:170:77]
wire _entries_T_50; // @[TLB.scala:170:77]
wire _entries_T_49; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_34 = {{sectored_entries_0_2_data_3}, {sectored_entries_0_2_data_2}, {sectored_entries_0_2_data_1}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_5 = _GEN_34[_entries_T_48]; // @[package.scala:163:13]
assign _entries_T_49 = _entries_WIRE_5[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_fragmented_superpage = _entries_T_49; // @[TLB.scala:170:77]
assign _entries_T_50 = _entries_WIRE_5[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_c = _entries_T_50; // @[TLB.scala:170:77]
assign _entries_T_51 = _entries_WIRE_5[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_eff = _entries_T_51; // @[TLB.scala:170:77]
assign _entries_T_52 = _entries_WIRE_5[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_paa = _entries_T_52; // @[TLB.scala:170:77]
assign _entries_T_53 = _entries_WIRE_5[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pal = _entries_T_53; // @[TLB.scala:170:77]
assign _entries_T_54 = _entries_WIRE_5[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ppp = _entries_T_54; // @[TLB.scala:170:77]
assign _entries_T_55 = _entries_WIRE_5[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pr = _entries_T_55; // @[TLB.scala:170:77]
assign _entries_T_56 = _entries_WIRE_5[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_px = _entries_T_56; // @[TLB.scala:170:77]
assign _entries_T_57 = _entries_WIRE_5[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pw = _entries_T_57; // @[TLB.scala:170:77]
assign _entries_T_58 = _entries_WIRE_5[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hr = _entries_T_58; // @[TLB.scala:170:77]
assign _entries_T_59 = _entries_WIRE_5[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hx = _entries_T_59; // @[TLB.scala:170:77]
assign _entries_T_60 = _entries_WIRE_5[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hw = _entries_T_60; // @[TLB.scala:170:77]
assign _entries_T_61 = _entries_WIRE_5[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sr = _entries_T_61; // @[TLB.scala:170:77]
assign _entries_T_62 = _entries_WIRE_5[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sx = _entries_T_62; // @[TLB.scala:170:77]
assign _entries_T_63 = _entries_WIRE_5[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sw = _entries_T_63; // @[TLB.scala:170:77]
assign _entries_T_64 = _entries_WIRE_5[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_gf = _entries_T_64; // @[TLB.scala:170:77]
assign _entries_T_65 = _entries_WIRE_5[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pf = _entries_T_65; // @[TLB.scala:170:77]
assign _entries_T_66 = _entries_WIRE_5[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_stage2 = _entries_T_66; // @[TLB.scala:170:77]
assign _entries_T_67 = _entries_WIRE_5[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_final = _entries_T_67; // @[TLB.scala:170:77]
assign _entries_T_68 = _entries_WIRE_5[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_ptw = _entries_T_68; // @[TLB.scala:170:77]
assign _entries_T_69 = _entries_WIRE_5[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_g = _entries_T_69; // @[TLB.scala:170:77]
assign _entries_T_70 = _entries_WIRE_5[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_u = _entries_T_70; // @[TLB.scala:170:77]
assign _entries_T_71 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_4_ppn = _entries_T_71; // @[TLB.scala:170:77]
wire [19:0] _entries_T_95; // @[TLB.scala:170:77]
wire _entries_T_94; // @[TLB.scala:170:77]
wire _entries_T_93; // @[TLB.scala:170:77]
wire _entries_T_92; // @[TLB.scala:170:77]
wire _entries_T_91; // @[TLB.scala:170:77]
wire _entries_T_90; // @[TLB.scala:170:77]
wire _entries_T_89; // @[TLB.scala:170:77]
wire _entries_T_88; // @[TLB.scala:170:77]
wire _entries_T_87; // @[TLB.scala:170:77]
wire _entries_T_86; // @[TLB.scala:170:77]
wire _entries_T_85; // @[TLB.scala:170:77]
wire _entries_T_84; // @[TLB.scala:170:77]
wire _entries_T_83; // @[TLB.scala:170:77]
wire _entries_T_82; // @[TLB.scala:170:77]
wire _entries_T_81; // @[TLB.scala:170:77]
wire _entries_T_80; // @[TLB.scala:170:77]
wire _entries_T_79; // @[TLB.scala:170:77]
wire _entries_T_78; // @[TLB.scala:170:77]
wire _entries_T_77; // @[TLB.scala:170:77]
wire _entries_T_76; // @[TLB.scala:170:77]
wire _entries_T_75; // @[TLB.scala:170:77]
wire _entries_T_74; // @[TLB.scala:170:77]
wire _entries_T_73; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_35 = {{sectored_entries_0_3_data_3}, {sectored_entries_0_3_data_2}, {sectored_entries_0_3_data_1}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_7 = _GEN_35[_entries_T_72]; // @[package.scala:163:13]
assign _entries_T_73 = _entries_WIRE_7[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_fragmented_superpage = _entries_T_73; // @[TLB.scala:170:77]
assign _entries_T_74 = _entries_WIRE_7[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_c = _entries_T_74; // @[TLB.scala:170:77]
assign _entries_T_75 = _entries_WIRE_7[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_eff = _entries_T_75; // @[TLB.scala:170:77]
assign _entries_T_76 = _entries_WIRE_7[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_paa = _entries_T_76; // @[TLB.scala:170:77]
assign _entries_T_77 = _entries_WIRE_7[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pal = _entries_T_77; // @[TLB.scala:170:77]
assign _entries_T_78 = _entries_WIRE_7[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ppp = _entries_T_78; // @[TLB.scala:170:77]
assign _entries_T_79 = _entries_WIRE_7[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pr = _entries_T_79; // @[TLB.scala:170:77]
assign _entries_T_80 = _entries_WIRE_7[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_px = _entries_T_80; // @[TLB.scala:170:77]
assign _entries_T_81 = _entries_WIRE_7[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pw = _entries_T_81; // @[TLB.scala:170:77]
assign _entries_T_82 = _entries_WIRE_7[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hr = _entries_T_82; // @[TLB.scala:170:77]
assign _entries_T_83 = _entries_WIRE_7[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hx = _entries_T_83; // @[TLB.scala:170:77]
assign _entries_T_84 = _entries_WIRE_7[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hw = _entries_T_84; // @[TLB.scala:170:77]
assign _entries_T_85 = _entries_WIRE_7[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sr = _entries_T_85; // @[TLB.scala:170:77]
assign _entries_T_86 = _entries_WIRE_7[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sx = _entries_T_86; // @[TLB.scala:170:77]
assign _entries_T_87 = _entries_WIRE_7[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sw = _entries_T_87; // @[TLB.scala:170:77]
assign _entries_T_88 = _entries_WIRE_7[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_gf = _entries_T_88; // @[TLB.scala:170:77]
assign _entries_T_89 = _entries_WIRE_7[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pf = _entries_T_89; // @[TLB.scala:170:77]
assign _entries_T_90 = _entries_WIRE_7[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_stage2 = _entries_T_90; // @[TLB.scala:170:77]
assign _entries_T_91 = _entries_WIRE_7[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_final = _entries_T_91; // @[TLB.scala:170:77]
assign _entries_T_92 = _entries_WIRE_7[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_ptw = _entries_T_92; // @[TLB.scala:170:77]
assign _entries_T_93 = _entries_WIRE_7[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_g = _entries_T_93; // @[TLB.scala:170:77]
assign _entries_T_94 = _entries_WIRE_7[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_u = _entries_T_94; // @[TLB.scala:170:77]
assign _entries_T_95 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_6_ppn = _entries_T_95; // @[TLB.scala:170:77]
wire [19:0] _entries_T_119; // @[TLB.scala:170:77]
wire _entries_T_118; // @[TLB.scala:170:77]
wire _entries_T_117; // @[TLB.scala:170:77]
wire _entries_T_116; // @[TLB.scala:170:77]
wire _entries_T_115; // @[TLB.scala:170:77]
wire _entries_T_114; // @[TLB.scala:170:77]
wire _entries_T_113; // @[TLB.scala:170:77]
wire _entries_T_112; // @[TLB.scala:170:77]
wire _entries_T_111; // @[TLB.scala:170:77]
wire _entries_T_110; // @[TLB.scala:170:77]
wire _entries_T_109; // @[TLB.scala:170:77]
wire _entries_T_108; // @[TLB.scala:170:77]
wire _entries_T_107; // @[TLB.scala:170:77]
wire _entries_T_106; // @[TLB.scala:170:77]
wire _entries_T_105; // @[TLB.scala:170:77]
wire _entries_T_104; // @[TLB.scala:170:77]
wire _entries_T_103; // @[TLB.scala:170:77]
wire _entries_T_102; // @[TLB.scala:170:77]
wire _entries_T_101; // @[TLB.scala:170:77]
wire _entries_T_100; // @[TLB.scala:170:77]
wire _entries_T_99; // @[TLB.scala:170:77]
wire _entries_T_98; // @[TLB.scala:170:77]
wire _entries_T_97; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_36 = {{sectored_entries_0_4_data_3}, {sectored_entries_0_4_data_2}, {sectored_entries_0_4_data_1}, {sectored_entries_0_4_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_9 = _GEN_36[_entries_T_96]; // @[package.scala:163:13]
assign _entries_T_97 = _entries_WIRE_9[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_fragmented_superpage = _entries_T_97; // @[TLB.scala:170:77]
assign _entries_T_98 = _entries_WIRE_9[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_c = _entries_T_98; // @[TLB.scala:170:77]
assign _entries_T_99 = _entries_WIRE_9[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_eff = _entries_T_99; // @[TLB.scala:170:77]
assign _entries_T_100 = _entries_WIRE_9[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_paa = _entries_T_100; // @[TLB.scala:170:77]
assign _entries_T_101 = _entries_WIRE_9[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pal = _entries_T_101; // @[TLB.scala:170:77]
assign _entries_T_102 = _entries_WIRE_9[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ppp = _entries_T_102; // @[TLB.scala:170:77]
assign _entries_T_103 = _entries_WIRE_9[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pr = _entries_T_103; // @[TLB.scala:170:77]
assign _entries_T_104 = _entries_WIRE_9[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_px = _entries_T_104; // @[TLB.scala:170:77]
assign _entries_T_105 = _entries_WIRE_9[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pw = _entries_T_105; // @[TLB.scala:170:77]
assign _entries_T_106 = _entries_WIRE_9[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hr = _entries_T_106; // @[TLB.scala:170:77]
assign _entries_T_107 = _entries_WIRE_9[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hx = _entries_T_107; // @[TLB.scala:170:77]
assign _entries_T_108 = _entries_WIRE_9[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hw = _entries_T_108; // @[TLB.scala:170:77]
assign _entries_T_109 = _entries_WIRE_9[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sr = _entries_T_109; // @[TLB.scala:170:77]
assign _entries_T_110 = _entries_WIRE_9[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sx = _entries_T_110; // @[TLB.scala:170:77]
assign _entries_T_111 = _entries_WIRE_9[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sw = _entries_T_111; // @[TLB.scala:170:77]
assign _entries_T_112 = _entries_WIRE_9[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_gf = _entries_T_112; // @[TLB.scala:170:77]
assign _entries_T_113 = _entries_WIRE_9[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pf = _entries_T_113; // @[TLB.scala:170:77]
assign _entries_T_114 = _entries_WIRE_9[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_stage2 = _entries_T_114; // @[TLB.scala:170:77]
assign _entries_T_115 = _entries_WIRE_9[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_final = _entries_T_115; // @[TLB.scala:170:77]
assign _entries_T_116 = _entries_WIRE_9[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_ptw = _entries_T_116; // @[TLB.scala:170:77]
assign _entries_T_117 = _entries_WIRE_9[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_g = _entries_T_117; // @[TLB.scala:170:77]
assign _entries_T_118 = _entries_WIRE_9[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_u = _entries_T_118; // @[TLB.scala:170:77]
assign _entries_T_119 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_8_ppn = _entries_T_119; // @[TLB.scala:170:77]
wire [19:0] _entries_T_143; // @[TLB.scala:170:77]
wire _entries_T_142; // @[TLB.scala:170:77]
wire _entries_T_141; // @[TLB.scala:170:77]
wire _entries_T_140; // @[TLB.scala:170:77]
wire _entries_T_139; // @[TLB.scala:170:77]
wire _entries_T_138; // @[TLB.scala:170:77]
wire _entries_T_137; // @[TLB.scala:170:77]
wire _entries_T_136; // @[TLB.scala:170:77]
wire _entries_T_135; // @[TLB.scala:170:77]
wire _entries_T_134; // @[TLB.scala:170:77]
wire _entries_T_133; // @[TLB.scala:170:77]
wire _entries_T_132; // @[TLB.scala:170:77]
wire _entries_T_131; // @[TLB.scala:170:77]
wire _entries_T_130; // @[TLB.scala:170:77]
wire _entries_T_129; // @[TLB.scala:170:77]
wire _entries_T_128; // @[TLB.scala:170:77]
wire _entries_T_127; // @[TLB.scala:170:77]
wire _entries_T_126; // @[TLB.scala:170:77]
wire _entries_T_125; // @[TLB.scala:170:77]
wire _entries_T_124; // @[TLB.scala:170:77]
wire _entries_T_123; // @[TLB.scala:170:77]
wire _entries_T_122; // @[TLB.scala:170:77]
wire _entries_T_121; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_37 = {{sectored_entries_0_5_data_3}, {sectored_entries_0_5_data_2}, {sectored_entries_0_5_data_1}, {sectored_entries_0_5_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_11 = _GEN_37[_entries_T_120]; // @[package.scala:163:13]
assign _entries_T_121 = _entries_WIRE_11[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_fragmented_superpage = _entries_T_121; // @[TLB.scala:170:77]
assign _entries_T_122 = _entries_WIRE_11[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_c = _entries_T_122; // @[TLB.scala:170:77]
assign _entries_T_123 = _entries_WIRE_11[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_eff = _entries_T_123; // @[TLB.scala:170:77]
assign _entries_T_124 = _entries_WIRE_11[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_paa = _entries_T_124; // @[TLB.scala:170:77]
assign _entries_T_125 = _entries_WIRE_11[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pal = _entries_T_125; // @[TLB.scala:170:77]
assign _entries_T_126 = _entries_WIRE_11[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ppp = _entries_T_126; // @[TLB.scala:170:77]
assign _entries_T_127 = _entries_WIRE_11[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pr = _entries_T_127; // @[TLB.scala:170:77]
assign _entries_T_128 = _entries_WIRE_11[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_px = _entries_T_128; // @[TLB.scala:170:77]
assign _entries_T_129 = _entries_WIRE_11[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pw = _entries_T_129; // @[TLB.scala:170:77]
assign _entries_T_130 = _entries_WIRE_11[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hr = _entries_T_130; // @[TLB.scala:170:77]
assign _entries_T_131 = _entries_WIRE_11[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hx = _entries_T_131; // @[TLB.scala:170:77]
assign _entries_T_132 = _entries_WIRE_11[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hw = _entries_T_132; // @[TLB.scala:170:77]
assign _entries_T_133 = _entries_WIRE_11[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sr = _entries_T_133; // @[TLB.scala:170:77]
assign _entries_T_134 = _entries_WIRE_11[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sx = _entries_T_134; // @[TLB.scala:170:77]
assign _entries_T_135 = _entries_WIRE_11[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sw = _entries_T_135; // @[TLB.scala:170:77]
assign _entries_T_136 = _entries_WIRE_11[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_gf = _entries_T_136; // @[TLB.scala:170:77]
assign _entries_T_137 = _entries_WIRE_11[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pf = _entries_T_137; // @[TLB.scala:170:77]
assign _entries_T_138 = _entries_WIRE_11[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_stage2 = _entries_T_138; // @[TLB.scala:170:77]
assign _entries_T_139 = _entries_WIRE_11[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_final = _entries_T_139; // @[TLB.scala:170:77]
assign _entries_T_140 = _entries_WIRE_11[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_ptw = _entries_T_140; // @[TLB.scala:170:77]
assign _entries_T_141 = _entries_WIRE_11[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_g = _entries_T_141; // @[TLB.scala:170:77]
assign _entries_T_142 = _entries_WIRE_11[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_u = _entries_T_142; // @[TLB.scala:170:77]
assign _entries_T_143 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_10_ppn = _entries_T_143; // @[TLB.scala:170:77]
wire [19:0] _entries_T_167; // @[TLB.scala:170:77]
wire _entries_T_166; // @[TLB.scala:170:77]
wire _entries_T_165; // @[TLB.scala:170:77]
wire _entries_T_164; // @[TLB.scala:170:77]
wire _entries_T_163; // @[TLB.scala:170:77]
wire _entries_T_162; // @[TLB.scala:170:77]
wire _entries_T_161; // @[TLB.scala:170:77]
wire _entries_T_160; // @[TLB.scala:170:77]
wire _entries_T_159; // @[TLB.scala:170:77]
wire _entries_T_158; // @[TLB.scala:170:77]
wire _entries_T_157; // @[TLB.scala:170:77]
wire _entries_T_156; // @[TLB.scala:170:77]
wire _entries_T_155; // @[TLB.scala:170:77]
wire _entries_T_154; // @[TLB.scala:170:77]
wire _entries_T_153; // @[TLB.scala:170:77]
wire _entries_T_152; // @[TLB.scala:170:77]
wire _entries_T_151; // @[TLB.scala:170:77]
wire _entries_T_150; // @[TLB.scala:170:77]
wire _entries_T_149; // @[TLB.scala:170:77]
wire _entries_T_148; // @[TLB.scala:170:77]
wire _entries_T_147; // @[TLB.scala:170:77]
wire _entries_T_146; // @[TLB.scala:170:77]
wire _entries_T_145; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_38 = {{sectored_entries_0_6_data_3}, {sectored_entries_0_6_data_2}, {sectored_entries_0_6_data_1}, {sectored_entries_0_6_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_13 = _GEN_38[_entries_T_144]; // @[package.scala:163:13]
assign _entries_T_145 = _entries_WIRE_13[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_fragmented_superpage = _entries_T_145; // @[TLB.scala:170:77]
assign _entries_T_146 = _entries_WIRE_13[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_c = _entries_T_146; // @[TLB.scala:170:77]
assign _entries_T_147 = _entries_WIRE_13[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_eff = _entries_T_147; // @[TLB.scala:170:77]
assign _entries_T_148 = _entries_WIRE_13[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_paa = _entries_T_148; // @[TLB.scala:170:77]
assign _entries_T_149 = _entries_WIRE_13[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pal = _entries_T_149; // @[TLB.scala:170:77]
assign _entries_T_150 = _entries_WIRE_13[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ppp = _entries_T_150; // @[TLB.scala:170:77]
assign _entries_T_151 = _entries_WIRE_13[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pr = _entries_T_151; // @[TLB.scala:170:77]
assign _entries_T_152 = _entries_WIRE_13[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_px = _entries_T_152; // @[TLB.scala:170:77]
assign _entries_T_153 = _entries_WIRE_13[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pw = _entries_T_153; // @[TLB.scala:170:77]
assign _entries_T_154 = _entries_WIRE_13[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hr = _entries_T_154; // @[TLB.scala:170:77]
assign _entries_T_155 = _entries_WIRE_13[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hx = _entries_T_155; // @[TLB.scala:170:77]
assign _entries_T_156 = _entries_WIRE_13[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hw = _entries_T_156; // @[TLB.scala:170:77]
assign _entries_T_157 = _entries_WIRE_13[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sr = _entries_T_157; // @[TLB.scala:170:77]
assign _entries_T_158 = _entries_WIRE_13[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sx = _entries_T_158; // @[TLB.scala:170:77]
assign _entries_T_159 = _entries_WIRE_13[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sw = _entries_T_159; // @[TLB.scala:170:77]
assign _entries_T_160 = _entries_WIRE_13[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_gf = _entries_T_160; // @[TLB.scala:170:77]
assign _entries_T_161 = _entries_WIRE_13[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pf = _entries_T_161; // @[TLB.scala:170:77]
assign _entries_T_162 = _entries_WIRE_13[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_stage2 = _entries_T_162; // @[TLB.scala:170:77]
assign _entries_T_163 = _entries_WIRE_13[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_final = _entries_T_163; // @[TLB.scala:170:77]
assign _entries_T_164 = _entries_WIRE_13[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_ptw = _entries_T_164; // @[TLB.scala:170:77]
assign _entries_T_165 = _entries_WIRE_13[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_g = _entries_T_165; // @[TLB.scala:170:77]
assign _entries_T_166 = _entries_WIRE_13[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_u = _entries_T_166; // @[TLB.scala:170:77]
assign _entries_T_167 = _entries_WIRE_13[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_12_ppn = _entries_T_167; // @[TLB.scala:170:77]
wire [19:0] _entries_T_191; // @[TLB.scala:170:77]
wire _entries_T_190; // @[TLB.scala:170:77]
wire _entries_T_189; // @[TLB.scala:170:77]
wire _entries_T_188; // @[TLB.scala:170:77]
wire _entries_T_187; // @[TLB.scala:170:77]
wire _entries_T_186; // @[TLB.scala:170:77]
wire _entries_T_185; // @[TLB.scala:170:77]
wire _entries_T_184; // @[TLB.scala:170:77]
wire _entries_T_183; // @[TLB.scala:170:77]
wire _entries_T_182; // @[TLB.scala:170:77]
wire _entries_T_181; // @[TLB.scala:170:77]
wire _entries_T_180; // @[TLB.scala:170:77]
wire _entries_T_179; // @[TLB.scala:170:77]
wire _entries_T_178; // @[TLB.scala:170:77]
wire _entries_T_177; // @[TLB.scala:170:77]
wire _entries_T_176; // @[TLB.scala:170:77]
wire _entries_T_175; // @[TLB.scala:170:77]
wire _entries_T_174; // @[TLB.scala:170:77]
wire _entries_T_173; // @[TLB.scala:170:77]
wire _entries_T_172; // @[TLB.scala:170:77]
wire _entries_T_171; // @[TLB.scala:170:77]
wire _entries_T_170; // @[TLB.scala:170:77]
wire _entries_T_169; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_39 = {{sectored_entries_0_7_data_3}, {sectored_entries_0_7_data_2}, {sectored_entries_0_7_data_1}, {sectored_entries_0_7_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_15 = _GEN_39[_entries_T_168]; // @[package.scala:163:13]
assign _entries_T_169 = _entries_WIRE_15[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_fragmented_superpage = _entries_T_169; // @[TLB.scala:170:77]
assign _entries_T_170 = _entries_WIRE_15[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_c = _entries_T_170; // @[TLB.scala:170:77]
assign _entries_T_171 = _entries_WIRE_15[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_eff = _entries_T_171; // @[TLB.scala:170:77]
assign _entries_T_172 = _entries_WIRE_15[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_paa = _entries_T_172; // @[TLB.scala:170:77]
assign _entries_T_173 = _entries_WIRE_15[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pal = _entries_T_173; // @[TLB.scala:170:77]
assign _entries_T_174 = _entries_WIRE_15[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ppp = _entries_T_174; // @[TLB.scala:170:77]
assign _entries_T_175 = _entries_WIRE_15[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pr = _entries_T_175; // @[TLB.scala:170:77]
assign _entries_T_176 = _entries_WIRE_15[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_px = _entries_T_176; // @[TLB.scala:170:77]
assign _entries_T_177 = _entries_WIRE_15[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pw = _entries_T_177; // @[TLB.scala:170:77]
assign _entries_T_178 = _entries_WIRE_15[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hr = _entries_T_178; // @[TLB.scala:170:77]
assign _entries_T_179 = _entries_WIRE_15[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hx = _entries_T_179; // @[TLB.scala:170:77]
assign _entries_T_180 = _entries_WIRE_15[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hw = _entries_T_180; // @[TLB.scala:170:77]
assign _entries_T_181 = _entries_WIRE_15[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sr = _entries_T_181; // @[TLB.scala:170:77]
assign _entries_T_182 = _entries_WIRE_15[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sx = _entries_T_182; // @[TLB.scala:170:77]
assign _entries_T_183 = _entries_WIRE_15[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sw = _entries_T_183; // @[TLB.scala:170:77]
assign _entries_T_184 = _entries_WIRE_15[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_gf = _entries_T_184; // @[TLB.scala:170:77]
assign _entries_T_185 = _entries_WIRE_15[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pf = _entries_T_185; // @[TLB.scala:170:77]
assign _entries_T_186 = _entries_WIRE_15[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_stage2 = _entries_T_186; // @[TLB.scala:170:77]
assign _entries_T_187 = _entries_WIRE_15[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_final = _entries_T_187; // @[TLB.scala:170:77]
assign _entries_T_188 = _entries_WIRE_15[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_ptw = _entries_T_188; // @[TLB.scala:170:77]
assign _entries_T_189 = _entries_WIRE_15[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_g = _entries_T_189; // @[TLB.scala:170:77]
assign _entries_T_190 = _entries_WIRE_15[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_u = _entries_T_190; // @[TLB.scala:170:77]
assign _entries_T_191 = _entries_WIRE_15[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_14_ppn = _entries_T_191; // @[TLB.scala:170:77]
wire [19:0] _entries_T_214; // @[TLB.scala:170:77]
wire _entries_T_213; // @[TLB.scala:170:77]
wire _entries_T_212; // @[TLB.scala:170:77]
wire _entries_T_211; // @[TLB.scala:170:77]
wire _entries_T_210; // @[TLB.scala:170:77]
wire _entries_T_209; // @[TLB.scala:170:77]
wire _entries_T_208; // @[TLB.scala:170:77]
wire _entries_T_207; // @[TLB.scala:170:77]
wire _entries_T_206; // @[TLB.scala:170:77]
wire _entries_T_205; // @[TLB.scala:170:77]
wire _entries_T_204; // @[TLB.scala:170:77]
wire _entries_T_203; // @[TLB.scala:170:77]
wire _entries_T_202; // @[TLB.scala:170:77]
wire _entries_T_201; // @[TLB.scala:170:77]
wire _entries_T_200; // @[TLB.scala:170:77]
wire _entries_T_199; // @[TLB.scala:170:77]
wire _entries_T_198; // @[TLB.scala:170:77]
wire _entries_T_197; // @[TLB.scala:170:77]
wire _entries_T_196; // @[TLB.scala:170:77]
wire _entries_T_195; // @[TLB.scala:170:77]
wire _entries_T_194; // @[TLB.scala:170:77]
wire _entries_T_193; // @[TLB.scala:170:77]
wire _entries_T_192; // @[TLB.scala:170:77]
assign _entries_T_192 = _entries_WIRE_17[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_fragmented_superpage = _entries_T_192; // @[TLB.scala:170:77]
assign _entries_T_193 = _entries_WIRE_17[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_c = _entries_T_193; // @[TLB.scala:170:77]
assign _entries_T_194 = _entries_WIRE_17[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_eff = _entries_T_194; // @[TLB.scala:170:77]
assign _entries_T_195 = _entries_WIRE_17[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_paa = _entries_T_195; // @[TLB.scala:170:77]
assign _entries_T_196 = _entries_WIRE_17[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pal = _entries_T_196; // @[TLB.scala:170:77]
assign _entries_T_197 = _entries_WIRE_17[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ppp = _entries_T_197; // @[TLB.scala:170:77]
assign _entries_T_198 = _entries_WIRE_17[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pr = _entries_T_198; // @[TLB.scala:170:77]
assign _entries_T_199 = _entries_WIRE_17[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_px = _entries_T_199; // @[TLB.scala:170:77]
assign _entries_T_200 = _entries_WIRE_17[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pw = _entries_T_200; // @[TLB.scala:170:77]
assign _entries_T_201 = _entries_WIRE_17[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hr = _entries_T_201; // @[TLB.scala:170:77]
assign _entries_T_202 = _entries_WIRE_17[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hx = _entries_T_202; // @[TLB.scala:170:77]
assign _entries_T_203 = _entries_WIRE_17[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hw = _entries_T_203; // @[TLB.scala:170:77]
assign _entries_T_204 = _entries_WIRE_17[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sr = _entries_T_204; // @[TLB.scala:170:77]
assign _entries_T_205 = _entries_WIRE_17[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sx = _entries_T_205; // @[TLB.scala:170:77]
assign _entries_T_206 = _entries_WIRE_17[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sw = _entries_T_206; // @[TLB.scala:170:77]
assign _entries_T_207 = _entries_WIRE_17[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_gf = _entries_T_207; // @[TLB.scala:170:77]
assign _entries_T_208 = _entries_WIRE_17[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pf = _entries_T_208; // @[TLB.scala:170:77]
assign _entries_T_209 = _entries_WIRE_17[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_stage2 = _entries_T_209; // @[TLB.scala:170:77]
assign _entries_T_210 = _entries_WIRE_17[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_final = _entries_T_210; // @[TLB.scala:170:77]
assign _entries_T_211 = _entries_WIRE_17[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_ptw = _entries_T_211; // @[TLB.scala:170:77]
assign _entries_T_212 = _entries_WIRE_17[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_g = _entries_T_212; // @[TLB.scala:170:77]
assign _entries_T_213 = _entries_WIRE_17[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_u = _entries_T_213; // @[TLB.scala:170:77]
assign _entries_T_214 = _entries_WIRE_17[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_16_ppn = _entries_T_214; // @[TLB.scala:170:77]
wire [19:0] _entries_T_237; // @[TLB.scala:170:77]
wire _entries_T_236; // @[TLB.scala:170:77]
wire _entries_T_235; // @[TLB.scala:170:77]
wire _entries_T_234; // @[TLB.scala:170:77]
wire _entries_T_233; // @[TLB.scala:170:77]
wire _entries_T_232; // @[TLB.scala:170:77]
wire _entries_T_231; // @[TLB.scala:170:77]
wire _entries_T_230; // @[TLB.scala:170:77]
wire _entries_T_229; // @[TLB.scala:170:77]
wire _entries_T_228; // @[TLB.scala:170:77]
wire _entries_T_227; // @[TLB.scala:170:77]
wire _entries_T_226; // @[TLB.scala:170:77]
wire _entries_T_225; // @[TLB.scala:170:77]
wire _entries_T_224; // @[TLB.scala:170:77]
wire _entries_T_223; // @[TLB.scala:170:77]
wire _entries_T_222; // @[TLB.scala:170:77]
wire _entries_T_221; // @[TLB.scala:170:77]
wire _entries_T_220; // @[TLB.scala:170:77]
wire _entries_T_219; // @[TLB.scala:170:77]
wire _entries_T_218; // @[TLB.scala:170:77]
wire _entries_T_217; // @[TLB.scala:170:77]
wire _entries_T_216; // @[TLB.scala:170:77]
wire _entries_T_215; // @[TLB.scala:170:77]
assign _entries_T_215 = _entries_WIRE_19[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_fragmented_superpage = _entries_T_215; // @[TLB.scala:170:77]
assign _entries_T_216 = _entries_WIRE_19[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_c = _entries_T_216; // @[TLB.scala:170:77]
assign _entries_T_217 = _entries_WIRE_19[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_eff = _entries_T_217; // @[TLB.scala:170:77]
assign _entries_T_218 = _entries_WIRE_19[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_paa = _entries_T_218; // @[TLB.scala:170:77]
assign _entries_T_219 = _entries_WIRE_19[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pal = _entries_T_219; // @[TLB.scala:170:77]
assign _entries_T_220 = _entries_WIRE_19[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ppp = _entries_T_220; // @[TLB.scala:170:77]
assign _entries_T_221 = _entries_WIRE_19[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pr = _entries_T_221; // @[TLB.scala:170:77]
assign _entries_T_222 = _entries_WIRE_19[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_px = _entries_T_222; // @[TLB.scala:170:77]
assign _entries_T_223 = _entries_WIRE_19[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pw = _entries_T_223; // @[TLB.scala:170:77]
assign _entries_T_224 = _entries_WIRE_19[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hr = _entries_T_224; // @[TLB.scala:170:77]
assign _entries_T_225 = _entries_WIRE_19[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hx = _entries_T_225; // @[TLB.scala:170:77]
assign _entries_T_226 = _entries_WIRE_19[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hw = _entries_T_226; // @[TLB.scala:170:77]
assign _entries_T_227 = _entries_WIRE_19[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sr = _entries_T_227; // @[TLB.scala:170:77]
assign _entries_T_228 = _entries_WIRE_19[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sx = _entries_T_228; // @[TLB.scala:170:77]
assign _entries_T_229 = _entries_WIRE_19[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sw = _entries_T_229; // @[TLB.scala:170:77]
assign _entries_T_230 = _entries_WIRE_19[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_gf = _entries_T_230; // @[TLB.scala:170:77]
assign _entries_T_231 = _entries_WIRE_19[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pf = _entries_T_231; // @[TLB.scala:170:77]
assign _entries_T_232 = _entries_WIRE_19[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_stage2 = _entries_T_232; // @[TLB.scala:170:77]
assign _entries_T_233 = _entries_WIRE_19[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_final = _entries_T_233; // @[TLB.scala:170:77]
assign _entries_T_234 = _entries_WIRE_19[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_ptw = _entries_T_234; // @[TLB.scala:170:77]
assign _entries_T_235 = _entries_WIRE_19[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_g = _entries_T_235; // @[TLB.scala:170:77]
assign _entries_T_236 = _entries_WIRE_19[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_u = _entries_T_236; // @[TLB.scala:170:77]
assign _entries_T_237 = _entries_WIRE_19[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_18_ppn = _entries_T_237; // @[TLB.scala:170:77]
wire [19:0] _entries_T_260; // @[TLB.scala:170:77]
wire _entries_T_259; // @[TLB.scala:170:77]
wire _entries_T_258; // @[TLB.scala:170:77]
wire _entries_T_257; // @[TLB.scala:170:77]
wire _entries_T_256; // @[TLB.scala:170:77]
wire _entries_T_255; // @[TLB.scala:170:77]
wire _entries_T_254; // @[TLB.scala:170:77]
wire _entries_T_253; // @[TLB.scala:170:77]
wire _entries_T_252; // @[TLB.scala:170:77]
wire _entries_T_251; // @[TLB.scala:170:77]
wire _entries_T_250; // @[TLB.scala:170:77]
wire _entries_T_249; // @[TLB.scala:170:77]
wire _entries_T_248; // @[TLB.scala:170:77]
wire _entries_T_247; // @[TLB.scala:170:77]
wire _entries_T_246; // @[TLB.scala:170:77]
wire _entries_T_245; // @[TLB.scala:170:77]
wire _entries_T_244; // @[TLB.scala:170:77]
wire _entries_T_243; // @[TLB.scala:170:77]
wire _entries_T_242; // @[TLB.scala:170:77]
wire _entries_T_241; // @[TLB.scala:170:77]
wire _entries_T_240; // @[TLB.scala:170:77]
wire _entries_T_239; // @[TLB.scala:170:77]
wire _entries_T_238; // @[TLB.scala:170:77]
assign _entries_T_238 = _entries_WIRE_21[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_fragmented_superpage = _entries_T_238; // @[TLB.scala:170:77]
assign _entries_T_239 = _entries_WIRE_21[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_c = _entries_T_239; // @[TLB.scala:170:77]
assign _entries_T_240 = _entries_WIRE_21[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_eff = _entries_T_240; // @[TLB.scala:170:77]
assign _entries_T_241 = _entries_WIRE_21[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_paa = _entries_T_241; // @[TLB.scala:170:77]
assign _entries_T_242 = _entries_WIRE_21[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pal = _entries_T_242; // @[TLB.scala:170:77]
assign _entries_T_243 = _entries_WIRE_21[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ppp = _entries_T_243; // @[TLB.scala:170:77]
assign _entries_T_244 = _entries_WIRE_21[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pr = _entries_T_244; // @[TLB.scala:170:77]
assign _entries_T_245 = _entries_WIRE_21[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_px = _entries_T_245; // @[TLB.scala:170:77]
assign _entries_T_246 = _entries_WIRE_21[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pw = _entries_T_246; // @[TLB.scala:170:77]
assign _entries_T_247 = _entries_WIRE_21[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hr = _entries_T_247; // @[TLB.scala:170:77]
assign _entries_T_248 = _entries_WIRE_21[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hx = _entries_T_248; // @[TLB.scala:170:77]
assign _entries_T_249 = _entries_WIRE_21[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hw = _entries_T_249; // @[TLB.scala:170:77]
assign _entries_T_250 = _entries_WIRE_21[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sr = _entries_T_250; // @[TLB.scala:170:77]
assign _entries_T_251 = _entries_WIRE_21[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sx = _entries_T_251; // @[TLB.scala:170:77]
assign _entries_T_252 = _entries_WIRE_21[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sw = _entries_T_252; // @[TLB.scala:170:77]
assign _entries_T_253 = _entries_WIRE_21[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_gf = _entries_T_253; // @[TLB.scala:170:77]
assign _entries_T_254 = _entries_WIRE_21[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pf = _entries_T_254; // @[TLB.scala:170:77]
assign _entries_T_255 = _entries_WIRE_21[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_stage2 = _entries_T_255; // @[TLB.scala:170:77]
assign _entries_T_256 = _entries_WIRE_21[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_final = _entries_T_256; // @[TLB.scala:170:77]
assign _entries_T_257 = _entries_WIRE_21[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_ptw = _entries_T_257; // @[TLB.scala:170:77]
assign _entries_T_258 = _entries_WIRE_21[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_g = _entries_T_258; // @[TLB.scala:170:77]
assign _entries_T_259 = _entries_WIRE_21[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_u = _entries_T_259; // @[TLB.scala:170:77]
assign _entries_T_260 = _entries_WIRE_21[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_20_ppn = _entries_T_260; // @[TLB.scala:170:77]
wire [19:0] _entries_T_283; // @[TLB.scala:170:77]
wire _entries_T_282; // @[TLB.scala:170:77]
wire _entries_T_281; // @[TLB.scala:170:77]
wire _entries_T_280; // @[TLB.scala:170:77]
wire _entries_T_279; // @[TLB.scala:170:77]
wire _entries_T_278; // @[TLB.scala:170:77]
wire _entries_T_277; // @[TLB.scala:170:77]
wire _entries_T_276; // @[TLB.scala:170:77]
wire _entries_T_275; // @[TLB.scala:170:77]
wire _entries_T_274; // @[TLB.scala:170:77]
wire _entries_T_273; // @[TLB.scala:170:77]
wire _entries_T_272; // @[TLB.scala:170:77]
wire _entries_T_271; // @[TLB.scala:170:77]
wire _entries_T_270; // @[TLB.scala:170:77]
wire _entries_T_269; // @[TLB.scala:170:77]
wire _entries_T_268; // @[TLB.scala:170:77]
wire _entries_T_267; // @[TLB.scala:170:77]
wire _entries_T_266; // @[TLB.scala:170:77]
wire _entries_T_265; // @[TLB.scala:170:77]
wire _entries_T_264; // @[TLB.scala:170:77]
wire _entries_T_263; // @[TLB.scala:170:77]
wire _entries_T_262; // @[TLB.scala:170:77]
wire _entries_T_261; // @[TLB.scala:170:77]
assign _entries_T_261 = _entries_WIRE_23[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_fragmented_superpage = _entries_T_261; // @[TLB.scala:170:77]
assign _entries_T_262 = _entries_WIRE_23[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_c = _entries_T_262; // @[TLB.scala:170:77]
assign _entries_T_263 = _entries_WIRE_23[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_eff = _entries_T_263; // @[TLB.scala:170:77]
assign _entries_T_264 = _entries_WIRE_23[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_paa = _entries_T_264; // @[TLB.scala:170:77]
assign _entries_T_265 = _entries_WIRE_23[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pal = _entries_T_265; // @[TLB.scala:170:77]
assign _entries_T_266 = _entries_WIRE_23[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ppp = _entries_T_266; // @[TLB.scala:170:77]
assign _entries_T_267 = _entries_WIRE_23[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pr = _entries_T_267; // @[TLB.scala:170:77]
assign _entries_T_268 = _entries_WIRE_23[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_px = _entries_T_268; // @[TLB.scala:170:77]
assign _entries_T_269 = _entries_WIRE_23[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pw = _entries_T_269; // @[TLB.scala:170:77]
assign _entries_T_270 = _entries_WIRE_23[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hr = _entries_T_270; // @[TLB.scala:170:77]
assign _entries_T_271 = _entries_WIRE_23[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hx = _entries_T_271; // @[TLB.scala:170:77]
assign _entries_T_272 = _entries_WIRE_23[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hw = _entries_T_272; // @[TLB.scala:170:77]
assign _entries_T_273 = _entries_WIRE_23[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sr = _entries_T_273; // @[TLB.scala:170:77]
assign _entries_T_274 = _entries_WIRE_23[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sx = _entries_T_274; // @[TLB.scala:170:77]
assign _entries_T_275 = _entries_WIRE_23[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sw = _entries_T_275; // @[TLB.scala:170:77]
assign _entries_T_276 = _entries_WIRE_23[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_gf = _entries_T_276; // @[TLB.scala:170:77]
assign _entries_T_277 = _entries_WIRE_23[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pf = _entries_T_277; // @[TLB.scala:170:77]
assign _entries_T_278 = _entries_WIRE_23[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_stage2 = _entries_T_278; // @[TLB.scala:170:77]
assign _entries_T_279 = _entries_WIRE_23[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_final = _entries_T_279; // @[TLB.scala:170:77]
assign _entries_T_280 = _entries_WIRE_23[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_ptw = _entries_T_280; // @[TLB.scala:170:77]
assign _entries_T_281 = _entries_WIRE_23[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_g = _entries_T_281; // @[TLB.scala:170:77]
assign _entries_T_282 = _entries_WIRE_23[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_u = _entries_T_282; // @[TLB.scala:170:77]
assign _entries_T_283 = _entries_WIRE_23[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_22_ppn = _entries_T_283; // @[TLB.scala:170:77]
wire [19:0] _entries_T_306; // @[TLB.scala:170:77]
wire _entries_T_305; // @[TLB.scala:170:77]
wire _entries_T_304; // @[TLB.scala:170:77]
wire _entries_T_303; // @[TLB.scala:170:77]
wire _entries_T_302; // @[TLB.scala:170:77]
wire _entries_T_301; // @[TLB.scala:170:77]
wire _entries_T_300; // @[TLB.scala:170:77]
wire _entries_T_299; // @[TLB.scala:170:77]
wire _entries_T_298; // @[TLB.scala:170:77]
wire _entries_T_297; // @[TLB.scala:170:77]
wire _entries_T_296; // @[TLB.scala:170:77]
wire _entries_T_295; // @[TLB.scala:170:77]
wire _entries_T_294; // @[TLB.scala:170:77]
wire _entries_T_293; // @[TLB.scala:170:77]
wire _entries_T_292; // @[TLB.scala:170:77]
wire _entries_T_291; // @[TLB.scala:170:77]
wire _entries_T_290; // @[TLB.scala:170:77]
wire _entries_T_289; // @[TLB.scala:170:77]
wire _entries_T_288; // @[TLB.scala:170:77]
wire _entries_T_287; // @[TLB.scala:170:77]
wire _entries_T_286; // @[TLB.scala:170:77]
wire _entries_T_285; // @[TLB.scala:170:77]
wire _entries_T_284; // @[TLB.scala:170:77]
assign _entries_T_284 = _entries_WIRE_25[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_fragmented_superpage = _entries_T_284; // @[TLB.scala:170:77]
assign _entries_T_285 = _entries_WIRE_25[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_c = _entries_T_285; // @[TLB.scala:170:77]
assign _entries_T_286 = _entries_WIRE_25[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_eff = _entries_T_286; // @[TLB.scala:170:77]
assign _entries_T_287 = _entries_WIRE_25[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_paa = _entries_T_287; // @[TLB.scala:170:77]
assign _entries_T_288 = _entries_WIRE_25[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pal = _entries_T_288; // @[TLB.scala:170:77]
assign _entries_T_289 = _entries_WIRE_25[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ppp = _entries_T_289; // @[TLB.scala:170:77]
assign _entries_T_290 = _entries_WIRE_25[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pr = _entries_T_290; // @[TLB.scala:170:77]
assign _entries_T_291 = _entries_WIRE_25[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_px = _entries_T_291; // @[TLB.scala:170:77]
assign _entries_T_292 = _entries_WIRE_25[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pw = _entries_T_292; // @[TLB.scala:170:77]
assign _entries_T_293 = _entries_WIRE_25[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hr = _entries_T_293; // @[TLB.scala:170:77]
assign _entries_T_294 = _entries_WIRE_25[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hx = _entries_T_294; // @[TLB.scala:170:77]
assign _entries_T_295 = _entries_WIRE_25[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hw = _entries_T_295; // @[TLB.scala:170:77]
assign _entries_T_296 = _entries_WIRE_25[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sr = _entries_T_296; // @[TLB.scala:170:77]
assign _entries_T_297 = _entries_WIRE_25[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sx = _entries_T_297; // @[TLB.scala:170:77]
assign _entries_T_298 = _entries_WIRE_25[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sw = _entries_T_298; // @[TLB.scala:170:77]
assign _entries_T_299 = _entries_WIRE_25[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_gf = _entries_T_299; // @[TLB.scala:170:77]
assign _entries_T_300 = _entries_WIRE_25[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pf = _entries_T_300; // @[TLB.scala:170:77]
assign _entries_T_301 = _entries_WIRE_25[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_stage2 = _entries_T_301; // @[TLB.scala:170:77]
assign _entries_T_302 = _entries_WIRE_25[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_final = _entries_T_302; // @[TLB.scala:170:77]
assign _entries_T_303 = _entries_WIRE_25[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_ptw = _entries_T_303; // @[TLB.scala:170:77]
assign _entries_T_304 = _entries_WIRE_25[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_g = _entries_T_304; // @[TLB.scala:170:77]
assign _entries_T_305 = _entries_WIRE_25[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_u = _entries_T_305; // @[TLB.scala:170:77]
assign _entries_T_306 = _entries_WIRE_25[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_24_ppn = _entries_T_306; // @[TLB.scala:170:77]
wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30]
wire [1:0] ppn_res = _entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_1 = _entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_3 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_2 = _entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_4 = _ppn_ignore_T_4; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_17 = ppn_ignore_4 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_18 = {_ppn_T_17[26:20], _ppn_T_17[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_19 = _ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_20 = {ppn_res_2, _ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_5 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_22 = {_ppn_T_21[26:20], _ppn_T_21[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_23 = _ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_24 = {_ppn_T_20, _ppn_T_23}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_3 = _entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_6 = _ppn_ignore_T_6; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_25 = ppn_ignore_6 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_26 = {_ppn_T_25[26:20], _ppn_T_25[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_27 = _ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_28 = {ppn_res_3, _ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_7 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_30 = {_ppn_T_29[26:20], _ppn_T_29[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_31 = _ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_32 = {_ppn_T_28, _ppn_T_31}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_4 = _entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_8 = _ppn_ignore_T_8; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_33 = ppn_ignore_8 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_34 = {_ppn_T_33[26:20], _ppn_T_33[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_35 = _ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_36 = {ppn_res_4, _ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_9 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56]
wire ppn_ignore_9 = _ppn_ignore_T_9; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_37 = ppn_ignore_9 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_38 = {_ppn_T_37[26:20], _ppn_T_37[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_39 = _ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_40 = {_ppn_T_36, _ppn_T_39}; // @[TLB.scala:198:{18,58}]
wire [19:0] _ppn_T_41 = vpn[19:0]; // @[TLB.scala:335:30, :502:125]
wire [19:0] _ppn_T_42 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_43 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_44 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_45 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_46 = hitsVec_4 ? _entries_barrier_4_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_47 = hitsVec_5 ? _entries_barrier_5_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_48 = hitsVec_6 ? _entries_barrier_6_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_49 = hitsVec_7 ? _entries_barrier_7_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_50 = hitsVec_8 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_51 = hitsVec_9 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_52 = hitsVec_10 ? _ppn_T_24 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_53 = hitsVec_11 ? _ppn_T_32 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_54 = hitsVec_12 ? _ppn_T_40 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_55 = _ppn_T ? _ppn_T_41 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_56 = _ppn_T_42 | _ppn_T_43; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_57 = _ppn_T_56 | _ppn_T_44; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_58 = _ppn_T_57 | _ppn_T_45; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_59 = _ppn_T_58 | _ppn_T_46; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_60 = _ppn_T_59 | _ppn_T_47; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_61 = _ppn_T_60 | _ppn_T_48; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_62 = _ppn_T_61 | _ppn_T_49; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_63 = _ppn_T_62 | _ppn_T_50; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_64 = _ppn_T_63 | _ppn_T_51; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_65 = _ppn_T_64 | _ppn_T_52; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_66 = _ppn_T_65 | _ppn_T_53; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_67 = _ppn_T_66 | _ppn_T_54; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_68 = _ppn_T_67 | _ppn_T_55; // @[Mux.scala:30:73]
wire [19:0] ppn = _ppn_T_68; // @[Mux.scala:30:73]
wire [1:0] ptw_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_ptw, _entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_ptw, _entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_ptw, _entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27]
wire [1:0] final_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_lo_lo = {final_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_lo_hi = {final_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [5:0] final_ae_array_lo = {final_ae_array_lo_hi, final_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] final_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_final, _entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_hi_lo = {final_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_final, _entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_final, _entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [3:0] final_ae_array_hi_hi = {final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] final_ae_array_hi = {final_ae_array_hi_hi, final_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27]
wire [1:0] ptw_pf_array_lo_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_lo_lo = {ptw_pf_array_lo_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_lo_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_lo_hi = {ptw_pf_array_lo_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, ptw_pf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_pf_array_hi_lo_hi = {_entries_barrier_8_io_y_pf, _entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_hi_lo = {ptw_pf_array_hi_lo_hi, _entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_hi_hi_lo = {_entries_barrier_10_io_y_pf, _entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_hi_hi_hi = {_entries_barrier_12_io_y_pf, _entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_pf_array_hi_hi = {ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, ptw_pf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27]
wire [1:0] ptw_gf_array_lo_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_lo_lo = {ptw_gf_array_lo_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_lo_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_lo_hi = {ptw_gf_array_lo_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, ptw_gf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_gf_array_hi_lo_hi = {_entries_barrier_8_io_y_gf, _entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_hi_lo = {ptw_gf_array_hi_lo_hi, _entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_hi_hi_lo = {_entries_barrier_10_io_y_gf, _entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_hi_hi_hi = {_entries_barrier_12_io_y_gf, _entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_gf_array_hi_hi = {ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, ptw_gf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27]
wire [13:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82]
wire [13:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63]
wire [13:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46]
wire _priv_rw_ok_T = ~priv_s; // @[TLB.scala:370:20, :513:24]
wire _priv_rw_ok_T_1 = _priv_rw_ok_T | sum; // @[TLB.scala:510:16, :513:{24,32}]
wire [1:0] _GEN_40 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_41 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_42 = {_entries_barrier_8_io_y_u, _entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_43 = {_entries_barrier_10_io_y_u, _entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27]
wire [1:0] _GEN_44 = {_entries_barrier_12_io_y_u, _entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27]
wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_1 ? _priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_6 = priv_s ? _priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}]
wire [12:0] priv_rw_ok = _priv_rw_ok_T_3 | _priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}]
wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27]
wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] priv_x_ok = priv_s ? _priv_x_ok_T_1 : _priv_x_ok_T_2; // @[package.scala:45:27]
wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83]
wire [12:0] _stage1_bypass_T_2 = {13{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}]
wire [1:0] stage1_bypass_lo_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_lo_lo = {stage1_bypass_lo_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_lo_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_lo_hi = {stage1_bypass_lo_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [5:0] stage1_bypass_lo = {stage1_bypass_lo_hi, stage1_bypass_lo_lo}; // @[package.scala:45:27]
wire [1:0] stage1_bypass_hi_lo_hi = {_entries_barrier_8_io_y_ae_stage2, _entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_hi_lo = {stage1_bypass_hi_lo_hi, _entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_hi_hi_lo = {_entries_barrier_10_io_y_ae_stage2, _entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_hi_hi_hi = {_entries_barrier_12_io_y_ae_stage2, _entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [3:0] stage1_bypass_hi_hi = {stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] stage1_bypass_hi = {stage1_bypass_hi_hi, stage1_bypass_hi_lo}; // @[package.scala:45:27]
wire [12:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27]
wire [12:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 | _stage1_bypass_T_3; // @[package.scala:45:27]
wire [1:0] r_array_lo_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] r_array_hi_lo_hi = {_entries_barrier_8_io_y_sr, _entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, _entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_lo = {_entries_barrier_10_io_y_sr, _entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_hi = {_entries_barrier_12_io_y_sr, _entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_45 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27]
assign r_array_lo_lo_hi_1 = _GEN_45; // @[package.scala:45:27]
wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27]
assign x_array_lo_lo_hi = _GEN_45; // @[package.scala:45:27]
wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_46 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27]
assign r_array_lo_hi_hi_1 = _GEN_46; // @[package.scala:45:27]
wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27]
assign x_array_lo_hi_hi = _GEN_46; // @[package.scala:45:27]
wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_47 = {_entries_barrier_8_io_y_sx, _entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27]
assign r_array_hi_lo_hi_1 = _GEN_47; // @[package.scala:45:27]
wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27]
assign x_array_hi_lo_hi = _GEN_47; // @[package.scala:45:27]
wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_48 = {_entries_barrier_10_io_y_sx, _entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27]
assign r_array_hi_hi_lo_1 = _GEN_48; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27]
assign x_array_hi_hi_lo = _GEN_48; // @[package.scala:45:27]
wire [1:0] _GEN_49 = {_entries_barrier_12_io_y_sx, _entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27]
assign r_array_hi_hi_hi_1 = _GEN_49; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27]
assign x_array_hi_hi_hi = _GEN_49; // @[package.scala:45:27]
wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27]
wire [12:0] _r_array_T_2 = mxr ? _r_array_T_1 : 13'h0; // @[package.scala:45:27]
wire [12:0] _r_array_T_3 = _r_array_T | _r_array_T_2; // @[package.scala:45:27]
wire [12:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}]
wire [12:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}]
wire [13:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}]
wire [13:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41]
wire [1:0] w_array_lo_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_lo_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] w_array_hi_lo_hi = {_entries_barrier_8_io_y_sw, _entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, _entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_hi_hi_lo = {_entries_barrier_10_io_y_sw, _entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_hi_hi_hi = {_entries_barrier_12_io_y_sw, _entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27]
wire [12:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27]
wire [12:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}]
wire [13:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}]
wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27]
wire [12:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27]
wire [12:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}]
wire [13:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}]
wire [1:0] hr_array_lo_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_lo_lo = {hr_array_lo_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_lo_hi = {hr_array_lo_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [5:0] hr_array_lo = {hr_array_lo_hi, hr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] hr_array_hi_lo_hi = {_entries_barrier_8_io_y_hr, _entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_hi_lo = {hr_array_hi_lo_hi, _entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_lo = {_entries_barrier_10_io_y_hr, _entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_hi = {_entries_barrier_12_io_y_hr, _entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [3:0] hr_array_hi_hi = {hr_array_hi_hi_hi, hr_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hr_array_hi = {hr_array_hi_hi, hr_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_50 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_lo_hi_1; // @[package.scala:45:27]
assign hr_array_lo_lo_hi_1 = _GEN_50; // @[package.scala:45:27]
wire [1:0] hx_array_lo_lo_hi; // @[package.scala:45:27]
assign hx_array_lo_lo_hi = _GEN_50; // @[package.scala:45:27]
wire [2:0] hr_array_lo_lo_1 = {hr_array_lo_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_51 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_hi_hi_1; // @[package.scala:45:27]
assign hr_array_lo_hi_hi_1 = _GEN_51; // @[package.scala:45:27]
wire [1:0] hx_array_lo_hi_hi; // @[package.scala:45:27]
assign hx_array_lo_hi_hi = _GEN_51; // @[package.scala:45:27]
wire [2:0] hr_array_lo_hi_1 = {hr_array_lo_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] hr_array_lo_1 = {hr_array_lo_hi_1, hr_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_52 = {_entries_barrier_8_io_y_hx, _entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_lo_hi_1; // @[package.scala:45:27]
assign hr_array_hi_lo_hi_1 = _GEN_52; // @[package.scala:45:27]
wire [1:0] hx_array_hi_lo_hi; // @[package.scala:45:27]
assign hx_array_hi_lo_hi = _GEN_52; // @[package.scala:45:27]
wire [2:0] hr_array_hi_lo_1 = {hr_array_hi_lo_hi_1, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_53 = {_entries_barrier_10_io_y_hx, _entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_lo_1; // @[package.scala:45:27]
assign hr_array_hi_hi_lo_1 = _GEN_53; // @[package.scala:45:27]
wire [1:0] hx_array_hi_hi_lo; // @[package.scala:45:27]
assign hx_array_hi_hi_lo = _GEN_53; // @[package.scala:45:27]
wire [1:0] _GEN_54 = {_entries_barrier_12_io_y_hx, _entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_hi_1; // @[package.scala:45:27]
assign hr_array_hi_hi_hi_1 = _GEN_54; // @[package.scala:45:27]
wire [1:0] hx_array_hi_hi_hi; // @[package.scala:45:27]
assign hx_array_hi_hi_hi = _GEN_54; // @[package.scala:45:27]
wire [3:0] hr_array_hi_hi_1 = {hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] hr_array_hi_1 = {hr_array_hi_hi_1, hr_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27]
wire [12:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 13'h0; // @[package.scala:45:27]
wire [12:0] _hr_array_T_3 = _hr_array_T | _hr_array_T_2; // @[package.scala:45:27]
wire [1:0] hw_array_lo_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_lo_lo = {hw_array_lo_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_lo_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_lo_hi = {hw_array_lo_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [5:0] hw_array_lo = {hw_array_lo_hi, hw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] hw_array_hi_lo_hi = {_entries_barrier_8_io_y_hw, _entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_hi_lo = {hw_array_hi_lo_hi, _entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_hi_hi_lo = {_entries_barrier_10_io_y_hw, _entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_hi_hi_hi = {_entries_barrier_12_io_y_hw, _entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [3:0] hw_array_hi_hi = {hw_array_hi_hi_hi, hw_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hw_array_hi = {hw_array_hi_hi, hw_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27]
wire [2:0] hx_array_lo_lo = {hx_array_lo_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [2:0] hx_array_lo_hi = {hx_array_lo_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] hx_array_lo = {hx_array_lo_hi, hx_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] hx_array_hi_lo = {hx_array_hi_lo_hi, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [3:0] hx_array_hi_hi = {hx_array_hi_hi_hi, hx_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hx_array_hi = {hx_array_hi_hi, hx_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27]
wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26]
wire [1:0] pr_array_lo_lo_hi = {_entries_barrier_2_io_y_pr, _entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pr_array_lo_hi_hi = {_entries_barrier_5_io_y_pr, _entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pr_array_hi_lo_hi = {_entries_barrier_8_io_y_pr, _entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, _entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pr_array_hi_hi_hi = {_entries_barrier_11_io_y_pr, _entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, _entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27]
wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27]
wire [13:0] _GEN_55 = ptw_ae_array | final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104]
wire [13:0] _pr_array_T_3; // @[TLB.scala:529:104]
assign _pr_array_T_3 = _GEN_55; // @[TLB.scala:529:104]
wire [13:0] _pw_array_T_3; // @[TLB.scala:531:104]
assign _pw_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :531:104]
wire [13:0] _px_array_T_3; // @[TLB.scala:533:104]
assign _px_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :533:104]
wire [13:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}]
wire [13:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}]
wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26]
wire [1:0] pw_array_lo_lo_hi = {_entries_barrier_2_io_y_pw, _entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pw_array_lo_hi_hi = {_entries_barrier_5_io_y_pw, _entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pw_array_hi_lo_hi = {_entries_barrier_8_io_y_pw, _entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, _entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pw_array_hi_hi_hi = {_entries_barrier_11_io_y_pw, _entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, _entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27]
wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27]
wire [13:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}]
wire [13:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}]
wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26]
wire [1:0] px_array_lo_lo_hi = {_entries_barrier_2_io_y_px, _entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] px_array_lo_hi_hi = {_entries_barrier_5_io_y_px, _entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] px_array_hi_lo_hi = {_entries_barrier_8_io_y_px, _entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, _entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] px_array_hi_hi_hi = {_entries_barrier_11_io_y_px, _entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, _entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27]
wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27]
wire [13:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}]
wire [13:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}]
wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27]
wire [1:0] eff_array_lo_lo_hi = {_entries_barrier_2_io_y_eff, _entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] eff_array_lo_hi_hi = {_entries_barrier_5_io_y_eff, _entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] eff_array_hi_lo_hi = {_entries_barrier_8_io_y_eff, _entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, _entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] eff_array_hi_hi_hi = {_entries_barrier_11_io_y_eff, _entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, _entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27]
wire [13:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27]
wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25]
wire [1:0] _GEN_56 = {_entries_barrier_2_io_y_c, _entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27]
assign c_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27]
assign prefetchable_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27]
wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_57 = {_entries_barrier_5_io_y_c, _entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27]
assign c_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27]
wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_58 = {_entries_barrier_8_io_y_c, _entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27]
assign c_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27]
wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_59 = {_entries_barrier_11_io_y_c, _entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27]
assign c_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27]
wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27]
wire [13:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27]
wire [13:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24]
wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27]
wire [1:0] ppp_array_lo_lo_hi = {_entries_barrier_2_io_y_ppp, _entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_lo_lo = {ppp_array_lo_lo_hi, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] ppp_array_lo_hi_hi = {_entries_barrier_5_io_y_ppp, _entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_lo_hi = {ppp_array_lo_hi_hi, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] ppp_array_lo = {ppp_array_lo_hi, ppp_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ppp_array_hi_lo_hi = {_entries_barrier_8_io_y_ppp, _entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_hi_lo = {ppp_array_hi_lo_hi, _entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] ppp_array_hi_hi_hi = {_entries_barrier_11_io_y_ppp, _entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_hi_hi = {ppp_array_hi_hi_hi, _entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] ppp_array_hi = {ppp_array_hi_hi, ppp_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27]
wire [13:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27]
wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27]
wire [1:0] paa_array_lo_lo_hi = {_entries_barrier_2_io_y_paa, _entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] paa_array_lo_hi_hi = {_entries_barrier_5_io_y_paa, _entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] paa_array_hi_lo_hi = {_entries_barrier_8_io_y_paa, _entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, _entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] paa_array_hi_hi_hi = {_entries_barrier_11_io_y_paa, _entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, _entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27]
wire [13:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27]
wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27]
wire [1:0] pal_array_lo_lo_hi = {_entries_barrier_2_io_y_pal, _entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pal_array_lo_hi_hi = {_entries_barrier_5_io_y_pal, _entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pal_array_hi_lo_hi = {_entries_barrier_8_io_y_pal, _entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, _entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pal_array_hi_hi_hi = {_entries_barrier_11_io_y_pal, _entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, _entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27]
wire [13:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27]
wire [13:0] ppp_array_if_cached = ppp_array | c_array; // @[TLB.scala:537:20, :539:22, :544:39]
wire [13:0] paa_array_if_cached = paa_array | c_array; // @[TLB.scala:537:20, :541:22, :545:39]
wire [13:0] pal_array_if_cached = pal_array | c_array; // @[TLB.scala:537:20, :543:22, :546:39]
wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65]
wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}]
wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27]
wire [13:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27]
wire [3:0] _misaligned_T = 4'h1 << io_req_bits_size_0; // @[OneHot.scala:58:35]
wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35]
wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[TLB.scala:550:69]
wire [39:0] _misaligned_T_3 = {36'h0, io_req_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[TLB.scala:318:7, :550:{39,69}]
wire misaligned = |_misaligned_T_3; // @[TLB.scala:550:{39,77}]
wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21]
wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43]
wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51]
wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86]
wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}]
wire _bad_va_T_5 = _bad_va_T_2 | _bad_va_T_4; // @[TLB.scala:560:{51,59,71}]
wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}]
wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}]
wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}]
wire _GEN_60 = io_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47]
wire _cmd_lrsc_T; // @[package.scala:16:47]
assign _cmd_lrsc_T = _GEN_60; // @[package.scala:16:47]
wire _cmd_read_T_2; // @[package.scala:16:47]
assign _cmd_read_T_2 = _GEN_60; // @[package.scala:16:47]
wire _GEN_61 = io_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47]
wire _cmd_lrsc_T_1; // @[package.scala:16:47]
assign _cmd_lrsc_T_1 = _GEN_61; // @[package.scala:16:47]
wire _cmd_read_T_3; // @[package.scala:16:47]
assign _cmd_read_T_3 = _GEN_61; // @[package.scala:16:47]
wire _cmd_write_T_3; // @[Consts.scala:90:66]
assign _cmd_write_T_3 = _GEN_61; // @[package.scala:16:47]
wire _cmd_lrsc_T_2 = _cmd_lrsc_T | _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59]
wire cmd_lrsc = _cmd_lrsc_T_2; // @[package.scala:81:59]
wire _GEN_62 = io_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _cmd_amo_logical_T; // @[package.scala:16:47]
assign _cmd_amo_logical_T = _GEN_62; // @[package.scala:16:47]
wire _cmd_read_T_7; // @[package.scala:16:47]
assign _cmd_read_T_7 = _GEN_62; // @[package.scala:16:47]
wire _cmd_write_T_5; // @[package.scala:16:47]
assign _cmd_write_T_5 = _GEN_62; // @[package.scala:16:47]
wire _GEN_63 = io_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _cmd_amo_logical_T_1; // @[package.scala:16:47]
assign _cmd_amo_logical_T_1 = _GEN_63; // @[package.scala:16:47]
wire _cmd_read_T_8; // @[package.scala:16:47]
assign _cmd_read_T_8 = _GEN_63; // @[package.scala:16:47]
wire _cmd_write_T_6; // @[package.scala:16:47]
assign _cmd_write_T_6 = _GEN_63; // @[package.scala:16:47]
wire _GEN_64 = io_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _cmd_amo_logical_T_2; // @[package.scala:16:47]
assign _cmd_amo_logical_T_2 = _GEN_64; // @[package.scala:16:47]
wire _cmd_read_T_9; // @[package.scala:16:47]
assign _cmd_read_T_9 = _GEN_64; // @[package.scala:16:47]
wire _cmd_write_T_7; // @[package.scala:16:47]
assign _cmd_write_T_7 = _GEN_64; // @[package.scala:16:47]
wire _GEN_65 = io_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _cmd_amo_logical_T_3; // @[package.scala:16:47]
assign _cmd_amo_logical_T_3 = _GEN_65; // @[package.scala:16:47]
wire _cmd_read_T_10; // @[package.scala:16:47]
assign _cmd_read_T_10 = _GEN_65; // @[package.scala:16:47]
wire _cmd_write_T_8; // @[package.scala:16:47]
assign _cmd_write_T_8 = _GEN_65; // @[package.scala:16:47]
wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T | _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 | _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 | _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59]
wire cmd_amo_logical = _cmd_amo_logical_T_6; // @[package.scala:81:59]
wire _GEN_66 = io_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T = _GEN_66; // @[package.scala:16:47]
wire _cmd_read_T_14; // @[package.scala:16:47]
assign _cmd_read_T_14 = _GEN_66; // @[package.scala:16:47]
wire _cmd_write_T_12; // @[package.scala:16:47]
assign _cmd_write_T_12 = _GEN_66; // @[package.scala:16:47]
wire _GEN_67 = io_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_1 = _GEN_67; // @[package.scala:16:47]
wire _cmd_read_T_15; // @[package.scala:16:47]
assign _cmd_read_T_15 = _GEN_67; // @[package.scala:16:47]
wire _cmd_write_T_13; // @[package.scala:16:47]
assign _cmd_write_T_13 = _GEN_67; // @[package.scala:16:47]
wire _GEN_68 = io_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_2 = _GEN_68; // @[package.scala:16:47]
wire _cmd_read_T_16; // @[package.scala:16:47]
assign _cmd_read_T_16 = _GEN_68; // @[package.scala:16:47]
wire _cmd_write_T_14; // @[package.scala:16:47]
assign _cmd_write_T_14 = _GEN_68; // @[package.scala:16:47]
wire _GEN_69 = io_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_3 = _GEN_69; // @[package.scala:16:47]
wire _cmd_read_T_17; // @[package.scala:16:47]
assign _cmd_read_T_17 = _GEN_69; // @[package.scala:16:47]
wire _cmd_write_T_15; // @[package.scala:16:47]
assign _cmd_write_T_15 = _GEN_69; // @[package.scala:16:47]
wire _GEN_70 = io_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_4 = _GEN_70; // @[package.scala:16:47]
wire _cmd_read_T_18; // @[package.scala:16:47]
assign _cmd_read_T_18 = _GEN_70; // @[package.scala:16:47]
wire _cmd_write_T_16; // @[package.scala:16:47]
assign _cmd_write_T_16 = _GEN_70; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T | _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 | _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 | _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 | _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59]
wire cmd_amo_arithmetic = _cmd_amo_arithmetic_T_8; // @[package.scala:81:59]
wire _GEN_71 = io_req_bits_cmd_0 == 5'h11; // @[TLB.scala:318:7, :573:41]
wire cmd_put_partial; // @[TLB.scala:573:41]
assign cmd_put_partial = _GEN_71; // @[TLB.scala:573:41]
wire _cmd_write_T_1; // @[Consts.scala:90:49]
assign _cmd_write_T_1 = _GEN_71; // @[TLB.scala:573:41]
wire _cmd_read_T = io_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47]
wire _GEN_72 = io_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47]
wire _cmd_read_T_1; // @[package.scala:16:47]
assign _cmd_read_T_1 = _GEN_72; // @[package.scala:16:47]
wire _cmd_readx_T; // @[TLB.scala:575:56]
assign _cmd_readx_T = _GEN_72; // @[package.scala:16:47]
wire _cmd_read_T_4 = _cmd_read_T | _cmd_read_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_5 = _cmd_read_T_4 | _cmd_read_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_6 = _cmd_read_T_5 | _cmd_read_T_3; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_11 = _cmd_read_T_7 | _cmd_read_T_8; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_12 = _cmd_read_T_11 | _cmd_read_T_9; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_13 = _cmd_read_T_12 | _cmd_read_T_10; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_19 = _cmd_read_T_14 | _cmd_read_T_15; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_20 = _cmd_read_T_19 | _cmd_read_T_16; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_21 = _cmd_read_T_20 | _cmd_read_T_17; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_22 = _cmd_read_T_21 | _cmd_read_T_18; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_23 = _cmd_read_T_13 | _cmd_read_T_22; // @[package.scala:81:59]
wire cmd_read = _cmd_read_T_6 | _cmd_read_T_23; // @[package.scala:81:59]
wire _cmd_write_T = io_req_bits_cmd_0 == 5'h1; // @[TLB.scala:318:7]
wire _cmd_write_T_2 = _cmd_write_T | _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}]
wire _cmd_write_T_4 = _cmd_write_T_2 | _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}]
wire _cmd_write_T_9 = _cmd_write_T_5 | _cmd_write_T_6; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_10 = _cmd_write_T_9 | _cmd_write_T_7; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_11 = _cmd_write_T_10 | _cmd_write_T_8; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_17 = _cmd_write_T_12 | _cmd_write_T_13; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_18 = _cmd_write_T_17 | _cmd_write_T_14; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_19 = _cmd_write_T_18 | _cmd_write_T_15; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_20 = _cmd_write_T_19 | _cmd_write_T_16; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_21 = _cmd_write_T_11 | _cmd_write_T_20; // @[package.scala:81:59]
wire cmd_write = _cmd_write_T_4 | _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _cmd_write_perms_T = io_req_bits_cmd_0 == 5'h5; // @[package.scala:16:47]
wire _cmd_write_perms_T_1 = io_req_bits_cmd_0 == 5'h17; // @[package.scala:16:47]
wire _cmd_write_perms_T_2 = _cmd_write_perms_T | _cmd_write_perms_T_1; // @[package.scala:16:47, :81:59]
wire cmd_write_perms = cmd_write | _cmd_write_perms_T_2; // @[package.scala:81:59]
wire [13:0] _ae_array_T = misaligned ? eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8]
wire [13:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19]
wire [13:0] _ae_array_T_2 = cmd_lrsc ? _ae_array_T_1 : 14'h0; // @[TLB.scala:570:33, :583:{8,19}]
wire [13:0] ae_array = _ae_array_T | _ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8]
wire [13:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46]
wire [13:0] _ae_ld_array_T_1 = ae_array | _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}]
wire [13:0] ae_ld_array = cmd_read ? _ae_ld_array_T_1 : 14'h0; // @[TLB.scala:586:{24,44}]
wire [13:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37]
wire [13:0] _ae_st_array_T_1 = ae_array | _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}]
wire [13:0] _ae_st_array_T_2 = cmd_write_perms ? _ae_st_array_T_1 : 14'h0; // @[TLB.scala:577:35, :588:{8,35}]
wire [13:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26]
wire [13:0] _ae_st_array_T_4 = cmd_put_partial ? _ae_st_array_T_3 : 14'h0; // @[TLB.scala:573:41, :589:{8,26}]
wire [13:0] _ae_st_array_T_5 = _ae_st_array_T_2 | _ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8]
wire [13:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26]
wire [13:0] _ae_st_array_T_7 = cmd_amo_logical ? _ae_st_array_T_6 : 14'h0; // @[TLB.scala:571:40, :590:{8,26}]
wire [13:0] _ae_st_array_T_8 = _ae_st_array_T_5 | _ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8]
wire [13:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29]
wire [13:0] _ae_st_array_T_10 = cmd_amo_arithmetic ? _ae_st_array_T_9 : 14'h0; // @[TLB.scala:572:43, :591:{8,29}]
wire [13:0] ae_st_array = _ae_st_array_T_8 | _ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8]
wire [13:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26]
wire [13:0] _must_alloc_array_T_1 = cmd_put_partial ? _must_alloc_array_T : 14'h0; // @[TLB.scala:573:41, :593:{8,26}]
wire [13:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26]
wire [13:0] _must_alloc_array_T_3 = cmd_amo_logical ? _must_alloc_array_T_2 : 14'h0; // @[TLB.scala:571:40, :594:{8,26}]
wire [13:0] _must_alloc_array_T_4 = _must_alloc_array_T_1 | _must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8]
wire [13:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29]
wire [13:0] _must_alloc_array_T_6 = cmd_amo_arithmetic ? _must_alloc_array_T_5 : 14'h0; // @[TLB.scala:572:43, :595:{8,29}]
wire [13:0] _must_alloc_array_T_7 = _must_alloc_array_T_4 | _must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8]
wire [13:0] _must_alloc_array_T_9 = {14{cmd_lrsc}}; // @[TLB.scala:570:33, :596:8]
wire [13:0] must_alloc_array = _must_alloc_array_T_7 | _must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8]
wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}]
wire [13:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73]
wire [13:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}]
wire [13:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 | ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}]
wire [13:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106]
wire [13:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}]
wire [13:0] pf_ld_array = cmd_read ? _pf_ld_array_T_6 : 14'h0; // @[TLB.scala:597:{24,104}]
wire [13:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44]
wire [13:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55]
wire [13:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}]
wire [13:0] _pf_st_array_T_3 = _pf_st_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}]
wire [13:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88]
wire [13:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}]
wire [13:0] pf_st_array = cmd_write_perms ? _pf_st_array_T_5 : 14'h0; // @[TLB.scala:577:35, :598:{24,86}]
wire [13:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25]
wire [13:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36]
wire [13:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}]
wire [13:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}]
wire [13:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69]
wire [13:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}]
wire [13:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100]
wire [13:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}]
wire [13:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81]
wire [13:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}]
wire [13:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64]
wire [13:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}]
wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73]
wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}]
wire [11:0] _gpa_hits_hit_mask_T_2 = {12{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}]
wire tlb_hit_if_not_gpa_miss = |real_hits; // @[package.scala:45:27]
wire tlb_hit = |_tlb_hit_T; // @[TLB.scala:611:{28,40}]
wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56]
wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}]
wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67]
wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}]
reg [6:0] state_vec_0; // @[Replacement.scala:305:17]
reg [2:0] state_reg_1; // @[Replacement.scala:168:70]
wire [1:0] _GEN_73 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45]
wire [1:0] lo_lo; // @[OneHot.scala:21:45]
assign lo_lo = _GEN_73; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_lo_lo; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_lo_lo = _GEN_73; // @[OneHot.scala:21:45]
wire [1:0] _GEN_74 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45]
wire [1:0] lo_hi; // @[OneHot.scala:21:45]
assign lo_hi = _GEN_74; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_lo_hi; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_lo_hi = _GEN_74; // @[OneHot.scala:21:45]
wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:21:45]
wire [3:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18]
wire [1:0] _GEN_75 = {sector_hits_5, sector_hits_4}; // @[OneHot.scala:21:45]
wire [1:0] hi_lo; // @[OneHot.scala:21:45]
assign hi_lo = _GEN_75; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_hi_lo; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_hi_lo = _GEN_75; // @[OneHot.scala:21:45]
wire [1:0] _GEN_76 = {sector_hits_7, sector_hits_6}; // @[OneHot.scala:21:45]
wire [1:0] hi_hi; // @[OneHot.scala:21:45]
assign hi_hi = _GEN_76; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_hi_hi; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_hi_hi = _GEN_76; // @[OneHot.scala:21:45]
wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:21:45]
wire [3:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18]
wire [3:0] _T_33 = hi_1 | lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28]
wire [2:0] state_vec_0_touch_way_sized = {|hi_1, |hi_2, hi_2[1] | lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_vec_0_set_left_older_T = state_vec_0_touch_way_sized[2]; // @[package.scala:163:13]
wire state_vec_0_set_left_older = ~_state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire [2:0] state_vec_0_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13]
wire [2:0] r_sectored_repl_addr_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13]
wire [2:0] state_vec_0_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :305:17]
wire [2:0] r_sectored_repl_addr_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :245:38, :305:17]
wire [1:0] _state_vec_0_T = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13]
wire [1:0] _state_vec_0_T_11 = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13]
wire _state_vec_0_set_left_older_T_1 = _state_vec_0_T[1]; // @[package.scala:163:13]
wire state_vec_0_set_left_older_1 = ~_state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}]
wire state_vec_0_left_subtree_state_1 = state_vec_0_left_subtree_state[1]; // @[package.scala:163:13]
wire state_vec_0_right_subtree_state_1 = state_vec_0_left_subtree_state[0]; // @[package.scala:163:13]
wire _state_vec_0_T_1 = _state_vec_0_T[0]; // @[package.scala:163:13]
wire _state_vec_0_T_5 = _state_vec_0_T[0]; // @[package.scala:163:13]
wire _state_vec_0_T_2 = _state_vec_0_T_1; // @[package.scala:163:13]
wire _state_vec_0_T_3 = ~_state_vec_0_T_2; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_4 = state_vec_0_set_left_older_1 ? state_vec_0_left_subtree_state_1 : _state_vec_0_T_3; // @[package.scala:163:13]
wire _state_vec_0_T_6 = _state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17]
wire _state_vec_0_T_7 = ~_state_vec_0_T_6; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_8 = state_vec_0_set_left_older_1 ? _state_vec_0_T_7 : state_vec_0_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_vec_0_hi = {state_vec_0_set_left_older_1, _state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_vec_0_T_9 = {state_vec_0_hi, _state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_vec_0_T_10 = state_vec_0_set_left_older ? state_vec_0_left_subtree_state : _state_vec_0_T_9; // @[package.scala:163:13]
wire _state_vec_0_set_left_older_T_2 = _state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62]
wire state_vec_0_set_left_older_2 = ~_state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}]
wire state_vec_0_left_subtree_state_2 = state_vec_0_right_subtree_state[1]; // @[package.scala:163:13]
wire state_vec_0_right_subtree_state_2 = state_vec_0_right_subtree_state[0]; // @[Replacement.scala:198:38]
wire _state_vec_0_T_12 = _state_vec_0_T_11[0]; // @[package.scala:163:13]
wire _state_vec_0_T_16 = _state_vec_0_T_11[0]; // @[package.scala:163:13]
wire _state_vec_0_T_13 = _state_vec_0_T_12; // @[package.scala:163:13]
wire _state_vec_0_T_14 = ~_state_vec_0_T_13; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_15 = state_vec_0_set_left_older_2 ? state_vec_0_left_subtree_state_2 : _state_vec_0_T_14; // @[package.scala:163:13]
wire _state_vec_0_T_17 = _state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17]
wire _state_vec_0_T_18 = ~_state_vec_0_T_17; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_19 = state_vec_0_set_left_older_2 ? _state_vec_0_T_18 : state_vec_0_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_vec_0_hi_1 = {state_vec_0_set_left_older_2, _state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_vec_0_T_20 = {state_vec_0_hi_1, _state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_vec_0_T_21 = state_vec_0_set_left_older ? _state_vec_0_T_20 : state_vec_0_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_vec_0_hi_2 = {state_vec_0_set_left_older, _state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_vec_0_T_22 = {state_vec_0_hi_2, _state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16]
wire [1:0] _GEN_77 = {superpage_hits_1, superpage_hits_0}; // @[OneHot.scala:21:45]
wire [1:0] lo_3; // @[OneHot.scala:21:45]
assign lo_3 = _GEN_77; // @[OneHot.scala:21:45]
wire [1:0] r_superpage_hit_bits_lo; // @[OneHot.scala:21:45]
assign r_superpage_hit_bits_lo = _GEN_77; // @[OneHot.scala:21:45]
wire [1:0] lo_4 = lo_3; // @[OneHot.scala:21:45, :31:18]
wire [1:0] _GEN_78 = {superpage_hits_3, superpage_hits_2}; // @[OneHot.scala:21:45]
wire [1:0] hi_3; // @[OneHot.scala:21:45]
assign hi_3 = _GEN_78; // @[OneHot.scala:21:45]
wire [1:0] r_superpage_hit_bits_hi; // @[OneHot.scala:21:45]
assign r_superpage_hit_bits_hi = _GEN_78; // @[OneHot.scala:21:45]
wire [1:0] hi_4 = hi_3; // @[OneHot.scala:21:45, :30:18]
wire [1:0] state_reg_touch_way_sized = {|hi_4, hi_4[1] | lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_reg_set_left_older_T = state_reg_touch_way_sized[1]; // @[package.scala:163:13]
wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13]
wire r_superpage_repl_addr_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38]
wire r_superpage_repl_addr_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire _state_reg_T = state_reg_touch_way_sized[0]; // @[package.scala:163:13]
wire _state_reg_T_4 = state_reg_touch_way_sized[0]; // @[package.scala:163:13]
wire _state_reg_T_1 = _state_reg_T; // @[package.scala:163:13]
wire _state_reg_T_2 = ~_state_reg_T_1; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_3 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_2; // @[package.scala:163:13]
wire _state_reg_T_5 = _state_reg_T_4; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_6 = ~_state_reg_T_5; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_7 = state_reg_set_left_older ? _state_reg_T_6 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_8 = {state_reg_hi, _state_reg_T_7}; // @[Replacement.scala:202:12, :206:16]
wire [5:0] _multipleHits_T = real_hits[5:0]; // @[package.scala:45:27]
wire [2:0] _multipleHits_T_1 = _multipleHits_T[2:0]; // @[Misc.scala:181:37]
wire _multipleHits_T_2 = _multipleHits_T_1[0]; // @[Misc.scala:181:37]
wire multipleHits_leftOne = _multipleHits_T_2; // @[Misc.scala:178:18, :181:37]
wire [1:0] _multipleHits_T_3 = _multipleHits_T_1[2:1]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_4 = _multipleHits_T_3[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_1 = _multipleHits_T_4; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_5 = _multipleHits_T_3[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne = _multipleHits_T_5; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_1 = multipleHits_leftOne_1 | multipleHits_rightOne; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_7 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo = _multipleHits_T_7; // @[Misc.scala:183:{49,61}]
wire _multipleHits_T_8 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}]
wire multipleHits_leftOne_2 = multipleHits_leftOne | multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_9 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}]
wire multipleHits_leftTwo = _multipleHits_T_8 | _multipleHits_T_9; // @[Misc.scala:183:{37,49,61}]
wire [2:0] _multipleHits_T_10 = _multipleHits_T[5:3]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_11 = _multipleHits_T_10[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_3 = _multipleHits_T_11; // @[Misc.scala:178:18, :181:37]
wire [1:0] _multipleHits_T_12 = _multipleHits_T_10[2:1]; // @[Misc.scala:182:39]
wire _multipleHits_T_13 = _multipleHits_T_12[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_4 = _multipleHits_T_13; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_14 = _multipleHits_T_12[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne_2 = _multipleHits_T_14; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_3 = multipleHits_leftOne_4 | multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_16 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo_1 = _multipleHits_T_16; // @[Misc.scala:183:{49,61}]
wire _multipleHits_T_17 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}]
wire multipleHits_rightOne_4 = multipleHits_leftOne_3 | multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_18 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}]
wire multipleHits_rightTwo_2 = _multipleHits_T_17 | _multipleHits_T_18; // @[Misc.scala:183:{37,49,61}]
wire multipleHits_leftOne_5 = multipleHits_leftOne_2 | multipleHits_rightOne_4; // @[Misc.scala:183:16]
wire _multipleHits_T_19 = multipleHits_leftTwo | multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}]
wire multipleHits_leftTwo_1 = _multipleHits_T_19 | _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}]
wire [6:0] _multipleHits_T_21 = real_hits[12:6]; // @[package.scala:45:27]
wire [2:0] _multipleHits_T_22 = _multipleHits_T_21[2:0]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_23 = _multipleHits_T_22[0]; // @[Misc.scala:181:37]
wire multipleHits_leftOne_6 = _multipleHits_T_23; // @[Misc.scala:178:18, :181:37]
wire [1:0] _multipleHits_T_24 = _multipleHits_T_22[2:1]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_25 = _multipleHits_T_24[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_7 = _multipleHits_T_25; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_26 = _multipleHits_T_24[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne_5 = _multipleHits_T_26; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_6 = multipleHits_leftOne_7 | multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_28 = multipleHits_leftOne_7 & multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo_3 = _multipleHits_T_28; // @[Misc.scala:183:{49,61}]
wire _multipleHits_T_29 = multipleHits_rightTwo_3; // @[Misc.scala:183:{37,49}]
wire multipleHits_leftOne_8 = multipleHits_leftOne_6 | multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_30 = multipleHits_leftOne_6 & multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:{16,61}]
wire multipleHits_leftTwo_2 = _multipleHits_T_29 | _multipleHits_T_30; // @[Misc.scala:183:{37,49,61}]
wire [3:0] _multipleHits_T_31 = _multipleHits_T_21[6:3]; // @[Misc.scala:182:39]
wire [1:0] _multipleHits_T_32 = _multipleHits_T_31[1:0]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_33 = _multipleHits_T_32[0]; // @[Misc.scala:181:37]
wire multipleHits_leftOne_9 = _multipleHits_T_33; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_34 = _multipleHits_T_32[1]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_rightOne_7 = _multipleHits_T_34; // @[Misc.scala:178:18, :182:39]
wire multipleHits_leftOne_10 = multipleHits_leftOne_9 | multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_36 = multipleHits_leftOne_9 & multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:61]
wire multipleHits_leftTwo_3 = _multipleHits_T_36; // @[Misc.scala:183:{49,61}]
wire [1:0] _multipleHits_T_37 = _multipleHits_T_31[3:2]; // @[Misc.scala:182:39]
wire _multipleHits_T_38 = _multipleHits_T_37[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_11 = _multipleHits_T_38; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_39 = _multipleHits_T_37[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne_8 = _multipleHits_T_39; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_9 = multipleHits_leftOne_11 | multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_41 = multipleHits_leftOne_11 & multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo_4 = _multipleHits_T_41; // @[Misc.scala:183:{49,61}]
wire multipleHits_rightOne_10 = multipleHits_leftOne_10 | multipleHits_rightOne_9; // @[Misc.scala:183:16]
wire _multipleHits_T_42 = multipleHits_leftTwo_3 | multipleHits_rightTwo_4; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_43 = multipleHits_leftOne_10 & multipleHits_rightOne_9; // @[Misc.scala:183:{16,61}]
wire multipleHits_rightTwo_5 = _multipleHits_T_42 | _multipleHits_T_43; // @[Misc.scala:183:{37,49,61}]
wire multipleHits_rightOne_11 = multipleHits_leftOne_8 | multipleHits_rightOne_10; // @[Misc.scala:183:16]
wire _multipleHits_T_44 = multipleHits_leftTwo_2 | multipleHits_rightTwo_5; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_45 = multipleHits_leftOne_8 & multipleHits_rightOne_10; // @[Misc.scala:183:{16,61}]
wire multipleHits_rightTwo_6 = _multipleHits_T_44 | _multipleHits_T_45; // @[Misc.scala:183:{37,49,61}]
wire _multipleHits_T_46 = multipleHits_leftOne_5 | multipleHits_rightOne_11; // @[Misc.scala:183:16]
wire _multipleHits_T_47 = multipleHits_leftTwo_1 | multipleHits_rightTwo_6; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_48 = multipleHits_leftOne_5 & multipleHits_rightOne_11; // @[Misc.scala:183:{16,61}]
wire multipleHits = _multipleHits_T_47 | _multipleHits_T_48; // @[Misc.scala:183:{37,49,61}]
assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25]
assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25]
wire _io_resp_pf_ld_T = bad_va & cmd_read; // @[TLB.scala:568:34, :633:28]
wire [13:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57]
wire _io_resp_pf_ld_T_2 = |_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}]
assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T | _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}]
assign io_resp_pf_ld_0 = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41]
wire _io_resp_pf_st_T = bad_va & cmd_write_perms; // @[TLB.scala:568:34, :577:35, :634:28]
wire [13:0] _io_resp_pf_st_T_1 = pf_st_array & hits; // @[TLB.scala:442:17, :598:24, :634:64]
wire _io_resp_pf_st_T_2 = |_io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}]
assign _io_resp_pf_st_T_3 = _io_resp_pf_st_T | _io_resp_pf_st_T_2; // @[TLB.scala:634:{28,48,72}]
assign io_resp_pf_st_0 = _io_resp_pf_st_T_3; // @[TLB.scala:318:7, :634:48]
wire [13:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47]
wire _io_resp_pf_inst_T_1 = |_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}]
assign _io_resp_pf_inst_T_2 = bad_va | _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}]
assign io_resp_pf_inst_0 = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29]
wire [13:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33]
assign _io_resp_ae_ld_T_1 = |_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}]
assign io_resp_ae_ld_0 = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41]
wire [13:0] _io_resp_ae_st_T = ae_st_array & hits; // @[TLB.scala:442:17, :590:53, :642:33]
assign _io_resp_ae_st_T_1 = |_io_resp_ae_st_T; // @[TLB.scala:642:{33,41}]
assign io_resp_ae_st_0 = _io_resp_ae_st_T_1; // @[TLB.scala:318:7, :642:41]
wire [13:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23]
wire [13:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}]
assign _io_resp_ae_inst_T_2 = |_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}]
assign io_resp_ae_inst_0 = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41]
assign _io_resp_ma_ld_T = misaligned & cmd_read; // @[TLB.scala:550:77, :645:31]
assign io_resp_ma_ld_0 = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31]
assign _io_resp_ma_st_T = misaligned & cmd_write; // @[TLB.scala:550:77, :646:31]
assign io_resp_ma_st_0 = _io_resp_ma_st_T; // @[TLB.scala:318:7, :646:31]
wire [13:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33]
assign _io_resp_cacheable_T_1 = |_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}]
assign io_resp_cacheable_0 = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41]
wire [13:0] _io_resp_must_alloc_T = must_alloc_array & hits; // @[TLB.scala:442:17, :595:46, :649:43]
assign _io_resp_must_alloc_T_1 = |_io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}]
assign io_resp_must_alloc_0 = _io_resp_must_alloc_T_1; // @[TLB.scala:318:7, :649:51]
wire [13:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47]
wire _io_resp_prefetchable_T_1 = |_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}]
assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}]
assign io_resp_prefetchable_0 = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59]
wire _io_resp_miss_T_1 = _io_resp_miss_T | tlb_miss; // @[TLB.scala:613:64, :651:{29,52}]
assign _io_resp_miss_T_2 = _io_resp_miss_T_1 | multipleHits; // @[Misc.scala:183:49]
assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64]
assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73]
assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23]
wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36]
wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}]
wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58]
wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47]
wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}]
assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8]
assign io_resp_gpa_0 = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8]
assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29]
wire r_superpage_repl_addr_left_subtree_older = state_reg_1[2]; // @[Replacement.scala:168:70, :243:38]
wire _r_superpage_repl_addr_T = r_superpage_repl_addr_left_subtree_state; // @[package.scala:163:13]
wire _r_superpage_repl_addr_T_1 = r_superpage_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12]
wire _r_superpage_repl_addr_T_2 = r_superpage_repl_addr_left_subtree_older ? _r_superpage_repl_addr_T : _r_superpage_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_superpage_repl_addr_T_3 = {r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] r_superpage_repl_addr_valids_lo = {superpage_entries_1_valid_0, superpage_entries_0_valid_0}; // @[package.scala:45:27]
wire [1:0] r_superpage_repl_addr_valids_hi = {superpage_entries_3_valid_0, superpage_entries_2_valid_0}; // @[package.scala:45:27]
wire [3:0] r_superpage_repl_addr_valids = {r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo}; // @[package.scala:45:27]
wire _r_superpage_repl_addr_T_4 = &r_superpage_repl_addr_valids; // @[package.scala:45:27]
wire [3:0] _r_superpage_repl_addr_T_5 = ~r_superpage_repl_addr_valids; // @[package.scala:45:27]
wire _r_superpage_repl_addr_T_6 = _r_superpage_repl_addr_T_5[0]; // @[OneHot.scala:48:45]
wire _r_superpage_repl_addr_T_7 = _r_superpage_repl_addr_T_5[1]; // @[OneHot.scala:48:45]
wire _r_superpage_repl_addr_T_8 = _r_superpage_repl_addr_T_5[2]; // @[OneHot.scala:48:45]
wire _r_superpage_repl_addr_T_9 = _r_superpage_repl_addr_T_5[3]; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_10 = {1'h1, ~_r_superpage_repl_addr_T_8}; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_11 = _r_superpage_repl_addr_T_7 ? 2'h1 : _r_superpage_repl_addr_T_10; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_12 = _r_superpage_repl_addr_T_6 ? 2'h0 : _r_superpage_repl_addr_T_11; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_13 = _r_superpage_repl_addr_T_4 ? _r_superpage_repl_addr_T_3 : _r_superpage_repl_addr_T_12; // @[Mux.scala:50:70]
wire r_sectored_repl_addr_left_subtree_older = state_vec_0[6]; // @[Replacement.scala:243:38, :305:17]
wire r_sectored_repl_addr_left_subtree_older_1 = r_sectored_repl_addr_left_subtree_state[2]; // @[package.scala:163:13]
wire r_sectored_repl_addr_left_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[1]; // @[package.scala:163:13]
wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state_1; // @[package.scala:163:13]
wire r_sectored_repl_addr_right_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[0]; // @[package.scala:163:13]
wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12]
wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older_1 ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire r_sectored_repl_addr_left_subtree_older_2 = r_sectored_repl_addr_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38]
wire r_sectored_repl_addr_left_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[1]; // @[package.scala:163:13]
wire _r_sectored_repl_addr_T_4 = r_sectored_repl_addr_left_subtree_state_2; // @[package.scala:163:13]
wire r_sectored_repl_addr_right_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[0]; // @[Replacement.scala:245:38]
wire _r_sectored_repl_addr_T_5 = r_sectored_repl_addr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12]
wire _r_sectored_repl_addr_T_6 = r_sectored_repl_addr_left_subtree_older_2 ? _r_sectored_repl_addr_T_4 : _r_sectored_repl_addr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_sectored_repl_addr_T_7 = {r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] _r_sectored_repl_addr_T_8 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_7; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [2:0] _r_sectored_repl_addr_T_9 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire _r_sectored_repl_addr_valids_T_1 = _r_sectored_repl_addr_valids_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_2 = _r_sectored_repl_addr_valids_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_4 = _r_sectored_repl_addr_valids_T_3 | sectored_entries_0_1_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_5 = _r_sectored_repl_addr_valids_T_4 | sectored_entries_0_1_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_7 = _r_sectored_repl_addr_valids_T_6 | sectored_entries_0_2_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_8 = _r_sectored_repl_addr_valids_T_7 | sectored_entries_0_2_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_10 = _r_sectored_repl_addr_valids_T_9 | sectored_entries_0_3_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_11 = _r_sectored_repl_addr_valids_T_10 | sectored_entries_0_3_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_13 = _r_sectored_repl_addr_valids_T_12 | sectored_entries_0_4_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_14 = _r_sectored_repl_addr_valids_T_13 | sectored_entries_0_4_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_16 = _r_sectored_repl_addr_valids_T_15 | sectored_entries_0_5_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_17 = _r_sectored_repl_addr_valids_T_16 | sectored_entries_0_5_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_19 = _r_sectored_repl_addr_valids_T_18 | sectored_entries_0_6_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_20 = _r_sectored_repl_addr_valids_T_19 | sectored_entries_0_6_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_22 = _r_sectored_repl_addr_valids_T_21 | sectored_entries_0_7_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_23 = _r_sectored_repl_addr_valids_T_22 | sectored_entries_0_7_valid_3; // @[package.scala:81:59]
wire [1:0] r_sectored_repl_addr_valids_lo_lo = {_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2}; // @[package.scala:45:27, :81:59]
wire [1:0] r_sectored_repl_addr_valids_lo_hi = {_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8}; // @[package.scala:45:27, :81:59]
wire [3:0] r_sectored_repl_addr_valids_lo = {r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo}; // @[package.scala:45:27]
wire [1:0] r_sectored_repl_addr_valids_hi_lo = {_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14}; // @[package.scala:45:27, :81:59]
wire [1:0] r_sectored_repl_addr_valids_hi_hi = {_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20}; // @[package.scala:45:27, :81:59]
wire [3:0] r_sectored_repl_addr_valids_hi = {r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo}; // @[package.scala:45:27]
wire [7:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27]
wire _r_sectored_repl_addr_T_10 = &r_sectored_repl_addr_valids; // @[package.scala:45:27]
wire [7:0] _r_sectored_repl_addr_T_11 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27]
wire _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_11[0]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_11[1]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_14 = _r_sectored_repl_addr_T_11[2]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_15 = _r_sectored_repl_addr_T_11[3]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_16 = _r_sectored_repl_addr_T_11[4]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_17 = _r_sectored_repl_addr_T_11[5]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_18 = _r_sectored_repl_addr_T_11[6]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_19 = _r_sectored_repl_addr_T_11[7]; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_20 = {2'h3, ~_r_sectored_repl_addr_T_18}; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_21 = _r_sectored_repl_addr_T_17 ? 3'h5 : _r_sectored_repl_addr_T_20; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_22 = _r_sectored_repl_addr_T_16 ? 3'h4 : _r_sectored_repl_addr_T_21; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_23 = _r_sectored_repl_addr_T_15 ? 3'h3 : _r_sectored_repl_addr_T_22; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_24 = _r_sectored_repl_addr_T_14 ? 3'h2 : _r_sectored_repl_addr_T_23; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_25 = _r_sectored_repl_addr_T_13 ? 3'h1 : _r_sectored_repl_addr_T_24; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_26 = _r_sectored_repl_addr_T_12 ? 3'h0 : _r_sectored_repl_addr_T_25; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_27 = _r_sectored_repl_addr_T_10 ? _r_sectored_repl_addr_T_9 : _r_sectored_repl_addr_T_26; // @[Mux.scala:50:70]
wire _r_sectored_hit_valid_T = sector_hits_0 | sector_hits_1; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T | sector_hits_2; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 | sector_hits_3; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_3 = _r_sectored_hit_valid_T_2 | sector_hits_4; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_4 = _r_sectored_hit_valid_T_3 | sector_hits_5; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_5 = _r_sectored_hit_valid_T_4 | sector_hits_6; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_6 = _r_sectored_hit_valid_T_5 | sector_hits_7; // @[package.scala:81:59]
wire [3:0] r_sectored_hit_bits_lo = {r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo}; // @[OneHot.scala:21:45]
wire [3:0] r_sectored_hit_bits_hi = {r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo}; // @[OneHot.scala:21:45]
wire [7:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45]
wire [3:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[7:4]; // @[OneHot.scala:21:45, :30:18]
wire [3:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[3:0]; // @[OneHot.scala:21:45, :31:18]
wire _r_sectored_hit_bits_T_1 = |r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 | r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] r_sectored_hit_bits_hi_2 = _r_sectored_hit_bits_T_2[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] r_sectored_hit_bits_lo_2 = _r_sectored_hit_bits_T_2[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _r_sectored_hit_bits_T_3 = |r_sectored_hit_bits_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _r_sectored_hit_bits_T_4 = r_sectored_hit_bits_hi_2 | r_sectored_hit_bits_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _r_sectored_hit_bits_T_5 = _r_sectored_hit_bits_T_4[1]; // @[OneHot.scala:32:28]
wire [1:0] _r_sectored_hit_bits_T_6 = {_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _r_sectored_hit_bits_T_7 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6}; // @[OneHot.scala:32:{10,14}]
wire _r_superpage_hit_valid_T = superpage_hits_0 | superpage_hits_1; // @[package.scala:81:59]
wire _r_superpage_hit_valid_T_1 = _r_superpage_hit_valid_T | superpage_hits_2; // @[package.scala:81:59]
wire _r_superpage_hit_valid_T_2 = _r_superpage_hit_valid_T_1 | superpage_hits_3; // @[package.scala:81:59]
wire [3:0] _r_superpage_hit_bits_T = {r_superpage_hit_bits_hi, r_superpage_hit_bits_lo}; // @[OneHot.scala:21:45]
wire [1:0] r_superpage_hit_bits_hi_1 = _r_superpage_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18]
wire [1:0] r_superpage_hit_bits_lo_1 = _r_superpage_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18]
wire _r_superpage_hit_bits_T_1 = |r_superpage_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _r_superpage_hit_bits_T_2 = r_superpage_hit_bits_hi_1 | r_superpage_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _r_superpage_hit_bits_T_3 = _r_superpage_hit_bits_T_2[1]; // @[OneHot.scala:32:28]
wire [1:0] _r_superpage_hit_bits_T_4 = {_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}]
wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45]
|
Generate the Verilog code corresponding to the following Chisel files.
File RegisterFile.scala:
package saturn.backend
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.tile.{CoreModule}
import freechips.rocketchip.util._
import saturn.common._
class OldestRRArbiter(val n: Int)(implicit p: Parameters) extends Module {
val io = IO(new ArbiterIO(new VectorReadReq, n))
val arb = Module(new RRArbiter(new VectorReadReq, n))
io <> arb.io
val oldest_oh = io.in.map(i => i.valid && i.bits.oldest)
//assert(PopCount(oldest_oh) <= 1.U)
when (oldest_oh.orR) {
io.chosen := VecInit(oldest_oh).asUInt
io.out.valid := true.B
io.out.bits := Mux1H(oldest_oh, io.in.map(_.bits))
for (i <- 0 until n) {
io.in(i).ready := oldest_oh(i) && io.out.ready
}
}
}
class RegisterReadXbar(n: Int, banks: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams {
val io = IO(new Bundle {
val in = Vec(n, Flipped(new VectorReadIO))
val out = Vec(banks, new VectorReadIO)
})
val arbs = Seq.fill(banks) { Module(new OldestRRArbiter(n)) }
for (i <- 0 until banks) {
io.out(i).req <> arbs(i).io.out
}
val bankOffset = log2Ceil(banks)
for (i <- 0 until n) {
val bank_sel = if (bankOffset == 0) true.B else UIntToOH(io.in(i).req.bits.eg(bankOffset-1,0))
for (j <- 0 until banks) {
arbs(j).io.in(i).valid := io.in(i).req.valid && bank_sel(j)
arbs(j).io.in(i).bits.eg := io.in(i).req.bits.eg >> bankOffset
arbs(j).io.in(i).bits.oldest := io.in(i).req.bits.oldest
}
io.in(i).req.ready := Mux1H(bank_sel, arbs.map(_.io.in(i).ready))
io.in(i).resp := Mux1H(bank_sel, io.out.map(_.resp))
}
}
class RegisterFileBank(reads: Int, maskReads: Int, rows: Int, maskRows: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams {
val io = IO(new Bundle {
val read = Vec(reads, Flipped(new VectorReadIO))
val mask_read = Vec(maskReads, Flipped(new VectorReadIO))
val write = Input(Valid(new VectorWrite(dLen)))
val ll_write = Flipped(Decoupled(new VectorWrite(dLen)))
})
val ll_write_valid = RegInit(false.B)
val ll_write_bits = Reg(new VectorWrite(dLen))
val vrf = Mem(rows, Vec(dLen, Bool()))
val v0_mask = Mem(maskRows, Vec(dLen, Bool()))
for (read <- io.read) {
read.req.ready := !(ll_write_valid && read.req.bits.eg === ll_write_bits.eg)
read.resp := DontCare
when (read.req.valid) {
read.resp := vrf.read(read.req.bits.eg).asUInt
}
}
for (mask_read <- io.mask_read) {
mask_read.req.ready := !(ll_write_valid && mask_read.req.bits.eg === ll_write_bits.eg)
mask_read.resp := DontCare
when (mask_read.req.valid) {
mask_read.resp := v0_mask.read(mask_read.req.bits.eg).asUInt
}
}
val write = WireInit(io.write)
io.ll_write.ready := false.B
if (vParams.vrfHiccupBuffer) {
when (!io.write.valid) { // drain hiccup buffer
write.valid := ll_write_valid || io.ll_write.valid
write.bits := Mux(ll_write_valid, ll_write_bits, io.ll_write.bits)
ll_write_valid := false.B
when (io.ll_write.valid && ll_write_valid) {
ll_write_valid := true.B
ll_write_bits := io.ll_write.bits
}
io.ll_write.ready := true.B
} .elsewhen (!ll_write_valid) { // fill hiccup buffer
when (io.ll_write.valid) {
ll_write_valid := true.B
ll_write_bits := io.ll_write.bits
}
io.ll_write.ready := true.B
}
} else {
when (!io.write.valid) {
io.ll_write.ready := true.B
write.valid := io.ll_write.valid
write.bits := io.ll_write.bits
}
}
when (write.valid) {
vrf.write(
write.bits.eg,
VecInit(write.bits.data.asBools),
write.bits.mask.asBools)
when (write.bits.eg < maskRows.U) {
v0_mask.write(
write.bits.eg,
VecInit(write.bits.data.asBools),
write.bits.mask.asBools)
}
}
}
class RegisterFile(reads: Seq[Int], maskReads: Seq[Int], pipeWrites: Int, llWrites: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams {
val nBanks = vParams.vrfBanking
// Support 1, 2, and 4 banks for the VRF
require(nBanks == 1 || nBanks == 2 || nBanks == 4)
val io = IO(new Bundle {
val read = MixedVec(reads.map(rc => Vec(rc, Flipped(new VectorReadIO))))
val mask_read = MixedVec(maskReads.map(rc => Vec(rc, Flipped(new VectorReadIO))))
val pipe_writes = Vec(pipeWrites, Input(Valid(new VectorWrite(dLen))))
val ll_writes = Vec(llWrites, Flipped(Decoupled(new VectorWrite(dLen))))
})
val vrf = Seq.fill(nBanks) { Module(new RegisterFileBank(reads.size, maskReads.size, egsTotal/nBanks, if (egsPerVReg < nBanks) 1 else egsPerVReg / nBanks)) }
reads.zipWithIndex.foreach { case (rc, i) =>
val xbar = Module(new RegisterReadXbar(rc, nBanks))
vrf.zipWithIndex.foreach { case (bank, j) =>
bank.io.read(i) <> xbar.io.out(j)
}
xbar.io.in <> io.read(i)
}
maskReads.zipWithIndex.foreach { case (rc, i) =>
val mask_xbar = Module(new RegisterReadXbar(rc, nBanks))
vrf.zipWithIndex.foreach { case (bank, j) =>
bank.io.mask_read(i) <> mask_xbar.io.out(j)
}
mask_xbar.io.in <> io.mask_read(i)
}
io.ll_writes.foreach(_.ready := false.B)
vrf.zipWithIndex.foreach { case (rf, i) =>
val bank_match = io.pipe_writes.map { w => (w.bits.bankId === i.U) && w.valid }
val bank_write_data = Mux1H(bank_match, io.pipe_writes.map(_.bits.data))
val bank_write_mask = Mux1H(bank_match, io.pipe_writes.map(_.bits.mask))
val bank_write_eg = Mux1H(bank_match, io.pipe_writes.map(_.bits.eg))
val bank_write_valid = bank_match.orR
rf.io.write.valid := bank_write_valid
rf.io.write.bits.data := bank_write_data
rf.io.write.bits.mask := bank_write_mask
rf.io.write.bits.eg := bank_write_eg >> vrfBankBits
when (bank_write_valid) { PopCount(bank_match) === 1.U }
val ll_arb = Module(new Arbiter(new VectorWrite(dLen), llWrites))
rf.io.ll_write <> ll_arb.io.out
io.ll_writes.zipWithIndex.foreach { case (w, j) =>
ll_arb.io.in(j).valid := w.valid && w.bits.bankId === i.U
ll_arb.io.in(j).bits.eg := w.bits.eg >> vrfBankBits
ll_arb.io.in(j).bits.data := w.bits.data
ll_arb.io.in(j).bits.mask := w.bits.mask
when (ll_arb.io.in(j).ready && w.bits.bankId === i.U) {
w.ready := true.B
}
}
}
}
|
module OldestRRArbiter( // @[RegisterFile.scala:10:7]
input clock, // @[RegisterFile.scala:10:7]
output io_in_0_ready, // @[RegisterFile.scala:11:14]
input io_in_0_valid, // @[RegisterFile.scala:11:14]
input [6:0] io_in_0_bits_eg, // @[RegisterFile.scala:11:14]
input io_in_0_bits_oldest, // @[RegisterFile.scala:11:14]
output io_in_1_ready, // @[RegisterFile.scala:11:14]
input io_in_1_valid, // @[RegisterFile.scala:11:14]
input [6:0] io_in_1_bits_eg, // @[RegisterFile.scala:11:14]
input io_in_1_bits_oldest, // @[RegisterFile.scala:11:14]
output io_in_2_ready, // @[RegisterFile.scala:11:14]
input io_in_2_valid, // @[RegisterFile.scala:11:14]
input [6:0] io_in_2_bits_eg, // @[RegisterFile.scala:11:14]
input io_out_ready, // @[RegisterFile.scala:11:14]
output io_out_valid, // @[RegisterFile.scala:11:14]
output [6:0] io_out_bits_eg // @[RegisterFile.scala:11:14]
);
wire _arb_io_in_0_ready; // @[RegisterFile.scala:13:19]
wire _arb_io_in_1_ready; // @[RegisterFile.scala:13:19]
wire _arb_io_in_2_ready; // @[RegisterFile.scala:13:19]
wire _arb_io_out_valid; // @[RegisterFile.scala:13:19]
wire [6:0] _arb_io_out_bits_eg; // @[RegisterFile.scala:13:19]
wire oldest_oh_0 = io_in_0_valid & io_in_0_bits_oldest; // @[RegisterFile.scala:15:42]
wire oldest_oh_1 = io_in_1_valid & io_in_1_bits_oldest; // @[RegisterFile.scala:15:42]
wire _GEN = oldest_oh_0 | oldest_oh_1; // @[RegisterFile.scala:15:42]
RRArbiter arb ( // @[RegisterFile.scala:13:19]
.clock (clock),
.io_in_0_ready (_arb_io_in_0_ready),
.io_in_0_valid (io_in_0_valid),
.io_in_0_bits_eg (io_in_0_bits_eg),
.io_in_1_ready (_arb_io_in_1_ready),
.io_in_1_valid (io_in_1_valid),
.io_in_1_bits_eg (io_in_1_bits_eg),
.io_in_2_ready (_arb_io_in_2_ready),
.io_in_2_valid (io_in_2_valid),
.io_in_2_bits_eg (io_in_2_bits_eg),
.io_out_ready (io_out_ready),
.io_out_valid (_arb_io_out_valid),
.io_out_bits_eg (_arb_io_out_bits_eg)
); // @[RegisterFile.scala:13:19]
assign io_in_0_ready = _GEN ? oldest_oh_0 & io_out_ready : _arb_io_in_0_ready; // @[RegisterFile.scala:10:7, :13:19, :14:6, :15:42, :17:24, :22:{22,38}]
assign io_in_1_ready = _GEN ? oldest_oh_1 & io_out_ready : _arb_io_in_1_ready; // @[RegisterFile.scala:10:7, :13:19, :14:6, :15:42, :17:24, :22:{22,38}]
assign io_in_2_ready = ~_GEN & _arb_io_in_2_ready; // @[RegisterFile.scala:10:7, :13:19, :14:6, :17:24, :22:22]
assign io_out_valid = _GEN | _arb_io_out_valid; // @[RegisterFile.scala:10:7, :13:19, :14:6, :17:24, :19:18]
assign io_out_bits_eg = _GEN ? (oldest_oh_0 ? io_in_0_bits_eg : 7'h0) | (oldest_oh_1 ? io_in_1_bits_eg : 7'h0) : _arb_io_out_bits_eg; // @[Mux.scala:30:73]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File INToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val signedIn = Input(Bool())
val in = Input(Bits(intWidth.W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val intAsRawFloat = rawFloatFromIN(io.signedIn, io.in);
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
intAsRawFloat.expWidth,
intWidth,
expWidth,
sigWidth,
flRoundOpt_sigMSBitAlwaysZero | flRoundOpt_neverUnderflows
))
roundAnyRawFNToRecFN.io.invalidExc := false.B
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := intAsRawFloat
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File rawFloatFromIN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
object rawFloatFromIN
{
def apply(signedIn: Bool, in: Bits): RawFloat =
{
val expWidth = log2Up(in.getWidth) + 1
//*** CHANGE THIS; CAN BE VERY LARGE:
val extIntWidth = 1<<(expWidth - 1)
val sign = signedIn && in(in.getWidth - 1)
val absIn = Mux(sign, -in.asUInt, in.asUInt)
val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0)
val adjustedNormDist = countLeadingZeros(extAbsIn)
val sig =
(extAbsIn<<adjustedNormDist)(
extIntWidth - 1, extIntWidth - in.getWidth)
val out = Wire(new RawFloat(expWidth, in.getWidth))
out.isNaN := false.B
out.isInf := false.B
out.isZero := ! sig(in.getWidth - 1)
out.sign := sign
out.sExp := (2.U(2.W) ## ~adjustedNormDist(expWidth - 2, 0)).zext
out.sig := sig
out
}
}
|
module INToRecFN_i1_e8_s24_17(); // @[INToRecFN.scala:43:7]
wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31]
wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44]
wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22]
wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33]
wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72]
wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72]
wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20]
wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20]
wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire io_in = 1'h1; // @[Mux.scala:50:70]
wire io_detectTininess = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70]
wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7]
wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29]
wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52]
wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23]
wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36]
RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_17 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Breakpoint.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile.{CoreBundle, HasCoreParameters}
import freechips.rocketchip.util._
class BPControl(implicit p: Parameters) extends CoreBundle()(p) {
val ttype = UInt(4.W)
val dmode = Bool()
val maskmax = UInt(6.W)
val reserved = UInt((xLen - (if (coreParams.useBPWatch) 26 else 24)).W)
val action = UInt((if (coreParams.useBPWatch) 3 else 1).W)
val chain = Bool()
val zero = UInt(2.W)
val tmatch = UInt(2.W)
val m = Bool()
val h = Bool()
val s = Bool()
val u = Bool()
val x = Bool()
val w = Bool()
val r = Bool()
def tType = 2
def maskMax = 4
def enabled(mstatus: MStatus) = !mstatus.debug && Cat(m, h, s, u)(mstatus.prv)
}
class TExtra(implicit p: Parameters) extends CoreBundle()(p) {
def mvalueBits: Int = if (xLen == 32) coreParams.mcontextWidth min 6 else coreParams.mcontextWidth min 13
def svalueBits: Int = if (xLen == 32) coreParams.scontextWidth min 16 else coreParams.scontextWidth min 34
def mselectPos: Int = if (xLen == 32) 25 else 50
def mvaluePos : Int = mselectPos + 1
def sselectPos: Int = 0
def svaluePos : Int = 2
val mvalue = UInt(mvalueBits.W)
val mselect = Bool()
val pad2 = UInt((mselectPos - svalueBits - 2).W)
val svalue = UInt(svalueBits.W)
val pad1 = UInt(1.W)
val sselect = Bool()
}
class BP(implicit p: Parameters) extends CoreBundle()(p) {
val control = new BPControl
val address = UInt(vaddrBits.W)
val textra = new TExtra
def contextMatch(mcontext: UInt, scontext: UInt) =
(if (coreParams.mcontextWidth > 0) (!textra.mselect || (mcontext(textra.mvalueBits-1,0) === textra.mvalue)) else true.B) &&
(if (coreParams.scontextWidth > 0) (!textra.sselect || (scontext(textra.svalueBits-1,0) === textra.svalue)) else true.B)
def mask(dummy: Int = 0) =
(0 until control.maskMax-1).scanLeft(control.tmatch(0))((m, i) => m && address(i)).asUInt
def pow2AddressMatch(x: UInt) =
(~x | mask()) === (~address | mask())
def rangeAddressMatch(x: UInt) =
(x >= address) ^ control.tmatch(0)
def addressMatch(x: UInt) =
Mux(control.tmatch(1), rangeAddressMatch(x), pow2AddressMatch(x))
}
class BPWatch (val n: Int) extends Bundle() {
val valid = Vec(n, Bool())
val rvalid = Vec(n, Bool())
val wvalid = Vec(n, Bool())
val ivalid = Vec(n, Bool())
val action = UInt(3.W)
}
class BreakpointUnit(n: Int)(implicit val p: Parameters) extends Module with HasCoreParameters {
val io = IO(new Bundle {
val status = Input(new MStatus())
val bp = Input(Vec(n, new BP))
val pc = Input(UInt(vaddrBits.W))
val ea = Input(UInt(vaddrBits.W))
val mcontext = Input(UInt(coreParams.mcontextWidth.W))
val scontext = Input(UInt(coreParams.scontextWidth.W))
val xcpt_if = Output(Bool())
val xcpt_ld = Output(Bool())
val xcpt_st = Output(Bool())
val debug_if = Output(Bool())
val debug_ld = Output(Bool())
val debug_st = Output(Bool())
val bpwatch = Output(Vec(n, new BPWatch(1)))
})
io.xcpt_if := false.B
io.xcpt_ld := false.B
io.xcpt_st := false.B
io.debug_if := false.B
io.debug_ld := false.B
io.debug_st := false.B
(io.bpwatch zip io.bp).foldLeft((true.B, true.B, true.B)) { case ((ri, wi, xi), (bpw, bp)) =>
val en = bp.control.enabled(io.status)
val cx = bp.contextMatch(io.mcontext, io.scontext)
val r = en && bp.control.r && bp.addressMatch(io.ea) && cx
val w = en && bp.control.w && bp.addressMatch(io.ea) && cx
val x = en && bp.control.x && bp.addressMatch(io.pc) && cx
val end = !bp.control.chain
val action = bp.control.action
bpw.action := action
bpw.valid(0) := false.B
bpw.rvalid(0) := false.B
bpw.wvalid(0) := false.B
bpw.ivalid(0) := false.B
when (end && r && ri) { io.xcpt_ld := (action === 0.U); io.debug_ld := (action === 1.U); bpw.valid(0) := true.B; bpw.rvalid(0) := true.B }
when (end && w && wi) { io.xcpt_st := (action === 0.U); io.debug_st := (action === 1.U); bpw.valid(0) := true.B; bpw.wvalid(0) := true.B }
when (end && x && xi) { io.xcpt_if := (action === 0.U); io.debug_if := (action === 1.U); bpw.valid(0) := true.B; bpw.ivalid(0) := true.B }
(end || r, end || w, end || x)
}
}
|
module BreakpointUnit_10( // @[Breakpoint.scala:79:7]
input clock, // @[Breakpoint.scala:79:7]
input reset, // @[Breakpoint.scala:79:7]
input io_status_debug, // @[Breakpoint.scala:80:14]
input io_status_cease, // @[Breakpoint.scala:80:14]
input io_status_wfi, // @[Breakpoint.scala:80:14]
input [1:0] io_status_dprv, // @[Breakpoint.scala:80:14]
input io_status_dv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_prv, // @[Breakpoint.scala:80:14]
input io_status_v, // @[Breakpoint.scala:80:14]
input io_status_sd, // @[Breakpoint.scala:80:14]
input io_status_mpv, // @[Breakpoint.scala:80:14]
input io_status_gva, // @[Breakpoint.scala:80:14]
input io_status_tsr, // @[Breakpoint.scala:80:14]
input io_status_tw, // @[Breakpoint.scala:80:14]
input io_status_tvm, // @[Breakpoint.scala:80:14]
input io_status_mxr, // @[Breakpoint.scala:80:14]
input io_status_sum, // @[Breakpoint.scala:80:14]
input io_status_mprv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_fs, // @[Breakpoint.scala:80:14]
input [1:0] io_status_mpp, // @[Breakpoint.scala:80:14]
input io_status_spp, // @[Breakpoint.scala:80:14]
input io_status_mpie, // @[Breakpoint.scala:80:14]
input io_status_spie, // @[Breakpoint.scala:80:14]
input io_status_mie, // @[Breakpoint.scala:80:14]
input io_status_sie, // @[Breakpoint.scala:80:14]
input [38:0] io_ea // @[Breakpoint.scala:80:14]
);
wire io_status_debug_0 = io_status_debug; // @[Breakpoint.scala:79:7]
wire io_status_cease_0 = io_status_cease; // @[Breakpoint.scala:79:7]
wire io_status_wfi_0 = io_status_wfi; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_dprv_0 = io_status_dprv; // @[Breakpoint.scala:79:7]
wire io_status_dv_0 = io_status_dv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_prv_0 = io_status_prv; // @[Breakpoint.scala:79:7]
wire io_status_v_0 = io_status_v; // @[Breakpoint.scala:79:7]
wire io_status_sd_0 = io_status_sd; // @[Breakpoint.scala:79:7]
wire io_status_mpv_0 = io_status_mpv; // @[Breakpoint.scala:79:7]
wire io_status_gva_0 = io_status_gva; // @[Breakpoint.scala:79:7]
wire io_status_tsr_0 = io_status_tsr; // @[Breakpoint.scala:79:7]
wire io_status_tw_0 = io_status_tw; // @[Breakpoint.scala:79:7]
wire io_status_tvm_0 = io_status_tvm; // @[Breakpoint.scala:79:7]
wire io_status_mxr_0 = io_status_mxr; // @[Breakpoint.scala:79:7]
wire io_status_sum_0 = io_status_sum; // @[Breakpoint.scala:79:7]
wire io_status_mprv_0 = io_status_mprv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_fs_0 = io_status_fs; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[Breakpoint.scala:79:7]
wire io_status_spp_0 = io_status_spp; // @[Breakpoint.scala:79:7]
wire io_status_mpie_0 = io_status_mpie; // @[Breakpoint.scala:79:7]
wire io_status_spie_0 = io_status_spie; // @[Breakpoint.scala:79:7]
wire io_status_mie_0 = io_status_mie; // @[Breakpoint.scala:79:7]
wire io_status_sie_0 = io_status_sie; // @[Breakpoint.scala:79:7]
wire [38:0] io_ea_0 = io_ea; // @[Breakpoint.scala:79:7]
wire [38:0] io_pc = 39'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_sxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_uxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_xs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_vs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [7:0] io_status_zero1 = 8'h0; // @[Breakpoint.scala:79:7, :80:14]
wire io_status_mbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sd_rv32 = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_ube = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_upie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_hie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_uie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_if = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_ld = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_st = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_if = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_ld = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_st = 1'h0; // @[Breakpoint.scala:79:7]
wire [22:0] io_status_zero2 = 23'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [31:0] io_status_isa = 32'h14112D; // @[Breakpoint.scala:79:7, :80:14]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
|
module AsyncValidSync_122( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_136 io_out_sink_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
|
module AsyncQueueSink_Phit_1( // @[AsyncQueue.scala:136:7]
input clock, // @[AsyncQueue.scala:136:7]
input reset, // @[AsyncQueue.scala:136:7]
input io_deq_ready, // @[AsyncQueue.scala:139:14]
output io_deq_valid, // @[AsyncQueue.scala:139:14]
output [31:0] io_deq_bits_phit, // @[AsyncQueue.scala:139:14]
input [31:0] io_async_mem_0_phit, // @[AsyncQueue.scala:139:14]
input [31:0] io_async_mem_1_phit, // @[AsyncQueue.scala:139:14]
input [31:0] io_async_mem_2_phit, // @[AsyncQueue.scala:139:14]
input [31:0] io_async_mem_3_phit, // @[AsyncQueue.scala:139:14]
input [31:0] io_async_mem_4_phit, // @[AsyncQueue.scala:139:14]
input [31:0] io_async_mem_5_phit, // @[AsyncQueue.scala:139:14]
input [31:0] io_async_mem_6_phit, // @[AsyncQueue.scala:139:14]
input [31:0] io_async_mem_7_phit, // @[AsyncQueue.scala:139:14]
output [3:0] io_async_ridx, // @[AsyncQueue.scala:139:14]
input [3:0] io_async_widx, // @[AsyncQueue.scala:139:14]
output io_async_safe_ridx_valid, // @[AsyncQueue.scala:139:14]
input io_async_safe_widx_valid, // @[AsyncQueue.scala:139:14]
input io_async_safe_source_reset_n, // @[AsyncQueue.scala:139:14]
output io_async_safe_sink_reset_n // @[AsyncQueue.scala:139:14]
);
wire _source_extend_io_out; // @[AsyncQueue.scala:175:31]
wire _sink_valid_0_io_out; // @[AsyncQueue.scala:172:33]
wire io_deq_ready_0 = io_deq_ready; // @[AsyncQueue.scala:136:7]
wire [31:0] io_async_mem_0_phit_0 = io_async_mem_0_phit; // @[AsyncQueue.scala:136:7]
wire [31:0] io_async_mem_1_phit_0 = io_async_mem_1_phit; // @[AsyncQueue.scala:136:7]
wire [31:0] io_async_mem_2_phit_0 = io_async_mem_2_phit; // @[AsyncQueue.scala:136:7]
wire [31:0] io_async_mem_3_phit_0 = io_async_mem_3_phit; // @[AsyncQueue.scala:136:7]
wire [31:0] io_async_mem_4_phit_0 = io_async_mem_4_phit; // @[AsyncQueue.scala:136:7]
wire [31:0] io_async_mem_5_phit_0 = io_async_mem_5_phit; // @[AsyncQueue.scala:136:7]
wire [31:0] io_async_mem_6_phit_0 = io_async_mem_6_phit; // @[AsyncQueue.scala:136:7]
wire [31:0] io_async_mem_7_phit_0 = io_async_mem_7_phit; // @[AsyncQueue.scala:136:7]
wire [3:0] io_async_widx_0 = io_async_widx; // @[AsyncQueue.scala:136:7]
wire io_async_safe_widx_valid_0 = io_async_safe_widx_valid; // @[AsyncQueue.scala:136:7]
wire io_async_safe_source_reset_n_0 = io_async_safe_source_reset_n; // @[AsyncQueue.scala:136:7]
wire _ridx_T = reset; // @[AsyncQueue.scala:148:30]
wire _valid_reg_T = reset; // @[AsyncQueue.scala:165:35]
wire _ridx_reg_T = reset; // @[AsyncQueue.scala:168:34]
wire _sink_valid_0_reset_T = reset; // @[AsyncQueue.scala:177:35]
wire _sink_valid_1_reset_T = reset; // @[AsyncQueue.scala:178:35]
wire _source_extend_reset_T = reset; // @[AsyncQueue.scala:179:35]
wire _source_valid_reset_T = reset; // @[AsyncQueue.scala:180:34]
wire _io_async_safe_sink_reset_n_T = reset; // @[AsyncQueue.scala:193:32]
wire _io_deq_valid_T; // @[AsyncQueue.scala:166:29]
wire [31:0] _io_deq_bits_WIRE_phit; // @[SynchronizerReg.scala:211:26]
wire _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:193:25]
wire [31:0] io_deq_bits_phit_0; // @[AsyncQueue.scala:136:7]
wire io_deq_valid_0; // @[AsyncQueue.scala:136:7]
wire io_async_safe_ridx_valid_0; // @[AsyncQueue.scala:136:7]
wire io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:136:7]
wire [3:0] io_async_ridx_0; // @[AsyncQueue.scala:136:7]
wire source_ready; // @[AsyncQueue.scala:147:30]
wire _ridx_T_1 = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35]
wire _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala:147:30, :148:77]
wire [3:0] _ridx_incremented_T_2; // @[AsyncQueue.scala:53:23]
wire [3:0] ridx_incremented; // @[AsyncQueue.scala:51:27]
reg [3:0] ridx_ridx_bin; // @[AsyncQueue.scala:52:25]
wire [4:0] _ridx_incremented_T = {1'h0, ridx_ridx_bin} + {4'h0, _ridx_T_1}; // @[Decoupled.scala:51:35]
wire [3:0] _ridx_incremented_T_1 = _ridx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43]
assign _ridx_incremented_T_2 = _ridx_T_2 ? 4'h0 : _ridx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :148:77]
assign ridx_incremented = _ridx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23]
wire [2:0] _ridx_T_3 = ridx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32]
wire [3:0] ridx = {ridx_incremented[3], ridx_incremented[2:0] ^ _ridx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}]
wire [3:0] widx; // @[ShiftReg.scala:48:24]
wire _valid_T = ridx != widx; // @[ShiftReg.scala:48:24]
wire valid = source_ready & _valid_T; // @[AsyncQueue.scala:147:30, :150:{28,36}]
wire [2:0] _index_T = ridx[2:0]; // @[AsyncQueue.scala:54:17, :156:43]
wire _index_T_1 = ridx[3]; // @[AsyncQueue.scala:54:17, :156:62]
wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:156:{62,75}]
wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:156:{43,55,75}]
wire [7:0][31:0] _GEN = {{io_async_mem_7_phit_0}, {io_async_mem_6_phit_0}, {io_async_mem_5_phit_0}, {io_async_mem_4_phit_0}, {io_async_mem_3_phit_0}, {io_async_mem_2_phit_0}, {io_async_mem_1_phit_0}, {io_async_mem_0_phit_0}}; // @[SynchronizerReg.scala:209:18]
wire [31:0] _io_deq_bits_T; // @[SynchronizerReg.scala:211:26]
assign io_deq_bits_phit_0 = _io_deq_bits_WIRE_phit; // @[SynchronizerReg.scala:211:26]
wire [31:0] _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26]
assign _io_deq_bits_T = _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26]
assign _io_deq_bits_WIRE_phit = _io_deq_bits_T; // @[SynchronizerReg.scala:211:26]
reg valid_reg; // @[AsyncQueue.scala:165:56]
assign _io_deq_valid_T = valid_reg & source_ready; // @[AsyncQueue.scala:147:30, :165:56, :166:29]
assign io_deq_valid_0 = _io_deq_valid_T; // @[AsyncQueue.scala:136:7, :166:29]
reg [3:0] ridx_gray; // @[AsyncQueue.scala:168:55]
assign io_async_ridx_0 = ridx_gray; // @[AsyncQueue.scala:136:7, :168:55]
wire _sink_valid_0_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45]
wire _sink_valid_0_reset_T_2 = _sink_valid_0_reset_T | _sink_valid_0_reset_T_1; // @[AsyncQueue.scala:177:{35,42,45}]
wire _sink_valid_0_reset_T_3 = _sink_valid_0_reset_T_2; // @[AsyncQueue.scala:177:{42,66}]
wire _sink_valid_1_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :178:45]
wire _sink_valid_1_reset_T_2 = _sink_valid_1_reset_T | _sink_valid_1_reset_T_1; // @[AsyncQueue.scala:178:{35,42,45}]
wire _sink_valid_1_reset_T_3 = _sink_valid_1_reset_T_2; // @[AsyncQueue.scala:178:{42,66}]
wire _source_extend_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :179:45]
wire _source_extend_reset_T_2 = _source_extend_reset_T | _source_extend_reset_T_1; // @[AsyncQueue.scala:179:{35,42,45}]
wire _source_extend_reset_T_3 = _source_extend_reset_T_2; // @[AsyncQueue.scala:179:{42,66}]
assign _io_async_safe_sink_reset_n_T_1 = ~_io_async_safe_sink_reset_n_T; // @[AsyncQueue.scala:193:{25,32}]
assign io_async_safe_sink_reset_n_0 = _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:136:7, :193:25]
always @(posedge clock or posedge _ridx_T) begin // @[AsyncQueue.scala:136:7, :148:30]
if (_ridx_T) // @[AsyncQueue.scala:136:7, :148:30]
ridx_ridx_bin <= 4'h0; // @[AsyncQueue.scala:52:25]
else // @[AsyncQueue.scala:136:7]
ridx_ridx_bin <= ridx_incremented; // @[AsyncQueue.scala:51:27, :52:25]
always @(posedge, posedge)
always @(posedge clock or posedge _valid_reg_T) begin // @[AsyncQueue.scala:136:7, :165:35]
if (_valid_reg_T) // @[AsyncQueue.scala:136:7, :165:35]
valid_reg <= 1'h0; // @[AsyncQueue.scala:165:56]
else // @[AsyncQueue.scala:136:7]
valid_reg <= valid; // @[AsyncQueue.scala:150:28, :165:56]
always @(posedge, posedge)
always @(posedge clock or posedge _ridx_reg_T) begin // @[AsyncQueue.scala:136:7, :168:34]
if (_ridx_reg_T) // @[AsyncQueue.scala:136:7, :168:34]
ridx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :168:55]
else // @[AsyncQueue.scala:136:7]
ridx_gray <= ridx; // @[AsyncQueue.scala:54:17, :168:55]
always @(posedge, posedge)
|
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
|
module OptimizationBarrier_TLBEntryData_203( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
|
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_185( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge)
|
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