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-- ========== Copyright Header Begin =============================================
-- AmgPacman File: freqDividerV3.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
-- Notas adicinales:
----------------------------------------------------------------------------------
-- IMPORTANTE: las salidas clk_1KHz, clk_100Hz y clk_2Hz mandan pulsos, no el reloj
-- completo. Tengo pendiente acabarlo. La frecuencia de entrada al modulo debe ser 50MHz,
-- que es la frecuencia de reloj de la Nexys2.
----------------------------------------------------------------------------------
-- Reporte de sintesis:
----------------------------------------------------------------------------------
-- Minimum period: 5.085ns (Maximum Frequency: 196.638MHz).
-- Codigo del divisor libre de warnings (en principio).
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity freqDividerV3 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
clk_1KHz : out STD_LOGIC;
pulso_2Hz: out std_logic
);
end freqDividerV3;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture rtl of freqDividerV3 is
-----------------------------------------------------------------------------
-- Declaracion de senales
-----------------------------------------------------------------------------
signal pulso_1KHz_aux: std_logic;
signal pulso_100Hz_aux: std_logic;
-----------------------------------------------------------------------------
-- Componentes
-----------------------------------------------------------------------------
COMPONENT modulo1KHz
PORT(
clk_50MHz : IN std_logic;
rst : IN std_logic;
clk_1KHz : OUT std_logic;
pulso_1KHz : OUT std_logic
);
END COMPONENT;
COMPONENT modulo100Hz
PORT(
clk_50MHz : IN std_logic;
ena : IN std_logic;
rst: in std_logic;
pulso_100Hz : OUT std_logic
);
END COMPONENT;
COMPONENT modulo2Hz
PORT(
clk_50MHz : IN std_logic;
ena : IN std_logic;
rst : IN std_logic;
pulso_2Hz : OUT std_logic
);
END COMPONENT;
begin
-----------------------------------------------------------------------------
-- Conexion de senales
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Conexion de componentes
-----------------------------------------------------------------------------
Inst_modulo1KHz: modulo1KHz PORT MAP(
clk_50MHz => clk,
rst => rst,
clk_1KHz => clk_1KHz,
pulso_1KHz => pulso_1KHz_aux
);
modulo100Hz_0: modulo100Hz PORT MAP(
clk_50MHz => clk,
ena => pulso_1KHz_aux,
rst => rst,
pulso_100Hz => pulso_100Hz_aux
);
modulo2Hz_0: modulo2Hz PORT MAP(
clk_50MHz => clk,
ena => pulso_100Hz_aux,
rst => rst,
pulso_2Hz => pulso_2Hz
);
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbjtag
-- File: ahbjtag.vhd
-- Author: Edvin Catovic, Jiri Gaisler - Gaisler Research
-- Description: JTAG communication link with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
use gaisler.libjtagcom.all;
use gaisler.jtag.all;
entity ahbjtag_bsd is
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
asel : in std_ulogic;
dsel : in std_ulogic;
tck : in std_ulogic;
regi : in std_ulogic;
shift : in std_ulogic;
rego : out std_ulogic
);
end;
architecture struct of ahbjtag_bsd is
-- Set REREAD to 1 to include support for re-read operation when host reads
-- out data register before jtagcom has completed the current AMBA access and
-- returned to state 'shft'.
constant REREAD : integer := 1;
constant REVISION : integer := REREAD;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal ltapi : tap_in_type;
signal ltapo : tap_out_type;
signal trst: std_ulogic;
begin
ahbmst0 : ahbmst
generic map (hindex => hindex, venid => VENDOR_GAISLER, devid => GAISLER_AHBJTAG, version => REVISION)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
jtagcom0 : jtagcom generic map (isel => 1, nsync => nsync, ainst => ainst, dinst => dinst, reread => REREAD)
port map (rst, clk, ltapo, ltapi, dmao, dmai, tck, trst);
ltapo.asel <= asel;
ltapo.dsel <= dsel;
ltapo.tck <= tck;
ltapo.tdi <= regi;
ltapo.shift <= shift;
ltapo.reset <= '0';
ltapo.inst <= (others => '0');
rego <= ltapi.tdo;
trst <= '1';
-- pragma translate_off
bootmsg : report_version
generic map ("ahbjtag AHB Debug JTAG rev " & tost(REVISION));
-- pragma translate_on
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Oct 17 02:50:46 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top RAT_slice_1_0_0 -prefix
-- RAT_slice_1_0_0_ RAT_slice_12_3_0_sim_netlist.vhdl
-- Design : RAT_slice_12_3_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_slice_1_0_0 is
port (
Din : in STD_LOGIC_VECTOR ( 17 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_slice_1_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of RAT_slice_1_0_0 : entity is "RAT_slice_12_3_0,xlslice,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_slice_1_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of RAT_slice_1_0_0 : entity is "xlslice,Vivado 2016.4";
end RAT_slice_1_0_0;
architecture STRUCTURE of RAT_slice_1_0_0 is
signal \^din\ : STD_LOGIC_VECTOR ( 17 downto 0 );
begin
Dout(7 downto 0) <= \^din\(7 downto 0);
\^din\(7 downto 0) <= Din(7 downto 0);
end STRUCTURE;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Oct 17 02:50:46 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top RAT_slice_1_0_0 -prefix
-- RAT_slice_1_0_0_ RAT_slice_12_3_0_sim_netlist.vhdl
-- Design : RAT_slice_12_3_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_slice_1_0_0 is
port (
Din : in STD_LOGIC_VECTOR ( 17 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_slice_1_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of RAT_slice_1_0_0 : entity is "RAT_slice_12_3_0,xlslice,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_slice_1_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of RAT_slice_1_0_0 : entity is "xlslice,Vivado 2016.4";
end RAT_slice_1_0_0;
architecture STRUCTURE of RAT_slice_1_0_0 is
signal \^din\ : STD_LOGIC_VECTOR ( 17 downto 0 );
begin
Dout(7 downto 0) <= \^din\(7 downto 0);
\^din\(7 downto 0) <= Din(7 downto 0);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_139 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_139;
architecture augh of cmp_139 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_139 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_139;
architecture augh of cmp_139 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, after, if-then-else, enumerations, array, record, case, for-loop, signals-attributes.
use work.std_logic_1164_for_tst.all;
entity ENT00011_Test_Bench is
end ENT00011_Test_Bench;
architecture ARCH00011_Test_Bench of ENT00011_Test_Bench is
type std_array_array is array (0 to 3, 1 to 4) of std_ulogic;
signal I_saa : std_array_array := (others => x"B");
subtype byte is bit_vector(7 downto 0);
subtype byte2 is bit_vector(0 to 7);
signal b1 : byte := x"00";
signal b2 : byte2 := x"00";
type bit_array_array is array (0 to 3, 4 downto 1) of bit;
signal I_baa : bit_array_array := (others => x"A");
type NatArray is array (natural range <>) of natural;
type std_array is array (0 to 7) of std_logic;
signal I_sa : std_array := "10101010";
type enum is (a_v, b_v, c_v, d_v, e_v, f_v);
type enum_array is array (integer range <>) of enum;
type rec is record
f1 : integer;
f2 : boolean;
f3 : bit;
f4 : enum;
f5 : enum_array(0 to 3);
f6 : NatArray(7 downto 0);
f7 : bit_vector(7 downto 0);
end record;
type rec_array is array (integer range <>) of rec;
signal e : enum := a_v;
signal ea : enum_array(0 to 3) := (others => a_v);
signal r : rec := (
f1 => 10
, f2 => true
, f3 => '1'
, f4 => a_v
, f5 => (others => a_v)
, f6 => (0 => 10, 7 => 3, others => 0)
, f7 => x"33"
);
signal ra : rec_array(0 to 3) := (others => (
f1 => 10
, f2 => true
, f3 => '1'
, f4 => a_v
, f5 => (others => a_v)
, f6 => (0 => 10, 7 => 3, others => 0)
, f7 => x"33"
)
);
signal bv : bit_vector(15 downto 0) := x"CCCC";
signal clk : std_ulogic := '0';
signal clk2 : std_ulogic := '0';
type BoolVector is array (integer range <>) of boolean;
signal bool : BoolVector(1 to 60);
begin
bool(37) <= bv'Active;
bool(38) <= ra'Active;
bool(39) <= r'Active;
bool(40) <= ea'Active;
bool(41) <= e'Active;
bool(42) <= I_sa'Active;
bool(43) <= I_baa'Active;
bool(44) <= I_saa'Active;
bool(45) <= b1'Active;
bool(46) <= b2'Active;
bool(47) <= clk'Active;
bool(48) <= clk2'Active;
clk <= not clk after 1 us;
clk2 <= not clk2 after 3 us;
process (clk)
begin
if clk'event and clk = '1' then
b1 <= b1(6 downto 0) & not b1(7);
case e is
when a_v => e <= b_v;
when b_v => e <= c_v;
when c_v => e <= d_v;
when d_v => e <= e_v;
when e_v => e <= f_v;
when f_v => e <= a_v;
end case;
ea(0) <= e;
ea_loop: for i in 1 to ea'length-1 loop
ea(i) <= ea(i-1);
end loop ea_loop;
elsif falling_edge(clk) then
bv <= bv(bv'left-1 downto bv'low) & bv(bv'high);
r.f1 <= r.f1 + 1;
r.f2 <= not r.f2;
r.f3 <= not r.f3;
r.f4 <= e;
r.f5 <= ea;
r_f6_loop: for i in r.f6'low to r.f6'high loop
r.f6(i) <= r.f6(i) + 1;
end loop r_f6_loop;
r.f7 <= r.f7(6 downto 0) & r.f7(7);
ra(ra'high) <= r;
ra_loop: for i in ra'high-1 downto 0 loop
ra(i) <= ra(i+1);
end loop;
end if;
end process;
process (clk2)
begin
if rising_edge(clk2) then
I_sa <= I_sa(I_sa'length-1) & I_sa(0 to I_sa'length-2);
elsif clk2'event and clk2 = '0' then
I_saa_loop_1: for i in 0 to 3 loop
I_saa_loop_2: for j in 1 to 4 loop
I_saa(i,j) <= I_sa(i+j);
end loop I_saa_loop_2;
end loop I_saa_loop_1;
I_baa_loop_1: for i in 0 to 3 loop
I_baa_loop_2: for j in 1 to 4 loop
I_baa(i,j) <= bv(i*j);
end loop I_baa_loop_2;
end loop I_baa_loop_1;
end if;
end process;
end ARCH00011_Test_Bench ; |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_fg_21_06.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity multiprocessor is
end entity multiprocessor;
-- code from book
architecture instrumented of multiprocessor is
-- not in book
constant num_processors : positive := 2;
-- end not in book
shared variable bus_ifetch_count,
bus_read_count,
bus_write_count : natural := 0;
signal bus_request, bus_grant : bit_vector(0 to num_processors - 1);
-- . . . -- other signal declarations
begin
processor_array :
for processor_id in 0 to num_processors - 1 generate
processor : process is
-- . . .
begin
-- . . . -- initialize
loop
bus_request(processor_id) <= '1';
wait until bus_grant(processor_id) = '1';
bus_ifetch_count := bus_ifetch_count + 1;
-- . . . -- fetch instruction
bus_request(processor_id) <= '0';
-- . . . -- decode and execute instruction
-- not in book
wait until bus_grant(processor_id) = '0';
-- end not in book
end loop;
end process processor;
end generate processor_array;
arbiter : process is
begin
-- . . .
-- not in book
loop
for i in bus_request'range loop
if bus_request(i) = '1' then
bus_grant(i) <= '1' after 5 ns;
wait until bus_request(i) = '0';
bus_grant(i) <= '0' after 5 ns;
end if;
end loop;
wait for 5 ns;
end loop;
-- end not in book
end process arbiter;
-- . . . -- other processes for memory, etc
end architecture instrumented;
-- end code from book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_fg_21_06.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity multiprocessor is
end entity multiprocessor;
-- code from book
architecture instrumented of multiprocessor is
-- not in book
constant num_processors : positive := 2;
-- end not in book
shared variable bus_ifetch_count,
bus_read_count,
bus_write_count : natural := 0;
signal bus_request, bus_grant : bit_vector(0 to num_processors - 1);
-- . . . -- other signal declarations
begin
processor_array :
for processor_id in 0 to num_processors - 1 generate
processor : process is
-- . . .
begin
-- . . . -- initialize
loop
bus_request(processor_id) <= '1';
wait until bus_grant(processor_id) = '1';
bus_ifetch_count := bus_ifetch_count + 1;
-- . . . -- fetch instruction
bus_request(processor_id) <= '0';
-- . . . -- decode and execute instruction
-- not in book
wait until bus_grant(processor_id) = '0';
-- end not in book
end loop;
end process processor;
end generate processor_array;
arbiter : process is
begin
-- . . .
-- not in book
loop
for i in bus_request'range loop
if bus_request(i) = '1' then
bus_grant(i) <= '1' after 5 ns;
wait until bus_request(i) = '0';
bus_grant(i) <= '0' after 5 ns;
end if;
end loop;
wait for 5 ns;
end loop;
-- end not in book
end process arbiter;
-- . . . -- other processes for memory, etc
end architecture instrumented;
-- end code from book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_fg_21_06.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity multiprocessor is
end entity multiprocessor;
-- code from book
architecture instrumented of multiprocessor is
-- not in book
constant num_processors : positive := 2;
-- end not in book
shared variable bus_ifetch_count,
bus_read_count,
bus_write_count : natural := 0;
signal bus_request, bus_grant : bit_vector(0 to num_processors - 1);
-- . . . -- other signal declarations
begin
processor_array :
for processor_id in 0 to num_processors - 1 generate
processor : process is
-- . . .
begin
-- . . . -- initialize
loop
bus_request(processor_id) <= '1';
wait until bus_grant(processor_id) = '1';
bus_ifetch_count := bus_ifetch_count + 1;
-- . . . -- fetch instruction
bus_request(processor_id) <= '0';
-- . . . -- decode and execute instruction
-- not in book
wait until bus_grant(processor_id) = '0';
-- end not in book
end loop;
end process processor;
end generate processor_array;
arbiter : process is
begin
-- . . .
-- not in book
loop
for i in bus_request'range loop
if bus_request(i) = '1' then
bus_grant(i) <= '1' after 5 ns;
wait until bus_request(i) = '0';
bus_grant(i) <= '0' after 5 ns;
end if;
end loop;
wait for 5 ns;
end loop;
-- end not in book
end process arbiter;
-- . . . -- other processes for memory, etc
end architecture instrumented;
-- end code from book
|
entity sub is
generic (
WIDTH : integer;
INIT : bit );
port (
x : out bit_vector(31 downto 0);
y : in bit_vector(WIDTH - 1 downto 0) );
end entity;
architecture test of sub is
signal y1 : bit_vector(WIDTH - 1 downto 0);
begin
x <= (31 downto WIDTH => '0') & y1;
y1 <= y;
end architecture;
-------------------------------------------------------------------------------
entity elab20 is
end entity;
architecture test of elab20 is
signal x : bit_vector(31 downto 0);
signal y : bit_vector(7 downto 0);
begin
process is
begin
y <= X"55";
wait for 1 ns;
assert x = X"00000055";
wait;
end process;
sub_i: entity work.sub
generic map (
WIDTH => 8,
INIT => '0' )
port map ( x, y );
end architecture;
|
entity sub is
generic (
WIDTH : integer;
INIT : bit );
port (
x : out bit_vector(31 downto 0);
y : in bit_vector(WIDTH - 1 downto 0) );
end entity;
architecture test of sub is
signal y1 : bit_vector(WIDTH - 1 downto 0);
begin
x <= (31 downto WIDTH => '0') & y1;
y1 <= y;
end architecture;
-------------------------------------------------------------------------------
entity elab20 is
end entity;
architecture test of elab20 is
signal x : bit_vector(31 downto 0);
signal y : bit_vector(7 downto 0);
begin
process is
begin
y <= X"55";
wait for 1 ns;
assert x = X"00000055";
wait;
end process;
sub_i: entity work.sub
generic map (
WIDTH => 8,
INIT => '0' )
port map ( x, y );
end architecture;
|
entity sub is
generic (
WIDTH : integer;
INIT : bit );
port (
x : out bit_vector(31 downto 0);
y : in bit_vector(WIDTH - 1 downto 0) );
end entity;
architecture test of sub is
signal y1 : bit_vector(WIDTH - 1 downto 0);
begin
x <= (31 downto WIDTH => '0') & y1;
y1 <= y;
end architecture;
-------------------------------------------------------------------------------
entity elab20 is
end entity;
architecture test of elab20 is
signal x : bit_vector(31 downto 0);
signal y : bit_vector(7 downto 0);
begin
process is
begin
y <= X"55";
wait for 1 ns;
assert x = X"00000055";
wait;
end process;
sub_i: entity work.sub
generic map (
WIDTH => 8,
INIT => '0' )
port map ( x, y );
end architecture;
|
entity sub is
generic (
WIDTH : integer;
INIT : bit );
port (
x : out bit_vector(31 downto 0);
y : in bit_vector(WIDTH - 1 downto 0) );
end entity;
architecture test of sub is
signal y1 : bit_vector(WIDTH - 1 downto 0);
begin
x <= (31 downto WIDTH => '0') & y1;
y1 <= y;
end architecture;
-------------------------------------------------------------------------------
entity elab20 is
end entity;
architecture test of elab20 is
signal x : bit_vector(31 downto 0);
signal y : bit_vector(7 downto 0);
begin
process is
begin
y <= X"55";
wait for 1 ns;
assert x = X"00000055";
wait;
end process;
sub_i: entity work.sub
generic map (
WIDTH => 8,
INIT => '0' )
port map ( x, y );
end architecture;
|
entity sub is
generic (
WIDTH : integer;
INIT : bit );
port (
x : out bit_vector(31 downto 0);
y : in bit_vector(WIDTH - 1 downto 0) );
end entity;
architecture test of sub is
signal y1 : bit_vector(WIDTH - 1 downto 0);
begin
x <= (31 downto WIDTH => '0') & y1;
y1 <= y;
end architecture;
-------------------------------------------------------------------------------
entity elab20 is
end entity;
architecture test of elab20 is
signal x : bit_vector(31 downto 0);
signal y : bit_vector(7 downto 0);
begin
process is
begin
y <= X"55";
wait for 1 ns;
assert x = X"00000055";
wait;
end process;
sub_i: entity work.sub
generic map (
WIDTH => 8,
INIT => '0' )
port map ( x, y );
end architecture;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dist_mem_gen_v8_0_9;
USE dist_mem_gen_v8_0_9.dist_mem_gen_v8_0_9;
ENTITY dist_mem_gen_0 IS
PORT (
a : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(1023 DOWNTO 0)
);
END dist_mem_gen_0;
ARCHITECTURE dist_mem_gen_0_arch OF dist_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dist_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT dist_mem_gen_v8_0_9 IS
GENERIC (
C_FAMILY : STRING;
C_ADDR_WIDTH : INTEGER;
C_DEFAULT_DATA : STRING;
C_DEPTH : INTEGER;
C_HAS_CLK : INTEGER;
C_HAS_D : INTEGER;
C_HAS_DPO : INTEGER;
C_HAS_DPRA : INTEGER;
C_HAS_I_CE : INTEGER;
C_HAS_QDPO : INTEGER;
C_HAS_QDPO_CE : INTEGER;
C_HAS_QDPO_CLK : INTEGER;
C_HAS_QDPO_RST : INTEGER;
C_HAS_QDPO_SRST : INTEGER;
C_HAS_QSPO : INTEGER;
C_HAS_QSPO_CE : INTEGER;
C_HAS_QSPO_RST : INTEGER;
C_HAS_QSPO_SRST : INTEGER;
C_HAS_SPO : INTEGER;
C_HAS_WE : INTEGER;
C_MEM_INIT_FILE : STRING;
C_ELABORATION_DIR : STRING;
C_MEM_TYPE : INTEGER;
C_PIPELINE_STAGES : INTEGER;
C_QCE_JOINED : INTEGER;
C_QUALIFY_WE : INTEGER;
C_READ_MIF : INTEGER;
C_REG_A_D_INPUTS : INTEGER;
C_REG_DPRA_INPUT : INTEGER;
C_SYNC_ENABLE : INTEGER;
C_WIDTH : INTEGER;
C_PARSER_TYPE : INTEGER
);
PORT (
a : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(1023 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
i_ce : IN STD_LOGIC;
qspo_ce : IN STD_LOGIC;
qdpo_ce : IN STD_LOGIC;
qdpo_clk : IN STD_LOGIC;
qspo_rst : IN STD_LOGIC;
qdpo_rst : IN STD_LOGIC;
qspo_srst : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(1023 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(1023 DOWNTO 0);
qspo : OUT STD_LOGIC_VECTOR(1023 DOWNTO 0);
qdpo : OUT STD_LOGIC_VECTOR(1023 DOWNTO 0)
);
END COMPONENT dist_mem_gen_v8_0_9;
BEGIN
U0 : dist_mem_gen_v8_0_9
GENERIC MAP (
C_FAMILY => "artix7",
C_ADDR_WIDTH => 12,
C_DEFAULT_DATA => "0",
C_DEPTH => 4096,
C_HAS_CLK => 0,
C_HAS_D => 0,
C_HAS_DPO => 0,
C_HAS_DPRA => 0,
C_HAS_I_CE => 0,
C_HAS_QDPO => 0,
C_HAS_QDPO_CE => 0,
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_RST => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_QSPO => 0,
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QSPO_SRST => 0,
C_HAS_SPO => 1,
C_HAS_WE => 0,
C_MEM_INIT_FILE => "dist_mem_gen_0.mif",
C_ELABORATION_DIR => "./",
C_MEM_TYPE => 0,
C_PIPELINE_STAGES => 0,
C_QCE_JOINED => 0,
C_QUALIFY_WE => 0,
C_READ_MIF => 1,
C_REG_A_D_INPUTS => 0,
C_REG_DPRA_INPUT => 0,
C_SYNC_ENABLE => 1,
C_WIDTH => 1024,
C_PARSER_TYPE => 1
)
PORT MAP (
a => a,
d => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1024)),
dpra => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
clk => '0',
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qspo_srst => '0',
qdpo_srst => '0',
spo => spo
);
END dist_mem_gen_0_arch;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_a_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_a_e-c.vhd,v 1.2 2005/07/15 16:20:01 wig Exp $
-- $Date: 2005/07/15 16:20:01 $
-- $Log: inst_shadow_a_e-c.vhd,v $
-- Revision 1.2 2005/07/15 16:20:01 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_shadow_a_rtl_conf / inst_shadow_a_e
--
configuration inst_shadow_a_rtl_conf of inst_shadow_a_e is
for rtl
-- Generated Configuration
end for;
end inst_shadow_a_rtl_conf;
--
-- End of Generated Configuration inst_shadow_a_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc380.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p04n01i00380ent IS
END c03s02b01x01p04n01i00380ent;
ARCHITECTURE c03s02b01x01p04n01i00380arch OF c03s02b01x01p04n01i00380ent IS
type bit_vctor is array (positive range -1 to 8) of integer;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p04n01i00380 - The index constraint values are not compatible with the corresponding subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p04n01i00380arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc380.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p04n01i00380ent IS
END c03s02b01x01p04n01i00380ent;
ARCHITECTURE c03s02b01x01p04n01i00380arch OF c03s02b01x01p04n01i00380ent IS
type bit_vctor is array (positive range -1 to 8) of integer;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p04n01i00380 - The index constraint values are not compatible with the corresponding subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p04n01i00380arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc380.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p04n01i00380ent IS
END c03s02b01x01p04n01i00380ent;
ARCHITECTURE c03s02b01x01p04n01i00380arch OF c03s02b01x01p04n01i00380ent IS
type bit_vctor is array (positive range -1 to 8) of integer;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p04n01i00380 - The index constraint values are not compatible with the corresponding subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p04n01i00380arch;
|
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|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8352)
`protect data_block
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8352)
`protect data_block
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1sg8s1nxvdJiU0DhaBsPlrCqHG/feXA7UgC7OIuf
`protect end_protected
|
library IEEE;
use IEEE.std_logic_1164.all;
library Examples;
use Examples.examples.all;
entity Top is
port (
clk_i : in std_logic;
led_o : out std_logic
);
end entity Top;
architecture Structural of Top is
constant FREQ : positive := 50e6;
begin
dut: Blinking
generic map (FREQ => FREQ, SECS => 1)
port map (clk_i => clk_i, led_o => led_o);
end architecture Structural;
|
library IEEE;
use IEEE.std_logic_1164.all;
library Examples;
use Examples.examples.all;
entity Top is
port (
clk_i : in std_logic;
led_o : out std_logic
);
end entity Top;
architecture Structural of Top is
constant FREQ : positive := 50e6;
begin
dut: Blinking
generic map (FREQ => FREQ, SECS => 1)
port map (clk_i => clk_i, led_o => led_o);
end architecture Structural;
|
library IEEE;
use IEEE.std_logic_1164.all;
library Examples;
use Examples.examples.all;
entity Top is
port (
clk_i : in std_logic;
led_o : out std_logic
);
end entity Top;
architecture Structural of Top is
constant FREQ : positive := 50e6;
begin
dut: Blinking
generic map (FREQ => FREQ, SECS => 1)
port map (clk_i => clk_i, led_o => led_o);
end architecture Structural;
|
library IEEE;
use IEEE.std_logic_1164.all;
library Examples;
use Examples.examples.all;
entity Top is
port (
clk_i : in std_logic;
led_o : out std_logic
);
end entity Top;
architecture Structural of Top is
constant FREQ : positive := 50e6;
begin
dut: Blinking
generic map (FREQ => FREQ, SECS => 1)
port map (clk_i => clk_i, led_o => led_o);
end architecture Structural;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
entity dmod is
generic(
width:integer := 16
);
port(
clk: in std_logic;
I: in std_logic_vector(width-1 downto 0);
Q: in std_logic_vector(width-1 downto 0);
output: out std_logic_vector(width-1 downto 0)
);
end dmod;
architecture Behavioral of dmod is
signal I_shift_reg: std_logic_vector(width*3-1 downto 0) := (others=>'0');
alias I_first : std_logic_vector(width-1 downto 0) is I_shift_reg(width*1-1 downto width*0);
alias I_mid : std_logic_vector(width-1 downto 0) is I_shift_reg(width*2-1 downto width*1);
alias I_last : std_logic_vector(width-1 downto 0) is I_shift_reg(width*3-1 downto width*2);
signal dI : std_logic_vector(width-1 downto 0) := (others=>'0');
signal Q_shift_reg: std_logic_vector(width*3-1 downto 0) := (others=>'0');
alias Q_first : std_logic_vector(width-1 downto 0) is Q_shift_reg(width*1-1 downto width*0);
alias Q_mid : std_logic_vector(width-1 downto 0) is Q_shift_reg(width*2-1 downto width*1);
alias Q_last : std_logic_vector(width-1 downto 0) is Q_shift_reg(width*3-1 downto width*2);
signal dQ : std_logic_vector(width-1 downto 0) := (others=>'0');
signal PQ_out, PI_out,scaled : std_logic_vector(31 downto 0) := (others=>'0');
-- alias Q_out : std_logic_vector(width-1 downto 0) is PQ_out(31 downto 31-width+1);
--alias I_out : std_logic_vector(width-1 downto 0) is PI_out(31 downto 31-width+1);
COMPONENT multi_QI
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
begin
dQ_I: multi_QI
PORT MAP (
CLK => clk,
A => dQ,
B => I_last,
P => PI_out
);
dI_Q: multi_QI
PORT MAP (
CLK => clk,
A => dI,
B => Q_last,
P => PQ_out
);
process(clk) begin
if(clk'event and clk = '1')then
I_shift_reg <= I_mid & I_first & I;
Q_shift_reg <= Q_mid & Q_first & Q;
dI <= I_last - I_first;
dQ <= Q_last - Q_first;
scaled <= std_logic_vector(signed(PQ_out) - signed(PI_out));
output <= scaled(31) & scaled(30 downto 30-14);
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: Digital Security Gorup - Faculty of Science - University of Radbound
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/02/2015
-- Design Name: TB_RAM
-- Module Name: TB_RAM
-- Project Name: Example
-- Target Devices: Any
-- Tool versions:
--
-- Description:
--
-- A simple test bench for the simple RAM
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
-- - Modified RAM to store 40*32 bits for the round keys (Jos Wetzels & Wouter Bokslag)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_ram is
Generic (
PERIOD : time := 10 ns
);
end tb_ram;
architecture Behavioral of tb_ram is
component ram
Port (
data_in : in STD_LOGIC_VECTOR(31 downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR(7 downto 0);
data_out : out STD_LOGIC_VECTOR(31 downto 0)
);
end component;
signal test_data_in : STD_LOGIC_VECTOR(31 downto 0);
signal test_rw : STD_LOGIC;
signal test_address : STD_LOGIC_VECTOR(7 downto 0);
signal test_data_out : STD_LOGIC_VECTOR(31 downto 0);
signal clk : STD_LOGIC := '0';
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
begin
test : ram
Port Map(
data_in => test_data_in,
rw => test_rw,
clk => clk,
address => test_address,
data_out => test_data_out
);
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
end loop;
wait;
end process;
process
begin
wait for PERIOD/2;
test_data_in <= X"03020100";
test_rw <= '1';
test_address <= X"00";
wait for PERIOD;
test_data_in <= X"0b0a0908";
test_rw <= '1';
test_address <= X"01";
wait for PERIOD;
test_data_in <= X"13121110";
test_rw <= '1';
test_address <= X"02";
wait for PERIOD;
test_data_in <= X"1b1a1918";
test_rw <= '1';
test_address <= X"03";
wait for PERIOD;
test_rw <= '0';
test_address <= X"00";
wait for PERIOD;
assert test_data_out = X"03020100" report "Error in RAM" severity FAILURE;
test_address <= X"01";
wait for PERIOD;
assert test_data_out = X"0b0a0908" report "Error in RAM" severity FAILURE;
test_address <= X"02";
wait for PERIOD;
assert test_data_out = X"13121110" report "Error in RAM" severity FAILURE;
test_address <= X"03";
wait for PERIOD;
assert test_data_out = X"1b1a1918" report "Error in RAM" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for PERIOD;
wait;
end process;
end Behavioral; |
----------------------------------------------------------------------------------
-- Company: Digital Security Gorup - Faculty of Science - University of Radbound
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/02/2015
-- Design Name: TB_RAM
-- Module Name: TB_RAM
-- Project Name: Example
-- Target Devices: Any
-- Tool versions:
--
-- Description:
--
-- A simple test bench for the simple RAM
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
-- - Modified RAM to store 40*32 bits for the round keys (Jos Wetzels & Wouter Bokslag)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_ram is
Generic (
PERIOD : time := 10 ns
);
end tb_ram;
architecture Behavioral of tb_ram is
component ram
Port (
data_in : in STD_LOGIC_VECTOR(31 downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR(7 downto 0);
data_out : out STD_LOGIC_VECTOR(31 downto 0)
);
end component;
signal test_data_in : STD_LOGIC_VECTOR(31 downto 0);
signal test_rw : STD_LOGIC;
signal test_address : STD_LOGIC_VECTOR(7 downto 0);
signal test_data_out : STD_LOGIC_VECTOR(31 downto 0);
signal clk : STD_LOGIC := '0';
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
begin
test : ram
Port Map(
data_in => test_data_in,
rw => test_rw,
clk => clk,
address => test_address,
data_out => test_data_out
);
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
end loop;
wait;
end process;
process
begin
wait for PERIOD/2;
test_data_in <= X"03020100";
test_rw <= '1';
test_address <= X"00";
wait for PERIOD;
test_data_in <= X"0b0a0908";
test_rw <= '1';
test_address <= X"01";
wait for PERIOD;
test_data_in <= X"13121110";
test_rw <= '1';
test_address <= X"02";
wait for PERIOD;
test_data_in <= X"1b1a1918";
test_rw <= '1';
test_address <= X"03";
wait for PERIOD;
test_rw <= '0';
test_address <= X"00";
wait for PERIOD;
assert test_data_out = X"03020100" report "Error in RAM" severity FAILURE;
test_address <= X"01";
wait for PERIOD;
assert test_data_out = X"0b0a0908" report "Error in RAM" severity FAILURE;
test_address <= X"02";
wait for PERIOD;
assert test_data_out = X"13121110" report "Error in RAM" severity FAILURE;
test_address <= X"03";
wait for PERIOD;
assert test_data_out = X"1b1a1918" report "Error in RAM" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for PERIOD;
wait;
end process;
end Behavioral; |
----------------------------------------------------------------------------------
-- Company: Digital Security Gorup - Faculty of Science - University of Radbound
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/02/2015
-- Design Name: TB_RAM
-- Module Name: TB_RAM
-- Project Name: Example
-- Target Devices: Any
-- Tool versions:
--
-- Description:
--
-- A simple test bench for the simple RAM
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
-- - Modified RAM to store 40*32 bits for the round keys (Jos Wetzels & Wouter Bokslag)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_ram is
Generic (
PERIOD : time := 10 ns
);
end tb_ram;
architecture Behavioral of tb_ram is
component ram
Port (
data_in : in STD_LOGIC_VECTOR(31 downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR(7 downto 0);
data_out : out STD_LOGIC_VECTOR(31 downto 0)
);
end component;
signal test_data_in : STD_LOGIC_VECTOR(31 downto 0);
signal test_rw : STD_LOGIC;
signal test_address : STD_LOGIC_VECTOR(7 downto 0);
signal test_data_out : STD_LOGIC_VECTOR(31 downto 0);
signal clk : STD_LOGIC := '0';
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
begin
test : ram
Port Map(
data_in => test_data_in,
rw => test_rw,
clk => clk,
address => test_address,
data_out => test_data_out
);
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
end loop;
wait;
end process;
process
begin
wait for PERIOD/2;
test_data_in <= X"03020100";
test_rw <= '1';
test_address <= X"00";
wait for PERIOD;
test_data_in <= X"0b0a0908";
test_rw <= '1';
test_address <= X"01";
wait for PERIOD;
test_data_in <= X"13121110";
test_rw <= '1';
test_address <= X"02";
wait for PERIOD;
test_data_in <= X"1b1a1918";
test_rw <= '1';
test_address <= X"03";
wait for PERIOD;
test_rw <= '0';
test_address <= X"00";
wait for PERIOD;
assert test_data_out = X"03020100" report "Error in RAM" severity FAILURE;
test_address <= X"01";
wait for PERIOD;
assert test_data_out = X"0b0a0908" report "Error in RAM" severity FAILURE;
test_address <= X"02";
wait for PERIOD;
assert test_data_out = X"13121110" report "Error in RAM" severity FAILURE;
test_address <= X"03";
wait for PERIOD;
assert test_data_out = X"1b1a1918" report "Error in RAM" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for PERIOD;
wait;
end process;
end Behavioral; |
----------------------------------------------------------------------------------
-- Company: Digital Security Gorup - Faculty of Science - University of Radbound
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/02/2015
-- Design Name: TB_RAM
-- Module Name: TB_RAM
-- Project Name: Example
-- Target Devices: Any
-- Tool versions:
--
-- Description:
--
-- A simple test bench for the simple RAM
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
-- - Modified RAM to store 40*32 bits for the round keys (Jos Wetzels & Wouter Bokslag)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_ram is
Generic (
PERIOD : time := 10 ns
);
end tb_ram;
architecture Behavioral of tb_ram is
component ram
Port (
data_in : in STD_LOGIC_VECTOR(31 downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR(7 downto 0);
data_out : out STD_LOGIC_VECTOR(31 downto 0)
);
end component;
signal test_data_in : STD_LOGIC_VECTOR(31 downto 0);
signal test_rw : STD_LOGIC;
signal test_address : STD_LOGIC_VECTOR(7 downto 0);
signal test_data_out : STD_LOGIC_VECTOR(31 downto 0);
signal clk : STD_LOGIC := '0';
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
begin
test : ram
Port Map(
data_in => test_data_in,
rw => test_rw,
clk => clk,
address => test_address,
data_out => test_data_out
);
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
end loop;
wait;
end process;
process
begin
wait for PERIOD/2;
test_data_in <= X"03020100";
test_rw <= '1';
test_address <= X"00";
wait for PERIOD;
test_data_in <= X"0b0a0908";
test_rw <= '1';
test_address <= X"01";
wait for PERIOD;
test_data_in <= X"13121110";
test_rw <= '1';
test_address <= X"02";
wait for PERIOD;
test_data_in <= X"1b1a1918";
test_rw <= '1';
test_address <= X"03";
wait for PERIOD;
test_rw <= '0';
test_address <= X"00";
wait for PERIOD;
assert test_data_out = X"03020100" report "Error in RAM" severity FAILURE;
test_address <= X"01";
wait for PERIOD;
assert test_data_out = X"0b0a0908" report "Error in RAM" severity FAILURE;
test_address <= X"02";
wait for PERIOD;
assert test_data_out = X"13121110" report "Error in RAM" severity FAILURE;
test_address <= X"03";
wait for PERIOD;
assert test_data_out = X"1b1a1918" report "Error in RAM" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for PERIOD;
wait;
end process;
end Behavioral; |
----------------------------------------------------------------------------------
-- Company: Digital Security Gorup - Faculty of Science - University of Radbound
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/02/2015
-- Design Name: TB_RAM
-- Module Name: TB_RAM
-- Project Name: Example
-- Target Devices: Any
-- Tool versions:
--
-- Description:
--
-- A simple test bench for the simple RAM
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
-- - Modified RAM to store 40*32 bits for the round keys (Jos Wetzels & Wouter Bokslag)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_ram is
Generic (
PERIOD : time := 10 ns
);
end tb_ram;
architecture Behavioral of tb_ram is
component ram
Port (
data_in : in STD_LOGIC_VECTOR(31 downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR(7 downto 0);
data_out : out STD_LOGIC_VECTOR(31 downto 0)
);
end component;
signal test_data_in : STD_LOGIC_VECTOR(31 downto 0);
signal test_rw : STD_LOGIC;
signal test_address : STD_LOGIC_VECTOR(7 downto 0);
signal test_data_out : STD_LOGIC_VECTOR(31 downto 0);
signal clk : STD_LOGIC := '0';
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
begin
test : ram
Port Map(
data_in => test_data_in,
rw => test_rw,
clk => clk,
address => test_address,
data_out => test_data_out
);
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
end loop;
wait;
end process;
process
begin
wait for PERIOD/2;
test_data_in <= X"03020100";
test_rw <= '1';
test_address <= X"00";
wait for PERIOD;
test_data_in <= X"0b0a0908";
test_rw <= '1';
test_address <= X"01";
wait for PERIOD;
test_data_in <= X"13121110";
test_rw <= '1';
test_address <= X"02";
wait for PERIOD;
test_data_in <= X"1b1a1918";
test_rw <= '1';
test_address <= X"03";
wait for PERIOD;
test_rw <= '0';
test_address <= X"00";
wait for PERIOD;
assert test_data_out = X"03020100" report "Error in RAM" severity FAILURE;
test_address <= X"01";
wait for PERIOD;
assert test_data_out = X"0b0a0908" report "Error in RAM" severity FAILURE;
test_address <= X"02";
wait for PERIOD;
assert test_data_out = X"13121110" report "Error in RAM" severity FAILURE;
test_address <= X"03";
wait for PERIOD;
assert test_data_out = X"1b1a1918" report "Error in RAM" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for PERIOD;
wait;
end process;
end Behavioral; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2300.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p35n01i02300ent IS
END c07s02b06x00p35n01i02300ent;
ARCHITECTURE c07s02b06x00p35n01i02300arch OF c07s02b06x00p35n01i02300ent IS
BEGIN
TESTING: PROCESS
BEGIN
-- Test the predefined type TIME in this respect.
assert ((1 sec / 1000.0) < 1 sec);
assert ((1 ms / 1000.0) < 1 ms);
assert ((1 us / 1000.0) < 1 us);
wait for 5 us;
assert NOT( ((1 sec / 1000.0) < 1 sec) and
((1 ms / 1000.0) < 1 ms) and
((1 us / 1000.0) < 1 us) )
report "***PASSED TEST: c07s02b06x00p35n01i02300"
severity NOTE;
assert ( ((1 sec / 1000.0) < 1 sec) and
((1 ms / 1000.0) < 1 ms) and
((1 us / 1000.0) < 1 us) )
report "***FAILED TEST: c07s02b06x00p35n01i02300 - Division of an predefined physical type by a real type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p35n01i02300arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2300.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p35n01i02300ent IS
END c07s02b06x00p35n01i02300ent;
ARCHITECTURE c07s02b06x00p35n01i02300arch OF c07s02b06x00p35n01i02300ent IS
BEGIN
TESTING: PROCESS
BEGIN
-- Test the predefined type TIME in this respect.
assert ((1 sec / 1000.0) < 1 sec);
assert ((1 ms / 1000.0) < 1 ms);
assert ((1 us / 1000.0) < 1 us);
wait for 5 us;
assert NOT( ((1 sec / 1000.0) < 1 sec) and
((1 ms / 1000.0) < 1 ms) and
((1 us / 1000.0) < 1 us) )
report "***PASSED TEST: c07s02b06x00p35n01i02300"
severity NOTE;
assert ( ((1 sec / 1000.0) < 1 sec) and
((1 ms / 1000.0) < 1 ms) and
((1 us / 1000.0) < 1 us) )
report "***FAILED TEST: c07s02b06x00p35n01i02300 - Division of an predefined physical type by a real type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p35n01i02300arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2300.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p35n01i02300ent IS
END c07s02b06x00p35n01i02300ent;
ARCHITECTURE c07s02b06x00p35n01i02300arch OF c07s02b06x00p35n01i02300ent IS
BEGIN
TESTING: PROCESS
BEGIN
-- Test the predefined type TIME in this respect.
assert ((1 sec / 1000.0) < 1 sec);
assert ((1 ms / 1000.0) < 1 ms);
assert ((1 us / 1000.0) < 1 us);
wait for 5 us;
assert NOT( ((1 sec / 1000.0) < 1 sec) and
((1 ms / 1000.0) < 1 ms) and
((1 us / 1000.0) < 1 us) )
report "***PASSED TEST: c07s02b06x00p35n01i02300"
severity NOTE;
assert ( ((1 sec / 1000.0) < 1 sec) and
((1 ms / 1000.0) < 1 ms) and
((1 us / 1000.0) < 1 us) )
report "***FAILED TEST: c07s02b06x00p35n01i02300 - Division of an predefined physical type by a real type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p35n01i02300arch;
|
entity bounds21 is
end entity;
architecture test of bounds21 is
type boolean_v is array (integer range <>) of boolean;
subtype boolean_4 is boolean_v (1 to 4);
subtype boolean_7 is boolean_v (1 to 7);
function return_array return boolean_4 is
constant l_operand : boolean_4 := (true,false,true,false);
begin
return l_operand;
end return_array;
begin
l : block
generic ( info : boolean_7 );
generic map ( return_array & return_array );
begin
assert not(info = (true,false,true,false,true,false,true,false))
report "***passed test: c07s02b04x00p20n01i02094"
severity note;
assert (info = (true,false,true,false,true,false,true,false))
report "***failed test: c07s02b04x00p20n01i02094 - function array concatenation did not succeed."
severity error;
end block;
end architecture;
|
architecture RTL of FIFO is
begin
process
begin
LOOP_LABEL : loop
end loop;
-- Violations below
LOOP_LABEL : loop
end loop;
end process;
end;
|
------------------------------------------------------------------------------
-- matrixmultiplier - entity/architecture pair
------------------------------------------------------------------------------
-- Filename: matrixmultiplier
-- Version: 2.00.a
-- Description: matrix multiplier(VHDL).
-- Date: Wed June 7 16:32:00 2013
-- VHDL Standard: VHDL'93
-- Author: Achim Loesch
------------------------------------------------------------------------------
-- Feel free to modify this file.
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity matrixmultiplier is
generic (
G_LINE_LEN_MATRIX : integer := 128;
G_RAM_DATA_WIDTH : integer := 32;
G_RAM_SIZE_MATRIX_A_C : integer := 128;
G_RAM_ADDR_WIDTH_MATRIX_A_C : integer := 7;
G_RAM_SIZE_MATRIX_B : integer := 16384;
G_RAM_ADDR_WIDTH_MATRIX_B : integer := 14
);
port(
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
done : out std_logic;
o_RAM_A_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
i_RAM_A_Data : in std_logic_vector(0 to 31);
o_RAM_B_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_B - 1);
i_RAM_B_Data : in std_logic_vector(0 to 31);
o_RAM_C_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
o_RAM_C_Data : out std_logic_vector(0 to 31);
o_RAM_C_WE : out std_logic
);
--attribute USE_DSP48 : string;
--attribute USE_DSP48 of matrixmultiplier : entity is "no";
end matrixmultiplier;
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
architecture Behavioral of matrixmultiplier is
type STATE_TYPE is (
STATE_IDLE,
STATE_LOAD,
STATE_LOAD_WAIT,
STATE_SUM,
STATE_DELAY_1,
STATE_DELAY_2,
STATE_STORE,
STATE_STORE_WAIT,
STATE_FINISH_CYCLE
);
signal state : STATE_TYPE;
signal temp : std_logic_vector(0 to G_RAM_DATA_WIDTH-1);
signal prod,delay : std_logic_vector(0 to G_RAM_DATA_WIDTH-1);
begin
multiply : process(clk, reset, start) is
variable j : integer := 0;
variable k : integer := 0;
begin
if (reset = '1') then
done <= '0';
o_RAM_A_Addr <= (others=>'0');
o_RAM_B_Addr <= (others=>'0');
o_RAM_C_Addr <= (others=>'0');
o_RAM_C_Data <= (others=>'0');
o_RAM_C_WE <= '0';
state <= STATE_IDLE;
elsif (clk'event and clk = '1') then
o_RAM_C_WE <= '0';
o_RAM_C_Data <= (others=>'0');
case state is
when STATE_IDLE =>
done <= '0';
if (start = '1') then
j := 0;
k := 0;
temp <= (others=>'0');
state <= STATE_LOAD;
end if;
when STATE_LOAD =>
o_RAM_A_Addr <= conv_std_logic_vector(integer(k), G_RAM_ADDR_WIDTH_MATRIX_A_C);
o_RAM_B_Addr <= conv_std_logic_vector(integer(k*G_LINE_LEN_MATRIX+j), G_RAM_ADDR_WIDTH_MATRIX_B);
k := k + 1;
state <= STATE_LOAD_WAIT;
when STATE_LOAD_WAIT =>
state <= STATE_DELAY_1;
when STATE_DELAY_1 =>
state <= STATE_DELAY_2;
when STATE_DELAY_2 =>
state <= STATE_SUM;
when STATE_SUM =>
temp <= temp + prod;
if (k = G_LINE_LEN_MATRIX) then
k := 0;
state <= STATE_STORE;
else
state <= STATE_LOAD;
end if;
when STATE_STORE =>
o_RAM_C_Addr <= conv_std_logic_vector(integer(j), G_RAM_ADDR_WIDTH_MATRIX_A_C);
o_RAM_C_WE <= '1';
o_RAM_C_Data <= temp;
state <= STATE_STORE_WAIT;
when STATE_STORE_WAIT =>
o_RAM_C_WE <= '0';
state <= STATE_FINISH_CYCLE;
when STATE_FINISH_CYCLE =>
j := j + 1;
if (j = G_LINE_LEN_MATRIX) then
j := 0;
done <= '1';
state <= STATE_IDLE;
else
temp <= (others => '0');
state <= STATE_LOAD;
end if;
end case;
end if;
end process;
process (clk)
begin
if clk'event and clk = '1' then
delay <= conv_std_logic_vector(signed(i_RAM_A_Data)*signed(i_RAM_B_Data),G_RAM_DATA_WIDTH);
prod <= delay;
end if;
end process;
end Behavioral;
|
------------------------------------------------------------------------------
-- matrixmultiplier - entity/architecture pair
------------------------------------------------------------------------------
-- Filename: matrixmultiplier
-- Version: 2.00.a
-- Description: matrix multiplier(VHDL).
-- Date: Wed June 7 16:32:00 2013
-- VHDL Standard: VHDL'93
-- Author: Achim Loesch
------------------------------------------------------------------------------
-- Feel free to modify this file.
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity matrixmultiplier is
generic (
G_LINE_LEN_MATRIX : integer := 128;
G_RAM_DATA_WIDTH : integer := 32;
G_RAM_SIZE_MATRIX_A_C : integer := 128;
G_RAM_ADDR_WIDTH_MATRIX_A_C : integer := 7;
G_RAM_SIZE_MATRIX_B : integer := 16384;
G_RAM_ADDR_WIDTH_MATRIX_B : integer := 14
);
port(
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
done : out std_logic;
o_RAM_A_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
i_RAM_A_Data : in std_logic_vector(0 to 31);
o_RAM_B_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_B - 1);
i_RAM_B_Data : in std_logic_vector(0 to 31);
o_RAM_C_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
o_RAM_C_Data : out std_logic_vector(0 to 31);
o_RAM_C_WE : out std_logic
);
--attribute USE_DSP48 : string;
--attribute USE_DSP48 of matrixmultiplier : entity is "no";
end matrixmultiplier;
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
architecture Behavioral of matrixmultiplier is
type STATE_TYPE is (
STATE_IDLE,
STATE_LOAD,
STATE_LOAD_WAIT,
STATE_SUM,
STATE_DELAY_1,
STATE_DELAY_2,
STATE_STORE,
STATE_STORE_WAIT,
STATE_FINISH_CYCLE
);
signal state : STATE_TYPE;
signal temp : std_logic_vector(0 to G_RAM_DATA_WIDTH-1);
signal prod,delay : std_logic_vector(0 to G_RAM_DATA_WIDTH-1);
begin
multiply : process(clk, reset, start) is
variable j : integer := 0;
variable k : integer := 0;
begin
if (reset = '1') then
done <= '0';
o_RAM_A_Addr <= (others=>'0');
o_RAM_B_Addr <= (others=>'0');
o_RAM_C_Addr <= (others=>'0');
o_RAM_C_Data <= (others=>'0');
o_RAM_C_WE <= '0';
state <= STATE_IDLE;
elsif (clk'event and clk = '1') then
o_RAM_C_WE <= '0';
o_RAM_C_Data <= (others=>'0');
case state is
when STATE_IDLE =>
done <= '0';
if (start = '1') then
j := 0;
k := 0;
temp <= (others=>'0');
state <= STATE_LOAD;
end if;
when STATE_LOAD =>
o_RAM_A_Addr <= conv_std_logic_vector(integer(k), G_RAM_ADDR_WIDTH_MATRIX_A_C);
o_RAM_B_Addr <= conv_std_logic_vector(integer(k*G_LINE_LEN_MATRIX+j), G_RAM_ADDR_WIDTH_MATRIX_B);
k := k + 1;
state <= STATE_LOAD_WAIT;
when STATE_LOAD_WAIT =>
state <= STATE_DELAY_1;
when STATE_DELAY_1 =>
state <= STATE_DELAY_2;
when STATE_DELAY_2 =>
state <= STATE_SUM;
when STATE_SUM =>
temp <= temp + prod;
if (k = G_LINE_LEN_MATRIX) then
k := 0;
state <= STATE_STORE;
else
state <= STATE_LOAD;
end if;
when STATE_STORE =>
o_RAM_C_Addr <= conv_std_logic_vector(integer(j), G_RAM_ADDR_WIDTH_MATRIX_A_C);
o_RAM_C_WE <= '1';
o_RAM_C_Data <= temp;
state <= STATE_STORE_WAIT;
when STATE_STORE_WAIT =>
o_RAM_C_WE <= '0';
state <= STATE_FINISH_CYCLE;
when STATE_FINISH_CYCLE =>
j := j + 1;
if (j = G_LINE_LEN_MATRIX) then
j := 0;
done <= '1';
state <= STATE_IDLE;
else
temp <= (others => '0');
state <= STATE_LOAD;
end if;
end case;
end if;
end process;
process (clk)
begin
if clk'event and clk = '1' then
delay <= conv_std_logic_vector(signed(i_RAM_A_Data)*signed(i_RAM_B_Data),G_RAM_DATA_WIDTH);
prod <= delay;
end if;
end process;
end Behavioral;
|
library IEEE;
use ieee.std_logic_1164.all;
entity memory_data_register is
port(
input : in std_logic_vector(31 downto 0);
clk, rst, pre, ce : in std_logic;
output : out std_logic_vector(31 downto 0)
);
end memory_data_register;
architecture behav of memory_data_register is
begin
Mem : entity work.thirty_two_bit_register(behav) port map(input, clk, rst, pre, ce, output);
end behav; |
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v3_30_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity system_xadc_wiz_0_0_soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end system_xadc_wiz_0_0_soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of system_xadc_wiz_0_0_soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
-- A6500 - 6502 CPU and variants
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or any later version.
--
-- A2601 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with A2601. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bcd_fixup is
port(a: in unsigned(4 downto 0);
o: out unsigned(4 downto 0);
add: in std_logic);
end bcd_fixup;
architecture arch of bcd_fixup is
signal add_o: unsigned(4 downto 0);
signal sub_o: unsigned(4 downto 0);
begin
with a select add_o <=
"00000" when "00000",
"00001" when "00001",
"00010" when "00010",
"00011" when "00011",
"00100" when "00100",
"00101" when "00101",
"00110" when "00110",
"00111" when "00111",
"01000" when "01000",
"01001" when "01001",
"10000" when "01010",
"10001" when "01011",
"10010" when "01100",
"10011" when "01101",
"10100" when "01110",
"10101" when "01111",
"10110" when "10000",
"10111" when "10001",
"11000" when "10010",
"11001" when "10011",
"XXXXX" when others;
with a select sub_o <=
"00000" when "00110",
"00001" when "00111",
"00010" when "01000",
"00011" when "01001",
"00100" when "01010",
"00101" when "01011",
"00110" when "01100",
"00111" when "01101",
"01000" when "01110",
"01001" when "01111",
"10000" when "10000",
"10001" when "10001",
"10010" when "10010",
"10011" when "10011",
"10100" when "10100",
"10101" when "10101",
"10110" when "10110",
"10111" when "10111",
"11000" when "11000",
"11001" when "11001",
"XXXXX" when others;
o <= add_o when add = '1' else sub_o;
end arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.types.all;
entity ALU is
Port(a: in std_logic_vector (7 downto 0);
b: in std_logic_vector (7 downto 0);
o: out std_logic_vector (7 downto 0);
c_in: in std_logic;
c_out: out std_logic;
z: out std_logic;
n: out std_logic;
v: out std_logic;
fn: in alu_fn;
bcd: in std_logic);
end ALU;
architecture arch of ALU is
component bcd_fixup is
port(a: in unsigned(4 downto 0);
o: out unsigned(4 downto 0);
add: in std_logic);
end component bcd_fixup;
signal full_sum: std_logic_vector(8 downto 0);
signal sum: std_logic_vector(7 downto 0);
signal res: std_logic_vector(7 downto 0);
signal res_nz: std_logic_vector(7 downto 0);
signal adder_b: std_logic_vector(7 downto 0);
signal adder_c_in: std_logic;
signal adder_c_out: std_logic;
signal adder_bcd: std_logic;
signal sum_lo: unsigned(4 downto 0);
signal sum_hi: unsigned(4 downto 0);
signal fixed_sum_lo: unsigned(4 downto 0);
signal fixed_sum_hi: unsigned(4 downto 0);
signal sum_bcd_lo: unsigned(4 downto 0);
signal sum_bcd_hi: unsigned(4 downto 0);
signal fixup_add: std_logic;
begin
with fn select fixup_add <=
'1' when "0011",
'0' when "0111",
'-' when others;
bcd_fixup_lo: bcd_fixup port map(sum_lo, sum_bcd_lo, fixup_add);
bcd_fixup_hi: bcd_fixup port map(sum_hi, sum_bcd_hi, fixup_add);
-- The adder is divided into two to get the half-carry required for BCD fixup.
sum_lo <= unsigned("0" & a(3 downto 0)) +
unsigned("0" & adder_b(3 downto 0)) +
(unsigned'("0000") & adder_c_in);
fixed_sum_lo <= sum_lo when adder_bcd = '0' else sum_bcd_lo;
sum_hi <= unsigned("0" & a(7 downto 4)) +
unsigned("0" & adder_b(7 downto 4)) +
(unsigned'("0000") & fixed_sum_lo(4));
fixed_sum_hi <= sum_hi when adder_bcd = '0' else sum_bcd_hi;
full_sum <= std_logic_vector(fixed_sum_hi & fixed_sum_lo(3 downto 0));
sum <= full_sum(7 downto 0);
adder_c_out <= full_sum(8);
-- The following is due to not having access to carrys from the adder
v <= (a(7) xnor adder_b(7)) and (a(7) xor full_sum(7));
o <= res;
res_nz <= full_sum(7 downto 0) when (adder_bcd = '1') and (bcd = '1') else res;
n <= res_nz(7);
z <= '1' when (res_nz = "00000000") else '0';
with fn select res <=
(a or b) when "0000", -- OR
(a and b) when "0001", -- AND
(a xor b) when "0010", -- XOR
(sum) when "0011", -- ADC
(a) when "0100", -- ST(A)
(b) when "0101", -- LD(A) -- b is connected to memory
(sum) when "0110", -- CMP
(sum) when "0111", -- SBC
(a(6 downto 0) & '0') when "1000", -- ASL
(a(6 downto 0) & c_in) when "1001", -- ROL
('0' & a(7 downto 1)) when "1010", -- LSR
(c_in & a(7 downto 1)) when "1011", -- ROR
(a) when "1100", -- ST(X)
(sum) when "1101", -- ADD
(sum) when "1110", -- DEC
(sum) when "1111", -- INC
"--------" when others;
with fn select c_out <=
(adder_c_out) when "0011", -- ADC
(adder_c_out) when "0110", -- CMP -- CHECK
(adder_c_out) when "0111", -- SBC -- CHECK
(a(7)) when "1000", -- ASL
(a(7)) when "1001", -- ROL
(a(0)) when "1010", -- LSR
(a(0)) when "1011", -- ROR
(adder_c_out) when "1101", -- ADD
'-' when others;
with fn select adder_bcd <=
(bcd) when "0011", -- ADC
'0' when "0110", -- CMP
(bcd) when "0111", -- SBC
'0' when "1101", -- ADD
'0' when "1110", -- DEC
'0' when "1111", -- INC
'-' when others;
with fn select adder_c_in <=
(c_in) when "0011", -- ADC
'1' when "0110", -- CMP
(c_in) when "0111", -- SBC
'0' when "1101", -- ADD
'0' when "1110", -- DEC
'1' when "1111", -- INC
'-' when others;
with fn select adder_b <=
(b) when "0011", -- ADC
(not b) when "0110", -- CMP
(not b) when "0111", -- SBC
(b) when "1101", -- ADD
"11111111" when "1110", -- DEC
"00000000" when "1111", -- INC
"--------" when others;
end arch;
|
entity tb_dpram2w is
end tb_dpram2w;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dpram2w is
signal waddr : natural range 0 to 3;
signal wnib : natural range 0 to 1;
signal wdat : std_logic_vector (3 downto 0);
signal raddr : natural range 0 to 3;
signal rdat : std_logic_vector(7 downto 0);
signal clk : std_logic;
begin
dut: entity work.dpram2w
port map (waddr => waddr, wnib => wnib, wdat => wdat,
raddr => raddr, rdat => rdat,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
waddr <= 0;
wnib <= 0;
wdat <= x"0";
raddr <= 1;
pulse;
waddr <= 0;
wnib <= 1;
wdat <= x"f";
raddr <= 1;
pulse;
waddr <= 1;
wnib <= 1;
wdat <= x"e";
raddr <= 0;
pulse;
assert rdat = x"f0" severity failure;
waddr <= 1;
wnib <= 0;
wdat <= x"1";
raddr <= 0;
pulse;
assert rdat = x"f0" severity failure;
waddr <= 3;
wnib <= 0;
wdat <= x"3";
raddr <= 1;
pulse;
assert rdat = x"e1" severity failure;
waddr <= 3;
wnib <= 1;
wdat <= x"c";
raddr <= 1;
pulse;
assert rdat = x"e1" severity failure;
waddr <= 2;
wnib <= 1;
wdat <= x"d";
raddr <= 3;
pulse;
assert rdat = x"c3" severity failure;
waddr <= 2;
wnib <= 0;
wdat <= x"2";
raddr <= 3;
pulse;
assert rdat = x"c3" severity failure;
waddr <= 1;
wnib <= 0;
wdat <= x"1";
raddr <= 2;
pulse;
assert rdat = x"d2" severity failure;
wait;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
package pkg_6502_defs is
subtype t_amux is integer range 0 to 3;
constant c_amux_vector : t_amux := 0;
constant c_amux_addr : t_amux := 1;
constant c_amux_stack : t_amux := 2;
constant c_amux_pc : t_amux := 3;
type t_pc_oper is (keep, increment, copy, from_alu);
type t_adl_oper is (keep, increment, add_idx, load_bus, copy_dreg);
type t_adh_oper is (keep, increment, clear, load_bus);
type t_sp_oper is (keep, increment, decrement);
type t_dout_mux is (reg_d, reg_accu, reg_axy, reg_flags, reg_pcl, reg_pch, shift_res);
end;
|
library ieee;
use ieee.std_logic_1164.all;
package pkg_6502_defs is
subtype t_amux is integer range 0 to 3;
constant c_amux_vector : t_amux := 0;
constant c_amux_addr : t_amux := 1;
constant c_amux_stack : t_amux := 2;
constant c_amux_pc : t_amux := 3;
type t_pc_oper is (keep, increment, copy, from_alu);
type t_adl_oper is (keep, increment, add_idx, load_bus, copy_dreg);
type t_adh_oper is (keep, increment, clear, load_bus);
type t_sp_oper is (keep, increment, decrement);
type t_dout_mux is (reg_d, reg_accu, reg_axy, reg_flags, reg_pcl, reg_pch, shift_res);
end;
|
library ieee;
use ieee.std_logic_1164.all;
package pkg_6502_defs is
subtype t_amux is integer range 0 to 3;
constant c_amux_vector : t_amux := 0;
constant c_amux_addr : t_amux := 1;
constant c_amux_stack : t_amux := 2;
constant c_amux_pc : t_amux := 3;
type t_pc_oper is (keep, increment, copy, from_alu);
type t_adl_oper is (keep, increment, add_idx, load_bus, copy_dreg);
type t_adh_oper is (keep, increment, clear, load_bus);
type t_sp_oper is (keep, increment, decrement);
type t_dout_mux is (reg_d, reg_accu, reg_axy, reg_flags, reg_pcl, reg_pch, shift_res);
end;
|
library ieee;
use ieee.std_logic_1164.all;
package pkg_6502_defs is
subtype t_amux is integer range 0 to 3;
constant c_amux_vector : t_amux := 0;
constant c_amux_addr : t_amux := 1;
constant c_amux_stack : t_amux := 2;
constant c_amux_pc : t_amux := 3;
type t_pc_oper is (keep, increment, copy, from_alu);
type t_adl_oper is (keep, increment, add_idx, load_bus, copy_dreg);
type t_adh_oper is (keep, increment, clear, load_bus);
type t_sp_oper is (keep, increment, decrement);
type t_dout_mux is (reg_d, reg_accu, reg_axy, reg_flags, reg_pcl, reg_pch, shift_res);
end;
|
library ieee;
use ieee.std_logic_1164.all;
package pkg_6502_defs is
subtype t_amux is integer range 0 to 3;
constant c_amux_vector : t_amux := 0;
constant c_amux_addr : t_amux := 1;
constant c_amux_stack : t_amux := 2;
constant c_amux_pc : t_amux := 3;
type t_pc_oper is (keep, increment, copy, from_alu);
type t_adl_oper is (keep, increment, add_idx, load_bus, copy_dreg);
type t_adh_oper is (keep, increment, clear, load_bus);
type t_sp_oper is (keep, increment, decrement);
type t_dout_mux is (reg_d, reg_accu, reg_axy, reg_flags, reg_pcl, reg_pch, shift_res);
end;
|
library ieee;
use ieee.std_logic_1164.all;
package pkg_6502_defs is
subtype t_amux is integer range 0 to 3;
constant c_amux_vector : t_amux := 0;
constant c_amux_addr : t_amux := 1;
constant c_amux_stack : t_amux := 2;
constant c_amux_pc : t_amux := 3;
type t_pc_oper is (keep, increment, copy, from_alu);
type t_adl_oper is (keep, increment, add_idx, load_bus, copy_dreg);
type t_adh_oper is (keep, increment, clear, load_bus);
type t_sp_oper is (keep, increment, decrement);
type t_dout_mux is (reg_d, reg_accu, reg_axy, reg_flags, reg_pcl, reg_pch, shift_res);
end;
|
library verilog;
use verilog.vl_types.all;
entity BFM_AHBL is
generic(
VECTFILE : string := "test.vec";
MAX_INSTRUCTIONS: integer := 16384;
MAX_STACK : integer := 1024;
MAX_MEMTEST : integer := 65536;
TPD : integer := 1;
DEBUGLEVEL : integer := -1;
ARGVALUE0 : integer := 0;
ARGVALUE1 : integer := 0;
ARGVALUE2 : integer := 0;
ARGVALUE3 : integer := 0;
ARGVALUE4 : integer := 0;
ARGVALUE5 : integer := 0;
ARGVALUE6 : integer := 0;
ARGVALUE7 : integer := 0;
ARGVALUE8 : integer := 0;
ARGVALUE9 : integer := 0;
ARGVALUE10 : integer := 0;
ARGVALUE11 : integer := 0;
ARGVALUE12 : integer := 0;
ARGVALUE13 : integer := 0;
ARGVALUE14 : integer := 0;
ARGVALUE15 : integer := 0;
ARGVALUE16 : integer := 0;
ARGVALUE17 : integer := 0;
ARGVALUE18 : integer := 0;
ARGVALUE19 : integer := 0;
ARGVALUE20 : integer := 0;
ARGVALUE21 : integer := 0;
ARGVALUE22 : integer := 0;
ARGVALUE23 : integer := 0;
ARGVALUE24 : integer := 0;
ARGVALUE25 : integer := 0;
ARGVALUE26 : integer := 0;
ARGVALUE27 : integer := 0;
ARGVALUE28 : integer := 0;
ARGVALUE29 : integer := 0;
ARGVALUE30 : integer := 0;
ARGVALUE31 : integer := 0;
ARGVALUE32 : integer := 0;
ARGVALUE33 : integer := 0;
ARGVALUE34 : integer := 0;
ARGVALUE35 : integer := 0;
ARGVALUE36 : integer := 0;
ARGVALUE37 : integer := 0;
ARGVALUE38 : integer := 0;
ARGVALUE39 : integer := 0;
ARGVALUE40 : integer := 0;
ARGVALUE41 : integer := 0;
ARGVALUE42 : integer := 0;
ARGVALUE43 : integer := 0;
ARGVALUE44 : integer := 0;
ARGVALUE45 : integer := 0;
ARGVALUE46 : integer := 0;
ARGVALUE47 : integer := 0;
ARGVALUE48 : integer := 0;
ARGVALUE49 : integer := 0;
ARGVALUE50 : integer := 0;
ARGVALUE51 : integer := 0;
ARGVALUE52 : integer := 0;
ARGVALUE53 : integer := 0;
ARGVALUE54 : integer := 0;
ARGVALUE55 : integer := 0;
ARGVALUE56 : integer := 0;
ARGVALUE57 : integer := 0;
ARGVALUE58 : integer := 0;
ARGVALUE59 : integer := 0;
ARGVALUE60 : integer := 0;
ARGVALUE61 : integer := 0;
ARGVALUE62 : integer := 0;
ARGVALUE63 : integer := 0;
ARGVALUE64 : integer := 0;
ARGVALUE65 : integer := 0;
ARGVALUE66 : integer := 0;
ARGVALUE67 : integer := 0;
ARGVALUE68 : integer := 0;
ARGVALUE69 : integer := 0;
ARGVALUE70 : integer := 0;
ARGVALUE71 : integer := 0;
ARGVALUE72 : integer := 0;
ARGVALUE73 : integer := 0;
ARGVALUE74 : integer := 0;
ARGVALUE75 : integer := 0;
ARGVALUE76 : integer := 0;
ARGVALUE77 : integer := 0;
ARGVALUE78 : integer := 0;
ARGVALUE79 : integer := 0;
ARGVALUE80 : integer := 0;
ARGVALUE81 : integer := 0;
ARGVALUE82 : integer := 0;
ARGVALUE83 : integer := 0;
ARGVALUE84 : integer := 0;
ARGVALUE85 : integer := 0;
ARGVALUE86 : integer := 0;
ARGVALUE87 : integer := 0;
ARGVALUE88 : integer := 0;
ARGVALUE89 : integer := 0;
ARGVALUE90 : integer := 0;
ARGVALUE91 : integer := 0;
ARGVALUE92 : integer := 0;
ARGVALUE93 : integer := 0;
ARGVALUE94 : integer := 0;
ARGVALUE95 : integer := 0;
ARGVALUE96 : integer := 0;
ARGVALUE97 : integer := 0;
ARGVALUE98 : integer := 0;
ARGVALUE99 : integer := 0
);
port(
SYSCLK : in vl_logic;
SYSRSTN : in vl_logic;
HADDR : out vl_logic_vector(31 downto 0);
HCLK : out vl_logic;
HRESETN : out vl_logic;
HBURST : out vl_logic_vector(2 downto 0);
HMASTLOCK : out vl_logic;
HPROT : out vl_logic_vector(3 downto 0);
HSIZE : out vl_logic_vector(2 downto 0);
HTRANS : out vl_logic_vector(1 downto 0);
HWRITE : out vl_logic;
HWDATA : out vl_logic_vector(31 downto 0);
HRDATA : in vl_logic_vector(31 downto 0);
HREADY : in vl_logic;
HRESP : in vl_logic;
HSEL : out vl_logic_vector(15 downto 0);
INTERRUPT : in vl_logic_vector(255 downto 0);
GP_OUT : out vl_logic_vector(31 downto 0);
GP_IN : in vl_logic_vector(31 downto 0);
EXT_WR : out vl_logic;
EXT_RD : out vl_logic;
EXT_ADDR : out vl_logic_vector(31 downto 0);
EXT_DATA : inout vl_logic_vector(31 downto 0);
EXT_WAIT : in vl_logic;
FINISHED : out vl_logic;
FAILED : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of VECTFILE : constant is 1;
attribute mti_svvh_generic_type of MAX_INSTRUCTIONS : constant is 1;
attribute mti_svvh_generic_type of MAX_STACK : constant is 1;
attribute mti_svvh_generic_type of MAX_MEMTEST : constant is 1;
attribute mti_svvh_generic_type of TPD : constant is 1;
attribute mti_svvh_generic_type of DEBUGLEVEL : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE0 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE1 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE2 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE3 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE4 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE5 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE6 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE7 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE8 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE9 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE10 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE11 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE12 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE13 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE14 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE15 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE16 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE17 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE18 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE19 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE20 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE21 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE22 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE23 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE24 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE25 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE26 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE27 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE28 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE29 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE30 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE31 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE32 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE33 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE34 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE35 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE36 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE37 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE38 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE39 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE40 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE41 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE42 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE43 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE44 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE45 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE46 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE47 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE48 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE49 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE50 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE51 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE52 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE53 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE54 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE55 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE56 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE57 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE58 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE59 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE60 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE61 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE62 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE63 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE64 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE65 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE66 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE67 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE68 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE69 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE70 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE71 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE72 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE73 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE74 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE75 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE76 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE77 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE78 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE79 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE80 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE81 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE82 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE83 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE84 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE85 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE86 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE87 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE88 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE89 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE90 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE91 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE92 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE93 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE94 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE95 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE96 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE97 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE98 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE99 : constant is 1;
end BFM_AHBL;
|
library verilog;
use verilog.vl_types.all;
entity BFM_AHBL is
generic(
VECTFILE : string := "test.vec";
MAX_INSTRUCTIONS: integer := 16384;
MAX_STACK : integer := 1024;
MAX_MEMTEST : integer := 65536;
TPD : integer := 1;
DEBUGLEVEL : integer := -1;
ARGVALUE0 : integer := 0;
ARGVALUE1 : integer := 0;
ARGVALUE2 : integer := 0;
ARGVALUE3 : integer := 0;
ARGVALUE4 : integer := 0;
ARGVALUE5 : integer := 0;
ARGVALUE6 : integer := 0;
ARGVALUE7 : integer := 0;
ARGVALUE8 : integer := 0;
ARGVALUE9 : integer := 0;
ARGVALUE10 : integer := 0;
ARGVALUE11 : integer := 0;
ARGVALUE12 : integer := 0;
ARGVALUE13 : integer := 0;
ARGVALUE14 : integer := 0;
ARGVALUE15 : integer := 0;
ARGVALUE16 : integer := 0;
ARGVALUE17 : integer := 0;
ARGVALUE18 : integer := 0;
ARGVALUE19 : integer := 0;
ARGVALUE20 : integer := 0;
ARGVALUE21 : integer := 0;
ARGVALUE22 : integer := 0;
ARGVALUE23 : integer := 0;
ARGVALUE24 : integer := 0;
ARGVALUE25 : integer := 0;
ARGVALUE26 : integer := 0;
ARGVALUE27 : integer := 0;
ARGVALUE28 : integer := 0;
ARGVALUE29 : integer := 0;
ARGVALUE30 : integer := 0;
ARGVALUE31 : integer := 0;
ARGVALUE32 : integer := 0;
ARGVALUE33 : integer := 0;
ARGVALUE34 : integer := 0;
ARGVALUE35 : integer := 0;
ARGVALUE36 : integer := 0;
ARGVALUE37 : integer := 0;
ARGVALUE38 : integer := 0;
ARGVALUE39 : integer := 0;
ARGVALUE40 : integer := 0;
ARGVALUE41 : integer := 0;
ARGVALUE42 : integer := 0;
ARGVALUE43 : integer := 0;
ARGVALUE44 : integer := 0;
ARGVALUE45 : integer := 0;
ARGVALUE46 : integer := 0;
ARGVALUE47 : integer := 0;
ARGVALUE48 : integer := 0;
ARGVALUE49 : integer := 0;
ARGVALUE50 : integer := 0;
ARGVALUE51 : integer := 0;
ARGVALUE52 : integer := 0;
ARGVALUE53 : integer := 0;
ARGVALUE54 : integer := 0;
ARGVALUE55 : integer := 0;
ARGVALUE56 : integer := 0;
ARGVALUE57 : integer := 0;
ARGVALUE58 : integer := 0;
ARGVALUE59 : integer := 0;
ARGVALUE60 : integer := 0;
ARGVALUE61 : integer := 0;
ARGVALUE62 : integer := 0;
ARGVALUE63 : integer := 0;
ARGVALUE64 : integer := 0;
ARGVALUE65 : integer := 0;
ARGVALUE66 : integer := 0;
ARGVALUE67 : integer := 0;
ARGVALUE68 : integer := 0;
ARGVALUE69 : integer := 0;
ARGVALUE70 : integer := 0;
ARGVALUE71 : integer := 0;
ARGVALUE72 : integer := 0;
ARGVALUE73 : integer := 0;
ARGVALUE74 : integer := 0;
ARGVALUE75 : integer := 0;
ARGVALUE76 : integer := 0;
ARGVALUE77 : integer := 0;
ARGVALUE78 : integer := 0;
ARGVALUE79 : integer := 0;
ARGVALUE80 : integer := 0;
ARGVALUE81 : integer := 0;
ARGVALUE82 : integer := 0;
ARGVALUE83 : integer := 0;
ARGVALUE84 : integer := 0;
ARGVALUE85 : integer := 0;
ARGVALUE86 : integer := 0;
ARGVALUE87 : integer := 0;
ARGVALUE88 : integer := 0;
ARGVALUE89 : integer := 0;
ARGVALUE90 : integer := 0;
ARGVALUE91 : integer := 0;
ARGVALUE92 : integer := 0;
ARGVALUE93 : integer := 0;
ARGVALUE94 : integer := 0;
ARGVALUE95 : integer := 0;
ARGVALUE96 : integer := 0;
ARGVALUE97 : integer := 0;
ARGVALUE98 : integer := 0;
ARGVALUE99 : integer := 0
);
port(
SYSCLK : in vl_logic;
SYSRSTN : in vl_logic;
HADDR : out vl_logic_vector(31 downto 0);
HCLK : out vl_logic;
HRESETN : out vl_logic;
HBURST : out vl_logic_vector(2 downto 0);
HMASTLOCK : out vl_logic;
HPROT : out vl_logic_vector(3 downto 0);
HSIZE : out vl_logic_vector(2 downto 0);
HTRANS : out vl_logic_vector(1 downto 0);
HWRITE : out vl_logic;
HWDATA : out vl_logic_vector(31 downto 0);
HRDATA : in vl_logic_vector(31 downto 0);
HREADY : in vl_logic;
HRESP : in vl_logic;
HSEL : out vl_logic_vector(15 downto 0);
INTERRUPT : in vl_logic_vector(255 downto 0);
GP_OUT : out vl_logic_vector(31 downto 0);
GP_IN : in vl_logic_vector(31 downto 0);
EXT_WR : out vl_logic;
EXT_RD : out vl_logic;
EXT_ADDR : out vl_logic_vector(31 downto 0);
EXT_DATA : inout vl_logic_vector(31 downto 0);
EXT_WAIT : in vl_logic;
FINISHED : out vl_logic;
FAILED : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of VECTFILE : constant is 1;
attribute mti_svvh_generic_type of MAX_INSTRUCTIONS : constant is 1;
attribute mti_svvh_generic_type of MAX_STACK : constant is 1;
attribute mti_svvh_generic_type of MAX_MEMTEST : constant is 1;
attribute mti_svvh_generic_type of TPD : constant is 1;
attribute mti_svvh_generic_type of DEBUGLEVEL : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE0 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE1 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE2 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE3 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE4 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE5 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE6 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE7 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE8 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE9 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE10 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE11 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE12 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE13 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE14 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE15 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE16 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE17 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE18 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE19 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE20 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE21 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE22 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE23 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE24 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE25 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE26 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE27 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE28 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE29 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE30 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE31 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE32 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE33 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE34 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE35 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE36 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE37 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE38 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE39 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE40 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE41 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE42 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE43 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE44 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE45 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE46 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE47 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE48 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE49 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE50 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE51 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE52 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE53 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE54 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE55 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE56 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE57 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE58 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE59 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE60 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE61 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE62 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE63 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE64 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE65 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE66 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE67 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE68 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE69 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE70 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE71 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE72 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE73 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE74 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE75 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE76 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE77 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE78 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE79 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE80 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE81 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE82 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE83 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE84 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE85 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE86 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE87 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE88 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE89 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE90 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE91 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE92 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE93 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE94 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE95 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE96 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE97 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE98 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE99 : constant is 1;
end BFM_AHBL;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_rows_V_2_loc_channel1_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_src_rows_V_2_loc_channel1_shiftReg;
architecture rtl of FIFO_image_filter_p_src_rows_V_2_loc_channel1_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_rows_V_2_loc_channel1 is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_src_rows_V_2_loc_channel1 is
component FIFO_image_filter_p_src_rows_V_2_loc_channel1_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_src_rows_V_2_loc_channel1_shiftReg : FIFO_image_filter_p_src_rows_V_2_loc_channel1_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_rows_V_2_loc_channel1_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_src_rows_V_2_loc_channel1_shiftReg;
architecture rtl of FIFO_image_filter_p_src_rows_V_2_loc_channel1_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_rows_V_2_loc_channel1 is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_src_rows_V_2_loc_channel1 is
component FIFO_image_filter_p_src_rows_V_2_loc_channel1_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_src_rows_V_2_loc_channel1_shiftReg : FIFO_image_filter_p_src_rows_V_2_loc_channel1_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
----------------------------------------------------------
-- ECE403 Lab3 Sorter Toplevel - 4 4-bit unsigned sorter
-- Jiawei Wu
-- Satyen Akolkar
-- Top level: sorter_top.vhd
-- Maps the multiplier core to the input and output pads
----------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY sorter_top IS
Port (
padA, padB, padC, padD : IN STD_LOGIC_VECTOR(3 downto 0);
padClk : IN STD_LOGIC;
padS1reg, padS2reg, padS3reg, padS4reg : OUT STD_LOGIC_VECTOR(3 downto 0)
);
END sorter_top;
ARCHITECTURE Structure of sorter_top IS
component sorter IS
Port (
Clk : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(3 downto 0);
B : IN STD_LOGIC_VECTOR(3 downto 0);
C : IN STD_LOGIC_VECTOR(3 downto 0);
D : IN STD_LOGIC_VECTOR(3 downto 0);
S1reg : OUT STD_LOGIC_VECTOR(3 downto 0);
S2reg : OUT STD_LOGIC_VECTOR(3 downto 0);
S3reg : OUT STD_LOGIC_VECTOR(3 downto 0);
S4reg : OUT STD_LOGIC_VECTOR(3 downto 0)
);
END component;
component PDO12CDG
port(A : in std_logic;
PAD : out std_logic);
end component;
component PDUDGZ
port(Y : out std_logic;
PAD : in std_logic);
end component;
signal A, B, C, D : STD_LOGIC_VECTOR(3 downto 0);
signal S1reg, S2reg, S3reg, S4reg : STD_LOGIC_VECTOR(3 downto 0);
signal clk : STD_LOGIC;
begin
-- Input A pad mapping
padAGen: for i in 3 downto 0 generate
begin
inpA: PDUDGZ port map (Y => A(i), PAD => padA(i));
end generate;
-- Input B pad mapping
padBGen: for i in 3 downto 0 generate
begin
inpB: PDUDGZ port map (Y => B(i), PAD => padB(i));
end generate;
-- Input C pad mapping
padCGen: for i in 3 downto 0 generate
begin
inpC: PDUDGZ port map (Y => C(i), PAD => padC(i));
end generate;
-- Input D pad mapping
padDGen: for i in 3 downto 0 generate
begin
inpD: PDUDGZ port map (Y => D(i), PAD => padD(i));
end generate;
-- Output result pad mapping
padS1Gen: for i in 3 downto 0 generate
begin
opResS1: PDO12CDG port map (PAD => padS1reg(i), A => S1reg(i));
end generate;
padS2Gen: for i in 3 downto 0 generate
begin
opResS2: PDO12CDG port map (PAD => padS2reg(i), A => S2reg(i));
end generate;
padS3Gen: for i in 3 downto 0 generate
begin
opResS3: PDO12CDG port map (PAD => padS3reg(i), A => S3reg(i));
end generate;
padS4Gen: for i in 3 downto 0 generate
begin
opResS4: PDO12CDG port map (PAD => padS4reg(i), A => S4reg(i));
end generate;
-- Misc pad mapping
padClkG: PDUDGZ port map (Y => Clk, PAD => padClk);
-- Sorter mapping
coreG: sorter port map (Clk => Clk, A => A, B => B, C => C, D => D, S1reg => S1reg,
S2reg => S2reg, S3reg => S3reg, S4reg => S4reg);
END Structure;
|
-- file: clk_182.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___182.500______0.000______50.0______121.506____104.359
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_182 is
port
(-- Clock in ports
clk_200MHz : in std_logic;
-- Clock out ports
clk_182MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_182;
architecture xilinx of clk_182 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_182,clk_wiz_v5_1,{component_name=clk_182,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_182_clk_wiz
port
(-- Clock in ports
clk_200MHz : in std_logic;
-- Clock out ports
clk_182MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_182_clk_wiz
port map (
-- Clock in ports
clk_200MHz => clk_200MHz,
-- Clock out ports
clk_182MHz => clk_182MHz,
-- Status and control signals
locked => locked
);
end xilinx;
|
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|
--
-- A simulation model of VIC20 hardware
-- Copyright (c) MikeJ - March 2003
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email [email protected]
--
--
-- Revision list
--
-- version 003 fix reset of T1/T2 IFR flags if T1/T2 is reload via reg5/reg9 from wolfgang
-- version 002 fix from Mark McDougall, untested
-- version 001 initial release
-- not very sure about the shift register, documentation is a bit light.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity M6522 is
port (
I_RS : in std_logic_vector(3 downto 0);
I_DATA : in std_logic_vector(7 downto 0);
O_DATA : out std_logic_vector(7 downto 0);
O_DATA_OE_L : out std_logic;
I_RW_L : in std_logic;
I_CS1 : in std_logic;
I_CS2_L : in std_logic;
O_IRQ_L : out std_logic; -- note, not open drain
-- port a
I_CA1 : in std_logic;
I_CA2 : in std_logic;
O_CA2 : out std_logic;
O_CA2_OE_L : out std_logic;
I_PA : in std_logic_vector(7 downto 0);
O_PA : out std_logic_vector(7 downto 0);
O_PA_OE_L : out std_logic_vector(7 downto 0);
-- port b
I_CB1 : in std_logic;
O_CB1 : out std_logic;
O_CB1_OE_L : out std_logic;
I_CB2 : in std_logic;
O_CB2 : out std_logic;
O_CB2_OE_L : out std_logic;
I_PB : in std_logic_vector(7 downto 0);
O_PB : out std_logic_vector(7 downto 0);
O_PB_OE_L : out std_logic_vector(7 downto 0);
I_P2_H : in std_logic; -- high for phase 2 clock ____----__
RESET_L : in std_logic;
ENA_4 : in std_logic; -- clk enable
CLK : in std_logic
);
end;
architecture RTL of M6522 is
signal phase : std_logic_vector(1 downto 0):="00";
signal p2_h_t1 : std_logic;
signal cs : std_logic;
-- registers
signal r_ddra : std_logic_vector(7 downto 0);
signal r_ora : std_logic_vector(7 downto 0);
signal r_ira : std_logic_vector(7 downto 0);
signal r_ddrb : std_logic_vector(7 downto 0);
signal r_orb : std_logic_vector(7 downto 0);
signal r_irb : std_logic_vector(7 downto 0);
signal r_t1l_l : std_logic_vector(7 downto 0);
signal r_t1l_h : std_logic_vector(7 downto 0);
signal r_t2l_l : std_logic_vector(7 downto 0);
signal r_t2l_h : std_logic_vector(7 downto 0); -- not in real chip
signal r_sr : std_logic_vector(7 downto 0);
signal r_acr : std_logic_vector(7 downto 0);
signal r_pcr : std_logic_vector(7 downto 0);
signal r_ifr : std_logic_vector(7 downto 0);
signal r_ier : std_logic_vector(6 downto 0);
signal sr_write_ena : boolean;
signal sr_read_ena : boolean;
signal ifr_write_ena : boolean;
signal ier_write_ena : boolean;
signal clear_irq : std_logic_vector(7 downto 0);
signal load_data : std_logic_vector(7 downto 0);
-- timer 1
signal t1c : std_logic_vector(15 downto 0) := (others => '1'); -- simulators may not catch up w/o init here...
signal t1c_active : boolean;
signal t1c_done : boolean;
signal t1_w_reset_int : boolean;
signal t1_r_reset_int : boolean;
signal t1_load_counter : boolean;
signal t1_reload_counter : boolean;
signal t1_toggle : std_logic;
signal t1_irq : std_logic := '0';
-- timer 2
signal t2c : std_logic_vector(15 downto 0) := (others => '1'); -- simulators may not catch up w/o init here...
signal t2c_active : boolean;
signal t2c_done : boolean;
signal t2_pb6 : std_logic;
signal t2_pb6_t1 : std_logic;
signal t2_w_reset_int : boolean;
signal t2_r_reset_int : boolean;
signal t2_load_counter : boolean;
signal t2_reload_counter : boolean;
signal t2_irq : std_logic := '0';
signal t2_sr_ena : boolean;
-- shift reg
signal sr_cnt : std_logic_vector(3 downto 0);
signal sr_cb1_oe_l : std_logic;
signal sr_cb1_out : std_logic;
signal sr_drive_cb2 : std_logic;
signal sr_strobe : std_logic;
signal sr_strobe_t1 : std_logic;
signal sr_strobe_falling : boolean;
signal sr_strobe_rising : boolean;
signal sr_irq : std_logic;
signal sr_out : std_logic;
signal sr_off_delay : std_logic;
-- io
signal w_orb_hs : std_logic;
signal w_ora_hs : std_logic;
signal r_irb_hs : std_logic;
signal r_ira_hs : std_logic;
signal ca_hs_sr : std_logic;
signal ca_hs_pulse : std_logic;
signal cb_hs_sr : std_logic;
signal cb_hs_pulse : std_logic;
signal cb1_in_mux : std_logic;
signal ca1_ip_reg : std_logic;
signal cb1_ip_reg : std_logic;
signal ca1_int : boolean;
signal cb1_int : boolean;
signal ca1_irq : std_logic;
signal cb1_irq : std_logic;
signal ca2_ip_reg : std_logic;
signal cb2_ip_reg : std_logic;
signal ca2_int : boolean;
signal cb2_int : boolean;
signal ca2_irq : std_logic;
signal cb2_irq : std_logic;
signal final_irq : std_logic;
begin
p_phase : process
begin
-- internal clock phase
wait until rising_edge(CLK);
if (ENA_4 = '1') then
p2_h_t1 <= I_P2_H;
if (p2_h_t1 = '0') and (I_P2_H = '1') then
phase <= "11";
else
phase <= phase + "1";
end if;
end if;
end process;
p_cs : process(I_CS1, I_CS2_L, I_P2_H)
begin
cs <= '0';
if (I_CS1 = '1') and (I_CS2_L = '0') and (I_P2_H = '1') then
cs <= '1';
end if;
end process;
-- peripheral control reg (pcr)
-- 0 ca1 interrupt control (0 +ve edge, 1 -ve edge)
-- 3..1 ca2 operation
-- 000 input -ve edge
-- 001 independend interrupt input -ve edge
-- 010 input +ve edge
-- 011 independend interrupt input +ve edge
-- 100 handshake output
-- 101 pulse output
-- 110 low output
-- 111 high output
-- 7..4 as 3..0 for cb1,cb2
-- auxiliary control reg (acr)
-- 0 input latch PA (0 disable, 1 enable)
-- 1 input latch PB (0 disable, 1 enable)
-- 4..2 shift reg control
-- 000 disable
-- 001 shift in using t2
-- 010 shift in using o2
-- 011 shift in using ext clk
-- 100 shift out free running t2 rate
-- 101 shift out using t2
-- 101 shift out using o2
-- 101 shift out using ext clk
-- 5 t2 timer control (0 timed interrupt, 1 count down with pulses on pb6)
-- 7..6 t1 timer control
-- 00 timed interrupt each time t1 is loaded pb7 disable
-- 01 continuous interrupts pb7 disable
-- 00 timed interrupt each time t1 is loaded pb7 one shot output
-- 01 continuous interrupts pb7 square wave output
--
p_write_reg_reset : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
r_ora <= x"00"; r_orb <= x"00";
r_ddra <= x"00"; r_ddrb <= x"00";
r_acr <= x"00"; r_pcr <= x"00";
w_orb_hs <= '0';
w_ora_hs <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
w_orb_hs <= '0';
w_ora_hs <= '0';
if (cs = '1') and (I_RW_L = '0') then
case I_RS is
when x"0" => r_orb <= I_DATA; w_orb_hs <= '1';
when x"1" => r_ora <= I_DATA; w_ora_hs <= '1';
when x"2" => r_ddrb <= I_DATA;
when x"3" => r_ddra <= I_DATA;
when x"B" => r_acr <= I_DATA;
when x"C" => r_pcr <= I_DATA;
when x"F" => r_ora <= I_DATA;
when others => null;
end case;
end if;
if (r_acr(7) = '1') and (t1_toggle = '1') then
r_orb(7) <= not r_orb(7); -- toggle
end if;
end if;
end if;
end process;
p_write_reg : process (RESET_L, CLK) is
begin
if (RESET_L = '0') then
-- The spec says, this is not reset.
-- Fact is that the 1541 VIA1 timer won't work,
-- as the firmware ONLY sets the r_t1l_h latch!!!!
r_t1l_l <= (others => '0');
r_t1l_h <= (others => '0');
r_t2l_l <= (others => '0');
r_t2l_h <= (others => '0');
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
t1_w_reset_int <= false;
t1_load_counter <= false;
t2_w_reset_int <= false;
t2_load_counter <= false;
load_data <= x"00";
sr_write_ena <= false;
ifr_write_ena <= false;
ier_write_ena <= false;
if (cs = '1') and (I_RW_L = '0') then
load_data <= I_DATA;
case I_RS is
when x"4" => r_t1l_l <= I_DATA;
when x"5" => r_t1l_h <= I_DATA; t1_w_reset_int <= true;
t1_load_counter <= true;
when x"6" => r_t1l_l <= I_DATA;
when x"7" => r_t1l_h <= I_DATA; t1_w_reset_int <= true;
when x"8" => r_t2l_l <= I_DATA;
when x"9" => r_t2l_h <= I_DATA; t2_w_reset_int <= true;
t2_load_counter <= true;
when x"A" => sr_write_ena <= true;
when x"D" => ifr_write_ena <= true;
when x"E" => ier_write_ena <= true;
when others => null;
end case;
end if;
end if;
end if;
end process;
p_oe : process(cs, I_RW_L)
begin
O_DATA_OE_L <= '1';
if (cs = '1') and (I_RW_L = '1') then
O_DATA_OE_L <= '0';
end if;
end process;
p_read : process(cs, I_RW_L, I_RS, r_irb, r_ira, r_ddrb, r_ddra, t1c, r_t1l_l,
r_t1l_h, t2c, r_sr, r_acr, r_pcr, r_ifr, r_ier, r_orb)
begin
t1_r_reset_int <= false;
t2_r_reset_int <= false;
sr_read_ena <= false;
r_irb_hs <= '0';
r_ira_hs <= '0';
O_DATA <= x"00"; -- default
if (cs = '1') and (I_RW_L = '1') then
case I_RS is
--when x"0" => O_DATA <= r_irb; r_irb_hs <= '1';
-- fix from Mark McDougall, untested
when x"0" => O_DATA <= (r_irb and not r_ddrb) or (r_orb and r_ddrb); r_irb_hs <= '1';
when x"1" => O_DATA <= r_ira; r_ira_hs <= '1';
when x"2" => O_DATA <= r_ddrb;
when x"3" => O_DATA <= r_ddra;
when x"4" => O_DATA <= t1c( 7 downto 0); t1_r_reset_int <= true;
when x"5" => O_DATA <= t1c(15 downto 8);
when x"6" => O_DATA <= r_t1l_l;
when x"7" => O_DATA <= r_t1l_h;
when x"8" => O_DATA <= t2c( 7 downto 0); t2_r_reset_int <= true;
when x"9" => O_DATA <= t2c(15 downto 8);
when x"A" => O_DATA <= r_sr; sr_read_ena <= true;
when x"B" => O_DATA <= r_acr;
when x"C" => O_DATA <= r_pcr;
when x"D" => O_DATA <= r_ifr;
when x"E" => O_DATA <= ('0' & r_ier);
when x"F" => O_DATA <= r_ira;
when others => null;
end case;
end if;
end process;
--
-- IO
--
p_ca1_cb1_sel : process(sr_cb1_oe_l, sr_cb1_out, I_CB1)
begin
-- if the shift register is enabled, cb1 may be an output
-- in this case, we should listen to the CB1_OUT for the interrupt
if (sr_cb1_oe_l = '1') then
cb1_in_mux <= I_CB1;
else
cb1_in_mux <= sr_cb1_out;
end if;
end process;
p_ca1_cb1_int : process(r_pcr, ca1_ip_reg, I_CA1, cb1_ip_reg, cb1_in_mux)
begin
if (r_pcr(0) = '0') then -- ca1 control
-- negative edge
ca1_int <= (ca1_ip_reg = '1') and (I_CA1 = '0');
else
-- positive edge
ca1_int <= (ca1_ip_reg = '0') and (I_CA1 = '1');
end if;
if (r_pcr(4) = '0') then -- cb1 control
-- negative edge
cb1_int <= (cb1_ip_reg = '1') and (cb1_in_mux = '0');
else
-- positive edge
cb1_int <= (cb1_ip_reg = '0') and (cb1_in_mux = '1');
end if;
end process;
p_ca2_cb2_int : process(r_pcr, ca2_ip_reg, I_CA2, cb2_ip_reg, I_CB2)
begin
ca2_int <= false;
if (r_pcr(3) = '0') then -- ca2 input
if (r_pcr(2) = '0') then -- ca2 edge
-- negative edge
ca2_int <= (ca2_ip_reg = '1') and (I_CA2 = '0');
else
-- positive edge
ca2_int <= (ca2_ip_reg = '0') and (I_CA2 = '1');
end if;
end if;
cb2_int <= false;
if (r_pcr(7) = '0') then -- cb2 input
if (r_pcr(6) = '0') then -- cb2 edge
-- negative edge
cb2_int <= (cb2_ip_reg = '1') and (I_CB2 = '0');
else
-- positive edge
cb2_int <= (cb2_ip_reg = '0') and (I_CB2 = '1');
end if;
end if;
end process;
p_ca2_cb2 : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
O_CA2 <= '0';
O_CA2_OE_L <= '1';
O_CB2 <= '0';
O_CB2_OE_L <= '1';
ca_hs_sr <= '0';
ca_hs_pulse <= '0';
cb_hs_sr <= '0';
cb_hs_pulse <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- ca
if (phase = "00") and ((w_ora_hs = '1') or (r_ira_hs = '1')) then
ca_hs_sr <= '1';
elsif ca1_int then
ca_hs_sr <= '0';
end if;
if (phase = "00") then
ca_hs_pulse <= w_ora_hs or r_ira_hs;
end if;
O_CA2_OE_L <= not r_pcr(3); -- ca2 output
case r_pcr(3 downto 1) is
when "000" => O_CA2 <= '0'; -- input
when "001" => O_CA2 <= '0'; -- input
when "010" => O_CA2 <= '0'; -- input
when "011" => O_CA2 <= '0'; -- input
when "100" => O_CA2 <= not (ca_hs_sr); -- handshake
when "101" => O_CA2 <= not (ca_hs_pulse); -- pulse
when "110" => O_CA2 <= '0'; -- low
when "111" => O_CA2 <= '1'; -- high
when others => null;
end case;
-- cb
if (phase = "00") and (w_orb_hs = '1') then
cb_hs_sr <= '1';
elsif cb1_int then
cb_hs_sr <= '0';
end if;
if (phase = "00") then
cb_hs_pulse <= w_orb_hs;
end if;
O_CB2_OE_L <= not (r_pcr(7) or sr_drive_cb2); -- cb2 output or serial
if (sr_drive_cb2 = '1') then -- serial output
O_CB2 <= sr_out;
else
case r_pcr(7 downto 5) is
when "000" => O_CB2 <= '0'; -- input
when "001" => O_CB2 <= '0'; -- input
when "010" => O_CB2 <= '0'; -- input
when "011" => O_CB2 <= '0'; -- input
when "100" => O_CB2 <= not (cb_hs_sr); -- handshake
when "101" => O_CB2 <= not (cb_hs_pulse); -- pulse
when "110" => O_CB2 <= '0'; -- low
when "111" => O_CB2 <= '1'; -- high
when others => null;
end case;
end if;
end if;
end if;
end process;
O_CB1 <= sr_cb1_out;
O_CB1_OE_L <= sr_cb1_oe_l;
p_ca_cb_irq : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
ca1_irq <= '0';
ca2_irq <= '0';
cb1_irq <= '0';
cb2_irq <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- not pretty
if ca1_int then
ca1_irq <= '1';
elsif (r_ira_hs = '1') or (w_ora_hs = '1') or (clear_irq(1) = '1') then
ca1_irq <= '0';
end if;
if ca2_int then
ca2_irq <= '1';
else
if (((r_ira_hs = '1') or (w_ora_hs = '1')) and (r_pcr(1) = '0')) or
(clear_irq(0) = '1') then
ca2_irq <= '0';
end if;
end if;
if cb1_int then
cb1_irq <= '1';
elsif (r_irb_hs = '1') or (w_orb_hs = '1') or (clear_irq(4) = '1') then
cb1_irq <= '0';
end if;
if cb2_int then
cb2_irq <= '1';
else
if (((r_irb_hs = '1') or (w_orb_hs = '1')) and (r_pcr(5) = '0')) or
(clear_irq(3) = '1') then
cb2_irq <= '0';
end if;
end if;
end if;
end if;
end process;
p_input_reg : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
ca1_ip_reg <= '0';
cb1_ip_reg <= '0';
ca2_ip_reg <= '0';
cb2_ip_reg <= '0';
r_ira <= x"00";
r_irb <= x"00";
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- we have a fast clock, so we can have input registers
ca1_ip_reg <= I_CA1;
cb1_ip_reg <= cb1_in_mux;
ca2_ip_reg <= I_CA2;
cb2_ip_reg <= I_CB2;
if (r_acr(0) = '0') then
r_ira <= I_PA;
else -- enable latching
if ca1_int then
r_ira <= I_PA;
end if;
end if;
if (r_acr(1) = '0') then
r_irb <= I_PB;
else -- enable latching
if cb1_int then
r_irb <= I_PB;
end if;
end if;
end if;
end if;
end process;
p_buffers : process(r_ddra, r_ora, r_ddrb, r_acr, r_orb)
begin
-- data direction reg (ddr) 0 = input, 1 = output
O_PA <= r_ora;
O_PA_OE_L <= not r_ddra;
if (r_acr(7) = '1') then -- not clear if r_ddrb(7) must be 1 as well
O_PB_OE_L(7) <= '0'; -- an output if under t1 control
else
O_PB_OE_L(7) <= not (r_ddrb(7));
end if;
O_PB_OE_L(6 downto 0) <= not r_ddrb(6 downto 0);
O_PB(7 downto 0) <= r_orb(7 downto 0);
end process;
--
-- Timer 1
--
p_timer1_done : process
variable done : boolean;
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
done := (t1c = x"0000");
t1c_done <= done and (phase = "11");
if (phase = "11") then
t1_reload_counter <= done and (r_acr(6) = '1');
end if;
if t1_load_counter then -- done reset on load!
t1c_done <= false;
end if;
end if;
end process;
p_timer1 : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
if t1_load_counter or (t1_reload_counter and phase = "11") then
t1c( 7 downto 0) <= r_t1l_l;
t1c(15 downto 8) <= r_t1l_h;
elsif (phase="11") then
t1c <= t1c - "1";
end if;
if t1_load_counter or t1_reload_counter then
t1c_active <= true;
elsif t1c_done then
t1c_active <= false;
end if;
t1_toggle <= '0';
if t1c_active and t1c_done then
t1_toggle <= '1';
t1_irq <= '1';
elsif t1_w_reset_int or t1_r_reset_int or (clear_irq(6) = '1') then
t1_irq <= '0';
end if;
if t1_load_counter then -- irq reset on load!
t1_irq <= '0';
end if;
end if;
end process;
--
-- Timer2
--
p_timer2_pb6_input : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
if (phase = "01") then -- leading edge p2_h
t2_pb6 <= I_PB(6);
t2_pb6_t1 <= t2_pb6;
end if;
end if;
end process;
p_timer2_done : process
variable done : boolean;
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
done := (t2c = x"0000");
t2c_done <= done and (phase = "11");
if (phase = "11") then
t2_reload_counter <= done;
end if;
if t2_load_counter then -- done reset on load!
t2c_done <= false;
end if;
end if;
end process;
p_timer2 : process
variable ena : boolean;
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
if (r_acr(5) = '0') then
ena := true;
else
ena := (t2_pb6_t1 = '1') and (t2_pb6 = '0'); -- falling edge
end if;
if t2_load_counter or (t2_reload_counter and phase = "11") then
-- not sure if t2c_reload should be here. Does timer2 just continue to
-- count down, or is it reloaded ? Reloaded makes more sense if using
-- it to generate a clock for the shift register.
t2c( 7 downto 0) <= r_t2l_l;
t2c(15 downto 8) <= r_t2l_h;
else
if (phase="11") and ena then -- or count mode
t2c <= t2c - "1";
end if;
end if;
t2_sr_ena <= (t2c(7 downto 0) = x"00") and (phase = "11");
if t2_load_counter then
t2c_active <= true;
elsif t2c_done then
t2c_active <= false;
end if;
if t2c_active and t2c_done then
t2_irq <= '1';
elsif t2_w_reset_int or t2_r_reset_int or (clear_irq(5) = '1') then
t2_irq <= '0';
end if;
if t2_load_counter then -- irq reset on load!
t2_irq <= '0';
end if;
end if;
end process;
--
-- Shift Register
--
p_sr : process(RESET_L, CLK)
variable dir_out : std_logic;
variable ena : std_logic;
variable cb1_op : std_logic;
variable cb1_ip : std_logic;
variable use_t2 : std_logic;
variable free_run : std_logic;
variable sr_count_ena : boolean;
begin
if (RESET_L = '0') then
r_sr <= x"00";
sr_drive_cb2 <= '0';
sr_cb1_oe_l <= '1';
sr_cb1_out <= '0';
sr_strobe <= '1';
sr_cnt <= "0000";
sr_irq <= '0';
sr_out <= '1';
sr_off_delay <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- decode mode
dir_out := r_acr(4); -- output on cb2
cb1_op := '0';
cb1_ip := '0';
use_t2 := '0';
free_run := '0';
case r_acr(4 downto 2) is
when "000" => ena := '0'; cb1_ip := '1';
when "001" => ena := '1'; cb1_op := '1'; use_t2 := '1';
when "010" => ena := '1'; cb1_op := '1';
when "011" => ena := '1'; cb1_ip := '1';
when "100" => ena := '1'; use_t2 := '1'; free_run := '1';
when "101" => ena := '1'; cb1_op := '1'; use_t2 := '1';
when "110" => ena := '1';
when "111" => ena := '1'; cb1_ip := '1';
when others => null;
end case;
-- clock select
-- SR still runs even in disabled mode (on rising edge of CB1). It
-- just doesn't generate any interrupts.
-- Ref BBC micro advanced user guide p409
if (cb1_ip = '1') then
sr_strobe <= I_CB1;
else
if (sr_cnt(3) = '0') and (free_run = '0') then
sr_strobe <= '1';
else
if ((use_t2 = '1') and t2_sr_ena) or
((use_t2 = '0') and (phase = "00")) then
sr_strobe <= not sr_strobe;
end if;
end if;
end if;
-- latch on rising edge, shift on falling edge
if sr_write_ena then
r_sr <= load_data;
else
if (dir_out = '0') then
-- input
if (sr_cnt(3) = '1') or (cb1_ip = '1') then
if sr_strobe_rising then
r_sr(0) <= I_CB2;
elsif sr_strobe_falling then
r_sr(7 downto 1) <= r_sr(6 downto 0);
end if;
end if;
sr_out <= '1';
else
-- output
if (sr_cnt(3) = '1') or (sr_off_delay = '1') or (cb1_ip = '1') or (free_run = '1') then
if sr_strobe_falling then
r_sr(7 downto 1) <= r_sr(6 downto 0);
r_sr(0) <= r_sr(7);
sr_out <= r_sr(7);
end if;
else
sr_out <= '1';
end if;
end if;
end if;
sr_count_ena := sr_strobe_rising;
if sr_write_ena or sr_read_ena then
-- some documentation says sr bit in IFR must be set as well ?
sr_cnt <= "1000";
elsif sr_count_ena and (sr_cnt(3) = '1') then
sr_cnt <= sr_cnt + "1";
end if;
if (phase = "00") then
sr_off_delay <= sr_cnt(3); -- give some hold time when shifting out
end if;
if sr_count_ena and (sr_cnt = "1111") and (ena = '1') and (free_run = '0') then
sr_irq <= '1';
elsif sr_write_ena or sr_read_ena or (clear_irq(2) = '1') then
sr_irq <= '0';
end if;
-- assign ops
sr_drive_cb2 <= dir_out;
sr_cb1_oe_l <= not cb1_op;
sr_cb1_out <= sr_strobe;
end if;
end if;
end process;
p_sr_strobe_rise_fall : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
sr_strobe_t1 <= sr_strobe;
sr_strobe_rising <= (sr_strobe_t1 = '0') and (sr_strobe = '1');
sr_strobe_falling <= (sr_strobe_t1 = '1') and (sr_strobe = '0');
end if;
end process;
--
-- Interrupts
--
p_ier : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
r_ier <= "0000000";
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
if ier_write_ena then
if (load_data(7) = '1') then
-- set
r_ier <= r_ier or load_data(6 downto 0);
else
-- clear
r_ier <= r_ier and not load_data(6 downto 0);
end if;
end if;
end if;
end if;
end process;
p_ifr : process(t1_irq, t2_irq, final_irq, ca1_irq, ca2_irq, sr_irq,
cb1_irq, cb2_irq)
begin
r_ifr(7) <= final_irq;
r_ifr(6) <= t1_irq;
r_ifr(5) <= t2_irq;
r_ifr(4) <= cb1_irq;
r_ifr(3) <= cb2_irq;
r_ifr(2) <= sr_irq;
r_ifr(1) <= ca1_irq;
r_ifr(0) <= ca2_irq;
O_IRQ_L <= not final_irq;
end process;
p_irq : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
final_irq <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
if ((r_ifr(6 downto 0) and r_ier(6 downto 0)) = "0000000") then
final_irq <= '0'; -- no interrupts
else
final_irq <= '1';
end if;
end if;
end if;
end process;
p_clear_irq : process(ifr_write_ena, load_data)
begin
clear_irq <= x"00";
if ifr_write_ena then
clear_irq <= load_data;
end if;
end process;
end architecture RTL;
|
--
-- TemporalMixer.vhd
--
-- Copyright (c) 2006 Mitsutaka Okazaki ([email protected])
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.vm2413.all;
entity TemporalMixer is
port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in std_logic_vector( 4 downto 0 );
stage : in std_logic_vector( 1 downto 0 );
rhythm : in std_logic;
maddr : out std_logic_vector( 4 downto 0 );
mdata : in SIGNED_LI_TYPE;
mo : out std_logic_vector(9 downto 0);
ro : out std_logic_vector(9 downto 0)
);
end entity;
architecture RTL of TemporalMixer is
signal mmute, rmute : std_logic;
begin
process (clk, reset)
begin
if reset = '1' then
mo <= (others =>'0');
ro <= (others =>'0');
maddr <= (others => '0');
mmute <= '1';
rmute <= '1';
elsif clk'event and clk = '1' then
if clkena='1' then
if stage = 0 then
mo <= "1000000000";
ro <= "1000000000";
if rhythm = '0' then
case slot is
when "00000" => maddr <= "00001"; mmute <='0'; -- CH0
when "00001" => maddr <= "00011"; mmute <='0'; -- CH1
when "00010" => maddr <= "00101"; mmute <='0'; -- CH2
when "00011" => mmute <= '1';
when "00100" => mmute <= '1';
when "00101" => mmute <= '1';
when "00110" => maddr <= "00111"; mmute<='0'; -- CH3
when "00111" => maddr <= "01001"; mmute<='0'; -- CH4
when "01000" => maddr <= "01011"; mmute<='0'; -- CH5
when "01001" => mmute <= '1';
when "01010" => mmute <= '1';
when "01011" => mmute <= '1';
when "01100" => maddr <= "01101"; mmute<='0'; -- CH6
when "01101" => maddr <= "01111"; mmute<='0'; -- CH7
when "01110" => maddr <= "10001"; mmute<='0'; -- CH8
when "01111" => mmute <= '1';
when "10000" => mmute <= '1';
when "10001" => mmute <= '1';
when others =>
end case;
rmute <= '1';
else
case slot is
when "00000" => maddr <= "00001"; mmute <='0'; rmute <='1'; -- CH0
when "00001" => maddr <= "00011"; mmute <='0'; rmute <='1'; -- CH1
when "00010" => maddr <= "00101"; mmute <='0'; rmute <='1'; -- CH2
when "00011" => maddr <= "01111"; mmute <='1'; rmute <='0'; -- SD
when "00100" => maddr <= "10001"; mmute <='1'; rmute <='0'; -- CYM
when "00101" => mmute <='1'; rmute <='1';
when "00110" => maddr <= "00111"; mmute <='0'; rmute <='1'; -- CH3
when "00111" => maddr <= "01001"; mmute <='0'; rmute <='1'; -- CH4
when "01000" => maddr <= "01011"; mmute <='0'; rmute <='1'; -- CH5
when "01001" => maddr <= "01110"; mmute <='1'; rmute <='0'; -- HH
when "01010" => maddr <= "10000"; mmute <='1'; rmute <='0'; -- TOM
when "01011" => maddr <= "01101"; mmute <='1'; rmute <='0'; -- BD
when "01100" => maddr <= "01111"; mmute <='1'; rmute <='0'; -- SD
when "01101" => maddr <= "10001"; mmute <='1'; rmute <='0'; -- CYM
when "01110" => maddr <= "01110"; mmute <='1'; rmute <='0'; -- HH
when "01111" => maddr <= "10000"; mmute <='1'; rmute <='0'; -- TOM
when "10000" => maddr <= "01101"; mmute <='1'; rmute <='0'; -- BD
when "10001" => mmute <='1'; rmute <='1';
when others =>
end case;
end if;
else
if mmute = '0' then
if mdata.sign = '0' then
mo <= "1000000000" + mdata.value;
else
mo <= "1000000000" - mdata.value;
end if;
else
mo <= "1000000000";
end if;
if rmute = '0' then
if mdata.sign = '0' then
ro <= "1000000000" + mdata.value;
else
ro <= "1000000000" - mdata.value;
end if;
else
ro <= "1000000000";
end if;
end if;
end if; end if;
end process;
end architecture; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity time_keeper is
Port ( memRead : in STD_LOGIC_VECTOR (7 downto 0);
memWrite : out STD_LOGIC_VECTOR (7 downto 0);
memAddress : out STD_LOGIC_VECTOR (11 downto 0);
mem_valid : out STD_LOGIC;
mem_write : out STD_LOGIC;
mem_hold : out STD_LOGIC;
mem_done : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
heart_beat : out STD_LOGIC;
buzz : out STD_LOGIC );
end time_keeper;
architecture Behavioral of time_keeper is
constant DT_ADDRESS : std_logic_vector(11 downto 0):= "000000000000";
constant ST_ADDRESS : std_logic_vector(11 downto 0):= "000000000001";
type state is ( init, count, update, writeDT, readST, writeST, memA, memB );
signal current_state : state;
signal counter60hz : std_logic_vector( 23 downto 0 );
-- close enough, only lets us know the timer is running about
-- at the correct speed.
signal counter1hz : std_logic_vector( 6 downto 0 );
signal mem_ret_state : state;
signal tmp_mem_write : STD_LOGIC;
signal mem_ret_data : STD_LOGIC_VECTOR (7 downto 0);
begin
heart_beat <= counter1hz(6); -- for chip
-- heart_beat <= counter1hz(0); -- for simulation
mem_write <= tmp_mem_write;
process( clk, reset )
variable tmp_count : std_logic_vector( 23 downto 0 );
variable tmp_8 : std_logic_vector( 7 downto 0 );
begin
if ( reset = '1' ) then
current_state <= init;
memWrite <= ( others => '0' );
memAddress <= ( others => '0' );
mem_valid <= '0';
tmp_mem_write <= '0';
mem_hold <= '0';
buzz <= '0';
counter1hz <= "1000000";
elsif ( rising_edge( clk ) ) then
current_state <= current_state;
case current_state is
when init =>
counter60hz <= ( others => '0' );
current_state <= count;
when count =>
mem_hold <= '0';
tmp_count := counter60hz;
tmp_count := tmp_count + 1;
if( tmp_count = "000000011010101010101010" ) then -- for board divider
--if( tmp_count = "000110101010101010101010" ) then -- for board
--if( tmp_count = "000000000000000010000000" ) then -- for test bench
current_state <= update;
tmp_count := ( others => '0' );
counter1hz <= counter1hz + 1;
end if;
counter60hz <= tmp_count;
when update =>
memAddress <= DT_ADDRESS;
tmp_mem_write <= '0';
mem_hold <= '1';
mem_ret_state <= writeDT;
current_state <= memA;
when writeDT =>
tmp_8 := mem_ret_data;
if ( tmp_8 /= "00000000" ) then
tmp_8 := tmp_8 - "00000001";
end if;
memAddress <= DT_ADDRESS;
tmp_mem_write <= '1';
mem_ret_state <= readST;
memWrite <= tmp_8;
current_state <= memA;
when readST =>
memAddress <= ST_ADDRESS;
tmp_mem_write <= '0';
mem_ret_state <= writeST;
current_state <= memA;
when writeST =>
tmp_8 := mem_ret_data;
if ( tmp_8 /= "00000000" ) then
tmp_8 := tmp_8 - "00000001";
buzz <= '1';
else
buzz <= '0';
end if;
memAddress <= ST_ADDRESS;
tmp_mem_write <= '1';
mem_ret_state <= count;
memWrite <= tmp_8;
current_state <= memA;
when memA =>
if ( mem_done = '0' ) then
mem_valid <= '1';
current_state <= memB;
end if;
when memB =>
if( mem_done = '1' ) then
if ( tmp_mem_write = '0' ) then
mem_ret_data <= memRead;
end if;
mem_valid <= '0';
current_state <= mem_ret_state;
end if;
end case;
end if;
end process;
end Behavioral;
|
-- multiple1902 <[email protected]>
-- Released under GNU GPL v3, or later.
library ieee;
use ieee.std_logic_1164.all;
entity memory_tb is
end memory_tb;
architecture behav of memory_tb is
component memory
port (
cs : in std_logic; -- Chip select
re, we : in std_logic; -- Read / Write Enable
clk : in std_logic;
addr_h, addr_l
: in std_logic_vector(4 downto 0);
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(15 downto 0) -- no semicolon here!
);
end component;
for memory_0: memory use entity work.memory;
signal cs : std_logic; -- Chip select
signal re, we : std_logic; -- Read / Write Enable
signal clk : std_logic;
signal addr_h, addr_l : std_logic_vector(4 downto 0);
signal data_in : std_logic_vector(15 downto 0);
signal data_out : std_logic_vector(15 downto 0);
begin
memory_0: memory port map (
cs => cs,
re => re,
we => we,
clk => clk,
addr_h => addr_h,
addr_l => addr_l,
data_in => data_in,
data_out => data_out
);
process
begin
cs<='1';
we<='1';
re<='0';
clk<='0';
addr_h<="00000";
addr_l<="11111";
data_in<="0101011010100101";
wait for 10 ms;
clk<='1';
wait for 10 ms;
we<='0';
cs<='1';
re<='1';
clk<='0';
addr_h<="00000";
addr_l<="11111";
data_in<="ZZZZZZZZZZZZZZZZ";
wait for 10 ms;
clk<='0';
clk<='1';
wait for 10 ms;
assert false report "have a nice day!" severity note;
wait;
end process;
end behav;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2951.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p12n01i02951ent IS
END c02s02b00x00p12n01i02951ent;
ARCHITECTURE c02s02b00x00p12n01i02951arch OF c02s02b00x00p12n01i02951ent IS
function Concat(
constant in1 : in STRING;
constant in2 : in STRING
) return STRING is
variable result : STRING(1 to (in1'LENGTH + in2'LENGTH));
begin
for i in in1'RANGE loop
result(result'left + i - in1'left) := in1(i);
end loop;
for i in in2'RANGE loop
result(result'left + in1'length + i - in2'left) := in2(i);
end loop;
return result;
end;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( Concat( Concat("Let's ","try "), Concat("multiple ", "levels!")) =
"Let's try multiple levels!" )
report "***PASSED TEST: c02s02b00x00p12n01i02951"
severity NOTE;
assert ( Concat( Concat("Let's ","try "), Concat("multiple ", "levels!")) =
"Let's try multiple levels!" )
report "***FAILED TEST: c02s02b00x00p12n01i02951 - The execution of a subprogram test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p12n01i02951arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2951.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p12n01i02951ent IS
END c02s02b00x00p12n01i02951ent;
ARCHITECTURE c02s02b00x00p12n01i02951arch OF c02s02b00x00p12n01i02951ent IS
function Concat(
constant in1 : in STRING;
constant in2 : in STRING
) return STRING is
variable result : STRING(1 to (in1'LENGTH + in2'LENGTH));
begin
for i in in1'RANGE loop
result(result'left + i - in1'left) := in1(i);
end loop;
for i in in2'RANGE loop
result(result'left + in1'length + i - in2'left) := in2(i);
end loop;
return result;
end;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( Concat( Concat("Let's ","try "), Concat("multiple ", "levels!")) =
"Let's try multiple levels!" )
report "***PASSED TEST: c02s02b00x00p12n01i02951"
severity NOTE;
assert ( Concat( Concat("Let's ","try "), Concat("multiple ", "levels!")) =
"Let's try multiple levels!" )
report "***FAILED TEST: c02s02b00x00p12n01i02951 - The execution of a subprogram test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p12n01i02951arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2951.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p12n01i02951ent IS
END c02s02b00x00p12n01i02951ent;
ARCHITECTURE c02s02b00x00p12n01i02951arch OF c02s02b00x00p12n01i02951ent IS
function Concat(
constant in1 : in STRING;
constant in2 : in STRING
) return STRING is
variable result : STRING(1 to (in1'LENGTH + in2'LENGTH));
begin
for i in in1'RANGE loop
result(result'left + i - in1'left) := in1(i);
end loop;
for i in in2'RANGE loop
result(result'left + in1'length + i - in2'left) := in2(i);
end loop;
return result;
end;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( Concat( Concat("Let's ","try "), Concat("multiple ", "levels!")) =
"Let's try multiple levels!" )
report "***PASSED TEST: c02s02b00x00p12n01i02951"
severity NOTE;
assert ( Concat( Concat("Let's ","try "), Concat("multiple ", "levels!")) =
"Let's try multiple levels!" )
report "***FAILED TEST: c02s02b00x00p12n01i02951 - The execution of a subprogram test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p12n01i02951arch;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: System Monitor wrapper for temperature supervision applications
--
-- Description:
-- ------------------------------------
-- This module wraps a Virtex-6 System Monitor primitive to report if preconfigured
-- temperature values are overrun.
--
-- Temperature curve:
-- ------------------
--
-- | /-----\
-- Temp_ov on=80 | - - - - - - /-------/ \
-- | / | \
-- Temp_ov off=60 | - - - - - / - - - - | - - - - \----\
-- | / | \
-- | / | | \
-- Temp_us on=35 | - /---/ | | \
-- Temp_us off=30 | - / - -|- - - - - - | - - - - - - -|- \------\
-- | / | | | \
-- ----------------|--------|------------|--------------|----------|---------
-- pwm = | min | medium | max | medium | min
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
LIBRARY UniSim;
USE UniSim.vComponents.ALL;
entity xil_SystemMonitor_Virtex6 is
port (
Reset : in STD_LOGIC; -- Reset signal for the System Monitor control logic
Alarm_UserTemp : out STD_LOGIC; -- Temperature-sensor alarm output
Alarm_OverTemp : out STD_LOGIC; -- Over-Temperature alarm output
Alarm : out STD_LOGIC; -- OR'ed output of all the Alarms
VP : in STD_LOGIC; -- Dedicated Analog Input Pair
VN : in STD_LOGIC
);
end;
architecture xilinx of xil_SystemMonitor_Virtex6 is
signal FLOAT_VCCAUX_ALARM : STD_LOGIC;
signal FLOAT_VCCINT_ALARM : STD_LOGIC;
signal aux_channel_p : STD_LOGIC_VECTOR(15 downto 0);
signal aux_channel_n : STD_LOGIC_VECTOR(15 downto 0);
signal SysMonitor_Alarm : STD_LOGIC_VECTOR(2 downto 0);
signal SysMonitor_OverTemp : STD_LOGIC;
begin
genAUXChannel : for i in 0 to 15 generate
aux_channel_p(i) <= '0';
aux_channel_n(i) <= '0';
end generate;
SysMonitor : SYSMON
generic map (
INIT_40 => x"0000", -- config reg 0
INIT_41 => x"300c", -- config reg 1
INIT_42 => x"0a00", -- config reg 2
INIT_48 => x"0100", -- Sequencer channel selection
INIT_49 => x"0000", -- Sequencer channel selection
INIT_4A => x"0000", -- Sequencer Average selection
INIT_4B => x"0000", -- Sequencer Average selection
INIT_4C => x"0000", -- Sequencer Bipolar selection
INIT_4D => x"0000", -- Sequencer Bipolar selection
INIT_4E => x"0000", -- Sequencer Acq time selection
INIT_4F => x"0000", -- Sequencer Acq time selection
INIT_50 => x"a418", -- Temp alarm trigger
INIT_51 => x"5999", -- Vccint upper alarm limit
INIT_52 => x"e000", -- Vccaux upper alarm limit
INIT_53 => x"b363", -- Temp alarm OT upper
INIT_54 => x"9c87", -- Temp alarm reset
INIT_55 => x"5111", -- Vccint lower alarm limit
INIT_56 => x"caaa", -- Vccaux lower alarm limit
INIT_57 => x"a425", -- Temp alarm OT reset
SIM_DEVICE => "VIRTEX6",
SIM_MONITOR_FILE => "SystemMonitor_sim.txt"
)
port map (
-- Control and Clock
RESET => Reset,
CONVSTCLK => '0',
CONVST => '0',
-- DRP port
DCLK => '0',
DEN => '0',
DADDR => "0000000",
DWE => '0',
DI => x"0000",
DO => open,
DRDY => open,
-- External analog inputs
VAUXN => aux_channel_n(15 downto 0),
VAUXP => aux_channel_p(15 downto 0),
VN => VN,
VP => VP,
-- Alarms
OT => SysMonitor_OverTemp,
ALM => SysMonitor_Alarm,
-- Status
CHANNEL => open,
BUSY => open,
EOC => open,
EOS => open,
JTAGBUSY => open,
JTAGLOCKED => open,
JTAGMODIFIED => open
);
Alarm_UserTemp <= SysMonitor_Alarm(0);
Alarm_OverTemp <= SysMonitor_OverTemp;
Alarm <= SysMonitor_Alarm(0) or SysMonitor_OverTemp;
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: System Monitor wrapper for temperature supervision applications
--
-- Description:
-- ------------------------------------
-- This module wraps a Virtex-6 System Monitor primitive to report if preconfigured
-- temperature values are overrun.
--
-- Temperature curve:
-- ------------------
--
-- | /-----\
-- Temp_ov on=80 | - - - - - - /-------/ \
-- | / | \
-- Temp_ov off=60 | - - - - - / - - - - | - - - - \----\
-- | / | \
-- | / | | \
-- Temp_us on=35 | - /---/ | | \
-- Temp_us off=30 | - / - -|- - - - - - | - - - - - - -|- \------\
-- | / | | | \
-- ----------------|--------|------------|--------------|----------|---------
-- pwm = | min | medium | max | medium | min
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
LIBRARY UniSim;
USE UniSim.vComponents.ALL;
entity xil_SystemMonitor_Virtex6 is
port (
Reset : in STD_LOGIC; -- Reset signal for the System Monitor control logic
Alarm_UserTemp : out STD_LOGIC; -- Temperature-sensor alarm output
Alarm_OverTemp : out STD_LOGIC; -- Over-Temperature alarm output
Alarm : out STD_LOGIC; -- OR'ed output of all the Alarms
VP : in STD_LOGIC; -- Dedicated Analog Input Pair
VN : in STD_LOGIC
);
end;
architecture xilinx of xil_SystemMonitor_Virtex6 is
signal FLOAT_VCCAUX_ALARM : STD_LOGIC;
signal FLOAT_VCCINT_ALARM : STD_LOGIC;
signal aux_channel_p : STD_LOGIC_VECTOR(15 downto 0);
signal aux_channel_n : STD_LOGIC_VECTOR(15 downto 0);
signal SysMonitor_Alarm : STD_LOGIC_VECTOR(2 downto 0);
signal SysMonitor_OverTemp : STD_LOGIC;
begin
genAUXChannel : for i in 0 to 15 generate
aux_channel_p(i) <= '0';
aux_channel_n(i) <= '0';
end generate;
SysMonitor : SYSMON
generic map (
INIT_40 => x"0000", -- config reg 0
INIT_41 => x"300c", -- config reg 1
INIT_42 => x"0a00", -- config reg 2
INIT_48 => x"0100", -- Sequencer channel selection
INIT_49 => x"0000", -- Sequencer channel selection
INIT_4A => x"0000", -- Sequencer Average selection
INIT_4B => x"0000", -- Sequencer Average selection
INIT_4C => x"0000", -- Sequencer Bipolar selection
INIT_4D => x"0000", -- Sequencer Bipolar selection
INIT_4E => x"0000", -- Sequencer Acq time selection
INIT_4F => x"0000", -- Sequencer Acq time selection
INIT_50 => x"a418", -- Temp alarm trigger
INIT_51 => x"5999", -- Vccint upper alarm limit
INIT_52 => x"e000", -- Vccaux upper alarm limit
INIT_53 => x"b363", -- Temp alarm OT upper
INIT_54 => x"9c87", -- Temp alarm reset
INIT_55 => x"5111", -- Vccint lower alarm limit
INIT_56 => x"caaa", -- Vccaux lower alarm limit
INIT_57 => x"a425", -- Temp alarm OT reset
SIM_DEVICE => "VIRTEX6",
SIM_MONITOR_FILE => "SystemMonitor_sim.txt"
)
port map (
-- Control and Clock
RESET => Reset,
CONVSTCLK => '0',
CONVST => '0',
-- DRP port
DCLK => '0',
DEN => '0',
DADDR => "0000000",
DWE => '0',
DI => x"0000",
DO => open,
DRDY => open,
-- External analog inputs
VAUXN => aux_channel_n(15 downto 0),
VAUXP => aux_channel_p(15 downto 0),
VN => VN,
VP => VP,
-- Alarms
OT => SysMonitor_OverTemp,
ALM => SysMonitor_Alarm,
-- Status
CHANNEL => open,
BUSY => open,
EOC => open,
EOS => open,
JTAGBUSY => open,
JTAGLOCKED => open,
JTAGMODIFIED => open
);
Alarm_UserTemp <= SysMonitor_Alarm(0);
Alarm_OverTemp <= SysMonitor_OverTemp;
Alarm <= SysMonitor_Alarm(0) or SysMonitor_OverTemp;
end;
|
-- $Id: ib_sres_or_3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ib_sres_or_3 - syn
-- Description: ibus: result or, 3 input
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.1 add ib_sres_or_mon
-- 2008-08-22 161 1.0.2 renamed pdp11_ibres_ -> ib_sres_; use iblib
-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-29 107 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ib_sres_or_3 is -- ibus result or, 3 input
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end ib_sres_or_3;
architecture syn of ib_sres_or_3 is
begin
proc_comb : process (IB_SRES_1, IB_SRES_2, IB_SRES_3)
begin
IB_SRES_OR.ack <= IB_SRES_1.ack or
IB_SRES_2.ack or
IB_SRES_3.ack;
IB_SRES_OR.busy <= IB_SRES_1.busy or
IB_SRES_2.busy or
IB_SRES_3.busy;
IB_SRES_OR.dout <= IB_SRES_1.dout or
IB_SRES_2.dout or
IB_SRES_3.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : ib_sres_or_mon
port map (
IB_SRES_1 => IB_SRES_1,
IB_SRES_2 => IB_SRES_2,
IB_SRES_3 => IB_SRES_3,
IB_SRES_4 => ib_sres_init
);
-- synthesis translate_on
end syn;
|
entity grlib1 is
end entity;
architecture test of grlib1 is
constant NAHBMST : integer := 16; -- maximum AHB masters
constant NAHBSLV : integer := 16; -- maximum AHB slaves
constant NAPBSLV : integer := 16; -- maximum APB slaves
constant NAHBAMR : integer := 4; -- maximum address mapping registers
constant NAHBIR : integer := 4; -- maximum AHB identification registers
constant NAHBCFG : integer := NAHBIR + NAHBAMR; -- words in AHB config block
subtype amba_vendor_type is integer range 0 to 16#ff#;
subtype amba_device_type is integer range 0 to 16#3ff#;
subtype amba_version_type is integer range 0 to 16#3f#;
subtype amba_cfgver_type is integer range 0 to 3;
subtype ahb_addr_type is integer range 0 to 16#fff#;
subtype amba_config_word is bit_vector(31 downto 0);
type ahb_config_type is array (0 to NAHBCFG-1) of amba_config_word;
constant gAWidth: Positive := 18; -- address width
constant zero32 : bit_vector(31 downto 0) := (others => '0');
constant HADDR: Integer := 0;
constant HMASK: Integer := 16#FFF#;
function ahb_device_reg(vendor : amba_vendor_type; device : amba_device_type;
cfgver : amba_cfgver_type; version : amba_version_type)
return bit_vector is
begin
return X"01234567";
end function;
function ahb_membar(memaddr : ahb_addr_type; prefetch, cache : bit;
addrmask : ahb_addr_type)
return bit_vector is
begin
return (31 downto 0 => '1');
end function;
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg (0, 0, 0, gAWidth),
4 => ahb_membar(HADDR, '1', '1', HMASK),
others => zero32);
begin
check: process is
begin
assert HCONFIG(0) = X"01234567";
assert HCONFIG(1) = X"00000000";
assert HCONFIG(4) = X"ffffffff";
wait;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1085.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p02n01i01085ent IS
END c06s05b00x00p02n01i01085ent;
ARCHITECTURE c06s05b00x00p02n01i01085arch OF c06s05b00x00p02n01i01085ent IS
BEGIN
TESTING: PROCESS
type FIVE is range 1 to 5;
type A51 is array (FIVE) of BOOLEAN;
type A53 is array (FIVE) of A51;
variable V51: A51 ;
variable V53: A53 ;
BEGIN
V53(2 downto 1, 1 to 4) := V53(2 downto 1, 1 to 4);
-- SYNTAX ERROR: NO MULTIPLE DISCRETE RANGES IN SLICE NAMES
assert FALSE
report "***FAILED TEST: c06s05b00x00p02n01i01085 - Slice name consists of a single discrete range enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p02n01i01085arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1085.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p02n01i01085ent IS
END c06s05b00x00p02n01i01085ent;
ARCHITECTURE c06s05b00x00p02n01i01085arch OF c06s05b00x00p02n01i01085ent IS
BEGIN
TESTING: PROCESS
type FIVE is range 1 to 5;
type A51 is array (FIVE) of BOOLEAN;
type A53 is array (FIVE) of A51;
variable V51: A51 ;
variable V53: A53 ;
BEGIN
V53(2 downto 1, 1 to 4) := V53(2 downto 1, 1 to 4);
-- SYNTAX ERROR: NO MULTIPLE DISCRETE RANGES IN SLICE NAMES
assert FALSE
report "***FAILED TEST: c06s05b00x00p02n01i01085 - Slice name consists of a single discrete range enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p02n01i01085arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1085.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p02n01i01085ent IS
END c06s05b00x00p02n01i01085ent;
ARCHITECTURE c06s05b00x00p02n01i01085arch OF c06s05b00x00p02n01i01085ent IS
BEGIN
TESTING: PROCESS
type FIVE is range 1 to 5;
type A51 is array (FIVE) of BOOLEAN;
type A53 is array (FIVE) of A51;
variable V51: A51 ;
variable V53: A53 ;
BEGIN
V53(2 downto 1, 1 to 4) := V53(2 downto 1, 1 to 4);
-- SYNTAX ERROR: NO MULTIPLE DISCRETE RANGES IN SLICE NAMES
assert FALSE
report "***FAILED TEST: c06s05b00x00p02n01i01085 - Slice name consists of a single discrete range enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p02n01i01085arch;
|
--MIT License
--
--Copyright (c) 2017 Danny Savory
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
library ieee, dsaves;
use ieee.std_logic_1164.all;
entity TAP_CONTROLLER is
port(
tclk : in std_logic;
tms : in std_logic;
tdi : in std_logic;
trst : in std_logic;
tdo : out std_logic
);
end entity;
architecture IEEE_STD_1149_1_2013 of TAP_CONTROLLER is
type TAP_STATE is ( RESET, IDLE,
SELECT_DR_SCAN, CAPTURE_DR, SHIFT_DR, EXIT1_DR, PAUSE_DR, EXIT2_DR, UPDATE_DR,
SELECT_IR_SCAN, CAPTURE_IR, SHIFT_IR, EXIT1_IR, PAUSE_IR, EXIT2_IR, UPDATE_IR );
signal CURRENT_STATE, NEXT_STATE : TAP_STATE;
begin
--CURRENT_STATE assignment
process(tclk, trst)
begin
if(trst = '1') then
CURRENT_STATE <= RESET;
end if;
if(tclk'event and tclk='1') then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
--NEXT STATE logic
process(tclk, trst)
begin
if(trst = '1') then
NEXT_STATE <= RESET;
end if;
if(tclk'event and tclk = '1') then
case CURRENT_STATE is
when RESET =>
if(tms = '1') then
NEXT_STATE <= RESET;
else
NEXT_STATE <= IDLE;
end if;
when IDLE =>
if(tms = '1') then
NEXT_STATE <= SELECT_DR_SCAN;
else
NEXT_STATE <= IDLE;
end if;
when SELECT_DR_SCAN =>
if(tms = '1') then
NEXT_STATE <= SELECT_IR_SCAN;
else
NEXT_STATE <= CAPTURE_DR;
end if;
when CAPTURE_DR =>
if(tms = '1') then
NEXT_STATE <= EXIT1_DR;
else
NEXT_STATE <= SHIFT_DR;
end if;
when SHIFT_DR =>
if(tms = '1') then
NEXT_STATE <= EXIT1_DR;
else
NEXT_STATE <= SHIFT_DR;
end if;
when EXIT1_DR =>
if(tms = '1') then
NEXT_STATE <= UPDATE_DR;
else
NEXT_STATE <= PAUSE_DR;
end if;
when PAUSE_DR =>
if(tms = '1') then
NEXT_STATE <= EXIT2_DR;
else
NEXT_STATE <= PAUSE_DR;
end if;
when EXIT2_DR =>
if(tms = '1') then
NEXT_STATE <= UPDATE_DR;
else
NEXT_STATE <= SHIFT_DR;
end if;
when UPDATE_DR =>
if(tms = '1') then
NEXT_STATE <= SELECT_DR_SCAN;
else
NEXT_STATE <= IDLE;
end if;
when SELECT_IR_SCAN =>
if(tms = '1') then
NEXT_STATE <= RESET;
else
NEXT_STATE <= CAPTURE_IR;
end if;
when CAPTURE_IR =>
if(tms = '1') then
NEXT_STATE <= EXIT1_IR;
else
NEXT_STATE <= SHIFT_IR;
end if;
when SHIFT_IR =>
if(tms = '1') then
NEXT_STATE <= EXIT1_IR;
else
NEXT_STATE <= SHIFT_IR;
end if;
when EXIT1_IR =>
if(tms = '1') then
NEXT_STATE <= UPDATE_IR;
else
NEXT_STATE <= PAUSE_IR;
end if;
when PAUSE_IR =>
if(tms = '1') then
NEXT_STATE <= EXIT2_IR;
else
NEXT_STATE <= PAUSE_IR;
end if;
when EXIT2_IR =>
if(tms = '1') then
NEXT_STATE <= UPDATE_IR;
else
NEXT_STATE <= SHIFT_IR;
end if;
when UPDATE_IR =>
if(tms = '1') then
NEXT_STATE <= SELECT_DR_SCAN;
else
NEXT_STATE <= IDLE;
end if;
end case;
end if;
end process;
end architecture;
|
Library IEEE;
use IEEE.std_logic_1164.all;
entity DC7 is
port( A: in std_logic_vector (3 downto 0);
Q: out std_logic_vector (6 downto 0));
end entity DC7;
architecture Behave of DC7 is
begin
process (A)
begin
case A is
when "0000" => Q <= "0000001";
when "0001" => Q <= "1001111";
when "0010" => Q <= "0010011";
when "0011" => Q <= "0000110";
when "0100" => Q <= "1001100";
when "0101" => Q <= "0100100";
when "0110" => Q <= "0100000";
when "0111" => Q <= "0001111";
when "1000" => Q <= "0000000";
when "1001" => Q <= "0000100";
when "1010" => Q <= "0001000";
when "1011" => Q <= "1100000";
when "1100" => Q <= "1110010";
when "1101" => Q <= "1000010";
when "1110" => Q <= "0110000";
when "1111" => Q <= "0111000";
when others => Q <= "0000001";
end case;
end process;
end Behave; |
--
-- Package File Template
--
-- Purpose: This package defines data types for AXI transfers
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package axi is
type axi_in_type is record
data_in : STD_LOGIC_VECTOR (7 downto 0);
data_in_valid : STD_LOGIC; -- indicates data_in valid on clock
data_in_last : STD_LOGIC; -- indicates last data in frame
end record;
type axi_out_type is record
data_out_valid : std_logic; -- indicates data out is valid
data_out_last : std_logic; -- with data out valid indicates the last byte of a frame
data_out : std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
end record;
end axi;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity global_memory is
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
--compute group 0
ADDRESS_A_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_B_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_C_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_0_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_1_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_W_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_TO_W_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_EN_CG0 : IN STD_LOGIC;
ENABLE_CG0 : IN STD_LOGIC;
DATA_A_TO_CG0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_B_TO_CG0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_C_TO_CG0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_0_TO_CG0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_1_TO_CG0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
STALL_CG0 : OUT STD_LOGIC;
--compute group 1
ADDRESS_A_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_B_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_C_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_0_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_1_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_W_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_TO_W_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_EN_CG1 : IN STD_LOGIC;
ENABLE_CG1 : IN STD_LOGIC;
DATA_A_TO_CG1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_B_TO_CG1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_C_TO_CG1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_0_TO_CG1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_1_TO_CG1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
STALL_CG1 : OUT STD_LOGIC;
--compute group 2
ADDRESS_A_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_B_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_C_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_0_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_1_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_W_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_TO_W_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_EN_CG2 : IN STD_LOGIC;
ENABLE_CG2 : IN STD_LOGIC;
DATA_A_TO_CG2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_B_TO_CG2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_C_TO_CG2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_0_TO_CG2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_1_TO_CG2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
STALL_CG2 : OUT STD_LOGIC;
--compute group 3
ADDRESS_A_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_B_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_C_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_0_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_1_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_W_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_TO_W_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_EN_CG3 : IN STD_LOGIC;
ENABLE_CG3 : IN STD_LOGIC;
DATA_A_TO_CG3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_B_TO_CG3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_C_TO_CG3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_0_TO_CG3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_1_TO_CG3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
STALL_CG3 : OUT STD_LOGIC;
--IO controller
ADDRESS_IO : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_TO_W_IO : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_EN_IO : IN STD_LOGIC;
ENABLE_IO : IN STD_LOGIC;
DATA_RET_IO : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--DONE signals
DONE_C0 : OUT STD_LOGIC;
DONE_C1 : OUT STD_LOGIC;
DONE_C2 : OUT STD_LOGIC;
DONE_C3 : OUT STD_LOGIC;
DONE_C4 : OUT STD_LOGIC;
DONE_C5 : OUT STD_LOGIC;
DONE_C6 : OUT STD_LOGIC;
DONE_C7 : OUT STD_LOGIC;
RCC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end;
architecture global of global_memory is
component MAGIC_global
PORT (
ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
DATA_OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_C : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
C0_STALL : OUT STD_LOGIC;
C1_STALL : OUT STD_LOGIC;
CORE_IDENT : OUT STD_LOGIC;
IO_ENABLE : IN STD_LOGIC
);
end component;
type state_type is (cg0, cg1, cg2, cg3);
signal state : state_type;
signal address_a_cg0_buffer : std_logic_vector(31 downto 0);
signal address_b_cg0_buffer : std_logic_vector(31 downto 0);
signal address_c_cg0_buffer : std_logic_vector(31 downto 0);
signal address_0_cg0_buffer : std_logic_vector(31 downto 0);
signal address_1_cg0_buffer : std_logic_vector(31 downto 0);
signal address_w_cg0_buffer : std_logic_vector(31 downto 0);
signal data_to_w_cg0_buffer : std_logic_vector(31 downto 0);
signal w_en_cg0_buffer : std_logic;
signal access_request_cg0 : std_logic;
signal data_a_to_cg0_buffer : std_logic_vector (31 downto 0);
signal data_b_to_cg0_buffer : std_logic_vector (31 downto 0);
signal data_c_to_cg0_buffer : std_logic_vector (31 downto 0);
signal data_0_to_cg0_buffer : std_logic_vector (31 downto 0);
signal data_1_to_cg0_buffer : std_logic_vector (31 downto 0);
signal address_a_cg1_buffer : std_logic_vector(31 downto 0);
signal address_b_cg1_buffer : std_logic_vector(31 downto 0);
signal address_c_cg1_buffer : std_logic_vector(31 downto 0);
signal address_0_cg1_buffer : std_logic_vector(31 downto 0);
signal address_1_cg1_buffer : std_logic_vector(31 downto 0);
signal address_w_cg1_buffer : std_logic_vector(31 downto 0);
signal data_to_w_cg1_buffer : std_logic_vector(31 downto 0);
signal w_en_cg1_buffer : std_logic;
signal access_request_cg1 : std_logic;
signal data_a_to_cg1_buffer : std_logic_vector (31 downto 0);
signal data_b_to_cg1_buffer : std_logic_vector (31 downto 0);
signal data_c_to_cg1_buffer : std_logic_vector (31 downto 0);
signal data_0_to_cg1_buffer : std_logic_vector (31 downto 0);
signal data_1_to_cg1_buffer : std_logic_vector (31 downto 0);
signal address_a_cg2_buffer : std_logic_vector(31 downto 0);
signal address_b_cg2_buffer : std_logic_vector(31 downto 0);
signal address_c_cg2_buffer : std_logic_vector(31 downto 0);
signal address_0_cg2_buffer : std_logic_vector(31 downto 0);
signal address_1_cg2_buffer : std_logic_vector(31 downto 0);
signal address_w_cg2_buffer : std_logic_vector(31 downto 0);
signal data_to_w_cg2_buffer : std_logic_vector(31 downto 0);
signal w_en_cg2_buffer : std_logic;
signal access_request_cg2 : std_logic;
signal data_a_to_cg2_buffer : std_logic_vector (31 downto 0);
signal data_b_to_cg2_buffer : std_logic_vector (31 downto 0);
signal data_c_to_cg2_buffer : std_logic_vector (31 downto 0);
signal data_0_to_cg2_buffer : std_logic_vector (31 downto 0);
signal data_1_to_cg2_buffer : std_logic_vector (31 downto 0);
signal address_a_cg3_buffer : std_logic_vector(31 downto 0);
signal address_b_cg3_buffer : std_logic_vector(31 downto 0);
signal address_c_cg3_buffer : std_logic_vector(31 downto 0);
signal address_0_cg3_buffer : std_logic_vector(31 downto 0);
signal address_1_cg3_buffer : std_logic_vector(31 downto 0);
signal address_w_cg3_buffer : std_logic_vector(31 downto 0);
signal data_to_w_cg3_buffer : std_logic_vector(31 downto 0);
signal w_en_cg3_buffer : std_logic;
signal access_request_cg3 : std_logic;
signal data_a_to_cg3_buffer : std_logic_vector (31 downto 0);
signal data_b_to_cg3_buffer : std_logic_vector (31 downto 0);
signal data_c_to_cg3_buffer : std_logic_vector (31 downto 0);
signal data_0_to_cg3_buffer : std_logic_vector (31 downto 0);
signal data_1_to_cg3_buffer : std_logic_vector (31 downto 0);
signal address_a_to_mem : std_logic_vector(31 downto 0);
signal address_b_to_mem : std_logic_vector(31 downto 0);
signal address_c_to_mem : std_logic_vector(31 downto 0);
signal address_0_to_mem : std_logic_vector(31 downto 0);
signal address_1_to_mem : std_logic_vector(31 downto 0);
signal address_w_to_mem : std_logic_vector(31 downto 0);
signal data_to_w_to_mem : std_logic_vector(31 downto 0);
signal w_en_to_mem : std_logic;
signal address_a_mem : std_logic_vector(31 downto 0);
signal address_b_mem : std_logic_vector(31 downto 0);
signal address_c_mem : std_logic_vector(31 downto 0);
signal address_0_mem : std_logic_vector(31 downto 0);
signal address_1_mem : std_logic_vector(31 downto 0);
signal address_w_mem : std_logic_vector(31 downto 0);
signal data_to_w_mem : std_logic_vector(31 downto 0);
signal w_en_mem : std_logic;
signal data_a : std_logic_vector(31 downto 0);
signal data_b : std_logic_vector(31 downto 0);
signal data_c : std_logic_vector(31 downto 0);
signal data_0 : std_logic_vector(31 downto 0);
signal data_1 : std_logic_vector(31 downto 0);
signal core_id : std_logic;
signal gnd : std_logic;
signal stall_c0 : std_logic;
signal stall_c1 : std_logic;
signal stall_c0_raw : std_logic;
signal stall_c1_raw : std_logic;
signal done_cg0 : std_logic;
signal done_cg1 : std_logic;
signal done_cg2 : std_logic;
signal done_cg3 : std_logic;
signal clear_stall_cg0 : std_logic;
signal clear_stall_cg1 : std_logic;
signal clear_stall_cg2 : std_logic;
signal clear_stall_cg3 : std_logic;
signal buffer_cg0 : std_logic;
signal buffer_cg1 : std_logic;
signal buffer_cg2 : std_logic;
signal buffer_cg3 : std_logic;
signal done_reg_c0 : std_logic;
signal done_reg_c1 : std_logic;
signal done_reg_c2 : std_logic;
signal done_reg_c3 : std_logic;
signal done_reg_c4 : std_logic;
signal done_reg_c5 : std_logic;
signal done_reg_c6 : std_logic;
signal done_reg_c7 : std_logic;
signal ready_clear_count : std_logic_vector(3 downto 0);
begin
gnd <= '0';
--immidiately stall the requesting core
STALL_CG0 <= ENABLE_CG0 and clear_stall_cg0;
STALL_CG1 <= ENABLE_CG1 and clear_stall_cg1;
STALL_CG2 <= ENABLE_CG2 and clear_stall_cg2;
STALL_CG3 <= ENABLE_CG3 and clear_stall_cg3;
--pass buffered values back to compute groups
DATA_A_TO_CG0 <= data_a_to_cg0_buffer;
DATA_B_TO_CG0 <= data_b_to_cg0_buffer;
DATA_C_TO_CG0 <= data_c_to_cg0_buffer;
DATA_0_TO_CG0 <= data_0_to_cg0_buffer;
DATA_1_TO_CG0 <= data_1_to_cg0_buffer;
DATA_A_TO_CG1 <= data_a_to_cg1_buffer;
DATA_B_TO_CG1 <= data_b_to_cg1_buffer;
DATA_C_TO_CG1 <= data_c_to_cg1_buffer;
DATA_0_TO_CG1 <= data_0_to_cg1_buffer;
DATA_1_TO_CG1 <= data_1_to_cg1_buffer;
DATA_A_TO_CG2 <= data_a_to_cg2_buffer;
DATA_B_TO_CG2 <= data_b_to_cg2_buffer;
DATA_C_TO_CG2 <= data_c_to_cg2_buffer;
DATA_0_TO_CG2 <= data_0_to_cg2_buffer;
DATA_1_TO_CG2 <= data_1_to_cg2_buffer;
DATA_A_TO_CG3 <= data_a_to_cg3_buffer;
DATA_B_TO_CG3 <= data_b_to_cg3_buffer;
DATA_C_TO_CG3 <= data_c_to_cg3_buffer;
DATA_0_TO_CG3 <= data_0_to_cg3_buffer;
DATA_1_TO_CG3 <= data_1_to_cg3_buffer;
buffer_input_lines : process (CLK, RESET_n) begin
if (RESET_n = '0') then
address_a_cg0_buffer <= "00000000000000000000000000000000";
address_b_cg0_buffer <= "00000000000000000000000000000001";
address_c_cg0_buffer <= "00000000000000000000000000000010";
address_0_cg0_buffer <= "00000000000000000000000000000011";
address_1_cg0_buffer <= "00000000000000000000000000000100";
address_w_cg0_buffer <= "00000000000000000000000000000101";
data_to_w_cg0_buffer <= "00000000000000000000000000000110";
w_en_cg0_buffer <= '0';
access_request_cg0 <= '0';
address_a_cg1_buffer <= "00000000000000000000000000000000";
address_b_cg1_buffer <= "00000000000000000000000000000001";
address_c_cg1_buffer <= "00000000000000000000000000000010";
address_0_cg1_buffer <= "00000000000000000000000000000011";
address_1_cg1_buffer <= "00000000000000000000000000000100";
address_w_cg1_buffer <= "00000000000000000000000000000101";
data_to_w_cg1_buffer <= "00000000000000000000000000000110";
w_en_cg1_buffer <= '0';
access_request_cg1 <= '0';
address_a_cg2_buffer <= "00000000000000000000000000000000";
address_b_cg2_buffer <= "00000000000000000000000000000001";
address_c_cg2_buffer <= "00000000000000000000000000000010";
address_0_cg2_buffer <= "00000000000000000000000000000011";
address_1_cg2_buffer <= "00000000000000000000000000000100";
address_w_cg2_buffer <= "00000000000000000000000000000101";
data_to_w_cg2_buffer <= "00000000000000000000000000000110";
w_en_cg2_buffer <= '0';
access_request_cg2 <= '0';
address_a_cg3_buffer <= "00000000000000000000000000000000";
address_b_cg3_buffer <= "00000000000000000000000000000001";
address_c_cg3_buffer <= "00000000000000000000000000000010";
address_0_cg3_buffer <= "00000000000000000000000000000011";
address_1_cg3_buffer <= "00000000000000000000000000000100";
address_w_cg3_buffer <= "00000000000000000000000000000101";
data_to_w_cg3_buffer <= "00000000000000000000000000000110";
w_en_cg3_buffer <= '0';
access_request_cg3 <= '0';
elsif (rising_edge(CLK)) then
address_a_cg0_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_A_CG0(14 downto 13)) - 1) & ADDRESS_A_CG0(12 downto 0);
address_b_cg0_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_B_CG0(14 downto 13)) - 1) & ADDRESS_B_CG0(12 downto 0);
address_c_cg0_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_C_CG0(14 downto 13)) - 1) & ADDRESS_C_CG0(12 downto 0);
address_0_cg0_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_0_CG0(14 downto 13)) - 1) & ADDRESS_0_CG0(12 downto 0);
address_1_cg0_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_1_CG0(14 downto 13)) - 1) & ADDRESS_1_CG0(12 downto 0);
address_w_cg0_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_W_CG0(14 downto 13)) - 1) & ADDRESS_W_CG0(12 downto 0);
data_to_w_cg0_buffer <= DATA_TO_W_CG0;
w_en_cg0_buffer <= W_EN_CG0;
access_request_cg0 <= ENABLE_CG0;
address_a_cg1_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_A_CG1(14 downto 13)) - 1) & ADDRESS_A_CG1(12 downto 0);
address_b_cg1_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_B_CG1(14 downto 13)) - 1) & ADDRESS_B_CG1(12 downto 0);
address_c_cg1_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_C_CG1(14 downto 13)) - 1) & ADDRESS_C_CG1(12 downto 0);
address_0_cg1_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_0_CG1(14 downto 13)) - 1) & ADDRESS_0_CG1(12 downto 0);
address_1_cg1_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_1_CG1(14 downto 13)) - 1) & ADDRESS_1_CG1(12 downto 0);
address_w_cg1_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_W_CG1(14 downto 13)) - 1) & ADDRESS_W_CG1(12 downto 0);
data_to_w_cg1_buffer <= DATA_TO_W_CG1;
w_en_cg1_buffer <= W_EN_CG1;
access_request_cg1 <= ENABLE_CG1;
address_a_cg2_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_A_CG2(14 downto 13)) - 1) & ADDRESS_A_CG2(12 downto 0);
address_b_cg2_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_B_CG2(14 downto 13)) - 1) & ADDRESS_B_CG2(12 downto 0);
address_c_cg2_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_C_CG2(14 downto 13)) - 1) & ADDRESS_C_CG2(12 downto 0);
address_0_cg2_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_0_CG2(14 downto 13)) - 1) & ADDRESS_0_CG2(12 downto 0);
address_1_cg2_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_1_CG2(14 downto 13)) - 1) & ADDRESS_1_CG2(12 downto 0);
address_w_cg2_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_W_CG2(14 downto 13)) - 1) & ADDRESS_W_CG2(12 downto 0);
data_to_w_cg2_buffer <= DATA_TO_W_CG2;
w_en_cg2_buffer <= W_EN_CG2;
access_request_cg2 <= ENABLE_CG2;
address_a_cg3_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_A_CG3(14 downto 13)) - 1) & ADDRESS_A_CG3(12 downto 0);
address_b_cg3_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_B_CG3(14 downto 13)) - 1) & ADDRESS_B_CG3(12 downto 0);
address_c_cg3_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_C_CG3(14 downto 13)) - 1) & ADDRESS_C_CG3(12 downto 0);
address_0_cg3_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_0_CG3(14 downto 13)) - 1) & ADDRESS_0_CG3(12 downto 0);
address_1_cg3_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_1_CG3(14 downto 13)) - 1) & ADDRESS_1_CG3(12 downto 0);
address_w_cg3_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_W_CG3(14 downto 13)) - 1) & ADDRESS_W_CG3(12 downto 0);
data_to_w_cg3_buffer <= DATA_TO_W_CG3;
w_en_cg3_buffer <= W_EN_CG3;
access_request_cg3 <= ENABLE_CG3;
end if;
end process;
buffer_enables: process (RESET_n, CLK) begin
if (RESET_n = '0') then
buffer_cg0 <= '0';
buffer_cg1 <= '0';
buffer_cg2 <= '0';
buffer_cg3 <= '0';
elsif (rising_edge(CLK)) then
clear_stall_cg0 <= not buffer_cg0;
clear_stall_cg1 <= not buffer_cg1;
clear_stall_cg2 <= not buffer_cg2;
clear_stall_cg3 <= not buffer_cg3;
buffer_cg0 <= done_cg0 and access_request_cg0;
buffer_cg1 <= done_cg1 and access_request_cg1;
buffer_cg2 <= done_cg2 and access_request_cg2;
buffer_cg3 <= done_cg3 and access_request_cg3;
end if;
end process;
buffer_data: process (RESET_n, CLK) begin
if (RESET_n = '0') then
data_a_to_cg0_buffer <= "00000000000000000000000000000000";
data_b_to_cg0_buffer <= "00000000000000000000000000000000";
data_c_to_cg0_buffer <= "00000000000000000000000000000000";
data_0_to_cg0_buffer <= "00000000000000000000000000000000";
data_1_to_cg0_buffer <= "00000000000000000000000000000000";
data_a_to_cg1_buffer <= "00000000000000000000000000000000";
data_b_to_cg1_buffer <= "00000000000000000000000000000000";
data_c_to_cg1_buffer <= "00000000000000000000000000000000";
data_0_to_cg1_buffer <= "00000000000000000000000000000000";
data_1_to_cg1_buffer <= "00000000000000000000000000000000";
data_a_to_cg2_buffer <= "00000000000000000000000000000000";
data_b_to_cg2_buffer <= "00000000000000000000000000000000";
data_c_to_cg2_buffer <= "00000000000000000000000000000000";
data_0_to_cg2_buffer <= "00000000000000000000000000000000";
data_1_to_cg2_buffer <= "00000000000000000000000000000000";
data_a_to_cg3_buffer <= "00000000000000000000000000000000";
data_b_to_cg3_buffer <= "00000000000000000000000000000000";
data_c_to_cg3_buffer <= "00000000000000000000000000000000";
data_0_to_cg3_buffer <= "00000000000000000000000000000000";
data_1_to_cg3_buffer <= "00000000000000000000000000000000";
elsif (rising_edge(CLK)) then
if (buffer_cg0 = '1') then
data_a_to_cg0_buffer <= data_a;
data_b_to_cg0_buffer <= data_b;
data_c_to_cg0_buffer <= data_c;
data_0_to_cg0_buffer <= data_0;
data_1_to_cg0_buffer <= data_1;
end if;
if (buffer_cg1 = '1') then
data_a_to_cg1_buffer <= data_a;
data_b_to_cg1_buffer <= data_b;
data_c_to_cg1_buffer <= data_c;
data_0_to_cg1_buffer <= data_0;
data_1_to_cg1_buffer <= data_1;
end if;
if (buffer_cg2 = '1') then
data_a_to_cg2_buffer <= data_a;
data_b_to_cg2_buffer <= data_b;
data_c_to_cg2_buffer <= data_c;
data_0_to_cg2_buffer <= data_0;
data_1_to_cg2_buffer <= data_1;
end if;
if (buffer_cg3 = '1') then
data_a_to_cg3_buffer <= data_a;
data_b_to_cg3_buffer <= data_b;
data_c_to_cg3_buffer <= data_c;
data_0_to_cg3_buffer <= data_0;
data_1_to_cg3_buffer <= data_1;
end if;
end if;
end process;
state_machine : process (RESET_n, CLK, done_cg0, done_cg1, done_cg2, done_cg3) begin
if (RESET_n = '0') then
state <= cg0;
elsif (rising_edge(CLK)) then
case state is
when cg0 =>
if (done_cg0 = '0') then
state <= cg0;
else
state <= cg1;
end if;
when cg1 =>
if (done_cg1 = '0') then
state <= cg1;
else
state <= cg2;
end if;
when cg2 =>
if (done_cg2 = '0') then
state <= cg2;
else
state <= cg3;
end if;
when cg3 =>
if (done_cg3 = '0') then
state <= cg3;
else
state <= cg0;
end if;
end case;
end if;
end process;
passing_adresses : process (state, stall_c0, stall_c1, access_request_cg0, access_request_cg1, access_request_cg2, access_request_cg3,
address_a_cg0_buffer, address_b_cg0_buffer, address_c_cg0_buffer, address_0_cg0_buffer, address_1_cg0_buffer,
address_a_cg1_buffer, address_b_cg1_buffer, address_c_cg1_buffer, address_0_cg1_buffer, address_1_cg1_buffer,
address_a_cg2_buffer, address_b_cg2_buffer, address_c_cg2_buffer, address_0_cg2_buffer, address_1_cg2_buffer,
address_a_cg3_buffer, address_b_cg3_buffer, address_c_cg3_buffer, address_0_cg3_buffer, address_1_cg3_buffer,
address_w_cg0_buffer, address_w_cg1_buffer, address_w_cg2_buffer, address_w_cg3_buffer,
data_to_w_cg0_buffer, data_to_w_cg1_buffer, data_to_w_cg2_buffer, data_to_w_cg3_buffer,
w_en_cg0_buffer, w_en_cg1_buffer, w_en_cg2_buffer, w_en_cg3_buffer) begin
case state is
when cg0 =>
--if access requested, pass adresses
if (access_request_cg0 = '1') then
address_a_to_mem <= address_a_cg0_buffer;
address_b_to_mem <= address_b_cg0_buffer;
address_c_to_mem <= address_c_cg0_buffer;
address_0_to_mem <= address_0_cg0_buffer;
address_1_to_mem <= address_1_cg0_buffer;
address_w_to_mem <= address_w_cg0_buffer;
data_to_w_to_mem <= data_to_w_cg0_buffer;
w_en_to_mem <= w_en_cg0_buffer;
--wait for memory to respond
if ((stall_c0 and stall_c1) = '1') then
done_cg0 <= '0';
else
done_cg0 <= '1';
end if;
--if access not requested, supply dummy adresses
else
address_a_to_mem <= "00000000000000000000000000000000";
address_b_to_mem <= "00000000000000000000000000000001";
address_c_to_mem <= "00000000000000000000000000000010";
address_0_to_mem <= "00000000000000000000000000000011";
address_1_to_mem <= "00000000000000000000000000000100";
address_w_to_mem <= "00000000000000000000000000000101";
data_to_w_to_mem <= "00000000000000000000000000000110";
w_en_to_mem <= '0';
--move on to next group
done_cg0 <= '1';
end if;
--all other compute groups not getting service yet
done_cg1 <= '0';
done_cg2 <= '0';
done_cg3 <= '0';
when cg1 =>
--if access requested, pass adresses
if (access_request_cg1 = '1') then
address_a_to_mem <= address_a_cg1_buffer;
address_b_to_mem <= address_b_cg1_buffer;
address_c_to_mem <= address_c_cg1_buffer;
address_0_to_mem <= address_0_cg1_buffer;
address_1_to_mem <= address_1_cg1_buffer;
address_w_to_mem <= address_w_cg1_buffer;
data_to_w_to_mem <= data_to_w_cg1_buffer;
w_en_to_mem <= w_en_cg1_buffer;
--wait for memory to respond
if ((stall_c0 and stall_c1) = '1') then
done_cg1 <= '0';
else
done_cg1 <= '1';
end if;
--if access not requested, supply dummy adresses
else
address_a_to_mem <= "00000000000000000000000000000000";
address_b_to_mem <= "00000000000000000000000000000001";
address_c_to_mem <= "00000000000000000000000000000010";
address_0_to_mem <= "00000000000000000000000000000011";
address_1_to_mem <= "00000000000000000000000000000100";
address_w_to_mem <= "00000000000000000000000000000101";
data_to_w_to_mem <= "00000000000000000000000000000110";
w_en_to_mem <= '0';
--move on to next group
done_cg1 <= '1';
end if;
--all other compute groups not getting service yet
done_cg0 <= '0';
done_cg2 <= '0';
done_cg3 <= '0';
when cg2 =>
--if access requested, pass adresses
if (access_request_cg2 = '1') then
address_a_to_mem <= address_a_cg2_buffer;
address_b_to_mem <= address_b_cg2_buffer;
address_c_to_mem <= address_c_cg2_buffer;
address_0_to_mem <= address_0_cg2_buffer;
address_1_to_mem <= address_1_cg2_buffer;
address_w_to_mem <= address_w_cg2_buffer;
data_to_w_to_mem <= data_to_w_cg2_buffer;
w_en_to_mem <= w_en_cg2_buffer;
--wait for memory to respond
if ((stall_c0 and stall_c1) = '1') then
done_cg2 <= '0';
else
done_cg2 <= '1';
end if;
--if access not requested, supply dummy adresses
else
address_a_to_mem <= "00000000000000000000000000000000";
address_b_to_mem <= "00000000000000000000000000000001";
address_c_to_mem <= "00000000000000000000000000000010";
address_0_to_mem <= "00000000000000000000000000000011";
address_1_to_mem <= "00000000000000000000000000000100";
address_w_to_mem <= "00000000000000000000000000000101";
data_to_w_to_mem <= "00000000000000000000000000000110";
w_en_to_mem <= '0';
--move on to next group
done_cg2 <= '1';
end if;
--all other compute groups not getting service yet
done_cg1 <= '0';
done_cg0 <= '0';
done_cg3 <= '0';
when cg3 =>
--if access requested, pass adresses
if (access_request_cg3 = '1') then
address_a_to_mem <= address_a_cg3_buffer;
address_b_to_mem <= address_b_cg3_buffer;
address_c_to_mem <= address_c_cg3_buffer;
address_0_to_mem <= address_0_cg3_buffer;
address_1_to_mem <= address_1_cg3_buffer;
address_w_to_mem <= address_w_cg3_buffer;
data_to_w_to_mem <= data_to_w_cg3_buffer;
w_en_to_mem <= w_en_cg3_buffer;
--wait for memory to respond
if ((stall_c0 and stall_c1) = '1') then
done_cg3 <= '0';
else
done_cg3 <= '1';
end if;
--if access not requested, supply dummy adresses
else
address_a_to_mem <= "00000000000000000000000000000000";
address_b_to_mem <= "00000000000000000000000000000001";
address_c_to_mem <= "00000000000000000000000000000010";
address_0_to_mem <= "00000000000000000000000000000011";
address_1_to_mem <= "00000000000000000000000000000100";
address_w_to_mem <= "00000000000000000000000000000101";
data_to_w_to_mem <= "00000000000000000000000000000110";
w_en_to_mem <= '0';
--move on to next group
done_cg3 <= '1';
end if;
--all other compute groups not getting service yet
done_cg1 <= '0';
done_cg2 <= '0';
done_cg0 <= '0';
end case;
end process;
global_cache : MAGIC_global PORT MAP (
ADDRESS_A => address_a_mem,
ADDRESS_B => address_b_mem,
ADDRESS_C => address_c_mem,
ADDRESS_0 => address_0_mem,
ADDRESS_1 => address_1_mem,
ADDRESS_W => address_w_mem,
DATA_TO_W => data_to_w_mem,
W_EN => w_en_mem,
CLK => CLK,
RESET_n => RESET_n,
DATA_OUT_A => data_a,
DATA_OUT_B => data_b,
DATA_OUT_C => data_c,
DATA_OUT_0 => data_0,
DATA_OUT_1 => data_1,
C0_STALL => stall_c0_raw,
C1_STALL => stall_c1_raw,
CORE_IDENT => core_id,
IO_ENABLE => gnd
);
--io override
stall_c0 <= stall_c0_raw or ENABLE_IO;
stall_c1 <= stall_c1_raw or ENABLE_IO;
DATA_RET_IO <= data_a;
process (ENABLE_IO, ADDRESS_IO, DATA_TO_W_IO, W_EN_IO, data_a, address_a_to_mem,
address_b_to_mem, address_c_to_mem, address_0_to_mem, address_1_to_mem,
data_to_w_to_mem, w_en_to_mem, address_w_to_mem) begin
if (ENABLE_IO = '1') then
if (W_EN_IO = '1') then
address_a_mem <= "00000000000000000000000000000000";
address_b_mem <= "00000000000000000000000000000001";
address_c_mem <= "00000000000000000000000000000010";
address_0_mem <= "00000000000000000000000000000011";
address_1_mem <= "00000000000000000000000000000100";
address_w_mem <= ADDRESS_IO;
data_to_w_mem <= DATA_TO_W_IO;
w_en_mem <= '1';
else
address_a_mem <= ADDRESS_IO;
address_b_mem <= "00000000000000000000000000000001";
address_c_mem <= "00000000000000000000000000000010";
address_0_mem <= "00000000000000000000000000000011";
address_1_mem <= "00000000000000000000000000000100";
address_w_mem <= "00000000000000000000000000000100";
data_to_w_mem <= data_to_w_to_mem;
w_en_mem <= '0';
end if;
else
address_a_mem <= address_a_to_mem;
address_b_mem <= address_b_to_mem;
address_c_mem <= address_c_to_mem;
address_0_mem <= address_0_to_mem;
address_1_mem <= address_1_to_mem;
address_w_mem <= address_w_to_mem;
data_to_w_mem <= data_to_w_to_mem;
w_en_mem <= w_en_to_mem;
end if;
end process;
process (address_w_mem, w_en_mem, data_to_w_mem, CLK, RESET_n) begin
if (RESET_n = '0') then
done_reg_c0 <= '0';
done_reg_c1 <= '0';
done_reg_c2 <= '0';
done_reg_c3 <= '0';
done_reg_c4 <= '0';
done_reg_c5 <= '0';
done_reg_c6 <= '0';
done_reg_c7 <= '0';
ready_clear_count <= "0000";
elsif (rising_edge(CLK)) then
if ((address_w_mem = "00000000000000000010000000000000") and (w_en_mem = '1')) then
done_reg_c0 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000001") and (w_en_mem = '1')) then
done_reg_c1 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000010") and (w_en_mem = '1')) then
done_reg_c2 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000011") and (w_en_mem = '1')) then
done_reg_c3 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000100") and (w_en_mem = '1')) then
done_reg_c4 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000101") and (w_en_mem = '1')) then
done_reg_c5 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000110") and (w_en_mem = '1')) then
done_reg_c6 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000111") and (w_en_mem = '1')) then
done_reg_c7 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000001000") and (w_en_mem = '1')) then
ready_clear_count <= std_logic_vector(unsigned(ready_clear_count) + 1);
end if;
end if;
end process;
DONE_C0 <= done_reg_c0;
DONE_C1 <= done_reg_c1;
DONE_C2 <= done_reg_c2;
DONE_C3 <= done_reg_c3;
DONE_C4 <= done_reg_c4;
DONE_C5 <= done_reg_c5;
DONE_C6 <= done_reg_c6;
DONE_C7 <= done_reg_c7;
RCC <= ready_clear_count;
end; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity global_memory is
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
--compute group 0
ADDRESS_A_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_B_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_C_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_0_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_1_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_W_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_TO_W_CG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_EN_CG0 : IN STD_LOGIC;
ENABLE_CG0 : IN STD_LOGIC;
DATA_A_TO_CG0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_B_TO_CG0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_C_TO_CG0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_0_TO_CG0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_1_TO_CG0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
STALL_CG0 : OUT STD_LOGIC;
--compute group 1
ADDRESS_A_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_B_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_C_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_0_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_1_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_W_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_TO_W_CG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_EN_CG1 : IN STD_LOGIC;
ENABLE_CG1 : IN STD_LOGIC;
DATA_A_TO_CG1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_B_TO_CG1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_C_TO_CG1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_0_TO_CG1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_1_TO_CG1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
STALL_CG1 : OUT STD_LOGIC;
--compute group 2
ADDRESS_A_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_B_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_C_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_0_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_1_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_W_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_TO_W_CG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_EN_CG2 : IN STD_LOGIC;
ENABLE_CG2 : IN STD_LOGIC;
DATA_A_TO_CG2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_B_TO_CG2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_C_TO_CG2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_0_TO_CG2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_1_TO_CG2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
STALL_CG2 : OUT STD_LOGIC;
--compute group 3
ADDRESS_A_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_B_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_C_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_0_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_1_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ADDRESS_W_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_TO_W_CG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_EN_CG3 : IN STD_LOGIC;
ENABLE_CG3 : IN STD_LOGIC;
DATA_A_TO_CG3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_B_TO_CG3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_C_TO_CG3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_0_TO_CG3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_1_TO_CG3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
STALL_CG3 : OUT STD_LOGIC;
--IO controller
ADDRESS_IO : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATA_TO_W_IO : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_EN_IO : IN STD_LOGIC;
ENABLE_IO : IN STD_LOGIC;
DATA_RET_IO : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--DONE signals
DONE_C0 : OUT STD_LOGIC;
DONE_C1 : OUT STD_LOGIC;
DONE_C2 : OUT STD_LOGIC;
DONE_C3 : OUT STD_LOGIC;
DONE_C4 : OUT STD_LOGIC;
DONE_C5 : OUT STD_LOGIC;
DONE_C6 : OUT STD_LOGIC;
DONE_C7 : OUT STD_LOGIC;
RCC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end;
architecture global of global_memory is
component MAGIC_global
PORT (
ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
DATA_OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_C : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
C0_STALL : OUT STD_LOGIC;
C1_STALL : OUT STD_LOGIC;
CORE_IDENT : OUT STD_LOGIC;
IO_ENABLE : IN STD_LOGIC
);
end component;
type state_type is (cg0, cg1, cg2, cg3);
signal state : state_type;
signal address_a_cg0_buffer : std_logic_vector(31 downto 0);
signal address_b_cg0_buffer : std_logic_vector(31 downto 0);
signal address_c_cg0_buffer : std_logic_vector(31 downto 0);
signal address_0_cg0_buffer : std_logic_vector(31 downto 0);
signal address_1_cg0_buffer : std_logic_vector(31 downto 0);
signal address_w_cg0_buffer : std_logic_vector(31 downto 0);
signal data_to_w_cg0_buffer : std_logic_vector(31 downto 0);
signal w_en_cg0_buffer : std_logic;
signal access_request_cg0 : std_logic;
signal data_a_to_cg0_buffer : std_logic_vector (31 downto 0);
signal data_b_to_cg0_buffer : std_logic_vector (31 downto 0);
signal data_c_to_cg0_buffer : std_logic_vector (31 downto 0);
signal data_0_to_cg0_buffer : std_logic_vector (31 downto 0);
signal data_1_to_cg0_buffer : std_logic_vector (31 downto 0);
signal address_a_cg1_buffer : std_logic_vector(31 downto 0);
signal address_b_cg1_buffer : std_logic_vector(31 downto 0);
signal address_c_cg1_buffer : std_logic_vector(31 downto 0);
signal address_0_cg1_buffer : std_logic_vector(31 downto 0);
signal address_1_cg1_buffer : std_logic_vector(31 downto 0);
signal address_w_cg1_buffer : std_logic_vector(31 downto 0);
signal data_to_w_cg1_buffer : std_logic_vector(31 downto 0);
signal w_en_cg1_buffer : std_logic;
signal access_request_cg1 : std_logic;
signal data_a_to_cg1_buffer : std_logic_vector (31 downto 0);
signal data_b_to_cg1_buffer : std_logic_vector (31 downto 0);
signal data_c_to_cg1_buffer : std_logic_vector (31 downto 0);
signal data_0_to_cg1_buffer : std_logic_vector (31 downto 0);
signal data_1_to_cg1_buffer : std_logic_vector (31 downto 0);
signal address_a_cg2_buffer : std_logic_vector(31 downto 0);
signal address_b_cg2_buffer : std_logic_vector(31 downto 0);
signal address_c_cg2_buffer : std_logic_vector(31 downto 0);
signal address_0_cg2_buffer : std_logic_vector(31 downto 0);
signal address_1_cg2_buffer : std_logic_vector(31 downto 0);
signal address_w_cg2_buffer : std_logic_vector(31 downto 0);
signal data_to_w_cg2_buffer : std_logic_vector(31 downto 0);
signal w_en_cg2_buffer : std_logic;
signal access_request_cg2 : std_logic;
signal data_a_to_cg2_buffer : std_logic_vector (31 downto 0);
signal data_b_to_cg2_buffer : std_logic_vector (31 downto 0);
signal data_c_to_cg2_buffer : std_logic_vector (31 downto 0);
signal data_0_to_cg2_buffer : std_logic_vector (31 downto 0);
signal data_1_to_cg2_buffer : std_logic_vector (31 downto 0);
signal address_a_cg3_buffer : std_logic_vector(31 downto 0);
signal address_b_cg3_buffer : std_logic_vector(31 downto 0);
signal address_c_cg3_buffer : std_logic_vector(31 downto 0);
signal address_0_cg3_buffer : std_logic_vector(31 downto 0);
signal address_1_cg3_buffer : std_logic_vector(31 downto 0);
signal address_w_cg3_buffer : std_logic_vector(31 downto 0);
signal data_to_w_cg3_buffer : std_logic_vector(31 downto 0);
signal w_en_cg3_buffer : std_logic;
signal access_request_cg3 : std_logic;
signal data_a_to_cg3_buffer : std_logic_vector (31 downto 0);
signal data_b_to_cg3_buffer : std_logic_vector (31 downto 0);
signal data_c_to_cg3_buffer : std_logic_vector (31 downto 0);
signal data_0_to_cg3_buffer : std_logic_vector (31 downto 0);
signal data_1_to_cg3_buffer : std_logic_vector (31 downto 0);
signal address_a_to_mem : std_logic_vector(31 downto 0);
signal address_b_to_mem : std_logic_vector(31 downto 0);
signal address_c_to_mem : std_logic_vector(31 downto 0);
signal address_0_to_mem : std_logic_vector(31 downto 0);
signal address_1_to_mem : std_logic_vector(31 downto 0);
signal address_w_to_mem : std_logic_vector(31 downto 0);
signal data_to_w_to_mem : std_logic_vector(31 downto 0);
signal w_en_to_mem : std_logic;
signal address_a_mem : std_logic_vector(31 downto 0);
signal address_b_mem : std_logic_vector(31 downto 0);
signal address_c_mem : std_logic_vector(31 downto 0);
signal address_0_mem : std_logic_vector(31 downto 0);
signal address_1_mem : std_logic_vector(31 downto 0);
signal address_w_mem : std_logic_vector(31 downto 0);
signal data_to_w_mem : std_logic_vector(31 downto 0);
signal w_en_mem : std_logic;
signal data_a : std_logic_vector(31 downto 0);
signal data_b : std_logic_vector(31 downto 0);
signal data_c : std_logic_vector(31 downto 0);
signal data_0 : std_logic_vector(31 downto 0);
signal data_1 : std_logic_vector(31 downto 0);
signal core_id : std_logic;
signal gnd : std_logic;
signal stall_c0 : std_logic;
signal stall_c1 : std_logic;
signal stall_c0_raw : std_logic;
signal stall_c1_raw : std_logic;
signal done_cg0 : std_logic;
signal done_cg1 : std_logic;
signal done_cg2 : std_logic;
signal done_cg3 : std_logic;
signal clear_stall_cg0 : std_logic;
signal clear_stall_cg1 : std_logic;
signal clear_stall_cg2 : std_logic;
signal clear_stall_cg3 : std_logic;
signal buffer_cg0 : std_logic;
signal buffer_cg1 : std_logic;
signal buffer_cg2 : std_logic;
signal buffer_cg3 : std_logic;
signal done_reg_c0 : std_logic;
signal done_reg_c1 : std_logic;
signal done_reg_c2 : std_logic;
signal done_reg_c3 : std_logic;
signal done_reg_c4 : std_logic;
signal done_reg_c5 : std_logic;
signal done_reg_c6 : std_logic;
signal done_reg_c7 : std_logic;
signal ready_clear_count : std_logic_vector(3 downto 0);
begin
gnd <= '0';
--immidiately stall the requesting core
STALL_CG0 <= ENABLE_CG0 and clear_stall_cg0;
STALL_CG1 <= ENABLE_CG1 and clear_stall_cg1;
STALL_CG2 <= ENABLE_CG2 and clear_stall_cg2;
STALL_CG3 <= ENABLE_CG3 and clear_stall_cg3;
--pass buffered values back to compute groups
DATA_A_TO_CG0 <= data_a_to_cg0_buffer;
DATA_B_TO_CG0 <= data_b_to_cg0_buffer;
DATA_C_TO_CG0 <= data_c_to_cg0_buffer;
DATA_0_TO_CG0 <= data_0_to_cg0_buffer;
DATA_1_TO_CG0 <= data_1_to_cg0_buffer;
DATA_A_TO_CG1 <= data_a_to_cg1_buffer;
DATA_B_TO_CG1 <= data_b_to_cg1_buffer;
DATA_C_TO_CG1 <= data_c_to_cg1_buffer;
DATA_0_TO_CG1 <= data_0_to_cg1_buffer;
DATA_1_TO_CG1 <= data_1_to_cg1_buffer;
DATA_A_TO_CG2 <= data_a_to_cg2_buffer;
DATA_B_TO_CG2 <= data_b_to_cg2_buffer;
DATA_C_TO_CG2 <= data_c_to_cg2_buffer;
DATA_0_TO_CG2 <= data_0_to_cg2_buffer;
DATA_1_TO_CG2 <= data_1_to_cg2_buffer;
DATA_A_TO_CG3 <= data_a_to_cg3_buffer;
DATA_B_TO_CG3 <= data_b_to_cg3_buffer;
DATA_C_TO_CG3 <= data_c_to_cg3_buffer;
DATA_0_TO_CG3 <= data_0_to_cg3_buffer;
DATA_1_TO_CG3 <= data_1_to_cg3_buffer;
buffer_input_lines : process (CLK, RESET_n) begin
if (RESET_n = '0') then
address_a_cg0_buffer <= "00000000000000000000000000000000";
address_b_cg0_buffer <= "00000000000000000000000000000001";
address_c_cg0_buffer <= "00000000000000000000000000000010";
address_0_cg0_buffer <= "00000000000000000000000000000011";
address_1_cg0_buffer <= "00000000000000000000000000000100";
address_w_cg0_buffer <= "00000000000000000000000000000101";
data_to_w_cg0_buffer <= "00000000000000000000000000000110";
w_en_cg0_buffer <= '0';
access_request_cg0 <= '0';
address_a_cg1_buffer <= "00000000000000000000000000000000";
address_b_cg1_buffer <= "00000000000000000000000000000001";
address_c_cg1_buffer <= "00000000000000000000000000000010";
address_0_cg1_buffer <= "00000000000000000000000000000011";
address_1_cg1_buffer <= "00000000000000000000000000000100";
address_w_cg1_buffer <= "00000000000000000000000000000101";
data_to_w_cg1_buffer <= "00000000000000000000000000000110";
w_en_cg1_buffer <= '0';
access_request_cg1 <= '0';
address_a_cg2_buffer <= "00000000000000000000000000000000";
address_b_cg2_buffer <= "00000000000000000000000000000001";
address_c_cg2_buffer <= "00000000000000000000000000000010";
address_0_cg2_buffer <= "00000000000000000000000000000011";
address_1_cg2_buffer <= "00000000000000000000000000000100";
address_w_cg2_buffer <= "00000000000000000000000000000101";
data_to_w_cg2_buffer <= "00000000000000000000000000000110";
w_en_cg2_buffer <= '0';
access_request_cg2 <= '0';
address_a_cg3_buffer <= "00000000000000000000000000000000";
address_b_cg3_buffer <= "00000000000000000000000000000001";
address_c_cg3_buffer <= "00000000000000000000000000000010";
address_0_cg3_buffer <= "00000000000000000000000000000011";
address_1_cg3_buffer <= "00000000000000000000000000000100";
address_w_cg3_buffer <= "00000000000000000000000000000101";
data_to_w_cg3_buffer <= "00000000000000000000000000000110";
w_en_cg3_buffer <= '0';
access_request_cg3 <= '0';
elsif (rising_edge(CLK)) then
address_a_cg0_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_A_CG0(14 downto 13)) - 1) & ADDRESS_A_CG0(12 downto 0);
address_b_cg0_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_B_CG0(14 downto 13)) - 1) & ADDRESS_B_CG0(12 downto 0);
address_c_cg0_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_C_CG0(14 downto 13)) - 1) & ADDRESS_C_CG0(12 downto 0);
address_0_cg0_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_0_CG0(14 downto 13)) - 1) & ADDRESS_0_CG0(12 downto 0);
address_1_cg0_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_1_CG0(14 downto 13)) - 1) & ADDRESS_1_CG0(12 downto 0);
address_w_cg0_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_W_CG0(14 downto 13)) - 1) & ADDRESS_W_CG0(12 downto 0);
data_to_w_cg0_buffer <= DATA_TO_W_CG0;
w_en_cg0_buffer <= W_EN_CG0;
access_request_cg0 <= ENABLE_CG0;
address_a_cg1_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_A_CG1(14 downto 13)) - 1) & ADDRESS_A_CG1(12 downto 0);
address_b_cg1_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_B_CG1(14 downto 13)) - 1) & ADDRESS_B_CG1(12 downto 0);
address_c_cg1_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_C_CG1(14 downto 13)) - 1) & ADDRESS_C_CG1(12 downto 0);
address_0_cg1_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_0_CG1(14 downto 13)) - 1) & ADDRESS_0_CG1(12 downto 0);
address_1_cg1_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_1_CG1(14 downto 13)) - 1) & ADDRESS_1_CG1(12 downto 0);
address_w_cg1_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_W_CG1(14 downto 13)) - 1) & ADDRESS_W_CG1(12 downto 0);
data_to_w_cg1_buffer <= DATA_TO_W_CG1;
w_en_cg1_buffer <= W_EN_CG1;
access_request_cg1 <= ENABLE_CG1;
address_a_cg2_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_A_CG2(14 downto 13)) - 1) & ADDRESS_A_CG2(12 downto 0);
address_b_cg2_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_B_CG2(14 downto 13)) - 1) & ADDRESS_B_CG2(12 downto 0);
address_c_cg2_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_C_CG2(14 downto 13)) - 1) & ADDRESS_C_CG2(12 downto 0);
address_0_cg2_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_0_CG2(14 downto 13)) - 1) & ADDRESS_0_CG2(12 downto 0);
address_1_cg2_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_1_CG2(14 downto 13)) - 1) & ADDRESS_1_CG2(12 downto 0);
address_w_cg2_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_W_CG2(14 downto 13)) - 1) & ADDRESS_W_CG2(12 downto 0);
data_to_w_cg2_buffer <= DATA_TO_W_CG2;
w_en_cg2_buffer <= W_EN_CG2;
access_request_cg2 <= ENABLE_CG2;
address_a_cg3_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_A_CG3(14 downto 13)) - 1) & ADDRESS_A_CG3(12 downto 0);
address_b_cg3_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_B_CG3(14 downto 13)) - 1) & ADDRESS_B_CG3(12 downto 0);
address_c_cg3_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_C_CG3(14 downto 13)) - 1) & ADDRESS_C_CG3(12 downto 0);
address_0_cg3_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_0_CG3(14 downto 13)) - 1) & ADDRESS_0_CG3(12 downto 0);
address_1_cg3_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_1_CG3(14 downto 13)) - 1) & ADDRESS_1_CG3(12 downto 0);
address_w_cg3_buffer <= "00000000000000000" & std_logic_vector(unsigned(ADDRESS_W_CG3(14 downto 13)) - 1) & ADDRESS_W_CG3(12 downto 0);
data_to_w_cg3_buffer <= DATA_TO_W_CG3;
w_en_cg3_buffer <= W_EN_CG3;
access_request_cg3 <= ENABLE_CG3;
end if;
end process;
buffer_enables: process (RESET_n, CLK) begin
if (RESET_n = '0') then
buffer_cg0 <= '0';
buffer_cg1 <= '0';
buffer_cg2 <= '0';
buffer_cg3 <= '0';
elsif (rising_edge(CLK)) then
clear_stall_cg0 <= not buffer_cg0;
clear_stall_cg1 <= not buffer_cg1;
clear_stall_cg2 <= not buffer_cg2;
clear_stall_cg3 <= not buffer_cg3;
buffer_cg0 <= done_cg0 and access_request_cg0;
buffer_cg1 <= done_cg1 and access_request_cg1;
buffer_cg2 <= done_cg2 and access_request_cg2;
buffer_cg3 <= done_cg3 and access_request_cg3;
end if;
end process;
buffer_data: process (RESET_n, CLK) begin
if (RESET_n = '0') then
data_a_to_cg0_buffer <= "00000000000000000000000000000000";
data_b_to_cg0_buffer <= "00000000000000000000000000000000";
data_c_to_cg0_buffer <= "00000000000000000000000000000000";
data_0_to_cg0_buffer <= "00000000000000000000000000000000";
data_1_to_cg0_buffer <= "00000000000000000000000000000000";
data_a_to_cg1_buffer <= "00000000000000000000000000000000";
data_b_to_cg1_buffer <= "00000000000000000000000000000000";
data_c_to_cg1_buffer <= "00000000000000000000000000000000";
data_0_to_cg1_buffer <= "00000000000000000000000000000000";
data_1_to_cg1_buffer <= "00000000000000000000000000000000";
data_a_to_cg2_buffer <= "00000000000000000000000000000000";
data_b_to_cg2_buffer <= "00000000000000000000000000000000";
data_c_to_cg2_buffer <= "00000000000000000000000000000000";
data_0_to_cg2_buffer <= "00000000000000000000000000000000";
data_1_to_cg2_buffer <= "00000000000000000000000000000000";
data_a_to_cg3_buffer <= "00000000000000000000000000000000";
data_b_to_cg3_buffer <= "00000000000000000000000000000000";
data_c_to_cg3_buffer <= "00000000000000000000000000000000";
data_0_to_cg3_buffer <= "00000000000000000000000000000000";
data_1_to_cg3_buffer <= "00000000000000000000000000000000";
elsif (rising_edge(CLK)) then
if (buffer_cg0 = '1') then
data_a_to_cg0_buffer <= data_a;
data_b_to_cg0_buffer <= data_b;
data_c_to_cg0_buffer <= data_c;
data_0_to_cg0_buffer <= data_0;
data_1_to_cg0_buffer <= data_1;
end if;
if (buffer_cg1 = '1') then
data_a_to_cg1_buffer <= data_a;
data_b_to_cg1_buffer <= data_b;
data_c_to_cg1_buffer <= data_c;
data_0_to_cg1_buffer <= data_0;
data_1_to_cg1_buffer <= data_1;
end if;
if (buffer_cg2 = '1') then
data_a_to_cg2_buffer <= data_a;
data_b_to_cg2_buffer <= data_b;
data_c_to_cg2_buffer <= data_c;
data_0_to_cg2_buffer <= data_0;
data_1_to_cg2_buffer <= data_1;
end if;
if (buffer_cg3 = '1') then
data_a_to_cg3_buffer <= data_a;
data_b_to_cg3_buffer <= data_b;
data_c_to_cg3_buffer <= data_c;
data_0_to_cg3_buffer <= data_0;
data_1_to_cg3_buffer <= data_1;
end if;
end if;
end process;
state_machine : process (RESET_n, CLK, done_cg0, done_cg1, done_cg2, done_cg3) begin
if (RESET_n = '0') then
state <= cg0;
elsif (rising_edge(CLK)) then
case state is
when cg0 =>
if (done_cg0 = '0') then
state <= cg0;
else
state <= cg1;
end if;
when cg1 =>
if (done_cg1 = '0') then
state <= cg1;
else
state <= cg2;
end if;
when cg2 =>
if (done_cg2 = '0') then
state <= cg2;
else
state <= cg3;
end if;
when cg3 =>
if (done_cg3 = '0') then
state <= cg3;
else
state <= cg0;
end if;
end case;
end if;
end process;
passing_adresses : process (state, stall_c0, stall_c1, access_request_cg0, access_request_cg1, access_request_cg2, access_request_cg3,
address_a_cg0_buffer, address_b_cg0_buffer, address_c_cg0_buffer, address_0_cg0_buffer, address_1_cg0_buffer,
address_a_cg1_buffer, address_b_cg1_buffer, address_c_cg1_buffer, address_0_cg1_buffer, address_1_cg1_buffer,
address_a_cg2_buffer, address_b_cg2_buffer, address_c_cg2_buffer, address_0_cg2_buffer, address_1_cg2_buffer,
address_a_cg3_buffer, address_b_cg3_buffer, address_c_cg3_buffer, address_0_cg3_buffer, address_1_cg3_buffer,
address_w_cg0_buffer, address_w_cg1_buffer, address_w_cg2_buffer, address_w_cg3_buffer,
data_to_w_cg0_buffer, data_to_w_cg1_buffer, data_to_w_cg2_buffer, data_to_w_cg3_buffer,
w_en_cg0_buffer, w_en_cg1_buffer, w_en_cg2_buffer, w_en_cg3_buffer) begin
case state is
when cg0 =>
--if access requested, pass adresses
if (access_request_cg0 = '1') then
address_a_to_mem <= address_a_cg0_buffer;
address_b_to_mem <= address_b_cg0_buffer;
address_c_to_mem <= address_c_cg0_buffer;
address_0_to_mem <= address_0_cg0_buffer;
address_1_to_mem <= address_1_cg0_buffer;
address_w_to_mem <= address_w_cg0_buffer;
data_to_w_to_mem <= data_to_w_cg0_buffer;
w_en_to_mem <= w_en_cg0_buffer;
--wait for memory to respond
if ((stall_c0 and stall_c1) = '1') then
done_cg0 <= '0';
else
done_cg0 <= '1';
end if;
--if access not requested, supply dummy adresses
else
address_a_to_mem <= "00000000000000000000000000000000";
address_b_to_mem <= "00000000000000000000000000000001";
address_c_to_mem <= "00000000000000000000000000000010";
address_0_to_mem <= "00000000000000000000000000000011";
address_1_to_mem <= "00000000000000000000000000000100";
address_w_to_mem <= "00000000000000000000000000000101";
data_to_w_to_mem <= "00000000000000000000000000000110";
w_en_to_mem <= '0';
--move on to next group
done_cg0 <= '1';
end if;
--all other compute groups not getting service yet
done_cg1 <= '0';
done_cg2 <= '0';
done_cg3 <= '0';
when cg1 =>
--if access requested, pass adresses
if (access_request_cg1 = '1') then
address_a_to_mem <= address_a_cg1_buffer;
address_b_to_mem <= address_b_cg1_buffer;
address_c_to_mem <= address_c_cg1_buffer;
address_0_to_mem <= address_0_cg1_buffer;
address_1_to_mem <= address_1_cg1_buffer;
address_w_to_mem <= address_w_cg1_buffer;
data_to_w_to_mem <= data_to_w_cg1_buffer;
w_en_to_mem <= w_en_cg1_buffer;
--wait for memory to respond
if ((stall_c0 and stall_c1) = '1') then
done_cg1 <= '0';
else
done_cg1 <= '1';
end if;
--if access not requested, supply dummy adresses
else
address_a_to_mem <= "00000000000000000000000000000000";
address_b_to_mem <= "00000000000000000000000000000001";
address_c_to_mem <= "00000000000000000000000000000010";
address_0_to_mem <= "00000000000000000000000000000011";
address_1_to_mem <= "00000000000000000000000000000100";
address_w_to_mem <= "00000000000000000000000000000101";
data_to_w_to_mem <= "00000000000000000000000000000110";
w_en_to_mem <= '0';
--move on to next group
done_cg1 <= '1';
end if;
--all other compute groups not getting service yet
done_cg0 <= '0';
done_cg2 <= '0';
done_cg3 <= '0';
when cg2 =>
--if access requested, pass adresses
if (access_request_cg2 = '1') then
address_a_to_mem <= address_a_cg2_buffer;
address_b_to_mem <= address_b_cg2_buffer;
address_c_to_mem <= address_c_cg2_buffer;
address_0_to_mem <= address_0_cg2_buffer;
address_1_to_mem <= address_1_cg2_buffer;
address_w_to_mem <= address_w_cg2_buffer;
data_to_w_to_mem <= data_to_w_cg2_buffer;
w_en_to_mem <= w_en_cg2_buffer;
--wait for memory to respond
if ((stall_c0 and stall_c1) = '1') then
done_cg2 <= '0';
else
done_cg2 <= '1';
end if;
--if access not requested, supply dummy adresses
else
address_a_to_mem <= "00000000000000000000000000000000";
address_b_to_mem <= "00000000000000000000000000000001";
address_c_to_mem <= "00000000000000000000000000000010";
address_0_to_mem <= "00000000000000000000000000000011";
address_1_to_mem <= "00000000000000000000000000000100";
address_w_to_mem <= "00000000000000000000000000000101";
data_to_w_to_mem <= "00000000000000000000000000000110";
w_en_to_mem <= '0';
--move on to next group
done_cg2 <= '1';
end if;
--all other compute groups not getting service yet
done_cg1 <= '0';
done_cg0 <= '0';
done_cg3 <= '0';
when cg3 =>
--if access requested, pass adresses
if (access_request_cg3 = '1') then
address_a_to_mem <= address_a_cg3_buffer;
address_b_to_mem <= address_b_cg3_buffer;
address_c_to_mem <= address_c_cg3_buffer;
address_0_to_mem <= address_0_cg3_buffer;
address_1_to_mem <= address_1_cg3_buffer;
address_w_to_mem <= address_w_cg3_buffer;
data_to_w_to_mem <= data_to_w_cg3_buffer;
w_en_to_mem <= w_en_cg3_buffer;
--wait for memory to respond
if ((stall_c0 and stall_c1) = '1') then
done_cg3 <= '0';
else
done_cg3 <= '1';
end if;
--if access not requested, supply dummy adresses
else
address_a_to_mem <= "00000000000000000000000000000000";
address_b_to_mem <= "00000000000000000000000000000001";
address_c_to_mem <= "00000000000000000000000000000010";
address_0_to_mem <= "00000000000000000000000000000011";
address_1_to_mem <= "00000000000000000000000000000100";
address_w_to_mem <= "00000000000000000000000000000101";
data_to_w_to_mem <= "00000000000000000000000000000110";
w_en_to_mem <= '0';
--move on to next group
done_cg3 <= '1';
end if;
--all other compute groups not getting service yet
done_cg1 <= '0';
done_cg2 <= '0';
done_cg0 <= '0';
end case;
end process;
global_cache : MAGIC_global PORT MAP (
ADDRESS_A => address_a_mem,
ADDRESS_B => address_b_mem,
ADDRESS_C => address_c_mem,
ADDRESS_0 => address_0_mem,
ADDRESS_1 => address_1_mem,
ADDRESS_W => address_w_mem,
DATA_TO_W => data_to_w_mem,
W_EN => w_en_mem,
CLK => CLK,
RESET_n => RESET_n,
DATA_OUT_A => data_a,
DATA_OUT_B => data_b,
DATA_OUT_C => data_c,
DATA_OUT_0 => data_0,
DATA_OUT_1 => data_1,
C0_STALL => stall_c0_raw,
C1_STALL => stall_c1_raw,
CORE_IDENT => core_id,
IO_ENABLE => gnd
);
--io override
stall_c0 <= stall_c0_raw or ENABLE_IO;
stall_c1 <= stall_c1_raw or ENABLE_IO;
DATA_RET_IO <= data_a;
process (ENABLE_IO, ADDRESS_IO, DATA_TO_W_IO, W_EN_IO, data_a, address_a_to_mem,
address_b_to_mem, address_c_to_mem, address_0_to_mem, address_1_to_mem,
data_to_w_to_mem, w_en_to_mem, address_w_to_mem) begin
if (ENABLE_IO = '1') then
if (W_EN_IO = '1') then
address_a_mem <= "00000000000000000000000000000000";
address_b_mem <= "00000000000000000000000000000001";
address_c_mem <= "00000000000000000000000000000010";
address_0_mem <= "00000000000000000000000000000011";
address_1_mem <= "00000000000000000000000000000100";
address_w_mem <= ADDRESS_IO;
data_to_w_mem <= DATA_TO_W_IO;
w_en_mem <= '1';
else
address_a_mem <= ADDRESS_IO;
address_b_mem <= "00000000000000000000000000000001";
address_c_mem <= "00000000000000000000000000000010";
address_0_mem <= "00000000000000000000000000000011";
address_1_mem <= "00000000000000000000000000000100";
address_w_mem <= "00000000000000000000000000000100";
data_to_w_mem <= data_to_w_to_mem;
w_en_mem <= '0';
end if;
else
address_a_mem <= address_a_to_mem;
address_b_mem <= address_b_to_mem;
address_c_mem <= address_c_to_mem;
address_0_mem <= address_0_to_mem;
address_1_mem <= address_1_to_mem;
address_w_mem <= address_w_to_mem;
data_to_w_mem <= data_to_w_to_mem;
w_en_mem <= w_en_to_mem;
end if;
end process;
process (address_w_mem, w_en_mem, data_to_w_mem, CLK, RESET_n) begin
if (RESET_n = '0') then
done_reg_c0 <= '0';
done_reg_c1 <= '0';
done_reg_c2 <= '0';
done_reg_c3 <= '0';
done_reg_c4 <= '0';
done_reg_c5 <= '0';
done_reg_c6 <= '0';
done_reg_c7 <= '0';
ready_clear_count <= "0000";
elsif (rising_edge(CLK)) then
if ((address_w_mem = "00000000000000000010000000000000") and (w_en_mem = '1')) then
done_reg_c0 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000001") and (w_en_mem = '1')) then
done_reg_c1 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000010") and (w_en_mem = '1')) then
done_reg_c2 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000011") and (w_en_mem = '1')) then
done_reg_c3 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000100") and (w_en_mem = '1')) then
done_reg_c4 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000101") and (w_en_mem = '1')) then
done_reg_c5 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000110") and (w_en_mem = '1')) then
done_reg_c6 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000000111") and (w_en_mem = '1')) then
done_reg_c7 <= data_to_w_mem(0);
end if;
if ((address_w_mem = "00000000000000000010000000001000") and (w_en_mem = '1')) then
ready_clear_count <= std_logic_vector(unsigned(ready_clear_count) + 1);
end if;
end if;
end process;
DONE_C0 <= done_reg_c0;
DONE_C1 <= done_reg_c1;
DONE_C2 <= done_reg_c2;
DONE_C3 <= done_reg_c3;
DONE_C4 <= done_reg_c4;
DONE_C5 <= done_reg_c5;
DONE_C6 <= done_reg_c6;
DONE_C7 <= done_reg_c7;
RCC <= ready_clear_count;
end; |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: test bench for the FPU core
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: [email protected]
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use std.textio.all;
use work.txt_util.all;
-- fpu operations (fpu_op_i):
-- ========================
-- 000 = add,
-- 001 = substract,
-- 010 = multiply,
-- 011 = divide,
-- 100 = square root
-- 101 = unused
-- 110 = unused
-- 111 = unused
-- Rounding Mode:
-- ==============
-- 00 = round to nearest even(default),
-- 01 = round to zero,
-- 10 = round up,
-- 11 = round down
entity tb_fpu is
end tb_fpu;
architecture rtl of tb_fpu is
--component fpu
-- port (
-- CLK0I : in std_logic;
-- opa0i : in std_logic_vector(31 downto 0);
-- opb0i : in std_logic_vector(31 downto 0);
-- fpu0op0i : in std_logic_vector(2 downto 0);
-- rmode0i : in std_logic_vector(1 downto 0);
-- output0o : out std_logic_vector(31 downto 0);
-- ine0o : out std_logic;
-- overflow0o : out std_logic;
-- underflow0o : out std_logic;
-- div0zero0o : out std_logic;
-- inf0o : out std_logic;
-- zero0o : out std_logic;
-- qnan0o : out std_logic;
-- snan0o : out std_logic;
-- start0i : in std_logic;
-- ready0o : out std_logic
-- );
--end component;
component fpu
port (
clk_i : in std_logic;
opa_i : in std_logic_vector(31 downto 0);
opb_i : in std_logic_vector(31 downto 0);
fpu_op_i : in std_logic_vector(2 downto 0);
rmode_i : in std_logic_vector(1 downto 0);
output_o : out std_logic_vector(31 downto 0);
ine_o : out std_logic;
overflow_o : out std_logic;
underflow_o : out std_logic;
div_zero_o : out std_logic;
inf_o : out std_logic;
zero_o : out std_logic;
qnan_o : out std_logic;
snan_o : out std_logic;
start_i : in std_logic;
ready_o : out std_logic
);
end component;
signal clk_i : std_logic := '1';
signal opa_i, opb_i : std_logic_vector(31 downto 0);
signal fpu_op_i : std_logic_vector(2 downto 0);
signal rmode_i : std_logic_vector(1 downto 0);
signal output_o : std_logic_vector(31 downto 0);
signal start_i, ready_o : std_logic;
signal ine_o, overflow_o, underflow_o, div_zero_o, inf_o, zero_o, qnan_o, snan_o : std_logic;
signal slv_out : std_logic_vector(31 downto 0);
constant CLK_PERIOD : time := 60 ns; -- period of clk period
begin
-- instantiate fpu
--i_fpu : fpu port map (
-- CLK0I => clk_i,
-- opa0i => opa_i,
-- opb0i => opb_i,
-- fpu0op0i => fpu_op_i,
-- rmode0i => rmode_i,
-- output0o => output_o,
-- ine0o => ine_o,
-- overflow0o => overflow_o,
-- underflow0o => underflow_o,
-- div0zero0o => div_zero_o,
-- inf0o => inf_o,
-- zero0o => zero_o,
-- qnan0o => qnan_o,
-- snan0o => snan_o,
-- start0i => start_i,
-- ready0o => ready_o);
i_fpu : fpu port map (
clk_i => clk_i,
opa_i => opa_i,
opb_i => opb_i,
fpu_op_i => fpu_op_i,
rmode_i => rmode_i,
output_o => output_o,
ine_o => ine_o,
overflow_o => overflow_o,
underflow_o => underflow_o,
div_zero_o => div_zero_o,
inf_o => inf_o,
zero_o => zero_o,
qnan_o => qnan_o,
snan_o => snan_o,
start_i => start_i,
ready_o => ready_o);
---------------------------------------------------------------------------
-- toggle clock
---------------------------------------------------------------------------
clk_i <= not(clk_i) after 30 ns;
verify : process
--The operands and results are in Hex format. The test vectors must be placed in a strict order for the verfication to work.
file testcases_file : text open read_mode is "testcases_mul.txt"; --Name of the file containing the test cases.
variable file_line : line;
variable str_in : string(8 downto 1);
variable str_fpu_op : string(3 downto 1);
variable str_rmode : string(2 downto 1);
begin
---------------------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------SoftFloat test vectors (10000 test cases for each operation) --------------------------------------------------------------------
start_i <= '0';
wait for 10*CLK_PERIOD;
while not endfile(testcases_file) loop
wait for CLK_PERIOD; start_i <= '1';
str_read(testcases_file, str_in);
opa_i <= strhex_to_slv(str_in);
str_read(testcases_file, str_in);
opb_i <= strhex_to_slv(str_in);
str_read(testcases_file, str_fpu_op);
fpu_op_i <= to_std_logic_vector(str_fpu_op);
str_read(testcases_file, str_rmode);
rmode_i <= to_std_logic_vector(str_rmode);
str_read(testcases_file, str_in);
slv_out <= strhex_to_slv(str_in);
wait for CLK_PERIOD; start_i <= '0'; wait until ready_o = '1';
--assert output_o = slv_out
-- report "Error!!!"
-- severity failure;
str_read(testcases_file, str_in);
end loop;
-------- Boundary values-----
start_i <= '0';
-- seeeeeeeefffffffffffffffffffffff
--infinity
wait for CLK_PERIOD; start_i <= '1';
opa_i <= "01111111011111111111111111111111";
opb_i <= "01111111011111111111111111111111";
fpu_op_i <= "000";
rmode_i <= "00";
wait for CLK_PERIOD; start_i <= '0'; wait until ready_o = '1';
assert output_o = "01111111100000000000000000000000"
report "Error!!!"
severity failure;
-- seeeeeeeefffffffffffffffffffffff
-- 1 x1.001 - 1x1.000 = 0x0.001
wait for CLK_PERIOD; start_i <= '1';
opa_i <= "00000000100100000000000000000000";
opb_i <= "10000000100000000000000000000000";
fpu_op_i <= "000";
rmode_i <= "00";
wait for CLK_PERIOD; start_i <= '0'; wait until ready_o = '1';
assert output_o = "00000000000100000000000000000000"
report "Error!!!"
severity failure;
-- seeeeeeeefffffffffffffffffffffff
-- 10 x 1.0001 - 10 x 1.0000 =
wait for CLK_PERIOD; start_i <= '1';
opa_i <= "00000001000010000000000000000000";
opb_i <= "10000001000000000000000000000000";
fpu_op_i <= "000";
rmode_i <= "00";
wait for CLK_PERIOD; start_i <= '0'; wait until ready_o = '1';
assert output_o = "00000000000100000000000000000000"
report "Error!!!"
severity failure;
-- seeeeeeeefffffffffffffffffffffff
-- -0 -0 = -0
wait for CLK_PERIOD; start_i <= '1';
opa_i <= "10000000000000000000000000000000";
opb_i <= "10000000000000000000000000000000";
fpu_op_i <= "000";
rmode_i <= "00";
wait for CLK_PERIOD; start_i <= '0'; wait until ready_o = '1';
assert output_o = "10000000000000000000000000000000"
report "Error!!!"
severity failure;
-- seeeeeeeefffffffffffffffffffffff
-- 0 + x = x
wait for CLK_PERIOD; start_i <= '1';
opa_i <= "00000000000000000000000000000000";
opb_i <= "01000010001000001000000000100000";
fpu_op_i <= "000";
rmode_i <= "00";
wait for CLK_PERIOD; start_i <= '0'; wait until ready_o = '1';
assert output_o = "01000010001000001000000000100000"
report "Error!!!"
severity failure;
while not endfile(testcases_file) loop
wait for CLK_PERIOD; start_i <= '1';
str_read(testcases_file, str_in);
opa_i <= strhex_to_slv(str_in);
str_read(testcases_file, str_in);
opb_i <= strhex_to_slv(str_in);
str_read(testcases_file, str_fpu_op);
fpu_op_i <= to_std_logic_vector(str_fpu_op);
str_read(testcases_file, str_rmode);
rmode_i <= to_std_logic_vector(str_rmode);
str_read(testcases_file, str_in);
slv_out <= strhex_to_slv(str_in);
wait for CLK_PERIOD; start_i <= '0'; wait until ready_o = '1';
--assert output_o = slv_out
-- report "Error!!!"
-- severity failure;
str_read(testcases_file, str_in);
end loop;
----------------------------------------------------------------------------------------------------------------------------------------------------
assert false
report "Success!!!.......Yahoooooooooooooo"
severity failure;
wait;
end process verify;
end rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity graphics is
Port ( CLK50 : in STD_LOGIC;
CLK12 : in STD_LOGIC;
CS : in STD_LOGIC;
RW : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (13 downto 0);
Din : in STD_LOGIC_VECTOR (15 downto 0);
Dout : out STD_LOGIC_VECTOR (15 downto 0) := x"0000";
INT : out STD_LOGIC := '0';
IAK : in STD_LOGIC;
VBLANK : in STD_LOGIC;
VRAM0Read : out STD_LOGIC;
VRAM1Read : out STD_LOGIC;
VRAM2Read : out STD_LOGIC;
VRAM3Read : out STD_LOGIC;
VRAM4Read : out STD_LOGIC;
VRAM0Write : out STD_LOGIC;
VRAM1Write : out STD_LOGIC;
VRAM2Write : out STD_LOGIC;
VRAM3Write : out STD_LOGIC;
VRAM4Write : out STD_LOGIC;
VRAMAddr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM0DataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM1DataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM2DataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM3DataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM4DataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAMDataOut : out STD_LOGIC_VECTOR ( 8 downto 0);
SprRD : out STD_LOGIC;
SprWR : out STD_LOGIC;
SprAddr : out STD_LOGIC_VECTOR ( 7 downto 0);
SprDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
SprDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
PalRD : out STD_LOGIC;
PalWR : out STD_LOGIC;
PalAddr : out STD_LOGIC_VECTOR ( 4 downto 0);
PalDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
PalDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
ROW_BASE : out STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
CURSOR_ROW : out STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
CURSOR_COL : out STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
PPU_CTRL : out STD_LOGIC_VECTOR (15 downto 0) := x"0000";
PPU_HSCR : out STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
PPU_VSCR : out STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
MODE : out STD_LOGIC);
end graphics;
architecture Behavioral of graphics is
signal LASTCS : STD_LOGIC := '0';
signal LASTVBLANK : STD_LOGIC := '0';
signal LASTVBLANK2 : STD_LOGIC := '0';
-- general registers
signal ROW_BASE_REG : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal CURSOR_ROW_REG : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal CURSOR_COL_REG : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal MODE_REG : STD_LOGIC := '0';
-- PPU registers
signal PPU_CTRL_REG : STD_LOGIC_VECTOR (15 downto 0) := x"0000";
signal PPU_HSCR_REG : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal PPU_VSCR_REG : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal PPU_ADDR_REG : STD_LOGIC_VECTOR (15 downto 0) := x"0000";
signal PPU_SMA_REG : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal PPU_HIT_REG : STD_LOGIC := '0';
signal PPU_VBLANK_REG : STD_LOGIC := '0';
signal PPU_FF : STD_LOGIC := '0';
begin
process (CLK12)
procedure ppu_mem_access(write : in STD_LOGIC;
data : in STD_LOGIC_VECTOR(7 downto 0)) is
begin
case PPU_ADDR_REG(13 downto 12) is
when "00" =>
-- ram0 and ram1
if (PPU_ADDR_REG(3) = '0') then
VRAM0Read <= NOT write;
VRAM0Write <= write;
else
VRAM1Read <= NOT write;
VRAM1Write <= write;
end if;
VRAMAddr <= PPU_ADDR_REG(11 downto 4) &
PPU_ADDR_REG( 2 downto 0);
VRAMDataOut <= "0" & data;
when "01" =>
-- ram2 and ram3
if (PPU_ADDR_REG(3) = '0') then
VRAM2Read <= NOT write;
VRAM2Write <= write;
else
VRAM3Read <= NOT write;
VRAM3Write <= write;
end if;
VRAMAddr <= PPU_ADDR_REG(11 downto 4) &
PPU_ADDR_REG( 2 downto 0);
VRAMDataOut <= "0" & data;
when "10" =>
-- ram4 (namtabs)
VRAM4Read <= NOT write;
VRAM4Write <= write;
VRAMAddr <= PPU_ADDR_REG(10 downto 0);
VRAMDataOut <= "0" & data;
when "11" =>
-- palette
if (PPU_ADDR_REG(13 downto 8) = "111111") then
if (PPU_ADDR_REG(3 downto 0) = "0000") then
PalAddr <= "00000";
else
PalAddr <= PPU_ADDR_REG(4 downto 0);
end if;
if (write = '0') then
PalRD <= '1';
else
PalWR <= '1';
PalDataOut <= data;
end if;
end if;
when others =>
end case;
if (PPU_CTRL_REG(2) = '1') then
-- vertical write
PPU_ADDR_REG <=
conv_std_logic_vector(conv_integer(PPU_ADDR_REG) + 32, 16);
else
PPU_ADDR_REG <=
conv_std_logic_vector(conv_integer(PPU_ADDR_REG) + 1, 16);
end if;
end ppu_mem_access;
begin
if (CLK12 = '0' and CLK12'event ) then
if (CS = '1') then
if (MODE_REG = '1' and RW='1' and LASTCS='0') then
-- write
case A(2 downto 0) is
when "000" =>
-- control 1
PPU_CTRL_REG( 7 downto 0) <= Din(7 downto 0);
when "001" =>
-- control 2
PPU_CTRL_REG(15 downto 8) <= Din(7 downto 0);
when "010" =>
-- status
when "011" =>
-- Sprite Memory Address
PPU_SMA_REG <= Din(7 downto 0);
when "100" =>
-- Sprite Memory Data
SprWR <= '1';
SprAddr <= PPU_SMA_REG;
SprDataOut <= Din(7 downto 0);
PPU_SMA_REG <= conv_std_logic_vector(
conv_integer(
unsigned(PPU_SMA_REG))+1,8);
when "101" =>
-- scroll data
if (PPU_FF = '0') then
-- horizontal scroll
PPU_HSCR_REG <= Din(7 downto 0);
else
-- vertical scroll
PPU_VSCR_REG <= Din(7 downto 0);
end if;
PPU_FF <= NOT PPU_FF;
when "110" =>
-- address
if (PPU_FF = '0') then
PPU_ADDR_REG(13 downto 8) <= Din(5 downto 0);
else
PPU_ADDR_REG( 7 downto 0) <= Din(7 downto 0);
end if;
PPU_FF <= NOT PPU_FF;
when "111" =>
-- data
ppu_mem_access('1', Din(7 downto 0));
when others =>
end case;
elsif (MODE_REG = '1' and RW='0' and LASTCS = '0') then
-- read
case A(2 downto 0) is
when "000" =>
-- control 1 - illegal read
when "001" =>
-- control 2 - illegal read
when "010" =>
-- status
Dout(6) <= PPU_HIT_REG;
Dout(7) <= PPU_VBLANK_REG;
PPU_VBLANK_REG <= '0';
PPU_FF <= '0';
when "011" =>
-- Sprite Memory Address - illegal read
when "100" =>
-- TODO: Sprite Memory Data
when "101" =>
-- scroll offset - illegal read
when "110" =>
-- address - illegal
when "111" =>
-- data
ppu_mem_access('0', x"00");
when others =>
end case;
elsif (A = "0" & x"FFC" & "0") then
MODE_REG <= Din(0);
elsif (A = "0" & x"FFD" & "0") then
ROW_BASE_REG <= Din(7 downto 0);
elsif (A = "0" & x"FFE" & "0") then
CURSOR_ROW_REG <= Din(7 downto 0);
elsif (A = "0" & x"FFF" & "0") then
CURSOR_COL_REG <= Din(7 downto 0);
else
-- access to any other address
if (MODE_REG = '0' and LASTCS = '0') then
VRAM0Read <= (NOT RW) and (NOT A(1)) and (NOT A(13));
VRAM1Read <= (NOT RW) and ( A(1)) and (NOT A(13));
VRAM2Read <= (NOT RW) and (NOT A(1)) and ( A(13));
VRAM3Read <= (NOT RW) and ( A(1)) and ( A(13));
VRAM0Write <= ( RW) and (NOT A(1)) and (NOT A(13));
VRAM1Write <= ( RW) and ( A(1)) and (NOT A(13));
VRAM2Write <= ( RW) and (NOT A(1)) and ( A(13));
VRAM3Write <= ( RW) and ( A(1)) and ( A(13));
VRAMAddr(10 downto 0) <= A(12 downto 2);
VRAMDataOut <= Din(8 downto 0);
end if;
if (MODE_REG = '0' or (RW='0' and A(2 downto 0)="111")) then
Dout(8 downto 0) <= VRAM0DataIn or VRAM1DataIn or
VRAM2DataIn or VRAM3DataIn or
VRAM4DataIn;
end if;
end if;
else
VRAM0Read <= '0';
VRAM1Read <= '0';
VRAM2Read <= '0';
VRAM3Read <= '0';
VRAM4Read <= '0';
VRAM0Write <= '0';
VRAM1Write <= '0';
VRAM2Write <= '0';
VRAM3Write <= '0';
VRAM4Write <= '0';
SprRD <= '0';
SprWR <= '0';
PalRD <= '0';
PalWR <= '0';
Dout <= x"0000";
SprAddr <= x"00";
SprDataOut <= x"00";
PalAddr <= "00000";
PalDataOut <= x"00";
if (VBLANK /= LASTVBLANK) then
PPU_VBLANK_REG <= VBLANK;
end if;
LASTVBLANK <= VBLANK;
end if;
LASTCS <= CS;
end if;
end process;
process (CLK50)
begin
if (CLK50 = '0' and CLK50'event ) then
LASTVBLANK2 <= VBLANK;
if (IAK = '1') then
INT <= '0';
elsif (VBLANK /= LASTVBLANK2) then
if (VBLANK = '1' and PPU_CTRL_REG(7) = '1') then
-- generate interrupt
INT <= '1';
end if;
end if;
end if;
end process;
ROW_BASE <= ROW_BASE_REG;
CURSOR_ROW <= CURSOR_ROW_REG;
CURSOR_COL <= CURSOR_COL_REG;
MODE <= MODE_REG;
PPU_CTRL <= PPU_CTRL_REG;
PPU_HSCR <= PPU_HSCR_REG;
PPU_VSCR <= PPU_VSCR_REG;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Tue Mar 30 18:39:52 2004
-- cmd: H:\work\mix_new\MIX\mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a.vhd,v 1.1 2004/04/06 11:19:52 wig Exp $
-- $Date: 2004/04/06 11:19:52 $
-- $Log: inst_a_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 11:19:52 wig
-- Adding result/autoopen
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.39 2004/03/30 11:05:58 wig Exp
--
-- Generator: mix_0.pl Revision: 1.28 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_aa_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_aa_e
p_mix_s_ai14_go : out std_ulogic_vector(7 downto 0);
p_mix_s_ai16_gi : in std_ulogic_vector(7 downto 0);
p_mix_s_ai6_go : out std_ulogic;
p_mix_s_ai8_gi : in std_ulogic;
p_mix_s_aio17_gc : inout std_ulogic;
p_mix_s_aio18_gc : inout std_ulogic;
p_mix_s_aio19_gc : inout std_ulogic;
p_mix_s_ao10_go : out std_ulogic_vector(7 downto 0);
p_mix_s_ao11_go : out std_ulogic_vector(7 downto 0);
p_mix_s_ao12_gi : in std_ulogic_vector(7 downto 0);
p_mix_s_ao13_gi : in std_ulogic_vector(7 downto 0);
p_mix_s_ao1_go : out std_ulogic;
p_mix_s_ao2_go : out std_ulogic;
p_mix_s_ao3_go : out std_ulogic;
p_mix_s_ao4_gi : in std_ulogic;
p_mix_s_ao5_go : out std_ulogic;
p_mix_s_ao9_go : out std_ulogic_vector(7 downto 0);
port_aa : out std_ulogic
-- End of Generated Port for Entity inst_aa_e
);
end component;
-- ---------
component inst_ab_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ab_e
s_ao10 : in std_ulogic_vector(7 downto 0);
s_ao2 : in std_ulogic
-- End of Generated Port for Entity inst_ab_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal s_aio17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_ao10 : std_ulogic_vector(7 downto 0);
signal s_ao11 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_ao2 : std_ulogic;
signal s_ao3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
-- __I_OUT_OPEN signal s_intname : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
s_aio17 <= p_mix_s_aio17_gc; -- __I_I_BIT_PORT
p_mix_s_ao11_go <= s_ao11; -- __I_O_BUS_PORT
p_mix_s_ao3_go <= s_ao3; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_aa
inst_aa: inst_aa_e
port map (
p_mix_s_ai14_go => s_ai14,
p_mix_s_ai16_gi => s_ai16,
p_mix_s_ai6_go => s_ai6,
p_mix_s_ai8_gi => s_ai8,
p_mix_s_aio17_gc => s_aio17,
p_mix_s_aio18_gc => s_aio18,
p_mix_s_aio19_gc => s_aio19,
p_mix_s_ao10_go => s_ao10,
p_mix_s_ao11_go => s_ao11,
p_mix_s_ao12_gi => s_ao12,
p_mix_s_ao13_gi => s_ao13,
p_mix_s_ao1_go => s_ao1,
p_mix_s_ao2_go => s_ao2,
p_mix_s_ao3_go => s_ao3,
p_mix_s_ao4_gi => s_ao4,
p_mix_s_ao5_go => s_ao5,
p_mix_s_ao9_go => s_ao9,
-- __I_RECONN port_aa => open, -- __I_OUT_OPEN
port_aa => s_outname
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: inst_ab_e
port map (
s_ao10 => s_ao10,
s_ao2 => s_ao2
);
-- End of Generated Instance Port Map for inst_ab
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
-- Module Name: colour_space_conversion - Behavioral
--
-- Description: Convert the input pixel data into YCbCr 422 values
--
-- Feel free to use this how you see fit, and fix any errors you find :-)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity colour_space_conversion is
Port ( clk : in STD_LOGIC;
r1_in : IN std_logic_vector(8 downto 0);
g1_in : IN std_logic_vector(8 downto 0);
b1_in : IN std_logic_vector(8 downto 0);
r2_in : IN std_logic_vector(8 downto 0);
g2_in : IN std_logic_vector(8 downto 0);
b2_in : IN std_logic_vector(8 downto 0);
pair_start_in: IN std_logic;
de_in : IN std_logic;
vsync_in : IN std_logic;
hsync_in : IN std_logic;
y_out : OUT std_logic_vector(7 downto 0);
c_out : OUT std_logic_vector(7 downto 0);
de_out : OUT std_logic;
hsync_out : OUT std_logic;
vsync_out : OUT std_logic
);
end colour_space_conversion;
architecture Behavioral of colour_space_conversion is
signal d_a : std_logic;
signal h_a : std_logic;
signal v_a : std_logic;
signal c1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
signal a_r1, a_g1, a_b1 : STD_LOGIC_VECTOR(29 DOWNTO 0);
signal b_r1, b_g1, b_b1 : STD_LOGIC_VECTOR(17 DOWNTO 0);
signal pc_r1, pc_g1, p_b1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
signal c2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
signal a_r2, a_g2 , a_b2 : STD_LOGIC_VECTOR(29 DOWNTO 0);
signal b_r2, b_g2, b_b2 : STD_LOGIC_VECTOR(17 DOWNTO 0);
signal pc_r2, pc_g2, p_b2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
signal hs_delay : STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
signal vs_delay : STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
signal de_delay : STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
begin
-- y = ( 8432 * r + 16425 * g + 3176 * B) / 32768 + 16;
-- cb = (-4818 * r - 9527 * g + 14345 * B) / 32768 + 128;
-- cr = (14345 * r - 12045 * g - 2300 * B) / 32768 + 128;
c1 <= x"002000000000";
a_r1 <= "000000" & r1_in & x"000" & "000";
a_g1 <= "000000" & g1_in & x"000" & "000";
a_b1 <= "000000" & b1_in & x"000" & "000";
c2 <= x"010000000000";
a_r2 <= "000000" & r2_in & x"000" & "000";
a_g2 <= "000000" & g2_in & x"000" & "000";
a_b2 <= "000000" & b2_in & x"000" & "000";
b_r1 <= x"20F0"&"00";
b_g1 <= x"4029"&"00";
b_b1 <= x"0C68"&"00";
b_r2 <= x"ED2E"&"00" when pair_start_in = '1' else x"3809"&"00";
b_g2 <= x"DAC9"&"00" when pair_start_in = '1' else x"D0F3"&"00";
b_b2 <= x"3809"&"00" when pair_start_in = '1' else x"F704"&"00";
process(clk)
begin
if rising_edge(clk) then
hsync_out <= hs_delay(hs_delay'high);
vsync_out <= vs_delay(vs_delay'high);
de_out <= de_delay(de_delay'high);
de_delay <= de_delay(de_delay'high-1 downto 0) & de_in;
vs_delay <= vs_delay(de_delay'high-1 downto 0) & vsync_in;
hs_delay <= hs_delay(de_delay'high-1 downto 0) & hsync_in;
y_out <= p_b1(40 downto 33);
c_out <= p_b2(40 downto 33);
end if;
end process;
mult_r1 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 0, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 0, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 0, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 0, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 0, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => PC_r1, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => open, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others => '0'), -- 30-bit input: A cascade data input
BCIN => (others => '0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => (others => '0'), -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
CLK => CLK, -- 1-bit input: Clock input
ALUMODE => "0000", -- 4-bit input: ALU control input
CARRYINSEL => "000", -- 3-bit input: Carry select input
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
INMODE => "00000", -- 5-bit input: INMODE control input
OPMODE => "0110101", -- 7-bit input: Operation mode input
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
-- Data: 30-bit (each) input: Data Ports
A => a_r1, -- 30-bit input: A data input
B => b_r1, -- 18-bit input: B data input
C => c1, -- 48-bit input: C data input
CARRYIN => '0', -- 1-bit input: Carry input signal
D => (others =>'0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '0', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '0', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '0', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '0', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '0', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '0', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '0', -- 1-bit input: Clock enable input for DREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
mult_g1 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 1, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 0, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) input: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => PC_g1, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => open, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others => '0'), -- 30-bit input: A cascade data input
BCIN => (others => '0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => pc_r1, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
CLK => CLK, -- 1-bit input: Clock input
ALUMODE => "0000", -- 4-bit input: ALU control input
CARRYINSEL => "000", -- 3-bit input: Carry select input
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
INMODE => "00000", -- 5-bit input: INMODE control input
OPMODE => "0010101", -- 7-bit input: Operation mode input
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
-- Data: 30-bit (each) input: Data Ports
A => a_g1, -- 30-bit input: A data input
B => b_g1, -- 18-bit input: B data input
C => (others =>'0'), -- 48-bit input: C data input
CARRYIN => '0', -- 1-bit input: Carry input signal
D => (others =>'0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '0', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '1', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '0', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '0', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '0', -- 1-bit input: Clock enable input for DREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
mult_b1 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 2, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 2, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 0, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => open, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => P_b1, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others =>'0'), -- 30-bit input: A cascade data input
BCIN => (others =>'0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => pc_g1, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
CLK => CLK, -- 1-bit input: Clock input
ALUMODE => "0000", -- 4-bit input: ALU control input
CARRYINSEL => "000", -- 3-bit input: Carry select input
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
INMODE => "00000", -- 5-bit input: INMODE control input
OPMODE => "0010101", -- 7-bit input: Operation mode input
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
-- Data: 30-bit (each) input: Data Ports
A => a_b1, -- 30-bit input: A data input
B => b_b1, -- 18-bit input: B data input
C => (others =>'0'), -- 48-bit input: C data input
CARRYIN => '0', -- 1-bit input: Carry input signal
D => (others =>'0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '1', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '0', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '0', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '0', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '0', -- 1-bit input: Clock enable input for DREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
-----------------------------------------
mult_r2 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 0, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 0, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 0, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 0, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 0, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => PC_r2, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => open, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others => '0'), -- 30-bit input: A cascade data input
BCIN => (others => '0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => (others => '0'), -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
CLK => CLK, -- 1-bit input: Clock input
ALUMODE => "0000", -- 4-bit input: ALU control input
CARRYINSEL => "000", -- 3-bit input: Carry select input
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
INMODE => "00000", -- 5-bit input: INMODE control input
OPMODE => "0110101", -- 7-bit input: Operation mode input
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
-- Data: 30-bit (each) input: Data Ports
A => a_r2, -- 30-bit input: A data input
B => b_r2, -- 18-bit input: B data input
C => c2, -- 48-bit input: C data input
CARRYIN => '0', -- 1-bit input: Carry input signal
D => (others =>'0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '0', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '0', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '0', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '0', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '0', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '0', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '0', -- 1-bit input: Clock enable input for DREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
mult_g2 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 1, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 0, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => PC_g2, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => open, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others=>'0'), -- 30-bit input: A cascade data input
BCIN => (others=>'0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => pc_r2, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
CLK => CLK, -- 1-bit input: Clock input
ALUMODE => "0000", -- 4-bit input: ALU control input
CARRYINSEL => "000", -- 3-bit input: Carry select input
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
INMODE => "00000", -- 5-bit input: INMODE control input
OPMODE => "0010101", -- 7-bit input: Operation mode input
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
-- Data: 30-bit (each) input: Data Ports
A => a_g2, -- 30-bit input: A data input
B => b_g2, -- 18-bit input: B data input
C => (others =>'0'), -- 48-bit input: C data input
CARRYIN => '0', -- 1-bit input: Carry input signal
D => (others =>'0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '0', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '0', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '0', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '0', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '0', -- 1-bit input: Clock enable input for DREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
mult_b2 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 2, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 2, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 2, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 2, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 0, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => open, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => P_b2, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others =>'0'), -- 30-bit input: A cascade data input
BCIN => (others =>'0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => pc_g2, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
CLK => CLK, -- 1-bit input: Clock input
ALUMODE => "0000", -- 4-bit input: ALU control input
CARRYINSEL => "000", -- 3-bit input: Carry select input
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
INMODE => "00000", -- 5-bit input: INMODE control input
OPMODE => "0010101", -- 7-bit input: Operation mode input
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
-- Data: 30-bit (each) input: Data Ports
A => a_b2, -- 30-bit input: A data input
B => b_b2, -- 18-bit input: B data input
C => (others =>'0'), -- 48-bit input: C data input
CARRYIN => '0', -- 1-bit input: Carry input signal
D => (others =>'0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '1', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '0', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '1', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '0', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '0', -- 1-bit input: Clock enable input for DREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
end Behavioral; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: memctrl
-- File: memctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory controller package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package memctrl is
type memory_in_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bwidth : std_logic_vector(1 downto 0);
sd : std_logic_vector(63 downto 0);
cb : std_logic_vector(7 downto 0);
scb : std_logic_vector(7 downto 0);
edac : std_logic;
end record;
type memory_out_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
sddata : std_logic_vector(63 downto 0);
ramsn : std_logic_vector(7 downto 0);
ramoen : std_logic_vector(7 downto 0);
ramn : std_ulogic;
romn : std_ulogic;
mben : std_logic_vector(3 downto 0);
iosn : std_logic;
romsn : std_logic_vector(7 downto 0);
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bdrive : std_logic_vector(3 downto 0);
vbdrive : std_logic_vector(31 downto 0); --vector bus drive
svbdrive : std_logic_vector(63 downto 0); --vector bus drive sdram
read : std_logic;
sa : std_logic_vector(14 downto 0);
cb : std_logic_vector(7 downto 0);
scb : std_logic_vector(7 downto 0);
vcdrive : std_logic_vector(7 downto 0); --vector bus drive cb
svcdrive : std_logic_vector(7 downto 0); --vector bus drive cb sdram
ce : std_ulogic;
end record;
type sdctrl_in_type is record
wprot : std_ulogic;
data : std_logic_vector (127 downto 0); -- data in
cb : std_logic_vector(15 downto 0);
end record;
type sdctrl_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 15 downto 0); -- data i/o mask
bdrive : std_ulogic; -- bus drive
qdrive : std_ulogic; -- bus drive
vbdrive : std_logic_vector(31 downto 0); -- vector bus drive
address : std_logic_vector (16 downto 2); -- address out
data : std_logic_vector (127 downto 0); -- data out
cb : std_logic_vector(15 downto 0);
ce : std_ulogic;
ba : std_logic_vector ( 1 downto 0); -- bank address
cal_en : std_logic_vector(7 downto 0); -- enable delay calibration
cal_inc : std_logic_vector(7 downto 0); -- inc/dec delay
cal_rst : std_logic; -- calibration reset
odt : std_logic_vector(1 downto 0);
end record;
type sdram_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 7 downto 0); -- data i/o mask
end record;
component sdctrl
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
oepol : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ftsdctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
edacen : integer := 1;
errcnt : integer := 0;
cntbits : integer range 1 to 8 := 1;
oepol : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component srctrl
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
prom8en : integer := 0;
oepol : integer := 0;
srbanks : integer range 1 to 5 := 1;
banksz : integer range 0 to 13 := 13;
romasel : integer range 0 to 28 := 19
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
component ftsrctrl is
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
rombanks : integer range 1 to 8 := 1;
rombanksz : integer range 0 to 15 := 15;
rombankszdef : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 0;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0;
prom8en : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
type sdram_in_type is record
haddr : std_logic_vector(31 downto 0); -- memory address
rhaddr : std_logic_vector(31 downto 0); -- latched memory address
hready : std_ulogic;
hsize : std_logic_vector(1 downto 0);
hsel : std_ulogic;
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
rhtrans : std_logic_vector(1 downto 0);
nhtrans : std_logic_vector(1 downto 0);
idle : std_ulogic;
enable : std_ulogic;
error : std_ulogic;
brmw : std_ulogic;
edac : std_ulogic;
srdis : std_logic;
end record;
type sdram_mctrl_out_type is record
address : std_logic_vector(16 downto 2);
busy : std_ulogic;
aload : std_ulogic;
bdrive : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
bsel : std_ulogic;
hresp : std_logic_vector (1 downto 0);
vhready : std_ulogic;
prdata : std_logic_vector (31 downto 0);
end record;
type wprot_out_type is record
wprothit : std_ulogic;
end record;
component sdmctrl
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end component;
component ftsdmctrl
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
syncrst : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end component;
component ftmctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
edac : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
writefb : integer := 0;
netlist : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end component;
component ssrctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
paddr : integer := 0;
pmask : integer := 16#fff#;
oepol : integer := 0;
bus16 : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type
);
end component;
type ddrmem_in_type is record
cke : std_ulogic;
cs : std_logic_vector(1 downto 0);
control : std_logic_vector(2 downto 0); --RAS,CAS,WE
ba : std_logic_vector(1 downto 0);
adr : std_logic_vector(13 downto 0);
dq : std_logic_vector(63 downto 0);
dm : std_logic_vector(15 downto 0);
dqs : std_logic_vector(15 downto 0);
dq_oe : std_logic_vector(63 downto 0);
dqs_oe : std_logic_vector(15 downto 0);
end record;
type ddrmem_out_type is record
dq : std_logic_vector(63 downto 0);
dqs : std_logic_vector(15 downto 0);
end record;
component ddrctrl
generic (
hindex1 : integer := 0;
haddr1 : integer := 0;
hmask1 : integer := 16#f80#;
hindex2 : integer := 0;
haddr2 : integer := 0;
hmask2 : integer := 16#f80#;
pindex : integer := 3;
paddr : integer := 0;
numahb : integer := 1; -- Allowed: 1, 2
ahb1sepclk : integer := 0; -- Allowed: 0, 1
ahb2sepclk : integer := 0; -- Allowed: 0, 1
modbanks : integer := 1; -- Allowed: 1, 2
numchips : integer := 8; -- Allowed: 1, 2, 4, 8, 16
chipbits : integer := 8; -- Allowed: 4, 8, 16
chipsize : integer := 128; -- Allowed: 64, 128, 256, 512, 1024 (MB)
plldelay : integer := 0; -- Allowed: 0, 1 (Use 200us start up delay)
tech : integer := 0;
clkperiod : integer := 10); -- 100 Mhz
port (
rst : in std_ulogic;
clk0 : in std_ulogic;
clk90 : in std_ulogic;
clk180 : in std_ulogic;
clk270 : in std_ulogic;
hclk1 : in std_ulogic;
hclk2 : in std_ulogic;
pclk : in std_ulogic;
ahb1si : in ahb_slv_in_type;
ahb1so : out ahb_slv_out_type;
ahb2si : in ahb_slv_in_type;
ahb2so : out ahb_slv_out_type;
apbsi : in apb_slv_in_type;
apbso : out apb_slv_out_type;
-- dapbso : out apb_slv_out_type;
ddsi : out ddrmem_in_type;
ddso : in ddrmem_out_type);
end component;
component ftsrctrl_v1
generic (
hindex: Integer := 1;
romaddr: Integer := 16#000#;
rommask: Integer := 16#ff0#;
ramaddr: Integer := 16#400#;
rammask: Integer := 16#ff0#;
ioaddr: Integer := 16#200#;
iomask: Integer := 16#ff0#;
ramws: Integer := 0;
romws: Integer := 0;
iows: Integer := 0;
rmw: Integer := 1;
srbanks: Integer range 1 to 8 := 8;
banksz: Integer range 0 to 13 := 0;
rombanks: Integer range 1 to 8 := 8;
rombanksz: Integer range 0 to 13 := 0;
rombankszdef: Integer range 0 to 13 := 6;
romasel: Integer range 0 to 28 := 0;
pindex: Integer := 0;
paddr: Integer := 16#000#;
pmask: Integer := 16#fff#;
edacen: Integer range 0 to 1 := 1;
errcnt: Integer range 0 to 1 := 0;
cntbits: Integer range 1 to 8 := 1;
wsreg: Integer := 1;
oepol: Integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
component ddrsp
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbit : integer := 256;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddrsp64a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddrsp32a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddrsp16a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clkread : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddrspa
generic (
fabtech : integer := 0;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits-1 downto 0) -- ddr data
);
end component;
component ddr2sp16a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddr2sp32a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddr2sp64a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddr2spa
generic (
fabtech : integer := 0;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50;
readdly : integer := 1;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clkref200 : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
-- ddr_clk_fb_out : out std_logic;
-- ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0)
);
end component;
component ddr_phy
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkread : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
sdi : out sdctrl_in_type;
sdo : in sdctrl_out_type);
end component;
component ddr2_phy
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
sdi : out sdctrl_in_type;
sdo : in sdctrl_out_type);
end component;
component ftsrctrl8 is
generic (
hindex : integer := 0;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
iows : integer := 2;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 1;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type
);
end component;
end;
|
-- name can be any name chosen for this architecture
-- entity is the name of the entity previously defined
ARCHITECTURE name OF entity IS
-- Signal, component, type and constant declarations go here
...
BEGIN
-- Concurrent statements and processes go here
...
END name;
|
library verilog;
use verilog.vl_types.all;
entity Transmit is
port(
Transmit_CLK : in vl_logic;
Line_Num : in vl_logic_vector(7 downto 0);
Focus_Num : in vl_logic_vector(1 downto 0);
Pr_Gate : in vl_logic;
RX_Gate : in vl_logic;
Sample_Gate : out vl_logic;
P : out vl_logic_vector(15 downto 0);
N : out vl_logic_vector(15 downto 0);
HV_SW_CLR : out vl_logic;
HV_SW_LE : out vl_logic;
HV_SW_CLK : out vl_logic;
HV_SW_DOUT : out vl_logic;
AX : out vl_logic_vector(3 downto 0);
AY : out vl_logic_vector(2 downto 0);
MT_CS : out vl_logic;
MT_Strobe : out vl_logic;
MT_Data : out vl_logic
);
end Transmit;
|
Subsets and Splits