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--
-- -----------------------------------------------------------------------------
-- Abstract : constants package for the non-levelling AFI PHY sequencer
-- The constant package (alt_mem_phy_constants_pkg) contains global
-- 'constants' which are fixed thoughout the sequencer and will not
-- change (for constants which may change between sequencer
-- instances generics are used)
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg is
-- -------------------------------
-- Register number definitions
-- -------------------------------
constant c_max_mode_reg_index : natural := 13; -- number of MR bits..
-- Top bit of vector (i.e. width -1) used for address decoding :
constant c_debug_reg_addr_top : natural := 3;
constant c_mmi_access_codeword : std_logic_vector(31 downto 0) := X"00D0_0DEB"; -- to check for legal Avalon interface accesses
-- Register addresses.
constant c_regofst_cal_status : natural := 0;
constant c_regofst_debug_access : natural := 1;
constant c_regofst_hl_css : natural := 2;
constant c_regofst_mr_register_a : natural := 5;
constant c_regofst_mr_register_b : natural := 6;
constant c_regofst_codvw_status : natural := 12;
constant c_regofst_if_param : natural := 13;
constant c_regofst_if_test : natural := 14; -- pll_phs_shft, ac_1t, extra stuff
constant c_regofst_test_status : natural := 15;
constant c_hl_css_reg_cal_dis_bit : natural := 0;
constant c_hl_css_reg_phy_initialise_dis_bit : natural := 1;
constant c_hl_css_reg_init_dram_dis_bit : natural := 2;
constant c_hl_css_reg_write_ihi_dis_bit : natural := 3;
constant c_hl_css_reg_write_btp_dis_bit : natural := 4;
constant c_hl_css_reg_write_mtp_dis_bit : natural := 5;
constant c_hl_css_reg_read_mtp_dis_bit : natural := 6;
constant c_hl_css_reg_rrp_reset_dis_bit : natural := 7;
constant c_hl_css_reg_rrp_sweep_dis_bit : natural := 8;
constant c_hl_css_reg_rrp_seek_dis_bit : natural := 9;
constant c_hl_css_reg_rdv_dis_bit : natural := 10;
constant c_hl_css_reg_poa_dis_bit : natural := 11;
constant c_hl_css_reg_was_dis_bit : natural := 12;
constant c_hl_css_reg_adv_rd_lat_dis_bit : natural := 13;
constant c_hl_css_reg_adv_wr_lat_dis_bit : natural := 14;
constant c_hl_css_reg_prep_customer_mr_setup_dis_bit : natural := 15;
constant c_hl_css_reg_tracking_dis_bit : natural := 16;
constant c_hl_ccs_num_stages : natural := 17;
-- -----------------------------------------------------
-- Constants for DRAM addresses used during calibration:
-- -----------------------------------------------------
-- the mtp training pattern is x30F5
-- 1. write 0011 0000 and 1100 0000 such that one location will contains 0011 0000
-- 2. write in 1111 0101
-- also require locations containing all ones and all zeros
-- default choice of calibration burst length (overriden to 8 for reads for DDR3 devices)
constant c_cal_burst_len : natural := 4;
constant c_cal_ofs_step_size : natural := 8;
constant c_cal_ofs_zeros : natural := 0 * c_cal_ofs_step_size;
constant c_cal_ofs_ones : natural := 1 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_0 : natural := 2 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_1 : natural := 3 * c_cal_ofs_step_size;
constant c_cal_ofs_xF5 : natural := 5 * c_cal_ofs_step_size;
constant c_cal_ofs_wd_lat : natural := 6 * c_cal_ofs_step_size;
constant c_cal_data_len : natural := c_cal_ofs_wd_lat + c_cal_ofs_step_size;
constant c_cal_ofs_mtp : natural := 6*c_cal_ofs_step_size;
constant c_cal_ofs_mtp_len : natural := 4*4;
constant c_cal_ofs_01_pairs : natural := 2 * c_cal_burst_len;
constant c_cal_ofs_10_pairs : natural := 3 * c_cal_burst_len;
constant c_cal_ofs_1100_step : natural := 4 * c_cal_burst_len;
constant c_cal_ofs_0011_step : natural := 5 * c_cal_burst_len;
-- -----------------------------------------------------
-- Reset values. - These are chosen as default values for one PHY variation
-- with DDR2 memory and CAS latency 6, however in each calibration
-- mode these values will be set for a given PHY configuration.
-- -----------------------------------------------------
constant c_default_rd_lat : natural := 20;
constant c_default_wr_lat : natural := 5;
-- -----------------------------------------------------
-- Errorcodes
-- -----------------------------------------------------
-- implemented
constant C_SUCCESS : natural := 0;
constant C_ERR_RESYNC_NO_VALID_PHASES : natural := 5; -- No valid data-valid windows found
constant C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS : natural := 6; -- Multiple equally-sized data valid windows
constant C_ERR_RESYNC_NO_INVALID_PHASES : natural := 7; -- No invalid data-valid windows found. Training patterns are designed so that there should always be at least one invalid phase.
constant C_ERR_CRITICAL : natural := 15; -- A condition that can't happen just happened.
constant C_ERR_READ_MTP_NO_VALID_ALMT : natural := 23;
constant C_ERR_READ_MTP_BOTH_ALMT_PASS : natural := 24;
constant C_ERR_WD_LAT_DISAGREEMENT : natural := 22; -- MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS copies of write-latency are written to memory. If all of these are not the same this error is generated.
constant C_ERR_MAX_RD_LAT_EXCEEDED : natural := 25;
constant C_ERR_MAX_TRK_SHFT_EXCEEDED : natural := 26;
-- not implemented yet
constant c_err_ac_lat_some_beats_are_different : natural := 1; -- implies DQ_1T setup failure or earlier.
constant c_err_could_not_find_read_lat : natural := 2; -- dodgy RDP setup
constant c_err_could_not_find_write_lat : natural := 3; -- dodgy WDP setup
constant c_err_clock_cycle_iteration_timeout : natural := 8; -- depends on srate calling error -- GENERIC
constant c_err_clock_cycle_it_timeout_rdp : natural := 9;
constant c_err_clock_cycle_it_timeout_rdv : natural := 10;
constant c_err_clock_cycle_it_timeout_poa : natural := 11;
constant c_err_pll_ack_timeout : natural := 13;
constant c_err_WindowProc_multiple_rsc_windows : natural := 16;
constant c_err_WindowProc_window_det_no_ones : natural := 17;
constant c_err_WindowProc_window_det_no_zeros : natural := 18;
constant c_err_WindowProc_undefined : natural := 19; -- catch all
constant c_err_tracked_mmc_offset_overflow : natural := 20;
constant c_err_no_mimic_feedback : natural := 21;
constant c_err_ctrl_ack_timeout : natural := 32;
constant c_err_ctrl_done_timeout : natural := 33;
-- -----------------------------------------------------
-- PLL phase locations per device family
-- (unused but a limited set is maintained here for reference)
-- -----------------------------------------------------
constant c_pll_resync_phs_select_ciii : natural := 5;
constant c_pll_mimic_phs_select_ciii : natural := 4;
constant c_pll_resync_phs_select_siii : natural := 5;
constant c_pll_mimic_phs_select_siii : natural := 7;
-- -----------------------------------------------------
-- Maximum sizing constraints
-- -----------------------------------------------------
constant C_MAX_NUM_PLL_RSC_PHASES : natural := 32;
-- -----------------------------------------------------
-- IO control Params
-- -----------------------------------------------------
constant c_set_oct_to_rs : std_logic := '0';
constant c_set_oct_to_rt : std_logic := '1';
constant c_set_odt_rt : std_logic := '1';
constant c_set_odt_off : std_logic := '0';
--
end ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : record package for the non-levelling AFI sequencer
-- The record package (alt_mem_phy_record_pkg) is used to combine
-- command and status signals (into records) to be passed between
-- sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr_ctrl_ip_phy_alt_mem_phy_record_pkg is
-- set some maximum constraints to bound natural numbers below
constant c_max_num_dqs_groups : natural := 24;
constant c_max_num_pins : natural := 8;
constant c_max_ranks : natural := 16;
constant c_max_pll_steps : natural := 80;
-- a prefix for all report signals to identify phy and sequencer block
--
constant record_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_record_pkg : ";
type t_family is (
cyclone3,
stratix2,
stratix3
);
-- -----------------------------------------------------------------------
-- the following are required for the non-levelling AFI PHY sequencer block interfaces
-- -----------------------------------------------------------------------
-- admin mode register settings (from mmi block)
type t_admin_ctrl is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
end record;
function defaults return t_admin_ctrl;
-- current admin status
type t_admin_stat is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
init_done : std_logic;
end record;
function defaults return t_admin_stat;
-- mmi to iram ctrl signals
type t_iram_ctrl is record
addr : natural range 0 to 1023;
wdata : std_logic_vector(31 downto 0);
write : std_logic;
read : std_logic;
end record;
function defaults return t_iram_ctrl;
-- broadcast iram status to mmi and dgrb
type t_iram_stat is record
rdata : std_logic_vector(31 downto 0);
done : std_logic;
err : std_logic;
err_code : std_logic_vector(3 downto 0);
init_done : std_logic;
out_of_mem : std_logic;
contested_access : std_logic;
end record;
function defaults return t_iram_stat;
-- codvw status signals from dgrb to mmi block
type t_dgrb_mmi is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record;
function defaults return t_dgrb_mmi;
-- signal to id which block is active
type t_ctrl_active_block is (
idle,
admin,
dgwb,
dgrb,
proc, -- unused in non-levelling AFI sequencer
setup, -- unused in non-levelling AFI sequencer
iram
);
function ret_proc return t_ctrl_active_block;
function ret_dgrb return t_ctrl_active_block;
-- control record for dgwb, dgrb, iram and admin blocks:
-- the possible commands
type t_ctrl_cmd_id is (
cmd_idle,
-- initialisation stages
cmd_phy_initialise,
cmd_init_dram,
cmd_prog_cal_mr,
cmd_write_ihi,
-- calibration stages
cmd_write_btp,
cmd_write_mtp,
cmd_read_mtp,
cmd_rrp_reset,
cmd_rrp_sweep,
cmd_rrp_seek,
cmd_rdv,
cmd_poa,
cmd_was,
-- advertise controller settings and re-configure for customer operation mode.
cmd_prep_adv_rd_lat,
cmd_prep_adv_wr_lat,
cmd_prep_customer_mr_setup,
cmd_tr_due
);
-- which block should execute each command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block;
-- specify command operands as a record
type t_command_op is record
current_cs : natural range 0 to c_max_ranks-1; -- which chip select is being calibrated
single_bit : std_logic; -- current operation should be single bit
mtp_almt : natural range 0 to 1; -- signals mtp alignment to be used for operation
end record;
function defaults return t_command_op;
-- command request record (sent to each block)
type t_ctrl_command is record
command : t_ctrl_cmd_id;
command_op : t_command_op;
command_req : std_logic;
end record;
function defaults return t_ctrl_command;
-- a generic status record for each block
type t_ctrl_stat is record
command_ack : std_logic;
command_done : std_logic;
command_result : std_logic_vector(7 downto 0 );
command_err : std_logic;
end record;
function defaults return t_ctrl_stat;
-- push interface for dgwb / dgrb blocks (only the dgrb uses this interface at present)
type t_iram_push is record
iram_done : std_logic;
iram_write : std_logic;
iram_wordnum : natural range 0 to 511; -- acts as an offset to current location (max = 80 pll steps *2 sweeps and 80 pins)
iram_bitnum : natural range 0 to 31; -- for bitwise packing modes
iram_pushdata : std_logic_vector(31 downto 0); -- only bit zero used for bitwise packing_mode
end record;
function defaults return t_iram_push;
-- control block "master" state machine
type t_master_sm_state is
(
s_reset,
s_phy_initialise, -- wait for dll lock and init done flag from iram
s_init_dram, -- dram initialisation - reset sequence
s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
s_write_ihi, -- write header information in iRAM
s_cal, -- check if calibration to be executed
s_write_btp, -- write burst training pattern
s_write_mtp, -- write more training pattern
s_read_mtp, -- read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
s_rrp_reset, -- read resync phase setup - reset initial conditions
s_rrp_sweep, -- read resync phase setup - sweep phases per chip select
s_rrp_seek, -- read resync phase setup - seek correct phase
s_rdv, -- read data valid setup
s_was, -- write datapath setup (ac to write data timing)
s_adv_rd_lat, -- advertise read latency
s_adv_wr_lat, -- advertise write latency
s_poa, -- calibrate the postamble (dqs based capture only)
s_tracking_setup, -- perform tracking (1st pass to setup mimic window)
s_prep_customer_mr_setup, -- apply user mode register settings (in admin block)
s_tracking, -- perform tracking (subsequent passes in user mode)
s_operational, -- calibration successful and in user mode
s_non_operational -- calibration unsuccessful and in user mode
);
-- record (set in mmi block) to disable calibration states
type t_hl_css_reg is record
phy_initialise_dis : std_logic;
init_dram_dis : std_logic;
write_ihi_dis : std_logic;
cal_dis : std_logic;
write_btp_dis : std_logic;
write_mtp_dis : std_logic;
read_mtp_dis : std_logic;
rrp_reset_dis : std_logic;
rrp_sweep_dis : std_logic;
rrp_seek_dis : std_logic;
rdv_dis : std_logic;
poa_dis : std_logic;
was_dis : std_logic;
adv_rd_lat_dis : std_logic;
adv_wr_lat_dis : std_logic;
prep_customer_mr_setup_dis : std_logic;
tracking_dis : std_logic;
end record;
function defaults return t_hl_css_reg;
-- record (set in ctrl block) to identify when a command has been acknowledged
type t_cal_stage_ack_seen is record
cal : std_logic;
phy_initialise : std_logic;
init_dram : std_logic;
write_ihi : std_logic;
write_btp : std_logic;
write_mtp : std_logic;
read_mtp : std_logic;
rrp_reset : std_logic;
rrp_sweep : std_logic;
rrp_seek : std_logic;
rdv : std_logic;
poa : std_logic;
was : std_logic;
adv_rd_lat : std_logic;
adv_wr_lat : std_logic;
prep_customer_mr_setup : std_logic;
tracking_setup : std_logic;
end record;
function defaults return t_cal_stage_ack_seen;
-- ctrl to mmi block interface (calibration status)
type t_ctrl_mmi is record
master_state_r : t_master_sm_state;
ctrl_calibration_success : std_logic;
ctrl_calibration_fail : std_logic;
ctrl_current_stage_done : std_logic;
ctrl_current_stage : t_ctrl_cmd_id;
ctrl_current_active_block : t_ctrl_active_block;
ctrl_cal_stage_ack_seen : t_cal_stage_ack_seen;
ctrl_err_code : std_logic_vector(7 downto 0);
end record;
function defaults return t_ctrl_mmi;
-- mmi to ctrl block interface (calibration control signals)
type t_mmi_ctrl is record
hl_css : t_hl_css_reg;
calibration_start : std_logic;
tracking_period_ms : natural range 0 to 255;
tracking_orvd_to_10ms : std_logic;
end record;
function defaults return t_mmi_ctrl;
-- algorithm parameterisation (generated in mmi block)
type t_algm_paramaterisation is record
num_phases_per_tck_pll : natural range 1 to c_max_pll_steps;
nominal_dqs_delay : natural range 0 to 4;
pll_360_sweeps : natural range 0 to 15;
nominal_poa_phase_lead : natural range 0 to 7;
maximum_poa_delay : natural range 0 to 15;
odt_enabled : boolean;
extend_octrt_by : natural range 0 to 15;
delay_octrt_by : natural range 0 to 15;
tracking_period_ms : natural range 0 to 255;
end record;
-- interface between mmi and pll to control phase shifting
type t_mmi_pll_reconfig is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
end record;
type t_pll_mmi is record
pll_busy : std_logic;
err : std_logic_vector(1 downto 0);
end record;
-- specify the iram configuration this is default
-- currently always dq_bitwise packing and a write mode of overwrite_ram
type t_iram_packing_mode is (
dq_bitwise,
dq_wordwise
);
type t_iram_write_mode is (
overwrite_ram,
or_into_ram,
and_into_ram
);
type t_ctrl_iram is record
packing_mode : t_iram_packing_mode;
write_mode : t_iram_write_mode;
active_block : t_ctrl_active_block;
end record;
function defaults return t_ctrl_iram;
-- -----------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFI PHY sequencer
-- -----------------------------------------------------------------------
type t_sc_ctrl_if is record
read : std_logic;
write : std_logic;
dqs_group_sel : std_logic_vector( 4 downto 0);
sc_in_group_sel : std_logic_vector( 5 downto 0);
wdata : std_logic_vector(45 downto 0);
op_type : std_logic_vector( 1 downto 0);
end record;
function defaults return t_sc_ctrl_if;
type t_sc_stat is record
rdata : std_logic_vector(45 downto 0);
busy : std_logic;
error_det : std_logic;
err_code : std_logic_vector(1 downto 0);
sc_cap : std_logic_vector(7 downto 0);
end record;
function defaults return t_sc_stat;
type t_element_to_reconfigure is (
pp_t9,
pp_t10,
pp_t1,
dqslb_rsc_phs,
dqslb_poa_phs_ofst,
dqslb_dqs_phs,
dqslb_dq_phs_ofst,
dqslb_dq_1t,
dqslb_dqs_1t,
dqslb_rsc_1t,
dqslb_div2_phs,
dqslb_oct_t9,
dqslb_oct_t10,
dqslb_poa_t7,
dqslb_poa_t11,
dqslb_dqs_dly,
dqslb_lvlng_byps
);
type t_sc_type is (
DQS_LB,
DQS_DQ_DM_PINS,
DQ_DM_PINS,
dqs_dqsn_pins,
dq_pin,
dqs_pin,
dm_pin,
dq_pins
);
type t_sc_int_ctrl is record
group_num : natural range 0 to c_max_num_dqs_groups;
group_type : t_sc_type;
pin_num : natural range 0 to c_max_num_pins;
sc_element : t_element_to_reconfigure;
prog_val : std_logic_vector(3 downto 0);
ram_set : std_logic;
sc_update : std_logic;
end record;
function defaults return t_sc_int_ctrl;
-- -----------------------------------------------------------------------
-- record and functions for instant on mode
-- -----------------------------------------------------------------------
-- ranges on the below are not important because this logic is not synthesised
type t_preset_cal is record
codvw_phase : natural range 0 to 2*c_max_pll_steps;-- rsc phase
codvw_size : natural range 0 to c_max_pll_steps; -- rsc size (unused but reported)
rlat : natural; -- advertised read latency ctl_rlat (in phy clock cycles)
rdv_lat : natural; -- read data valid latency decrements needed (in memory clock cycles)
wlat : natural; -- advertised write latency ctl_wlat (in phy clock cycles)
ac_1t : std_logic; -- address / command 1t delay setting (HR only)
poa_lat : natural; -- poa latency decrements needed (in memory clock cycles)
end record;
-- the below are hardcoded (do not change)
constant c_ddr_default_cl : natural := 3;
constant c_ddr2_default_cl : natural := 6;
constant c_ddr3_default_cl : natural := 6;
constant c_ddr2_default_cwl : natural := 5;
constant c_ddr3_default_cwl : natural := 5;
constant c_ddr2_default_al : natural := 0;
constant c_ddr3_default_al : natural := 0;
constant c_ddr_default_rl : integer := c_ddr_default_cl;
constant c_ddr2_default_rl : integer := c_ddr2_default_cl + c_ddr2_default_al;
constant c_ddr3_default_rl : integer := c_ddr3_default_cl + c_ddr3_default_al;
constant c_ddr_default_wl : integer := 1;
constant c_ddr2_default_wl : integer := c_ddr2_default_cwl + c_ddr2_default_al;
constant c_ddr3_default_wl : integer := c_ddr3_default_cwl + c_ddr3_default_al;
function defaults return t_preset_cal;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal;
--
end ddr_ctrl_ip_phy_alt_mem_phy_record_pkg;
--
package body ddr_ctrl_ip_phy_alt_mem_phy_record_pkg IS
-- -----------------------------------------------------------------------
-- function implementations for the above declarations
-- these are mainly default conditions for records
-- -----------------------------------------------------------------------
function defaults return t_admin_ctrl is
variable output : t_admin_ctrl;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_admin_stat is
variable output : t_admin_stat;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_iram_ctrl is
variable output : t_iram_ctrl;
begin
output.addr := 0;
output.wdata := (others => '0');
output.write := '0';
output.read := '0';
return output;
end function;
function defaults return t_iram_stat is
variable output : t_iram_stat;
begin
output.rdata := (others => '0');
output.done := '0';
output.err := '0';
output.err_code := (others => '0');
output.init_done := '0';
output.out_of_mem := '0';
output.contested_access := '0';
return output;
end function;
function defaults return t_dgrb_mmi is
variable output : t_dgrb_mmi;
begin
output.cal_codvw_phase := (others => '0');
output.cal_codvw_size := (others => '0');
output.codvw_trk_shift := (others => '0');
output.codvw_grt_one_dvw := '0';
return output;
end function;
function ret_proc return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := proc;
return output;
end function;
function ret_dgrb return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := dgrb;
return output;
end function;
function defaults return t_ctrl_iram is
variable output : t_ctrl_iram;
begin
output.packing_mode := dq_bitwise;
output.write_mode := overwrite_ram;
output.active_block := idle;
return output;
end function;
function defaults return t_command_op is
variable output : t_command_op;
begin
output.current_cs := 0;
output.single_bit := '0';
output.mtp_almt := 0;
return output;
end function;
function defaults return t_ctrl_command is
variable output : t_ctrl_command;
begin
output.command := cmd_idle;
output.command_req := '0';
output.command_op := defaults;
return output;
end function;
-- decode which block is associated with which command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block is
begin
case ctrl_cmd_id is
when cmd_idle => return idle;
when cmd_phy_initialise => return idle;
when cmd_init_dram => return admin;
when cmd_prog_cal_mr => return admin;
when cmd_write_ihi => return iram;
when cmd_write_btp => return dgwb;
when cmd_write_mtp => return dgwb;
when cmd_read_mtp => return dgrb;
when cmd_rrp_reset => return dgrb;
when cmd_rrp_sweep => return dgrb;
when cmd_rrp_seek => return dgrb;
when cmd_rdv => return dgrb;
when cmd_poa => return dgrb;
when cmd_was => return dgwb;
when cmd_prep_adv_rd_lat => return dgrb;
when cmd_prep_adv_wr_lat => return dgrb;
when cmd_prep_customer_mr_setup => return admin;
when cmd_tr_due => return dgrb;
when others => return idle;
end case;
end function;
function defaults return t_ctrl_stat is
variable output : t_ctrl_stat;
begin
output.command_ack := '0';
output.command_done := '0';
output.command_err := '0';
output.command_result := (others => '0');
return output;
end function;
function defaults return t_iram_push is
variable output : t_iram_push;
begin
output.iram_done := '0';
output.iram_write := '0';
output.iram_wordnum := 0;
output.iram_bitnum := 0;
output.iram_pushdata := (others => '0');
return output;
end function;
function defaults return t_hl_css_reg is
variable output : t_hl_css_reg;
begin
output.phy_initialise_dis := '0';
output.init_dram_dis := '0';
output.write_ihi_dis := '0';
output.cal_dis := '0';
output.write_btp_dis := '0';
output.write_mtp_dis := '0';
output.read_mtp_dis := '0';
output.rrp_reset_dis := '0';
output.rrp_sweep_dis := '0';
output.rrp_seek_dis := '0';
output.rdv_dis := '0';
output.poa_dis := '0';
output.was_dis := '0';
output.adv_rd_lat_dis := '0';
output.adv_wr_lat_dis := '0';
output.prep_customer_mr_setup_dis := '0';
output.tracking_dis := '0';
return output;
end function;
function defaults return t_cal_stage_ack_seen is
variable output : t_cal_stage_ack_seen;
begin
output.cal := '0';
output.phy_initialise := '0';
output.init_dram := '0';
output.write_ihi := '0';
output.write_btp := '0';
output.write_mtp := '0';
output.read_mtp := '0';
output.rrp_reset := '0';
output.rrp_sweep := '0';
output.rrp_seek := '0';
output.rdv := '0';
output.poa := '0';
output.was := '0';
output.adv_rd_lat := '0';
output.adv_wr_lat := '0';
output.prep_customer_mr_setup := '0';
output.tracking_setup := '0';
return output;
end function;
function defaults return t_mmi_ctrl is
variable output : t_mmi_ctrl;
begin
output.hl_css := defaults;
output.calibration_start := '0';
output.tracking_period_ms := 0;
output.tracking_orvd_to_10ms := '0';
return output;
end function;
function defaults return t_ctrl_mmi is
variable output : t_ctrl_mmi;
begin
output.master_state_r := s_reset;
output.ctrl_calibration_success := '0';
output.ctrl_calibration_fail := '0';
output.ctrl_current_stage_done := '0';
output.ctrl_current_stage := cmd_idle;
output.ctrl_current_active_block := idle;
output.ctrl_cal_stage_ack_seen := defaults;
output.ctrl_err_code := (others => '0');
return output;
end function;
-------------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFi PHY sequencer
-------------------------------------------------------------------------
function defaults return t_sc_ctrl_if is
variable output : t_sc_ctrl_if;
begin
output.read := '0';
output.write := '0';
output.dqs_group_sel := (others => '0');
output.sc_in_group_sel := (others => '0');
output.wdata := (others => '0');
output.op_type := (others => '0');
return output;
end function;
function defaults return t_sc_stat is
variable output : t_sc_stat;
begin
output.rdata := (others => '0');
output.busy := '0';
output.error_det := '0';
output.err_code := (others => '0');
output.sc_cap := (others => '0');
return output;
end function;
function defaults return t_sc_int_ctrl is
variable output : t_sc_int_ctrl;
begin
output.group_num := 0;
output.group_type := DQ_PIN;
output.pin_num := 0;
output.sc_element := pp_t9;
output.prog_val := (others => '0');
output.ram_set := '0';
output.sc_update := '0';
return output;
end function;
-- -----------------------------------------------------------------------
-- functions for instant on mode
--
--
-- Guide on how to use:
--
-- The following factors effect the setup of the PHY:
-- - AC Phase - phase at which address/command signals launched wrt PHY clock
-- - this effects the read/write latency
-- - MR settings - CL, CWL, AL
-- - Data rate - HR or FR (DDR/DDR2 only)
-- - Family - datapaths are subtly different for each
-- - Memory type - DDR/DDR2/DDR3 (different latency behaviour - see specs)
--
-- Instant on mode is designed to work for the following subset of the
-- above factors:
-- - AC Phase - out of the box defaults, which is 240 degrees for SIII type
-- families (includes SIV, HCIII, HCIV), else 90 degrees
-- - MR Settings - DDR - CL 3 only
-- - DDR2 - CL 3,4,5,6, AL 0
-- - DDR3 - CL 5,6 CWL 5, AL 0
-- - Data rate - All
-- - Families - All
-- - Memory type - All
--
-- Hints on bespoke setup for parameters outside the above or if the
-- datapath is modified (only for VHDL sim mode):
--
-- Step 1 - Run simulation with REDUCE_SIM_TIME mode 2 (FAST)
--
-- Step 2 - From the output log find the following text:
-- # -----------------------------------------------------------------------
-- **** ALTMEMPHY CALIBRATION has completed ****
-- Status:
-- calibration has : PASSED
-- PHY read latency (ctl_rlat) is : 14
-- address/command to PHY write latency (ctl_wlat) is : 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32
-- calibrated centre of data valid window size : 24
-- chosen address and command 1T delay: no 1T delay
-- poa 'dec' adjustments = 27
-- rdv 'dec' adjustments = 25
-- # -----------------------------------------------------------------------
--
-- Step 3 - Convert the text to bespoke instant on settings at the end of the
-- setup_instant_on function using the
-- override_instant_on function, note type is t_preset_cal
--
-- The mapping is as follows:
--
-- PHY read latency (ctl_rlat) is : 14 => rlat := 14
-- address/command to PHY write latency (ctl_wlat) is : 2 => wlat := 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32 => codvw_phase := 32
-- calibrated centre of data valid window size : 24 => codvw_size := 24
-- chosen address and command 1T delay: no 1T delay => ac_1t := '0'
-- poa 'dec' adjustments = 27 => poa_lat := 27
-- rdv 'dec' adjustments = 25 => rdv_lat := 25
--
-- Step 4 - Try running in REDUCE_SIM_TIME mode 1 (SUPERFAST mode)
--
-- Step 5 - If still fails observe the behaviour of the controller, for the
-- following symptoms:
-- - If first 2 beats of read data lost (POA enable too late) - inc poa_lat by 1 (poa_lat is number of POA decrements not actual latency)
-- - If last 2 beats of read data lost (POA enable too early) - dec poa_lat by 1
-- - If ctl_rdata_valid misaligned to ctl_rdata then alter number of RDV adjustments (rdv_lat)
-- - If write data is not 4-beat aligned (when written into memory) toggle ac_1t (HR only)
-- - If read data is not 4-beat aligned (but write data is) add 360 degrees to phase (PLL_STEPS_PER_CYCLE) mod 2*PLL_STEPS_PER_CYCLE (HR only)
--
-- Step 6 - If the above fails revert to REDUCE_SIM_TIME = 2 (FAST) mode
--
-- --------------------------------------------------------------------------
-- defaults
function defaults return t_preset_cal is
variable output : t_preset_cal;
begin
output.codvw_phase := 0;
output.codvw_size := 0;
output.wlat := 0;
output.rlat := 0;
output.rdv_lat := 0;
output.ac_1t := '1'; -- default on for FR
output.poa_lat := 0;
return output;
end function;
-- Functions to extract values from MR
-- return cl (for DDR memory 2*cl because of 1/2 cycle latencies)
procedure mr0_to_cl (memory_type : string;
mr0 : std_logic_vector(15 downto 0);
cl : out natural;
half_cl : out std_logic) is
variable v_cl : natural;
begin
half_cl := '0';
if memory_type = "DDR" then -- DDR memories
-- returns cl*2 because of 1/2 latencies
v_cl := to_integer(unsigned(mr0(5 downto 4)));
-- integer values of cl
if mr0(6) = '0' then
assert v_cl > 1 report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
end if;
if mr0(6) = '1' then
assert (v_cl = 1 or v_cl = 2) report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
half_cl := '1';
end if;
elsif memory_type = "DDR2" then -- DDR2 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)));
-- sanity checks
assert (v_cl > 1 and v_cl < 7) report record_report_prefix & "invalid cas latency for DDR2 memory, should be in range 2-6 but equals " & integer'image(v_cl) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)))+4;
--sanity checks
assert mr0(2) = '0' report record_report_prefix & "invalid cas latency for DDR3 memory, bit a2 in mr0 is set" severity failure;
assert v_cl /= 4 report record_report_prefix & "invalid cas latency for DDR3 memory, bits a6:4 set to zero" severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
cl := v_cl;
end procedure;
function mr1_to_al (memory_type : string;
mr1 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable al : natural;
begin
if memory_type = "DDR" then -- DDR memories
-- unsupported so return zero
al := 0;
elsif memory_type = "DDR2" then -- DDR2 memories
al := to_integer(unsigned(mr1(5 downto 3)));
assert al < 6 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
al := to_integer(unsigned(mr1(4 downto 3)));
assert al /= 3 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
if al /= 0 then -- CL-1 or CL-2
al := cl - al;
end if;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return al;
end function;
-- return cwl
function mr2_to_cwl (memory_type : string;
mr2 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable cwl : natural;
begin
if memory_type = "DDR" then -- DDR memories
cwl := 1;
elsif memory_type = "DDR2" then -- DDR2 memories
cwl := cl - 1;
elsif memory_type = "DDR3" then -- DDR3 memories
cwl := to_integer(unsigned(mr2(5 downto 3))) + 5;
--sanity checks
assert cwl < 9 report record_report_prefix & "invalid cas write latency for DDR3 memory, should be in range 5-8 but equals " & integer'image(cwl) severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return cwl;
end function;
-- -----------------------------------
-- Functions to determine which family group
-- Include any family alias here
-- -----------------------------------
function is_siii(family_id : natural) return boolean is
begin
if family_id = 3 or family_id = 5 then
return true;
else
return false;
end if;
end function;
function is_ciii(family_id : natural) return boolean is
begin
if family_id = 2 then
return true;
else
return false;
end if;
end function;
function is_aii(family_id : natural) return boolean is
begin
if family_id = 4 then
return true;
else
return false;
end if;
end function;
function is_sii(family_id : natural) return boolean is
begin
if family_id = 1 then
return true;
else
return false;
end if;
end function;
-- -----------------------------------
-- Functions to lookup hardcoded values
-- on per family basis
-- DDR: CL = 3
-- DDR2: CL = 6, CWL = 5, AL = 0
-- DDR3: CL = 6, CWL = 5, AL = 0
-- -----------------------------------
-- default ac phase = 240
function siii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural
) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 8;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 16;
v_output.rdv_lat := 21;
v_output.ac_1t := '0';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 2;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
-- adapt settings for ac_phase (default 240 degrees so leave commented)
-- if dwidth_ratio = 2 then
-- v_output.wlat := v_output.wlat - 1;
-- v_output.rlat := v_output.rlat - 1;
-- v_output.rdv_lat := v_output.rdv_lat + 1;
-- v_output.poa_lat := v_output.poa_lat + 1;
-- else
-- v_output.ac_1t := not v_output.ac_1t;
-- end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function ciii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11; --unused
else
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 27; --unused
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 8; --unused
else
v_output.codvw_phase := pll_steps + 3*pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 25; --unused
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps/2;
return v_output;
end function;
-- default ac phase = 90
function sii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 13;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 10;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 20;
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function aii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 15;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 19;
v_output.rdv_lat := 9;
v_output.poa_lat := 12;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
function is_odd(num : integer) return boolean is
variable v_num : integer;
begin
v_num := num;
if v_num - (v_num/2)*2 = 0 then
return false;
else
return true;
end if;
end function;
------------------------------------------------
-- top level function to setup instant on mode
------------------------------------------------
function override_instant_on return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
-- add in overrides here
return v_output;
end function;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal is
variable v_output : t_preset_cal;
variable v_cl : natural; -- cas latency
variable v_half_cl : std_logic; -- + 0.5 cycles (DDR only)
variable v_al : natural; -- additive latency (ddr2/ddr3 only)
variable v_cwl : natural; -- cas write latency (ddr3 only)
variable v_rl : integer range 0 to 15;
variable v_wl : integer;
variable v_delta_rl : integer range -10 to 10; -- from given defaults
variable v_delta_wl : integer; -- from given defaults
variable v_debug : boolean;
begin
v_debug := true;
v_output := defaults;
if sim_time_red = 1 then -- only set if STR equals 1
-- ----------------------------------------
-- extract required parameters from MRs
-- ----------------------------------------
mr0_to_cl(memory_type, mr0, v_cl, v_half_cl);
v_al := mr1_to_al(memory_type, mr1, v_cl);
v_cwl := mr2_to_cwl(memory_type, mr2, v_cl);
v_rl := v_cl + v_al;
v_wl := v_cwl + v_al;
if v_debug then
report record_report_prefix & "Extracted MR parameters" & LF &
"CAS = " & integer'image(v_cl) & LF &
"CWL = " & integer'image(v_cwl) & LF &
"AL = " & integer'image(v_al) & LF;
end if;
-- ----------------------------------------
-- apply per family, memory type and dwidth_ratio static setup
-- ----------------------------------------
if is_siii(family_id) then
v_output := siii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_ciii(family_id) then
v_output := ciii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_aii(family_id) then
v_output := aii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_sii(family_id) then
v_output := sii_family_settings(dwidth_ratio, memory_type, pll_steps);
end if;
-- ----------------------------------------
-- correct for different cwl, cl and al settings
-- ----------------------------------------
if memory_type = "DDR" then
v_delta_rl := v_rl - c_ddr_default_rl;
v_delta_wl := v_wl - c_ddr_default_wl;
elsif memory_type = "DDR2" then
v_delta_rl := v_rl - c_ddr2_default_rl;
v_delta_wl := v_wl - c_ddr2_default_wl;
else -- DDR3
v_delta_rl := v_rl - c_ddr3_default_rl;
v_delta_wl := v_wl - c_ddr3_default_wl;
end if;
if v_debug then
report record_report_prefix & "Extracted memory latency (and delta from default)" & LF &
"RL = " & integer'image(v_rl) & LF &
"WL = " & integer'image(v_wl) & LF &
"delta RL = " & integer'image(v_delta_rl) & LF &
"delta WL = " & integer'image(v_delta_wl) & LF;
end if;
if dwidth_ratio = 2 then
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl;
elsif dwidth_ratio = 4 then
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl/2;
if is_odd(v_delta_wl) then -- add / sub 1t write latency
-- toggle ac_1t in all cases
v_output.ac_1t := not v_output.ac_1t;
if v_delta_wl < 0 then -- sub 1 from latency
if v_output.ac_1t = '0' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat - 1;
end if;
else -- add 1 to latency
if v_output.ac_1t = '1' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat + 1;
end if;
end if;
-- update read latency
if v_output.ac_1t = '1' then -- added 1t to address/command so inc read_lat
v_delta_rl := v_delta_rl + 1;
else -- subtracted 1t from address/command so dec read_lat
v_delta_rl := v_delta_rl - 1;
end if;
end if;
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl/2;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
if memory_type = "DDR3" then
if is_odd(v_delta_rl) xor is_odd(v_delta_wl) then
if is_aii(family_id) then
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.rdv_lat := v_output.rdv_lat + 1;
v_output.poa_lat := v_output.poa_lat + 1;
end if;
end if;
end if;
if is_odd(v_delta_rl) then
if v_delta_rl > 0 then -- add 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
v_output.rlat := v_output.rlat + 1;
end if;
else -- subtract 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
v_output.rlat := v_output.rlat - 1;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
end if;
end if;
end if;
end if;
if v_half_cl = '1' and is_ciii(family_id) then
v_output.codvw_phase := v_output.codvw_phase - pll_steps/2;
end if;
end if;
return v_output;
end function;
--
END ddr_ctrl_ip_phy_alt_mem_phy_record_pkg;
--/* Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details. */
--
-- -----------------------------------------------------------------------------
-- Abstract : address and command package, shared between all variations of
-- the AFI sequencer
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is
-- used to combine DRAM address and command signals in one record
-- and unify the functions operating on this record.
--
--
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg is
-- the following are bounds on the maximum range of address and command signals
constant c_max_addr_bits : natural := 15;
constant c_max_ba_bits : natural := 3;
constant c_max_ranks : natural := 16;
constant c_max_mode_reg_bit : natural := 12;
constant c_max_cmds_per_clk : natural := 4; -- quarter rate
-- a prefix for all report signals to identify phy and sequencer block
--
constant ac_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (addr_cmd_pkg) : ";
-- -------------------------------------------------------------
-- this record represents a single mem_clk command cycle
-- -------------------------------------------------------------
type t_addr_cmd is record
addr : natural range 0 to 2**c_max_addr_bits - 1;
ba : natural range 0 to 2**c_max_ba_bits - 1;
cas_n : boolean;
ras_n : boolean;
we_n : boolean;
cke : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
cs_n : natural range 2**c_max_ranks - 1 downto 0; -- bounded max of 8 ranks
odt : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
rst_n : boolean;
end record t_addr_cmd;
-- -------------------------------------------------------------
-- this vector is used to describe the fact that for slower clock domains
-- mutiple commands per clock can be issued and encapsulates all these options in a
-- type which can scale with rate
-- -------------------------------------------------------------
type t_addr_cmd_vector is array (natural range <>) of t_addr_cmd;
-- -------------------------------------------------------------
-- this record is used to define the memory interface type and allow packing and checking
-- (it should be used as a generic to a entity or from a poject level constant)
-- -------------------------------------------------------------
-- enumeration for mem_type
type t_mem_type is
(
DDR,
DDR2,
DDR3
);
-- memory interface configuration parameters
type t_addr_cmd_config_rec is record
num_addr_bits : natural;
num_ba_bits : natural;
num_cs_bits : natural;
num_ranks : natural;
cmds_per_clk : natural range 1 to c_max_cmds_per_clk; -- commands per clock cycle (equal to DWIDTH_RATIO/2)
mem_type : t_mem_type;
end record;
-- -----------------------------------
-- the following type is used to switch between signals
-- (for example, in the mask function below)
-- -----------------------------------
type t_addr_cmd_signals is
(
addr,
ba,
cas_n,
ras_n,
we_n,
cke,
cs_n,
odt,
rst_n
);
-- -----------------------------------
-- odt record
-- to hold the odt settings
-- (an odt_record) per rank (in odt_array)
-- -----------------------------------
type t_odt_record is record
write : natural;
read : natural;
end record t_odt_record;
type t_odt_array is array (natural range <>) of t_odt_record;
-- -------------------------------------------------------------
-- exposed functions and procedures
--
-- these functions cover the following memory types:
-- DDR3, DDR2, DDR
--
-- and the following operations:
-- MRS, REF, PRE, PREA, ACT,
-- WR, WRS8, WRS4, WRA, WRAS8, WRAS4,
-- RD, RDS8, RDS4, RDA, RDAS8, RDAS4,
--
-- for DDR3 on the fly burst length setting for reads/writes
-- is supported
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function int_pup_reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector;
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector;
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function refresh ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function self_refresh_entry ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector;
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector;
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector;
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: currently only supports DDR/DDR2 memories
-- -------------------------------------------------------------
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array;
-- -------------------------------------------------------------
-- the following function enables assignment to the constant config_rec
-- -------------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- -------------------------------------------------------------
-- the following function and procedure unpack address and
-- command signals from the t_addr_cmd_vector format
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector);
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector);
-- -------------------------------------------------------------
-- the following functions perform bit masking to 0 or 1 (as
-- specified by mask_value) to a chosen address/command signal (signal_name)
-- across all signal bits or to a selected bit (mask_bit)
-- -------------------------------------------------------------
-- mask all signal bits procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic) return t_addr_cmd_vector;
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic);
-- mask signal bit (mask_bit) procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural) return t_addr_cmd_vector;
--
end ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg;
--
package body ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg IS
-- -------------------------------------------------------------
-- Basic functions for a single command
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := 0;
v_retval.ba := 0;
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (Same as default with cke and rst_n 0 )
-- -------------------------------------------------------------
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := defaults(config_rec);
v_retval.cke := 0;
if config_rec.mem_type = DDR3 then
v_retval.rst_n := true;
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues deselect (command) JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '1'; -- set AP bit high
v_retval.addr := to_integer(v_addr);
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - 1 - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '0'; -- set AP bit low
v_retval.addr := to_integer(v_addr);
v_retval.ba := bank;
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits - 1;
row : in natural range 0 to 2**c_max_addr_bits - 1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := row;
v_retval.ba := bank;
v_retval.cas_n := false;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := previous.odt;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports writes of burst length 4 or 8, the requested length was: " & integer'image(op_length) severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory writes" severity failure;
end if;
-- set a/c signal assignments for write
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := ranks;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports reads of burst length 4 or 8" severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory reads" severity failure;
end if;
-- set a/c signals for read command
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.rst_n := false;
-- addr, BA and ODT are don't care therfore leave as previous value
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr_remap : unsigned(c_max_mode_reg_bit downto 0);
begin
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
v_retval.ba := mode_register_num;
v_retval.addr := to_integer(unsigned(mode_reg_value));
if remap_addr_and_ba = true then
v_addr_remap := unsigned(mode_reg_value);
v_addr_remap(8 downto 7) := v_addr_remap(7) & v_addr_remap(8);
v_addr_remap(6 downto 5) := v_addr_remap(5) & v_addr_remap(6);
v_addr_remap(4 downto 3) := v_addr_remap(3) & v_addr_remap(4);
v_retval.addr := to_integer(v_addr_remap);
v_addr_remap := to_unsigned(mode_register_num, c_max_mode_reg_bit + 1);
v_addr_remap(1 downto 0) := v_addr_remap(0) & v_addr_remap(1);
v_retval.ba := to_integer(v_addr_remap);
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- -------------------------------------------------------------
function maintain_pd_or_sr (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cke := (2 ** config_rec.num_ranks) - 1 - ranks;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCS (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 0; -- clear bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCL (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 1024; -- set bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- functions acting on all clock cycles from whatever rate
-- in halfrate clock domain issues 1 command per clock
-- in quarter rate issues 1 command per clock
-- In the above cases they will be correctly aligned using the
-- ALTMEMPHY 2T and 4T SDC
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => defaults(config_rec));
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (same as default with cke 0)
-- -------------------------------------------------------------
function reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => reset(config_rec));
return v_retval;
end function;
function int_pup_reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_addr_cmd_config_rst : t_addr_cmd_config_rec;
begin
v_addr_cmd_config_rst := config_rec;
v_addr_cmd_config_rst.num_ranks := c_max_ranks;
return reset(v_addr_cmd_config_rst);
end function;
-- -------------------------------------------------------------
-- issues a deselect command JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(a_previous'range);
begin
for rate in a_previous'range loop
v_retval(rate) := deselect(config_rec, a_previous(a_previous'high));
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_all(config_rec, previous(a_previous'high), ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_bank(config_rec, previous(a_previous'high), ranks, bank);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := activate(config_rec, previous(previous'high), bank, row, ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
--
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := write(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := read(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := refresh(config_rec, previous(previous'high), ranks);
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh_entry command JEDEC abbreviated name: SRE
-- -------------------------------------------------------------
function self_refresh_entry (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := enter_sr_pd_mode(config_rec, refresh(config_rec, previous, ranks), ranks);
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh exit or power_down exit command
-- JEDEC abbreviated names: SRX, PDX
-- -------------------------------------------------------------
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := maintain_pd_or_sr(config_rec, previous, ranks);
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) or v_mask_workings_b(i);
end loop;
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- cause the selected ranks to enter Self-refresh or Powerdown mode
-- JEDEC abbreviated names: PDE,
-- SRE (if a refresh is concurrently issued to the same ranks)
-- -------------------------------------------------------------
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := previous;
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) and not v_mask_workings_b(i);
end loop;
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => load_mode(config_rec, mode_register_num, mode_reg_value, ranks, remap_addr_and_ba));
for rate in v_retval'range loop
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- NOTE: does not affect previous command
-- -------------------------------------------------------------
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for command in v_retval'range loop
v_retval(command) := maintain_pd_or_sr(config_rec, previous(command), ranks);
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCL(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCS(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- ----------------------
-- Additional Rank manipulation functions (main use DDR3)
-- -------------
-- -----------------------------------
-- set the chip select for a group of ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or not mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- set the chip select for a group of ranks in a way which handles diffrent rates
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_unreversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above handling ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_reversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- --------------------------------------------------
-- Program a single control word onto RDIMM.
-- This is accomplished rather goofily by asserting all chip selects
-- and then writing out both the addr/data of the word onto the addr/ba bus
-- --------------------------------------------------
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable ba : std_logic_vector(2 downto 0);
variable addr : std_logic_vector(4 downto 0);
begin
v_retval := defaults(config_rec);
v_retval.cs_n := 0;
ba := control_word_addr(3) & control_word_data(3) & control_word_data(2);
v_retval.ba := to_integer(unsigned(ba));
addr := control_word_data(1) & control_word_data(0) & control_word_addr(2) &
control_word_addr(1) & control_word_addr(0);
v_retval.addr := to_integer(unsigned(addr));
return v_retval;
end function;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => program_rdimm_register(config_rec, control_word_addr, control_word_data));
return v_retval;
end function;
-- --------------------------------------------------
-- overloaded functions, to simplify use, or provide simplified functionality
-- --------------------------------------------------
-- ----------------------------------------------------
-- Precharge all, defaulting all bits.
-- ----------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
v_retval := precharge_all(config_rec, v_retval, ranks);
return v_retval;
end function;
-- ----------------------------------------------------
-- perform DLL reset through mode registers
-- ----------------------------------------------------
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector is
variable int_mode_reg : std_logic_vector(mode_reg_val'range);
variable output : t_addr_cmd_vector(0 to config_rec.cmds_per_clk - 1);
begin
int_mode_reg := mode_reg_val;
int_mode_reg(8) := '1'; -- set DLL reset bit.
output := load_mode(config_rec, 0, int_mode_reg, rank_num, reorder_addr_bits);
return output;
end function;
-- -------------------------------------------------------------
-- package configuration functions
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: supports DDR/DDR2/DDR3 SDRAM memories
-- -------------------------------------------------------------
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array is
variable v_num_slots : natural;
variable v_cs : natural range 0 to ranks-1;
variable v_odt_values : t_odt_array(0 to ranks-1);
variable v_cs_addr : unsigned(ranks-1 downto 0);
begin
if mem_type = "DDR" then
-- ODT not supported for DDR memory so set default off
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 0;
v_odt_values(v_cs).read := 0;
end loop;
elsif mem_type = "DDR2" then
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr);
v_odt_values(v_cs).read := v_odt_values(v_cs).write;
end loop;
end if;
elsif mem_type = "DDR3" then
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr) + 2**(v_cs); -- turn on a neighbouring slots cs and current rank being written to
v_odt_values(v_cs).read := 2**to_integer(v_cs_addr);
end loop;
end if;
else
report ac_report_prefix & "unknown mem_type specified in the set_odt_values function in addr_cmd_pkg package" severity failure;
end if;
return v_odt_values;
end function;
-- -----------------------------------------------------------
-- set constant values to config_rec
-- ----------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
variable v_config_rec : t_addr_cmd_config_rec;
begin
v_config_rec.num_addr_bits := num_addr_bits;
v_config_rec.num_ba_bits := num_ba_bits;
v_config_rec.num_cs_bits := num_cs_bits;
v_config_rec.num_ranks := num_ranks;
v_config_rec.cmds_per_clk := dwidth_ratio/2;
if mem_type = "DDR" then
v_config_rec.mem_type := DDR;
elsif mem_type = "DDR2" then
v_config_rec.mem_type := DDR2;
elsif mem_type = "DDR3" then
v_config_rec.mem_type := DDR3;
else
report ac_report_prefix & "unknown mem_type specified in the set_config_rec function in addr_cmd_pkg package" severity failure;
end if;
return v_config_rec;
end function;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
begin
return set_config_rec(num_addr_bits, num_ba_bits, num_cs_bits, num_cs_bits, dwidth_ratio, mem_type);
end function;
-- -----------------------------------------------------------
-- unpack and pack address and command signals from and to t_addr_cmd_vector
-- -----------------------------------------------------------
-- -------------------------------------------------------------
-- convert from t_addr_cmd_vector to expanded addr/cmd signals
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
v_vec_len := config_rec.cmds_per_clk;
v_mem_if_ranks := config_rec.num_ranks;
for v_i in 0 to v_vec_len-1 loop
assert addr_cmd_vector(v_i).addr < 2**config_rec.num_addr_bits report ac_report_prefix &
"value of addr exceeds range of number of address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).ba < 2**config_rec.num_ba_bits report ac_report_prefix &
"value of ba exceeds range of number of bank address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).odt < 2**v_mem_if_ranks report ac_report_prefix &
"value of odt exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cs_n < 2**config_rec.num_cs_bits report ac_report_prefix &
"value of cs_n exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cke < 2**v_mem_if_ranks report ac_report_prefix &
"value of cke exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
v_addr((v_i+1)*config_rec.num_addr_bits - 1 downto v_i*config_rec.num_addr_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).addr,config_rec.num_addr_bits));
v_ba((v_i+1)*config_rec.num_ba_bits - 1 downto v_i*config_rec.num_ba_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).ba,config_rec.num_ba_bits));
v_cke((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cke,v_mem_if_ranks));
v_cs_n((v_i+1)*config_rec.num_cs_bits - 1 downto v_i*config_rec.num_cs_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cs_n,config_rec.num_cs_bits));
v_odt((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).odt,v_mem_if_ranks));
if (addr_cmd_vector(v_i).cas_n) then v_cas_n(v_i) := '0'; else v_cas_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).ras_n) then v_ras_n(v_i) := '0'; else v_ras_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).we_n) then v_we_n(v_i) := '0'; else v_we_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).rst_n) then v_rst_n(v_i) := '0'; else v_rst_n(v_i) := '1'; end if;
end loop;
addr := v_addr;
ba := v_ba;
cke := v_cke;
cs_n := v_cs_n;
odt := v_odt;
cas_n := v_cas_n;
ras_n := v_ras_n;
we_n := v_we_n;
rst_n := v_rst_n;
end procedure;
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_seq_ac_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_seq_ac_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_seq_ac_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_seq_ac_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
unpack_addr_cmd_vector (
addr_cmd_vector,
config_rec,
v_seq_ac_addr,
v_seq_ac_ba,
v_seq_ac_cas_n,
v_seq_ac_ras_n,
v_seq_ac_we_n,
v_seq_ac_cke,
v_seq_ac_cs_n,
v_seq_ac_odt,
v_seq_ac_rst_n);
addr <= v_seq_ac_addr;
ba <= v_seq_ac_ba;
cas_n <= v_seq_ac_cas_n;
ras_n <= v_seq_ac_ras_n;
we_n <= v_seq_ac_we_n;
cke <= v_seq_ac_cke;
cs_n <= v_seq_ac_cs_n;
odt <= v_seq_ac_odt;
rst_n <= v_seq_ac_rst_n;
end procedure;
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_
-- -----------------------------------------------------------
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then v_addr_cmd_vector(v_i).addr := 0; else v_addr_cmd_vector(v_i).addr := (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then v_addr_cmd_vector(v_i).ba := 0; else v_addr_cmd_vector(v_i).ba := (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cas_n := true; else v_addr_cmd_vector(v_i).cas_n := false; end if;
when ras_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).ras_n := true; else v_addr_cmd_vector(v_i).ras_n := false; end if;
when we_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).we_n := true; else v_addr_cmd_vector(v_i).we_n := false; end if;
when cke => if (mask_value = '0') then v_addr_cmd_vector(v_i).cke := 0; else v_addr_cmd_vector(v_i).cke := (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cs_n := 0; else v_addr_cmd_vector(v_i).cs_n := (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then v_addr_cmd_vector(v_i).odt := 0; else v_addr_cmd_vector(v_i).odt := (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).rst_n := true; else v_addr_cmd_vector(v_i).rst_n := false; end if;
when others => report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
-- -----------------------------------------------------------
-- procedure to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
)
is
variable v_i : integer;
begin
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then addr_cmd_vector(v_i).addr <= 0; else addr_cmd_vector(v_i).addr <= (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then addr_cmd_vector(v_i).ba <= 0; else addr_cmd_vector(v_i).ba <= (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then addr_cmd_vector(v_i).cas_n <= true; else addr_cmd_vector(v_i).cas_n <= false; end if;
when ras_n => if (mask_value = '0') then addr_cmd_vector(v_i).ras_n <= true; else addr_cmd_vector(v_i).ras_n <= false; end if;
when we_n => if (mask_value = '0') then addr_cmd_vector(v_i).we_n <= true; else addr_cmd_vector(v_i).we_n <= false; end if;
when cke => if (mask_value = '0') then addr_cmd_vector(v_i).cke <= 0; else addr_cmd_vector(v_i).cke <= (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then addr_cmd_vector(v_i).cs_n <= 0; else addr_cmd_vector(v_i).cs_n <= (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then addr_cmd_vector(v_i).odt <= 0; else addr_cmd_vector(v_i).odt <= (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then addr_cmd_vector(v_i).rst_n <= true; else addr_cmd_vector(v_i).rst_n <= false; end if;
when others => report ac_report_prefix & "masking not supported for the given signal name" severity failure;
end case;
end loop;
end procedure;
-- -----------------------------------------------------------
-- function to mask a given bit (mask_bit) of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr : std_logic_vector(config_rec.num_addr_bits-1 downto 0); -- v_addr is bit vector of address
variable v_ba : std_logic_vector(config_rec.num_ba_bits-1 downto 0); -- v_addr is bit vector of bank address
variable v_vec_len : natural range 0 to 4;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
v_vec_len := config_rec.cmds_per_clk;
for v_i in 0 to v_vec_len-1 loop
case signal_name is
when addr =>
v_addr := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).addr,v_addr'length));
v_addr(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).addr := to_integer(unsigned(v_addr));
when ba =>
v_ba := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).ba,v_ba'length));
v_ba(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).ba := to_integer(unsigned(v_ba));
when others =>
report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
--
end ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram addressing package for the non-levelling AFI PHY sequencer
-- The iram address package (alt_mem_phy_iram_addr_pkg) is
-- used to define the base addresses used for iram writes
-- during calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg IS
constant c_ihi_size : natural := 8;
type t_base_hdr_addresses is record
base_hdr : natural;
rrp : natural;
safe_dummy : natural;
required_addr_bits : natural;
end record;
function defaults return t_base_hdr_addresses;
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses;
--
end ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg;
--
package body ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg IS
-- set some safe default values
function defaults return t_base_hdr_addresses is
variable temp : t_base_hdr_addresses;
begin
temp.base_hdr := 0;
temp.rrp := 0;
temp.safe_dummy := 0;
temp.required_addr_bits := 1;
return temp;
end function;
-- this function determines now many times the PLL phases are swept through per pin
-- i.e. an n * 360 degree phase sweep
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
begin
if dwidth_ratio = 2 and dqs_capture = 1 then
v_output := 2; -- if dqs_capture then a 720 degree sweep needed in FR
else
v_output := (dwidth_ratio/2);
end if;
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := dq_pins * (((v_phase_mul * pll_phases) + 31) / 32);
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := ((v_phase_mul * pll_phases) + 31) / 32;
return v_output;
end function;
-- return iram addresses
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses
is
variable working : t_base_hdr_addresses;
variable temp : natural;
variable v_required_words : natural;
begin
working.base_hdr := 0;
working.rrp := working.base_hdr + c_ihi_size;
-- work out required number of address bits
-- + for 1 full rrp calibration
v_required_words := iram_wd_for_full_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2; -- +2 for header + footer
-- * loop per cs
v_required_words := v_required_words * num_ranks;
-- + for 1 rrp_seek result
v_required_words := v_required_words + 3; -- 1 header, 1 word result, 1 footer
-- + 2 mtp_almt passes
v_required_words := v_required_words + 2 * (iram_wd_for_one_pin_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2);
-- + for 2 read_mtp result calculation
v_required_words := v_required_words + 3*2; -- 1 header, 1 word result, 1 footer
-- * possible dwidth_ratio/2 iterations for different ac_nt settings
v_required_words := v_required_words * (dwidth_ratio / 2);
working.safe_dummy := working.rrp + v_required_words;
temp := working.safe_dummy;
working.required_addr_bits := 0;
while (temp >= 1) loop
working.required_addr_bits := working.required_addr_bits + 1;
temp := temp /2;
end loop;
return working;
end function calc_iram_addresses;
--
END ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : register package for the non-levelling AFI PHY sequencer
-- The registers package (alt_mem_phy_regs_pkg) is used to
-- combine the definition of the registers for the mmi status
-- registers and functions/procedures applied to the registers
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
--
package ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg is
-- a prefix for all report signals to identify phy and sequencer block
--
constant regs_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (register package) : ";
-- ---------------------------------------------------------------
-- register declarations with associated functions of:
-- default - assign default values
-- write - write data into the reg (from avalon i/f)
-- read - read data from the reg (sent to the avalon i/f)
-- write_clear - clear reg to all zeros
-- ---------------------------------------------------------------
-- TYPE DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
type t_cal_status is record
iram_addr_width : std_logic_vector(3 downto 0);
out_of_mem : std_logic;
contested_access : std_logic;
cal_fail : std_logic;
cal_success : std_logic;
ctrl_err_code : std_logic_vector(7 downto 0);
trefi_failure : std_logic;
int_ac_1t : std_logic;
dqs_capture : std_logic;
iram_present : std_logic;
active_block : std_logic_vector(3 downto 0);
current_stage : std_logic_vector(7 downto 0);
end record;
-- codvw status
type t_codvw_status is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record t_codvw_status;
-- test status report
type t_test_status is record
ack_seen : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
pll_mmi_err : std_logic_vector(1 downto 0);
pll_busy : std_logic;
end record;
-- define all the read only registers :
type t_ro_regs is record
cal_status : t_cal_status;
codvw_status : t_codvw_status;
test_status : t_test_status;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
type t_hl_css is record
hl_css : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
cal_start : std_logic;
end record t_hl_css;
-- Mode register A
type t_mr_register_a is record
mr0 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr1 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_a;
-- Mode register B
type t_mr_register_b is record
mr2 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr3 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_b;
-- algorithm parameterisation register
type t_parameterisation_reg_a is record
nominal_poa_phase_lead : std_logic_vector(3 downto 0);
maximum_poa_delay : std_logic_vector(3 downto 0);
num_phases_per_tck_pll : std_logic_vector(3 downto 0);
pll_360_sweeps : std_logic_vector(3 downto 0);
nominal_dqs_delay : std_logic_vector(2 downto 0);
extend_octrt_by : std_logic_vector(3 downto 0);
delay_octrt_by : std_logic_vector(3 downto 0);
end record;
-- test signal register
type t_if_test_reg is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
ac_1t_toggle : std_logic; -- unused
tracking_period_ms : std_logic_vector(7 downto 0); -- 0 = as fast as possible approx in ms
tracking_units_are_10us : std_logic;
end record;
-- define all the read/write registers
type t_rw_regs is record
mr_reg_a : t_mr_register_a;
mr_reg_b : t_mr_register_b;
rw_hl_css : t_hl_css;
rw_param_reg : t_parameterisation_reg_a;
rw_if_test : t_if_test_reg;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
type t_mmi_regs is record
rw_regs : t_rw_regs;
ro_regs : t_ro_regs;
enable_writes : std_logic;
end record;
-- FUNCTION DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
function defaults return t_cal_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status;
function read (reg : t_cal_status) return std_logic_vector;
-- codvw status
function defaults return t_codvw_status;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status;
function read (reg : in t_codvw_status) return std_logic_vector;
-- test status report
function defaults return t_test_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status;
function read (reg : t_test_status) return std_logic_vector;
-- define all the read only registers
function defaults return t_ro_regs;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
-- high level calibration stage set register comprises a bit vector for
-- the calibration stage coding and the 1 control bit.
function defaults return t_hl_css;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_hl_css;
function read (reg : in t_hl_css) return std_logic_vector;
procedure write_clear (signal reg : inout t_hl_css);
-- Mode register A
-- mode registers 0 and 1 (mr and emr1)
function defaults return t_mr_register_a;
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a;
function read (reg : in t_mr_register_a) return std_logic_vector;
-- Mode register B
-- mode registers 2 and 3 (emr2 and emr3) - not present in ddr DRAM
function defaults return t_mr_register_b;
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b;
function read (reg : in t_mr_register_b) return std_logic_vector;
-- algorithm parameterisation register
function defaults return t_parameterisation_reg_a;
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a;
-- test signal register
function defaults return t_if_test_reg;
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg;
function read ( reg : in t_if_test_reg) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg;
procedure write_clear (signal reg : inout t_if_test_reg);
-- define all the read/write registers
function defaults return t_rw_regs;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs;
procedure write_clear (signal regs : inout t_rw_regs);
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0));
-- >>>>>>>>>>>>>>>>>>>>>>>
-- functions to communicate register settings to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl;
function pack_record ( ip_regs : t_rw_regs) return t_algm_paramaterisation;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- helper functions
-- >>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css ) return t_hl_css_reg;
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector;
-- encoding of stage and active block for register setting
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id) return std_logic_vector;
function encode_active_block (active_block : t_ctrl_active_block) return std_logic_vector;
--
end ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg;
--
package body ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg is
-- >>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- CODVW status report
-- ---------------------------------------------------------------
function defaults return t_codvw_status is
variable temp: t_codvw_status;
begin
temp.cal_codvw_phase := (others => '0');
temp.cal_codvw_size := (others => '0');
temp.codvw_trk_shift := (others => '0');
temp.codvw_grt_one_dvw := '0';
return temp;
end function;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status is
variable temp: t_codvw_status;
begin
temp := defaults;
temp.cal_codvw_phase := dgrb_mmi.cal_codvw_phase;
temp.cal_codvw_size := dgrb_mmi.cal_codvw_size;
temp.codvw_trk_shift := dgrb_mmi.codvw_trk_shift;
temp.codvw_grt_one_dvw := dgrb_mmi.codvw_grt_one_dvw;
return temp;
end function;
function read (reg : in t_codvw_status) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0);
begin
temp := (others => '0');
temp(31 downto 24) := reg.cal_codvw_phase;
temp(23 downto 16) := reg.cal_codvw_size;
temp(15 downto 4) := reg.codvw_trk_shift;
temp(0) := reg.codvw_grt_one_dvw;
return temp;
end function;
-- ---------------------------------------------------------------
-- Calibration status report
-- ---------------------------------------------------------------
function defaults return t_cal_status is
variable temp: t_cal_status;
begin
temp.iram_addr_width := (others => '0');
temp.out_of_mem := '0';
temp.contested_access := '0';
temp.cal_fail := '0';
temp.cal_success := '0';
temp.ctrl_err_code := (others => '0');
temp.trefi_failure := '0';
temp.int_ac_1t := '0';
temp.dqs_capture := '0';
temp.iram_present := '0';
temp.active_block := (others => '0');
temp.current_stage := (others => '0');
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status is
variable temp : t_cal_status;
begin
temp := defaults;
temp.iram_addr_width := std_logic_vector(to_unsigned(IRAM_AWIDTH, temp.iram_addr_width'length));
temp.out_of_mem := iram_status.out_of_mem;
temp.contested_access := iram_status.contested_access;
temp.cal_fail := ctrl_mmi.ctrl_calibration_fail;
temp.cal_success := ctrl_mmi.ctrl_calibration_success;
temp.ctrl_err_code := ctrl_mmi.ctrl_err_code;
temp.trefi_failure := trefi_failure;
temp.int_ac_1t := int_ac_1t;
if dqs_capture = 1 then
temp.dqs_capture := '1';
elsif dqs_capture = 0 then
temp.dqs_capture := '0';
else
report regs_report_prefix & " invalid value for dqs_capture constant of " & integer'image(dqs_capture) severity failure;
end if;
temp.iram_present := USE_IRAM;
temp.active_block := encode_active_block(ctrl_mmi.ctrl_current_active_block);
temp.current_stage := encode_current_stage(ctrl_mmi.ctrl_current_stage);
return temp;
end function;
-- read for mmi status register
function read ( reg : t_cal_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output( 7 downto 0) := reg.current_stage;
output(11 downto 8) := reg.active_block;
output(12) := reg.iram_present;
output(13) := reg.dqs_capture;
output(14) := reg.int_ac_1t;
output(15) := reg.trefi_failure;
output(23 downto 16) := reg.ctrl_err_code;
output(24) := reg.cal_success;
output(25) := reg.cal_fail;
output(26) := reg.contested_access;
output(27) := reg.out_of_mem;
output(31 downto 28) := reg.iram_addr_width;
return output;
end function;
-- ---------------------------------------------------------------
-- Test status report
-- ---------------------------------------------------------------
function defaults return t_test_status is
variable temp: t_test_status;
begin
temp.ack_seen := (others => '0');
temp.pll_mmi_err := (others => '0');
temp.pll_busy := '0';
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status is
variable temp : t_test_status;
begin
temp := defaults;
temp.ack_seen := pack_ack_seen(ctrl_mmi.ctrl_cal_stage_ack_seen);
temp.pll_mmi_err := pll_mmi.err;
temp.pll_busy := pll_mmi.pll_busy or rw_if_test.pll_phs_shft_up_wc or rw_if_test.pll_phs_shft_dn_wc;
return temp;
end function;
-- read for mmi status register
function read ( reg : t_test_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output(31 downto 32-c_hl_ccs_num_stages) := reg.ack_seen;
output( 5 downto 4) := reg.pll_mmi_err;
output(0) := reg.pll_busy;
return output;
end function;
-------------------------------------------------
-- FOR ALL RO REGS:
-------------------------------------------------
function defaults return t_ro_regs is
variable temp: t_ro_regs;
begin
temp.cal_status := defaults;
temp.codvw_status := defaults;
return temp;
end function;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs is
variable output : t_ro_regs;
begin
output := defaults;
output.cal_status := defaults(ctrl_mmi, USE_IRAM, dqs_capture, int_ac_1t, trefi_failure, iram_status, IRAM_AWIDTH);
output.codvw_status := defaults(dgrb_mmi);
output.test_status := defaults(ctrl_mmi, pll_mmi, rw_if_test);
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- mode register set A
-- ---------------------------------------------------------------
function defaults return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := (others => '0');
temp.mr1 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp := defaults;
temp.mr0 := mr0(temp.mr0'range);
temp.mr1 := mr1(temp.mr1'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr1 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_a) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr0;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr1;
return temp;
end function;
-- ---------------------------------------------------------------
-- mode register set B
-- ---------------------------------------------------------------
function defaults return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := (others => '0');
temp.mr3 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp := defaults;
temp.mr2 := mr2(temp.mr2'range);
temp.mr3 := mr3(temp.mr3'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr3 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_b) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr2;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr3;
return temp;
end function;
-- ---------------------------------------------------------------
-- HL CSS (high level calibration state status)
-- ---------------------------------------------------------------
function defaults return t_hl_css is
variable temp : t_hl_css;
begin
temp.hl_css := (others => '0');
temp.cal_start := '0';
return temp;
end function;
function defaults ( C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
) return t_hl_css is
variable temp: t_hl_css;
begin
temp := defaults;
temp.hl_css := temp.hl_css OR C_HL_STAGE_ENABLE;
return temp;
end function;
function read ( reg : in t_hl_css) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp(30 downto 30-c_hl_ccs_num_stages+1) := reg.hl_css;
temp(0) := reg.cal_start;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0) )return t_hl_css is
variable reg : t_hl_css;
begin
reg.hl_css := wdata_in(30 downto 30-c_hl_ccs_num_stages+1);
reg.cal_start := wdata_in(0);
return reg;
end function;
procedure write_clear (signal reg : inout t_hl_css) is
begin
reg.cal_start <= '0';
end procedure;
-- ---------------------------------------------------------------
-- paramaterisation of sequencer through Avalon interface
-- ---------------------------------------------------------------
function defaults return t_parameterisation_reg_a is
variable temp : t_parameterisation_reg_a;
begin
temp.nominal_poa_phase_lead := (others => '0');
temp.maximum_poa_delay := (others => '0');
temp.pll_360_sweeps := "0000";
temp.num_phases_per_tck_pll := "0011";
temp.nominal_dqs_delay := (others => '0');
temp.extend_octrt_by := "0100";
temp.delay_octrt_by := "0000";
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a is
variable temp: t_parameterisation_reg_a;
begin
temp := defaults;
temp.num_phases_per_tck_pll := std_logic_vector(to_unsigned(PLL_STEPS_PER_CYCLE /8 , temp.num_phases_per_tck_pll'high + 1 ));
temp.pll_360_sweeps := std_logic_vector(to_unsigned(pll_360_sweeps , temp.pll_360_sweeps'high + 1 ));
temp.nominal_dqs_delay := std_logic_vector(to_unsigned(NOM_DQS_PHASE_SETTING , temp.nominal_dqs_delay'high + 1 ));
temp.extend_octrt_by := std_logic_vector(to_unsigned(5 , temp.extend_octrt_by'high + 1 ));
temp.delay_octrt_by := std_logic_vector(to_unsigned(6 , temp.delay_octrt_by'high + 1 ));
return temp;
end function;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := reg.pll_360_sweeps;
temp( 7 downto 4) := reg.num_phases_per_tck_pll;
temp(10 downto 8) := reg.nominal_dqs_delay;
temp(19 downto 16) := reg.nominal_poa_phase_lead;
temp(23 downto 20) := reg.maximum_poa_delay;
temp(27 downto 24) := reg.extend_octrt_by;
temp(31 downto 28) := reg.delay_octrt_by;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a is
variable reg : t_parameterisation_reg_a;
begin
reg.pll_360_sweeps := wdata_in( 3 downto 0);
reg.num_phases_per_tck_pll := wdata_in( 7 downto 4);
reg.nominal_dqs_delay := wdata_in(10 downto 8);
reg.nominal_poa_phase_lead := wdata_in(19 downto 16);
reg.maximum_poa_delay := wdata_in(23 downto 20);
reg.extend_octrt_by := wdata_in(27 downto 24);
reg.delay_octrt_by := wdata_in(31 downto 28);
return reg;
end function;
-- ---------------------------------------------------------------
-- t_if_test_reg - additional test support register
-- ---------------------------------------------------------------
function defaults return t_if_test_reg is
variable temp : t_if_test_reg;
begin
temp.pll_phs_shft_phase_sel := 0;
temp.pll_phs_shft_up_wc := '0';
temp.pll_phs_shft_dn_wc := '0';
temp.ac_1t_toggle := '0';
temp.tracking_period_ms := "10000000"; -- 127 ms interval
temp.tracking_units_are_10us := '0';
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg is
variable temp: t_if_test_reg;
begin
temp := defaults;
temp.tracking_period_ms := std_logic_vector(to_unsigned(TRACKING_INTERVAL_IN_MS, temp.tracking_period_ms'length));
return temp;
end function;
function read ( reg : in t_if_test_reg) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := std_logic_vector(to_unsigned(reg.pll_phs_shft_phase_sel,4));
temp(4) := reg.pll_phs_shft_up_wc;
temp(5) := reg.pll_phs_shft_dn_wc;
temp(16) := reg.ac_1t_toggle;
temp(15 downto 8) := reg.tracking_period_ms;
temp(20) := reg.tracking_units_are_10us;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg is
variable reg : t_if_test_reg;
begin
reg.pll_phs_shft_phase_sel := to_integer(unsigned(wdata_in( 3 downto 0)));
reg.pll_phs_shft_up_wc := wdata_in(4);
reg.pll_phs_shft_dn_wc := wdata_in(5);
reg.ac_1t_toggle := wdata_in(16);
reg.tracking_period_ms := wdata_in(15 downto 8);
reg.tracking_units_are_10us := wdata_in(20);
return reg;
end function;
procedure write_clear (signal reg : inout t_if_test_reg) is
begin
reg.ac_1t_toggle <= '0';
reg.pll_phs_shft_up_wc <= '0';
reg.pll_phs_shft_dn_wc <= '0';
end procedure;
-- ---------------------------------------------------------------
-- RW Regs, record of read/write register records (to simplify handling)
-- ---------------------------------------------------------------
function defaults return t_rw_regs is
variable temp : t_rw_regs;
begin
temp.mr_reg_a := defaults;
temp.mr_reg_b := defaults;
temp.rw_hl_css := defaults;
temp.rw_param_reg := defaults;
temp.rw_if_test := defaults;
return temp;
end function;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs is
variable temp : t_rw_regs;
begin
temp := defaults;
temp.mr_reg_a := defaults(mr0, mr1);
temp.mr_reg_b := defaults(mr2, mr3);
temp.rw_param_reg := defaults(NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
pll_360_sweeps);
temp.rw_if_test := defaults(TRACKING_INTERVAL_IN_MS);
temp.rw_hl_css := defaults(C_HL_STAGE_ENABLE);
return temp;
end function;
procedure write_clear (signal regs : inout t_rw_regs) is
begin
write_clear(regs.rw_if_test);
write_clear(regs.rw_hl_css);
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- All mmi registers:
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs is
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs.rw_regs := defaults;
v_mmi_regs.ro_regs := defaults;
v_mmi_regs.enable_writes := '0';
return v_mmi_regs;
end function;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
case address is
-- status register
when c_regofst_cal_status => output := read (mmi_regs.ro_regs.cal_status);
-- debug access register
when c_regofst_debug_access =>
if (mmi_regs.enable_writes = '1') then
output := c_mmi_access_codeword;
else
output := (others => '0');
end if;
-- test i/f to check which stages have acknowledged a command and pll checks
when c_regofst_test_status => output := read(mmi_regs.ro_regs.test_status);
-- mode registers
when c_regofst_mr_register_a => output := read(mmi_regs.rw_regs.mr_reg_a);
when c_regofst_mr_register_b => output := read(mmi_regs.rw_regs.mr_reg_b);
-- codvw r/o status register
when c_regofst_codvw_status => output := read(mmi_regs.ro_regs.codvw_status);
-- read/write registers
when c_regofst_hl_css => output := read(mmi_regs.rw_regs.rw_hl_css);
when c_regofst_if_param => output := read(mmi_regs.rw_regs.rw_param_reg);
when c_regofst_if_test => output := read(mmi_regs.rw_regs.rw_if_test);
when others => report regs_report_prefix & "MMI registers detected an attempt to read to non-existant register location" severity warning;
-- set illegal addr interrupt.
end case;
return output;
end function;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs := mmi_regs;
output := v_read(v_mmi_regs, address);
return output;
end function;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0)) is
begin
-- intercept writes to codeword. This needs to be set for iRAM access :
if address = c_regofst_debug_access then
if wdata = c_mmi_access_codeword then
mmi_regs.enable_writes := '1';
else
mmi_regs.enable_writes := '0';
end if;
else
case address is
-- read only registers
when c_regofst_cal_status |
c_regofst_codvw_status |
c_regofst_test_status =>
report regs_report_prefix & "MMI registers detected an attempt to write to read only register number" & integer'image(address) severity failure;
-- read/write registers
when c_regofst_mr_register_a => mmi_regs.rw_regs.mr_reg_a := write(wdata);
when c_regofst_mr_register_b => mmi_regs.rw_regs.mr_reg_b := write(wdata);
when c_regofst_hl_css => mmi_regs.rw_regs.rw_hl_css := write(wdata);
when c_regofst_if_param => mmi_regs.rw_regs.rw_param_reg := write(wdata);
when c_regofst_if_test => mmi_regs.rw_regs.rw_if_test := write(wdata);
when others => -- set illegal addr interrupt.
report regs_report_prefix & "MMI registers detected an attempt to write to non existant register, with expected number" & integer'image(address) severity failure;
end case;
end if;
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- the following functions enable register data to be communicated to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function pack_record ( ip_regs : t_rw_regs
) return t_algm_paramaterisation is
variable output : t_algm_paramaterisation;
begin
-- default assignments
output.num_phases_per_tck_pll := 16;
output.pll_360_sweeps := 1;
output.nominal_dqs_delay := 2;
output.nominal_poa_phase_lead := 1;
output.maximum_poa_delay := 5;
output.odt_enabled := false;
output.num_phases_per_tck_pll := to_integer(unsigned(ip_regs.rw_param_reg.num_phases_per_tck_pll)) * 8;
case ip_regs.rw_param_reg.nominal_dqs_delay is
when "010" => output.nominal_dqs_delay := 2;
when "001" => output.nominal_dqs_delay := 1;
when "000" => output.nominal_dqs_delay := 0;
when "011" => output.nominal_dqs_delay := 3;
when others => report regs_report_prefix &
"there is a unsupported number of DQS taps (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_dqs_delay))) &
") being advertised as the standard value" severity error;
end case;
case ip_regs.rw_param_reg.nominal_poa_phase_lead is
when "0001" => output.nominal_poa_phase_lead := 1;
when "0010" => output.nominal_poa_phase_lead := 2;
when "0011" => output.nominal_poa_phase_lead := 3;
when "0000" => output.nominal_poa_phase_lead := 0;
when others => report regs_report_prefix &
"there is an unsupported nominal postamble phase lead paramater set (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_poa_phase_lead))) &
")" severity error;
end case;
if ( (ip_regs.mr_reg_a.mr1(2) = '1')
or (ip_regs.mr_reg_a.mr1(6) = '1')
or (ip_regs.mr_reg_a.mr1(9) = '1')
) then
output.odt_enabled := true;
end if;
output.pll_360_sweeps := to_integer(unsigned(ip_regs.rw_param_reg.pll_360_sweeps));
output.maximum_poa_delay := to_integer(unsigned(ip_regs.rw_param_reg.maximum_poa_delay));
output.extend_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.extend_octrt_by));
output.delay_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.delay_octrt_by));
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig is
variable output : t_mmi_pll_reconfig;
begin
output.pll_phs_shft_phase_sel := ip_regs.rw_if_test.pll_phs_shft_phase_sel;
output.pll_phs_shft_up_wc := ip_regs.rw_if_test.pll_phs_shft_up_wc;
output.pll_phs_shft_dn_wc := ip_regs.rw_if_test.pll_phs_shft_dn_wc;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl is
variable output : t_admin_ctrl := defaults;
begin
output.mr0 := ip_regs.mr_reg_a.mr0;
output.mr1 := ip_regs.mr_reg_a.mr1;
output.mr2 := ip_regs.mr_reg_b.mr2;
output.mr3 := ip_regs.mr_reg_b.mr3;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl is
variable output : t_mmi_ctrl := defaults;
begin
output.hl_css := to_t_hl_css_reg (ip_regs.rw_hl_css);
output.calibration_start := ip_regs.rw_hl_css.cal_start;
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
output.tracking_orvd_to_10ms := ip_regs.rw_if_test.tracking_units_are_10us;
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- Helper functions :
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css
) return t_hl_css_reg is
variable output : t_hl_css_reg := defaults;
begin
output.phy_initialise_dis := hl_css.hl_css(c_hl_css_reg_phy_initialise_dis_bit);
output.init_dram_dis := hl_css.hl_css(c_hl_css_reg_init_dram_dis_bit);
output.write_ihi_dis := hl_css.hl_css(c_hl_css_reg_write_ihi_dis_bit);
output.cal_dis := hl_css.hl_css(c_hl_css_reg_cal_dis_bit);
output.write_btp_dis := hl_css.hl_css(c_hl_css_reg_write_btp_dis_bit);
output.write_mtp_dis := hl_css.hl_css(c_hl_css_reg_write_mtp_dis_bit);
output.read_mtp_dis := hl_css.hl_css(c_hl_css_reg_read_mtp_dis_bit);
output.rrp_reset_dis := hl_css.hl_css(c_hl_css_reg_rrp_reset_dis_bit);
output.rrp_sweep_dis := hl_css.hl_css(c_hl_css_reg_rrp_sweep_dis_bit);
output.rrp_seek_dis := hl_css.hl_css(c_hl_css_reg_rrp_seek_dis_bit);
output.rdv_dis := hl_css.hl_css(c_hl_css_reg_rdv_dis_bit);
output.poa_dis := hl_css.hl_css(c_hl_css_reg_poa_dis_bit);
output.was_dis := hl_css.hl_css(c_hl_css_reg_was_dis_bit);
output.adv_rd_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_rd_lat_dis_bit);
output.adv_wr_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_wr_lat_dis_bit);
output.prep_customer_mr_setup_dis := hl_css.hl_css(c_hl_css_reg_prep_customer_mr_setup_dis_bit);
output.tracking_dis := hl_css.hl_css(c_hl_css_reg_tracking_dis_bit);
return output;
end function;
-- pack the ack seen record element into a std_logic_vector
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector is
variable v_output: std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
variable v_start : natural range 0 to c_hl_ccs_num_stages-1;
begin
v_output := (others => '0');
v_output(c_hl_css_reg_cal_dis_bit ) := cal_stage_ack_seen.cal;
v_output(c_hl_css_reg_phy_initialise_dis_bit ) := cal_stage_ack_seen.phy_initialise;
v_output(c_hl_css_reg_init_dram_dis_bit ) := cal_stage_ack_seen.init_dram;
v_output(c_hl_css_reg_write_ihi_dis_bit ) := cal_stage_ack_seen.write_ihi;
v_output(c_hl_css_reg_write_btp_dis_bit ) := cal_stage_ack_seen.write_btp;
v_output(c_hl_css_reg_write_mtp_dis_bit ) := cal_stage_ack_seen.write_mtp;
v_output(c_hl_css_reg_read_mtp_dis_bit ) := cal_stage_ack_seen.read_mtp;
v_output(c_hl_css_reg_rrp_reset_dis_bit ) := cal_stage_ack_seen.rrp_reset;
v_output(c_hl_css_reg_rrp_sweep_dis_bit ) := cal_stage_ack_seen.rrp_sweep;
v_output(c_hl_css_reg_rrp_seek_dis_bit ) := cal_stage_ack_seen.rrp_seek;
v_output(c_hl_css_reg_rdv_dis_bit ) := cal_stage_ack_seen.rdv;
v_output(c_hl_css_reg_poa_dis_bit ) := cal_stage_ack_seen.poa;
v_output(c_hl_css_reg_was_dis_bit ) := cal_stage_ack_seen.was;
v_output(c_hl_css_reg_adv_rd_lat_dis_bit ) := cal_stage_ack_seen.adv_rd_lat;
v_output(c_hl_css_reg_adv_wr_lat_dis_bit ) := cal_stage_ack_seen.adv_wr_lat;
v_output(c_hl_css_reg_prep_customer_mr_setup_dis_bit) := cal_stage_ack_seen.prep_customer_mr_setup;
v_output(c_hl_css_reg_tracking_dis_bit ) := cal_stage_ack_seen.tracking_setup;
return v_output;
end function;
-- reg encoding of current stage
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id
) return std_logic_vector is
variable output : std_logic_vector(7 downto 0);
begin
case ctrl_cmd_id is
when cmd_idle => output := X"00";
when cmd_phy_initialise => output := X"01";
when cmd_init_dram |
cmd_prog_cal_mr => output := X"02";
when cmd_write_ihi => output := X"03";
when cmd_write_btp => output := X"04";
when cmd_write_mtp => output := X"05";
when cmd_read_mtp => output := X"06";
when cmd_rrp_reset => output := X"07";
when cmd_rrp_sweep => output := X"08";
when cmd_rrp_seek => output := X"09";
when cmd_rdv => output := X"0A";
when cmd_poa => output := X"0B";
when cmd_was => output := X"0C";
when cmd_prep_adv_rd_lat => output := X"0D";
when cmd_prep_adv_wr_lat => output := X"0E";
when cmd_prep_customer_mr_setup => output := X"0F";
when cmd_tr_due => output := X"10";
when others =>
null;
report regs_report_prefix & "unknown cal command (" & t_ctrl_cmd_id'image(ctrl_cmd_id) & ") seen in encode_current_stage function" severity failure;
end case;
return output;
end function;
-- reg encoding of current active block
function encode_active_block (active_block : t_ctrl_active_block
) return std_logic_vector is
variable output : std_logic_vector(3 downto 0);
begin
case active_block is
when idle => output := X"0";
when admin => output := X"1";
when dgwb => output := X"2";
when dgrb => output := X"3";
when proc => output := X"4";
when setup => output := X"5";
when iram => output := X"6";
when others =>
output := X"7";
report regs_report_prefix & "unknown active_block seen in encode_active_block function" severity failure;
end case;
return output;
end function;
--
end ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : mmi block for the non-levelling AFI PHY sequencer
-- This is an optional block with an Avalon interface and status
-- register instantiations to enhance the debug capabilities of
-- the sequencer. The format of the block is:
-- a) an Avalon interface which supports different avalon and
-- sequencer clock sources
-- b) mmi status registers (which hold information about the
-- successof the calibration)
-- c) a read interface to the iram to enable debug through the
-- avalon interface.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_mmi is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DQS_CAPTURE : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural;
AV_IF_ADDR_WIDTH : natural;
MEM_IF_MEMTYPE : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : std_logic_vector(15 downto 0);
PHY_DEF_MR_2ND : std_logic_vector(15 downto 0);
PHY_DEF_MR_3RD : std_logic_vector(15 downto 0);
PHY_DEF_MR_4TH : std_logic_vector(15 downto 0);
PRESET_RLAT : natural; -- read latency preset value
CAPABILITIES : natural; -- sequencer capabilities flags
USE_IRAM : std_logic; -- RFU
IRAM_AWIDTH : natural;
TRACKING_INTERVAL_IN_MS : natural;
READ_LAT_WIDTH : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock)
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH -1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic;
-- mmi to admin interface
regs_admin_ctrl : out t_admin_ctrl;
admin_regs_status : in t_admin_stat;
trefi_failure : in std_logic;
-- mmi to iram interface
mmi_iram : out t_iram_ctrl;
mmi_iram_enable_writes : out std_logic;
iram_status : in t_iram_stat;
-- mmi to control interface
mmi_ctrl : out t_mmi_ctrl;
ctrl_mmi : in t_ctrl_mmi;
int_ac_1t : in std_logic;
invert_ac_1t : out std_logic;
-- global parameterisation record
parameterisation_rec : out t_algm_paramaterisation;
-- mmi pll interface
pll_mmi : in t_pll_mmi;
mmi_pll : out t_mmi_pll_reconfig;
-- codvw status signals
dgrb_mmi : in t_dgrb_mmi
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_mmi IS
-- maximum function
function max (a, b : natural) return natural is
begin
if a > b then
return a;
else
return b;
end if;
end function;
-- -------------------------------------------
-- constant definitions
-- -------------------------------------------
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE);
constant c_response_lat : natural := 6;
constant c_codeword : std_logic_vector(31 downto 0) := c_mmi_access_codeword;
constant c_int_iram_start_size : natural := max(IRAM_AWIDTH, 4);
-- enable for ctrl state machine states
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(CAPABILITIES, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
-- a prefix for all report signals to identify phy and sequencer block
--
constant mmi_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (mmi) : ";
-- --------------------------------------------
-- internal signals
-- --------------------------------------------
-- internal clock domain register interface signals
signal int_wdata : std_logic_vector(31 downto 0);
signal int_rdata : std_logic_vector(31 downto 0);
signal int_address : std_logic_vector(AV_IF_ADDR_WIDTH-1 downto 0);
signal int_read : std_logic;
signal int_cs : std_logic;
signal int_write : std_logic;
signal waitreq_int : std_logic;
-- register storage
-- contains:
-- read only (ro_regs)
-- read/write (rw_regs)
-- enable_writes flag
signal mmi_regs : t_mmi_regs := defaults;
signal mmi_rw_regs_initialised : std_logic;
-- this counter ensures that the mmi waits for c_response_lat clocks before
-- responding to a new Avalon request
signal waitreq_count : natural range 0 to 15;
signal waitreq_count_is_zero : std_logic;
-- register error signals
signal int_ac_1t_r : std_logic;
signal trefi_failure_r : std_logic;
-- iram ready - calibration complete and USE_IRAM high
signal iram_ready : std_logic;
begin -- architecture struct
-- the following signals are reserved for future use
invert_ac_1t <= '0';
-- --------------------------------------------------------------
-- generate for synchronous avalon interface
-- --------------------------------------------------------------
simply_registered_avalon : if RESYNCHRONISE_AVALON_DBG = 0 generate
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
elsif rising_edge(clk) then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= dbg_seq_cs;
end if;
end process;
seq_dbg_rd_data <= int_rdata;
seq_dbg_waitrequest <= waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate simply_registered_avalon;
-- --------------------------------------------------------------
-- clock domain crossing for asynchronous mmi interface
-- --------------------------------------------------------------
re_synchronise_avalon : if RESYNCHRONISE_AVALON_DBG = 1 generate
--clock domain crossing signals
signal ccd_new_cmd : std_logic;
signal ccd_new_cmd_ack : std_logic;
signal ccd_cmd_done : std_logic;
signal ccd_cmd_done_ack : std_logic;
signal ccd_rd_data : std_logic_vector(dbg_seq_wr_data'range);
signal ccd_cmd_done_ack_t : std_logic;
signal ccd_cmd_done_ack_2t : std_logic;
signal ccd_cmd_done_ack_3t : std_logic;
signal ccd_cmd_done_t : std_logic;
signal ccd_cmd_done_2t : std_logic;
signal ccd_cmd_done_3t : std_logic;
signal ccd_new_cmd_t : std_logic;
signal ccd_new_cmd_2t : std_logic;
signal ccd_new_cmd_3t : std_logic;
signal ccd_new_cmd_ack_t : std_logic;
signal ccd_new_cmd_ack_2t : std_logic;
signal ccd_new_cmd_ack_3t : std_logic;
signal cmd_pending : std_logic;
signal seq_clk_waitreq_int : std_logic;
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
ccd_new_cmd_ack <= '0';
ccd_new_cmd_t <= '0';
ccd_new_cmd_2t <= '0';
ccd_new_cmd_3t <= '0';
elsif rising_edge(clk) then
ccd_new_cmd_t <= ccd_new_cmd;
ccd_new_cmd_2t <= ccd_new_cmd_t;
ccd_new_cmd_3t <= ccd_new_cmd_2t;
if ccd_new_cmd_3t = '0' and ccd_new_cmd_2t = '1' then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= '1';
ccd_new_cmd_ack <= '1';
elsif ccd_new_cmd_3t = '1' and ccd_new_cmd_2t = '0' then
ccd_new_cmd_ack <= '0';
end if;
if int_cs = '1' and waitreq_int= '0' then
int_cs <= '0';
int_read <= '0';
int_write <= '0';
end if;
end if;
end process;
-- process to generate new cmd
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_new_cmd <= '0';
ccd_new_cmd_ack_t <= '0';
ccd_new_cmd_ack_2t <= '0';
ccd_new_cmd_ack_3t <= '0';
cmd_pending <= '0';
elsif rising_edge(dbg_seq_clk) then
ccd_new_cmd_ack_t <= ccd_new_cmd_ack;
ccd_new_cmd_ack_2t <= ccd_new_cmd_ack_t;
ccd_new_cmd_ack_3t <= ccd_new_cmd_ack_2t;
if ccd_new_cmd = '0' and dbg_seq_cs = '1' and cmd_pending = '0' then
ccd_new_cmd <= '1';
cmd_pending <= '1';
elsif ccd_new_cmd_ack_2t = '1' and ccd_new_cmd_ack_3t = '0' then
ccd_new_cmd <= '0';
end if;
-- use falling edge of cmd_done
if cmd_pending = '1' and ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
cmd_pending <= '0';
end if;
end if;
end process;
-- process to take read data back and transfer it across the clock domains
process (rst_n, clk)
begin
if rst_n = '0' then
ccd_cmd_done <= '0';
ccd_rd_data <= (others => '0');
ccd_cmd_done_ack_3t <= '0';
ccd_cmd_done_ack_2t <= '0';
ccd_cmd_done_ack_t <= '0';
elsif rising_edge(clk) then
if ccd_cmd_done_ack_2t = '1' and ccd_cmd_done_ack_3t = '0' then
ccd_cmd_done <= '0';
elsif waitreq_int = '0' then
ccd_cmd_done <= '1';
ccd_rd_data <= int_rdata;
end if;
ccd_cmd_done_ack_3t <= ccd_cmd_done_ack_2t;
ccd_cmd_done_ack_2t <= ccd_cmd_done_ack_t;
ccd_cmd_done_ack_t <= ccd_cmd_done_ack;
end if;
end process;
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_cmd_done_ack <= '0';
ccd_cmd_done_3t <= '0';
ccd_cmd_done_2t <= '0';
ccd_cmd_done_t <= '0';
seq_dbg_rd_data <= (others => '0');
seq_clk_waitreq_int <= '1';
elsif rising_edge(dbg_seq_clk) then
seq_clk_waitreq_int <= '1';
if ccd_cmd_done_2t = '1' and ccd_cmd_done_3t = '0' then
seq_clk_waitreq_int <= '0';
ccd_cmd_done_ack <= '1';
seq_dbg_rd_data <= ccd_rd_data; -- if read
elsif ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
ccd_cmd_done_ack <= '0';
end if;
ccd_cmd_done_3t <= ccd_cmd_done_2t;
ccd_cmd_done_2t <= ccd_cmd_done_t;
ccd_cmd_done_t <= ccd_cmd_done;
end if;
end process;
seq_dbg_waitrequest <= seq_clk_waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate re_synchronise_avalon;
-- register some inputs for speed.
process (rst_n, clk)
begin
if rst_n = '0' then
int_ac_1t_r <= '0';
trefi_failure_r <= '0';
elsif rising_edge(clk) then
int_ac_1t_r <= int_ac_1t;
trefi_failure_r <= trefi_failure;
end if;
end process;
-- mmi not able to write to iram in current instance of mmi block
mmi_iram_enable_writes <= '0';
-- check if iram ready
process (rst_n, clk)
begin
if rst_n = '0' then
iram_ready <= '0';
elsif rising_edge(clk) then
if USE_IRAM = '0' then
iram_ready <= '0';
else
if ctrl_mmi.ctrl_calibration_success = '1' or ctrl_mmi.ctrl_calibration_fail = '1' then
iram_ready <= '1';
else
iram_ready <= '0';
end if;
end if;
end if;
end process;
-- --------------------------------------------------------------
-- single registered process for mmi access.
-- --------------------------------------------------------------
process (rst_n, clk)
variable v_mmi_regs : t_mmi_regs;
begin
if rst_n = '0' then
mmi_regs <= defaults;
mmi_rw_regs_initialised <= '0';
-- this register records whether the c_codeword has been written to address 0x0001
-- once it has, then other writes are accepted.
mmi_regs.enable_writes <= '0';
int_rdata <= (others => '0');
waitreq_int <= '1';
-- clear wait request counter
waitreq_count <= 0;
waitreq_count_is_zero <= '1';
-- iram interface defaults
mmi_iram <= defaults;
elsif rising_edge(clk) then
-- default assignment
waitreq_int <= '1';
write_clear(mmi_regs.rw_regs);
-- only initialise rw_regs once after hard reset
if mmi_rw_regs_initialised = '0' then
mmi_rw_regs_initialised <= '1';
--reset all read/write regs and read path ouput registers and apply default MRS Settings.
mmi_regs.rw_regs <= defaults(PHY_DEF_MR_1ST,
PHY_DEF_MR_2ND,
PHY_DEF_MR_3RD,
PHY_DEF_MR_4TH,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps, -- number of times 360 degrees is swept
TRACKING_INTERVAL_IN_MS,
c_hl_stage_enable);
end if;
-- bit packing input data structures into the ro_regs structure, for reading
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
USE_IRAM,
MEM_IF_DQS_CAPTURE,
int_ac_1t_r,
trefi_failure_r,
iram_status,
IRAM_AWIDTH);
-- write has priority over read
if int_write = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register write
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
v_mmi_regs := mmi_regs;
write(v_mmi_regs, to_integer(unsigned(int_address(3 downto 0))), int_wdata);
if mmi_regs.enable_writes = '1' then
v_mmi_regs.rw_regs.rw_hl_css.hl_css := c_hl_stage_enable or v_mmi_regs.rw_regs.rw_hl_css.hl_css;
end if;
mmi_regs <= v_mmi_regs;
-- handshake for safe transactions
waitreq_int <= '0';
waitreq_count <= c_response_lat;
-- iram write just handshake back (no write supported)
else
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif int_read = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register read
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
int_rdata <= read(mmi_regs, to_integer(unsigned(int_address(3 downto 0))));
waitreq_count <= c_response_lat;
waitreq_int <= '0'; -- acknowledge read command regardless.
-- iram being addressed
elsif to_integer(unsigned(int_address(int_address'high downto c_int_iram_start_size))) = 1
and iram_ready = '1'
then
mmi_iram.read <= '1';
mmi_iram.addr <= to_integer(unsigned(int_address(IRAM_AWIDTH -1 downto 0)));
if iram_status.done = '1' then
waitreq_int <= '0';
mmi_iram.read <= '0';
waitreq_count <= c_response_lat;
int_rdata <= iram_status.rdata;
end if;
else -- respond and keep the interface from hanging
int_rdata <= x"DEADBEEF";
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif waitreq_count /= 0 then
waitreq_count <= waitreq_count -1;
-- if performing a write, set back to defaults. If not, default anyway
mmi_iram <= defaults;
end if;
if waitreq_count = 1 or waitreq_count = 0 then
waitreq_count_is_zero <= '1'; -- as it will be next clock cycle
else
waitreq_count_is_zero <= '0';
end if;
-- supply iram read data when ready
if iram_status.done = '1' then
int_rdata <= iram_status.rdata;
end if;
end if;
end process;
-- pack the registers into the output data structures
regs_admin_ctrl <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : admin block for the non-levelling AFI PHY sequencer
-- The admin block supports the autonomy of the sequencer from
-- the memory interface controller. In this task admin handles
-- memory initialisation (incl. the setting of mode registers)
-- and memory refresh, bank activation and pre-charge commands
-- (during memory interface calibration). Once calibration is
-- complete admin is 'idle' and control of the memory device is
-- passed to the users chosen memory interface controller. The
-- supported memory types are exclusively DDR, DDR2 and DDR3.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_admin is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
MEM_IF_DQSN_EN : natural;
MEM_IF_MEMTYPE : string;
-- calibration address information
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
MEM_IF_CAL_BASE_ROW : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
NON_OP_EVAL_MD : string; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
-- timing parameters
MEM_IF_CLK_PS : natural;
TINIT_TCK : natural; -- initial delay
TINIT_RST : natural -- used for DDR3 device support
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- the 2 signals below are unused for non-levelled sequencer (maintained for equivalent interface to levelled sequencer)
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- addr/cmd interface
seq_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
seq_ac_sel : out std_logic;
-- determined from MR settings
enable_odt : out std_logic;
-- interface to the mmi block
regs_admin_ctrl_rec : in t_admin_ctrl;
admin_regs_status_rec : out t_admin_stat;
trefi_failure : out std_logic;
-- interface to the ctrl block
ctrl_admin : in t_ctrl_command;
admin_ctrl : out t_ctrl_stat;
-- interface with dgrb/dgwb blocks
ac_access_req : in std_logic;
ac_access_gnt : out std_logic;
-- calibration status signals (from ctrl block)
cal_fail : in std_logic;
cal_success : in std_logic;
-- recalibrate request issued
ctl_recalibrate_req : in std_logic
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_admin is
constant c_max_mode_reg_index : natural := 12;
-- timing below is safe for range 80-400MHz operation - taken from worst case DDR2 (JEDEC JESD79-2E) / DDR3 (JESD79-3B)
-- Note: timings account for worst case use for both full rate and half rate ALTMEMPHY interfaces
constant c_init_prech_delay : natural := 162; -- precharge delay (360ns = tRFC+10ns) (TXPR for DDR3)
constant c_trp_in_clks : natural := 8; -- set equal to trp / tck (trp = 15ns)
constant c_tmrd_in_clks : natural := 4; -- maximum 4 clock cycles (DDR3)
constant c_tmod_in_clks : natural := 8; -- ODT update from MRS command (tmod = 12ns (DDR2))
constant c_trrd_min_in_clks : natural := 4; -- minimum clk cycles between bank activate cmds (10ns)
constant c_trcd_min_in_clks : natural := 8; -- minimum bank activate to read/write cmd (15ns)
-- the 2 constants below are parameterised to MEM_IF_CLK_PS due to the large range of possible clock frequency
constant c_trfc_min_in_clks : natural := (350000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) + 2; -- refresh-refresh timing (worst case trfc = 350 ns (DDR3))
constant c_trefi_min_in_clks : natural := (3900000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) - 2; -- average refresh interval worst case trefi = 3.9 us (industrial grade devices)
constant c_max_num_stacked_refreshes : natural := 8; -- max no. of stacked refreshes allowed
constant c_max_wait_value : natural := 4; -- delay before moving from s_idle to s_refresh_state
-- DDR3 specific:
constant c_zq_init_duration_clks : natural := 514; -- full rate (worst case) cycle count for tZQCL init
constant c_tzqcs : natural := 66; -- number of full rate clock cycles
-- below is a record which is used to parameterise the address and command signals (addr_cmd) used in this block
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant admin_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (admin) : ";
-- state type for admin_state (main state machine of admin block)
type t_admin_state is
(
s_reset, -- reset state
s_run_init_seq, -- run the initialisation sequence (up to but not including MR setting)
s_program_cal_mrs, -- program the mode registers ready for calibration (this is the user settings
-- with some overloads and extra init functionality)
s_idle, -- idle (i.e. maintaining refresh to max)
s_topup_refresh, -- make sure refreshes are maxed out before going on.
s_topup_refresh_done, -- wait for tRFC after refresh command
s_zq_cal_short, -- ZQCAL short command (issued prior to activate) - DDR3 only
s_access_act, -- activate
s_access, -- dgrb, dgwb accesses,
s_access_precharge, -- precharge all memory banks
s_prog_user_mrs, -- program user mode register settings
s_dummy_wait, -- wait before going to s_refresh state
s_refresh, -- issue a memory refresh command
s_refresh_done, -- wait for trfc after refresh command
s_non_operational -- special debug state to toggle interface if calibration fails
);
signal state : t_admin_state; -- admin block state machine
-- state type for ac_state
type t_ac_state is
( s_0 ,
s_1 ,
s_2 ,
s_3 ,
s_4 ,
s_5 ,
s_6 ,
s_7 ,
s_8 ,
s_9 ,
s_10,
s_11,
s_12,
s_13,
s_14);
-- enforce one-hot fsm encoding
attribute syn_encoding : string;
attribute syn_encoding of t_ac_state : TYPE is "one-hot";
signal ac_state : t_ac_state; -- state machine for sub-states of t_admin_state states
signal stage_counter : natural range 0 to 2**18 - 1; -- counter to support memory timing delays
signal stage_counter_zero : std_logic;
signal addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1); -- internal copy of output DRAM addr/cmd signals
signal mem_init_complete : std_logic; -- signifies memory initialisation is complete
signal cal_complete : std_logic; -- calibration complete (equals: cal_success OR cal_fail)
signal int_mr0 : std_logic_vector(regs_admin_ctrl_rec.mr0'range); -- an internal copy of mode register settings
signal int_mr1 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr2 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr3 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal refresh_count : natural range c_trefi_min_in_clks downto 0; -- determine when refresh is due
signal refresh_due : std_logic; -- need to do a refresh now
signal refresh_done : std_logic; -- pulse when refresh complete
signal num_stacked_refreshes : natural range 0 to c_max_num_stacked_refreshes - 1; -- can stack upto 8 refreshes (for DDR2)
signal refreshes_maxed : std_logic; -- signal refreshes are maxed out
signal initial_refresh_issued : std_logic; -- to start the refresh counter off
signal ctrl_rec : t_ctrl_command;
-- last state logic
signal command_started : std_logic; -- provides a pulse when admin starts processing a command
signal command_done : std_logic; -- provides a pulse when admin completes processing a command is completed
signal finished_state : std_logic; -- finished current t_admin_state state
signal admin_req_extended : std_logic; -- keep requests for this block asserted until it is an ack is asserted
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1; -- which chip select being programmed at this instance
signal per_cs_init_seen : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- some signals to enable non_operational debug (optimised away if GENERATE_ADDITIONAL_DBG_RTL = 0)
signal nop_toggle_signal : t_addr_cmd_signals;
signal nop_toggle_pin : natural range 0 to MEM_IF_ADDR_WIDTH - 1; -- track which pin in a signal to toggle
signal nop_toggle_value : std_logic;
begin -- architecture struct
-- concurrent assignment of internal addr_cmd to output port seq_ac
process (addr_cmd)
begin
seq_ac <= addr_cmd;
end process;
-- generate calibration complete signal
process (cal_success, cal_fail)
begin
cal_complete <= cal_success or cal_fail;
end process;
-- register the control command record
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_rec <= defaults;
elsif rising_edge(clk) then
ctrl_rec <= ctrl_admin;
end if;
end process;
-- extend the admin block request until ack is asserted
process (clk, rst_n)
begin
if rst_n = '0' then
admin_req_extended <= '0';
elsif rising_edge(clk) then
if ( (ctrl_rec.command_req = '1') and ( curr_active_block(ctrl_rec.command) = admin) ) then
admin_req_extended <= '1';
elsif command_started = '1' then -- this is effectively a copy of command_ack generation
admin_req_extended <= '0';
end if;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if ctrl_rec.command_req = '1' then
current_cs <= ctrl_rec.command_op.current_cs;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- refresh logic: DDR/DDR2/DDR3 allows upto 8 refreshes to be "stacked" or queued up.
-- In the idle state, will ensure refreshes are issued when necessary. Then,
-- when an access_request is received, 7 topup refreshes will be done to max out
-- the number of queued refreshes. That way, we know we have the maximum time
-- available before another refresh is due.
-- -----------------------------------------------------------------------------
-- initial_refresh_issued flag: used to sync refresh_count
process (clk, rst_n)
begin
if rst_n = '0' then
initial_refresh_issued <= '0';
elsif rising_edge(clk) then
if cal_complete = '1' then
initial_refresh_issued <= '0';
else
if state = s_refresh_done or
state = s_topup_refresh_done then
initial_refresh_issued <= '1';
end if;
end if;
end if;
end process;
-- refresh timer: used to work out when a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_count <= c_trefi_min_in_clks;
elsif rising_edge(clk) then
if cal_complete = '1' then
refresh_count <= c_trefi_min_in_clks;
else
if refresh_count = 0 or
initial_refresh_issued = '0' or
(refreshes_maxed = '1' and refresh_done = '1') then -- if refresh issued when already maxed
refresh_count <= c_trefi_min_in_clks;
else
refresh_count <= refresh_count - 1;
end if;
end if;
end if;
end process;
-- refresh_due generation: 1 cycle pulse to indicate that c_trefi_min_in_clks has elapsed, and
-- therefore a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_due <= '0';
elsif rising_edge(clk) then
if refresh_count = 0 and cal_complete = '0' then
refresh_due <= '1';
else
refresh_due <= '0';
end if;
end if;
end process;
-- counter to keep track of number of refreshes "stacked". NB: Up to 8
-- refreshes can be stacked.
process (clk, rst_n)
begin
if rst_n = '0' then
num_stacked_refreshes <= 0;
trefi_failure <= '0'; -- default no trefi failure
elsif rising_edge (clk) then
if state = s_reset then
trefi_failure <= '0'; -- default no trefi failure (in restart)
end if;
if cal_complete = '1' then
num_stacked_refreshes <= 0;
else
if refresh_due = '1' and num_stacked_refreshes /= 0 then
num_stacked_refreshes <= num_stacked_refreshes - 1;
elsif refresh_done = '1' and num_stacked_refreshes /= c_max_num_stacked_refreshes - 1 then
num_stacked_refreshes <= num_stacked_refreshes + 1;
end if;
-- debug message if stacked refreshes are depleted and refresh is due
if refresh_due = '1' and num_stacked_refreshes = 0 and initial_refresh_issued = '1' then
report admin_report_prefix & "error refresh is due and num_stacked_refreshes is zero" severity error;
trefi_failure <= '1'; -- persist
end if;
end if;
end if;
end process;
-- generate signal to state if refreshes are maxed out
process (clk, rst_n)
begin
if rst_n = '0' then
refreshes_maxed <= '0';
elsif rising_edge (clk) then
if num_stacked_refreshes < c_max_num_stacked_refreshes - 1 then
refreshes_maxed <= '0';
else
refreshes_maxed <= '1';
end if;
end if;
end process;
-- ----------------------------------------------------
-- Mode register selection
-- -----------------------------------------------------
int_mr0(regs_admin_ctrl_rec.mr0'range) <= regs_admin_ctrl_rec.mr0;
int_mr1(regs_admin_ctrl_rec.mr1'range) <= regs_admin_ctrl_rec.mr1;
int_mr2(regs_admin_ctrl_rec.mr2'range) <= regs_admin_ctrl_rec.mr2;
int_mr3(regs_admin_ctrl_rec.mr3'range) <= regs_admin_ctrl_rec.mr3;
-- -------------------------------------------------------
-- State machine
-- -------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
state <= s_reset;
command_done <= '0';
command_started <= '0';
elsif rising_edge(clk) then
-- Last state logic
command_done <= '0';
command_started <= '0';
case state is
when s_reset |
s_non_operational =>
if ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then
state <= s_run_init_seq;
command_started <= '1';
end if;
when s_run_init_seq =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_program_cal_mrs =>
if finished_state = '1' then
if refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh if all ranks initialised
state <= s_topup_refresh;
else
state <= s_idle;
end if;
command_done <= '1';
end if;
when s_idle =>
if ac_access_req = '1' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then -- start initialisation sequence
state <= s_run_init_seq;
command_started <= '1';
elsif ctrl_rec.command = cmd_prog_cal_mr and admin_req_extended = '1' then -- program mode registers (used for >1 chip select)
state <= s_program_cal_mrs;
command_started <= '1';
-- always enter s_prog_user_mrs via topup refresh
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_topup_refresh;
elsif refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh once all ranks initialised
state <= s_dummy_wait;
end if;
when s_dummy_wait =>
if finished_state = '1' then
state <= s_refresh;
end if;
when s_topup_refresh =>
if finished_state = '1' then
state <= s_topup_refresh_done;
end if;
when s_topup_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_prog_user_mrs;
command_started <= '1';
elsif ac_access_req = '1' then
if MEM_IF_MEMTYPE = "DDR3" then
state <= s_zq_cal_short;
else
state <= s_access_act;
end if;
else
state <= s_idle;
end if;
end if;
when s_zq_cal_short => -- DDR3 only
if finished_state = '1' then
state <= s_access_act;
end if;
when s_access_act =>
if finished_state = '1' then
state <= s_access;
end if;
when s_access =>
if ac_access_req = '0' then
state <= s_access_precharge;
end if;
when s_access_precharge =>
-- ensure precharge all timer has elapsed.
if finished_state = '1' then
state <= s_idle;
end if;
when s_prog_user_mrs =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_refresh =>
if finished_state = '1' then
state <= s_refresh_done;
end if;
when s_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_refresh;
else
state <= s_idle;
end if;
end if;
when others =>
state <= s_reset;
end case;
if cal_complete = '1' then
state <= s_idle;
if GENERATE_ADDITIONAL_DBG_RTL = 1 and cal_success = '0' then
state <= s_non_operational; -- if calibration failed and debug enabled then toggle pins in pre-defined pattern
end if;
end if;
-- if recalibrating then put admin in reset state to
-- avoid issuing refresh commands when not needed
if ctl_recalibrate_req = '1' then
state <= s_reset;
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate initialisation complete
-- --------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
mem_init_complete <= '0';
elsif rising_edge(clk) then
if to_integer(unsigned(per_cs_init_seen)) = 2**MEM_IF_NUM_RANKS - 1 then
mem_init_complete <= '1';
else
mem_init_complete <= '0';
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate addr/cmd.
-- --------------------------------------------------
process(rst_n, clk)
variable v_mr_overload : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
-- required for non_operational state only
variable v_nop_ac_0 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
variable v_nop_ac_1 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
ac_state <= s_0;
stage_counter <= 0;
stage_counter_zero <= '1';
finished_state <= '0';
seq_ac_sel <= '1';
refresh_done <= '0';
per_cs_init_seen <= (others => '0');
addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
elsif rising_edge(clk) then
finished_state <= '0';
refresh_done <= '0';
-- address / command path control
-- if seq_ac_sel = 1 then sequencer has control of a/c
-- if seq_ac_sel = 0 then memory controller has control of a/c
seq_ac_sel <= '1';
if cal_complete = '1' then
if cal_success = '1' or
GENERATE_ADDITIONAL_DBG_RTL = 0 then -- hand over interface if cal successful or no debug enabled
seq_ac_sel <= '0';
end if;
end if;
-- if recalibration request then take control of a/c path
if ctl_recalibrate_req = '1' then
seq_ac_sel <= '1';
end if;
if state = s_reset then
addr_cmd <= reset(c_seq_addr_cmd_config);
stage_counter <= 0;
elsif state /= s_run_init_seq and
state /= s_non_operational then
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
end if;
if (stage_counter = 1 or stage_counter = 0) then
stage_counter_zero <= '1';
else
stage_counter_zero <= '0';
end if;
if stage_counter_zero /= '1' and state /= s_reset then
stage_counter <= stage_counter -1;
else
stage_counter_zero <= '0';
case state is
when s_run_init_seq =>
per_cs_init_seen <= (others => '0'); -- per cs test
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
case ac_state is
-- JEDEC (JESD79-2E) stage c
when s_0 to s_9 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10)+1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
-- JEDEC (JESD79-2E) stage d
when s_10 =>
ac_state <= s_11;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_11 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then -- DDR3 specific initialisation sequence
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= TINIT_RST + 1;
addr_cmd <= reset(c_seq_addr_cmd_config);
when s_1 to s_10 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10) + 1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
when s_11 =>
ac_state <= s_12;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, addr_cmd);
when s_12 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of initialisation sequence
when s_program_cal_mrs =>
if MEM_IF_MEMTYPE = "DDR2" then -- DDR2 style mode register settings
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage d
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage e
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage f
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage g
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
v_mr_overload(9 downto 7) := "000"; -- required in JESD79-2E (but not in JESD79-2B)
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage h
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage i
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
-- JEDEC (JESD79-2E) stage j
when s_7 =>
ac_state <= s_8;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage j - second refresh
when s_8 =>
ac_state <= s_9;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage k
when s_9 =>
ac_state <= s_10;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
v_mr_overload(8) := '0'; -- required in JESD79-2E
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - wait 200 cycles
when s_10 =>
ac_state <= s_11;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage l - OCD default
when s_11 =>
ac_state <= s_12;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "111"; -- OCD calibration default (i.e. OCD unused)
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - OCD cal exit
when s_12 =>
ac_state <= s_13;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "000"; -- OCD calibration exit
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
per_cs_init_seen(current_cs) <= '1';
-- JEDEC (JESD79-2E) stage m - cal finished
when s_13 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR" then -- DDR style mode register setting following JEDEC (JESD79E)
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_5 =>
ac_state <= s_6;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_7 =>
ac_state <= s_8;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_8 =>
ac_state <= s_9;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
per_cs_init_seen(current_cs) <= '1';
when s_9 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trp_in_clks;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- Override for DLL enable
v_mr_overload(12) := '0'; -- output buffer enable.
v_mr_overload(7) := '0'; -- Disable Write levelling
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 0);
v_mr_overload(1 downto 0) := "01"; -- override to on the fly burst length choice
v_mr_overload(7) := '0'; -- test mode not enabled
v_mr_overload(8) := '1'; -- DLL reset
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_5 =>
ac_state <= s_6;
stage_counter <= c_zq_init_duration_clks;
addr_cmd <= ZQCL(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
per_cs_init_seen(current_cs) <= '1';
when s_6 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of s_program_cal_mrs case
when s_prog_user_mrs =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
if MEM_IF_MEMTYPE = "DDR" then -- for DDR memory skip MR2/3 because not present
ac_state <= s_4;
else -- for DDR2/DDR3 all MRs programmed
ac_state <= s_2;
end if;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if to_integer(unsigned(int_mr3)) /= 0 then
report admin_report_prefix & " mode register 3 is expected to have a value of 0 but has a value of : " &
integer'image(to_integer(unsigned(int_mr3))) severity warning;
end if;
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
int_mr1(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if (MEM_IF_DQSN_EN = 0) and (int_mr1(10) = '0') and (MEM_IF_MEMTYPE = "DDR2") then
report admin_report_prefix & "mode register and generic conflict:" & LF &
"* generic MEM_IF_DQSN_EN is set to 'disable' DQSN" & LF &
"* user mode register MEM_IF_MR1 bit 10 is set to 'enable' DQSN" severity warning;
end if;
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_6 =>
ac_state <= s_7;
stage_counter <= 1;
when s_7 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- end of s_prog_user_mr case
when s_access_precharge =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 10;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh | s_refresh =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= 1;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**MEM_IF_NUM_RANKS - 1); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh_done | s_refresh_done =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trfc_min_in_clks;
refresh_done <= '1'; -- ensure trfc not violated
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_zq_cal_short =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tzqcs;
addr_cmd <= ZQCS(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- all ranks
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_access_act =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trrd_min_in_clks;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trcd_min_in_clks;
addr_cmd <= activate(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_ROW, -- row address
2**current_cs); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- counter to delay transition from s_idle to s_refresh - this is to ensure a refresh command is not sent
-- just as we enter operational state (could cause a trfc violation)
when s_dummy_wait =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_max_wait_value;
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_reset =>
stage_counter <= 1;
-- default some s_non_operational signals
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
when s_non_operational => -- if failed then output a recognised pattern to the memory (Only executes if GENERATE_ADDITIONAL_DBG_RTL set)
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
if NON_OP_EVAL_MD = "PIN_FINDER" then -- toggle pins in turn for 200 memory clk cycles
stage_counter <= 200/(DWIDTH_RATIO/2); -- 200 mem_clk cycles
case nop_toggle_signal is
when addr =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_ADDR_WIDTH-1 then
nop_toggle_signal <= ba;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when ba =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_BANKADDR_WIDTH-1 then
nop_toggle_signal <= cas_n;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when cas_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, cas_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= ras_n;
end if;
when ras_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ras_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= we_n;
end if;
when we_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, we_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= addr;
end if;
when others =>
report admin_report_prefix & " an attempt to toggle a non addr/cmd pin detected" severity failure;
end case;
elsif NON_OP_EVAL_MD = "SI_EVALUATOR" then -- toggle all addr/cmd pins at fmax
stage_counter <= 0; -- every mem_clk cycle
stage_counter_zero <= '1';
v_nop_ac_0 := mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ba, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, we_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ras_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, cas_n, nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, addr_cmd, addr, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ba, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, we_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ras_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, cas_n, not nop_toggle_value);
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if i mod 2 = 0 then
addr_cmd(i) <= v_nop_ac_0(i);
else
addr_cmd(i) <= v_nop_ac_1(i);
end if;
end loop;
if DWIDTH_RATIO = 2 then
nop_toggle_value <= not nop_toggle_value;
end if;
else
report admin_report_prefix & "unknown non-operational evaluation mode " & NON_OP_EVAL_MD severity failure;
end if;
when others =>
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
stage_counter <= 1;
ac_state <= s_0;
end case;
end if;
end if;
end process;
-- -------------------------------------------------------------------
-- output packing of mode register settings and enabling of ODT
-- -------------------------------------------------------------------
process (int_mr0, int_mr1, int_mr2, int_mr3, mem_init_complete)
begin
admin_regs_status_rec.mr0 <= int_mr0;
admin_regs_status_rec.mr1 <= int_mr1;
admin_regs_status_rec.mr2 <= int_mr2;
admin_regs_status_rec.mr3 <= int_mr3;
admin_regs_status_rec.init_done <= mem_init_complete;
enable_odt <= int_mr1(2) or int_mr1(6); -- if ODT enabled in MR settings (i.e. MR1 bits 2 or 6 /= 0)
end process;
-- --------------------------------------------------------------------------------
-- generation of handshake signals with ctrl, dgrb and dgwb blocks (this includes
-- command ack, command done for ctrl and access grant for dgrb/dgwb)
-- --------------------------------------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
elsif rising_edge(clk) then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
admin_ctrl.command_ack <= command_started;
admin_ctrl.command_done <= command_done;
if state = s_access then
ac_access_gnt <= '1';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : inferred ram for the non-levelling AFI PHY sequencer
-- The inferred ram is used in the iram block to store
-- debug information about the sequencer. It is variable in
-- size based on the IRAM_AWIDTH generic and is of size
-- 32 * (2 ** IRAM_ADDR_WIDTH) bits
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_iram_ram IS
generic (
IRAM_AWIDTH : natural
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- ram ports
addr : in unsigned(IRAM_AWIDTH-1 downto 0);
wdata : in std_logic_vector(31 downto 0);
write : in std_logic;
rdata : out std_logic_vector(31 downto 0)
);
end entity;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_iram_ram is
-- infer ram
constant c_max_ram_address : natural := 2**IRAM_AWIDTH -1;
-- registered ram signals
signal addr_r : unsigned(IRAM_AWIDTH-1 downto 0);
signal wdata_r : std_logic_vector(31 downto 0);
signal write_r : std_logic;
signal rdata_r : std_logic_vector(31 downto 0);
-- ram storage array
type t_iram is array (0 to c_max_ram_address) of std_logic_vector(31 downto 0);
signal iram_ram : t_iram;
attribute altera_attribute : string;
attribute altera_attribute of iram_ram : signal is "-name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ""OFF""";
begin -- architecture struct
-- inferred ram instance - standard ram logic
process (clk, rst_n)
begin
if rst_n = '0' then
rdata_r <= (others => '0');
elsif rising_edge(clk) then
if write_r = '1' then
iram_ram(to_integer(addr_r)) <= wdata_r;
end if;
rdata_r <= iram_ram(to_integer(addr_r));
end if;
end process;
-- register i/o for speed
process (clk, rst_n)
begin
if rst_n = '0' then
rdata <= (others => '0');
write_r <= '0';
addr_r <= (others => '0');
wdata_r <= (others => '0');
elsif rising_edge(clk) then
rdata <= rdata_r;
write_r <= write;
addr_r <= addr;
wdata_r <= wdata;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram block for the non-levelling AFI PHY sequencer
-- This block is an optional storage of debug information for
-- the sequencer. In the current form the iram stores header
-- information about the arrangement of the sequencer and pass/
-- fail information for per-delay/phase/pin sweeps for the
-- read resynch phase calibration stage. Support for debug of
-- additional commands can be added at a later date
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The altmemphy iram ram (alt_mem_phy_iram_ram) is an inferred ram memory to implement the debug
-- iram ram block
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_iram_ram;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_iram is
generic (
-- physical interface width definitions
MEM_IF_MEMTYPE : string;
FAMILYGROUP_ID : natural;
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
IRAM_AWIDTH : natural;
REFRESH_COUNT_INIT : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural;
CAPABILITIES : natural;
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- read interface from mmi block:
mmi_iram : in t_iram_ctrl;
mmi_iram_enable_writes : in std_logic;
--iram status signal (includes read data from iram)
iram_status : out t_iram_stat;
iram_push_done : out std_logic;
-- from ctrl block
ctrl_iram : in t_ctrl_command;
-- from dgrb block
dgrb_iram : in t_iram_push;
-- from admin block
admin_regs_status_rec : in t_admin_stat;
-- current write position in the iram
ctrl_idib_top : in natural range 0 to 2 ** IRAM_AWIDTH - 1;
ctrl_iram_push : in t_ctrl_iram;
-- the following signals are unused and reserved for future use
dgwb_iram : in t_iram_push
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg.all;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_iram is
-- -------------------------------------------
-- IHI fields
-- -------------------------------------------
-- memory type , Quartus Build No., Quartus release, sequencer architecture version :
signal memtype : std_logic_vector(7 downto 0);
signal ihi_self_description : std_logic_vector(31 downto 0);
signal ihi_self_description_extra : std_logic_vector(31 downto 0);
-- for iram address generation:
signal curr_iram_offset : natural range 0 to 2 ** IRAM_AWIDTH - 1;
-- set read latency for iram_rdata_valid signal control:
constant c_iram_rlat : natural := 3; -- iram read latency (increment if read pipelining added
-- for rdata valid generation:
signal read_valid_ctr : natural range 0 to c_iram_rlat;
signal iram_addr_r : unsigned(IRAM_AWIDTH downto 0);
constant c_ihi_phys_if_desc : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(MEM_IF_NUM_RANKS,8) & to_unsigned(MEM_IF_DM_WIDTH,8) & to_unsigned(MEM_IF_DQS_WIDTH,8) & to_unsigned(MEM_IF_DWIDTH,8));
constant c_ihi_timing_info : std_logic_vector(31 downto 0) := X"DEADDEAD";
constant c_ihi_ctrl_ss_word2 : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(PRESET_RLAT,16) & X"0000");
-- IDIB header codes
constant c_idib_header_code0 : std_logic_vector(7 downto 0) := X"4A";
constant c_idib_footer_code : std_logic_vector(7 downto 0) := X"5A";
-- encoded Quartus version
-- constant c_quartus_version : natural := 0; -- Quartus 7.2
-- constant c_quartus_version : natural := 1; -- Quartus 8.0
--constant c_quartus_version : natural := 2; -- Quartus 8.1
--constant c_quartus_version : natural := 3; -- Quartus 9.0
--constant c_quartus_version : natural := 4; -- Quartus 9.0sp2
--constant c_quartus_version : natural := 5; -- Quartus 9.1
--constant c_quartus_version : natural := 6; -- Quartus 9.1sp1?
--constant c_quartus_version : natural := 7; -- Quartus 9.1sp2?
constant c_quartus_version : natural := 8; -- Quartus 10.0
-- constant c_quartus_version : natural := 114; -- reserved
-- allow for different variants for debug i/f
constant c_dbg_if_version : natural := 2;
-- sequencer type 1 for levelling, 2 for non-levelling
constant c_sequencer_type : natural := 2;
-- a prefix for all report signals to identify phy and sequencer block
--
constant iram_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (iram) : ";
-- -------------------------------------------
-- signal and type declarations
-- -------------------------------------------
type t_iram_state is ( s_reset, -- system reset
s_pre_init_ram, -- identify pre-initialisation
s_init_ram, -- zero all locations
s_idle, -- default state
s_word_access_ram, -- mmi access to the iram (post-calibration)
s_word_fetch_ram_rdata, -- sample read data from RAM
s_word_fetch_ram_rdata_r,-- register the sampling of data from RAM (to improve timing)
s_word_complete, -- finalise iram ram write
s_idib_header_write, -- when starting a command
s_idib_header_inc_addr, -- address increment
s_idib_footer_write, -- unique footer to indicate end of data
s_cal_data_read, -- read RAM location (read occurs continuously from idle state)
s_cal_data_read_r,
s_cal_data_modify, -- modify RAM location (read occurs continuously)
s_cal_data_write, -- write modified value back to RAM
s_ihi_header_word0_wr, -- from 0 to 6 writing iram header info
s_ihi_header_word1_wr,
s_ihi_header_word2_wr,
s_ihi_header_word3_wr,
s_ihi_header_word4_wr,
s_ihi_header_word5_wr,
s_ihi_header_word6_wr,
s_ihi_header_word7_wr-- end writing iram header info
);
signal state : t_iram_state;
signal contested_access : std_logic;
signal idib_header_count : std_logic_vector(7 downto 0);
-- register a new cmd request
signal new_cmd : std_logic;
signal cmd_processed : std_logic;
-- signals to control dgrb writes
signal iram_modified_data : std_logic_vector(31 downto 0); -- scratchpad memory for read-modify-write
-- -------------------------------------------
-- physical ram connections
-- -------------------------------------------
-- Note that the iram_addr here is created IRAM_AWIDTH downto 0, and not
-- IRAM_AWIDTH-1 downto 0. This means that the MSB is outside the addressable
-- area of the RAM. The purpose of this is that this shall be our memory
-- overflow bit. It shall be directly connected to the iram_out_of_memory flag
-- 32-bit interface port (read and write)
signal iram_addr : unsigned(IRAM_AWIDTH downto 0);
signal iram_wdata : std_logic_vector(31 downto 0);
signal iram_rdata : std_logic_vector(31 downto 0);
signal iram_write : std_logic;
-- signal generated external to the iram to say when read data is valid
signal iram_rdata_valid : std_logic;
-- The FSM owns local storage that is loaded with the wdata/addr from the
-- requesting sub-block, which is then fed to the iram's wdata/addr in turn
-- until all data has gone across
signal fsm_read : std_logic;
-- -------------------------------------------
-- multiplexed push data
-- -------------------------------------------
signal iram_done : std_logic; -- unused
signal iram_pushdata : std_logic_vector(31 downto 0);
signal pending_push : std_logic; -- push data to RAM
signal iram_wordnum : natural range 0 to 511;
signal iram_bitnum : natural range 0 to 31;
begin -- architecture struct
-- -------------------------------------------
-- iram ram instantiation
-- -------------------------------------------
-- Note that the IRAM_AWIDTH is the physical number of address bits that the RAM has.
-- However, for out of range access detection purposes, an additional bit is added to
-- the various address signals. The iRAM does not register any of its inputs as the addr,
-- wdata etc are registered directly before being driven to it.
-- The dgrb accesses are of format read-modify-write to a single bit of a 32-bit word, the
-- mmi reads and header writes are in 32-bit words
--
ram : entity ddr_ctrl_ip_phy_alt_mem_phy_iram_ram
generic map (
IRAM_AWIDTH => IRAM_AWIDTH
)
port map (
clk => clk,
rst_n => rst_n,
addr => iram_addr(IRAM_AWIDTH-1 downto 0),
wdata => iram_wdata,
write => iram_write,
rdata => iram_rdata
);
-- -------------------------------------------
-- IHI fields
-- asynchronously
-- -------------------------------------------
-- this field identifies the type of memory
memtype <= X"03" when (MEM_IF_MEMTYPE = "DDR3") else
X"02" when (MEM_IF_MEMTYPE = "DDR2") else
X"01" when (MEM_IF_MEMTYPE = "DDR") else
X"10" when (MEM_IF_MEMTYPE = "QDRII") else
X"00" ;
-- this field indentifies the gross level description of the sequencer
ihi_self_description <= memtype
& std_logic_vector(to_unsigned(IP_BUILDNUM,8))
& std_logic_vector(to_unsigned(c_quartus_version,8))
& std_logic_vector(to_unsigned(c_dbg_if_version,8));
-- some extra information for the debug gui - sequencer type and familygroup
ihi_self_description_extra <= std_logic_vector(to_unsigned(FAMILYGROUP_ID,4))
& std_logic_vector(to_unsigned(c_sequencer_type,4))
& x"000000";
-- -------------------------------------------
-- check for contested memory accesses
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
contested_access <= '0';
elsif rising_edge(clk) then
contested_access <= '0';
if mmi_iram.read = '1' and pending_push = '1' then
report iram_report_prefix & "contested memory accesses to the iram" severity failure;
contested_access <= '1';
end if;
-- sanity checks
if mmi_iram.write = '1' then
report iram_report_prefix & "mmi writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
if dgwb_iram.iram_write = '1' then
report iram_report_prefix & "dgwb writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end process;
-- -------------------------------------------
-- mux push data and associated signals
-- note: single bit taken for iram_pushdata because 1-bit read-modify-write to
-- a 32-bit word in the ram. This interface style is maintained for future
-- scalability / wider application of the iram block.
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
iram_done <= '0';
iram_pushdata <= (others => '0');
pending_push <= '0';
iram_wordnum <= 0;
iram_bitnum <= 0;
elsif rising_edge(clk) then
case curr_active_block(ctrl_iram.command) is
when dgrb =>
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
when others => -- default dgrb
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
end case;
end if;
end process;
-- -------------------------------------------
-- generate write signal for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_write <= '0';
elsif rising_edge(clk) then
case state is
when s_idle =>
iram_write <= '0';
when s_pre_init_ram |
s_init_ram =>
iram_write <= '1';
when s_ihi_header_word0_wr |
s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_write <= '1';
when s_idib_header_write =>
iram_write <= '1';
when s_idib_footer_write =>
iram_write <= '1';
when s_cal_data_write =>
iram_write <= '1';
when others =>
iram_write <= '0'; -- default
end case;
end if;
end process;
-- -------------------------------------------
-- generate wdata for the ram
-- -------------------------------------------
process(clk, rst_n)
variable v_current_cs : std_logic_vector(3 downto 0);
variable v_mtp_alignment : std_logic_vector(0 downto 0);
variable v_single_bit : std_logic;
begin
if rst_n = '0' then
iram_wdata <= (others => '0');
elsif rising_edge(clk) then
case state is
when s_pre_init_ram |
s_init_ram =>
iram_wdata <= (others => '0');
when s_ihi_header_word0_wr =>
iram_wdata <= ihi_self_description;
when s_ihi_header_word1_wr =>
iram_wdata <= c_ihi_phys_if_desc;
when s_ihi_header_word2_wr =>
iram_wdata <= c_ihi_timing_info;
when s_ihi_header_word3_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr0'range) <= admin_regs_status_rec.mr0;
iram_wdata(admin_regs_status_rec.mr1'high + 16 downto 16) <= admin_regs_status_rec.mr1;
when s_ihi_header_word4_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr2'range) <= admin_regs_status_rec.mr2;
iram_wdata(admin_regs_status_rec.mr3'high + 16 downto 16) <= admin_regs_status_rec.mr3;
when s_ihi_header_word5_wr =>
iram_wdata <= c_ihi_ctrl_ss_word2;
when s_ihi_header_word6_wr =>
iram_wdata <= std_logic_vector(to_unsigned(IRAM_AWIDTH,32)); -- tbd write the occupancy at end of cal
when s_ihi_header_word7_wr =>
iram_wdata <= ihi_self_description_extra;
when s_idib_header_write =>
-- encode command_op for current operation
v_current_cs := std_logic_vector(to_unsigned(ctrl_iram.command_op.current_cs, 4));
v_mtp_alignment := std_logic_vector(to_unsigned(ctrl_iram.command_op.mtp_almt, 1));
v_single_bit := ctrl_iram.command_op.single_bit;
iram_wdata <= encode_current_stage(ctrl_iram.command) & -- which command being executed (currently this should only be cmd_rrp_sweep (8 bits)
v_current_cs & -- which chip select being processed (4 bits)
v_mtp_alignment & -- currently used MTP alignment (1 bit)
v_single_bit & -- is single bit calibration selected (1 bit) - used during MTP alignment
"00" & -- RFU
idib_header_count & -- unique ID to how many headers have been written (8 bits)
c_idib_header_code0; -- unique ID for headers (8 bits)
when s_idib_footer_write =>
iram_wdata <= c_idib_footer_code & c_idib_footer_code & c_idib_footer_code & c_idib_footer_code;
when s_cal_data_modify =>
-- default don't overwrite
iram_modified_data <= iram_rdata;
-- update iram data based on packing and write modes
if ctrl_iram_push.packing_mode = dq_bitwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0);
when or_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) or iram_rdata(0);
when and_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) and iram_rdata(0);
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
elsif ctrl_iram_push.packing_mode = dq_wordwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data <= iram_pushdata;
when or_into_ram =>
iram_modified_data <= iram_pushdata or iram_rdata;
when and_into_ram =>
iram_modified_data <= iram_pushdata and iram_rdata;
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
else
report iram_report_prefix & "unidentified packing mode of " & t_iram_packing_mode'image(ctrl_iram_push.packing_mode) &
" specified when generating iram write data" severity failure;
end if;
when s_cal_data_write =>
iram_wdata <= iram_modified_data;
when others =>
iram_wdata <= (others => '0');
end case;
end if;
end process;
-- -------------------------------------------
-- generate addr for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_addr <= (others => '0');
curr_iram_offset <= 0;
elsif rising_edge(clk) then
case (state) is
when s_idle =>
if mmi_iram.read = '1' then -- pre-set mmi read location address
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
else -- default get next push data location from iram
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1);
end if;
when s_word_access_ram =>
-- calculate the address
if mmi_iram.read = '1' then -- mmi access
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
end if;
when s_ihi_header_word0_wr =>
iram_addr <= (others => '0');
-- increment address for IHI word writes :
when s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_addr <= iram_addr + 1;
when s_idib_header_write =>
iram_addr <= '0' & to_unsigned(ctrl_idib_top, IRAM_AWIDTH); -- Always write header at idib_top location
when s_idib_footer_write =>
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1); -- active block communicates where to put the footer with done signal
when s_idib_header_inc_addr =>
iram_addr <= iram_addr + 1;
curr_iram_offset <= to_integer('0' & iram_addr) + 1;
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
iram_addr <= (others => '0'); -- this prevents erroneous out-of-mem flag after initialisation
else
iram_addr <= iram_addr + 1;
end if;
when others =>
iram_addr <= iram_addr;
end case;
end if;
end process;
-- -------------------------------------------
-- generate new cmd signal to register the command_req signal
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
new_cmd <= '0';
elsif rising_edge(clk) then
if ctrl_iram.command_req = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep | -- only prompt new_cmd for commands we wish to write headers for
cmd_rrp_seek |
cmd_read_mtp |
cmd_write_ihi =>
new_cmd <= '1';
when others =>
new_cmd <= '0';
end case;
end if;
if cmd_processed = '1' then
new_cmd <= '0';
end if;
end if;
end process;
-- -------------------------------------------
-- generate read valid signal which takes account of pipelining of reads
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_rdata_valid <= '0';
read_valid_ctr <= 0;
iram_addr_r <= (others => '0');
elsif rising_edge(clk) then
if read_valid_ctr < c_iram_rlat then
iram_rdata_valid <= '0';
read_valid_ctr <= read_valid_ctr + 1;
else
iram_rdata_valid <= '1';
end if;
if to_integer(iram_addr) /= to_integer(iram_addr_r) or
iram_write = '1' then
read_valid_ctr <= 0;
iram_rdata_valid <= '0';
end if;
-- register iram address
iram_addr_r <= iram_addr;
end if;
end process;
-- -------------------------------------------
-- state machine
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
state <= s_reset;
cmd_processed <= '0';
elsif rising_edge(clk) then
cmd_processed <= '0';
case state is
when s_reset =>
state <= s_pre_init_ram;
when s_pre_init_ram =>
state <= s_init_ram;
-- remain in the init_ram state until all the ram locations have been zero'ed
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
state <= s_idle;
end if;
-- default state after reset
when s_idle =>
if pending_push = '1' then
state <= s_cal_data_read;
elsif iram_done = '1' then
state <= s_idib_footer_write;
elsif new_cmd = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep |
cmd_rrp_seek |
cmd_read_mtp => state <= s_idib_header_write;
when cmd_write_ihi => state <= s_ihi_header_word0_wr;
when others => state <= state;
end case;
cmd_processed <= '1';
elsif mmi_iram.read = '1' then
state <= s_word_access_ram;
end if;
-- mmi read accesses
when s_word_access_ram => state <= s_word_fetch_ram_rdata;
when s_word_fetch_ram_rdata => state <= s_word_fetch_ram_rdata_r;
when s_word_fetch_ram_rdata_r => if iram_rdata_valid = '1' then
state <= s_word_complete;
end if;
when s_word_complete => if iram_rdata_valid = '1' then -- return to idle when iram_rdata stable
state <= s_idle;
end if;
-- header write (currently only for cmp_rrp stage)
when s_idib_header_write => state <= s_idib_header_inc_addr;
when s_idib_header_inc_addr => state <= s_idle; -- return to idle to wait for push
when s_idib_footer_write => state <= s_word_complete;
-- push data accesses (only used by the dgrb block at present)
when s_cal_data_read => state <= s_cal_data_read_r;
when s_cal_data_read_r => if iram_rdata_valid = '1' then
state <= s_cal_data_modify;
end if;
when s_cal_data_modify => state <= s_cal_data_write;
when s_cal_data_write => state <= s_word_complete;
-- IHI Header write accesses
when s_ihi_header_word0_wr => state <= s_ihi_header_word1_wr;
when s_ihi_header_word1_wr => state <= s_ihi_header_word2_wr;
when s_ihi_header_word2_wr => state <= s_ihi_header_word3_wr;
when s_ihi_header_word3_wr => state <= s_ihi_header_word4_wr;
when s_ihi_header_word4_wr => state <= s_ihi_header_word5_wr;
when s_ihi_header_word5_wr => state <= s_ihi_header_word6_wr;
when s_ihi_header_word6_wr => state <= s_ihi_header_word7_wr;
when s_ihi_header_word7_wr => state <= s_idle;
when others => state <= state;
end case;
end if;
end process;
-- -------------------------------------------
-- drive read data and responses back.
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_status <= defaults;
iram_push_done <= '0';
idib_header_count <= (others => '0');
fsm_read <= '0';
elsif rising_edge(clk) then
-- defaults
iram_status <= defaults;
iram_status.done <= '0';
iram_status.rdata <= (others => '0');
iram_push_done <= '0';
if state = s_init_ram then
iram_status.out_of_mem <= '0';
else
iram_status.out_of_mem <= iram_addr(IRAM_AWIDTH);
end if;
-- register read flag for 32 bit accesses
if state = s_idle then
fsm_read <= mmi_iram.read;
end if;
if state = s_word_complete then
iram_status.done <= '1';
if fsm_read = '1' then
iram_status.rdata <= iram_rdata;
else
iram_status.rdata <= (others => '0');
end if;
end if;
-- if another access is ever presented while the FSM is busy, set the contested flag
if contested_access = '1' then
iram_status.contested_access <= '1';
end if;
-- set (and keep set) the iram_init_done output once initialisation of the RAM is complete
if (state /= s_init_ram) and (state /= s_pre_init_ram) and (state /= s_reset) then
iram_status.init_done <= '1';
end if;
if state = s_ihi_header_word7_wr then
iram_push_done <= '1';
end if;
-- if completing push or footer write then acknowledge
if state = s_cal_data_modify or state = s_idib_footer_write then
iram_push_done <= '1';
end if;
-- increment IDIB header count each time a header is written
if state = s_idib_header_write then
idib_header_count <= std_logic_vector(unsigned(idib_header_count) + to_unsigned(1,idib_header_count'high +1));
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (read bias) [dgrb] block for the non-levelling
-- AFI PHY sequencer
-- This block handles all calibration commands which require
-- memory read operations.
--
-- These include:
-- Resync phase calibration - sweep of phases, calculation of
-- result and optional storage to iram
-- Postamble calibration - clock cycle calibration of the postamble
-- enable signal
-- Read data valid signal alignment
-- Calculation of advertised read and write latencies
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_dgrb is
generic (
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQS_CAPTURE : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
CLOCK_INDEX_WIDTH : natural;
DWIDTH_RATIO : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural; -- number of PLL phase steps per PHY clock cycle
SIM_TIME_REDUCTIONS : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
PRESET_CODVW_PHASE : natural;
PRESET_CODVW_SIZE : natural;
-- base column address to which calibration data is written
-- memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data
MEM_IF_CAL_BANK : natural; -- bank to which calibration data is written
MEM_IF_CAL_BASE_COL : natural;
EN_OCT : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- control interface
dgrb_ctrl : out t_ctrl_stat;
ctrl_dgrb : in t_ctrl_command;
parameterisation_rec : in t_algm_paramaterisation;
-- PLL reconfig interface
phs_shft_busy : in std_logic;
seq_pll_inc_dec_n : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
seq_pll_start_reconfig : out std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic / aka measure clock
-- iram 'push' interface
dgrb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- addr/cmd output for write commands
dgrb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- admin block req/gnt interface
dgrb_ac_access_req : out std_logic;
dgrb_ac_access_gnt : in std_logic;
-- RDV latency controls
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
-- POA latency controls
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
-- read datapath interface
rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0);
rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- advertised write latency
wd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- OCT control
seq_oct_value : out std_logic;
dgrb_wdp_ovride : out std_logic;
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- calibration byte lane select (reserved for future use - RFU)
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1);
-- signal to identify if a/c nt setting is correct (set after wr_lat calculation)
-- NOTE: labelled nt for future scalability to quarter rate interfaces
dgrb_ctrl_ac_nt_good : out std_logic;
-- status signals on calibrated cdvw
dgrb_mmi : out t_dgrb_mmi
);
end entity;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_dgrb is
-- ------------------------------------------------------------------
-- constant declarations
-- ------------------------------------------------------------------
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- command/result length
constant c_command_result_len : natural := 8;
-- burst characteristics and latency characteristics
constant c_max_read_lat : natural := 2**rd_lat'length - 1; -- maximum read latency in phy clock-cycles
-- training pattern characteristics
constant c_cal_mtp_len : natural := 16;
constant c_cal_mtp : std_logic_vector(c_cal_mtp_len - 1 downto 0) := x"30F5";
constant c_cal_mtp_t : natural := c_cal_mtp_len / DWIDTH_RATIO; -- number of phy-clk cycles required to read BTP
-- read/write latency defaults
constant c_default_rd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_rd_lat, ADV_LAT_WIDTH));
constant c_default_wd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_wr_lat, ADV_LAT_WIDTH));
-- tracking reporting parameters
constant c_max_rsc_drift_in_phases : natural := 127; -- this must be a value of < 2^10 - 1 because of the range of signal codvw_trk_shift
-- Returns '1' when boolean b is True; '0' otherwise.
function active_high(b : in boolean) return std_logic is
variable r : std_logic;
begin
if b then
r := '1';
else
r := '0';
end if;
return r;
end function;
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgrb_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (dgrb) : ";
-- Return the number of clock periods the resync clock should sweep.
--
-- On half-rate systems and in DQS-capture based systems a 720
-- to guarantee the resync window can be properly observed.
function rsc_sweep_clk_periods return natural is
variable v_num_periods : natural;
begin
if DWIDTH_RATIO = 2 then
if MEM_IF_DQS_CAPTURE = 1 then -- families which use DQS capture require a 720 degree sweep for FR to show a window
v_num_periods := 2;
else
v_num_periods := 1;
end if;
elsif DWIDTH_RATIO = 4 then
v_num_periods := 2;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO." severity failure;
end if;
return v_num_periods;
end function;
-- window for PLL sweep
constant c_max_phase_shifts : natural := rsc_sweep_clk_periods*PLL_STEPS_PER_CYCLE;
constant c_pll_phs_inc : std_logic := '1';
constant c_pll_phs_dec : std_logic := not c_pll_phs_inc;
-- ------------------------------------------------------------------
-- type declarations
-- ------------------------------------------------------------------
-- dgrb main state machine
type t_dgrb_state is (
-- idle state
s_idle,
-- request access to memory address/command bus from the admin block
s_wait_admin,
-- relinquish address/command bus access
s_release_admin,
-- wind back resync phase to a 'zero' point
s_reset_cdvw,
-- perform resync phase sweep (used for MTP alignment checking and actual RRP sweep)
s_test_phases,
-- processing to when checking MTP alignment
s_read_mtp,
-- processing for RRP (read resync phase) sweep
s_seek_cdvw,
-- clock cycle alignment of read data valid signal
s_rdata_valid_align,
-- calculate advertised read latency
s_adv_rd_lat_setup,
s_adv_rd_lat,
-- calculate advertised write latency
s_adv_wd_lat,
-- postamble clock cycle calibration
s_poa_cal,
-- tracking - setup and periodic update
s_track
);
-- dgrb slave state machine for addr/cmd signals
type t_ac_state is (
-- idle state
s_ac_idle,
-- wait X cycles (issuing NOP command) to flush address/command and DQ buses
s_ac_relax,
-- read MTP pattern
s_ac_read_mtp,
-- read pattern for read data valid alignment
s_ac_read_rdv,
-- read pattern for POA calibration
s_ac_read_poa_mtp,
-- read pattern to calculate advertised write latency
s_ac_read_wd_lat
);
-- dgrb slave state machine for read resync phase calibration
type t_resync_state is (
-- idle state
s_rsc_idle,
-- shift resync phase by one
s_rsc_next_phase,
-- start test sequence for current pin and current phase
s_rsc_test_phase,
-- flush the read datapath
s_rsc_wait_for_idle_dimm, -- wait until no longer driving
s_rsc_flush_datapath, -- flush a/c path
-- sample DQ data to test phase
s_rsc_test_dq,
-- reset rsc phase to a zero position
s_rsc_reset_cdvw,
s_rsc_rewind_phase,
-- calculate the centre of resync window
s_rsc_cdvw_calc,
s_rsc_cdvw_wait, -- wait for calc result
-- set rsc clock phase to centre of data valid window
s_rsc_seek_cdvw,
-- wait until all results written to iram
s_rsc_wait_iram -- only entered if GENERATE_ADDITIONAL_DBG_RTL = 1
);
-- record definitions for window processing
type t_win_processing_status is ( calculating,
valid_result,
no_invalid_phases,
multiple_equal_windows,
no_valid_phases
);
type t_window_processing is record
working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
first_good_edge : natural range 0 to c_max_phase_shifts - 1; -- pointer to first detected good edge
current_window_start : natural range 0 to c_max_phase_shifts - 1;
current_window_size : natural range 0 to c_max_phase_shifts - 1;
current_window_centre : natural range 0 to c_max_phase_shifts - 1;
largest_window_start : natural range 0 to c_max_phase_shifts - 1;
largest_window_size : natural range 0 to c_max_phase_shifts - 1;
largest_window_centre : natural range 0 to c_max_phase_shifts - 1;
current_bit : natural range 0 to c_max_phase_shifts - 1;
window_centre_update : std_logic;
last_bit_value : std_logic;
valid_phase_seen : boolean;
invalid_phase_seen : boolean;
first_cycle : boolean;
multiple_eq_windows : boolean;
found_a_good_edge : boolean;
status : t_win_processing_status;
windows_seen : natural range 0 to c_max_phase_shifts/2 - 1;
end record;
-- ------------------------------------------------------------------
-- function and procedure definitions
-- ------------------------------------------------------------------
-- Returns a string representation of a std_logic_vector.
-- Not synthesizable.
function str(v: std_logic_vector) return string is
variable str_value : string (1 to v'length);
variable str_len : integer;
variable c : character;
begin
str_len := 1;
for i in v'range loop
case v(i) is
when '0' => c := '0';
when '1' => c := '1';
when others => c := '?';
end case;
str_value(str_len) := c;
str_len := str_len + 1;
end loop;
return str_value;
end str;
-- functions and procedures for window processing
function defaults return t_window_processing is
variable output : t_window_processing;
begin
output.working_window := (others => '1');
output.last_bit_value := '1';
output.first_good_edge := 0;
output.current_window_start := 0;
output.current_window_size := 0;
output.current_window_centre := 0;
output.largest_window_start := 0;
output.largest_window_size := 0;
output.largest_window_centre := 0;
output.window_centre_update := '1';
output.current_bit := 0;
output.multiple_eq_windows := false;
output.valid_phase_seen := false;
output.invalid_phase_seen := false;
output.found_a_good_edge := false;
output.status := no_valid_phases;
output.first_cycle := false;
output.windows_seen := 0;
return output;
end function defaults;
procedure initialise_window_for_proc ( working : inout t_window_processing ) is
variable v_working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
begin
v_working_window := working.working_window;
working := defaults;
working.working_window := v_working_window;
working.status := calculating;
working.first_cycle := true;
working.window_centre_update := '1';
working.windows_seen := 0;
end procedure initialise_window_for_proc;
procedure shift_window (working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
)
is
begin
if working.working_window(0) = '0' then
working.invalid_phase_seen := true;
else
working.valid_phase_seen := true;
end if;
-- general bit serial shifting of window and incrementing of current bit counter.
if working.current_bit < num_phases - 1 then
working.current_bit := working.current_bit + 1;
else
working.current_bit := 0;
end if;
working.last_bit_value := working.working_window(0);
working.working_window := working.working_window(0) & working.working_window(working.working_window'high downto 1);
--synopsis translate_off
-- for simulation to make it simpler to see IF we are not using all the bits in the window
working.working_window(working.working_window'high) := 'H'; -- for visual debug
--synopsis translate_on
working.working_window(num_phases -1) := working.last_bit_value;
working.first_cycle := false;
end procedure shift_window;
procedure find_centre_of_largest_data_valid_window
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure, then handle end conditions
if working.current_bit = 0 and working.found_a_good_edge = false then -- have been all way arround window (circular)
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
end if;
elsif working.current_bit = working.first_good_edge then -- if have found a good edge then complete a circular sweep to that edge
if working.multiple_eq_windows = true then
working.status := multiple_equal_windows;
else
working.status := valid_result;
end if;
end if;
end if;
-- start of a window condition
if working.last_bit_value = '0' and working.working_window(0) = '1' then
working.current_window_start := working.current_bit;
working.current_window_size := working.current_window_size + 1; -- equivalent to assigning to one because if not in a window then it is set to 0
working.window_centre_update := not working.window_centre_update;
working.current_window_centre := working.current_bit;
if working.found_a_good_edge /= true then -- if have not yet found a good edge then store this value
working.first_good_edge := working.current_bit;
working.found_a_good_edge := true;
end if;
-- end of window conditions
elsif working.last_bit_value = '1' and working.working_window(0) = '0' then
if working.current_window_size > working.largest_window_size then
working.largest_window_size := working.current_window_size;
working.largest_window_start := working.current_window_start;
working.largest_window_centre := working.current_window_centre;
working.multiple_eq_windows := false;
elsif working.current_window_size = working.largest_window_size then
working.multiple_eq_windows := true;
end if;
-- put counter in here because start of window 1 is observed twice
if working.found_a_good_edge = true then
working.windows_seen := working.windows_seen + 1;
end if;
working.current_window_size := 0;
elsif working.last_bit_value = '1' and working.working_window(0) = '1' and (working.found_a_good_edge = true) then --note operand in brackets is excessive but for may provide power savings and makes visual inspection of simulatuion easier
if working.window_centre_update = '1' then
if working.current_window_centre < num_phases -1 then
working.current_window_centre := working.current_window_centre + 1;
else
working.current_window_centre := 0;
end if;
end if;
working.window_centre_update := not working.window_centre_update;
working.current_window_size := working.current_window_size + 1;
end if;
shift_window(working,num_phases);
end procedure find_centre_of_largest_data_valid_window;
procedure find_last_failing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts + 1
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(1) = '1' and working.working_window(0) = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_last_failing_phase;
procedure find_first_passing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(0) = '1' and working.last_bit_value = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_first_passing_phase;
-- shift in current pass/fail result to the working window
procedure shift_in(
working : inout t_window_processing;
status : in std_logic;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
working.last_bit_value := working.working_window(0);
working.working_window(num_phases-1 downto 0) := (working.working_window(0) and status) & working.working_window(num_phases-1 downto 1);
end procedure;
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgrb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
-- extract PHY 'addr/cmd' to 'wdata_valid' write latency from current read data
function wd_lat_from_rdata(signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0))
return std_logic_vector is
variable v_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
v_wd_lat := (others => '0');
if set_wlat_dq_rep_width >= ADV_LAT_WIDTH then
v_wd_lat := rdata(v_wd_lat'high downto 0);
else
v_wd_lat := (others => '0');
v_wd_lat(set_wlat_dq_rep_width - 1 downto 0) := rdata(set_wlat_dq_rep_width - 1 downto 0);
end if;
return v_wd_lat;
end function;
-- check if rdata_valid is correctly aligned
function rdata_valid_aligned(
signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
signal rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0)
) return std_logic is
variable v_dq_rdata : std_logic_vector(DWIDTH_RATIO - 1 downto 0);
variable v_aligned : std_logic;
begin
-- Look at data from a single DQ pin 0 (DWIDTH_RATIO data bits)
for i in 0 to DWIDTH_RATIO - 1 loop
v_dq_rdata(i) := rdata(i*MEM_IF_DWIDTH);
end loop;
-- Check each alignment (necessary because in the HR case rdata can be in any alignment)
v_aligned := '0';
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata_valid(i) = '1' then
if v_dq_rdata(2*i + 1 downto 2*i) = "00" then
v_aligned := '1';
end if;
end if;
end loop;
return v_aligned;
end function;
-- set severity level for calibration failures
function set_cal_fail_sev_level (
generate_additional_debug_rtl : natural
) return severity_level is
begin
if generate_additional_debug_rtl = 1 then
return warning;
else
return failure;
end if;
end function;
constant cal_fail_sev_level : severity_level := set_cal_fail_sev_level(GENERATE_ADDITIONAL_DBG_RTL);
-- ------------------------------------------------------------------
-- signal declarations
-- rsc = resync - the mechanism of capturing DQ pin data onto a local clock domain
-- trk = tracking - a mechanism to track rsc clock phase with PVT variations
-- poa = postamble - protection circuitry from postamble glitched on DQS
-- ac = memory address / command signals
-- ------------------------------------------------------------------
-- main state machine
signal sig_dgrb_state : t_dgrb_state;
signal sig_dgrb_last_state : t_dgrb_state;
signal sig_rsc_req : t_resync_state; -- tells resync block which state to transition to.
-- centre of data-valid window process
signal sig_cdvw_state : t_window_processing;
-- control signals for the address/command process
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_ac_req : t_ac_state;
signal sig_dimm_driving_dq : std_logic;
signal sig_doing_rd : std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
signal sig_ac_even : std_logic; -- odd/even count of PHY clock cycles.
--
-- sig_ac_even behaviour
--
-- sig_ac_even is always '1' on the cycle a command is issued. It will
-- be '1' on even clock cycles thereafter and '0' otherwise.
--
-- ; ; ; ; ; ;
-- ; _______ ; ; ; ; ;
-- XXXXX / \ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- addr/cmd XXXXXX CMD XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- sig_ac_even ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- phy clk
-- count (0) (1) (2) (3) (4)
--
--
-- resync related signals
signal sig_rsc_ack : std_logic;
signal sig_rsc_err : std_logic;
signal sig_rsc_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_rsc_cdvw_phase : std_logic;
signal sig_rsc_cdvw_shift_in : std_logic;
signal sig_rsc_cdvw_calc : std_logic;
signal sig_rsc_pll_start_reconfig : std_logic;
signal sig_rsc_pll_inc_dec_n : std_logic;
signal sig_rsc_ac_access_req : std_logic; -- High when the resync block requires a training pattern to be read.
-- tracking related signals
signal sig_trk_ack : std_logic;
signal sig_trk_err : std_logic;
signal sig_trk_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_trk_cdvw_phase : std_logic;
signal sig_trk_cdvw_shift_in : std_logic;
signal sig_trk_cdvw_calc : std_logic;
signal sig_trk_pll_start_reconfig : std_logic;
signal sig_trk_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
signal sig_trk_pll_inc_dec_n : std_logic;
signal sig_trk_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
-- phs_shft_busy could (potentially) be asynchronous
-- triple register it for metastability hardening
-- these signals are the taps on the shift register
signal sig_phs_shft_busy : std_logic;
signal sig_phs_shft_busy_1t : std_logic;
signal sig_phs_shft_start : std_logic;
signal sig_phs_shft_end : std_logic;
-- locally register crl_dgrb to minimise fan out
signal ctrl_dgrb_r : t_ctrl_command;
-- command_op signals
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal current_mtp_almt : natural range 0 to 1;
signal single_bit_cal : std_logic;
-- codvw status signals (packed into record and sent to mmi block)
signal cal_codvw_phase : std_logic_vector(7 downto 0);
signal codvw_trk_shift : std_logic_vector(11 downto 0);
signal cal_codvw_size : std_logic_vector(7 downto 0);
-- error signal and result from main state machine (operations other than rsc or tracking)
signal sig_cmd_err : std_logic;
signal sig_cmd_result : std_logic_vector(c_command_result_len - 1 downto 0 );
-- signals that the training pattern matched correctly on the last clock
-- cycle.
signal sig_dq_pin_ctr : natural range 0 to MEM_IF_DWIDTH - 1;
signal sig_mtp_match : std_logic;
-- controls postamble match and timing.
signal sig_poa_match_en : std_logic;
signal sig_poa_match : std_logic;
-- postamble signals
signal sig_poa_ack : std_logic; -- '1' for postamble block to acknowledge.
-- calibration byte lane select
signal cal_byte_lanes : std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
signal codvw_grt_one_dvw : std_logic;
begin
doing_rd <= sig_doing_rd;
-- pack record of codvw status signals
dgrb_mmi.cal_codvw_phase <= cal_codvw_phase;
dgrb_mmi.codvw_trk_shift <= codvw_trk_shift;
dgrb_mmi.cal_codvw_size <= cal_codvw_size;
dgrb_mmi.codvw_grt_one_dvw <= codvw_grt_one_dvw;
-- map some internal signals to outputs
dgrb_ac <= sig_addr_cmd;
-- locally register crl_dgrb to minimise fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_dgrb_r <= defaults;
elsif rising_edge(clk) then
ctrl_dgrb_r <= ctrl_dgrb;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
current_mtp_almt <= 0;
single_bit_cal <= '0';
cal_byte_lanes <= (others => '0');
elsif rising_edge(clk) then
if ctrl_dgrb_r.command_req = '1' then
current_cs <= ctrl_dgrb_r.command_op.current_cs;
current_mtp_almt <= ctrl_dgrb_r.command_op.mtp_almt;
single_bit_cal <= ctrl_dgrb_r.command_op.single_bit;
end if;
-- mux byte lane select for given chip select
for i in 0 to MEM_IF_DQS_WIDTH - 1 loop
cal_byte_lanes(i) <= ctl_cal_byte_lanes((current_cs * MEM_IF_DQS_WIDTH) + i);
end loop;
assert ctl_cal_byte_lanes(0) = '1' report dgrb_report_prefix & " Byte lane 0 (chip select 0) disable is not supported - ending simulation" severity failure;
end if;
end process;
-- ------------------------------------------------------------------
-- main state machine for dgrb architecture
--
-- process of commands from control (ctrl) block and overall control of
-- the subsequent calibration processing functions
-- also communicates completion and any errors back to the ctrl block
-- read data valid alignment and advertised latency calculations are
-- included in this block
-- ------------------------------------------------------------------
dgrb_main_block : block
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
dgrb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
-- initialise state
sig_dgrb_state <= s_idle;
sig_dgrb_last_state <= s_idle;
sig_ac_req <= s_ac_idle;
sig_rsc_req <= s_rsc_idle;
-- set up rd_lat defaults
rd_lat <= c_default_rd_lat_slv;
wd_lat <= c_default_wd_lat_slv;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- reset counter
sig_count <= 0;
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- sig_wd_lat
sig_wd_lat <= (others => '0');
-- status of the ac_nt alignment
dgrb_ctrl_ac_nt_good <= '1';
elsif rising_edge(clk) then
sig_dgrb_last_state <= sig_dgrb_state;
sig_rsc_req <= s_rsc_idle;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- register wd_lat output.
wd_lat <= sig_wd_lat;
case sig_dgrb_state is
when s_idle =>
sig_count <= 0;
if ctrl_dgrb_r.command_req = '1' then
if curr_active_block(ctrl_dgrb_r.command) = dgrb then
sig_dgrb_state <= s_wait_admin;
end if;
end if;
sig_ac_req <= s_ac_idle;
when s_wait_admin =>
sig_dgrb_state <= s_wait_admin;
case ctrl_dgrb_r.command is
when cmd_read_mtp => sig_dgrb_state <= s_read_mtp;
when cmd_rrp_reset => sig_dgrb_state <= s_reset_cdvw;
when cmd_rrp_sweep => sig_dgrb_state <= s_test_phases;
when cmd_rrp_seek => sig_dgrb_state <= s_seek_cdvw;
when cmd_rdv => sig_dgrb_state <= s_rdata_valid_align;
when cmd_prep_adv_rd_lat => sig_dgrb_state <= s_adv_rd_lat_setup;
when cmd_prep_adv_wr_lat => sig_dgrb_state <= s_adv_wd_lat;
when cmd_tr_due => sig_dgrb_state <= s_track;
when cmd_poa => sig_dgrb_state <= s_poa_cal;
when others =>
report dgrb_report_prefix & "unknown command" severity failure;
sig_dgrb_state <= s_idle;
end case;
when s_reset_cdvw =>
-- the cdvw proc watches for this state and resets the cdvw
-- state block.
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_reset_cdvw;
end if;
when s_test_phases =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_test_phase;
if sig_rsc_ac_access_req = '1' then
sig_ac_req <= s_ac_read_mtp;
else
sig_ac_req <= s_ac_idle;
end if;
end if;
when s_seek_cdvw | s_read_mtp =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_cdvw_calc;
end if;
when s_release_admin =>
sig_ac_req <= s_ac_idle;
if dgrb_ac_access_gnt = '0' and sig_dimm_driving_dq = '0' then
sig_dgrb_state <= s_idle;
end if;
when s_rdata_valid_align =>
sig_ac_req <= s_ac_read_rdv;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
if sig_dimm_driving_dq = '1' then
-- only do comparison if rdata_valid is all 'ones'
if rdata_valid /= std_logic_vector(to_unsigned(0, DWIDTH_RATIO/2)) then
-- rdata_valid is all ones
if rdata_valid_aligned(rdata, rdata_valid) = '1' then
-- success: rdata_valid and rdata are properly aligned
sig_dgrb_state <= s_release_admin;
else
-- misaligned: bring in rdata_valid by a clock cycle
seq_rdata_valid_lat_dec <= '1';
end if;
end if;
end if;
when s_adv_rd_lat_setup =>
-- wait for sig_doing_rd to go high
sig_ac_req <= s_ac_read_rdv;
if sig_dgrb_state /= sig_dgrb_last_state then
rd_lat <= (others => '0');
sig_count <= 0;
elsif sig_dimm_driving_dq = '1' and sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) = '1' then
-- a read has started: start counter
sig_dgrb_state <= s_adv_rd_lat;
end if;
when s_adv_rd_lat =>
sig_ac_req <= s_ac_read_rdv;
if sig_dimm_driving_dq = '1' then
if sig_count >= 2**rd_lat'length then
report dgrb_report_prefix & "maximum read latency exceeded while waiting for rdata_valid" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_MAX_RD_LAT_EXCEEDED,sig_cmd_result'length));
end if;
if rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- have found the read latency
sig_dgrb_state <= s_release_admin;
else
sig_count <= sig_count + 1;
end if;
rd_lat <= std_logic_vector(to_unsigned(sig_count, rd_lat'length));
end if;
when s_adv_wd_lat =>
sig_ac_req <= s_ac_read_wd_lat;
if sig_dgrb_state /= sig_dgrb_last_state then
sig_wd_lat <= (others => '0');
else
if sig_dimm_driving_dq = '1' and rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- construct wd_lat using data from the lowest addresses
-- wd_lat <= rdata(MEM_IF_DQ_PER_DQS - 1 downto 0);
sig_wd_lat <= wd_lat_from_rdata(rdata);
sig_dgrb_state <= s_release_admin;
-- check data integrity
for i in 1 to MEM_IF_DWIDTH/set_wlat_dq_rep_width - 1 loop
-- wd_lat is copied across MEM_IF_DWIDTH bits in fields of width MEM_IF_DQ_PER_DQS.
-- All of these fields must have the same value or it is an error.
-- only check if byte lane not disabled
if cal_byte_lanes((i*set_wlat_dq_rep_width)/MEM_IF_DQ_PER_DQS) = '1' then
if rdata(set_wlat_dq_rep_width - 1 downto 0) /= rdata((i+1)*set_wlat_dq_rep_width - 1 downto i*set_wlat_dq_rep_width) then
-- signal write latency different between DQS groups
report dgrb_report_prefix & "the write latency read from memory is different accross dqs groups" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_WD_LAT_DISAGREEMENT, sig_cmd_result'length));
end if;
end if;
end loop;
-- check if ac_nt alignment is ok
-- in this condition all DWIDTH_RATIO copies of rdata should be identical
dgrb_ctrl_ac_nt_good <= '1';
if DWIDTH_RATIO /= 2 then
for j in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata(j*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto j*MEM_IF_DWIDTH) /= rdata((j+2)*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto (j+2)*MEM_IF_DWIDTH) then
dgrb_ctrl_ac_nt_good <= '0';
end if;
end loop;
end if;
end if;
end if;
when s_poa_cal =>
-- Request the address/command block begins reading the "M"
-- training pattern here. There is no provision for doing
-- refreshes so this limits the time spent in this state
-- to 9 x tREFI (by the DDR2 JEDEC spec). Instead of the
-- maximum value, a maximum "safe" time in this postamble
-- state is chosen to be tpoamax = 5 x tREFI = 5 x 3.9us.
-- When entering this s_poa_cal state it must be guaranteed
-- that the number of stacked refreshes is at maximum.
--
-- Minimum clock freq supported by DRAM is fck,min=125MHz.
-- Each adjustment to postamble latency requires 16*clock
-- cycles (time to read "M" training pattern twice) so
-- maximum number of adjustments to POA latency (n) is:
--
-- n = (5 x trefi x fck,min) / 16
-- = (5 x 3.9us x 125MHz) / 16
-- ~ 152
--
-- Postamble latency must be adjusted less than 152 cycles
-- to meet this requirement.
--
sig_ac_req <= s_ac_read_poa_mtp;
if sig_poa_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when s_track =>
if sig_trk_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when others => null;
report dgrb_report_prefix & "undefined state" severity failure;
sig_dgrb_state <= s_idle;
end case;
-- default if not calibrating go to idle state via s_release_admin
if ctrl_dgrb_r.command = cmd_idle and
sig_dgrb_state /= s_idle and
sig_dgrb_state /= s_release_admin then
sig_dgrb_state <= s_release_admin;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- metastability hardening of potentially async phs_shift_busy signal
--
-- Triple register it for metastability hardening. This process
-- creates the shift register. Also add a sig_phs_shft_busy and
-- an sig_phs_shft_busy_1t echo because various other processes find
-- this useful.
-- ------------------------------------------------------------------
phs_shft_busy_reg: block
signal phs_shft_busy_1r : std_logic;
signal phs_shft_busy_2r : std_logic;
signal phs_shft_busy_3r : std_logic;
begin
phs_shift_busy_sync : process (clk, rst_n)
begin
if rst_n = '0' then
sig_phs_shft_busy <= '0';
sig_phs_shft_busy_1t <= '0';
phs_shft_busy_1r <= '0';
phs_shft_busy_2r <= '0';
phs_shft_busy_3r <= '0';
sig_phs_shft_start <= '0';
sig_phs_shft_end <= '0';
elsif rising_edge(clk) then
sig_phs_shft_busy_1t <= phs_shft_busy_3r;
sig_phs_shft_busy <= phs_shft_busy_2r;
-- register the below to reduce fan out on sig_phs_shft_busy and sig_phs_shft_busy_1t
sig_phs_shft_start <= phs_shft_busy_3r or phs_shft_busy_2r;
sig_phs_shft_end <= phs_shft_busy_3r and not(phs_shft_busy_2r);
phs_shft_busy_3r <= phs_shft_busy_2r;
phs_shft_busy_2r <= phs_shft_busy_1r;
phs_shft_busy_1r <= phs_shft_busy;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- PLL reconfig MUX
--
-- switches PLL Reconfig input between tracking and resync blocks
-- ------------------------------------------------------------------
pll_reconf_mux : process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_select <= (others => '0');
seq_pll_start_reconfig <= '0';
elsif rising_edge(clk) then
if sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_reset_cdvw then
seq_pll_select <= pll_resync_clk_index;
seq_pll_inc_dec_n <= sig_rsc_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_rsc_pll_start_reconfig;
elsif sig_dgrb_state = s_track then
seq_pll_select <= sig_trk_pll_select;
seq_pll_inc_dec_n <= sig_trk_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_trk_pll_start_reconfig;
else
seq_pll_select <= pll_measure_clk_index;
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- Centre of data valid window calculation block
--
-- This block handles the sharing of the centre of window calculation
-- logic between the rsc and trk operations. Functions defined in the
-- header of this entity are called to do this.
-- ------------------------------------------------------------------
cdvw_block : block
signal sig_cdvw_calc_1t : std_logic;
begin
-- purpose: manages centre of data valid window calculations
-- type : sequential
-- inputs : clk, rst_n
-- outputs: sig_cdvw_state
cdvw_proc: process (clk, rst_n)
variable v_cdvw_state : t_window_processing;
variable v_start_calc : std_logic;
variable v_shift_in : std_logic;
variable v_phase : std_logic;
begin -- process cdvw_proc
if rst_n = '0' then -- asynchronous reset (active low)
sig_cdvw_state <= defaults;
sig_cdvw_calc_1t <= '0';
elsif rising_edge(clk) then -- rising clock edge
v_cdvw_state := sig_cdvw_state;
case sig_dgrb_state is
when s_track =>
v_start_calc := sig_trk_cdvw_calc;
v_phase := sig_trk_cdvw_phase;
v_shift_in := sig_trk_cdvw_shift_in;
when s_read_mtp | s_seek_cdvw | s_test_phases =>
v_start_calc := sig_rsc_cdvw_calc;
v_phase := sig_rsc_cdvw_phase;
v_shift_in := sig_rsc_cdvw_shift_in;
when others =>
v_start_calc := '0';
v_phase := '0';
v_shift_in := '0';
end case;
if sig_dgrb_state = s_reset_cdvw or (sig_dgrb_state = s_track and sig_dgrb_last_state /= s_track) then
-- reset *C*entre of *D*ata *V*alid *W*indow
v_cdvw_state := defaults;
elsif sig_cdvw_calc_1t /= '1' and v_start_calc = '1' then
initialise_window_for_proc(v_cdvw_state);
elsif v_cdvw_state.status = calculating then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, PLL_STEPS_PER_CYCLE);
else -- can be a 720 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, c_max_phase_shifts);
end if;
elsif v_shift_in = '1' then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
shift_in(v_cdvw_state, v_phase, PLL_STEPS_PER_CYCLE);
else
shift_in(v_cdvw_state, v_phase, c_max_phase_shifts);
end if;
end if;
sig_cdvw_calc_1t <= v_start_calc;
sig_cdvw_state <= v_cdvw_state;
end if;
end process cdvw_proc;
end block;
-- ------------------------------------------------------------------
-- block for resync calculation.
--
-- This block implements the following:
-- 1) Control logic for the rsc slave state machine
-- 2) Processing of resync operations - through reports form cdvw block and
-- test pattern match blocks
-- 3) Shifting of the resync phase for rsc sweeps
-- 4) Writing of results to iram (optional)
-- ------------------------------------------------------------------
rsc_block : block
signal sig_rsc_state : t_resync_state;
signal sig_rsc_last_state : t_resync_state;
signal sig_num_phase_shifts : natural range c_max_phase_shifts - 1 downto 0;
signal sig_rewind_direction : std_logic;
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_test_dq_expired : std_logic;
signal sig_chkd_all_dq_pins : std_logic;
-- prompts to write data to iram
signal sig_dgrb_iram : t_iram_push; -- internal copy of dgrb to iram control signals
signal sig_rsc_push_rrp_sweep : std_logic; -- push result of a rrp sweep pass (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_pass : std_logic; -- result of a rrp sweep result (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_seek : std_logic; -- write seek results (for cmd_rrp_seek / cmd_read_mtp states)
signal sig_rsc_push_footer : std_logic; -- write a footer
signal sig_dq_pin_ctr_r : natural range 0 to MEM_IF_DWIDTH - 1; -- registered version of dq_pin_ctr
signal sig_rsc_curr_phase : natural range 0 to c_max_phase_shifts - 1; -- which phase is being processed
signal sig_iram_idle : std_logic; -- track if iram currently writing data
signal sig_mtp_match_en : std_logic;
-- current byte lane disabled?
signal sig_curr_byte_ln_dis : std_logic;
signal sig_iram_wds_req : integer; -- words required for a given iram dump (used to locate where to write footer)
begin
-- When using DQS capture or not at full-rate only match on "even" clock cycles.
sig_mtp_match_en <= active_high(sig_ac_even = '1' or MEM_IF_DQS_CAPTURE = 0 or DWIDTH_RATIO /= 2);
-- register current byte lane disable mux for speed
byte_lane_dis: process (clk, rst_n)
begin
if rst_n = '0' then
sig_curr_byte_ln_dis <= '0';
elsif rising_edge(clk) then
sig_curr_byte_ln_dis <= cal_byte_lanes(sig_dq_pin_ctr/MEM_IF_DQ_PER_DQS);
end if;
end process;
-- check if all dq pins checked in rsc sweep
chkd_dq : process (clk, rst_n)
begin
if rst_n = '0' then
sig_chkd_all_dq_pins <= '0';
elsif rising_edge(clk) then
if sig_dq_pin_ctr = 0 then
sig_chkd_all_dq_pins <= '1';
else
sig_chkd_all_dq_pins <= '0';
end if;
end if;
end process;
-- main rsc process
rsc_proc : process (clk, rst_n)
-- these are temporary variables which should not infer FFs and
-- are not guaranteed to be initialized by s_rsc_idle.
variable v_rdata_correct : std_logic;
variable v_phase_works : std_logic;
begin
if rst_n = '0' then
-- initialise signals
sig_rsc_state <= s_rsc_idle;
sig_rsc_last_state <= s_rsc_idle;
sig_dq_pin_ctr <= 0;
sig_num_phase_shifts <= c_max_phase_shifts - 1; -- want c_max_phase_shifts-1 inc / decs of phase
sig_count <= 0;
sig_test_dq_expired <= '0';
v_phase_works := '0';
-- interface to other processes to tell them when we are done.
sig_rsc_ack <= '0';
sig_rsc_err <= '0';
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, c_command_result_len));
-- centre of data valid window functions
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
-- set up PLL reconfig interface controls
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- True when access to the ac_block is required.
sig_rsc_ac_access_req <= '0';
-- default values on centre and size of data valid window
if SIM_TIME_REDUCTIONS = 1 then
cal_codvw_phase <= std_logic_vector(to_unsigned(PRESET_CODVW_PHASE, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(PRESET_CODVW_SIZE, 8));
else
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
end if;
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
codvw_grt_one_dvw <= '0';
elsif rising_edge(clk) then
-- default values assigned to some signals
sig_rsc_ack <= '0';
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- by default don't ask the resync block to read anything
sig_rsc_ac_access_req <= '0';
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
sig_test_dq_expired <= '0';
-- resync state machine
case sig_rsc_state is
when s_rsc_idle =>
-- initialize those signals we are ready to use.
sig_dq_pin_ctr <= 0;
sig_count <= 0;
if sig_rsc_state = sig_rsc_last_state then -- avoid transition when acknowledging a command has finished
if sig_rsc_req = s_rsc_test_phase then
sig_rsc_state <= s_rsc_test_phase;
elsif sig_rsc_req = s_rsc_cdvw_calc then
sig_rsc_state <= s_rsc_cdvw_calc;
elsif sig_rsc_req = s_rsc_seek_cdvw then
sig_rsc_state <= s_rsc_seek_cdvw;
elsif sig_rsc_req = s_rsc_reset_cdvw then
sig_rsc_state <= s_rsc_reset_cdvw;
else
sig_rsc_state <= s_rsc_idle;
end if;
end if;
when s_rsc_next_phase =>
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- PLL phase shift started - so stop requesting a shift
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_state <= s_rsc_test_phase;
end if;
when s_rsc_test_phase =>
v_phase_works := '1';
-- Note: For single pin single CS calibration set sig_dq_pin_ctr to 0 to
-- ensure that only 1 pin calibrated
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
if single_bit_cal = '1' then
sig_dq_pin_ctr <= 0;
else
sig_dq_pin_ctr <= MEM_IF_DWIDTH-1;
end if;
when s_rsc_wait_for_idle_dimm =>
if sig_dimm_driving_dq = '0' then
sig_rsc_state <= s_rsc_flush_datapath;
end if;
when s_rsc_flush_datapath =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= c_max_read_lat - 1;
else
if sig_dimm_driving_dq = '1' then
if sig_count = 0 then
sig_rsc_state <= s_rsc_test_dq;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_test_dq =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= 2*c_cal_mtp_t;
else
if sig_dimm_driving_dq = '1' then
if (
(sig_mtp_match = '1' and sig_mtp_match_en = '1') or -- have a pattern match
(sig_test_dq_expired = '1') or -- time in this phase has expired.
sig_curr_byte_ln_dis = '0' -- byte lane disabled
) then
v_phase_works := v_phase_works and ((sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis));
sig_rsc_push_rrp_sweep <= '1';
sig_rsc_push_rrp_pass <= (sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis);
if sig_chkd_all_dq_pins = '1' then
-- finished checking all dq pins.
-- done checking this phase.
-- shift phase status into
sig_rsc_cdvw_phase <= v_phase_works;
sig_rsc_cdvw_shift_in <= '1';
if sig_num_phase_shifts /= 0 then
-- there are more phases to test so shift to next phase
sig_rsc_state <= s_rsc_next_phase;
else
-- no more phases to check.
-- clean up after ourselves by
-- going into s_rsc_rewind_phase
sig_rsc_state <= s_rsc_rewind_phase;
sig_rewind_direction <= c_pll_phs_dec;
sig_num_phase_shifts <= c_max_phase_shifts - 1;
end if;
else
-- shift to next dq pin
if MEM_IF_DWIDTH > 71 and -- if >= 72 pins then:
(sig_dq_pin_ctr mod 64) = 0 then -- ensure refreshes at least once every 64 pins
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
else -- otherwise continue sweep
sig_rsc_state <= s_rsc_flush_datapath;
end if;
sig_dq_pin_ctr <= sig_dq_pin_ctr - 1;
end if;
else
sig_count <= sig_count - 1;
if sig_count = 1 then
sig_test_dq_expired <= '1';
end if;
end if;
end if;
end if;
when s_rsc_reset_cdvw =>
sig_rsc_state <= s_rsc_rewind_phase;
-- determine the amount to rewind by (may be wind forward depending on tracking behaviour)
if to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift < 0 then
sig_num_phase_shifts <= - (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_inc;
else
sig_num_phase_shifts <= (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_dec;
end if;
-- reset the calibrated phase and size to zero (because un-doing prior calibration here)
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
when s_rsc_rewind_phase =>
-- rewinds the resync PLL by sig_num_phase_shifts steps and returns to idle state
if sig_num_phase_shifts = 0 then
-- no more steps to take off, go to next state
sig_num_phase_shifts <= c_max_phase_shifts - 1;
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
sig_rsc_pll_inc_dec_n <= sig_rewind_direction;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_busy = '1' then
-- inhibit a phase shift if phase shift is busy.
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_busy_1t = '1' and sig_phs_shft_busy /= '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_pll_start_reconfig <= '0';
end if;
end if;
when s_rsc_cdvw_calc =>
if sig_rsc_state /= sig_rsc_last_state then
if sig_dgrb_state = s_read_mtp then
report dgrb_report_prefix & "gathered resync phase samples (for mtp alignment " & natural'image(current_mtp_almt) & ") is DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
else
report dgrb_report_prefix & "gathered resync phase samples DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
end if;
sig_rsc_cdvw_calc <= '1'; -- begin calculating result
else
sig_rsc_state <= s_rsc_cdvw_wait;
end if;
when s_rsc_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
-- a result has been reached.
if sig_dgrb_state = s_read_mtp then -- if doing mtp alignment then skip setting phase
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
if sig_cdvw_state.status = valid_result then
-- calculation successfully found a
-- data-valid window to seek to.
sig_rsc_state <= s_rsc_seek_cdvw;
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, sig_rsc_result'length));
-- If more than one data valid window was seen, then set the result code :
if (sig_cdvw_state.windows_seen > 1) then
report dgrb_report_prefix & "Warning : multiple data-valid windows found, largest chosen." severity note;
codvw_grt_one_dvw <= '1';
else
report dgrb_report_prefix & "data-valid window found successfully." severity note;
end if;
else
-- calculation failed to find a data-valid window.
report dgrb_report_prefix & "couldn't find a data-valid window in resync." severity warning;
sig_rsc_ack <= '1';
sig_rsc_err <= '1';
sig_rsc_state <= s_rsc_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when multiple_equal_windows =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_rsc_result'length));
when no_valid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when others =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_rsc_result'length));
end case;
end if;
end if;
-- signal to write a rrp_sweep result to iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
sig_rsc_push_rrp_seek <= '1';
end if;
end if;
when s_rsc_seek_cdvw =>
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_count <= sig_cdvw_state.largest_window_centre;
else
if sig_count = 0 or
((MEM_IF_DQS_CAPTURE = 1 and DWIDTH_RATIO = 2) and
sig_count = PLL_STEPS_PER_CYCLE) -- if FR and DQS capture ensure within 0-360 degrees phase
then
-- ready to transition to next state
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
-- return largest window centre and size in the result
-- perform cal_codvw phase / size update only if a valid result is found
if sig_cdvw_state.status = valid_result then
cal_codvw_phase <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
end if;
-- leaving sig_rsc_err or sig_rsc_result at
-- their default values (of success)
else
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- inhibit a phase shift if phase shift is busy
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_wait_iram =>
-- hold off check 1 clock cycle to enable last rsc push operations to start
if sig_rsc_state = sig_rsc_last_state then
if sig_iram_idle = '1' then
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
if sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_read_mtp then
sig_rsc_push_footer <= '1';
end if;
end if;
end if;
when others =>
null;
end case;
sig_rsc_last_state <= sig_rsc_state;
end if;
end process;
-- write results to the iram
iram_push: process (clk, rst_n)
begin
if rst_n = '0' then
sig_dgrb_iram <= defaults;
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_iram_wds_req <= 0;
elsif rising_edge(clk) then
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
if sig_dgrb_iram.iram_write = '1' and sig_dgrb_iram.iram_done = '1' then
report dgrb_report_prefix & "iram_done and iram_write signals concurrently set - iram contents may be corrupted" severity failure;
end if;
if sig_dgrb_iram.iram_write = '0' and sig_dgrb_iram.iram_done = '0' then
sig_iram_idle <= '1';
else
sig_iram_idle <= '0';
end if;
-- registered sig_dq_pin_ctr to align with rrp_sweep result
sig_dq_pin_ctr_r <= sig_dq_pin_ctr;
-- calculate current phase (registered to align with rrp_sweep result)
sig_rsc_curr_phase <= (c_max_phase_shifts - 1) - sig_num_phase_shifts;
-- serial push of rrp_sweep results into memory
if sig_rsc_push_rrp_sweep = '1' then
-- signal an iram write and track a write pending
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
-- if not single_bit_cal then pack pin phase results in MEM_IF_DWIDTH word blocks
if single_bit_cal = '1' then
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32);
sig_iram_wds_req <= iram_wd_for_one_pin_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
else
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32) * MEM_IF_DWIDTH;
sig_iram_wds_req <= iram_wd_for_full_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
end if;
-- check if current pin and phase passed:
sig_dgrb_iram.iram_pushdata(0) <= sig_rsc_push_rrp_pass;
-- bit offset is modulo phase
sig_dgrb_iram.iram_bitnum <= sig_rsc_curr_phase mod 32;
end if;
-- write result of rrp_calc to iram when completed
if sig_rsc_push_rrp_seek = '1' then -- a result found
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
sig_dgrb_iram.iram_wordnum <= 0;
sig_iram_wds_req <= 1; -- note total word requirement
if sig_cdvw_state.status = valid_result then -- result is valid
sig_dgrb_iram.iram_pushdata <= x"0000" &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8)) &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
else -- invalid result (error code communicated elsewhere)
sig_dgrb_iram.iram_pushdata <= x"FFFF" & -- signals an error condition
x"0000";
end if;
end if;
-- when stage finished write footer
if sig_rsc_push_footer = '1' then
sig_dgrb_iram.iram_done <= '1';
sig_iram_idle <= '0';
-- set address location of footer
sig_dgrb_iram.iram_wordnum <= sig_iram_wds_req;
end if;
-- if write completed deassert iram_write and done signals
if iram_push_done = '1' then
sig_dgrb_iram.iram_write <= '0';
sig_dgrb_iram.iram_done <= '0';
end if;
else
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_dgrb_iram <= defaults;
end if;
end if;
end process;
-- concurrently assign sig_dgrb_iram to dgrb_iram
dgrb_iram <= sig_dgrb_iram;
end block; -- resync calculation
-- ------------------------------------------------------------------
-- test pattern match block
--
-- This block handles the sharing of logic for test pattern matching
-- which is used in resync and postamble calibration / code blocks
-- ------------------------------------------------------------------
tp_match_block : block
--
-- Ascii Waveforms:
--
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- delayed_dqs |____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ ; _______ ; _______ ; _______ ; _______ _______
-- XXXXX / \ / \ / \ / \ / \ / \
-- c0,c1 XXXXXX A B X C D X E F X G H X I J X L M X captured data
-- XXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____; ____; ____ ____ ____ ____ ____
-- 180-resync_clk |____| |____| |____| |____| |____| |____| | 180deg shift from delayed dqs
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ _______ _______ _______ _______ ____
-- XXXXXXXXXX / \ / \ / \ / \ / \ /
-- 180-r0,r1 XXXXXXXXXXX A B X C D X E F X G H X I J X L resync data
-- XXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- 360-resync_clk ____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ ; _______ ; _______ ; _______ ; _______
-- XXXXXXXXXXXXXXX / \ / \ / \ / \ / \
-- 360-r0,r1 XXXXXXXXXXXXXXXX A B X C D X E F X G H X I J X resync data
-- XXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____ ____
-- 540-resync_clk |____| |____| |____| |____| |____| |____| |
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ _______ _______ _______ ____
-- XXXXXXXXXXXXXXXXXXX / \ / \ / \ / \ /
-- 540-r0,r1 XXXXXXXXXXXXXXXXXXXX A B X C D X E F X G H X I resync data
-- XXXXXXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ;____ ____ ____ ____ ____ ____
-- phy_clk |____| |____| |____| |____| |____| |____| |____|
--
-- 0 1 2 3 4 5 6
--
--
-- |<- Aligned Data ->|
-- phy_clk 180-r0,r1 540-r0,r1 sig_mtp_match_en (generated from sig_ac_even)
-- 0 XXXXXXXX XXXXXXXX '1'
-- 1 XXXXXXAB XXXXXXXX '0'
-- 2 XXXXABCD XXXXXXAB '1'
-- 3 XXABCDEF XXXXABCD '0'
-- 4 ABCDEFGH XXABCDEF '1'
-- 5 CDEFGHAB ABCDEFGH '0'
--
-- In DQS-based capture, sweeping resync_clk from 180 degrees to 360
-- does not necessarily result in a failure because the setup/hold
-- requirements are so small. The data comparison needs to fail when
-- the resync_clk is shifted more than 360 degrees. The
-- sig_mtp_match_en signal allows the sequencer to blind itself
-- training pattern matches that occur above 360 degrees.
--
--
--
--
--
-- Asserts sig_mtp_match.
--
-- Data comes in from rdata and is pushed into a two-bit wide shift register.
-- It is a critical assumption that the rdata comes back byte aligned.
--
--
--sig_mtp_match_valid
-- rdata_valid (shift-enable)
-- |
-- |
-- +-----------------------+-----------+------------------+
-- ___ | | |
-- dq(0) >---| \ | Shift Register |
-- dq(1) >---| \ +------+ +------+ +------------------+
-- dq(2) >---| )--->| D(0) |-+->| D(1) |-+->...-+->| D(c_cal_mtp_len - 1) |
-- ... | / +------+ | +------+ | | +------------------+
-- dq(n-1) >---|___/ +-----------++-...-+
-- | || +---+
-- | (==)--------> sig_mtp_match_0t ---->| |-->sig_mtp_match_1t-->sig_mtp_match
-- | || +---+
-- | +-----------++...-+
-- sig_dq_pin_ctr >-+ +------+ | +------+ | | +------------------+
-- | P(0) |-+ | P(1) |-+ ...-+->| P(c_cal_mtp_len - 1) |
-- +------+ +------+ +------------------+
--
--
--
--
signal sig_rdata_current_pin : std_logic_vector(c_cal_mtp_len - 1 downto 0);
-- A fundamental assumption here is that rdata_valid is all
-- ones or all zeros - not both.
signal sig_rdata_valid_1t : std_logic; -- rdata_valid delayed by 1 clock period.
signal sig_rdata_valid_2t : std_logic; -- rdata_valid delayed by 2 clock periods.
begin
rdata_valid_1t_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_valid_1t <= '0';
sig_rdata_valid_2t <= '0';
elsif rising_edge(clk) then
sig_rdata_valid_2t <= sig_rdata_valid_1t;
sig_rdata_valid_1t <= rdata_valid(0);
end if;
end process;
-- MUX data into sig_rdata_current_pin shift register.
rdata_current_pin_proc: process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_current_pin <= (others => '0');
elsif rising_edge(clk) then
-- shift old data down the shift register
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO downto 0) <=
sig_rdata_current_pin(sig_rdata_current_pin'high downto DWIDTH_RATIO);
-- shift new data into the bottom of the shift register.
for i in 0 to DWIDTH_RATIO - 1 loop
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO + 1 + i) <= rdata(i*MEM_IF_DWIDTH + sig_dq_pin_ctr);
end loop;
end if;
end process;
mtp_match_proc : process (clk, rst_n)
begin
if rst_n = '0' then -- * when at least c_max_read_lat clock cycles have passed
sig_mtp_match <= '0';
elsif rising_edge(clk) then
sig_mtp_match <= '0';
if sig_rdata_current_pin = c_cal_mtp then
sig_mtp_match <= '1';
end if;
end if;
end process;
poa_match_proc : process (clk, rst_n)
-- poa_match_Calibration Strategy
--
-- Ascii Waveforms:
--
-- __ __ __ __ __ __ __ __ __
-- clk __| |__| |__| |__| |__| |__| |__| |__| |__| |
--
-- ; ; ; ;
-- _________________
-- rdata_valid ________| |___________________________
--
-- ; ; ; ;
-- _____
-- poa_match_en ______________________________________| |_______________
--
-- ; ; ; ;
-- _____
-- poa_match XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
--
--
-- Notes:
-- -poa_match is only valid while poa_match_en is asserted.
--
--
--
--
--
--
begin
if rst_n = '0' then
sig_poa_match_en <= '0';
sig_poa_match <= '0';
elsif rising_edge(clk) then
sig_poa_match <= '0';
sig_poa_match_en <= '0';
if sig_rdata_valid_2t = '1' and sig_rdata_valid_1t = '0' then
sig_poa_match_en <= '1';
end if;
if DWIDTH_RATIO = 2 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 6) = "111100" then
sig_poa_match <= '1';
end if;
elsif DWIDTH_RATIO = 4 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 8) = "11111100" then
sig_poa_match <= '1';
end if;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO" severity failure;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- Postamble calibration
--
-- Implements the postamble slave state machine and collates the
-- processing data from the test pattern match block.
-- ------------------------------------------------------------------
poa_block : block
-- Postamble Calibration Strategy
--
-- Ascii Waveforms:
--
-- c_read_burst_t c_read_burst_t
-- ;<------->; ;<------->;
-- ; ; ; ;
-- __ / / __
-- mem_dq[0] ___________| |_____\ \________| |___
--
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- poa_enable ______| |___\ \_| |___
-- ; ; ; ;
-- ; ; ; ;
-- __ / / ______
-- rdata[0] ___________| |______\ \_______|
-- ; ; ; ;
-- ; ; ; ;
-- ; ; ; ;
-- _ / / _
-- poa_match_en _____________| |___\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / / _
-- poa_match ___________________\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _ / /
-- seq_poa_lat_dec _______________| |_\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / /
-- seq_poa_lat_inc ___________________\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
--
-- (1) (2)
--
--
-- (1) poa_enable signal is late, and the zeros on mem_dq after (1)
-- are captured.
-- (2) poa_enable signal is aligned. Zeros following (2) are not
-- captured rdata remains at '1'.
--
-- The DQS capture circuit wth the dqs enable asynchronous set.
--
--
--
-- dqs_en_async_preset ----------+
-- |
-- v
-- +---------+
-- +--|Q SET D|----------- gnd
-- | | <O---+
-- | +---------+ |
-- | |
-- | |
-- +--+---. |
-- |AND )--------+------- dqs_bus
-- delayed_dqs -----+---^
--
--
--
-- _____ _____ _____ _____
-- dqs ____| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ;
-- ; ; ; ;
-- _____ _____ _____ _____
-- delayed_dqs _______| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ; ; ; ;
-- ; ______________________________________________________________
-- dqs_en_async_ _____________________________| |_____
-- preset
-- ; ; ; ; ;
-- ; ; ; ; ;
-- _____ _____ _____
-- dqs_bus _______| |_________________| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ;
-- (1) (2)
--
--
-- Notes:
-- (1) The dqs_bus pulse here comes because the last value of Q
-- is '1' until the first DQS pulse clocks gnd into the FF,
-- brings low the AND gate, and disables dqs_bus. A training
-- pattern could potentially match at this point even though
-- between (1) and (2) there are no dqs_bus triggers. Data
-- is frozen on rdata while awaiting the dqs_bus pulses at
-- (2). For this reason, wait until the first match of the
-- training pattern, and continue reducing latency until it
-- TP no longer matches, then increase latency by one. In
-- this case, dqs_en_async_preset will have its latency
-- reduced by three until the training pattern is not matched,
-- then latency is increased by one.
--
--
--
--
-- Postamble calibration state
type t_poa_state is (
-- decrease poa enable latency by 1 cycle iteratively until 'correct' position found
s_poa_rewind_to_pass,
-- poa cal complete
s_poa_done
);
constant c_poa_lat_cmd_wait : natural := 10; -- Number of clock cycles to wait for lat_inc/lat_dec signal to take effect.
constant c_poa_max_lat : natural := 100; -- Maximum number of allowable latency changes.
signal sig_poa_adjust_count : integer range 0 to 2**8 - 1;
signal sig_poa_state : t_poa_state;
begin
poa_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_poa_ack <= '0';
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
sig_poa_adjust_count <= 0;
sig_poa_state <= s_poa_rewind_to_pass;
elsif rising_edge(clk) then
sig_poa_ack <= '0';
seq_poa_lat_inc_1x <= (others => '0');
seq_poa_lat_dec_1x <= (others => '0');
if sig_dgrb_state = s_poa_cal then
case sig_poa_state is
when s_poa_rewind_to_pass =>
-- In postamble calibration
--
-- Normally, must wait for sig_dimm_driving_dq to be '1'
-- before reading, but by this point in calibration
-- rdata_valid is assumed to be set up properly. The
-- sig_poa_match_en (derived from rdata_valid) is used
-- here rather than sig_dimm_driving_dq.
if sig_poa_match_en = '1' then
if sig_poa_match = '1' then
sig_poa_state <= s_poa_done;
else
seq_poa_lat_dec_1x <= (others => '1');
end if;
sig_poa_adjust_count <= sig_poa_adjust_count + 1;
end if;
when s_poa_done =>
sig_poa_ack <= '1';
end case;
else
sig_poa_state <= s_poa_rewind_to_pass;
sig_poa_adjust_count <= 0;
end if;
assert sig_poa_adjust_count <= c_poa_max_lat
report dgrb_report_prefix & "Maximum number of postamble latency adjustments exceeded."
severity failure;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- code block for tracking signal generation
--
-- this is used for initial tracking setup (finding a reference window)
-- and periodic tracking operations (PVT compensation on rsc phase)
--
-- A slave trk state machine is described and implemented within the block
-- The mimic path is controlled within this block
-- ------------------------------------------------------------------
trk_block : block
type t_tracking_state is (
-- initialise variables out of reset
s_trk_init,
-- idle state
s_trk_idle,
-- sample data from the mimic path (build window)
s_trk_mimic_sample,
-- 'shift' mimic path phase
s_trk_next_phase,
-- calculate mimic window
s_trk_cdvw_calc,
s_trk_cdvw_wait, -- for results
-- calculate how much mimic window has moved (only entered in periodic tracking)
s_trk_cdvw_drift,
-- track rsc phase (only entered in periodic tracking)
s_trk_adjust_resync,
-- communicate command complete to the master state machine
s_trk_complete
);
signal sig_mmc_seq_done : std_logic;
signal sig_mmc_seq_done_1t : std_logic;
signal mmc_seq_value_r : std_logic;
signal sig_mmc_start : std_logic;
signal sig_trk_state : t_tracking_state;
signal sig_trk_last_state : t_tracking_state;
signal sig_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
signal sig_req_rsc_shift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores required shift in rsc phase instantaneously
signal sig_mimic_cdv_found : std_logic;
signal sig_mimic_cdv : integer range 0 to PLL_STEPS_PER_CYCLE; -- centre of data valid window calculated from first mimic-cycle
signal sig_mimic_delta : integer range -PLL_STEPS_PER_CYCLE to PLL_STEPS_PER_CYCLE;
signal sig_large_drift_seen : std_logic;
signal sig_remaining_samples : natural range 0 to 2**8 - 1;
begin
-- advertise the codvw phase shift
process (clk, rst_n)
variable v_length : integer;
begin
if rst_n = '0' then
codvw_trk_shift <= (others => '0');
elsif rising_edge(clk) then
if sig_mimic_cdv_found = '1' then
-- check range
v_length := codvw_trk_shift'length;
codvw_trk_shift <= std_logic_vector(to_signed(sig_rsc_drift, v_length));
else
codvw_trk_shift <= (others => '0');
end if;
end if;
end process;
-- request a mimic sample
mimic_sample_req : process (clk, rst_n)
variable seq_mmc_start_r : std_logic_vector(3 downto 0);
begin
if rst_n = '0' then
seq_mmc_start <= '0';
seq_mmc_start_r := "0000";
elsif rising_edge(clk) then
seq_mmc_start_r(3) := seq_mmc_start_r(2);
seq_mmc_start_r(2) := seq_mmc_start_r(1);
seq_mmc_start_r(1) := seq_mmc_start_r(0);
-- extend sig_mmc_start by one clock cycle
if sig_mmc_start = '1' then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '1';
elsif ( (seq_mmc_start_r(3) = '1') or (seq_mmc_start_r(2) = '1') or (seq_mmc_start_r(1) = '1') or (seq_mmc_start_r(0) = '1') ) then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '0';
else
seq_mmc_start <= '0';
end if;
end if;
end process;
-- metastability hardening of async mmc_seq_done signal
mmc_seq_req_sync : process (clk, rst_n)
variable v_mmc_seq_done_1r : std_logic;
variable v_mmc_seq_done_2r : std_logic;
variable v_mmc_seq_done_3r : std_logic;
begin
if rst_n = '0' then
sig_mmc_seq_done <= '0';
sig_mmc_seq_done_1t <= '0';
v_mmc_seq_done_1r := '0';
v_mmc_seq_done_2r := '0';
v_mmc_seq_done_3r := '0';
elsif rising_edge(clk) then
sig_mmc_seq_done_1t <= v_mmc_seq_done_3r;
sig_mmc_seq_done <= v_mmc_seq_done_2r;
mmc_seq_value_r <= mmc_seq_value;
v_mmc_seq_done_3r := v_mmc_seq_done_2r;
v_mmc_seq_done_2r := v_mmc_seq_done_1r;
v_mmc_seq_done_1r := mmc_seq_done;
end if;
end process;
-- collect mimic samples as they arrive
shift_in_mmc_seq_value : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
elsif rising_edge(clk) then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
sig_trk_cdvw_shift_in <= '1';
sig_trk_cdvw_phase <= mmc_seq_value_r;
end if;
end if;
end process;
-- main tracking state machine
trk_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_state <= s_trk_init;
sig_trk_last_state <= s_trk_init;
sig_trk_result <= (others => '0');
sig_trk_err <= '0';
sig_mmc_start <= '0';
sig_trk_pll_select <= (others => '0');
sig_req_rsc_shift <= -c_max_rsc_drift_in_phases;
sig_rsc_drift <= -c_max_rsc_drift_in_phases;
sig_mimic_delta <= -PLL_STEPS_PER_CYCLE;
sig_mimic_cdv_found <= '0';
sig_mimic_cdv <= 0;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_remaining_samples <= 0;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_trk_ack <= '0';
elsif rising_edge(clk) then
sig_trk_pll_select <= pll_measure_clk_index;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_trk_ack <= '0';
sig_trk_err <= '0';
sig_trk_result <= (others => '0');
sig_mmc_start <= '0';
-- if no cdv found then reset tracking results
if sig_mimic_cdv_found = '0' then
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
end if;
if sig_dgrb_state = s_track then
-- resync state machine
case sig_trk_state is
when s_trk_init =>
sig_trk_state <= s_trk_idle;
sig_mimic_cdv_found <= '0';
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
when s_trk_idle =>
sig_remaining_samples <= PLL_STEPS_PER_CYCLE; -- ensure a 360 degrees sweep
sig_trk_state <= s_trk_mimic_sample;
when s_trk_mimic_sample =>
if sig_remaining_samples = 0 then
sig_trk_state <= s_trk_cdvw_calc;
else
if sig_trk_state /= sig_trk_last_state then
-- request a sample as soon as we arrive in this state.
-- the default value of sig_mmc_start is zero!
sig_mmc_start <= '1';
end if;
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
-- a sample has been collected, go to next PLL phase
sig_remaining_samples <= sig_remaining_samples - 1;
sig_trk_state <= s_trk_next_phase;
end if;
end if;
when s_trk_next_phase =>
sig_trk_pll_start_reconfig <= '1';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_mimic_sample;
end if;
when s_trk_cdvw_calc =>
if sig_trk_state /= sig_trk_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_trk_cdvw_calc <= '1';
report dgrb_report_prefix & "gathered mimic phase samples DGRB_MIMIC_SAMPLES: " & str(sig_cdvw_state.working_window(sig_cdvw_state.working_window'high downto sig_cdvw_state.working_window'length - PLL_STEPS_PER_CYCLE)) severity note;
else
sig_trk_state <= s_trk_cdvw_wait;
end if;
when s_trk_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
if sig_cdvw_state.status = valid_result then
report dgrb_report_prefix & "mimic window successfully found." severity note;
if sig_mimic_cdv_found = '0' then -- first run of tracking operation
sig_mimic_cdv_found <= '1';
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_complete;
else -- subsequent tracking operation runs
sig_mimic_delta <= sig_mimic_cdv - sig_cdvw_state.largest_window_centre;
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_cdvw_drift;
end if;
else
report dgrb_report_prefix & "couldn't find a data-valid window for tracking." severity cal_fail_sev_level;
sig_trk_ack <= '1';
sig_trk_err <= '1';
sig_trk_state <= s_trk_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_INVALID_PHASES, sig_trk_result'length));
when multiple_equal_windows =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_trk_result'length));
when no_valid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_trk_result'length));
when others =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_trk_result'length));
end case;
end if;
end if;
when s_trk_cdvw_drift => -- calculate the drift in rsc phase
-- pipeline stage 1
if abs(sig_mimic_delta) > PLL_STEPS_PER_CYCLE/2 then
sig_large_drift_seen <= '1';
else
sig_large_drift_seen <= '0';
end if;
--pipeline stage 2
if sig_trk_state = sig_trk_last_state then
if sig_large_drift_seen = '1' then
if sig_mimic_delta < 0 then -- anti-clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta + PLL_STEPS_PER_CYCLE;
else -- clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta - PLL_STEPS_PER_CYCLE;
end if;
else
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta;
end if;
sig_trk_state <= s_trk_adjust_resync;
end if;
when s_trk_adjust_resync =>
sig_trk_pll_select <= pll_resync_clk_index;
sig_trk_pll_start_reconfig <= '1';
if sig_trk_state /= sig_trk_last_state then
if sig_req_rsc_shift < 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_req_rsc_shift <= sig_req_rsc_shift + 1;
sig_rsc_drift <= sig_rsc_drift + 1;
elsif sig_req_rsc_shift > 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_dec;
sig_req_rsc_shift <= sig_req_rsc_shift - 1;
sig_rsc_drift <= sig_rsc_drift - 1;
else
sig_trk_state <= s_trk_complete;
sig_trk_pll_start_reconfig <= '0';
end if;
else
sig_trk_pll_inc_dec_n <= sig_trk_pll_inc_dec_n; -- maintain current value
end if;
if abs(sig_rsc_drift) = c_max_rsc_drift_in_phases then
report dgrb_report_prefix & " a maximum absolute change in resync_clk of " & integer'image(sig_rsc_drift) & " phases has " & LF &
" occurred (since read resynch phase calibration) during tracking" severity cal_fail_sev_level;
sig_trk_err <= '1';
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_MAX_TRK_SHFT_EXCEEDED, sig_trk_result'length));
end if;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_complete;
end if;
when s_trk_complete =>
sig_trk_ack <= '1';
end case;
sig_trk_last_state <= sig_trk_state;
else
sig_trk_state <= s_trk_idle;
sig_trk_last_state <= s_trk_idle;
end if;
end if;
end process;
rsc_drift: process (sig_rsc_drift)
begin
sig_trk_rsc_drift <= sig_rsc_drift; -- communicate tracking shift to rsc process
end process;
end block; -- tracking signals
-- ------------------------------------------------------------------
-- write-datapath (WDP) ` and on-chip-termination (OCT) signal
-- ------------------------------------------------------------------
wdp_oct : process(clk,rst_n)
begin
if rst_n = '0' then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
elsif rising_edge(clk) then
if ((sig_dgrb_state = s_idle) or (EN_OCT = 0)) then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
else
seq_oct_value <= c_set_oct_to_rt;
dgrb_wdp_ovride <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- handles muxing of error codes to the control block
-- ------------------------------------------------------------------
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgrb_ctrl <= defaults;
elsif rising_edge(clk) then
dgrb_ctrl <= defaults;
if sig_dgrb_state = s_wait_admin and sig_dgrb_last_state = s_idle then
dgrb_ctrl.command_ack <= '1';
end if;
case sig_dgrb_state is
when s_seek_cdvw =>
dgrb_ctrl.command_err <= sig_rsc_err;
dgrb_ctrl.command_result <= sig_rsc_result;
when s_track =>
dgrb_ctrl.command_err <= sig_trk_err;
dgrb_ctrl.command_result <= sig_trk_result;
when others => -- from main state machine
dgrb_ctrl.command_err <= sig_cmd_err;
dgrb_ctrl.command_result <= sig_cmd_result;
end case;
if ctrl_dgrb_r.command = cmd_read_mtp then -- check against command because aligned with command done not command_err
dgrb_ctrl.command_err <= '0';
dgrb_ctrl.command_result <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size,dgrb_ctrl.command_result'length));
end if;
if sig_dgrb_state = s_idle and sig_dgrb_last_state = s_release_admin then
dgrb_ctrl.command_done <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- address/command state machine
-- process is commanded to begin reading training patterns.
--
-- implements the address/command slave state machine
-- issues read commands to the memory relative to given calibration
-- stage being implemented
-- burst length is dependent on memory type
-- ------------------------------------------------------------------
ac_block : block
-- override the calibration burst length for DDR3 device support
-- (requires BL8 / on the fly setting in MR in admin block)
function set_read_bl ( memtype: in string ) return natural is
begin
if memtype = "DDR3" then
return 8;
elsif memtype = "DDR" or memtype = "DDR2" then
return c_cal_burst_len;
else
report dgrb_report_prefix & " a calibration burst length choice has not been set for memory type " & memtype severity failure;
end if;
return 0;
end function;
-- parameterisation of the read algorithm by burst length
constant c_poa_addr_width : natural := 6;
constant c_cal_read_burst_len : natural := set_read_bl(MEM_IF_MEMTYPE);
constant c_bursts_per_btp : natural := c_cal_mtp_len / c_cal_read_burst_len;
constant c_read_burst_t : natural := c_cal_read_burst_len / DWIDTH_RATIO;
constant c_max_rdata_valid_lat : natural := 50*(c_cal_read_burst_len / DWIDTH_RATIO); -- maximum latency that rdata_valid can ever have with respect to doing_rd
constant c_rdv_ones_rd_clks : natural := (c_max_rdata_valid_lat + c_read_burst_t) / c_read_burst_t; -- number of cycles to read ones for before a pulse of zeros
-- array of burst training pattern addresses
-- here the MTP is used in this addressing
subtype t_btp_addr is natural range 0 to 2 ** MEM_IF_ADDR_WIDTH - 1;
type t_btp_addr_array is array (0 to c_bursts_per_btp - 1) of t_btp_addr;
-- default values
function defaults return t_btp_addr_array is
variable v_btp_array : t_btp_addr_array;
begin
for i in 0 to c_bursts_per_btp - 1 loop
v_btp_array(i) := 0;
end loop;
return v_btp_array;
end function;
-- load btp array addresses
-- Note: this scales to burst lengths of 2, 4 and 8
-- the settings here are specific to the choice of training pattern and need updating if the pattern changes
function set_btp_addr (mtp_almt : natural ) return t_btp_addr_array is
variable v_addr_array : t_btp_addr_array;
begin
for i in 0 to 8/c_cal_read_burst_len - 1 loop
-- set addresses for xF5 data
v_addr_array((c_bursts_per_btp - 1) - i) := MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + i*c_cal_read_burst_len;
-- set addresses for x30 data (based on mtp alignment)
if mtp_almt = 0 then
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + i*c_cal_read_burst_len;
else
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + i*c_cal_read_burst_len;
end if;
end loop;
return v_addr_array;
end function;
function find_poa_cycle_period return natural is
-- Returns the period over which the postamble reads
-- repeat in c_read_burst_t units.
variable v_num_bursts : natural;
begin
v_num_bursts := 2 ** c_poa_addr_width / c_read_burst_t;
if v_num_bursts * c_read_burst_t < 2**c_poa_addr_width then
v_num_bursts := v_num_bursts + 1;
end if;
v_num_bursts := v_num_bursts + c_bursts_per_btp + 1;
return v_num_bursts;
end function;
function get_poa_burst_addr(burst_count : in natural; mtp_almt : in natural) return t_btp_addr is
variable v_addr : t_btp_addr;
begin
if burst_count = 0 then
if mtp_almt = 0 then
v_addr := c_cal_ofs_x30_almt_1;
elsif mtp_almt = 1 then
v_addr := c_cal_ofs_x30_almt_0;
else
report "Unsupported mtp_almt " & natural'image(mtp_almt) severity failure;
end if;
-- address gets incremented by four if in burst-length four.
v_addr := v_addr + (8 - c_cal_read_burst_len);
else
v_addr := c_cal_ofs_zeros;
end if;
return v_addr;
end function;
signal btp_addr_array : t_btp_addr_array; -- burst training pattern addresses
signal sig_addr_cmd_state : t_ac_state;
signal sig_addr_cmd_last_state : t_ac_state;
signal sig_doing_rd_count : integer range 0 to c_read_burst_t - 1;
signal sig_count : integer range 0 to 2**8 - 1;
signal sig_setup : integer range c_max_read_lat downto 0;
signal sig_burst_count : integer range 0 to c_read_burst_t;
begin
-- handles counts for when to begin burst-reads (sig_burst_count)
-- sets sig_dimm_driving_dq
-- sets dgrb_ac_access_req
dimm_driving_dq_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dimm_driving_dq <= '1';
sig_setup <= c_max_read_lat;
sig_burst_count <= 0;
dgrb_ac_access_req <= '0';
sig_ac_even <= '0';
elsif rising_edge(clk) then
sig_dimm_driving_dq <= '0';
if sig_addr_cmd_state /= s_ac_idle and sig_addr_cmd_state /= s_ac_relax then
dgrb_ac_access_req <= '1';
else
dgrb_ac_access_req <= '0';
end if;
case sig_addr_cmd_state is
when s_ac_read_mtp | s_ac_read_rdv | s_ac_read_wd_lat | s_ac_read_poa_mtp =>
sig_ac_even <= not sig_ac_even;
-- a counter that keeps track of when we are ready
-- to issue a burst read. Issue burst read eigvery
-- time we are at zero.
if sig_burst_count = 0 then
sig_burst_count <= c_read_burst_t - 1;
else
sig_burst_count <= sig_burst_count - 1;
end if;
if dgrb_ac_access_gnt /= '1' then
sig_setup <= c_max_read_lat;
else
-- primes reads
-- signal that dimms are driving dq pins after
-- at least c_max_read_lat clock cycles have passed.
--
if sig_setup = 0 then
sig_dimm_driving_dq <= '1';
elsif dgrb_ac_access_gnt = '1' then
sig_setup <= sig_setup - 1;
end if;
end if;
when s_ac_relax =>
sig_dimm_driving_dq <= '1';
sig_burst_count <= 0;
sig_ac_even <= '0';
when others =>
sig_burst_count <= 0;
sig_ac_even <= '0';
end case;
end if;
end process;
ac_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_count <= 0;
sig_addr_cmd_state <= s_ac_idle;
sig_addr_cmd_last_state <= s_ac_idle;
sig_doing_rd_count <= 0;
sig_addr_cmd <= reset(c_seq_addr_cmd_config);
btp_addr_array <= defaults;
sig_doing_rd <= (others => '0');
elsif rising_edge(clk) then
assert c_cal_mtp_len mod c_cal_read_burst_len = 0 report dgrb_report_prefix & "burst-training pattern length must be a multiple of burst-length." severity failure;
assert MEM_IF_CAL_BANK < 2**MEM_IF_BANKADDR_WIDTH report dgrb_report_prefix & "MEM_IF_CAL_BANK out of range." severity failure;
assert MEM_IF_CAL_BASE_COL < 2**MEM_IF_ADDR_WIDTH - 1 - C_CAL_DATA_LEN report dgrb_report_prefix & "MEM_IF_CAL_BASE_COL out of range." severity failure;
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
if sig_ac_req /= sig_addr_cmd_state and sig_addr_cmd_state /= s_ac_idle then
-- and dgrb_ac_access_gnt = '1'
sig_addr_cmd_state <= s_ac_relax;
else
sig_addr_cmd_state <= sig_ac_req;
end if;
if sig_doing_rd_count /= 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= sig_doing_rd_count - 1;
else
sig_doing_rd <= (others => '0');
end if;
case sig_addr_cmd_state is
when s_ac_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
when s_ac_relax =>
-- waits at least c_max_read_lat before returning to s_ac_idle state
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_max_read_lat;
else
if sig_count = 0 then
sig_addr_cmd_state <= s_ac_idle;
else
sig_count <= sig_count - 1;
end if;
end if;
when s_ac_read_mtp =>
-- reads 'more'-training pattern
-- issue read commands for proper addresses
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_bursts_per_btp - 1; -- counts number of bursts in a training pattern
else
sig_doing_rd <= (others => '1');
-- issue a read command every c_read_burst_t clock cycles
if sig_burst_count = 0 then
-- decide which read command to issue
for i in 0 to c_bursts_per_btp - 1 loop
if sig_count = i then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
btp_addr_array(i), -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
end if;
end loop;
-- Set next value of count
if sig_count = 0 then
sig_count <= c_bursts_per_btp - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_poa_mtp =>
-- Postamble rdata/rdata_valid Activity:
--
--
-- (0) (1) (2)
-- ; ; ; ;
-- _________ __ ____________ _____________ _______ _________
-- \ / \ / \ \ \ / \ /
-- (a) rdata[0] 00000000 X 11 X 0000000000 / / 0000000000 X MTP X 00000000
-- _________/ \__/ \____________\ \____________/ \_______/ \_________
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- rdata_valid ____| |_____________\ \_____________| |__________
--
-- ;<- (b) ->;<------------(c)------------>; ;
-- ; ; ; ;
--
--
-- This block must issue reads and drive doing_rd to place the above pattern on
-- the rdata and rdata_valid ports. MTP will most likely come back corrupted but
-- the postamble block (poa_block) will make the necessary adjustments to improve
-- matters.
--
-- (a) Read zeros followed by two ones. The two will be at the end of a burst.
-- Assert rdata_valid only during the burst containing the ones.
-- (b) c_read_burst_t clock cycles.
-- (c) Must be greater than but NOT equal to maximum postamble latency clock
-- cycles. Another way: c_min = (max_poa_lat + 1) phy clock cycles. This
-- must also be long enough to allow the postamble block to respond to a
-- the seq_poa_lat_dec_1x signal, but this requirement is less stringent
-- than the first so that we can ignore it.
--
-- The find_poa_cycle_period function should return (b+c)/c_read_burst_t
-- rounded up to the next largest integer.
--
--
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
-- issue read commands for proper addresses
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= find_poa_cycle_period - 1; -- length of read patter in bursts.
elsif dgrb_ac_access_gnt = '1' then
-- only begin operation once dgrb_ac_access_gnt has been issued
-- otherwise rdata_valid may be asserted when rdasta is not
-- valid.
--
-- *** WARNING: BE SAFE. DON'T LET THIS HAPPEN TO YOU: ***
--
-- ; ; ; ; ; ;
-- ; _______ ; ; _______ ; ; _______
-- XXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX
-- addr/cmd XXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ; _______
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX / \
-- rdata XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX MTP X
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- doing_rd ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- __________________________________________________
-- ac_accesss_gnt ______________|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________
-- rdata_valid __________________________________| |_________| |
-- ; ; ; ; ; ;
--
-- (0) (1) (2)
--
--
-- Cmmand and doing_rd issued at (0). The doing_rd signal enters the
-- rdata_valid pipe here so that it will return on rdata_valid with the
-- expected latency (at this point in calibration, rdata_valid and adv_rd_lat
-- should be properly calibrated). Unlike doing_rd, since ac_access_gnt is not
-- asserted the READ command at (0) is never actually issued. This results
-- in the situation at (2) where rdata is undefined yet rdata_valid indicates
-- valid data. The moral of this story is to wait for ac_access_gnt = '1'
-- before issuing commands when it is important that rdata_valid be accurate.
--
--
--
--
if sig_burst_count = 0 then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
get_poa_burst_addr(sig_count, current_mtp_almt),-- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
-- Set doing_rd
if sig_count = 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= c_read_burst_t - 1; -- Extend doing_rd pulse by this many phy_clk cycles.
end if;
-- Set next value of count
if sig_count = 0 then
sig_count <= find_poa_cycle_period - 1; -- read for one period then relax (no read) for same time period
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_rdv =>
assert c_max_rdata_valid_lat mod c_read_burst_t = 0 report dgrb_report_prefix & "c_max_rdata_valid_lat must be a multiple of c_read_burst_t." severity failure;
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_rdv_ones_rd_clks - 1;
else
if sig_burst_count = 0 then
if sig_count = 0 then
-- expecting to read ZEROS
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous valid
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ZEROS, -- column
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
else
-- expecting to read ONES
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ONES, -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- op length
false);
end if;
if sig_count = 0 then
sig_count <= c_rdv_ones_rd_clks - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
if (sig_count = c_rdv_ones_rd_clks - 1 and sig_burst_count = 1) or
(sig_count = 0 and c_read_burst_t = 1) then
-- the last burst read- that was issued was supposed to read only zeros
-- a burst read command will be issued on the next clock cycle
--
-- A long (>= maximim rdata_valid latency) series of burst reads are
-- issued for ONES.
-- Into this stream a single burst read for ZEROs is issued. After
-- the ZERO read command is issued, rdata_valid needs to come back
-- high one clock cycle before the next read command (reading ONES
-- again) is issued. Since the rdata_valid is just a delayed
-- version of doing_rd, doing_rd needs to exhibit the same behaviour.
--
-- for FR (burst length 4): require that doing_rd high 1 clock cycle after cs_n is low
-- ____ ____ ____ ____ ____ ____ ____ ____ ____
-- clk ____| |____| |____| |____| |____| |____| |____| |____| |____|
--
-- ___ _______ _______ _______ _______
-- \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXX
-- addr XXXXXXXXXXX ONES XXXXXXXXXXX ONES XXXXXXXXXXX ZEROS XXXXXXXXXXX ONES XXXXX--> Repeat
-- ___/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXX
--
-- _________ _________ _________ _________ ____
-- cs_n ____| |_________| |_________| |_________| |_________|
--
-- _________
-- doing_rd ________________________________________________________________| |______________
--
--
-- for HR: require that doing_rd high in the same clock cycle as cs_n is low
--
sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) <= '1';
end if;
end if;
when s_ac_read_wd_lat =>
-- continuously issues reads on the memory locations
-- containing write latency addr=[2*c_cal_burst_len - (3*c_cal_burst_len - 1)]
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
-- no initialization required here. Must still wait
-- a clock cycle before beginning operations so that
-- we are properly synchronized with
-- dimm_driving_dq_proc.
else
if sig_burst_count = 0 then
if sig_dimm_driving_dq = '1' then
sig_doing_rd <= (others => '1');
end if;
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- column
2**current_cs, -- rank
c_cal_read_burst_len,
false);
end if;
end if;
when others =>
report dgrb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_addr_cmd_state <= s_ac_idle;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).read;
end loop;
sig_addr_cmd_last_state <= sig_addr_cmd_state;
end if;
end process;
end block ac_block;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (write bias) [dgwb] block for the non-levelling
-- AFI PHY sequencer
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_dgwb is
generic (
-- Physical IF width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
DWIDTH_RATIO : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural; -- The sequencer outputs memory control signals of width num_ranks
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
-- Base column address to which calibration data is written.
-- Memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data.
MEM_IF_CAL_BASE_COL : natural
);
port (
-- CLK Reset
clk : in std_logic;
rst_n : in std_logic;
parameterisation_rec : in t_algm_paramaterisation;
-- Control interface :
dgwb_ctrl : out t_ctrl_stat;
ctrl_dgwb : in t_ctrl_command;
-- iRAM 'push' interface :
dgwb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- Admin block req/gnt interface.
dgwb_ac_access_req : out std_logic;
dgwb_ac_access_gnt : in std_logic;
-- WDP interface
dgwb_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
dgwb_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
dgwb_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
dgwb_wdp_ovride : out std_logic;
-- addr/cmd output for write commands.
dgwb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
bypassed_rdata : in std_logic_vector(MEM_IF_DWIDTH-1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1)
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
--
architecture rtl of ddr_ctrl_ip_phy_alt_mem_phy_dgwb is
type t_dgwb_state is (
s_idle,
s_wait_admin,
s_write_btp, -- Writes bit-training pattern
s_write_ones, -- Writes ones
s_write_zeros, -- Writes zeros
s_write_mtp, -- Write more training patterns (requires read to check allignment)
s_write_01_pairs, -- Writes 01 pairs
s_write_1100_step,-- Write step function (half zeros, half ones)
s_write_0011_step,-- Write reversed step function (half ones, half zeros)
s_write_wlat, -- Writes the write latency into a memory address.
s_release_admin
);
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgwb_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (dgwb) : ";
function dqs_pattern return std_logic_vector is
variable dqs : std_logic_vector( DWIDTH_RATIO - 1 downto 0);
begin
if DWIDTH_RATIO = 2 then
dqs := "10";
elsif DWIDTH_RATIO = 4 then
dqs := "1100";
else
report dgwb_report_prefix & "unsupported DWIDTH_RATIO in function dqs_pattern." severity failure;
end if;
return dqs;
end;
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_dgwb_state : t_dgwb_state;
signal sig_dgwb_last_state : t_dgwb_state;
signal access_complete : std_logic;
signal generate_wdata : std_logic; -- for s_write_wlat only
-- current chip select being processed
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS-1;
begin
dgwb_ac <= sig_addr_cmd;
-- Set IRAM interface to defaults
dgwb_iram <= defaults;
-- Master state machine. Generates state transitions.
master_dgwb_state_block : if True generate
signal sig_ctrl_dgwb : t_ctrl_command; -- registers ctrl_dgwb input.
begin
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if sig_ctrl_dgwb.command_req = '1' then
current_cs <= sig_ctrl_dgwb.command_op.current_cs;
end if;
end if;
end process;
master_dgwb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dgwb_state <= s_idle;
sig_dgwb_last_state <= s_idle;
sig_ctrl_dgwb <= defaults;
elsif rising_edge(clk) then
case sig_dgwb_state is
when s_idle =>
if sig_ctrl_dgwb.command_req = '1' then
if (curr_active_block(sig_ctrl_dgwb.command) = dgwb) then
sig_dgwb_state <= s_wait_admin;
end if;
end if;
when s_wait_admin =>
case sig_ctrl_dgwb.command is
when cmd_write_btp => sig_dgwb_state <= s_write_btp;
when cmd_write_mtp => sig_dgwb_state <= s_write_mtp;
when cmd_was => sig_dgwb_state <= s_write_wlat;
when others =>
report dgwb_report_prefix & "unknown command" severity error;
end case;
if dgwb_ac_access_gnt /= '1' then
sig_dgwb_state <= s_wait_admin;
end if;
when s_write_btp =>
sig_dgwb_state <= s_write_zeros;
when s_write_zeros =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_ones;
end if;
when s_write_ones =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_mtp =>
sig_dgwb_state <= s_write_01_pairs;
when s_write_01_pairs =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_1100_step;
end if;
when s_write_1100_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_0011_step;
end if;
when s_write_0011_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_wlat =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_release_admin =>
if dgwb_ac_access_gnt = '0' then
sig_dgwb_state <= s_idle;
end if;
when others =>
report dgwb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_dgwb_state <= s_idle;
end case;
sig_dgwb_last_state <= sig_dgwb_state;
sig_ctrl_dgwb <= ctrl_dgwb;
end if;
end process;
end generate;
-- Generates writes
ac_write_block : if True generate
constant C_BURST_T : natural := C_CAL_BURST_LEN / DWIDTH_RATIO; -- Number of phy-clock cycles per burst
constant C_MAX_WLAT : natural := 2**ADV_LAT_WIDTH-1; -- Maximum latency in clock cycles
constant C_MAX_COUNT : natural := C_MAX_WLAT + C_BURST_T + 4*12 - 1; -- up to 12 consecutive writes at 4 cycle intervals
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgwb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
constant C_WLAT_DQ_REP_WIDTH : natural := set_wlat_dq_rep_width;
signal sig_count : natural range 0 to 2**8 - 1;
begin
ac_write_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
generate_wdata <= '0'; -- for s_write_wlat only
sig_count <= 0;
sig_addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
access_complete <= '0';
elsif rising_edge(clk) then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
access_complete <= '0';
generate_wdata <= '0'; -- for s_write_wlat only
case sig_dgwb_state is
when s_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
-- require ones in locations:
-- 1. c_cal_ofs_ones (8 locations)
-- 2. 2nd half of location c_cal_ofs_xF5 (4 locations)
when s_write_ones =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ONES to DQ pins
dgwb_wdata <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
-- ensure safe intervals for DDRx memory writes (min 4 mem clk cycles between writes for BC4 DDR3)
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require zeros in locations:
-- 1. c_cal_ofs_zeros (8 locations)
-- 2. 1st half of c_cal_ofs_x30_almt_0 (4 locations)
-- 3. 1st half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_zeros =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ZEROS to DQ pins
dgwb_wdata <= (others => '0');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 12 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require 0101 pattern in locations:
-- 1. 1st half of location c_cal_ofs_xF5 (4 locations)
when s_write_01_pairs =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 01 to pairs of memory addresses
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if i mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
-- require pattern "0011" (or "1100") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_0 (4 locations)
when s_write_0011_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 0011 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
-- this calculation has 2 parts:
-- a) sig_count mod C_BURST_T is a timewise iterator of repetition of the pattern
-- b) i represents the temporal iterator of the pattern
-- it is required to sum a and b and switch the pattern between 0 and 1 every 2 locations in each dimension
-- Note: the same formulae is used below for the 1100 pattern
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
end if;
end loop;
-- require pattern "1100" (or "0011") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_1100_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 1100 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
when s_write_wlat =>
-- Effect:
-- *Writes the memory latency to an array formed
-- from memory addr=[2*C_CAL_BURST_LEN-(3*C_CAL_BURST_LEN-1)].
-- The write latency is written to pairs of addresses
-- across the given range.
--
-- Example
-- C_CAL_BURST_LEN = 4
-- addr 8 - 9 [WLAT] size = 2*MEM_IF_DWIDTH bits
-- addr 10 - 11 [WLAT] size = 2*MEM_IF_DWIDTH bits
--
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config, -- A/C configuration
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- address
2**current_cs, -- rank
8, -- burst length (8 for DDR3 and 4 for DDR/DDR2)
false); -- auto-precharge
sig_count <= 0;
else
-- hold wdata_valid and wdata 2 clock cycles
-- 1 - because ac signal registered at top level of sequencer
-- 2 - because want time to dqs_burst edge which occurs 1 cycle earlier
-- than wdata_valid in an AFI compliant controller
generate_wdata <= '1';
end if;
if generate_wdata = '1' then
for i in 0 to dgwb_wdata'length/C_WLAT_DQ_REP_WIDTH - 1 loop
dgwb_wdata((i+1)*C_WLAT_DQ_REP_WIDTH - 1 downto i*C_WLAT_DQ_REP_WIDTH) <= std_logic_vector(to_unsigned(sig_count, C_WLAT_DQ_REP_WIDTH));
end loop;
-- delay by 1 clock cycle to account for 1 cycle discrepancy
-- between dqs_burst and wdata_valid
if sig_count = C_MAX_COUNT then
access_complete <= '1';
end if;
sig_count <= sig_count + 1;
end if;
when others =>
null;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).write;
end loop;
end if;
end process;
end generate;
-- Handles handshaking for access to address/command
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
elsif rising_edge(clk) then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
if sig_dgwb_state /= s_idle and sig_dgwb_state /= s_release_admin then
dgwb_ac_access_req <= '1';
elsif sig_dgwb_state = s_idle or sig_dgwb_state = s_release_admin then
dgwb_ac_access_req <= '0';
else
report dgwb_report_prefix & "unexpected state in ac_handshake_proc so haven't requested access to address/command." severity warning;
end if;
if sig_dgwb_state = s_wait_admin and sig_dgwb_last_state = s_idle then
dgwb_ctrl.command_ack <= '1';
end if;
if sig_dgwb_state = s_idle and sig_dgwb_last_state = s_release_admin then
dgwb_ctrl.command_done <= '1';
end if;
end if;
end process;
end architecture rtl;
--
-- -----------------------------------------------------------------------------
-- Abstract : ctrl block for the non-levelling AFI PHY sequencer
-- This block is the central control unit for the sequencer. The method
-- of control is to issue commands (prefixed cmd_) to each of the other
-- sequencer blocks to execute. Each command corresponds to a stage of
-- the AFI PHY calibaration stage, and in turn each state represents a
-- command or a supplimentary flow control operation. In addition to
-- controlling the sequencer this block also checks for time out
-- conditions which occur when a different system block is faulty.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_ctrl is
generic (
FAMILYGROUP_ID : natural;
MEM_IF_DLL_LOCK_COUNT : natural;
MEM_IF_MEMTYPE : string;
DWIDTH_RATIO : natural;
IRAM_ADDRESSING : t_base_hdr_addresses;
MEM_IF_CLK_PS : natural;
TRACKING_INTERVAL_IN_MS : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_DQS_WIDTH : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 1 skip rrp, if 2 rrp for 1 dqs group and 1 cs
ACK_SEVERITY : severity_level
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and redo request
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_recalibrate_req : in std_logic; -- acts as a synchronous reset
-- status signals from iram
iram_status : in t_iram_stat;
iram_push_done : in std_logic;
-- standard control signal to all blocks
ctrl_op_rec : out t_ctrl_command;
-- standardised response from all system blocks
admin_ctrl : in t_ctrl_stat;
dgrb_ctrl : in t_ctrl_stat;
dgwb_ctrl : in t_ctrl_stat;
-- mmi to ctrl interface
mmi_ctrl : in t_mmi_ctrl;
ctrl_mmi : out t_ctrl_mmi;
-- byte lane select
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- signals to control the ac_nt setting
dgrb_ctrl_ac_nt_good : in std_logic;
int_ac_nt : out std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0); -- width of 1 for DWIDTH_RATIO =2,4 and 2 for DWIDTH_RATIO = 8
-- the following signals are reserved for future use
ctrl_iram_push : out t_ctrl_iram
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_ctrl is
-- a prefix for all report signals to identify phy and sequencer block
--
constant ctrl_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (ctrl) : ";
-- decoder to find the relevant disable bit (from mmi registers) for a given state
function find_dis_bit
(
state : t_master_sm_state;
mmi_ctrl : t_mmi_ctrl
) return std_logic is
variable v_dis : std_logic;
begin
case state is
when s_phy_initialise => v_dis := mmi_ctrl.hl_css.phy_initialise_dis;
when s_init_dram |
s_prog_cal_mr => v_dis := mmi_ctrl.hl_css.init_dram_dis;
when s_write_ihi => v_dis := mmi_ctrl.hl_css.write_ihi_dis;
when s_cal => v_dis := mmi_ctrl.hl_css.cal_dis;
when s_write_btp => v_dis := mmi_ctrl.hl_css.write_btp_dis;
when s_write_mtp => v_dis := mmi_ctrl.hl_css.write_mtp_dis;
when s_read_mtp => v_dis := mmi_ctrl.hl_css.read_mtp_dis;
when s_rrp_reset => v_dis := mmi_ctrl.hl_css.rrp_reset_dis;
when s_rrp_sweep => v_dis := mmi_ctrl.hl_css.rrp_sweep_dis;
when s_rrp_seek => v_dis := mmi_ctrl.hl_css.rrp_seek_dis;
when s_rdv => v_dis := mmi_ctrl.hl_css.rdv_dis;
when s_poa => v_dis := mmi_ctrl.hl_css.poa_dis;
when s_was => v_dis := mmi_ctrl.hl_css.was_dis;
when s_adv_rd_lat => v_dis := mmi_ctrl.hl_css.adv_rd_lat_dis;
when s_adv_wr_lat => v_dis := mmi_ctrl.hl_css.adv_wr_lat_dis;
when s_prep_customer_mr_setup => v_dis := mmi_ctrl.hl_css.prep_customer_mr_setup_dis;
when s_tracking_setup |
s_tracking => v_dis := mmi_ctrl.hl_css.tracking_dis;
when others => v_dis := '1'; -- default change stage
end case;
return v_dis;
end function;
-- decoder to find the relevant command for a given state
function find_cmd
(
state : t_master_sm_state
) return t_ctrl_cmd_id is
begin
case state is
when s_phy_initialise => return cmd_phy_initialise;
when s_init_dram => return cmd_init_dram;
when s_prog_cal_mr => return cmd_prog_cal_mr;
when s_write_ihi => return cmd_write_ihi;
when s_cal => return cmd_idle;
when s_write_btp => return cmd_write_btp;
when s_write_mtp => return cmd_write_mtp;
when s_read_mtp => return cmd_read_mtp;
when s_rrp_reset => return cmd_rrp_reset;
when s_rrp_sweep => return cmd_rrp_sweep;
when s_rrp_seek => return cmd_rrp_seek;
when s_rdv => return cmd_rdv;
when s_poa => return cmd_poa;
when s_was => return cmd_was;
when s_adv_rd_lat => return cmd_prep_adv_rd_lat;
when s_adv_wr_lat => return cmd_prep_adv_wr_lat;
when s_prep_customer_mr_setup => return cmd_prep_customer_mr_setup;
when s_tracking_setup |
s_tracking => return cmd_tr_due;
when others => return cmd_idle;
end case;
end function;
function mcs_rw_state -- returns true for multiple cs read/write states
(
state : t_master_sm_state
) return boolean is
begin
case state is
when s_write_btp | s_write_mtp | s_rrp_sweep =>
return true;
when s_reset | s_phy_initialise | s_init_dram | s_prog_cal_mr | s_write_ihi | s_cal |
s_read_mtp | s_rrp_reset | s_rrp_seek | s_rdv | s_poa |
s_was | s_adv_rd_lat | s_adv_wr_lat | s_prep_customer_mr_setup |
s_tracking_setup | s_tracking | s_operational | s_non_operational =>
return false;
when others =>
--
return false;
end case;
end function;
-- timing parameters
constant c_done_timeout_count : natural := 32768;
constant c_ack_timeout_count : natural := 1000;
constant c_ticks_per_ms : natural := 1000000000/(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
constant c_ticks_per_10us : natural := 10000000 /(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
-- local copy of calibration fail/success signals
signal int_ctl_init_fail : std_logic;
signal int_ctl_init_success : std_logic;
-- state machine (master for sequencer)
signal state : t_master_sm_state;
signal last_state : t_master_sm_state;
-- flow control signals for state machine
signal dis_state : std_logic; -- disable state
signal hold_state : std_logic; -- hold in state for 1 clock cycle
signal master_ctrl_op_rec : t_ctrl_command; -- master command record to all sequencer blocks
signal master_ctrl_iram_push : t_ctrl_iram; -- record indicating control details for pushes
signal dll_lock_counter : natural range MEM_IF_DLL_LOCK_COUNT - 1 downto 0; -- to wait for dll to lock
signal iram_init_complete : std_logic;
-- timeout signals to check if a block has 'hung'
signal timeout_counter : natural range c_done_timeout_count - 1 downto 0;
signal timeout_counter_stop : std_logic;
signal timeout_counter_enable : std_logic;
signal timeout_counter_clear : std_logic;
signal cmd_req_asserted : std_logic; -- a command has been issued
signal flag_ack_timeout : std_logic; -- req -> ack timed out
signal flag_done_timeout : std_logic; -- reg -> done timed out
signal waiting_for_ack : std_logic; -- command issued
signal cmd_ack_seen : std_logic; -- command completed
signal curr_ctrl : t_ctrl_stat; -- response for current active block
signal curr_cmd : t_ctrl_cmd_id;
-- store state information based on issued command
signal int_ctrl_prev_stage : t_ctrl_cmd_id;
signal int_ctrl_current_stage : t_ctrl_cmd_id;
-- multiple chip select counter
signal cs_counter : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal reissue_cmd_req : std_logic; -- reissue command request for multiple cs
signal cal_cs_enabled : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- signals to check the ac_nt setting
signal ac_nt_almts_checked : natural range 0 to DWIDTH_RATIO/2-1;
signal ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
-- track the mtp alignment setting
signal mtp_almts_checked : natural range 0 to 2;
signal mtp_correct_almt : natural range 0 to 1;
signal mtp_no_valid_almt : std_logic;
signal mtp_both_valid_almt : std_logic;
signal mtp_err : std_logic;
-- tracking timing
signal milisecond_tick_gen_count : natural range 0 to c_ticks_per_ms -1 := c_ticks_per_ms -1;
signal tracking_ms_counter : natural range 0 to 255;
signal tracking_update_due : std_logic;
begin -- architecture struct
-------------------------------------------------------------------------------
-- check if chip selects are enabled
-- this only effects reactive stages (i,e, those requiring memory reads)
-------------------------------------------------------------------------------
process(ctl_cal_byte_lanes)
variable v_cs_enabled : std_logic;
begin
for i in 0 to MEM_IF_NUM_RANKS - 1 loop
-- check if any bytes enabled
v_cs_enabled := '0';
for j in 0 to MEM_IF_DQS_WIDTH - 1 loop
v_cs_enabled := v_cs_enabled or ctl_cal_byte_lanes(i*MEM_IF_DQS_WIDTH + j);
end loop;
-- if any byte enabled set cs as enabled else not
cal_cs_enabled(i) <= v_cs_enabled;
-- sanity checking:
if i = 0 and v_cs_enabled = '0' then
report ctrl_report_prefix & " disabling of chip select 0 is unsupported by the sequencer," & LF &
"-> if this is your intention then please remap CS pins such that CS 0 is not disabled" severity failure;
end if;
end loop;
end process;
-- -----------------------------------------------------------------------------
-- dll lock counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif rising_edge(clk) then
if ctl_recalibrate_req = '1' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif dll_lock_counter /= 0 then
dll_lock_counter <= dll_lock_counter - 1;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- timeout counter : this counter is used to determine if an ack, or done has
-- not been received within the expected number of clock cycles of a req being
-- asserted.
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter <= c_done_timeout_count - 1;
elsif rising_edge(clk) then
if timeout_counter_clear = '1' then
timeout_counter <= c_done_timeout_count - 1;
elsif timeout_counter_enable = '1' and state /= s_init_dram then
if timeout_counter /= 0 then
timeout_counter <= timeout_counter - 1;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- register current ctrl signal based on current command
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
curr_ctrl <= defaults;
curr_cmd <= cmd_idle;
elsif rising_edge(clk) then
case curr_active_block(curr_cmd) is
when admin => curr_ctrl <= admin_ctrl;
when dgrb => curr_ctrl <= dgrb_ctrl;
when dgwb => curr_ctrl <= dgwb_ctrl;
when others => curr_ctrl <= defaults;
end case;
curr_cmd <= master_ctrl_op_rec.command;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of cmd_ack_seen
-- -----------------------------------------------------------------------------
process (curr_ctrl)
begin
cmd_ack_seen <= curr_ctrl.command_ack;
end process;
-------------------------------------------------------------------------------
-- generation of waiting_for_ack flag (to determine whether ack has timed out)
-------------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
waiting_for_ack <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
waiting_for_ack <= '1';
elsif cmd_ack_seen = '1' then
waiting_for_ack <= '0';
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of timeout flags
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
flag_ack_timeout <= '0';
flag_done_timeout <= '0';
elsif rising_edge(clk) then
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_ack_timeout <= '0';
elsif timeout_counter = 0 and waiting_for_ack = '1' then
flag_ack_timeout <= '1';
end if;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_done_timeout <= '0';
elsif timeout_counter = 0 and
state /= s_rrp_sweep and -- rrp can take enough cycles to overflow counter so don't timeout
state /= s_init_dram and -- init_dram takes about 200 us, so don't timeout
timeout_counter_clear /= '1' then -- check if currently clearing the timeout (i.e. command_done asserted for s_init_dram or s_rrp_sweep)
flag_done_timeout <= '1';
end if;
end if;
end process;
-- generation of timeout_counter_stop
timeout_counter_stop <= curr_ctrl.command_done;
-- -----------------------------------------------------------------------------
-- generation of timeout_counter_enable and timeout_counter_clear
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter_enable <= '0';
timeout_counter_clear <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
timeout_counter_enable <= '1';
timeout_counter_clear <= '0';
elsif timeout_counter_stop = '1'
or state = s_operational
or state = s_non_operational
or state = s_reset then
timeout_counter_enable <= '0';
timeout_counter_clear <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- assignment to ctrl_mmi record
-------------------------------------------------------------------------------
process (clk, rst_n)
variable v_ctrl_mmi : t_ctrl_mmi;
begin
if rst_n = '0' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
int_ctrl_prev_stage <= cmd_idle;
int_ctrl_current_stage <= cmd_idle;
elsif rising_edge(clk) then
ctrl_mmi <= v_ctrl_mmi;
v_ctrl_mmi.ctrl_calibration_success := '0';
v_ctrl_mmi.ctrl_calibration_fail := '0';
if (curr_ctrl.command_ack = '1') then
case state is
when s_init_dram => v_ctrl_mmi.ctrl_cal_stage_ack_seen.init_dram := '1';
when s_write_btp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_btp := '1';
when s_write_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_mtp := '1';
when s_read_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.read_mtp := '1';
when s_rrp_reset => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_reset := '1';
when s_rrp_sweep => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_sweep := '1';
when s_rrp_seek => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_seek := '1';
when s_rdv => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rdv := '1';
when s_poa => v_ctrl_mmi.ctrl_cal_stage_ack_seen.poa := '1';
when s_was => v_ctrl_mmi.ctrl_cal_stage_ack_seen.was := '1';
when s_adv_rd_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_rd_lat := '1';
when s_adv_wr_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_wr_lat := '1';
when s_prep_customer_mr_setup => v_ctrl_mmi.ctrl_cal_stage_ack_seen.prep_customer_mr_setup := '1';
when s_tracking_setup |
s_tracking => v_ctrl_mmi.ctrl_cal_stage_ack_seen.tracking_setup := '1';
when others => null;
end case;
end if;
-- special 'ack' (actually finished) triggers for phy_initialise, writing iram header info and s_cal
if state = s_phy_initialise then
if iram_status.init_done = '1' and dll_lock_counter = 0 then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.phy_initialise := '1';
end if;
end if;
if state = s_write_ihi then
if iram_push_done = '1' then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_ihi := '1';
end if;
end if;
if state = s_cal and find_dis_bit(state, mmi_ctrl) = '0' then -- if cal state and calibration not disabled acknowledge
v_ctrl_mmi.ctrl_cal_stage_ack_seen.cal := '1';
end if;
if state = s_operational then
v_ctrl_mmi.ctrl_calibration_success := '1';
end if;
if state = s_non_operational then
v_ctrl_mmi.ctrl_calibration_fail := '1';
end if;
if state /= s_non_operational then
v_ctrl_mmi.ctrl_current_active_block := master_ctrl_iram_push.active_block;
v_ctrl_mmi.ctrl_current_stage := master_ctrl_op_rec.command;
else
v_ctrl_mmi.ctrl_current_active_block := v_ctrl_mmi.ctrl_current_active_block;
v_ctrl_mmi.ctrl_current_stage := v_ctrl_mmi.ctrl_current_stage;
end if;
int_ctrl_prev_stage <= int_ctrl_current_stage;
int_ctrl_current_stage <= v_ctrl_mmi.ctrl_current_stage;
if int_ctrl_prev_stage /= int_ctrl_current_stage then
v_ctrl_mmi.ctrl_current_stage_done := '0';
else
if curr_ctrl.command_done = '1' then
v_ctrl_mmi.ctrl_current_stage_done := '1';
end if;
end if;
v_ctrl_mmi.master_state_r := last_state;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
end if;
-- assert error codes here
if curr_ctrl.command_err = '1' then
v_ctrl_mmi.ctrl_err_code := curr_ctrl.command_result;
elsif flag_ack_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_ack_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif flag_done_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_done_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_err = '1' then
if mtp_no_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_NO_VALID_ALMT, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_both_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_BOTH_ALMT_PASS, v_ctrl_mmi.ctrl_err_code'length));
end if;
end if;
end if;
end process;
-- check if iram finished init
process(iram_status)
begin
if GENERATE_ADDITIONAL_DBG_RTL = 0 then
iram_init_complete <= '1';
else
iram_init_complete <= iram_status.init_done;
end if;
end process;
-- -----------------------------------------------------------------------------
-- master state machine
-- (this controls the operation of the entire sequencer)
-- the states are summarised as follows:
-- s_reset
-- s_phy_initialise - wait for dll lock and init done flag from iram
-- s_init_dram, -- dram initialisation - reset sequence
-- s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
-- s_write_ihi - write header information in iRAM
-- s_cal - check if calibration to be executed
-- s_write_btp - write burst training pattern
-- s_write_mtp - write more training pattern
-- s_rrp_reset - read resync phase setup - reset initial conditions
-- s_rrp_sweep - read resync phase setup - sweep phases per chip select
-- s_read_mtp - read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
-- s_rrp_seek - read resync phase setup - seek correct alignment
-- s_rdv - read data valid setup
-- s_poa - calibrate the postamble
-- s_was - write datapath setup (ac to write data timing)
-- s_adv_rd_lat - advertise read latency
-- s_adv_wr_lat - advertise write latency
-- s_tracking_setup - perform tracking (1st pass to setup mimic window)
-- s_prep_customer_mr_setup - apply user mode register settings (in admin block)
-- s_tracking - perform tracking (subsequent passes in user mode)
-- s_operational - calibration successful and in user mode
-- s_non_operational - calibration unsuccessful and in user mode
-- -----------------------------------------------------------------------------
process(clk, rst_n)
variable v_seen_ack : boolean;
variable v_dis : std_logic; -- disable bit
begin
if rst_n = '0' then
state <= s_reset;
last_state <= s_reset;
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
v_seen_ack := false;
hold_state <= '0';
cs_counter <= 0;
mtp_almts_checked <= 0;
ac_nt <= (others => '1');
ac_nt_almts_checked <= 0;
reissue_cmd_req <= '0';
dis_state <= '0';
elsif rising_edge(clk) then
last_state <= state;
-- check if state_tx required
if curr_ctrl.command_ack = '1' then
v_seen_ack := true;
end if;
-- find disable bit for current state (do once to avoid exit mid-state)
if state /= last_state then
dis_state <= find_dis_bit(state, mmi_ctrl);
end if;
-- Set special conditions:
if state = s_reset or
state = s_operational or
state = s_non_operational then
dis_state <= '1';
end if;
-- override to ensure execution of next state logic
if (state = s_cal) then
dis_state <= '1';
end if;
-- if header writing in iram check finished
if (state = s_write_ihi) then
if iram_push_done = '1' or mmi_ctrl.hl_css.write_ihi_dis = '1' then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
-- Special condition for initialisation
if (state = s_phy_initialise) then
if ((dll_lock_counter = 0) and (iram_init_complete = '1')) or
(mmi_ctrl.hl_css.phy_initialise_dis = '1') then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
if dis_state = '1' then
v_seen_ack := false;
elsif curr_ctrl.command_done = '1' then
if v_seen_ack = false then
report ctrl_report_prefix & "have not seen ack but have seen command done from " & t_ctrl_active_block'image(curr_active_block(master_ctrl_op_rec.command)) & "_block in state " & t_master_sm_state'image(state) severity warning;
end if;
v_seen_ack := false;
end if;
-- default do not reissue command request
reissue_cmd_req <= '0';
if (hold_state = '1') then
hold_state <= '0';
else
if ((dis_state = '1') or
(curr_ctrl.command_done = '1') or
((cal_cs_enabled(cs_counter) = '0') and (mcs_rw_state(state) = True))) then -- current chip select is disabled and read/write
hold_state <= '1';
-- Only reset the below if making state change
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
-- default chip select counter gets reset to zero
cs_counter <= 0;
case state is
when s_reset => state <= s_phy_initialise;
ac_nt <= (others => '1');
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_phy_initialise => state <= s_init_dram;
when s_init_dram => state <= s_prog_cal_mr;
when s_prog_cal_mr => if cs_counter = MEM_IF_NUM_RANKS - 1 then
-- if no debug interface don't write iram header
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
state <= s_write_ihi;
else
state <= s_cal;
end if;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_write_ihi => state <= s_cal;
when s_cal => if mmi_ctrl.hl_css.cal_dis = '0' then
state <= s_write_btp;
else
state <= s_tracking_setup;
end if;
-- always enter s_cal before calibration so reset some variables here
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_write_btp => if cs_counter = MEM_IF_NUM_RANKS-1 or
SIM_TIME_REDUCTIONS = 2 then
state <= s_write_mtp;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_write_mtp => if cs_counter = MEM_IF_NUM_RANKS - 1 or
SIM_TIME_REDUCTIONS = 2 then
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_rrp_reset => state <= s_rrp_sweep;
when s_rrp_sweep => if cs_counter = MEM_IF_NUM_RANKS - 1 or
mtp_almts_checked /= 2 or
SIM_TIME_REDUCTIONS = 2 then
if mtp_almts_checked /= 2 then
state <= s_read_mtp;
else
state <= s_rrp_seek;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_read_mtp => if mtp_almts_checked /= 2 then
mtp_almts_checked <= mtp_almts_checked + 1;
end if;
state <= s_rrp_reset;
when s_rrp_seek => state <= s_rdv;
when s_rdv => state <= s_was;
when s_was => state <= s_adv_rd_lat;
when s_adv_rd_lat => state <= s_adv_wr_lat;
when s_adv_wr_lat => if dgrb_ctrl_ac_nt_good = '1' then
state <= s_poa;
else
if ac_nt_almts_checked = (DWIDTH_RATIO/2 - 1) then
state <= s_non_operational;
else
-- switch alignment and restart calibration
ac_nt <= std_logic_vector(unsigned(ac_nt) + 1);
ac_nt_almts_checked <= ac_nt_almts_checked + 1;
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
mtp_almts_checked <= 0;
end if;
end if;
when s_poa => state <= s_tracking_setup;
when s_tracking_setup => state <= s_prep_customer_mr_setup;
when s_prep_customer_mr_setup => if cs_counter = MEM_IF_NUM_RANKS - 1 then -- s_prep_customer_mr_setup is always performed over all cs
state <= s_operational;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_tracking => state <= s_operational;
int_ctl_init_success <= int_ctl_init_success;
int_ctl_init_fail <= int_ctl_init_fail;
when s_operational => int_ctl_init_success <= '1';
int_ctl_init_fail <= '0';
hold_state <= '0';
if tracking_update_due = '1' and mmi_ctrl.hl_css.tracking_dis = '0' then
state <= s_tracking;
hold_state <= '1';
end if;
when s_non_operational => int_ctl_init_success <= '0';
int_ctl_init_fail <= '1';
hold_state <= '0';
if last_state /= s_non_operational then -- print a warning on entering this state
report ctrl_report_prefix & "memory calibration has failed (output from ctrl block)" severity WARNING;
end if;
when others => state <= t_master_sm_state'succ(state);
end case;
end if;
end if;
if flag_done_timeout = '1' -- no done signal from current active block
or flag_ack_timeout = '1' -- or no ack signal from current active block
or curr_ctrl.command_err = '1' -- or an error from current active block
or mtp_err = '1' then -- or an error due to mtp alignment
state <= s_non_operational;
end if;
if mmi_ctrl.calibration_start = '1' then -- restart calibration process
state <= s_cal;
end if;
if ctl_recalibrate_req = '1' then -- restart all incl. initialisation
state <= s_reset;
end if;
end if;
end process;
-- generate output calibration fail/success signals
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= int_ctl_init_fail;
ctl_init_success <= int_ctl_init_success;
end if;
end process;
-- assign ac_nt to the output int_ac_nt
process(ac_nt)
begin
int_ac_nt <= ac_nt;
end process;
-- ------------------------------------------------------------------------------
-- find correct mtp_almt from returned data
-- ------------------------------------------------------------------------------
mtp_almt: block
signal dvw_size_a0 : natural range 0 to 255; -- maximum size of command result
signal dvw_size_a1 : natural range 0 to 255;
begin
process (clk, rst_n)
variable v_dvw_a0_small : boolean;
variable v_dvw_a1_small : boolean;
begin
if rst_n = '0' then
mtp_correct_almt <= 0;
dvw_size_a0 <= 0;
dvw_size_a1 <= 0;
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
elsif rising_edge(clk) then
-- update the dvw sizes
if state = s_read_mtp then
if curr_ctrl.command_done = '1' then
if mtp_almts_checked = 0 then
dvw_size_a0 <= to_integer(unsigned(curr_ctrl.command_result));
else
dvw_size_a1 <= to_integer(unsigned(curr_ctrl.command_result));
end if;
end if;
end if;
-- check dvw size and set mtp almt
if dvw_size_a0 < dvw_size_a1 then
mtp_correct_almt <= 1;
else
mtp_correct_almt <= 0;
end if;
-- error conditions
if mtp_almts_checked = 2 and GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if finished alignment checking (and GENERATE_ADDITIONAL_DBG_RTL set)
-- perform size checks once per dvw
if dvw_size_a0 < 3 then
v_dvw_a0_small := true;
else
v_dvw_a0_small := false;
end if;
if dvw_size_a1 < 3 then
v_dvw_a1_small := true;
else
v_dvw_a1_small := false;
end if;
if v_dvw_a0_small = true and v_dvw_a1_small = true then
mtp_no_valid_almt <= '1';
mtp_err <= '1';
end if;
if v_dvw_a0_small = false and v_dvw_a1_small = false then
mtp_both_valid_almt <= '1';
mtp_err <= '1';
end if;
else
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------------------
-- process to generate command outputs, based on state, last_state and mmi_ctrl.
-- asynchronously
-- ------------------------------------------------------------------------------
process (state, last_state, mmi_ctrl, reissue_cmd_req, cs_counter, mtp_almts_checked, mtp_correct_almt)
begin
master_ctrl_op_rec <= defaults;
master_ctrl_iram_push <= defaults;
case state is
-- special condition states
when s_reset | s_phy_initialise | s_cal =>
null;
when s_write_ihi =>
if mmi_ctrl.hl_css.write_ihi_dis = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state then
master_ctrl_op_rec.command_req <= '1';
end if;
end if;
when s_operational | s_non_operational =>
master_ctrl_op_rec.command <= find_cmd(state);
when others => -- default condition for most states
if find_dis_bit(state, mmi_ctrl) = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state or reissue_cmd_req = '1' then
master_ctrl_op_rec.command_req <= '1';
end if;
else
if state = last_state then -- safe state exit if state disabled mid-calibration
master_ctrl_op_rec.command <= find_cmd(state);
end if;
end if;
end case;
-- for multiple chip select commands assign operand to cs_counter
master_ctrl_op_rec.command_op <= defaults;
master_ctrl_op_rec.command_op.current_cs <= cs_counter;
if state = s_rrp_sweep or state = s_read_mtp or state = s_poa then
if mtp_almts_checked /= 2 or SIM_TIME_REDUCTIONS = 2 then
master_ctrl_op_rec.command_op.single_bit <= '1';
end if;
if mtp_almts_checked /= 2 then
master_ctrl_op_rec.command_op.mtp_almt <= mtp_almts_checked;
else
master_ctrl_op_rec.command_op.mtp_almt <= mtp_correct_almt;
end if;
end if;
-- set write mode and packing mode for iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
case state is
when s_rrp_sweep =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_bitwise;
when s_rrp_seek |
s_read_mtp =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_wordwise;
when others =>
null;
end case;
end if;
-- set current active block
master_ctrl_iram_push.active_block <= curr_active_block(find_cmd(state));
end process;
-- some concurc_read_burst_trent assignments to outputs
process (master_ctrl_iram_push, master_ctrl_op_rec)
begin
ctrl_iram_push <= master_ctrl_iram_push;
ctrl_op_rec <= master_ctrl_op_rec;
cmd_req_asserted <= master_ctrl_op_rec.command_req;
end process;
-- -----------------------------------------------------------------------------
-- tracking interval counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
milisecond_tick_gen_count <= c_ticks_per_ms -1;
tracking_ms_counter <= 0;
tracking_update_due <= '0';
elsif rising_edge(clk) then
if state = s_operational and last_state/= s_operational then
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
tracking_ms_counter <= mmi_ctrl.tracking_period_ms;
elsif state = s_operational then
if milisecond_tick_gen_count = 0 and tracking_update_due /= '1' then
if tracking_ms_counter = 0 then
tracking_update_due <= '1';
else
tracking_ms_counter <= tracking_ms_counter -1;
end if;
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
elsif milisecond_tick_gen_count /= 0 then
milisecond_tick_gen_count <= milisecond_tick_gen_count -1;
end if;
else
tracking_update_due <= '0';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : top level for the non-levelling AFI PHY sequencer
-- The top level instances the sub-blocks of the AFI PHY
-- sequencer. In addition a number of multiplexing and high-
-- level control operations are performed. This includes the
-- multiplexing and generation of control signals for: the
-- address and command DRAM interface and pll, oct and datapath
-- latency control signals.
-- -----------------------------------------------------------------------------
--altera message_off 10036
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_seq IS
generic (
-- choice of FPGA device family and DRAM type
FAMILY : string;
MEM_IF_MEMTYPE : string;
SPEED_GRADE : string;
FAMILYGROUP_ID : natural;
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_CS_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_RANKS_PER_SLOT : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural; -- 0 = false, 1 = true
AV_IF_ADDR_WIDTH : natural;
-- Not used for non-levelled seq
CHIP_OR_DIMM : string;
RDIMM_CONFIG_BITS : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
WRITE_DESKEW_T10 : natural;
WRITE_DESKEW_HC_T10 : natural;
WRITE_DESKEW_T9NI : natural;
WRITE_DESKEW_HC_T9NI : natural;
WRITE_DESKEW_T9I : natural;
WRITE_DESKEW_HC_T9I : natural;
WRITE_DESKEW_RANGE : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : natural;
PHY_DEF_MR_2ND : natural;
PHY_DEF_MR_3RD : natural;
PHY_DEF_MR_4TH : natural;
MEM_IF_DQSN_EN : natural; -- default off for Cyclone-III
MEM_IF_DQS_CAPTURE_EN : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural; -- 1 signals to include iram and mmi blocks and 0 not to include
SINGLE_DQS_DELAY_CONTROL_CODE : natural; -- reserved for future use
PRESET_RLAT : natural; -- reserved for future use
EN_OCT : natural; -- Does the sequencer use OCT during calibration.
OCT_LAT_WIDTH : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 2 rrp for 1 dqs group and 1 cs
FORCE_HC : natural; -- Use to force HardCopy in simulation.
CAPABILITIES : natural; -- advertise capabilities i.e. which ctrl block states to execute (default all on)
TINIT_TCK : natural;
TINIT_RST : natural;
GENERATE_TRACKING_PHASE_STORE : natural; -- reserved for future use
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and prompt
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_init_warning : out std_logic; -- unused
ctl_recalibrate_req : in std_logic;
-- the following two signals are reserved for future use
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- pll reconfiguration
seq_pll_inc_dec_n : out std_logic;
seq_pll_start_reconfig : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
seq_pll_phs_shift_busy : in std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic/measure clock
-- scanchain associated signals (reserved for future use)
seq_scan_clk : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqs_config : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_update : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_din : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_ck : out std_logic_vector(MEM_IF_CLK_PAIR_COUNT - 1 downto 0);
seq_scan_enable_dqs : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqsn : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dq : out std_logic_vector(MEM_IF_DWIDTH - 1 downto 0);
seq_scan_enable_dm : out std_logic_vector(MEM_IF_DM_WIDTH - 1 downto 0);
hr_rsc_clk : in std_logic;
-- address / command interface (note these are mapped internally to the seq_ac record)
seq_ac_addr : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 downto 0);
seq_ac_ba : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 downto 0);
seq_ac_cas_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_ras_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_we_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_cke : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_cs_n : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_odt : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_rst_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_sel : out std_logic;
seq_mem_clk_disable : out std_logic;
-- additional datapath latency (reserved for future use)
seq_ac_add_1t_ac_lat_internal : out std_logic;
seq_ac_add_1t_odt_lat_internal : out std_logic;
seq_ac_add_2t : out std_logic;
-- read datapath interface
seq_rdp_reset_req_n : out std_logic;
seq_rdp_inc_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_rdp_dec_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
rdata : in std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
-- read data valid (associated signals) interface
seq_rdv_doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rdata_valid : in std_logic_vector( DWIDTH_RATIO/2 - 1 downto 0);
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
seq_ctl_rlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- postamble interface (unused for Cyclone-III)
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_protection_override_1x : out std_logic;
-- OCT path control
seq_oct_oct_delay : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_oct_extend : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_value : out std_logic;
-- write data path interface
seq_wdp_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
seq_wdp_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
seq_wdp_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
seq_wdp_ovride : out std_logic;
seq_dqs_add_2t_delay : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_ctl_wlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- parity signals (not used for non-levelled PHY)
mem_err_out_n : in std_logic;
parity_error_n : out std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock (a generic option))
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH - 1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic
);
end entity;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg.all;
-- Individually include each of library files for the sub-blocks of the sequencer:
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_admin;
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_mmi;
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_iram;
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_dgrb;
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_dgwb;
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_ctrl;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_seq IS
attribute altera_attribute : string;
attribute altera_attribute of struct : architecture is "-name MESSAGE_DISABLE 18010";
-- debug signals (similar to those seen in the Quartus v8.0 DDR/DDR2 sequencer)
signal rsu_multiple_valid_latencies_err : std_logic; -- true if >2 valid latency values are detected
signal rsu_grt_one_dvw_err : std_logic; -- true if >1 data valid window is detected
signal rsu_no_dvw_err : std_logic; -- true if no data valid window is detected
signal rsu_codvw_phase : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_codvw_size : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_read_latency : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0); -- set to the correct read latency if calibration is successful
-- outputs from the dgrb to generate the above rsu_codvw_* signals and report status to the mmi
signal dgrb_mmi : t_dgrb_mmi;
-- admin to mmi interface
signal regs_admin_ctrl_rec : t_admin_ctrl; -- mmi register settings information
signal admin_regs_status_rec : t_admin_stat; -- admin status information
-- odt enable from the admin block based on mr settings
signal enable_odt : std_logic;
-- iram status information (sent to the ctrl block)
signal iram_status : t_iram_stat;
-- dgrb iram write interface
signal dgrb_iram : t_iram_push;
-- ctrl to iram interface
signal ctrl_idib_top : natural; -- current write location in the iram
signal ctrl_active_block : t_ctrl_active_block;
signal ctrl_iram_push : t_ctrl_iram;
signal iram_push_done : std_logic;
signal ctrl_iram_ihi_write : std_logic;
-- local copies of calibration status
signal ctl_init_success_int : std_logic;
signal ctl_init_fail_int : std_logic;
-- refresh period failure flag
signal trefi_failure : std_logic;
-- unified ctrl signal broadcast to all blocks from the ctrl block
signal ctrl_broadcast : t_ctrl_command;
-- standardised status report per block to control block
signal admin_ctrl : t_ctrl_stat;
signal dgwb_ctrl : t_ctrl_stat;
signal dgrb_ctrl : t_ctrl_stat;
-- mmi and ctrl block interface
signal mmi_ctrl : t_mmi_ctrl;
signal ctrl_mmi : t_ctrl_mmi;
-- write datapath override signals
signal dgwb_wdp_override : std_logic;
signal dgrb_wdp_override : std_logic;
-- address/command access request and grant between the dgrb/dgwb blocks and the admin block
signal dgb_ac_access_gnt : std_logic;
signal dgb_ac_access_gnt_r : std_logic;
signal dgb_ac_access_req : std_logic;
signal dgwb_ac_access_req : std_logic;
signal dgrb_ac_access_req : std_logic;
-- per block address/command record (multiplexed in this entity)
signal admin_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgwb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgrb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- doing read signal
signal seq_rdv_doing_rd_int : std_logic_vector(seq_rdv_doing_rd'range);
-- local copy of interface to inc/dec latency on rdata_valid and postamble
signal seq_rdata_valid_lat_dec_int : std_logic;
signal seq_rdata_valid_lat_inc_int : std_logic;
signal seq_poa_lat_inc_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
signal seq_poa_lat_dec_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
-- local copy of write/read latency
signal seq_ctl_wlat_int : std_logic_vector(seq_ctl_wlat'range);
signal seq_ctl_rlat_int : std_logic_vector(seq_ctl_rlat'range);
-- parameterisation of dgrb / dgwb / admin blocks from mmi register settings
signal parameterisation_rec : t_algm_paramaterisation;
-- PLL reconfig
signal seq_pll_phs_shift_busy_r : std_logic;
signal seq_pll_phs_shift_busy_ccd : std_logic;
signal dgrb_pll_inc_dec_n : std_logic;
signal dgrb_pll_start_reconfig : std_logic;
signal dgrb_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal dgrb_phs_shft_busy : std_logic;
signal mmi_pll_inc_dec_n : std_logic;
signal mmi_pll_start_reconfig : std_logic;
signal mmi_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal pll_mmi : t_pll_mmi;
signal mmi_pll : t_mmi_pll_reconfig;
-- address and command 1t setting (unused for Full Rate)
signal int_ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
signal dgrb_ctrl_ac_nt_good : std_logic;
-- the following signals are reserved for future use
signal ctl_cal_byte_lanes_r : std_logic_vector(ctl_cal_byte_lanes'range);
signal mmi_setup : t_ctrl_cmd_id;
signal dgwb_iram : t_iram_push;
-- track number of poa / rdv adjustments (reporting only)
signal poa_adjustments : natural;
signal rdv_adjustments : natural;
-- convert input generics from natural to std_logic_vector
constant c_phy_def_mr_1st_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_1ST, 16));
constant c_phy_def_mr_2nd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_2ND, 16));
constant c_phy_def_mr_3rd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_3RD, 16));
constant c_phy_def_mr_4th_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_4TH, 16));
-- overrride on capabilities to speed up simulation time
function capabilities_override(capabilities : natural;
sim_time_reductions : natural) return natural is
begin
if sim_time_reductions = 1 then
return 2**c_hl_css_reg_cal_dis_bit; -- disable calibration completely
else
return capabilities;
end if;
end function;
-- set sequencer capabilities
constant c_capabilities_override : natural := capabilities_override(CAPABILITIES, SIM_TIME_REDUCTIONS);
constant c_capabilities : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override,32));
-- setup for address/command interface
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- setup for odt signals
-- odt setting as implemented in the altera high-performance controller for ddrx memories
constant c_odt_settings : t_odt_array(0 to MEM_IF_NUM_RANKS-1) := set_odt_values(MEM_IF_NUM_RANKS, MEM_IF_RANKS_PER_SLOT, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant seq_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (top) : ";
-- setup iram configuration
constant c_iram_addresses : t_base_hdr_addresses := calc_iram_addresses(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_NUM_RANKS, MEM_IF_DQS_CAPTURE_EN);
constant c_int_iram_awidth : natural := c_iram_addresses.required_addr_bits;
constant c_preset_cal_setup : t_preset_cal := setup_instant_on(SIM_TIME_REDUCTIONS, FAMILYGROUP_ID, MEM_IF_MEMTYPE, DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, c_phy_def_mr_1st_sl_vector, c_phy_def_mr_2nd_sl_vector, c_phy_def_mr_3rd_sl_vector);
constant c_preset_codvw_phase : natural := c_preset_cal_setup.codvw_phase;
constant c_preset_codvw_size : natural := c_preset_cal_setup.codvw_size;
constant c_tracking_interval_in_ms : natural := 128;
constant c_mem_if_cal_bank : natural := 0; -- location to calibrate to
constant c_mem_if_cal_base_col : natural := 0; -- default all zeros
constant c_mem_if_cal_base_row : natural := 0;
constant c_non_op_eval_md : string := "PIN_FINDER"; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
begin -- architecture struct
-- ---------------------------------------------------------------
-- tie off unused signals to default values
-- ---------------------------------------------------------------
-- scan chain associated signals
seq_scan_clk <= (others => '0');
seq_scan_enable_dqs_config <= (others => '0');
seq_scan_update <= (others => '0');
seq_scan_din <= (others => '0');
seq_scan_enable_ck <= (others => '0');
seq_scan_enable_dqs <= (others => '0');
seq_scan_enable_dqsn <= (others => '0');
seq_scan_enable_dq <= (others => '0');
seq_scan_enable_dm <= (others => '0');
seq_dqs_add_2t_delay <= (others => '0');
seq_rdp_inc_read_lat_1x <= (others => '0');
seq_rdp_dec_read_lat_1x <= (others => '0');
-- warning flag (not used in non-levelled sequencer)
ctl_init_warning <= '0';
-- parity error flag (not used in non-levelled sequencer)
parity_error_n <= '1';
--
admin: entity ddr_ctrl_ip_phy_alt_mem_phy_admin
generic map
(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_DQSN_EN => MEM_IF_DQSN_EN,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_ROW => c_mem_if_cal_base_row,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
NON_OP_EVAL_MD => c_non_op_eval_md,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TINIT_TCK => TINIT_TCK,
TINIT_RST => TINIT_RST
)
port map
(
clk => clk,
rst_n => rst_n,
mem_ac_swapped_ranks => mem_ac_swapped_ranks,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
seq_ac => admin_ac,
seq_ac_sel => seq_ac_sel,
enable_odt => enable_odt,
regs_admin_ctrl_rec => regs_admin_ctrl_rec,
admin_regs_status_rec => admin_regs_status_rec,
trefi_failure => trefi_failure,
ctrl_admin => ctrl_broadcast,
admin_ctrl => admin_ctrl,
ac_access_req => dgb_ac_access_req,
ac_access_gnt => dgb_ac_access_gnt,
cal_fail => ctl_init_fail_int,
cal_success => ctl_init_success_int,
ctl_recalibrate_req => ctl_recalibrate_req
);
-- selectively include the debug i/f (iram and mmi blocks)
with_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 1 generate
signal mmi_iram : t_iram_ctrl;
signal mmi_iram_enable_writes : std_logic;
signal rrp_mem_loc : natural range 0 to 2 ** c_int_iram_awidth - 1;
signal command_req_r : std_logic;
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
--
mmi : entity ddr_ctrl_ip_phy_alt_mem_phy_mmi
generic map (
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
RESYNCHRONISE_AVALON_DBG => RESYNCHRONISE_AVALON_DBG,
AV_IF_ADDR_WIDTH => AV_IF_ADDR_WIDTH,
NOM_DQS_PHASE_SETTING => NOM_DQS_PHASE_SETTING,
SCAN_CLK_DIVIDE_BY => SCAN_CLK_DIVIDE_BY,
RDP_ADDR_WIDTH => RDP_ADDR_WIDTH,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
IOE_PHASES_PER_TCK => IOE_PHASES_PER_TCK,
IOE_DELAYS_PER_PHS => IOE_DELAYS_PER_PHS,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
PHY_DEF_MR_1ST => c_phy_def_mr_1st_sl_vector,
PHY_DEF_MR_2ND => c_phy_def_mr_2nd_sl_vector,
PHY_DEF_MR_3RD => c_phy_def_mr_3rd_sl_vector,
PHY_DEF_MR_4TH => c_phy_def_mr_4th_sl_vector,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
PRESET_RLAT => PRESET_RLAT,
CAPABILITIES => c_capabilities_override,
USE_IRAM => '1', -- always use iram (generic is rfu)
IRAM_AWIDTH => c_int_iram_awidth,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
READ_LAT_WIDTH => ADV_LAT_WIDTH
)
port map(
clk => clk,
rst_n => rst_n,
dbg_seq_clk => dbg_seq_clk,
dbg_seq_rst_n => dbg_seq_rst_n,
dbg_seq_addr => dbg_seq_addr,
dbg_seq_wr => dbg_seq_wr,
dbg_seq_rd => dbg_seq_rd,
dbg_seq_cs => dbg_seq_cs,
dbg_seq_wr_data => dbg_seq_wr_data,
seq_dbg_rd_data => seq_dbg_rd_data,
seq_dbg_waitrequest => seq_dbg_waitrequest,
regs_admin_ctrl => regs_admin_ctrl_rec,
admin_regs_status => admin_regs_status_rec,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi,
int_ac_1t => int_ac_nt(0),
invert_ac_1t => open,
trefi_failure => trefi_failure,
parameterisation_rec => parameterisation_rec,
pll_mmi => pll_mmi,
mmi_pll => mmi_pll,
dgrb_mmi => dgrb_mmi
);
--
iram : entity ddr_ctrl_ip_phy_alt_mem_phy_iram
generic map(
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
IRAM_AWIDTH => c_int_iram_awidth,
REFRESH_COUNT_INIT => 12,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
CAPABILITIES => c_capabilities_override,
IP_BUILDNUM => IP_BUILDNUM
)
port map(
clk => clk,
rst_n => rst_n,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_iram => ctrl_broadcast_r,
dgrb_iram => dgrb_iram,
admin_regs_status_rec => admin_regs_status_rec,
ctrl_idib_top => ctrl_idib_top,
ctrl_iram_push => ctrl_iram_push,
dgwb_iram => dgwb_iram
);
-- calculate where current data should go in the iram
process (clk, rst_n)
variable v_words_req : natural range 0 to 2 * MEM_IF_DWIDTH * PLL_STEPS_PER_CYCLE * DWIDTH_RATIO - 1; -- how many words are required
begin
if rst_n = '0' then
ctrl_idib_top <= 0;
command_req_r <= '0';
rrp_mem_loc <= 0;
elsif rising_edge(clk) then
if command_req_r = '0' and ctrl_broadcast_r.command_req = '1' then -- execute once on each command_req assertion
-- default a 'safe location'
ctrl_idib_top <= c_iram_addresses.safe_dummy;
case ctrl_broadcast_r.command is
when cmd_write_ihi => -- reset pointers
rrp_mem_loc <= c_iram_addresses.rrp;
ctrl_idib_top <= 0; -- write header to zero location always
when cmd_rrp_sweep =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- add the current space requirement to v_rrp_mem_loc
-- there are (DWIDTH_RATIO/2) * PLL_STEPS_PER_CYCLE phases swept packed into 32 bit words per pin
-- note: special case for single_bit calibration stages (e.g. read_mtp alignment)
if ctrl_broadcast_r.command_op.single_bit = '1' then
v_words_req := iram_wd_for_one_pin_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
else
v_words_req := iram_wd_for_full_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
end if;
v_words_req := v_words_req + 2; -- add 1 word location for header / footer information
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when cmd_rrp_seek |
cmd_read_mtp =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- require 3 words - header, result and footer
v_words_req := 3;
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when others =>
null;
end case;
end if;
command_req_r <= ctrl_broadcast_r.command_req;
-- if recalibration request then reset iram address
if ctl_recalibrate_req = '1' or mmi_ctrl.calibration_start = '1' then
rrp_mem_loc <= c_iram_addresses.rrp;
end if;
end if;
end process;
end generate; -- with debug interface
-- if no debug interface (iram/mmi block) tie off relevant signals
without_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 0 generate
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE_EN);
signal mmi_regs : t_mmi_regs := defaults;
begin
-- avalon interface signals
seq_dbg_rd_data <= (others => '0');
seq_dbg_waitrequest <= '0';
-- The following registers are generated to simplify the assignments which follow
-- but will be optimised away in synthesis
mmi_regs.rw_regs <= defaults(c_phy_def_mr_1st_sl_vector,
c_phy_def_mr_2nd_sl_vector,
c_phy_def_mr_3rd_sl_vector,
c_phy_def_mr_4th_sl_vector,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps,
c_tracking_interval_in_ms,
c_hl_stage_enable);
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
'0', -- do not use iram
MEM_IF_DQS_CAPTURE_EN,
int_ac_nt(0),
trefi_failure,
iram_status,
c_int_iram_awidth);
process(mmi_regs)
begin
-- debug parameterisation signals
regs_admin_ctrl_rec <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end process;
-- from the iram
iram_status <= defaults;
iram_push_done <= '0';
end generate; -- without debug interface
--
dgrb : entity ddr_ctrl_ip_phy_alt_mem_phy_dgrb
generic map(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
PRESET_CODVW_PHASE => c_preset_codvw_phase,
PRESET_CODVW_SIZE => c_preset_codvw_size,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col,
EN_OCT => EN_OCT
)
port map(
clk => clk,
rst_n => rst_n,
dgrb_ctrl => dgrb_ctrl,
ctrl_dgrb => ctrl_broadcast,
parameterisation_rec => parameterisation_rec,
phs_shft_busy => dgrb_phs_shft_busy,
seq_pll_inc_dec_n => dgrb_pll_inc_dec_n,
seq_pll_select => dgrb_pll_select,
seq_pll_start_reconfig => dgrb_pll_start_reconfig,
pll_resync_clk_index => pll_resync_clk_index,
pll_measure_clk_index => pll_measure_clk_index,
dgrb_iram => dgrb_iram,
iram_push_done => iram_push_done,
dgrb_ac => dgrb_ac,
dgrb_ac_access_req => dgrb_ac_access_req,
dgrb_ac_access_gnt => dgb_ac_access_gnt_r,
seq_rdata_valid_lat_inc => seq_rdata_valid_lat_inc_int,
seq_rdata_valid_lat_dec => seq_rdata_valid_lat_dec_int,
seq_poa_lat_dec_1x => seq_poa_lat_dec_1x_int,
seq_poa_lat_inc_1x => seq_poa_lat_inc_1x_int,
rdata_valid => rdata_valid,
rdata => rdata,
doing_rd => seq_rdv_doing_rd_int,
rd_lat => seq_ctl_rlat_int,
wd_lat => seq_ctl_wlat_int,
dgrb_wdp_ovride => dgrb_wdp_override,
seq_oct_value => seq_oct_value,
seq_mmc_start => seq_mmc_start,
mmc_seq_done => mmc_seq_done,
mmc_seq_value => mmc_seq_value,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
odt_settings => c_odt_settings,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
dgrb_mmi => dgrb_mmi
);
--
dgwb : entity ddr_ctrl_ip_phy_alt_mem_phy_dgwb
generic map(
-- Physical IF width definitions
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
DWIDTH_RATIO => DWIDTH_RATIO,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col
)
port map(
clk => clk,
rst_n => rst_n,
parameterisation_rec => parameterisation_rec,
dgwb_ctrl => dgwb_ctrl,
ctrl_dgwb => ctrl_broadcast,
dgwb_iram => dgwb_iram,
iram_push_done => iram_push_done,
dgwb_ac_access_req => dgwb_ac_access_req,
dgwb_ac_access_gnt => dgb_ac_access_gnt_r,
dgwb_dqs_burst => seq_wdp_dqs_burst,
dgwb_wdata_valid => seq_wdp_wdata_valid,
dgwb_wdata => seq_wdp_wdata,
dgwb_dm => seq_wdp_dm,
dgwb_dqs => seq_wdp_dqs,
dgwb_wdp_ovride => dgwb_wdp_override,
dgwb_ac => dgwb_ac,
bypassed_rdata => rdata(DWIDTH_RATIO * MEM_IF_DWIDTH -1 downto (DWIDTH_RATIO-1) * MEM_IF_DWIDTH),
odt_settings => c_odt_settings
);
--
ctrl: entity ddr_ctrl_ip_phy_alt_mem_phy_ctrl
generic map(
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DLL_LOCK_COUNT => 1280/(DWIDTH_RATIO/2),
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
DWIDTH_RATIO => DWIDTH_RATIO,
IRAM_ADDRESSING => c_iram_addresses,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
ACK_SEVERITY => warning
)
port map(
clk => clk,
rst_n => rst_n,
ctl_init_success => ctl_init_success_int,
ctl_init_fail => ctl_init_fail_int,
ctl_recalibrate_req => ctl_recalibrate_req,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_op_rec => ctrl_broadcast,
admin_ctrl => admin_ctrl,
dgrb_ctrl => dgrb_ctrl,
dgwb_ctrl => dgwb_ctrl,
ctrl_iram_push => ctrl_iram_push,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
int_ac_nt => int_ac_nt,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi
);
-- ------------------------------------------------------------------
-- generate legacy rsu signals
-- ------------------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
rsu_multiple_valid_latencies_err <= '0';
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_codvw_phase <= (others => '0');
rsu_codvw_size <= (others => '0');
rsu_read_latency <= (others => '0');
elsif rising_edge(clk) then
if dgrb_ctrl.command_err = '1' then
case to_integer(unsigned(dgrb_ctrl.command_result)) is
when C_ERR_RESYNC_NO_VALID_PHASES =>
rsu_no_dvw_err <= '1';
when C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS =>
rsu_multiple_valid_latencies_err <= '1';
when others => null;
end case;
end if;
rsu_codvw_phase(dgrb_mmi.cal_codvw_phase'range) <= dgrb_mmi.cal_codvw_phase;
rsu_codvw_size(dgrb_mmi.cal_codvw_size'range) <= dgrb_mmi.cal_codvw_size;
rsu_read_latency <= seq_ctl_rlat_int;
rsu_grt_one_dvw_err <= dgrb_mmi.codvw_grt_one_dvw;
-- Reset the flag on a recal request :
if ( ctl_recalibrate_req = '1') then
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_multiple_valid_latencies_err <= '0';
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- top level multiplexing and ctrl functionality
-- ---------------------------------------------------------------
oct_delay_block : block
constant DEFAULT_OCT_DELAY_CONST : integer := - 2; -- higher increases delay by one mem_clk cycle, lower decreases delay by one mem_clk cycle.
constant DEFAULT_OCT_EXTEND : natural := 3;
-- Returns additive latency extracted from mr0 as a natural number.
function decode_cl(mr0 : in std_logic_vector(12 downto 0))
return natural is
variable v_cl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_cl := to_integer(unsigned(mr0(6 downto 4)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cl := to_integer(unsigned(mr0(6 downto 4))) + 4;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cl;
end function;
-- Returns additive latency extracted from mr1 as a natural number.
function decode_al(mr1 : in std_logic_vector(12 downto 0))
return natural is
variable v_al : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_al := to_integer(unsigned(mr1(5 downto 3)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_al := to_integer(unsigned(mr1(4 downto 3)));
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_al;
end function;
-- Returns cas write latency extracted from mr2 as a natural number.
function decode_cwl(
mr0 : in std_logic_vector(12 downto 0);
mr2 : in std_logic_vector(12 downto 0)
)
return natural is
variable v_cwl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" then
v_cwl := 1;
elsif MEM_IF_MEMTYPE = "DDR2" then
v_cwl := decode_cl(mr0) - 1;
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cwl := to_integer(unsigned(mr2(4 downto 3))) + 5;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cwl;
end function;
begin
-- Process to work out timings for OCT extension and delay with respect to doing_read. NOTE that it is calculated on the basis of CL, CWL, ctl_wlat
oct_delay_proc : process(clk, rst_n)
variable v_cl : natural range 0 to 2**4 - 1; -- Total read latency.
variable v_cwl : natural range 0 to 2**4 - 1; -- Total write latency
variable oct_delay : natural range 0 to 2**OCT_LAT_WIDTH - 1;
variable v_wlat : natural range 0 to 2**ADV_LAT_WIDTH - 1;
begin
if rst_n = '0' then
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
elsif rising_edge(clk) then
if ctl_init_success_int = '1' then
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
v_cl := decode_cl(admin_regs_status_rec.mr0);
v_cwl := decode_cwl(admin_regs_status_rec.mr0, admin_regs_status_rec.mr2);
if SIM_TIME_REDUCTIONS = 1 then
v_wlat := c_preset_cal_setup.wlat;
else
v_wlat := to_integer(unsigned(seq_ctl_wlat_int));
end if;
oct_delay := DWIDTH_RATIO * v_wlat / 2 + (v_cl - v_cwl) + DEFAULT_OCT_DELAY_CONST;
if not (FAMILYGROUP_ID = 2) then -- CIII doesn't support OCT
seq_oct_oct_delay <= std_logic_vector(to_unsigned(oct_delay, OCT_LAT_WIDTH));
end if;
else
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
end if;
end if;
end process;
end block;
-- control postamble protection override signal (seq_poa_protection_override_1x)
process(clk, rst_n)
variable v_warning_given : std_logic;
begin
if rst_n = '0' then
seq_poa_protection_override_1x <= '0';
v_warning_given := '0';
elsif rising_edge(clk) then
case ctrl_broadcast.command is
when cmd_rdv |
cmd_rrp_sweep |
cmd_rrp_seek |
cmd_prep_adv_rd_lat |
cmd_prep_adv_wr_lat => seq_poa_protection_override_1x <= '1';
when others => seq_poa_protection_override_1x <= '0';
end case;
end if;
end process;
ac_mux : block
constant c_mem_clk_disable_pipe_len : natural := 3;
signal seen_phy_init_complete : std_logic;
signal mem_clk_disable : std_logic_vector(c_mem_clk_disable_pipe_len - 1 downto 0);
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
-- #for speed and to reduce fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
-- multiplex mem interface control between admin, dgrb and dgwb
process(clk, rst_n)
variable v_seq_ac_mux : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
seq_rdv_doing_rd <= (others => '0');
seq_mem_clk_disable <= '1';
mem_clk_disable <= (others => '1');
seen_phy_init_complete <= '0';
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
elsif rising_edge(clk) then
seq_rdv_doing_rd <= seq_rdv_doing_rd_int;
seq_mem_clk_disable <= mem_clk_disable(c_mem_clk_disable_pipe_len-1);
mem_clk_disable(c_mem_clk_disable_pipe_len-1 downto 1) <= mem_clk_disable(c_mem_clk_disable_pipe_len-2 downto 0);
if dgwb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgwb_ac;
elsif dgrb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgrb_ac;
else
v_seq_ac_mux := admin_ac;
end if;
if ctl_recalibrate_req = '1' then
mem_clk_disable(0) <= '1';
seen_phy_init_complete <= '0';
elsif ctrl_broadcast_r.command = cmd_init_dram and ctrl_broadcast_r.command_req = '1' then
mem_clk_disable(0) <= '0';
seen_phy_init_complete <= '1';
end if;
if seen_phy_init_complete /= '1' then -- if not initialised the phy hold in reset
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
else
if enable_odt = '0' then
v_seq_ac_mux := mask(c_seq_addr_cmd_config, v_seq_ac_mux, odt, '0');
end if;
unpack_addr_cmd_vector (
c_seq_addr_cmd_config,
v_seq_ac_mux,
seq_ac_addr,
seq_ac_ba,
seq_ac_cas_n,
seq_ac_ras_n,
seq_ac_we_n,
seq_ac_cke,
seq_ac_cs_n,
seq_ac_odt,
seq_ac_rst_n);
end if;
end if;
end process;
end block;
-- register dgb_ac_access_gnt signal to ensure ODT set correctly in dgrb and dgwb prior to a read or write operation
process(clk, rst_n)
begin
if rst_n = '0' then
dgb_ac_access_gnt_r <= '0';
elsif rising_edge(clk) then
dgb_ac_access_gnt_r <= dgb_ac_access_gnt;
end if;
end process;
-- multiplex access request from dgrb/dgwb to admin block with checking for multiple accesses
process (dgrb_ac_access_req, dgwb_ac_access_req)
begin
dgb_ac_access_req <= '0';
if dgwb_ac_access_req = '1' and dgrb_ac_access_req = '1' then
report seq_report_prefix & "multiple accesses attempted from DGRB and DGWB to admin block via signals dg.b_ac_access_reg " severity failure;
elsif dgwb_ac_access_req = '1' or dgrb_ac_access_req = '1' then
dgb_ac_access_req <= '1';
end if;
end process;
rdv_poa_blk : block
-- signals to control static setup of ctl_rdata_valid signal for instant on mode:
constant c_static_rdv_offset : integer := c_preset_cal_setup.rdv_lat; -- required change in RDV latency (should always be > 0)
signal static_rdv_offset : natural range 0 to abs(c_static_rdv_offset); -- signal to count # RDV shifts
constant c_dly_rdv_set : natural := 7; -- delay between RDV shifts
signal dly_rdv_inc_dec : std_logic; -- 1 = inc, 0 = dec
signal rdv_set_delay : natural range 0 to c_dly_rdv_set; -- signal to delay RDV shifts
-- same for poa protection
constant c_static_poa_offset : integer := c_preset_cal_setup.poa_lat;
signal static_poa_offset : natural range 0 to abs(c_static_poa_offset);
constant c_dly_poa_set : natural := 7;
signal dly_poa_inc_dec : std_logic;
signal poa_set_delay : natural range 0 to c_dly_poa_set;
-- function to abstract increment or decrement checking
function set_inc_dec(offset : integer) return std_logic is
begin
if offset < 0 then
return '1';
else
return '0';
end if;
end function;
begin
-- register postamble and rdata_valid latencies
-- note: postamble unused for Cyclone-III
-- RDV
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
end if;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- perform static setup of RDV signal
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
else
if static_rdv_offset /= 0 and
rdv_set_delay = 0 then
seq_rdata_valid_lat_dec <= not dly_rdv_inc_dec;
seq_rdata_valid_lat_inc <= dly_rdv_inc_dec;
static_rdv_offset <= static_rdv_offset - 1;
rdv_set_delay <= c_dly_rdv_set;
else -- once conplete pass through internal signals
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
if rdv_set_delay /= 0 then
rdv_set_delay <= rdv_set_delay - 1;
end if;
end if;
else -- no static setup
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
end if;
end process;
-- count number of RDV adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
rdv_adjustments <= 0;
elsif rising_edge(clk) then
if seq_rdata_valid_lat_dec_int = '1' then
rdv_adjustments <= rdv_adjustments + 1;
end if;
if seq_rdata_valid_lat_inc_int = '1' then
if rdv_adjustments = 0 then
report seq_report_prefix & " read data valid adjustment wrap around detected - more increments than decrements" severity failure;
else
rdv_adjustments <= rdv_adjustments - 1;
end if;
end if;
end if;
end process;
-- POA protection
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
end if;
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- static setup
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
else
if static_poa_offset /= 0 and
poa_set_delay = 0 then
seq_poa_lat_dec_1x <= (others => not(dly_poa_inc_dec));
seq_poa_lat_inc_1x <= (others => dly_poa_inc_dec);
static_poa_offset <= static_poa_offset - 1;
poa_set_delay <= c_dly_poa_set;
else
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
if poa_set_delay /= 0 then
poa_set_delay <= poa_set_delay - 1;
end if;
end if;
else -- no static setup
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
end if;
end process;
-- count POA protection adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
poa_adjustments <= 0;
elsif rising_edge(clk) then
if seq_poa_lat_dec_1x_int(0) = '1' then
poa_adjustments <= poa_adjustments + 1;
end if;
if seq_poa_lat_inc_1x_int(0) = '1' then
if poa_adjustments = 0 then
report seq_report_prefix & " postamble adjustment wrap around detected - more increments than decrements" severity failure;
else
poa_adjustments <= poa_adjustments - 1;
end if;
end if;
end if;
end process;
end block;
-- register output fail/success signals - avoiding optimisation out
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= ctl_init_fail_int;
ctl_init_success <= ctl_init_success_int;
end if;
end process;
-- ctl_cal_byte_lanes register
-- seq_rdp_reset_req_n - when ctl_recalibrate_req issued
process(clk,rst_n)
begin
if rst_n = '0' then
seq_rdp_reset_req_n <= '0';
ctl_cal_byte_lanes_r <= (others => '1');
elsif rising_edge(clk) then
ctl_cal_byte_lanes_r <= not ctl_cal_byte_lanes;
if ctl_recalibrate_req = '1' then
seq_rdp_reset_req_n <= '0';
else
if ctrl_broadcast.command = cmd_rrp_sweep or
SIM_TIME_REDUCTIONS = 1 then
seq_rdp_reset_req_n <= '1';
end if;
end if;
end if;
end process;
-- register 1t addr/cmd and odt latency outputs
process(clk, rst_n)
begin
if rst_n = '0' then
seq_ac_add_1t_ac_lat_internal <= '0';
seq_ac_add_1t_odt_lat_internal <= '0';
seq_ac_add_2t <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then
seq_ac_add_1t_ac_lat_internal <= c_preset_cal_setup.ac_1t;
seq_ac_add_1t_odt_lat_internal <= c_preset_cal_setup.ac_1t;
else
seq_ac_add_1t_ac_lat_internal <= int_ac_nt(0);
seq_ac_add_1t_odt_lat_internal <= int_ac_nt(0);
end if;
seq_ac_add_2t <= '0';
end if;
end process;
-- override write datapath signal generation
process(dgwb_wdp_override, dgrb_wdp_override, ctl_init_success_int, ctl_init_fail_int)
begin
if ctl_init_success_int = '0' and ctl_init_fail_int = '0' then -- if calibrating
seq_wdp_ovride <= dgwb_wdp_override or dgrb_wdp_override;
else
seq_wdp_ovride <= '0';
end if;
end process;
-- output write/read latency (override with preset values when sim time reductions equals 1
seq_ctl_wlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.wlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_wlat_int;
seq_ctl_rlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.rlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_rlat_int;
process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_phs_shift_busy_r <= '0';
seq_pll_phs_shift_busy_ccd <= '0';
elsif rising_edge(clk) then
seq_pll_phs_shift_busy_r <= seq_pll_phs_shift_busy;
seq_pll_phs_shift_busy_ccd <= seq_pll_phs_shift_busy_r;
end if;
end process;
pll_ctrl: block
-- static resync setup variables for sim time reductions
signal static_rst_offset : natural range 0 to 2*PLL_STEPS_PER_CYCLE;
signal phs_shft_busy_1r : std_logic;
signal pll_set_delay : natural range 100 downto 0; -- wait 100 clock cycles for clk to be stable before setting resync phase
-- pll signal generation
signal mmi_pll_active : boolean;
signal seq_pll_phs_shift_busy_ccd_1t : std_logic;
begin
-- multiplex ppl interface between dgrb and mmi blocks
-- plus static setup of rsc phase to a known 'good' condition
process(clk,rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
seq_pll_select <= (others => '0');
dgrb_phs_shft_busy <= '0';
-- static resync setup variables for sim time reductions
if SIM_TIME_REDUCTIONS = 1 then
static_rst_offset <= c_preset_codvw_phase;
else
static_rst_offset <= 0;
end if;
phs_shft_busy_1r <= '0';
pll_set_delay <= 100;
elsif rising_edge(clk) then
dgrb_phs_shft_busy <= '0';
if static_rst_offset /= 0 and -- not finished decrementing
pll_set_delay = 0 and -- initial reset period over
SIM_TIME_REDUCTIONS = 1 then -- in reduce sim time mode (optimse logic away when not in this mode)
seq_pll_inc_dec_n <= '1';
seq_pll_start_reconfig <= '1';
seq_pll_select <= pll_resync_clk_index;
if seq_pll_phs_shift_busy_ccd = '1' then -- no metastability hardening needed in simulation
-- PLL phase shift started - so stop requesting a shift
seq_pll_start_reconfig <= '0';
end if;
if seq_pll_phs_shift_busy_ccd = '0' and phs_shft_busy_1r = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
static_rst_offset <= static_rst_offset - 1;
seq_pll_start_reconfig <= '0';
end if;
phs_shft_busy_1r <= seq_pll_phs_shift_busy_ccd;
else
if ctrl_iram_push.active_block = ret_dgrb then
seq_pll_inc_dec_n <= dgrb_pll_inc_dec_n;
seq_pll_start_reconfig <= dgrb_pll_start_reconfig;
seq_pll_select <= dgrb_pll_select;
dgrb_phs_shft_busy <= seq_pll_phs_shift_busy_ccd;
else
seq_pll_inc_dec_n <= mmi_pll_inc_dec_n;
seq_pll_start_reconfig <= mmi_pll_start_reconfig;
seq_pll_select <= mmi_pll_select;
end if;
end if;
if pll_set_delay /= 0 then
pll_set_delay <= pll_set_delay - 1;
end if;
if ctl_recalibrate_req = '1' then
pll_set_delay <= 100;
end if;
end if;
end process;
-- generate mmi pll signals
process (clk, rst_n)
begin
if rst_n = '0' then
pll_mmi.pll_busy <= '0';
pll_mmi.err <= (others => '0');
mmi_pll_inc_dec_n <= '0';
mmi_pll_start_reconfig <= '0';
mmi_pll_select <= (others => '0');
mmi_pll_active <= false;
seq_pll_phs_shift_busy_ccd_1t <= '0';
elsif rising_edge(clk) then
if mmi_pll_active = true then
pll_mmi.pll_busy <= '1';
else
pll_mmi.pll_busy <= mmi_pll.pll_phs_shft_up_wc or mmi_pll.pll_phs_shft_dn_wc;
end if;
if pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' then
pll_mmi.err <= "01";
elsif pll_mmi.err = "00" and mmi_pll_active = true then
pll_mmi.err <= "10";
elsif pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' and mmi_pll_active = true then
pll_mmi.err <= "11";
end if;
if mmi_pll.pll_phs_shft_up_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '1';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif mmi_pll.pll_phs_shft_dn_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '0';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif seq_pll_phs_shift_busy_ccd_1t = '1' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '0';
mmi_pll_active <= false;
elsif mmi_pll_active = true and mmi_pll_start_reconfig = '0' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '1';
elsif seq_pll_phs_shift_busy_ccd_1t = '0' and seq_pll_phs_shift_busy_ccd = '1' then
mmi_pll_start_reconfig <= '0';
end if;
seq_pll_phs_shift_busy_ccd_1t <= seq_pll_phs_shift_busy_ccd;
end if;
end process;
end block; -- pll_ctrl
--synopsys synthesis_off
reporting : block
function pass_or_fail_report( cal_success : in std_logic;
cal_fail : in std_logic
) return string is
begin
if cal_success = '1' and cal_fail = '1' then
return "unknown state cal_fail and cal_success both high";
end if;
if cal_success = '1' then
return "PASSED";
end if;
if cal_fail = '1' then
return "FAILED";
end if;
return "calibration report run whilst sequencer is still calibrating";
end function;
function is_stage_disabled ( stage_name : in string;
stage_dis : in std_logic
) return string is
begin
if stage_dis = '0' then
return "";
else
return stage_name & " stage is disabled" & LF;
end if;
end function;
function disabled_stages ( capabilities : in std_logic_vector
) return string is
begin
return is_stage_disabled("all calibration", c_capabilities(c_hl_css_reg_cal_dis_bit)) &
is_stage_disabled("initialisation", c_capabilities(c_hl_css_reg_phy_initialise_dis_bit)) &
is_stage_disabled("DRAM initialisation", c_capabilities(c_hl_css_reg_init_dram_dis_bit)) &
is_stage_disabled("iram header write", c_capabilities(c_hl_css_reg_write_ihi_dis_bit)) &
is_stage_disabled("burst training pattern write", c_capabilities(c_hl_css_reg_write_btp_dis_bit)) &
is_stage_disabled("more training pattern (MTP) write", c_capabilities(c_hl_css_reg_write_mtp_dis_bit)) &
is_stage_disabled("check MTP pattern alignment calculation", c_capabilities(c_hl_css_reg_read_mtp_dis_bit)) &
is_stage_disabled("read resynch phase reset stage", c_capabilities(c_hl_css_reg_rrp_reset_dis_bit)) &
is_stage_disabled("read resynch phase sweep stage", c_capabilities(c_hl_css_reg_rrp_sweep_dis_bit)) &
is_stage_disabled("read resynch phase seek stage (set phase)", c_capabilities(c_hl_css_reg_rrp_seek_dis_bit)) &
is_stage_disabled("read data valid window setup", c_capabilities(c_hl_css_reg_rdv_dis_bit)) &
is_stage_disabled("postamble calibration", c_capabilities(c_hl_css_reg_poa_dis_bit)) &
is_stage_disabled("write latency timing calc", c_capabilities(c_hl_css_reg_was_dis_bit)) &
is_stage_disabled("advertise read latency", c_capabilities(c_hl_css_reg_adv_rd_lat_dis_bit)) &
is_stage_disabled("advertise write latency", c_capabilities(c_hl_css_reg_adv_wr_lat_dis_bit)) &
is_stage_disabled("write customer mode register settings", c_capabilities(c_hl_css_reg_prep_customer_mr_setup_dis_bit)) &
is_stage_disabled("tracking", c_capabilities(c_hl_css_reg_tracking_dis_bit));
end function;
function ac_nt_report( ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal) return string
is
variable v_ac_nt : std_logic_vector(0 downto 0);
begin
if SIM_TIME_REDUCTIONS = 1 then
v_ac_nt(0) := preset_cal_setup.ac_1t;
if v_ac_nt(0) = '1' then
return "-- statically set address and command 1T delay: add 1T delay" & LF;
else
return "-- statically set address and command 1T delay: no 1T delay" & LF;
end if;
else
v_ac_nt(0) := ac_nt(0);
if dgrb_ctrl_ac_nt_good = '1' then
if v_ac_nt(0) = '1' then
return "-- chosen address and command 1T delay: add 1T delay" & LF;
else
return "-- chosen address and command 1T delay: no 1T delay" & LF;
end if;
else
return "-- no valid address and command phase chosen (calibration FAILED)" & LF;
end if;
end if;
end function;
function read_resync_report ( codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "-- read resynch phase static setup (no calibration run) report:" & LF &
" -- statically set centre of data valid window phase : " & natural'image(preset_cal_setup.codvw_phase) & LF &
" -- statically set centre of data valid window size : " & natural'image(preset_cal_setup.codvw_size) & LF &
" -- statically set read latency (ctl_rlat) : " & natural'image(preset_cal_setup.rlat) & LF &
" -- statically set write latency (ctl_wlat) : " & natural'image(preset_cal_setup.wlat) & LF &
" -- note: this mode only works for simulation and sets resync phase" & LF &
" to a known good operating condition for no test bench" & LF &
" delays on mem_dq signal" & LF;
else
return "-- PHY read latency (ctl_rlat) is : " & natural'image(to_integer(unsigned(ctl_rlat))) & LF &
"-- address/command to PHY write latency (ctl_wlat) is : " & natural'image(to_integer(unsigned(ctl_wlat))) & LF &
"-- read resynch phase calibration report:" & LF &
" -- calibrated centre of data valid window phase : " & natural'image(to_integer(unsigned(codvw_phase))) & LF &
" -- calibrated centre of data valid window size : " & natural'image(to_integer(unsigned(codvw_size))) & LF;
end if;
end function;
function poa_rdv_adjust_report( poa_adjust : in natural;
rdv_adjust : in natural;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "Statically set poa and rdv (adjustments from reset value):" & LF &
"poa 'dec' adjustments = " & natural'image(preset_cal_setup.poa_lat) & LF &
"rdv 'dec' adjustments = " & natural'image(preset_cal_setup.rdv_lat) & LF;
else
return "poa 'dec' adjustments = " & natural'image(poa_adjust) & LF &
"rdv 'dec' adjustments = " & natural'image(rdv_adjust) & LF;
end if;
end function;
function calibration_report ( capabilities : in std_logic_vector;
cal_success : in std_logic;
cal_fail : in std_logic;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal;
poa_adjust : in natural;
rdv_adjust : in natural) return string
is
begin
return seq_report_prefix & " report..." & LF &
"-----------------------------------------------------------------------" & LF &
"-- **** ALTMEMPHY CALIBRATION has completed ****" & LF &
"-- Status:" & LF &
"-- calibration has : " & pass_or_fail_report(cal_success, cal_fail) & LF &
read_resync_report(codvw_phase, codvw_size, ctl_rlat, ctl_wlat, preset_cal_setup) &
ac_nt_report(ac_nt, dgrb_ctrl_ac_nt_good, preset_cal_setup) &
poa_rdv_adjust_report(poa_adjust, rdv_adjust, preset_cal_setup) &
disabled_stages(capabilities) &
"-----------------------------------------------------------------------";
end function;
begin
-- -------------------------------------------------------
-- calibration result reporting
-- -------------------------------------------------------
process(rst_n, clk)
variable v_reports_written : std_logic;
variable v_cal_request_r : std_logic;
variable v_rewrite_report : std_logic;
begin
if rst_n = '0' then
v_reports_written := '0';
v_cal_request_r := '0';
v_rewrite_report := '0';
elsif Rising_Edge(clk) then
if v_reports_written = '0' then
if ctl_init_success_int = '1' or ctl_init_fail_int = '1' then
v_reports_written := '1';
report calibration_report(c_capabilities,
ctl_init_success_int,
ctl_init_fail_int,
seq_ctl_rlat_int,
seq_ctl_wlat_int,
dgrb_mmi.cal_codvw_phase,
dgrb_mmi.cal_codvw_size,
int_ac_nt,
dgrb_ctrl_ac_nt_good,
c_preset_cal_setup,
poa_adjustments,
rdv_adjustments
) severity note;
end if;
end if;
-- if recalibrate request triggered watch for cal success / fail going low and re-trigger report writing
if ctl_recalibrate_req = '1' and v_cal_request_r = '0' then
v_rewrite_report := '1';
end if;
if v_rewrite_report = '1' and ctl_init_success_int = '0' and ctl_init_fail_int = '0' then
v_reports_written := '0';
v_rewrite_report := '0';
end if;
v_cal_request_r := ctl_recalibrate_req;
end if;
end process;
-- -------------------------------------------------------
-- capabilities vector reporting and coarse PHY setup sanity checks
-- -------------------------------------------------------
process(rst_n, clk)
variable reports_written : std_logic;
begin
if rst_n = '0' then
reports_written := '0';
elsif Rising_Edge(clk) then
if reports_written = '0' then
reports_written := '1';
if MEM_IF_MEMTYPE="DDR" or MEM_IF_MEMTYPE="DDR2" or MEM_IF_MEMTYPE="DDR3" then
if DWIDTH_RATIO = 2 or DWIDTH_RATIO = 4 then
report disabled_stages(c_capabilities) severity note;
else
report seq_report_prefix & "unsupported rate for non-levelling AFI PHY sequencer - only full- or half-rate supported" severity warning;
end if;
else
report seq_report_prefix & "memory type " & MEM_IF_MEMTYPE & " is not supported in non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end if;
end process;
end block; -- reporting
--synopsys synthesis_on
end architecture struct;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_ch_08_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
--library ieee; use ieee.std_logic_1164.std_ulogic;
library ieee; use ieee.std_logic_1164.all;
entity logic_block is
port ( a, b : in std_ulogic;
y, z : out std_ulogic );
end entity logic_block;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_ch_08_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
--library ieee; use ieee.std_logic_1164.std_ulogic;
library ieee; use ieee.std_logic_1164.all;
entity logic_block is
port ( a, b : in std_ulogic;
y, z : out std_ulogic );
end entity logic_block;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_ch_08_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
--library ieee; use ieee.std_logic_1164.std_ulogic;
library ieee; use ieee.std_logic_1164.all;
entity logic_block is
port ( a, b : in std_ulogic;
y, z : out std_ulogic );
end entity logic_block;
|
library ieee;
use ieee.std_logic_1164.all;
entity ent is
end entity ent;
architecture a of ent is
signal clk : std_logic := '0';
signal check_stable_in_1 : std_logic_vector(1 to 5) := "00000";
alias check_stable_start_event_1 : std_logic is check_stable_in_1(1);
alias check_stable_end_event_1 : std_logic is check_stable_in_1(2);
alias check_stable_expr_1 : std_logic_vector(2 downto 0) is check_stable_in_1(3 to 5);
signal check_stable_en_1 : std_logic;
signal en, start_event, end_event, expr : std_logic := '1';
procedure check_stable(
signal clock : in std_logic;
signal en : in std_logic;
signal start_event : in std_logic;
signal end_event : in std_logic;
signal expr : in std_logic_vector) is
begin
wait until (falling_edge(clock) or rising_edge(clock)) and (to_x01(en) = '1');
end;
begin
clock : process is
begin
clk <= '1', '0' after 5 ns;
wait;
end process clock;
check_stable_1 : check_stable(clk,
check_stable_en_1,
check_stable_start_event_1,
check_stable_end_event_1,
check_stable_expr_1);
end architecture;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:50:54 11/19/2013
-- Design Name:
-- Module Name: C:/Users/etingi01/Mips32_948282_19.11.2013/My_SignExtend_tb_948282.vhd
-- Project Name: Mips32_948282_19.11.2013
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: My_SignExtend_948282
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY My_SignExtend_tb_948282 IS
END My_SignExtend_tb_948282;
ARCHITECTURE behavior OF My_SignExtend_tb_948282 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT My_SignExtend_948282
PORT(
Sign_In : IN std_logic_vector(15 downto 0);
Sign_Out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Sign_In : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal Sign_Out : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: My_SignExtend_948282 PORT MAP (
Sign_In => Sign_In,
Sign_Out => Sign_Out
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
Sign_In<="1100011110011001";
wait;
end process;
END;
|
PACKAGE test_pkg IS
TYPE string_array_t IS ARRAY (natural RANGE <>) OF string;
END test_pkg;
ENTITY test IS
END ENTITY test;
LIBRARY work;
USE work.test_pkg.string_array_t;
ARCHITECTURE rtl OF test IS
BEGIN
END ARCHITECTURE rtl;
|
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | 25 Oct. 2012 --
--======================================================--
--******************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--******************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- float
library fp_lib;
use fp_lib.float_pkg.all;
----------------------------------------------------------
-- Parameterized subtractor --
----------------------------------------------------------
entity parameterized_subtractor is
generic
(
bits : integer := 0
);
port
(
--inputs
A : in std_logic_vector(bits-1 downto 0);
B : in std_logic_vector(bits-1 downto 0);
--outputs
O : out std_logic_vector(bits-1 downto 0) := (others=>'0')
);
end parameterized_subtractor;
----------------------------------------------------------
-- Parameterized subtractor --
----------------------------------------------------------
architecture parameterized_subtractor_arch of parameterized_subtractor is
begin
--subtraction
O <= A - B;
end parameterized_subtractor_arch; -- end of architecture
|
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | 25 Oct. 2012 --
--======================================================--
--******************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--******************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- float
library fp_lib;
use fp_lib.float_pkg.all;
----------------------------------------------------------
-- Parameterized subtractor --
----------------------------------------------------------
entity parameterized_subtractor is
generic
(
bits : integer := 0
);
port
(
--inputs
A : in std_logic_vector(bits-1 downto 0);
B : in std_logic_vector(bits-1 downto 0);
--outputs
O : out std_logic_vector(bits-1 downto 0) := (others=>'0')
);
end parameterized_subtractor;
----------------------------------------------------------
-- Parameterized subtractor --
----------------------------------------------------------
architecture parameterized_subtractor_arch of parameterized_subtractor is
begin
--subtraction
O <= A - B;
end parameterized_subtractor_arch; -- end of architecture
|
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | 25 Oct. 2012 --
--======================================================--
--******************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--******************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- float
library fp_lib;
use fp_lib.float_pkg.all;
----------------------------------------------------------
-- Parameterized subtractor --
----------------------------------------------------------
entity parameterized_subtractor is
generic
(
bits : integer := 0
);
port
(
--inputs
A : in std_logic_vector(bits-1 downto 0);
B : in std_logic_vector(bits-1 downto 0);
--outputs
O : out std_logic_vector(bits-1 downto 0) := (others=>'0')
);
end parameterized_subtractor;
----------------------------------------------------------
-- Parameterized subtractor --
----------------------------------------------------------
architecture parameterized_subtractor_arch of parameterized_subtractor is
begin
--subtraction
O <= A - B;
end parameterized_subtractor_arch; -- end of architecture
|
---------------------------------------------------
-- Alan Daly 2009(c)
-- AtomIC project
-- minimal implementation of an 8255
-- just enough for the machine to function
---------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity I82C55 is
port (
I_ADDR : in std_logic_vector(1 downto 0); -- A1-A0
I_DATA : in std_logic_vector(7 downto 0); -- D7-D0
O_DATA : out std_logic_vector(7 downto 0);
CS_H : in std_logic;
WR_L : in std_logic;
O_PA : out std_logic_vector(7 downto 0);
I_PB : in std_logic_vector(7 downto 0);
I_PC : in std_logic_vector(3 downto 0);
O_PC : out std_logic_vector(3 downto 0);
RESET : in std_logic;
ENA : in std_logic; -- (CPU) clk enable
CLK : in std_logic);
end;
architecture RTL of I82C55 is
-- registers
signal r_porta : std_logic_vector(7 downto 0);
signal r_portb : std_logic_vector(7 downto 0);
signal l_portc : std_logic_vector(3 downto 0);
signal h_portc : std_logic_vector(3 downto 0);
signal ctrl_reg : std_logic_vector(7 downto 0);
begin
p_write_reg_reset : process(RESET, CLK)
begin
if (RESET = '0') then
r_porta <= x"00";
r_portb <= x"00";
l_portc <= x"0";
h_portc <= x"0";
ctrl_reg <= x"00";
elsif rising_edge(CLK) then
if ENA = '1' then
O_PA <= r_porta;
r_portb <= I_PB;
h_portc <= I_PC;
O_PC <= l_portc;
if (CS_H = '1') then
if (WR_L = '0') then
case I_ADDR is
when "00" => r_porta <= I_DATA;
--when "01" => r_portb <= I_DATA;
when "10" => l_portc <= I_DATA (3 downto 0);
when "11" => if (I_DATA(7) = '0') then -- set/clr
l_portc(2) <= I_DATA(0);
else
ctrl_reg <= I_DATA;
end if;
when others => null;
end case;
else -- read ports
case I_ADDR is
when "00" => O_DATA <= r_porta;
when "01" => O_DATA <= r_portb;
when "10" => O_DATA <= h_portc & l_portc;
when "11" => O_DATA <= ctrl_reg;
when others => null;
end case;
end if;
end if;
end if;
end if;
end process;
end architecture RTL;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1;
ENTITY fifo_generator_0 IS
PORT (
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC
);
END fifo_generator_0;
ARCHITECTURE fifo_generator_0_arch OF fifo_generator_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_0_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_0_1 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_0_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 master_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 slave_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 slave_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
BEGIN
U0 : fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 18,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 18,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 1,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 1,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "4kx4",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1022,
C_PROG_FULL_THRESH_NEGATE_VAL => 1021,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 1,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 1,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 1,
C_AXIS_TDATA_WIDTH => 32,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 4,
C_AXIS_TKEEP_WIDTH => 4,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 12,
C_IMPLEMENTATION_TYPE_WDCH => 11,
C_IMPLEMENTATION_TYPE_WRCH => 12,
C_IMPLEMENTATION_TYPE_RACH => 12,
C_IMPLEMENTATION_TYPE_RDCH => 11,
C_IMPLEMENTATION_TYPE_AXIS => 11,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx36",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 41,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 13,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1021,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 13,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 13,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1021,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1021,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 18)),
wr_en => '0',
rd_en => '0',
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
m_aclk => m_aclk,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tkeep => s_axis_tkeep,
s_axis_tlast => s_axis_tlast,
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => s_axis_tuser,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tkeep => m_axis_tkeep,
m_axis_tlast => m_axis_tlast,
m_axis_tuser => m_axis_tuser,
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_overflow => axis_overflow,
axis_underflow => axis_underflow
);
END fifo_generator_0_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2303.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p37n01i02303ent IS
END c07s02b06x00p37n01i02303ent;
ARCHITECTURE c07s02b06x00p37n01i02303arch OF c07s02b06x00p37n01i02303ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
BEGIN
-- Test dividing user-defined physical type values.
assert ((1 cm / 1 mm) = 10);
assert ((1 mm / 1 um) = 1000);
assert ((1 um / 1 nm) = 1000);
assert ((1 nm / 1 A) = 10);
wait for 5 ns;
assert NOT( ((1 cm / 1 mm) = 10) and
((1 mm / 1 um) = 1000) and
((1 um / 1 nm) = 1000) and
((1 nm / 1 A) = 10) )
report "***PASSED TEST: c07s02b06x00p37n01i02303"
severity NOTE;
assert ( ((1 cm / 1 mm) = 10) and
((1 mm / 1 um) = 1000) and
((1 um / 1 nm) = 1000) and
((1 nm / 1 A) = 10) )
report "***FAILED TEST: c07s02b06x00p37n01i02303 - Division of a physical type by another physical type (user-defined) test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p37n01i02303arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2303.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p37n01i02303ent IS
END c07s02b06x00p37n01i02303ent;
ARCHITECTURE c07s02b06x00p37n01i02303arch OF c07s02b06x00p37n01i02303ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
BEGIN
-- Test dividing user-defined physical type values.
assert ((1 cm / 1 mm) = 10);
assert ((1 mm / 1 um) = 1000);
assert ((1 um / 1 nm) = 1000);
assert ((1 nm / 1 A) = 10);
wait for 5 ns;
assert NOT( ((1 cm / 1 mm) = 10) and
((1 mm / 1 um) = 1000) and
((1 um / 1 nm) = 1000) and
((1 nm / 1 A) = 10) )
report "***PASSED TEST: c07s02b06x00p37n01i02303"
severity NOTE;
assert ( ((1 cm / 1 mm) = 10) and
((1 mm / 1 um) = 1000) and
((1 um / 1 nm) = 1000) and
((1 nm / 1 A) = 10) )
report "***FAILED TEST: c07s02b06x00p37n01i02303 - Division of a physical type by another physical type (user-defined) test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p37n01i02303arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2303.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p37n01i02303ent IS
END c07s02b06x00p37n01i02303ent;
ARCHITECTURE c07s02b06x00p37n01i02303arch OF c07s02b06x00p37n01i02303ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
BEGIN
-- Test dividing user-defined physical type values.
assert ((1 cm / 1 mm) = 10);
assert ((1 mm / 1 um) = 1000);
assert ((1 um / 1 nm) = 1000);
assert ((1 nm / 1 A) = 10);
wait for 5 ns;
assert NOT( ((1 cm / 1 mm) = 10) and
((1 mm / 1 um) = 1000) and
((1 um / 1 nm) = 1000) and
((1 nm / 1 A) = 10) )
report "***PASSED TEST: c07s02b06x00p37n01i02303"
severity NOTE;
assert ( ((1 cm / 1 mm) = 10) and
((1 mm / 1 um) = 1000) and
((1 um / 1 nm) = 1000) and
((1 nm / 1 A) = 10) )
report "***FAILED TEST: c07s02b06x00p37n01i02303 - Division of a physical type by another physical type (user-defined) test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p37n01i02303arch;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY MemFaces IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(799 DOWNTO 0)
);
END MemFaces;
ARCHITECTURE MemFaces_arch OF MemFaces IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF MemFaces_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(799 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(799 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(799 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(799 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(799 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(799 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF MemFaces_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF MemFaces_arch : ARCHITECTURE IS "MemFaces,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF MemFaces_arch: ARCHITECTURE IS "MemFaces,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=MemFaces.mif,C_INIT_FILE=MemFaces.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=800,C_READ_WIDTH_A=800,C_WRITE_DEPTH_A=720,C_READ_DEPTH_A=720,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=800,C_READ_WIDTH_B=800,C_WRITE_DEPTH_B=720,C_READ_DEPTH_B=720,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=22,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 60.4532 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "MemFaces.mif",
C_INIT_FILE => "MemFaces.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 800,
C_READ_WIDTH_A => 800,
C_WRITE_DEPTH_A => 720,
C_READ_DEPTH_A => 720,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 800,
C_READ_WIDTH_B => 800,
C_WRITE_DEPTH_B => 720,
C_READ_DEPTH_B => 720,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "22",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 60.4532 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 800)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 800)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 800)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END MemFaces_arch;
|
-- multiple1902 <[email protected]>
-- Released under GNU GPL v3, or later.
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use std.textio.all;
entity bfp is
port (ins_in : in std_logic_vector(2 downto 0);
data_in : in std_logic_vector(7 downto 0);
clk : in std_logic;
data_out: out std_logic_vector(7 downto 0);
halt : out std_logic -- no semicolon here!
);
end bfp;
architecture behv of bfp is
subtype bfp_instruction is std_logic_vector(2 downto 0);
subtype bfp_data is std_logic_vector(7 downto 0);
type insm_type is array(4095 downto 0) of bfp_instruction;
type datam_type is array(4095 downto 0) of bfp_data;
type stackm_type is array(4095 downto 0) of integer range 0 to 4095;
signal stage: integer range 0 to 2 := 0;
signal pc: integer range 0 to 4095 := 0;
signal ic: integer range 0 to 4095 := 0;
signal P: integer range 0 to 4095 := 0;
signal st: integer range 0 to 4095 := 0;
signal insm: insm_type;
signal datam: datam_type;
signal stackm: stackm_type;
begin
process(clk)
variable l: line;
variable bv: bit_vector(2 downto 0);
variable bv1: bit_vector(7 downto 0);
variable tst, tpc: integer;
begin
if clk = '1' then
case stage is
when 0 =>
-- input instructions
insm(ic) <= ins_in;
ic <= ic + 1;
bv := to_bitvector(ins_in);
if ieee.std_logic_1164."="(ins_in, "ZZZ") then
stage <= 1;
halt <= '0';
st <= 0;
for i in 0 to 4095 loop
datam(i) <= "00000000";
end loop;
end if;
when 1 =>
-- running
data_out <= "ZZZZZZZZ";
case insm(pc) is
when "000" =>
P <= P + 1;
pc <= pc + 1;
when "001" =>
P <= P - 1;
pc <= pc + 1;
when "010" =>
datam(P) <= datam(P) + 1;
pc <= pc + 1;
when "011" =>
datam(P) <= datam(P) - 1;
pc <= pc + 1;
when "100" =>
bv1 := to_bitvector(datam(P));
if ieee.std_logic_unsigned."/="(datam(P), "00000000") then
stackm(st) <= pc;
st <= st + 1;
end if;
if ieee.std_logic_1164."="(datam(P), "00000000") then
tst:=1;
tpc := pc;
while(tst/=0) loop
tpc := tpc + 1;
if ieee.std_logic_1164."="(insm(tpc), "100") then
tst := tst + 1;
end if;
if ieee.std_logic_1164."="(insm(tpc), "101") then
tst := tst - 1;
end if;
end loop;
pc <= tpc;
end if;
pc <= pc + 1;
when "101" =>
pc <= pc + 1;
if ieee.std_logic_unsigned."/="(datam(P), "00000000") then
pc <= stackm(st - 1);
end if;
st <= st - 1;
when "110" =>
data_out <= datam(P);
pc <= pc + 1;
when others =>
pc <= pc + 1;
end case;
if pc>ic then
stage <= 2;
end if;
when 2 =>
-- halt
halt <= '1';
end case;
end if;
end process;
end behv;
|
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
-- Violation below
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32
);
PORT (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrphy_datapath
-- File: ddrphy_datapath.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Generic DDR/DDR2 PHY data path (digital part of phy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ddrphy_datapath is
generic (
regtech: integer := 0;
dbits: integer;
abits: integer;
bankbits: integer range 2 to 3 := 2;
ncs: integer;
nclk: integer;
-- Enable extra resync stage clocked by clkresync
resync: integer range 0 to 2 := 0
);
port (
clk0: in std_ulogic;
clk90: in std_ulogic;
clk180: in std_ulogic;
clk270: in std_ulogic;
clkresync: in std_ulogic;
ddr_clk: out std_logic_vector(nclk-1 downto 0);
ddr_clkb: out std_logic_vector(nclk-1 downto 0);
ddr_dq_in: in std_logic_vector(dbits-1 downto 0);
ddr_dq_out: out std_logic_vector(dbits-1 downto 0);
ddr_dq_oen: out std_logic_vector(dbits-1 downto 0);
ddr_dqs_in90: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_in90n: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_out: out std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_oen: out std_logic_vector(dbits/8-1 downto 0);
ddr_cke: out std_logic_vector(ncs-1 downto 0);
ddr_csb: out std_logic_vector(ncs-1 downto 0);
ddr_web: out std_ulogic;
ddr_rasb: out std_ulogic;
ddr_casb: out std_ulogic;
ddr_ad: out std_logic_vector(abits-1 downto 0);
ddr_ba: out std_logic_vector(bankbits-1 downto 0);
ddr_dm: out std_logic_vector(dbits/8-1 downto 0);
ddr_odt: out std_logic_vector(ncs-1 downto 0);
-- Control signals synchronous to clk0
dqin: out std_logic_vector(dbits*2-1 downto 0);
dqout: in std_logic_vector(dbits*2-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector (bankbits-1 downto 0);
dm : in std_logic_vector (dbits/4-1 downto 0);
oen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0); -- Clk enable control signal to memory
odt : in std_logic_vector(ncs-1 downto 0);
dqs_en : in std_ulogic; -- Run dqs strobe (active low)
dqs_oen : in std_ulogic; -- DQS output enable (active low)
ddrclk_en : in std_logic_vector(nclk-1 downto 0) -- Enable/stop ddr_clk
);
end;
architecture rtl of ddrphy_datapath is
signal vcc,gnd: std_ulogic;
signal dqs_en_inv,dqs_en_inv180: std_ulogic;
signal dqcaptr,dqcaptf: std_logic_vector(dbits-1 downto 0);
signal dqsyncr,dqsyncf: std_logic_vector(dbits-1 downto 0);
begin
vcc <= '1';
gnd <= '0';
-----------------------------------------------------------------------------
-- DDR interface clock signal
-----------------------------------------------------------------------------
-- 90 degree shifted relative to master clock, gated by ddrclk_en
genclk: for x in 0 to nclk-1 generate
clkreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => ddrclk_en(x), d2 => gnd, ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_clk(x));
clkbreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => gnd, d2 => ddrclk_en(x), ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_clkb(x));
end generate;
-----------------------------------------------------------------------------
-- Control signals RAS,CAS,WE,BA,ADDR,CS,ODT,CKE
-----------------------------------------------------------------------------
rasreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => rasn, q => ddr_rasb);
casreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => casn, q => ddr_casb);
wereg: grdff generic map (tech => regtech)
port map (clk => clk0, d => wen, q => ddr_web);
genba: for x in 0 to bankbits-1 generate
bareg: grdff generic map (tech => regtech)
port map (clk => clk0, d => ba(x), q => ddr_ba(x));
end generate;
gencs: for x in 0 to ncs-1 generate
csreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => csn(x), q => ddr_csb(x));
ckereg: grdff generic map (tech => regtech)
port map (clk => clk0, d => cke(x), q => ddr_cke(x));
odtreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => odt(x), q => ddr_odt(x));
end generate;
genaddr: for x in 0 to abits-1 generate
addrreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => addr(x), q => ddr_ad(x));
end generate;
-----------------------------------------------------------------------------
-- Outgoing data, output enable, DQS, DQSOEN, DM
-----------------------------------------------------------------------------
gendqout: for x in 0 to dbits-1 generate
dqoutreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dqout(x+dbits), d2 => dqout(x), ce => vcc,
c1 => clk0, c2 => clk180, r => gnd, s => gnd,
q => ddr_dq_out(x));
dqoenreg: grdff
generic map (tech => regtech)
port map (clk => clk0, d => oen, q => ddr_dq_oen(x));
end generate;
-- dqs_en -> invert -> delay -> +90-deg DDR-regs -> dqs_out
-- In total oen is delayed 5/4 cycles. We use 1/2 cycle delay
-- instead of 1 cycle delay to get better timing margin to DDR regs.
-- DQSOEN is delayed one cycle just like ctrl sigs
dqs_en_inv <= not dqs_en;
dqseninv180reg: grdff
generic map (tech => regtech)
port map (clk => clk180, d => dqs_en_inv, q => dqs_en_inv180);
gendqsout: for x in 0 to dbits/8-1 generate
dqsreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dqs_en_inv180, d2 => gnd, ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_dqs_out(x));
dqsoenreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqs_oen, q => ddr_dqs_oen(x));
end generate;
gendm: for x in 0 to dbits/8-1 generate
dmreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dm(x+dbits/8), d2 => dm(x), ce => vcc,
c1 => clk0, c2 => clk180, r => gnd, s => gnd,
q => ddr_dm(x));
end generate;
-----------------------------------------------------------------------------
-- Incoming data
-----------------------------------------------------------------------------
gendqin: for x in 0 to dbits-1 generate
-- capture using dqs+90
-- Note: The ddr_ireg delivers both edges on c1 rising edge, therefore c1
-- is connected to inverted clock (c1 rising edge == dqs falling edge)
dqcaptreg: ddr_ireg generic map (tech => regtech)
port map (d => ddr_dq_in(x),
c1 => ddr_dqs_in90n(x/8), c2 => ddr_dqs_in90(x/8), ce => vcc, r => gnd, s => gnd,
q1 => dqcaptf(x), q2 => dqcaptr(x));
-- optional extra resync stage
ifresync: if resync=1 generate
genresync: for x in 0 to dbits-1 generate
dqsyncrreg: grdff generic map (tech => regtech)
port map (clk => clkresync, d => dqcaptr(x), q => dqsyncr(x));
dqsyncfreg: grdff generic map (tech => regtech)
port map (clk => clkresync, d => dqcaptf(x), q => dqsyncf(x));
end generate;
end generate;
noresync: if resync/=1 generate
dqsyncr <= dqcaptr;
dqsyncf <= dqcaptf;
end generate;
-- sample in clk0 domain
gensamp: if resync/=2 generate
dqinregr: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqsyncr(x), q => dqin(x+dbits));
dqinregf: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqsyncf(x), q => dqin(x));
end generate;
nosamp: if resync=2 generate
dqin(x+dbits) <= dqsyncr(x);
dqin(x) <= dqsyncf(x);
end generate;
end generate;
end;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:58:26 05/17/2011
-- Design Name:
-- Module Name: C:/Users/Ben/Desktop/Folders/Projects/Personal/Senior Project/FPGA Stuff/OZ3_Mandelbrot/OZ3_Sys_Top_TB.vhd
-- Project Name: OZ3_Mandelbrot
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: OZ3_Sys_Top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY OZ3_Sys_Top_TB IS
END OZ3_Sys_Top_TB;
ARCHITECTURE behavior OF OZ3_Sys_Top_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT OZ3_Sys_Top
PORT(
clk : IN std_logic;
rst : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 40 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: OZ3_Sys_Top PORT MAP (
clk => clk,
rst => rst
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for 1000 ns;
rst <= '0';
wait;
end process;
END;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in vl_logic;
PWDATA : in vl_logic_vector(31 downto 0);
PRDATA_PPE : out vl_logic_vector(31 downto 0);
PREADY_PPE : out vl_logic;
PPE2SSE_PSEL : out vl_logic;
PPE2SSE_PENABLE : out vl_logic;
PPE2SSE_PWRITE : out vl_logic;
PPE2SSE_PADDR : out vl_logic_vector(11 downto 0);
PPE2SSE_PWDATA : out vl_logic_vector(15 downto 0);
PPE2SSE_PRDATA : in vl_logic_vector(15 downto 0);
PPE2SSE_PREADY : in vl_logic;
PPE2SSE_STALL : out vl_logic;
PPE_BUSY : out vl_logic;
SSE_ADC0_RESULTS: in vl_logic;
SSE_ADC1_RESULTS: in vl_logic;
SSE_ADC2_RESULTS: in vl_logic;
ADC0_DATAVALID_rise: in vl_logic;
ADC1_DATAVALID_rise: in vl_logic;
ADC2_DATAVALID_rise: in vl_logic;
ADC0_RESULT : in vl_logic_vector(11 downto 0);
ADC1_RESULT : in vl_logic_vector(11 downto 0);
ADC2_RESULT : in vl_logic_vector(11 downto 0);
ADC0_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC1_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC2_CHNUMBER : in vl_logic_vector(4 downto 0);
PPE_FLAGS0 : out vl_logic_vector(31 downto 0);
PPE_FLAGS1 : out vl_logic_vector(31 downto 0);
PPE_FLAGS2 : out vl_logic_vector(31 downto 0);
PPE_FLAGS3 : out vl_logic_vector(31 downto 0);
PPE_SFFLAGS : out vl_logic_vector(31 downto 0);
ADC0_FIFO_FULL : out vl_logic;
ADC0_FIFO_AFULL : out vl_logic;
ADC1_FIFO_FULL : out vl_logic;
ADC1_FIFO_AFULL : out vl_logic;
ADC2_FIFO_FULL : out vl_logic;
ADC2_FIFO_AFULL : out vl_logic;
ADC0_FIFO_EMPTY : out vl_logic;
ADC1_FIFO_EMPTY : out vl_logic;
ADC2_FIFO_EMPTY : out vl_logic;
PPE_PDMA_DATAOUT_reg_move_target: out vl_logic;
PPE_PDMA_DATAOUT_chan_en: out vl_logic;
PPE_PDMA_DATAOUT_raw_en: out vl_logic;
PPE_PDMA_DATAOUT_tag_en: out vl_logic;
PPE_PDMA_CTRL_reg_move_target: out vl_logic;
xfer_din_mux : out vl_logic_vector(31 downto 0);
CURRENT_ADC_CHAN: out vl_logic_vector(5 downto 0);
TEST_MODE : in vl_logic;
RB_TEST : in vl_logic;
RB_CSBA : in vl_logic;
RB_CSBB : in vl_logic;
RB_RWBA : in vl_logic;
RB_RWBB : in vl_logic;
RB_ADA : in vl_logic_vector(8 downto 0);
RB_ADB : in vl_logic_vector(8 downto 0);
RB_WDA : in vl_logic_vector(31 downto 0);
RB_WDB : in vl_logic_vector(31 downto 0);
RB_RDA : out vl_logic_vector(31 downto 0);
RB_RDB : out vl_logic_vector(31 downto 0)
);
end F2DSS_ACE_PPE;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in vl_logic;
PWDATA : in vl_logic_vector(31 downto 0);
PRDATA_PPE : out vl_logic_vector(31 downto 0);
PREADY_PPE : out vl_logic;
PPE2SSE_PSEL : out vl_logic;
PPE2SSE_PENABLE : out vl_logic;
PPE2SSE_PWRITE : out vl_logic;
PPE2SSE_PADDR : out vl_logic_vector(11 downto 0);
PPE2SSE_PWDATA : out vl_logic_vector(15 downto 0);
PPE2SSE_PRDATA : in vl_logic_vector(15 downto 0);
PPE2SSE_PREADY : in vl_logic;
PPE2SSE_STALL : out vl_logic;
PPE_BUSY : out vl_logic;
SSE_ADC0_RESULTS: in vl_logic;
SSE_ADC1_RESULTS: in vl_logic;
SSE_ADC2_RESULTS: in vl_logic;
ADC0_DATAVALID_rise: in vl_logic;
ADC1_DATAVALID_rise: in vl_logic;
ADC2_DATAVALID_rise: in vl_logic;
ADC0_RESULT : in vl_logic_vector(11 downto 0);
ADC1_RESULT : in vl_logic_vector(11 downto 0);
ADC2_RESULT : in vl_logic_vector(11 downto 0);
ADC0_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC1_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC2_CHNUMBER : in vl_logic_vector(4 downto 0);
PPE_FLAGS0 : out vl_logic_vector(31 downto 0);
PPE_FLAGS1 : out vl_logic_vector(31 downto 0);
PPE_FLAGS2 : out vl_logic_vector(31 downto 0);
PPE_FLAGS3 : out vl_logic_vector(31 downto 0);
PPE_SFFLAGS : out vl_logic_vector(31 downto 0);
ADC0_FIFO_FULL : out vl_logic;
ADC0_FIFO_AFULL : out vl_logic;
ADC1_FIFO_FULL : out vl_logic;
ADC1_FIFO_AFULL : out vl_logic;
ADC2_FIFO_FULL : out vl_logic;
ADC2_FIFO_AFULL : out vl_logic;
ADC0_FIFO_EMPTY : out vl_logic;
ADC1_FIFO_EMPTY : out vl_logic;
ADC2_FIFO_EMPTY : out vl_logic;
PPE_PDMA_DATAOUT_reg_move_target: out vl_logic;
PPE_PDMA_DATAOUT_chan_en: out vl_logic;
PPE_PDMA_DATAOUT_raw_en: out vl_logic;
PPE_PDMA_DATAOUT_tag_en: out vl_logic;
PPE_PDMA_CTRL_reg_move_target: out vl_logic;
xfer_din_mux : out vl_logic_vector(31 downto 0);
CURRENT_ADC_CHAN: out vl_logic_vector(5 downto 0);
TEST_MODE : in vl_logic;
RB_TEST : in vl_logic;
RB_CSBA : in vl_logic;
RB_CSBB : in vl_logic;
RB_RWBA : in vl_logic;
RB_RWBB : in vl_logic;
RB_ADA : in vl_logic_vector(8 downto 0);
RB_ADB : in vl_logic_vector(8 downto 0);
RB_WDA : in vl_logic_vector(31 downto 0);
RB_WDB : in vl_logic_vector(31 downto 0);
RB_RDA : out vl_logic_vector(31 downto 0);
RB_RDB : out vl_logic_vector(31 downto 0)
);
end F2DSS_ACE_PPE;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in vl_logic;
PWDATA : in vl_logic_vector(31 downto 0);
PRDATA_PPE : out vl_logic_vector(31 downto 0);
PREADY_PPE : out vl_logic;
PPE2SSE_PSEL : out vl_logic;
PPE2SSE_PENABLE : out vl_logic;
PPE2SSE_PWRITE : out vl_logic;
PPE2SSE_PADDR : out vl_logic_vector(11 downto 0);
PPE2SSE_PWDATA : out vl_logic_vector(15 downto 0);
PPE2SSE_PRDATA : in vl_logic_vector(15 downto 0);
PPE2SSE_PREADY : in vl_logic;
PPE2SSE_STALL : out vl_logic;
PPE_BUSY : out vl_logic;
SSE_ADC0_RESULTS: in vl_logic;
SSE_ADC1_RESULTS: in vl_logic;
SSE_ADC2_RESULTS: in vl_logic;
ADC0_DATAVALID_rise: in vl_logic;
ADC1_DATAVALID_rise: in vl_logic;
ADC2_DATAVALID_rise: in vl_logic;
ADC0_RESULT : in vl_logic_vector(11 downto 0);
ADC1_RESULT : in vl_logic_vector(11 downto 0);
ADC2_RESULT : in vl_logic_vector(11 downto 0);
ADC0_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC1_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC2_CHNUMBER : in vl_logic_vector(4 downto 0);
PPE_FLAGS0 : out vl_logic_vector(31 downto 0);
PPE_FLAGS1 : out vl_logic_vector(31 downto 0);
PPE_FLAGS2 : out vl_logic_vector(31 downto 0);
PPE_FLAGS3 : out vl_logic_vector(31 downto 0);
PPE_SFFLAGS : out vl_logic_vector(31 downto 0);
ADC0_FIFO_FULL : out vl_logic;
ADC0_FIFO_AFULL : out vl_logic;
ADC1_FIFO_FULL : out vl_logic;
ADC1_FIFO_AFULL : out vl_logic;
ADC2_FIFO_FULL : out vl_logic;
ADC2_FIFO_AFULL : out vl_logic;
ADC0_FIFO_EMPTY : out vl_logic;
ADC1_FIFO_EMPTY : out vl_logic;
ADC2_FIFO_EMPTY : out vl_logic;
PPE_PDMA_DATAOUT_reg_move_target: out vl_logic;
PPE_PDMA_DATAOUT_chan_en: out vl_logic;
PPE_PDMA_DATAOUT_raw_en: out vl_logic;
PPE_PDMA_DATAOUT_tag_en: out vl_logic;
PPE_PDMA_CTRL_reg_move_target: out vl_logic;
xfer_din_mux : out vl_logic_vector(31 downto 0);
CURRENT_ADC_CHAN: out vl_logic_vector(5 downto 0);
TEST_MODE : in vl_logic;
RB_TEST : in vl_logic;
RB_CSBA : in vl_logic;
RB_CSBB : in vl_logic;
RB_RWBA : in vl_logic;
RB_RWBB : in vl_logic;
RB_ADA : in vl_logic_vector(8 downto 0);
RB_ADB : in vl_logic_vector(8 downto 0);
RB_WDA : in vl_logic_vector(31 downto 0);
RB_WDB : in vl_logic_vector(31 downto 0);
RB_RDA : out vl_logic_vector(31 downto 0);
RB_RDB : out vl_logic_vector(31 downto 0)
);
end F2DSS_ACE_PPE;
|
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x4q3w62Uqusl2Q3EG8HWpWgETCzQZyrGN53jmoE73Rz0mCEhk87NOGRITb2JWHM=
`protect end_protected
|
----------------------------------------------------------------------------
-- INFORMATION: http://www.GNSS-sensor.com
-- PROPERTY: GNSS Sensor Ltd
-- E-MAIL: [email protected]
-- DESCRIPTION: This file contains copy of the firmware image
------------------------------------------------------------------------------
-- WARNING:
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use std.textio.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
entity BootRom_inferred is
generic (
hex_filename : string
);
port (
clk : in std_ulogic;
address : in global_addr_array_type;
data : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
);
end;
architecture rtl of BootRom_inferred is
constant ROM_ADDR_WIDTH : integer := 13;
constant ROM_LENGTH : integer := 2**(ROM_ADDR_WIDTH - log2(CFG_NASTI_DATA_BYTES));
type rom_block is array (0 to ROM_LENGTH-1) of std_logic_vector(31 downto 0);
type rom_type is array (0 to CFG_WORDS_ON_BUS-1) of rom_block;
type local_addr_arr is array (0 to CFG_WORDS_ON_BUS-1) of integer;
impure function init_rom(file_name : in string) return rom_type is
file rom_file : text open read_mode is file_name;
variable rom_line : line;
variable temp_bv : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable temp_mem : rom_type;
begin
for i in 0 to (ROM_LENGTH-1) loop
readline(rom_file, rom_line);
hread(rom_line, temp_bv);
for n in 0 to (CFG_WORDS_ON_BUS-1) loop
temp_mem(n)(i) := temp_bv((n+1)*32-1 downto 32*n);
end loop;
end loop;
return temp_mem;
end function;
constant rom : rom_type := init_rom(hex_filename);
begin
reg : process (clk)
variable t_adr : local_addr_arr;
begin
if rising_edge(clk) then
for n in 0 to CFG_WORDS_ON_BUS-1 loop
t_adr(n) := conv_integer(address(n)(ROM_ADDR_WIDTH-1 downto log2(CFG_NASTI_DATA_BYTES)));
data(32*(n+1)-1 downto 32*n) <= rom(n)(t_adr(n));
end loop;
end if;
end process;
end;
|
----------------------------------------------------------------------------
-- INFORMATION: http://www.GNSS-sensor.com
-- PROPERTY: GNSS Sensor Ltd
-- E-MAIL: [email protected]
-- DESCRIPTION: This file contains copy of the firmware image
------------------------------------------------------------------------------
-- WARNING:
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use std.textio.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
entity BootRom_inferred is
generic (
hex_filename : string
);
port (
clk : in std_ulogic;
address : in global_addr_array_type;
data : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
);
end;
architecture rtl of BootRom_inferred is
constant ROM_ADDR_WIDTH : integer := 13;
constant ROM_LENGTH : integer := 2**(ROM_ADDR_WIDTH - log2(CFG_NASTI_DATA_BYTES));
type rom_block is array (0 to ROM_LENGTH-1) of std_logic_vector(31 downto 0);
type rom_type is array (0 to CFG_WORDS_ON_BUS-1) of rom_block;
type local_addr_arr is array (0 to CFG_WORDS_ON_BUS-1) of integer;
impure function init_rom(file_name : in string) return rom_type is
file rom_file : text open read_mode is file_name;
variable rom_line : line;
variable temp_bv : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable temp_mem : rom_type;
begin
for i in 0 to (ROM_LENGTH-1) loop
readline(rom_file, rom_line);
hread(rom_line, temp_bv);
for n in 0 to (CFG_WORDS_ON_BUS-1) loop
temp_mem(n)(i) := temp_bv((n+1)*32-1 downto 32*n);
end loop;
end loop;
return temp_mem;
end function;
constant rom : rom_type := init_rom(hex_filename);
begin
reg : process (clk)
variable t_adr : local_addr_arr;
begin
if rising_edge(clk) then
for n in 0 to CFG_WORDS_ON_BUS-1 loop
t_adr(n) := conv_integer(address(n)(ROM_ADDR_WIDTH-1 downto log2(CFG_NASTI_DATA_BYTES)));
data(32*(n+1)-1 downto 32*n) <= rom(n)(t_adr(n));
end loop;
end if;
end process;
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (18);
constant CFG_CLKDIV : integer := (9);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 0;
constant CFG_DDR2SP_INIT : integer := 0;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := 130;
constant CFG_DDR2SP_DATAWIDTH : integer := 64;
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := 9;
constant CFG_DDR2SP_SIZE : integer := 8;
constant CFG_DDR2SP_DELAY0 : integer := 0;
constant CFG_DDR2SP_DELAY1 : integer := 0;
constant CFG_DDR2SP_DELAY2 : integer := 0;
constant CFG_DDR2SP_DELAY3 : integer := 0;
constant CFG_DDR2SP_DELAY4 : integer := 0;
constant CFG_DDR2SP_DELAY5 : integer := 0;
constant CFG_DDR2SP_DELAY6 : integer := 0;
constant CFG_DDR2SP_DELAY7 : integer := 0;
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
ROM_form.vhd
Template for a KCPSM6 program memory. This template is primarily for use during code
development including generic parameters for the convenient selection of device family,
program memory size and the ability to include the JTAG Loader hardware for rapid
software development.
Kris Chaplin and Ken Chapman (Xilinx Ltd)
17th September 2010 - First Release
4th February 2011 - Correction to definition of 'we_b' in V6/1K/JTAG instance.
3rd March 2011 - Minor adjustments to comments only.
16th August 2011 - Additions and adjustments for support of 7-Series in ISE v13.2.
Simplification of JTAG Loader definition.
23rd November 2012 - 4K program for Spartan-6.
14th March 2013 - Unused address inputs on Virtex-6 and 7-Series BRAMs connected
High to reflect descriptions in UG363 and UG473.
This is a VHDL template file for the KCPSM6 assembler.
This VHDL file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.vhd' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Definition of a program memory for KCPSM6 including generic parameters for the
-- convenient selection of device family, program memory size and the ability to include
-- the JTAG Loader hardware for rapid software development.
--
-- This file is primarily for use during code development and it is recommended that the
-- appropriate simplified program memory definition be used in a final production design.
--
-- Generic Values Comments
-- Parameter Supported
--
-- C_FAMILY "S6" Spartan-6 device
-- "V6" Virtex-6 device
-- "7S" 7-Series device
-- (Artix-7, Kintex-7, Virtex-7 or Zynq)
--
-- C_RAM_SIZE_KWORDS 1, 2 or 4 Size of program memory in K-instructions
--
-- C_JTAG_LOADER_ENABLE 0 or 1 Set to '1' to include JTAG Loader
--
-- Notes
--
-- If your design contains MULTIPLE KCPSM6 instances then only one should have the
-- JTAG Loader enabled at a time (i.e. make sure that C_JTAG_LOADER_ENABLE is only set to
-- '1' on one instance of the program memory). Advanced users may be interested to know
-- that it is possible to connect JTAG Loader to multiple memories and then to use the
-- JTAG Loader utility to specify which memory contents are to be modified. However,
-- this scheme does require some effort to set up and the additional connectivity of the
-- multiple BRAMs can impact the placement, routing and performance of the complete
-- design. Please contact the author at Xilinx for more detailed information.
--
-- Regardless of the size of program memory specified by C_RAM_SIZE_KWORDS, the complete
-- 12-bit address bus is connected to KCPSM6. This enables the generic to be modified
-- without requiring changes to the fundamental hardware definition. However, when the
-- program memory is 1K then only the lower 10-bits of the address are actually used and
-- the valid address range is 000 to 3FF hex. Likewise, for a 2K program only the lower
-- 11-bits of the address are actually used and the valid address range is 000 to 7FF hex.
--
-- Programs are stored in Block Memory (BRAM) and the number of BRAM used depends on the
-- size of the program and the device family.
--
-- In a Spartan-6 device a BRAM is capable of holding 1K instructions. Hence a 2K program
-- will require 2 BRAMs to be used and a 4K program will require 4 BRAMs to be used. It
-- should be noted that a 4K program is not such a natural fit in a Spartan-6 device and
-- the implementation also requires a small amount of logic resulting in slightly lower
-- performance. A Spartan-6 BRAM can also be split into two 9k-bit memories suggesting
-- that a program containing up to 512 instructions could be implemented. However, there
-- is a silicon errata which makes this unsuitable and therefore it is not supported by
-- this file.
--
-- In a Virtex-6 or any 7-Series device a BRAM is capable of holding 2K instructions so
-- obviously a 2K program requires only a single BRAM. Each BRAM can also be divided into
-- 2 smaller memories supporting programs of 1K in half of a 36k-bit BRAM (generally
-- reported as being an 18k-bit BRAM). For a program of 4K instructions, 2 BRAMs are used.
--
--
-- Program defined by '{psmname}.psm'.
--
-- Generated by KCPSM6 Assembler: {timestamp}.
--
-- Assembler used ROM_form template: ROM_form_JTAGLoader_14March13.vhd
--
-- Standard IEEE libraries
--
--
package jtag_loader_pkg is
function addr_width_calc (size_in_k: integer) return integer;
end jtag_loader_pkg;
--
package body jtag_loader_pkg is
function addr_width_calc (size_in_k: integer) return integer is
begin
if (size_in_k = 1) then return 10;
elsif (size_in_k = 2) then return 11;
elsif (size_in_k = 4) then return 12;
else report "Invalid BlockRAM size. Please set to 1, 2 or 4 K words." severity FAILURE;
end if;
return 0;
end function addr_width_calc;
end package body;
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.jtag_loader_pkg.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
generic( C_FAMILY : string := "S6";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
signal address_a : std_logic_vector(15 downto 0);
signal pipe_a11 : std_logic;
signal data_in_a : std_logic_vector(35 downto 0);
signal data_out_a : std_logic_vector(35 downto 0);
signal data_out_a_l : std_logic_vector(35 downto 0);
signal data_out_a_h : std_logic_vector(35 downto 0);
signal data_out_a_ll : std_logic_vector(35 downto 0);
signal data_out_a_lh : std_logic_vector(35 downto 0);
signal data_out_a_hl : std_logic_vector(35 downto 0);
signal data_out_a_hh : std_logic_vector(35 downto 0);
signal address_b : std_logic_vector(15 downto 0);
signal data_in_b : std_logic_vector(35 downto 0);
signal data_in_b_l : std_logic_vector(35 downto 0);
signal data_in_b_ll : std_logic_vector(35 downto 0);
signal data_in_b_hl : std_logic_vector(35 downto 0);
signal data_out_b : std_logic_vector(35 downto 0);
signal data_out_b_l : std_logic_vector(35 downto 0);
signal data_out_b_ll : std_logic_vector(35 downto 0);
signal data_out_b_hl : std_logic_vector(35 downto 0);
signal data_in_b_h : std_logic_vector(35 downto 0);
signal data_in_b_lh : std_logic_vector(35 downto 0);
signal data_in_b_hh : std_logic_vector(35 downto 0);
signal data_out_b_h : std_logic_vector(35 downto 0);
signal data_out_b_lh : std_logic_vector(35 downto 0);
signal data_out_b_hh : std_logic_vector(35 downto 0);
signal enable_b : std_logic;
signal clk_b : std_logic;
signal we_b : std_logic_vector(7 downto 0);
signal we_b_l : std_logic_vector(3 downto 0);
signal we_b_h : std_logic_vector(3 downto 0);
--
signal jtag_addr : std_logic_vector(11 downto 0);
signal jtag_we : std_logic;
signal jtag_we_l : std_logic;
signal jtag_we_h : std_logic;
signal jtag_clk : std_logic;
signal jtag_din : std_logic_vector(17 downto 0);
signal jtag_dout : std_logic_vector(17 downto 0);
signal jtag_dout_1 : std_logic_vector(17 downto 0);
signal jtag_en : std_logic_vector(0 downto 0);
--
signal picoblaze_reset : std_logic_vector(0 downto 0);
signal rdl_bus : std_logic_vector(0 downto 0);
--
constant BRAM_ADDRESS_WIDTH : integer := addr_width_calc(C_RAM_SIZE_KWORDS);
--
--
component jtag_loader_6
generic( C_JTAG_LOADER_ENABLE : integer := 1;
C_FAMILY : string := "V6";
C_NUM_PICOBLAZE : integer := 1;
C_BRAM_MAX_ADDR_WIDTH : integer := 10;
C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18;
C_JTAG_CHAIN : integer := 2;
C_ADDR_WIDTH_0 : integer := 10;
C_ADDR_WIDTH_1 : integer := 10;
C_ADDR_WIDTH_2 : integer := 10;
C_ADDR_WIDTH_3 : integer := 10;
C_ADDR_WIDTH_4 : integer := 10;
C_ADDR_WIDTH_5 : integer := 10;
C_ADDR_WIDTH_6 : integer := 10;
C_ADDR_WIDTH_7 : integer := 10);
port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_din : out STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_addr : out STD_LOGIC_VECTOR(C_BRAM_MAX_ADDR_WIDTH-1 downto 0);
jtag_clk : out std_logic;
jtag_we : out std_logic;
jtag_dout_0 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_1 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_2 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_3 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_4 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_5 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_6 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_7 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0));
end component;
--
begin
--
--
ram_1k_generate : if (C_RAM_SIZE_KWORDS = 1) generate
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "0000";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "0000000000000000000000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "0000";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB16BWER
generic map ( DATA_WIDTH_A => 18,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 18,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a(31 downto 0),
DOPA => data_out_a(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b(31 downto 0),
DOPB => data_out_b(35 downto 32),
DIB => data_in_b(31 downto 0),
DIPB => data_in_b(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(17 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b(17 downto 0) <= data_out_b(17 downto 0);
address_b(13 downto 0) <= "11111111111111";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b(17 downto 0) <= jtag_din(17 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "1111";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
port map( ADDRARDADDR => address_a(13 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(13 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b(3 downto 0),
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(17 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b(17 downto 0) <= data_out_b(17 downto 0);
address_b(13 downto 0) <= "11111111111111";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b(17 downto 0) <= jtag_din(17 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "1111";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
port map( ADDRARDADDR => address_a(13 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(13 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b(3 downto 0),
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
end generate akv7;
--
end generate ram_1k_generate;
--
--
--
ram_2k_generate : if (C_RAM_SIZE_KWORDS = 2) generate
--
--
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(10 downto 0) & "000";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_l(31 downto 0),
DOPA => data_out_a_l(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_l(31 downto 0),
DOPB => data_out_b_l(35 downto 32),
DIB => data_in_b_l(31 downto 0),
DIPB => data_in_b_l(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_h: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_h(31 downto 0),
DOPA => data_out_a_h(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_h(31 downto 0),
DOPB => data_out_b_h(35 downto 32),
DIB => data_in_b_h(31 downto 0),
DIPB => data_in_b_h(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b <= '1' & jtag_addr(10 downto 0) & "1111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INIT_40 => X"{INIT_40}",
INIT_41 => X"{INIT_41}",
INIT_42 => X"{INIT_42}",
INIT_43 => X"{INIT_43}",
INIT_44 => X"{INIT_44}",
INIT_45 => X"{INIT_45}",
INIT_46 => X"{INIT_46}",
INIT_47 => X"{INIT_47}",
INIT_48 => X"{INIT_48}",
INIT_49 => X"{INIT_49}",
INIT_4A => X"{INIT_4A}",
INIT_4B => X"{INIT_4B}",
INIT_4C => X"{INIT_4C}",
INIT_4D => X"{INIT_4D}",
INIT_4E => X"{INIT_4E}",
INIT_4F => X"{INIT_4F}",
INIT_50 => X"{INIT_50}",
INIT_51 => X"{INIT_51}",
INIT_52 => X"{INIT_52}",
INIT_53 => X"{INIT_53}",
INIT_54 => X"{INIT_54}",
INIT_55 => X"{INIT_55}",
INIT_56 => X"{INIT_56}",
INIT_57 => X"{INIT_57}",
INIT_58 => X"{INIT_58}",
INIT_59 => X"{INIT_59}",
INIT_5A => X"{INIT_5A}",
INIT_5B => X"{INIT_5B}",
INIT_5C => X"{INIT_5C}",
INIT_5D => X"{INIT_5D}",
INIT_5E => X"{INIT_5E}",
INIT_5F => X"{INIT_5F}",
INIT_60 => X"{INIT_60}",
INIT_61 => X"{INIT_61}",
INIT_62 => X"{INIT_62}",
INIT_63 => X"{INIT_63}",
INIT_64 => X"{INIT_64}",
INIT_65 => X"{INIT_65}",
INIT_66 => X"{INIT_66}",
INIT_67 => X"{INIT_67}",
INIT_68 => X"{INIT_68}",
INIT_69 => X"{INIT_69}",
INIT_6A => X"{INIT_6A}",
INIT_6B => X"{INIT_6B}",
INIT_6C => X"{INIT_6C}",
INIT_6D => X"{INIT_6D}",
INIT_6E => X"{INIT_6E}",
INIT_6F => X"{INIT_6F}",
INIT_70 => X"{INIT_70}",
INIT_71 => X"{INIT_71}",
INIT_72 => X"{INIT_72}",
INIT_73 => X"{INIT_73}",
INIT_74 => X"{INIT_74}",
INIT_75 => X"{INIT_75}",
INIT_76 => X"{INIT_76}",
INIT_77 => X"{INIT_77}",
INIT_78 => X"{INIT_78}",
INIT_79 => X"{INIT_79}",
INIT_7A => X"{INIT_7A}",
INIT_7B => X"{INIT_7B}",
INIT_7C => X"{INIT_7C}",
INIT_7D => X"{INIT_7D}",
INIT_7E => X"{INIT_7E}",
INIT_7F => X"{INIT_7F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}",
INITP_08 => X"{INITP_08}",
INITP_09 => X"{INITP_09}",
INITP_0A => X"{INITP_0A}",
INITP_0B => X"{INITP_0B}",
INITP_0C => X"{INITP_0C}",
INITP_0D => X"{INITP_0D}",
INITP_0E => X"{INITP_0E}",
INITP_0F => X"{INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b <= '1' & jtag_addr(10 downto 0) & "1111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INIT_40 => X"{INIT_40}",
INIT_41 => X"{INIT_41}",
INIT_42 => X"{INIT_42}",
INIT_43 => X"{INIT_43}",
INIT_44 => X"{INIT_44}",
INIT_45 => X"{INIT_45}",
INIT_46 => X"{INIT_46}",
INIT_47 => X"{INIT_47}",
INIT_48 => X"{INIT_48}",
INIT_49 => X"{INIT_49}",
INIT_4A => X"{INIT_4A}",
INIT_4B => X"{INIT_4B}",
INIT_4C => X"{INIT_4C}",
INIT_4D => X"{INIT_4D}",
INIT_4E => X"{INIT_4E}",
INIT_4F => X"{INIT_4F}",
INIT_50 => X"{INIT_50}",
INIT_51 => X"{INIT_51}",
INIT_52 => X"{INIT_52}",
INIT_53 => X"{INIT_53}",
INIT_54 => X"{INIT_54}",
INIT_55 => X"{INIT_55}",
INIT_56 => X"{INIT_56}",
INIT_57 => X"{INIT_57}",
INIT_58 => X"{INIT_58}",
INIT_59 => X"{INIT_59}",
INIT_5A => X"{INIT_5A}",
INIT_5B => X"{INIT_5B}",
INIT_5C => X"{INIT_5C}",
INIT_5D => X"{INIT_5D}",
INIT_5E => X"{INIT_5E}",
INIT_5F => X"{INIT_5F}",
INIT_60 => X"{INIT_60}",
INIT_61 => X"{INIT_61}",
INIT_62 => X"{INIT_62}",
INIT_63 => X"{INIT_63}",
INIT_64 => X"{INIT_64}",
INIT_65 => X"{INIT_65}",
INIT_66 => X"{INIT_66}",
INIT_67 => X"{INIT_67}",
INIT_68 => X"{INIT_68}",
INIT_69 => X"{INIT_69}",
INIT_6A => X"{INIT_6A}",
INIT_6B => X"{INIT_6B}",
INIT_6C => X"{INIT_6C}",
INIT_6D => X"{INIT_6D}",
INIT_6E => X"{INIT_6E}",
INIT_6F => X"{INIT_6F}",
INIT_70 => X"{INIT_70}",
INIT_71 => X"{INIT_71}",
INIT_72 => X"{INIT_72}",
INIT_73 => X"{INIT_73}",
INIT_74 => X"{INIT_74}",
INIT_75 => X"{INIT_75}",
INIT_76 => X"{INIT_76}",
INIT_77 => X"{INIT_77}",
INIT_78 => X"{INIT_78}",
INIT_79 => X"{INIT_79}",
INIT_7A => X"{INIT_7A}",
INIT_7B => X"{INIT_7B}",
INIT_7C => X"{INIT_7C}",
INIT_7D => X"{INIT_7D}",
INIT_7E => X"{INIT_7E}",
INIT_7F => X"{INIT_7F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}",
INITP_08 => X"{INITP_08}",
INITP_09 => X"{INITP_09}",
INITP_0A => X"{INITP_0A}",
INITP_0B => X"{INITP_0B}",
INITP_0C => X"{INITP_0C}",
INITP_0D => X"{INITP_0D}",
INITP_0E => X"{INITP_0E}",
INITP_0F => X"{INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate akv7;
--
end generate ram_2k_generate;
--
--
ram_4k_generate : if (C_RAM_SIZE_KWORDS = 4) generate
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(10 downto 0) & "000";
data_in_a <= "000000000000000000000000000000000000";
--
s6_a11_flop: FD
port map ( D => address(11),
Q => pipe_a11,
C => clk);
--
s6_4k_mux0_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(0),
I1 => data_out_a_hl(0),
I2 => data_out_a_ll(1),
I3 => data_out_a_hl(1),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(0),
O6 => instruction(1));
--
s6_4k_mux2_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(2),
I1 => data_out_a_hl(2),
I2 => data_out_a_ll(3),
I3 => data_out_a_hl(3),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(2),
O6 => instruction(3));
--
s6_4k_mux4_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(4),
I1 => data_out_a_hl(4),
I2 => data_out_a_ll(5),
I3 => data_out_a_hl(5),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(4),
O6 => instruction(5));
--
s6_4k_mux6_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(6),
I1 => data_out_a_hl(6),
I2 => data_out_a_ll(7),
I3 => data_out_a_hl(7),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(6),
O6 => instruction(7));
--
s6_4k_mux8_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(32),
I1 => data_out_a_hl(32),
I2 => data_out_a_lh(0),
I3 => data_out_a_hh(0),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(8),
O6 => instruction(9));
--
s6_4k_mux10_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(1),
I1 => data_out_a_hh(1),
I2 => data_out_a_lh(2),
I3 => data_out_a_hh(2),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(10),
O6 => instruction(11));
--
s6_4k_mux12_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(3),
I1 => data_out_a_hh(3),
I2 => data_out_a_lh(4),
I3 => data_out_a_hh(4),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(12),
O6 => instruction(13));
--
s6_4k_mux14_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(5),
I1 => data_out_a_hh(5),
I2 => data_out_a_lh(6),
I3 => data_out_a_hh(6),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(14),
O6 => instruction(15));
--
s6_4k_mux16_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(7),
I1 => data_out_a_hh(7),
I2 => data_out_a_lh(32),
I3 => data_out_a_hh(32),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(16),
O6 => instruction(17));
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_ll <= "000" & data_out_b_ll(32) & "000000000000000000000000" & data_out_b_ll(7 downto 0);
data_in_b_lh <= "000" & data_out_b_lh(32) & "000000000000000000000000" & data_out_b_lh(7 downto 0);
data_in_b_hl <= "000" & data_out_b_hl(32) & "000000000000000000000000" & data_out_b_hl(7 downto 0);
data_in_b_hh <= "000" & data_out_b_hh(32) & "000000000000000000000000" & data_out_b_hh(7 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b_l(3 downto 0) <= "0000";
we_b_h(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
jtag_dout <= data_out_b_lh(32) & data_out_b_lh(7 downto 0) & data_out_b_ll(32) & data_out_b_ll(7 downto 0);
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_lh <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_ll <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
data_in_b_hh <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_hl <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000";
--
s6_4k_jtag_we_lut: LUT6_2
generic map (INIT => X"8000000020000000")
port map( I0 => jtag_we,
I1 => jtag_addr(11),
I2 => '1',
I3 => '1',
I4 => '1',
I5 => '1',
O5 => jtag_we_l,
O6 => jtag_we_h);
--
we_b_l(3 downto 0) <= jtag_we_l & jtag_we_l & jtag_we_l & jtag_we_l;
we_b_h(3 downto 0) <= jtag_we_h & jtag_we_h & jtag_we_h & jtag_we_h;
--
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
--
s6_4k_jtag_mux0_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(0),
I1 => data_out_b_hl(0),
I2 => data_out_b_ll(1),
I3 => data_out_b_hl(1),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(0),
O6 => jtag_dout(1));
--
s6_4k_jtag_mux2_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(2),
I1 => data_out_b_hl(2),
I2 => data_out_b_ll(3),
I3 => data_out_b_hl(3),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(2),
O6 => jtag_dout(3));
--
s6_4k_jtag_mux4_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(4),
I1 => data_out_b_hl(4),
I2 => data_out_b_ll(5),
I3 => data_out_b_hl(5),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(4),
O6 => jtag_dout(5));
--
s6_4k_jtag_mux6_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(6),
I1 => data_out_b_hl(6),
I2 => data_out_b_ll(7),
I3 => data_out_b_hl(7),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(6),
O6 => jtag_dout(7));
--
s6_4k_jtag_mux8_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(32),
I1 => data_out_b_hl(32),
I2 => data_out_b_lh(0),
I3 => data_out_b_hh(0),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(8),
O6 => jtag_dout(9));
--
s6_4k_jtag_mux10_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(1),
I1 => data_out_b_hh(1),
I2 => data_out_b_lh(2),
I3 => data_out_b_hh(2),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(10),
O6 => jtag_dout(11));
--
s6_4k_jtag_mux12_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(3),
I1 => data_out_b_hh(3),
I2 => data_out_b_lh(4),
I3 => data_out_b_hh(4),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(12),
O6 => jtag_dout(13));
--
s6_4k_jtag_mux14_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(5),
I1 => data_out_b_hh(5),
I2 => data_out_b_lh(6),
I3 => data_out_b_hh(6),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(14),
O6 => jtag_dout(15));
--
s6_4k_jtag_mux16_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(7),
I1 => data_out_b_hh(7),
I2 => data_out_b_lh(32),
I3 => data_out_b_hh(32),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(16),
O6 => jtag_dout(17));
--
end generate loader;
--
kcpsm6_rom_ll: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_ll(31 downto 0),
DOPA => data_out_a_ll(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_ll(31 downto 0),
DOPB => data_out_b_ll(35 downto 32),
DIB => data_in_b_ll(31 downto 0),
DIPB => data_in_b_ll(35 downto 32),
WEB => we_b_l(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_lh: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_lh(31 downto 0),
DOPA => data_out_a_lh(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_lh(31 downto 0),
DOPB => data_out_b_lh(35 downto 32),
DIB => data_in_b_lh(31 downto 0),
DIPB => data_in_b_lh(35 downto 32),
WEB => we_b_l(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_hl: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[8:0]_INIT_40}",
INIT_01 => X"{[8:0]_INIT_41}",
INIT_02 => X"{[8:0]_INIT_42}",
INIT_03 => X"{[8:0]_INIT_43}",
INIT_04 => X"{[8:0]_INIT_44}",
INIT_05 => X"{[8:0]_INIT_45}",
INIT_06 => X"{[8:0]_INIT_46}",
INIT_07 => X"{[8:0]_INIT_47}",
INIT_08 => X"{[8:0]_INIT_48}",
INIT_09 => X"{[8:0]_INIT_49}",
INIT_0A => X"{[8:0]_INIT_4A}",
INIT_0B => X"{[8:0]_INIT_4B}",
INIT_0C => X"{[8:0]_INIT_4C}",
INIT_0D => X"{[8:0]_INIT_4D}",
INIT_0E => X"{[8:0]_INIT_4E}",
INIT_0F => X"{[8:0]_INIT_4F}",
INIT_10 => X"{[8:0]_INIT_50}",
INIT_11 => X"{[8:0]_INIT_51}",
INIT_12 => X"{[8:0]_INIT_52}",
INIT_13 => X"{[8:0]_INIT_53}",
INIT_14 => X"{[8:0]_INIT_54}",
INIT_15 => X"{[8:0]_INIT_55}",
INIT_16 => X"{[8:0]_INIT_56}",
INIT_17 => X"{[8:0]_INIT_57}",
INIT_18 => X"{[8:0]_INIT_58}",
INIT_19 => X"{[8:0]_INIT_59}",
INIT_1A => X"{[8:0]_INIT_5A}",
INIT_1B => X"{[8:0]_INIT_5B}",
INIT_1C => X"{[8:0]_INIT_5C}",
INIT_1D => X"{[8:0]_INIT_5D}",
INIT_1E => X"{[8:0]_INIT_5E}",
INIT_1F => X"{[8:0]_INIT_5F}",
INIT_20 => X"{[8:0]_INIT_60}",
INIT_21 => X"{[8:0]_INIT_61}",
INIT_22 => X"{[8:0]_INIT_62}",
INIT_23 => X"{[8:0]_INIT_63}",
INIT_24 => X"{[8:0]_INIT_64}",
INIT_25 => X"{[8:0]_INIT_65}",
INIT_26 => X"{[8:0]_INIT_66}",
INIT_27 => X"{[8:0]_INIT_67}",
INIT_28 => X"{[8:0]_INIT_68}",
INIT_29 => X"{[8:0]_INIT_69}",
INIT_2A => X"{[8:0]_INIT_6A}",
INIT_2B => X"{[8:0]_INIT_6B}",
INIT_2C => X"{[8:0]_INIT_6C}",
INIT_2D => X"{[8:0]_INIT_6D}",
INIT_2E => X"{[8:0]_INIT_6E}",
INIT_2F => X"{[8:0]_INIT_6F}",
INIT_30 => X"{[8:0]_INIT_70}",
INIT_31 => X"{[8:0]_INIT_71}",
INIT_32 => X"{[8:0]_INIT_72}",
INIT_33 => X"{[8:0]_INIT_73}",
INIT_34 => X"{[8:0]_INIT_74}",
INIT_35 => X"{[8:0]_INIT_75}",
INIT_36 => X"{[8:0]_INIT_76}",
INIT_37 => X"{[8:0]_INIT_77}",
INIT_38 => X"{[8:0]_INIT_78}",
INIT_39 => X"{[8:0]_INIT_79}",
INIT_3A => X"{[8:0]_INIT_7A}",
INIT_3B => X"{[8:0]_INIT_7B}",
INIT_3C => X"{[8:0]_INIT_7C}",
INIT_3D => X"{[8:0]_INIT_7D}",
INIT_3E => X"{[8:0]_INIT_7E}",
INIT_3F => X"{[8:0]_INIT_7F}",
INITP_00 => X"{[8:0]_INITP_08}",
INITP_01 => X"{[8:0]_INITP_09}",
INITP_02 => X"{[8:0]_INITP_0A}",
INITP_03 => X"{[8:0]_INITP_0B}",
INITP_04 => X"{[8:0]_INITP_0C}",
INITP_05 => X"{[8:0]_INITP_0D}",
INITP_06 => X"{[8:0]_INITP_0E}",
INITP_07 => X"{[8:0]_INITP_0F}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_hl(31 downto 0),
DOPA => data_out_a_hl(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_hl(31 downto 0),
DOPB => data_out_b_hl(35 downto 32),
DIB => data_in_b_hl(31 downto 0),
DIPB => data_in_b_hl(35 downto 32),
WEB => we_b_h(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_hh: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[17:9]_INIT_40}",
INIT_01 => X"{[17:9]_INIT_41}",
INIT_02 => X"{[17:9]_INIT_42}",
INIT_03 => X"{[17:9]_INIT_43}",
INIT_04 => X"{[17:9]_INIT_44}",
INIT_05 => X"{[17:9]_INIT_45}",
INIT_06 => X"{[17:9]_INIT_46}",
INIT_07 => X"{[17:9]_INIT_47}",
INIT_08 => X"{[17:9]_INIT_48}",
INIT_09 => X"{[17:9]_INIT_49}",
INIT_0A => X"{[17:9]_INIT_4A}",
INIT_0B => X"{[17:9]_INIT_4B}",
INIT_0C => X"{[17:9]_INIT_4C}",
INIT_0D => X"{[17:9]_INIT_4D}",
INIT_0E => X"{[17:9]_INIT_4E}",
INIT_0F => X"{[17:9]_INIT_4F}",
INIT_10 => X"{[17:9]_INIT_50}",
INIT_11 => X"{[17:9]_INIT_51}",
INIT_12 => X"{[17:9]_INIT_52}",
INIT_13 => X"{[17:9]_INIT_53}",
INIT_14 => X"{[17:9]_INIT_54}",
INIT_15 => X"{[17:9]_INIT_55}",
INIT_16 => X"{[17:9]_INIT_56}",
INIT_17 => X"{[17:9]_INIT_57}",
INIT_18 => X"{[17:9]_INIT_58}",
INIT_19 => X"{[17:9]_INIT_59}",
INIT_1A => X"{[17:9]_INIT_5A}",
INIT_1B => X"{[17:9]_INIT_5B}",
INIT_1C => X"{[17:9]_INIT_5C}",
INIT_1D => X"{[17:9]_INIT_5D}",
INIT_1E => X"{[17:9]_INIT_5E}",
INIT_1F => X"{[17:9]_INIT_5F}",
INIT_20 => X"{[17:9]_INIT_60}",
INIT_21 => X"{[17:9]_INIT_61}",
INIT_22 => X"{[17:9]_INIT_62}",
INIT_23 => X"{[17:9]_INIT_63}",
INIT_24 => X"{[17:9]_INIT_64}",
INIT_25 => X"{[17:9]_INIT_65}",
INIT_26 => X"{[17:9]_INIT_66}",
INIT_27 => X"{[17:9]_INIT_67}",
INIT_28 => X"{[17:9]_INIT_68}",
INIT_29 => X"{[17:9]_INIT_69}",
INIT_2A => X"{[17:9]_INIT_6A}",
INIT_2B => X"{[17:9]_INIT_6B}",
INIT_2C => X"{[17:9]_INIT_6C}",
INIT_2D => X"{[17:9]_INIT_6D}",
INIT_2E => X"{[17:9]_INIT_6E}",
INIT_2F => X"{[17:9]_INIT_6F}",
INIT_30 => X"{[17:9]_INIT_70}",
INIT_31 => X"{[17:9]_INIT_71}",
INIT_32 => X"{[17:9]_INIT_72}",
INIT_33 => X"{[17:9]_INIT_73}",
INIT_34 => X"{[17:9]_INIT_74}",
INIT_35 => X"{[17:9]_INIT_75}",
INIT_36 => X"{[17:9]_INIT_76}",
INIT_37 => X"{[17:9]_INIT_77}",
INIT_38 => X"{[17:9]_INIT_78}",
INIT_39 => X"{[17:9]_INIT_79}",
INIT_3A => X"{[17:9]_INIT_7A}",
INIT_3B => X"{[17:9]_INIT_7B}",
INIT_3C => X"{[17:9]_INIT_7C}",
INIT_3D => X"{[17:9]_INIT_7D}",
INIT_3E => X"{[17:9]_INIT_7E}",
INIT_3F => X"{[17:9]_INIT_7F}",
INITP_00 => X"{[17:9]_INITP_08}",
INITP_01 => X"{[17:9]_INITP_09}",
INITP_02 => X"{[17:9]_INITP_0A}",
INITP_03 => X"{[17:9]_INITP_0B}",
INITP_04 => X"{[17:9]_INITP_0C}",
INITP_05 => X"{[17:9]_INITP_0D}",
INITP_06 => X"{[17:9]_INITP_0E}",
INITP_07 => X"{[17:9]_INITP_0F}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_hh(31 downto 0),
DOPA => data_out_a_hh(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_hh(31 downto 0),
DOPB => data_out_b_hh(35 downto 32),
DIB => data_in_b_hh(31 downto 0),
DIPB => data_in_b_hh(35 downto 32),
WEB => we_b_h(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a <= '1' & address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b <= '1' & jtag_addr(11 downto 0) & "111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INIT_40 => X"{[8:0]_INIT_40}",
INIT_41 => X"{[8:0]_INIT_41}",
INIT_42 => X"{[8:0]_INIT_42}",
INIT_43 => X"{[8:0]_INIT_43}",
INIT_44 => X"{[8:0]_INIT_44}",
INIT_45 => X"{[8:0]_INIT_45}",
INIT_46 => X"{[8:0]_INIT_46}",
INIT_47 => X"{[8:0]_INIT_47}",
INIT_48 => X"{[8:0]_INIT_48}",
INIT_49 => X"{[8:0]_INIT_49}",
INIT_4A => X"{[8:0]_INIT_4A}",
INIT_4B => X"{[8:0]_INIT_4B}",
INIT_4C => X"{[8:0]_INIT_4C}",
INIT_4D => X"{[8:0]_INIT_4D}",
INIT_4E => X"{[8:0]_INIT_4E}",
INIT_4F => X"{[8:0]_INIT_4F}",
INIT_50 => X"{[8:0]_INIT_50}",
INIT_51 => X"{[8:0]_INIT_51}",
INIT_52 => X"{[8:0]_INIT_52}",
INIT_53 => X"{[8:0]_INIT_53}",
INIT_54 => X"{[8:0]_INIT_54}",
INIT_55 => X"{[8:0]_INIT_55}",
INIT_56 => X"{[8:0]_INIT_56}",
INIT_57 => X"{[8:0]_INIT_57}",
INIT_58 => X"{[8:0]_INIT_58}",
INIT_59 => X"{[8:0]_INIT_59}",
INIT_5A => X"{[8:0]_INIT_5A}",
INIT_5B => X"{[8:0]_INIT_5B}",
INIT_5C => X"{[8:0]_INIT_5C}",
INIT_5D => X"{[8:0]_INIT_5D}",
INIT_5E => X"{[8:0]_INIT_5E}",
INIT_5F => X"{[8:0]_INIT_5F}",
INIT_60 => X"{[8:0]_INIT_60}",
INIT_61 => X"{[8:0]_INIT_61}",
INIT_62 => X"{[8:0]_INIT_62}",
INIT_63 => X"{[8:0]_INIT_63}",
INIT_64 => X"{[8:0]_INIT_64}",
INIT_65 => X"{[8:0]_INIT_65}",
INIT_66 => X"{[8:0]_INIT_66}",
INIT_67 => X"{[8:0]_INIT_67}",
INIT_68 => X"{[8:0]_INIT_68}",
INIT_69 => X"{[8:0]_INIT_69}",
INIT_6A => X"{[8:0]_INIT_6A}",
INIT_6B => X"{[8:0]_INIT_6B}",
INIT_6C => X"{[8:0]_INIT_6C}",
INIT_6D => X"{[8:0]_INIT_6D}",
INIT_6E => X"{[8:0]_INIT_6E}",
INIT_6F => X"{[8:0]_INIT_6F}",
INIT_70 => X"{[8:0]_INIT_70}",
INIT_71 => X"{[8:0]_INIT_71}",
INIT_72 => X"{[8:0]_INIT_72}",
INIT_73 => X"{[8:0]_INIT_73}",
INIT_74 => X"{[8:0]_INIT_74}",
INIT_75 => X"{[8:0]_INIT_75}",
INIT_76 => X"{[8:0]_INIT_76}",
INIT_77 => X"{[8:0]_INIT_77}",
INIT_78 => X"{[8:0]_INIT_78}",
INIT_79 => X"{[8:0]_INIT_79}",
INIT_7A => X"{[8:0]_INIT_7A}",
INIT_7B => X"{[8:0]_INIT_7B}",
INIT_7C => X"{[8:0]_INIT_7C}",
INIT_7D => X"{[8:0]_INIT_7D}",
INIT_7E => X"{[8:0]_INIT_7E}",
INIT_7F => X"{[8:0]_INIT_7F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}",
INITP_08 => X"{[8:0]_INITP_08}",
INITP_09 => X"{[8:0]_INITP_09}",
INITP_0A => X"{[8:0]_INITP_0A}",
INITP_0B => X"{[8:0]_INITP_0B}",
INITP_0C => X"{[8:0]_INITP_0C}",
INITP_0D => X"{[8:0]_INITP_0D}",
INITP_0E => X"{[8:0]_INITP_0E}",
INITP_0F => X"{[8:0]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
kcpsm6_rom_h: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INIT_40 => X"{[17:9]_INIT_40}",
INIT_41 => X"{[17:9]_INIT_41}",
INIT_42 => X"{[17:9]_INIT_42}",
INIT_43 => X"{[17:9]_INIT_43}",
INIT_44 => X"{[17:9]_INIT_44}",
INIT_45 => X"{[17:9]_INIT_45}",
INIT_46 => X"{[17:9]_INIT_46}",
INIT_47 => X"{[17:9]_INIT_47}",
INIT_48 => X"{[17:9]_INIT_48}",
INIT_49 => X"{[17:9]_INIT_49}",
INIT_4A => X"{[17:9]_INIT_4A}",
INIT_4B => X"{[17:9]_INIT_4B}",
INIT_4C => X"{[17:9]_INIT_4C}",
INIT_4D => X"{[17:9]_INIT_4D}",
INIT_4E => X"{[17:9]_INIT_4E}",
INIT_4F => X"{[17:9]_INIT_4F}",
INIT_50 => X"{[17:9]_INIT_50}",
INIT_51 => X"{[17:9]_INIT_51}",
INIT_52 => X"{[17:9]_INIT_52}",
INIT_53 => X"{[17:9]_INIT_53}",
INIT_54 => X"{[17:9]_INIT_54}",
INIT_55 => X"{[17:9]_INIT_55}",
INIT_56 => X"{[17:9]_INIT_56}",
INIT_57 => X"{[17:9]_INIT_57}",
INIT_58 => X"{[17:9]_INIT_58}",
INIT_59 => X"{[17:9]_INIT_59}",
INIT_5A => X"{[17:9]_INIT_5A}",
INIT_5B => X"{[17:9]_INIT_5B}",
INIT_5C => X"{[17:9]_INIT_5C}",
INIT_5D => X"{[17:9]_INIT_5D}",
INIT_5E => X"{[17:9]_INIT_5E}",
INIT_5F => X"{[17:9]_INIT_5F}",
INIT_60 => X"{[17:9]_INIT_60}",
INIT_61 => X"{[17:9]_INIT_61}",
INIT_62 => X"{[17:9]_INIT_62}",
INIT_63 => X"{[17:9]_INIT_63}",
INIT_64 => X"{[17:9]_INIT_64}",
INIT_65 => X"{[17:9]_INIT_65}",
INIT_66 => X"{[17:9]_INIT_66}",
INIT_67 => X"{[17:9]_INIT_67}",
INIT_68 => X"{[17:9]_INIT_68}",
INIT_69 => X"{[17:9]_INIT_69}",
INIT_6A => X"{[17:9]_INIT_6A}",
INIT_6B => X"{[17:9]_INIT_6B}",
INIT_6C => X"{[17:9]_INIT_6C}",
INIT_6D => X"{[17:9]_INIT_6D}",
INIT_6E => X"{[17:9]_INIT_6E}",
INIT_6F => X"{[17:9]_INIT_6F}",
INIT_70 => X"{[17:9]_INIT_70}",
INIT_71 => X"{[17:9]_INIT_71}",
INIT_72 => X"{[17:9]_INIT_72}",
INIT_73 => X"{[17:9]_INIT_73}",
INIT_74 => X"{[17:9]_INIT_74}",
INIT_75 => X"{[17:9]_INIT_75}",
INIT_76 => X"{[17:9]_INIT_76}",
INIT_77 => X"{[17:9]_INIT_77}",
INIT_78 => X"{[17:9]_INIT_78}",
INIT_79 => X"{[17:9]_INIT_79}",
INIT_7A => X"{[17:9]_INIT_7A}",
INIT_7B => X"{[17:9]_INIT_7B}",
INIT_7C => X"{[17:9]_INIT_7C}",
INIT_7D => X"{[17:9]_INIT_7D}",
INIT_7E => X"{[17:9]_INIT_7E}",
INIT_7F => X"{[17:9]_INIT_7F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}",
INITP_08 => X"{[17:9]_INITP_08}",
INITP_09 => X"{[17:9]_INITP_09}",
INITP_0A => X"{[17:9]_INITP_0A}",
INITP_0B => X"{[17:9]_INITP_0B}",
INITP_0C => X"{[17:9]_INITP_0C}",
INITP_0D => X"{[17:9]_INITP_0D}",
INITP_0E => X"{[17:9]_INITP_0E}",
INITP_0F => X"{[17:9]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a <= '1' & address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b <= '1' & jtag_addr(11 downto 0) & "111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INIT_40 => X"{[8:0]_INIT_40}",
INIT_41 => X"{[8:0]_INIT_41}",
INIT_42 => X"{[8:0]_INIT_42}",
INIT_43 => X"{[8:0]_INIT_43}",
INIT_44 => X"{[8:0]_INIT_44}",
INIT_45 => X"{[8:0]_INIT_45}",
INIT_46 => X"{[8:0]_INIT_46}",
INIT_47 => X"{[8:0]_INIT_47}",
INIT_48 => X"{[8:0]_INIT_48}",
INIT_49 => X"{[8:0]_INIT_49}",
INIT_4A => X"{[8:0]_INIT_4A}",
INIT_4B => X"{[8:0]_INIT_4B}",
INIT_4C => X"{[8:0]_INIT_4C}",
INIT_4D => X"{[8:0]_INIT_4D}",
INIT_4E => X"{[8:0]_INIT_4E}",
INIT_4F => X"{[8:0]_INIT_4F}",
INIT_50 => X"{[8:0]_INIT_50}",
INIT_51 => X"{[8:0]_INIT_51}",
INIT_52 => X"{[8:0]_INIT_52}",
INIT_53 => X"{[8:0]_INIT_53}",
INIT_54 => X"{[8:0]_INIT_54}",
INIT_55 => X"{[8:0]_INIT_55}",
INIT_56 => X"{[8:0]_INIT_56}",
INIT_57 => X"{[8:0]_INIT_57}",
INIT_58 => X"{[8:0]_INIT_58}",
INIT_59 => X"{[8:0]_INIT_59}",
INIT_5A => X"{[8:0]_INIT_5A}",
INIT_5B => X"{[8:0]_INIT_5B}",
INIT_5C => X"{[8:0]_INIT_5C}",
INIT_5D => X"{[8:0]_INIT_5D}",
INIT_5E => X"{[8:0]_INIT_5E}",
INIT_5F => X"{[8:0]_INIT_5F}",
INIT_60 => X"{[8:0]_INIT_60}",
INIT_61 => X"{[8:0]_INIT_61}",
INIT_62 => X"{[8:0]_INIT_62}",
INIT_63 => X"{[8:0]_INIT_63}",
INIT_64 => X"{[8:0]_INIT_64}",
INIT_65 => X"{[8:0]_INIT_65}",
INIT_66 => X"{[8:0]_INIT_66}",
INIT_67 => X"{[8:0]_INIT_67}",
INIT_68 => X"{[8:0]_INIT_68}",
INIT_69 => X"{[8:0]_INIT_69}",
INIT_6A => X"{[8:0]_INIT_6A}",
INIT_6B => X"{[8:0]_INIT_6B}",
INIT_6C => X"{[8:0]_INIT_6C}",
INIT_6D => X"{[8:0]_INIT_6D}",
INIT_6E => X"{[8:0]_INIT_6E}",
INIT_6F => X"{[8:0]_INIT_6F}",
INIT_70 => X"{[8:0]_INIT_70}",
INIT_71 => X"{[8:0]_INIT_71}",
INIT_72 => X"{[8:0]_INIT_72}",
INIT_73 => X"{[8:0]_INIT_73}",
INIT_74 => X"{[8:0]_INIT_74}",
INIT_75 => X"{[8:0]_INIT_75}",
INIT_76 => X"{[8:0]_INIT_76}",
INIT_77 => X"{[8:0]_INIT_77}",
INIT_78 => X"{[8:0]_INIT_78}",
INIT_79 => X"{[8:0]_INIT_79}",
INIT_7A => X"{[8:0]_INIT_7A}",
INIT_7B => X"{[8:0]_INIT_7B}",
INIT_7C => X"{[8:0]_INIT_7C}",
INIT_7D => X"{[8:0]_INIT_7D}",
INIT_7E => X"{[8:0]_INIT_7E}",
INIT_7F => X"{[8:0]_INIT_7F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}",
INITP_08 => X"{[8:0]_INITP_08}",
INITP_09 => X"{[8:0]_INITP_09}",
INITP_0A => X"{[8:0]_INITP_0A}",
INITP_0B => X"{[8:0]_INITP_0B}",
INITP_0C => X"{[8:0]_INITP_0C}",
INITP_0D => X"{[8:0]_INITP_0D}",
INITP_0E => X"{[8:0]_INITP_0E}",
INITP_0F => X"{[8:0]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
kcpsm6_rom_h: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INIT_40 => X"{[17:9]_INIT_40}",
INIT_41 => X"{[17:9]_INIT_41}",
INIT_42 => X"{[17:9]_INIT_42}",
INIT_43 => X"{[17:9]_INIT_43}",
INIT_44 => X"{[17:9]_INIT_44}",
INIT_45 => X"{[17:9]_INIT_45}",
INIT_46 => X"{[17:9]_INIT_46}",
INIT_47 => X"{[17:9]_INIT_47}",
INIT_48 => X"{[17:9]_INIT_48}",
INIT_49 => X"{[17:9]_INIT_49}",
INIT_4A => X"{[17:9]_INIT_4A}",
INIT_4B => X"{[17:9]_INIT_4B}",
INIT_4C => X"{[17:9]_INIT_4C}",
INIT_4D => X"{[17:9]_INIT_4D}",
INIT_4E => X"{[17:9]_INIT_4E}",
INIT_4F => X"{[17:9]_INIT_4F}",
INIT_50 => X"{[17:9]_INIT_50}",
INIT_51 => X"{[17:9]_INIT_51}",
INIT_52 => X"{[17:9]_INIT_52}",
INIT_53 => X"{[17:9]_INIT_53}",
INIT_54 => X"{[17:9]_INIT_54}",
INIT_55 => X"{[17:9]_INIT_55}",
INIT_56 => X"{[17:9]_INIT_56}",
INIT_57 => X"{[17:9]_INIT_57}",
INIT_58 => X"{[17:9]_INIT_58}",
INIT_59 => X"{[17:9]_INIT_59}",
INIT_5A => X"{[17:9]_INIT_5A}",
INIT_5B => X"{[17:9]_INIT_5B}",
INIT_5C => X"{[17:9]_INIT_5C}",
INIT_5D => X"{[17:9]_INIT_5D}",
INIT_5E => X"{[17:9]_INIT_5E}",
INIT_5F => X"{[17:9]_INIT_5F}",
INIT_60 => X"{[17:9]_INIT_60}",
INIT_61 => X"{[17:9]_INIT_61}",
INIT_62 => X"{[17:9]_INIT_62}",
INIT_63 => X"{[17:9]_INIT_63}",
INIT_64 => X"{[17:9]_INIT_64}",
INIT_65 => X"{[17:9]_INIT_65}",
INIT_66 => X"{[17:9]_INIT_66}",
INIT_67 => X"{[17:9]_INIT_67}",
INIT_68 => X"{[17:9]_INIT_68}",
INIT_69 => X"{[17:9]_INIT_69}",
INIT_6A => X"{[17:9]_INIT_6A}",
INIT_6B => X"{[17:9]_INIT_6B}",
INIT_6C => X"{[17:9]_INIT_6C}",
INIT_6D => X"{[17:9]_INIT_6D}",
INIT_6E => X"{[17:9]_INIT_6E}",
INIT_6F => X"{[17:9]_INIT_6F}",
INIT_70 => X"{[17:9]_INIT_70}",
INIT_71 => X"{[17:9]_INIT_71}",
INIT_72 => X"{[17:9]_INIT_72}",
INIT_73 => X"{[17:9]_INIT_73}",
INIT_74 => X"{[17:9]_INIT_74}",
INIT_75 => X"{[17:9]_INIT_75}",
INIT_76 => X"{[17:9]_INIT_76}",
INIT_77 => X"{[17:9]_INIT_77}",
INIT_78 => X"{[17:9]_INIT_78}",
INIT_79 => X"{[17:9]_INIT_79}",
INIT_7A => X"{[17:9]_INIT_7A}",
INIT_7B => X"{[17:9]_INIT_7B}",
INIT_7C => X"{[17:9]_INIT_7C}",
INIT_7D => X"{[17:9]_INIT_7D}",
INIT_7E => X"{[17:9]_INIT_7E}",
INIT_7F => X"{[17:9]_INIT_7F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}",
INITP_08 => X"{[17:9]_INITP_08}",
INITP_09 => X"{[17:9]_INITP_09}",
INITP_0A => X"{[17:9]_INITP_0A}",
INITP_0B => X"{[17:9]_INITP_0B}",
INITP_0C => X"{[17:9]_INITP_0C}",
INITP_0D => X"{[17:9]_INITP_0D}",
INITP_0E => X"{[17:9]_INITP_0E}",
INITP_0F => X"{[17:9]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate akv7;
--
end generate ram_4k_generate;
--
--
--
--
-- JTAG Loader
--
instantiate_loader : if (C_JTAG_LOADER_ENABLE = 1) generate
--
jtag_loader_6_inst : jtag_loader_6
generic map( C_FAMILY => C_FAMILY,
C_NUM_PICOBLAZE => 1,
C_JTAG_LOADER_ENABLE => C_JTAG_LOADER_ENABLE,
C_BRAM_MAX_ADDR_WIDTH => BRAM_ADDRESS_WIDTH,
C_ADDR_WIDTH_0 => BRAM_ADDRESS_WIDTH)
port map( picoblaze_reset => rdl_bus,
jtag_en => jtag_en,
jtag_din => jtag_din,
jtag_addr => jtag_addr(BRAM_ADDRESS_WIDTH-1 downto 0),
jtag_clk => jtag_clk,
jtag_we => jtag_we,
jtag_dout_0 => jtag_dout,
jtag_dout_1 => jtag_dout, -- ports 1-7 are not used
jtag_dout_2 => jtag_dout, -- in a 1 device debug
jtag_dout_3 => jtag_dout, -- session. However, Synplify
jtag_dout_4 => jtag_dout, -- etc require all ports to
jtag_dout_5 => jtag_dout, -- be connected
jtag_dout_6 => jtag_dout,
jtag_dout_7 => jtag_dout);
--
end generate instantiate_loader;
--
end low_level_definition;
--
--
-------------------------------------------------------------------------------------------
--
-- JTAG Loader
--
-------------------------------------------------------------------------------------------
--
--
-- JTAG Loader 6 - Version 6.00
-- Kris Chaplin 4 February 2010
-- Ken Chapman 15 August 2011 - Revised coding style
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
library unisim;
use unisim.vcomponents.all;
--
entity jtag_loader_6 is
generic( C_JTAG_LOADER_ENABLE : integer := 1;
C_FAMILY : string := "V6";
C_NUM_PICOBLAZE : integer := 1;
C_BRAM_MAX_ADDR_WIDTH : integer := 10;
C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18;
C_JTAG_CHAIN : integer := 2;
C_ADDR_WIDTH_0 : integer := 10;
C_ADDR_WIDTH_1 : integer := 10;
C_ADDR_WIDTH_2 : integer := 10;
C_ADDR_WIDTH_3 : integer := 10;
C_ADDR_WIDTH_4 : integer := 10;
C_ADDR_WIDTH_5 : integer := 10;
C_ADDR_WIDTH_6 : integer := 10;
C_ADDR_WIDTH_7 : integer := 10);
port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
jtag_din : out std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0');
jtag_addr : out std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0) := (others => '0');
jtag_clk : out std_logic := '0';
jtag_we : out std_logic := '0';
jtag_dout_0 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_1 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_2 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_3 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_4 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_5 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_6 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_7 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0));
end jtag_loader_6;
--
architecture Behavioral of jtag_loader_6 is
--
signal num_picoblaze : std_logic_vector(2 downto 0);
signal picoblaze_instruction_data_width : std_logic_vector(4 downto 0);
--
signal drck : std_logic;
signal shift_clk : std_logic;
signal shift_din : std_logic;
signal shift_dout : std_logic;
signal shift : std_logic;
signal capture : std_logic;
--
signal control_reg_ce : std_logic;
signal bram_ce : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
signal bus_zero : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
signal jtag_en_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
signal jtag_en_expanded : std_logic_vector(7 downto 0) := (others => '0');
signal jtag_addr_int : std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0);
signal jtag_din_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal control_din : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0');
signal control_dout : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0');
signal control_dout_int : std_logic_vector(7 downto 0):= (others => '0');
signal bram_dout_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0');
signal jtag_we_int : std_logic;
signal jtag_clk_int : std_logic;
signal bram_ce_valid : std_logic;
signal din_load : std_logic;
--
signal jtag_dout_0_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_1_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_2_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_3_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_4_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_5_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_6_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_7_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal picoblaze_reset_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
--
begin
bus_zero <= (others => '0');
--
jtag_loader_gen: if (C_JTAG_LOADER_ENABLE = 1) generate
--
-- Insert BSCAN primitive for target device architecture.
--
BSCAN_SPARTAN6_gen: if (C_FAMILY="S6") generate
begin
BSCAN_BLOCK_inst : BSCAN_SPARTAN6
generic map ( JTAG_CHAIN => C_JTAG_CHAIN)
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_SPARTAN6_gen;
--
BSCAN_VIRTEX6_gen: if (C_FAMILY="V6") generate
begin
BSCAN_BLOCK_inst: BSCAN_VIRTEX6
generic map( JTAG_CHAIN => C_JTAG_CHAIN,
DISABLE_JTAG => FALSE)
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_VIRTEX6_gen;
--
BSCAN_7SERIES_gen: if (C_FAMILY="7S") generate
begin
BSCAN_BLOCK_inst: BSCANE2
generic map( JTAG_CHAIN => C_JTAG_CHAIN,
DISABLE_JTAG => "FALSE")
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_7SERIES_gen;
--
--
-- Insert clock buffer to ensure reliable shift operations.
--
upload_clock: BUFG
port map( I => drck,
O => shift_clk);
--
--
-- Shift Register
--
--
control_reg_ce_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk = '1' then
if (shift = '1') then
control_reg_ce <= shift_din;
end if;
end if;
end process control_reg_ce_shift;
--
bram_ce_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
if(C_NUM_PICOBLAZE > 1) then
for i in 0 to C_NUM_PICOBLAZE-2 loop
bram_ce(i+1) <= bram_ce(i);
end loop;
end if;
bram_ce(0) <= control_reg_ce;
end if;
end if;
end process bram_ce_shift;
--
bram_we_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
jtag_we_int <= bram_ce(C_NUM_PICOBLAZE-1);
end if;
end if;
end process bram_we_shift;
--
bram_a_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
for i in 0 to C_BRAM_MAX_ADDR_WIDTH-2 loop
jtag_addr_int(i+1) <= jtag_addr_int(i);
end loop;
jtag_addr_int(0) <= jtag_we_int;
end if;
end if;
end process bram_a_shift;
--
bram_d_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (din_load = '1') then
jtag_din_int <= bram_dout_int;
elsif (shift = '1') then
for i in 0 to C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-2 loop
jtag_din_int(i+1) <= jtag_din_int(i);
end loop;
jtag_din_int(0) <= jtag_addr_int(C_BRAM_MAX_ADDR_WIDTH-1);
end if;
end if;
end process bram_d_shift;
--
shift_dout <= jtag_din_int(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1);
--
--
din_load_select:process (bram_ce, din_load, capture, bus_zero, control_reg_ce)
begin
if ( bram_ce = bus_zero ) then
din_load <= capture and control_reg_ce;
else
din_load <= capture;
end if;
end process din_load_select;
--
--
-- Control Registers
--
num_picoblaze <= conv_std_logic_vector(C_NUM_PICOBLAZE-1,3);
picoblaze_instruction_data_width <= conv_std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1,5);
--
control_registers: process(jtag_clk_int)
begin
if (jtag_clk_int'event and jtag_clk_int = '1') then
if (bram_ce_valid = '1') and (jtag_we_int = '0') and (control_reg_ce = '1') then
case (jtag_addr_int(3 downto 0)) is
when "0000" => -- 0 = version - returns (7 downto 4) illustrating number of PB
-- and (3 downto 0) picoblaze instruction data width
control_dout_int <= num_picoblaze & picoblaze_instruction_data_width;
when "0001" => -- 1 = PicoBlaze 0 reset / status
if (C_NUM_PICOBLAZE >= 1) then
control_dout_int <= picoblaze_reset_int(0) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_0-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0010" => -- 2 = PicoBlaze 1 reset / status
if (C_NUM_PICOBLAZE >= 2) then
control_dout_int <= picoblaze_reset_int(1) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_1-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0011" => -- 3 = PicoBlaze 2 reset / status
if (C_NUM_PICOBLAZE >= 3) then
control_dout_int <= picoblaze_reset_int(2) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_2-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0100" => -- 4 = PicoBlaze 3 reset / status
if (C_NUM_PICOBLAZE >= 4) then
control_dout_int <= picoblaze_reset_int(3) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_3-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0101" => -- 5 = PicoBlaze 4 reset / status
if (C_NUM_PICOBLAZE >= 5) then
control_dout_int <= picoblaze_reset_int(4) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_4-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0110" => -- 6 = PicoBlaze 5 reset / status
if (C_NUM_PICOBLAZE >= 6) then
control_dout_int <= picoblaze_reset_int(5) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_5-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0111" => -- 7 = PicoBlaze 6 reset / status
if (C_NUM_PICOBLAZE >= 7) then
control_dout_int <= picoblaze_reset_int(6) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_6-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "1000" => -- 8 = PicoBlaze 7 reset / status
if (C_NUM_PICOBLAZE >= 8) then
control_dout_int <= picoblaze_reset_int(7) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_7-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "1111" => control_dout_int <= conv_std_logic_vector(C_BRAM_MAX_ADDR_WIDTH -1,8);
when others => control_dout_int <= (others => '1');
end case;
else
control_dout_int <= (others => '0');
end if;
end if;
end process control_registers;
--
control_dout(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-8) <= control_dout_int;
--
pb_reset: process(jtag_clk_int)
begin
if (jtag_clk_int'event and jtag_clk_int = '1') then
if (bram_ce_valid = '1') and (jtag_we_int = '1') and (control_reg_ce = '1') then
picoblaze_reset_int(C_NUM_PICOBLAZE-1 downto 0) <= control_din(C_NUM_PICOBLAZE-1 downto 0);
end if;
end if;
end process pb_reset;
--
--
-- Assignments
--
control_dout (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-9 downto 0) <= (others => '0') when (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH > 8);
--
-- Qualify the blockram CS signal with bscan select output
jtag_en_int <= bram_ce when bram_ce_valid = '1' else (others => '0');
--
jtag_en_expanded(C_NUM_PICOBLAZE-1 downto 0) <= jtag_en_int;
jtag_en_expanded(7 downto C_NUM_PICOBLAZE) <= (others => '0') when (C_NUM_PICOBLAZE < 8);
--
bram_dout_int <= control_dout or jtag_dout_0_masked or jtag_dout_1_masked or jtag_dout_2_masked or jtag_dout_3_masked or jtag_dout_4_masked or jtag_dout_5_masked or jtag_dout_6_masked or jtag_dout_7_masked;
--
control_din <= jtag_din_int;
--
jtag_dout_0_masked <= jtag_dout_0 when jtag_en_expanded(0) = '1' else (others => '0');
jtag_dout_1_masked <= jtag_dout_1 when jtag_en_expanded(1) = '1' else (others => '0');
jtag_dout_2_masked <= jtag_dout_2 when jtag_en_expanded(2) = '1' else (others => '0');
jtag_dout_3_masked <= jtag_dout_3 when jtag_en_expanded(3) = '1' else (others => '0');
jtag_dout_4_masked <= jtag_dout_4 when jtag_en_expanded(4) = '1' else (others => '0');
jtag_dout_5_masked <= jtag_dout_5 when jtag_en_expanded(5) = '1' else (others => '0');
jtag_dout_6_masked <= jtag_dout_6 when jtag_en_expanded(6) = '1' else (others => '0');
jtag_dout_7_masked <= jtag_dout_7 when jtag_en_expanded(7) = '1' else (others => '0');
--
jtag_en <= jtag_en_int;
jtag_din <= jtag_din_int;
jtag_addr <= jtag_addr_int;
jtag_clk <= jtag_clk_int;
jtag_we <= jtag_we_int;
picoblaze_reset <= picoblaze_reset_int;
--
end generate jtag_loader_gen;
--
end Behavioral;
--
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
ROM_form.vhd
Template for a KCPSM6 program memory. This template is primarily for use during code
development including generic parameters for the convenient selection of device family,
program memory size and the ability to include the JTAG Loader hardware for rapid
software development.
Kris Chaplin and Ken Chapman (Xilinx Ltd)
17th September 2010 - First Release
4th February 2011 - Correction to definition of 'we_b' in V6/1K/JTAG instance.
3rd March 2011 - Minor adjustments to comments only.
16th August 2011 - Additions and adjustments for support of 7-Series in ISE v13.2.
Simplification of JTAG Loader definition.
23rd November 2012 - 4K program for Spartan-6.
14th March 2013 - Unused address inputs on Virtex-6 and 7-Series BRAMs connected
High to reflect descriptions in UG363 and UG473.
This is a VHDL template file for the KCPSM6 assembler.
This VHDL file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.vhd' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Definition of a program memory for KCPSM6 including generic parameters for the
-- convenient selection of device family, program memory size and the ability to include
-- the JTAG Loader hardware for rapid software development.
--
-- This file is primarily for use during code development and it is recommended that the
-- appropriate simplified program memory definition be used in a final production design.
--
-- Generic Values Comments
-- Parameter Supported
--
-- C_FAMILY "S6" Spartan-6 device
-- "V6" Virtex-6 device
-- "7S" 7-Series device
-- (Artix-7, Kintex-7, Virtex-7 or Zynq)
--
-- C_RAM_SIZE_KWORDS 1, 2 or 4 Size of program memory in K-instructions
--
-- C_JTAG_LOADER_ENABLE 0 or 1 Set to '1' to include JTAG Loader
--
-- Notes
--
-- If your design contains MULTIPLE KCPSM6 instances then only one should have the
-- JTAG Loader enabled at a time (i.e. make sure that C_JTAG_LOADER_ENABLE is only set to
-- '1' on one instance of the program memory). Advanced users may be interested to know
-- that it is possible to connect JTAG Loader to multiple memories and then to use the
-- JTAG Loader utility to specify which memory contents are to be modified. However,
-- this scheme does require some effort to set up and the additional connectivity of the
-- multiple BRAMs can impact the placement, routing and performance of the complete
-- design. Please contact the author at Xilinx for more detailed information.
--
-- Regardless of the size of program memory specified by C_RAM_SIZE_KWORDS, the complete
-- 12-bit address bus is connected to KCPSM6. This enables the generic to be modified
-- without requiring changes to the fundamental hardware definition. However, when the
-- program memory is 1K then only the lower 10-bits of the address are actually used and
-- the valid address range is 000 to 3FF hex. Likewise, for a 2K program only the lower
-- 11-bits of the address are actually used and the valid address range is 000 to 7FF hex.
--
-- Programs are stored in Block Memory (BRAM) and the number of BRAM used depends on the
-- size of the program and the device family.
--
-- In a Spartan-6 device a BRAM is capable of holding 1K instructions. Hence a 2K program
-- will require 2 BRAMs to be used and a 4K program will require 4 BRAMs to be used. It
-- should be noted that a 4K program is not such a natural fit in a Spartan-6 device and
-- the implementation also requires a small amount of logic resulting in slightly lower
-- performance. A Spartan-6 BRAM can also be split into two 9k-bit memories suggesting
-- that a program containing up to 512 instructions could be implemented. However, there
-- is a silicon errata which makes this unsuitable and therefore it is not supported by
-- this file.
--
-- In a Virtex-6 or any 7-Series device a BRAM is capable of holding 2K instructions so
-- obviously a 2K program requires only a single BRAM. Each BRAM can also be divided into
-- 2 smaller memories supporting programs of 1K in half of a 36k-bit BRAM (generally
-- reported as being an 18k-bit BRAM). For a program of 4K instructions, 2 BRAMs are used.
--
--
-- Program defined by '{psmname}.psm'.
--
-- Generated by KCPSM6 Assembler: {timestamp}.
--
-- Assembler used ROM_form template: ROM_form_JTAGLoader_14March13.vhd
--
-- Standard IEEE libraries
--
--
package jtag_loader_pkg is
function addr_width_calc (size_in_k: integer) return integer;
end jtag_loader_pkg;
--
package body jtag_loader_pkg is
function addr_width_calc (size_in_k: integer) return integer is
begin
if (size_in_k = 1) then return 10;
elsif (size_in_k = 2) then return 11;
elsif (size_in_k = 4) then return 12;
else report "Invalid BlockRAM size. Please set to 1, 2 or 4 K words." severity FAILURE;
end if;
return 0;
end function addr_width_calc;
end package body;
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.jtag_loader_pkg.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
generic( C_FAMILY : string := "S6";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
signal address_a : std_logic_vector(15 downto 0);
signal pipe_a11 : std_logic;
signal data_in_a : std_logic_vector(35 downto 0);
signal data_out_a : std_logic_vector(35 downto 0);
signal data_out_a_l : std_logic_vector(35 downto 0);
signal data_out_a_h : std_logic_vector(35 downto 0);
signal data_out_a_ll : std_logic_vector(35 downto 0);
signal data_out_a_lh : std_logic_vector(35 downto 0);
signal data_out_a_hl : std_logic_vector(35 downto 0);
signal data_out_a_hh : std_logic_vector(35 downto 0);
signal address_b : std_logic_vector(15 downto 0);
signal data_in_b : std_logic_vector(35 downto 0);
signal data_in_b_l : std_logic_vector(35 downto 0);
signal data_in_b_ll : std_logic_vector(35 downto 0);
signal data_in_b_hl : std_logic_vector(35 downto 0);
signal data_out_b : std_logic_vector(35 downto 0);
signal data_out_b_l : std_logic_vector(35 downto 0);
signal data_out_b_ll : std_logic_vector(35 downto 0);
signal data_out_b_hl : std_logic_vector(35 downto 0);
signal data_in_b_h : std_logic_vector(35 downto 0);
signal data_in_b_lh : std_logic_vector(35 downto 0);
signal data_in_b_hh : std_logic_vector(35 downto 0);
signal data_out_b_h : std_logic_vector(35 downto 0);
signal data_out_b_lh : std_logic_vector(35 downto 0);
signal data_out_b_hh : std_logic_vector(35 downto 0);
signal enable_b : std_logic;
signal clk_b : std_logic;
signal we_b : std_logic_vector(7 downto 0);
signal we_b_l : std_logic_vector(3 downto 0);
signal we_b_h : std_logic_vector(3 downto 0);
--
signal jtag_addr : std_logic_vector(11 downto 0);
signal jtag_we : std_logic;
signal jtag_we_l : std_logic;
signal jtag_we_h : std_logic;
signal jtag_clk : std_logic;
signal jtag_din : std_logic_vector(17 downto 0);
signal jtag_dout : std_logic_vector(17 downto 0);
signal jtag_dout_1 : std_logic_vector(17 downto 0);
signal jtag_en : std_logic_vector(0 downto 0);
--
signal picoblaze_reset : std_logic_vector(0 downto 0);
signal rdl_bus : std_logic_vector(0 downto 0);
--
constant BRAM_ADDRESS_WIDTH : integer := addr_width_calc(C_RAM_SIZE_KWORDS);
--
--
component jtag_loader_6
generic( C_JTAG_LOADER_ENABLE : integer := 1;
C_FAMILY : string := "V6";
C_NUM_PICOBLAZE : integer := 1;
C_BRAM_MAX_ADDR_WIDTH : integer := 10;
C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18;
C_JTAG_CHAIN : integer := 2;
C_ADDR_WIDTH_0 : integer := 10;
C_ADDR_WIDTH_1 : integer := 10;
C_ADDR_WIDTH_2 : integer := 10;
C_ADDR_WIDTH_3 : integer := 10;
C_ADDR_WIDTH_4 : integer := 10;
C_ADDR_WIDTH_5 : integer := 10;
C_ADDR_WIDTH_6 : integer := 10;
C_ADDR_WIDTH_7 : integer := 10);
port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_din : out STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_addr : out STD_LOGIC_VECTOR(C_BRAM_MAX_ADDR_WIDTH-1 downto 0);
jtag_clk : out std_logic;
jtag_we : out std_logic;
jtag_dout_0 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_1 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_2 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_3 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_4 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_5 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_6 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_7 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0));
end component;
--
begin
--
--
ram_1k_generate : if (C_RAM_SIZE_KWORDS = 1) generate
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "0000";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "0000000000000000000000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "0000";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB16BWER
generic map ( DATA_WIDTH_A => 18,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 18,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a(31 downto 0),
DOPA => data_out_a(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b(31 downto 0),
DOPB => data_out_b(35 downto 32),
DIB => data_in_b(31 downto 0),
DIPB => data_in_b(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(17 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b(17 downto 0) <= data_out_b(17 downto 0);
address_b(13 downto 0) <= "11111111111111";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b(17 downto 0) <= jtag_din(17 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "1111";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
port map( ADDRARDADDR => address_a(13 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(13 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b(3 downto 0),
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(17 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b(17 downto 0) <= data_out_b(17 downto 0);
address_b(13 downto 0) <= "11111111111111";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b(17 downto 0) <= jtag_din(17 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "1111";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
port map( ADDRARDADDR => address_a(13 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(13 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b(3 downto 0),
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
end generate akv7;
--
end generate ram_1k_generate;
--
--
--
ram_2k_generate : if (C_RAM_SIZE_KWORDS = 2) generate
--
--
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(10 downto 0) & "000";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_l(31 downto 0),
DOPA => data_out_a_l(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_l(31 downto 0),
DOPB => data_out_b_l(35 downto 32),
DIB => data_in_b_l(31 downto 0),
DIPB => data_in_b_l(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_h: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_h(31 downto 0),
DOPA => data_out_a_h(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_h(31 downto 0),
DOPB => data_out_b_h(35 downto 32),
DIB => data_in_b_h(31 downto 0),
DIPB => data_in_b_h(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b <= '1' & jtag_addr(10 downto 0) & "1111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INIT_40 => X"{INIT_40}",
INIT_41 => X"{INIT_41}",
INIT_42 => X"{INIT_42}",
INIT_43 => X"{INIT_43}",
INIT_44 => X"{INIT_44}",
INIT_45 => X"{INIT_45}",
INIT_46 => X"{INIT_46}",
INIT_47 => X"{INIT_47}",
INIT_48 => X"{INIT_48}",
INIT_49 => X"{INIT_49}",
INIT_4A => X"{INIT_4A}",
INIT_4B => X"{INIT_4B}",
INIT_4C => X"{INIT_4C}",
INIT_4D => X"{INIT_4D}",
INIT_4E => X"{INIT_4E}",
INIT_4F => X"{INIT_4F}",
INIT_50 => X"{INIT_50}",
INIT_51 => X"{INIT_51}",
INIT_52 => X"{INIT_52}",
INIT_53 => X"{INIT_53}",
INIT_54 => X"{INIT_54}",
INIT_55 => X"{INIT_55}",
INIT_56 => X"{INIT_56}",
INIT_57 => X"{INIT_57}",
INIT_58 => X"{INIT_58}",
INIT_59 => X"{INIT_59}",
INIT_5A => X"{INIT_5A}",
INIT_5B => X"{INIT_5B}",
INIT_5C => X"{INIT_5C}",
INIT_5D => X"{INIT_5D}",
INIT_5E => X"{INIT_5E}",
INIT_5F => X"{INIT_5F}",
INIT_60 => X"{INIT_60}",
INIT_61 => X"{INIT_61}",
INIT_62 => X"{INIT_62}",
INIT_63 => X"{INIT_63}",
INIT_64 => X"{INIT_64}",
INIT_65 => X"{INIT_65}",
INIT_66 => X"{INIT_66}",
INIT_67 => X"{INIT_67}",
INIT_68 => X"{INIT_68}",
INIT_69 => X"{INIT_69}",
INIT_6A => X"{INIT_6A}",
INIT_6B => X"{INIT_6B}",
INIT_6C => X"{INIT_6C}",
INIT_6D => X"{INIT_6D}",
INIT_6E => X"{INIT_6E}",
INIT_6F => X"{INIT_6F}",
INIT_70 => X"{INIT_70}",
INIT_71 => X"{INIT_71}",
INIT_72 => X"{INIT_72}",
INIT_73 => X"{INIT_73}",
INIT_74 => X"{INIT_74}",
INIT_75 => X"{INIT_75}",
INIT_76 => X"{INIT_76}",
INIT_77 => X"{INIT_77}",
INIT_78 => X"{INIT_78}",
INIT_79 => X"{INIT_79}",
INIT_7A => X"{INIT_7A}",
INIT_7B => X"{INIT_7B}",
INIT_7C => X"{INIT_7C}",
INIT_7D => X"{INIT_7D}",
INIT_7E => X"{INIT_7E}",
INIT_7F => X"{INIT_7F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}",
INITP_08 => X"{INITP_08}",
INITP_09 => X"{INITP_09}",
INITP_0A => X"{INITP_0A}",
INITP_0B => X"{INITP_0B}",
INITP_0C => X"{INITP_0C}",
INITP_0D => X"{INITP_0D}",
INITP_0E => X"{INITP_0E}",
INITP_0F => X"{INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b <= '1' & jtag_addr(10 downto 0) & "1111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INIT_40 => X"{INIT_40}",
INIT_41 => X"{INIT_41}",
INIT_42 => X"{INIT_42}",
INIT_43 => X"{INIT_43}",
INIT_44 => X"{INIT_44}",
INIT_45 => X"{INIT_45}",
INIT_46 => X"{INIT_46}",
INIT_47 => X"{INIT_47}",
INIT_48 => X"{INIT_48}",
INIT_49 => X"{INIT_49}",
INIT_4A => X"{INIT_4A}",
INIT_4B => X"{INIT_4B}",
INIT_4C => X"{INIT_4C}",
INIT_4D => X"{INIT_4D}",
INIT_4E => X"{INIT_4E}",
INIT_4F => X"{INIT_4F}",
INIT_50 => X"{INIT_50}",
INIT_51 => X"{INIT_51}",
INIT_52 => X"{INIT_52}",
INIT_53 => X"{INIT_53}",
INIT_54 => X"{INIT_54}",
INIT_55 => X"{INIT_55}",
INIT_56 => X"{INIT_56}",
INIT_57 => X"{INIT_57}",
INIT_58 => X"{INIT_58}",
INIT_59 => X"{INIT_59}",
INIT_5A => X"{INIT_5A}",
INIT_5B => X"{INIT_5B}",
INIT_5C => X"{INIT_5C}",
INIT_5D => X"{INIT_5D}",
INIT_5E => X"{INIT_5E}",
INIT_5F => X"{INIT_5F}",
INIT_60 => X"{INIT_60}",
INIT_61 => X"{INIT_61}",
INIT_62 => X"{INIT_62}",
INIT_63 => X"{INIT_63}",
INIT_64 => X"{INIT_64}",
INIT_65 => X"{INIT_65}",
INIT_66 => X"{INIT_66}",
INIT_67 => X"{INIT_67}",
INIT_68 => X"{INIT_68}",
INIT_69 => X"{INIT_69}",
INIT_6A => X"{INIT_6A}",
INIT_6B => X"{INIT_6B}",
INIT_6C => X"{INIT_6C}",
INIT_6D => X"{INIT_6D}",
INIT_6E => X"{INIT_6E}",
INIT_6F => X"{INIT_6F}",
INIT_70 => X"{INIT_70}",
INIT_71 => X"{INIT_71}",
INIT_72 => X"{INIT_72}",
INIT_73 => X"{INIT_73}",
INIT_74 => X"{INIT_74}",
INIT_75 => X"{INIT_75}",
INIT_76 => X"{INIT_76}",
INIT_77 => X"{INIT_77}",
INIT_78 => X"{INIT_78}",
INIT_79 => X"{INIT_79}",
INIT_7A => X"{INIT_7A}",
INIT_7B => X"{INIT_7B}",
INIT_7C => X"{INIT_7C}",
INIT_7D => X"{INIT_7D}",
INIT_7E => X"{INIT_7E}",
INIT_7F => X"{INIT_7F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}",
INITP_08 => X"{INITP_08}",
INITP_09 => X"{INITP_09}",
INITP_0A => X"{INITP_0A}",
INITP_0B => X"{INITP_0B}",
INITP_0C => X"{INITP_0C}",
INITP_0D => X"{INITP_0D}",
INITP_0E => X"{INITP_0E}",
INITP_0F => X"{INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate akv7;
--
end generate ram_2k_generate;
--
--
ram_4k_generate : if (C_RAM_SIZE_KWORDS = 4) generate
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(10 downto 0) & "000";
data_in_a <= "000000000000000000000000000000000000";
--
s6_a11_flop: FD
port map ( D => address(11),
Q => pipe_a11,
C => clk);
--
s6_4k_mux0_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(0),
I1 => data_out_a_hl(0),
I2 => data_out_a_ll(1),
I3 => data_out_a_hl(1),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(0),
O6 => instruction(1));
--
s6_4k_mux2_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(2),
I1 => data_out_a_hl(2),
I2 => data_out_a_ll(3),
I3 => data_out_a_hl(3),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(2),
O6 => instruction(3));
--
s6_4k_mux4_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(4),
I1 => data_out_a_hl(4),
I2 => data_out_a_ll(5),
I3 => data_out_a_hl(5),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(4),
O6 => instruction(5));
--
s6_4k_mux6_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(6),
I1 => data_out_a_hl(6),
I2 => data_out_a_ll(7),
I3 => data_out_a_hl(7),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(6),
O6 => instruction(7));
--
s6_4k_mux8_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(32),
I1 => data_out_a_hl(32),
I2 => data_out_a_lh(0),
I3 => data_out_a_hh(0),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(8),
O6 => instruction(9));
--
s6_4k_mux10_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(1),
I1 => data_out_a_hh(1),
I2 => data_out_a_lh(2),
I3 => data_out_a_hh(2),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(10),
O6 => instruction(11));
--
s6_4k_mux12_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(3),
I1 => data_out_a_hh(3),
I2 => data_out_a_lh(4),
I3 => data_out_a_hh(4),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(12),
O6 => instruction(13));
--
s6_4k_mux14_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(5),
I1 => data_out_a_hh(5),
I2 => data_out_a_lh(6),
I3 => data_out_a_hh(6),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(14),
O6 => instruction(15));
--
s6_4k_mux16_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(7),
I1 => data_out_a_hh(7),
I2 => data_out_a_lh(32),
I3 => data_out_a_hh(32),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(16),
O6 => instruction(17));
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_ll <= "000" & data_out_b_ll(32) & "000000000000000000000000" & data_out_b_ll(7 downto 0);
data_in_b_lh <= "000" & data_out_b_lh(32) & "000000000000000000000000" & data_out_b_lh(7 downto 0);
data_in_b_hl <= "000" & data_out_b_hl(32) & "000000000000000000000000" & data_out_b_hl(7 downto 0);
data_in_b_hh <= "000" & data_out_b_hh(32) & "000000000000000000000000" & data_out_b_hh(7 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b_l(3 downto 0) <= "0000";
we_b_h(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
jtag_dout <= data_out_b_lh(32) & data_out_b_lh(7 downto 0) & data_out_b_ll(32) & data_out_b_ll(7 downto 0);
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_lh <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_ll <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
data_in_b_hh <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_hl <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000";
--
s6_4k_jtag_we_lut: LUT6_2
generic map (INIT => X"8000000020000000")
port map( I0 => jtag_we,
I1 => jtag_addr(11),
I2 => '1',
I3 => '1',
I4 => '1',
I5 => '1',
O5 => jtag_we_l,
O6 => jtag_we_h);
--
we_b_l(3 downto 0) <= jtag_we_l & jtag_we_l & jtag_we_l & jtag_we_l;
we_b_h(3 downto 0) <= jtag_we_h & jtag_we_h & jtag_we_h & jtag_we_h;
--
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
--
s6_4k_jtag_mux0_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(0),
I1 => data_out_b_hl(0),
I2 => data_out_b_ll(1),
I3 => data_out_b_hl(1),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(0),
O6 => jtag_dout(1));
--
s6_4k_jtag_mux2_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(2),
I1 => data_out_b_hl(2),
I2 => data_out_b_ll(3),
I3 => data_out_b_hl(3),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(2),
O6 => jtag_dout(3));
--
s6_4k_jtag_mux4_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(4),
I1 => data_out_b_hl(4),
I2 => data_out_b_ll(5),
I3 => data_out_b_hl(5),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(4),
O6 => jtag_dout(5));
--
s6_4k_jtag_mux6_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(6),
I1 => data_out_b_hl(6),
I2 => data_out_b_ll(7),
I3 => data_out_b_hl(7),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(6),
O6 => jtag_dout(7));
--
s6_4k_jtag_mux8_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(32),
I1 => data_out_b_hl(32),
I2 => data_out_b_lh(0),
I3 => data_out_b_hh(0),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(8),
O6 => jtag_dout(9));
--
s6_4k_jtag_mux10_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(1),
I1 => data_out_b_hh(1),
I2 => data_out_b_lh(2),
I3 => data_out_b_hh(2),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(10),
O6 => jtag_dout(11));
--
s6_4k_jtag_mux12_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(3),
I1 => data_out_b_hh(3),
I2 => data_out_b_lh(4),
I3 => data_out_b_hh(4),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(12),
O6 => jtag_dout(13));
--
s6_4k_jtag_mux14_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(5),
I1 => data_out_b_hh(5),
I2 => data_out_b_lh(6),
I3 => data_out_b_hh(6),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(14),
O6 => jtag_dout(15));
--
s6_4k_jtag_mux16_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(7),
I1 => data_out_b_hh(7),
I2 => data_out_b_lh(32),
I3 => data_out_b_hh(32),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(16),
O6 => jtag_dout(17));
--
end generate loader;
--
kcpsm6_rom_ll: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_ll(31 downto 0),
DOPA => data_out_a_ll(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_ll(31 downto 0),
DOPB => data_out_b_ll(35 downto 32),
DIB => data_in_b_ll(31 downto 0),
DIPB => data_in_b_ll(35 downto 32),
WEB => we_b_l(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_lh: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_lh(31 downto 0),
DOPA => data_out_a_lh(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_lh(31 downto 0),
DOPB => data_out_b_lh(35 downto 32),
DIB => data_in_b_lh(31 downto 0),
DIPB => data_in_b_lh(35 downto 32),
WEB => we_b_l(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_hl: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[8:0]_INIT_40}",
INIT_01 => X"{[8:0]_INIT_41}",
INIT_02 => X"{[8:0]_INIT_42}",
INIT_03 => X"{[8:0]_INIT_43}",
INIT_04 => X"{[8:0]_INIT_44}",
INIT_05 => X"{[8:0]_INIT_45}",
INIT_06 => X"{[8:0]_INIT_46}",
INIT_07 => X"{[8:0]_INIT_47}",
INIT_08 => X"{[8:0]_INIT_48}",
INIT_09 => X"{[8:0]_INIT_49}",
INIT_0A => X"{[8:0]_INIT_4A}",
INIT_0B => X"{[8:0]_INIT_4B}",
INIT_0C => X"{[8:0]_INIT_4C}",
INIT_0D => X"{[8:0]_INIT_4D}",
INIT_0E => X"{[8:0]_INIT_4E}",
INIT_0F => X"{[8:0]_INIT_4F}",
INIT_10 => X"{[8:0]_INIT_50}",
INIT_11 => X"{[8:0]_INIT_51}",
INIT_12 => X"{[8:0]_INIT_52}",
INIT_13 => X"{[8:0]_INIT_53}",
INIT_14 => X"{[8:0]_INIT_54}",
INIT_15 => X"{[8:0]_INIT_55}",
INIT_16 => X"{[8:0]_INIT_56}",
INIT_17 => X"{[8:0]_INIT_57}",
INIT_18 => X"{[8:0]_INIT_58}",
INIT_19 => X"{[8:0]_INIT_59}",
INIT_1A => X"{[8:0]_INIT_5A}",
INIT_1B => X"{[8:0]_INIT_5B}",
INIT_1C => X"{[8:0]_INIT_5C}",
INIT_1D => X"{[8:0]_INIT_5D}",
INIT_1E => X"{[8:0]_INIT_5E}",
INIT_1F => X"{[8:0]_INIT_5F}",
INIT_20 => X"{[8:0]_INIT_60}",
INIT_21 => X"{[8:0]_INIT_61}",
INIT_22 => X"{[8:0]_INIT_62}",
INIT_23 => X"{[8:0]_INIT_63}",
INIT_24 => X"{[8:0]_INIT_64}",
INIT_25 => X"{[8:0]_INIT_65}",
INIT_26 => X"{[8:0]_INIT_66}",
INIT_27 => X"{[8:0]_INIT_67}",
INIT_28 => X"{[8:0]_INIT_68}",
INIT_29 => X"{[8:0]_INIT_69}",
INIT_2A => X"{[8:0]_INIT_6A}",
INIT_2B => X"{[8:0]_INIT_6B}",
INIT_2C => X"{[8:0]_INIT_6C}",
INIT_2D => X"{[8:0]_INIT_6D}",
INIT_2E => X"{[8:0]_INIT_6E}",
INIT_2F => X"{[8:0]_INIT_6F}",
INIT_30 => X"{[8:0]_INIT_70}",
INIT_31 => X"{[8:0]_INIT_71}",
INIT_32 => X"{[8:0]_INIT_72}",
INIT_33 => X"{[8:0]_INIT_73}",
INIT_34 => X"{[8:0]_INIT_74}",
INIT_35 => X"{[8:0]_INIT_75}",
INIT_36 => X"{[8:0]_INIT_76}",
INIT_37 => X"{[8:0]_INIT_77}",
INIT_38 => X"{[8:0]_INIT_78}",
INIT_39 => X"{[8:0]_INIT_79}",
INIT_3A => X"{[8:0]_INIT_7A}",
INIT_3B => X"{[8:0]_INIT_7B}",
INIT_3C => X"{[8:0]_INIT_7C}",
INIT_3D => X"{[8:0]_INIT_7D}",
INIT_3E => X"{[8:0]_INIT_7E}",
INIT_3F => X"{[8:0]_INIT_7F}",
INITP_00 => X"{[8:0]_INITP_08}",
INITP_01 => X"{[8:0]_INITP_09}",
INITP_02 => X"{[8:0]_INITP_0A}",
INITP_03 => X"{[8:0]_INITP_0B}",
INITP_04 => X"{[8:0]_INITP_0C}",
INITP_05 => X"{[8:0]_INITP_0D}",
INITP_06 => X"{[8:0]_INITP_0E}",
INITP_07 => X"{[8:0]_INITP_0F}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_hl(31 downto 0),
DOPA => data_out_a_hl(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_hl(31 downto 0),
DOPB => data_out_b_hl(35 downto 32),
DIB => data_in_b_hl(31 downto 0),
DIPB => data_in_b_hl(35 downto 32),
WEB => we_b_h(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_hh: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[17:9]_INIT_40}",
INIT_01 => X"{[17:9]_INIT_41}",
INIT_02 => X"{[17:9]_INIT_42}",
INIT_03 => X"{[17:9]_INIT_43}",
INIT_04 => X"{[17:9]_INIT_44}",
INIT_05 => X"{[17:9]_INIT_45}",
INIT_06 => X"{[17:9]_INIT_46}",
INIT_07 => X"{[17:9]_INIT_47}",
INIT_08 => X"{[17:9]_INIT_48}",
INIT_09 => X"{[17:9]_INIT_49}",
INIT_0A => X"{[17:9]_INIT_4A}",
INIT_0B => X"{[17:9]_INIT_4B}",
INIT_0C => X"{[17:9]_INIT_4C}",
INIT_0D => X"{[17:9]_INIT_4D}",
INIT_0E => X"{[17:9]_INIT_4E}",
INIT_0F => X"{[17:9]_INIT_4F}",
INIT_10 => X"{[17:9]_INIT_50}",
INIT_11 => X"{[17:9]_INIT_51}",
INIT_12 => X"{[17:9]_INIT_52}",
INIT_13 => X"{[17:9]_INIT_53}",
INIT_14 => X"{[17:9]_INIT_54}",
INIT_15 => X"{[17:9]_INIT_55}",
INIT_16 => X"{[17:9]_INIT_56}",
INIT_17 => X"{[17:9]_INIT_57}",
INIT_18 => X"{[17:9]_INIT_58}",
INIT_19 => X"{[17:9]_INIT_59}",
INIT_1A => X"{[17:9]_INIT_5A}",
INIT_1B => X"{[17:9]_INIT_5B}",
INIT_1C => X"{[17:9]_INIT_5C}",
INIT_1D => X"{[17:9]_INIT_5D}",
INIT_1E => X"{[17:9]_INIT_5E}",
INIT_1F => X"{[17:9]_INIT_5F}",
INIT_20 => X"{[17:9]_INIT_60}",
INIT_21 => X"{[17:9]_INIT_61}",
INIT_22 => X"{[17:9]_INIT_62}",
INIT_23 => X"{[17:9]_INIT_63}",
INIT_24 => X"{[17:9]_INIT_64}",
INIT_25 => X"{[17:9]_INIT_65}",
INIT_26 => X"{[17:9]_INIT_66}",
INIT_27 => X"{[17:9]_INIT_67}",
INIT_28 => X"{[17:9]_INIT_68}",
INIT_29 => X"{[17:9]_INIT_69}",
INIT_2A => X"{[17:9]_INIT_6A}",
INIT_2B => X"{[17:9]_INIT_6B}",
INIT_2C => X"{[17:9]_INIT_6C}",
INIT_2D => X"{[17:9]_INIT_6D}",
INIT_2E => X"{[17:9]_INIT_6E}",
INIT_2F => X"{[17:9]_INIT_6F}",
INIT_30 => X"{[17:9]_INIT_70}",
INIT_31 => X"{[17:9]_INIT_71}",
INIT_32 => X"{[17:9]_INIT_72}",
INIT_33 => X"{[17:9]_INIT_73}",
INIT_34 => X"{[17:9]_INIT_74}",
INIT_35 => X"{[17:9]_INIT_75}",
INIT_36 => X"{[17:9]_INIT_76}",
INIT_37 => X"{[17:9]_INIT_77}",
INIT_38 => X"{[17:9]_INIT_78}",
INIT_39 => X"{[17:9]_INIT_79}",
INIT_3A => X"{[17:9]_INIT_7A}",
INIT_3B => X"{[17:9]_INIT_7B}",
INIT_3C => X"{[17:9]_INIT_7C}",
INIT_3D => X"{[17:9]_INIT_7D}",
INIT_3E => X"{[17:9]_INIT_7E}",
INIT_3F => X"{[17:9]_INIT_7F}",
INITP_00 => X"{[17:9]_INITP_08}",
INITP_01 => X"{[17:9]_INITP_09}",
INITP_02 => X"{[17:9]_INITP_0A}",
INITP_03 => X"{[17:9]_INITP_0B}",
INITP_04 => X"{[17:9]_INITP_0C}",
INITP_05 => X"{[17:9]_INITP_0D}",
INITP_06 => X"{[17:9]_INITP_0E}",
INITP_07 => X"{[17:9]_INITP_0F}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_hh(31 downto 0),
DOPA => data_out_a_hh(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_hh(31 downto 0),
DOPB => data_out_b_hh(35 downto 32),
DIB => data_in_b_hh(31 downto 0),
DIPB => data_in_b_hh(35 downto 32),
WEB => we_b_h(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a <= '1' & address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b <= '1' & jtag_addr(11 downto 0) & "111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INIT_40 => X"{[8:0]_INIT_40}",
INIT_41 => X"{[8:0]_INIT_41}",
INIT_42 => X"{[8:0]_INIT_42}",
INIT_43 => X"{[8:0]_INIT_43}",
INIT_44 => X"{[8:0]_INIT_44}",
INIT_45 => X"{[8:0]_INIT_45}",
INIT_46 => X"{[8:0]_INIT_46}",
INIT_47 => X"{[8:0]_INIT_47}",
INIT_48 => X"{[8:0]_INIT_48}",
INIT_49 => X"{[8:0]_INIT_49}",
INIT_4A => X"{[8:0]_INIT_4A}",
INIT_4B => X"{[8:0]_INIT_4B}",
INIT_4C => X"{[8:0]_INIT_4C}",
INIT_4D => X"{[8:0]_INIT_4D}",
INIT_4E => X"{[8:0]_INIT_4E}",
INIT_4F => X"{[8:0]_INIT_4F}",
INIT_50 => X"{[8:0]_INIT_50}",
INIT_51 => X"{[8:0]_INIT_51}",
INIT_52 => X"{[8:0]_INIT_52}",
INIT_53 => X"{[8:0]_INIT_53}",
INIT_54 => X"{[8:0]_INIT_54}",
INIT_55 => X"{[8:0]_INIT_55}",
INIT_56 => X"{[8:0]_INIT_56}",
INIT_57 => X"{[8:0]_INIT_57}",
INIT_58 => X"{[8:0]_INIT_58}",
INIT_59 => X"{[8:0]_INIT_59}",
INIT_5A => X"{[8:0]_INIT_5A}",
INIT_5B => X"{[8:0]_INIT_5B}",
INIT_5C => X"{[8:0]_INIT_5C}",
INIT_5D => X"{[8:0]_INIT_5D}",
INIT_5E => X"{[8:0]_INIT_5E}",
INIT_5F => X"{[8:0]_INIT_5F}",
INIT_60 => X"{[8:0]_INIT_60}",
INIT_61 => X"{[8:0]_INIT_61}",
INIT_62 => X"{[8:0]_INIT_62}",
INIT_63 => X"{[8:0]_INIT_63}",
INIT_64 => X"{[8:0]_INIT_64}",
INIT_65 => X"{[8:0]_INIT_65}",
INIT_66 => X"{[8:0]_INIT_66}",
INIT_67 => X"{[8:0]_INIT_67}",
INIT_68 => X"{[8:0]_INIT_68}",
INIT_69 => X"{[8:0]_INIT_69}",
INIT_6A => X"{[8:0]_INIT_6A}",
INIT_6B => X"{[8:0]_INIT_6B}",
INIT_6C => X"{[8:0]_INIT_6C}",
INIT_6D => X"{[8:0]_INIT_6D}",
INIT_6E => X"{[8:0]_INIT_6E}",
INIT_6F => X"{[8:0]_INIT_6F}",
INIT_70 => X"{[8:0]_INIT_70}",
INIT_71 => X"{[8:0]_INIT_71}",
INIT_72 => X"{[8:0]_INIT_72}",
INIT_73 => X"{[8:0]_INIT_73}",
INIT_74 => X"{[8:0]_INIT_74}",
INIT_75 => X"{[8:0]_INIT_75}",
INIT_76 => X"{[8:0]_INIT_76}",
INIT_77 => X"{[8:0]_INIT_77}",
INIT_78 => X"{[8:0]_INIT_78}",
INIT_79 => X"{[8:0]_INIT_79}",
INIT_7A => X"{[8:0]_INIT_7A}",
INIT_7B => X"{[8:0]_INIT_7B}",
INIT_7C => X"{[8:0]_INIT_7C}",
INIT_7D => X"{[8:0]_INIT_7D}",
INIT_7E => X"{[8:0]_INIT_7E}",
INIT_7F => X"{[8:0]_INIT_7F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}",
INITP_08 => X"{[8:0]_INITP_08}",
INITP_09 => X"{[8:0]_INITP_09}",
INITP_0A => X"{[8:0]_INITP_0A}",
INITP_0B => X"{[8:0]_INITP_0B}",
INITP_0C => X"{[8:0]_INITP_0C}",
INITP_0D => X"{[8:0]_INITP_0D}",
INITP_0E => X"{[8:0]_INITP_0E}",
INITP_0F => X"{[8:0]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
kcpsm6_rom_h: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INIT_40 => X"{[17:9]_INIT_40}",
INIT_41 => X"{[17:9]_INIT_41}",
INIT_42 => X"{[17:9]_INIT_42}",
INIT_43 => X"{[17:9]_INIT_43}",
INIT_44 => X"{[17:9]_INIT_44}",
INIT_45 => X"{[17:9]_INIT_45}",
INIT_46 => X"{[17:9]_INIT_46}",
INIT_47 => X"{[17:9]_INIT_47}",
INIT_48 => X"{[17:9]_INIT_48}",
INIT_49 => X"{[17:9]_INIT_49}",
INIT_4A => X"{[17:9]_INIT_4A}",
INIT_4B => X"{[17:9]_INIT_4B}",
INIT_4C => X"{[17:9]_INIT_4C}",
INIT_4D => X"{[17:9]_INIT_4D}",
INIT_4E => X"{[17:9]_INIT_4E}",
INIT_4F => X"{[17:9]_INIT_4F}",
INIT_50 => X"{[17:9]_INIT_50}",
INIT_51 => X"{[17:9]_INIT_51}",
INIT_52 => X"{[17:9]_INIT_52}",
INIT_53 => X"{[17:9]_INIT_53}",
INIT_54 => X"{[17:9]_INIT_54}",
INIT_55 => X"{[17:9]_INIT_55}",
INIT_56 => X"{[17:9]_INIT_56}",
INIT_57 => X"{[17:9]_INIT_57}",
INIT_58 => X"{[17:9]_INIT_58}",
INIT_59 => X"{[17:9]_INIT_59}",
INIT_5A => X"{[17:9]_INIT_5A}",
INIT_5B => X"{[17:9]_INIT_5B}",
INIT_5C => X"{[17:9]_INIT_5C}",
INIT_5D => X"{[17:9]_INIT_5D}",
INIT_5E => X"{[17:9]_INIT_5E}",
INIT_5F => X"{[17:9]_INIT_5F}",
INIT_60 => X"{[17:9]_INIT_60}",
INIT_61 => X"{[17:9]_INIT_61}",
INIT_62 => X"{[17:9]_INIT_62}",
INIT_63 => X"{[17:9]_INIT_63}",
INIT_64 => X"{[17:9]_INIT_64}",
INIT_65 => X"{[17:9]_INIT_65}",
INIT_66 => X"{[17:9]_INIT_66}",
INIT_67 => X"{[17:9]_INIT_67}",
INIT_68 => X"{[17:9]_INIT_68}",
INIT_69 => X"{[17:9]_INIT_69}",
INIT_6A => X"{[17:9]_INIT_6A}",
INIT_6B => X"{[17:9]_INIT_6B}",
INIT_6C => X"{[17:9]_INIT_6C}",
INIT_6D => X"{[17:9]_INIT_6D}",
INIT_6E => X"{[17:9]_INIT_6E}",
INIT_6F => X"{[17:9]_INIT_6F}",
INIT_70 => X"{[17:9]_INIT_70}",
INIT_71 => X"{[17:9]_INIT_71}",
INIT_72 => X"{[17:9]_INIT_72}",
INIT_73 => X"{[17:9]_INIT_73}",
INIT_74 => X"{[17:9]_INIT_74}",
INIT_75 => X"{[17:9]_INIT_75}",
INIT_76 => X"{[17:9]_INIT_76}",
INIT_77 => X"{[17:9]_INIT_77}",
INIT_78 => X"{[17:9]_INIT_78}",
INIT_79 => X"{[17:9]_INIT_79}",
INIT_7A => X"{[17:9]_INIT_7A}",
INIT_7B => X"{[17:9]_INIT_7B}",
INIT_7C => X"{[17:9]_INIT_7C}",
INIT_7D => X"{[17:9]_INIT_7D}",
INIT_7E => X"{[17:9]_INIT_7E}",
INIT_7F => X"{[17:9]_INIT_7F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}",
INITP_08 => X"{[17:9]_INITP_08}",
INITP_09 => X"{[17:9]_INITP_09}",
INITP_0A => X"{[17:9]_INITP_0A}",
INITP_0B => X"{[17:9]_INITP_0B}",
INITP_0C => X"{[17:9]_INITP_0C}",
INITP_0D => X"{[17:9]_INITP_0D}",
INITP_0E => X"{[17:9]_INITP_0E}",
INITP_0F => X"{[17:9]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a <= '1' & address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b <= '1' & jtag_addr(11 downto 0) & "111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INIT_40 => X"{[8:0]_INIT_40}",
INIT_41 => X"{[8:0]_INIT_41}",
INIT_42 => X"{[8:0]_INIT_42}",
INIT_43 => X"{[8:0]_INIT_43}",
INIT_44 => X"{[8:0]_INIT_44}",
INIT_45 => X"{[8:0]_INIT_45}",
INIT_46 => X"{[8:0]_INIT_46}",
INIT_47 => X"{[8:0]_INIT_47}",
INIT_48 => X"{[8:0]_INIT_48}",
INIT_49 => X"{[8:0]_INIT_49}",
INIT_4A => X"{[8:0]_INIT_4A}",
INIT_4B => X"{[8:0]_INIT_4B}",
INIT_4C => X"{[8:0]_INIT_4C}",
INIT_4D => X"{[8:0]_INIT_4D}",
INIT_4E => X"{[8:0]_INIT_4E}",
INIT_4F => X"{[8:0]_INIT_4F}",
INIT_50 => X"{[8:0]_INIT_50}",
INIT_51 => X"{[8:0]_INIT_51}",
INIT_52 => X"{[8:0]_INIT_52}",
INIT_53 => X"{[8:0]_INIT_53}",
INIT_54 => X"{[8:0]_INIT_54}",
INIT_55 => X"{[8:0]_INIT_55}",
INIT_56 => X"{[8:0]_INIT_56}",
INIT_57 => X"{[8:0]_INIT_57}",
INIT_58 => X"{[8:0]_INIT_58}",
INIT_59 => X"{[8:0]_INIT_59}",
INIT_5A => X"{[8:0]_INIT_5A}",
INIT_5B => X"{[8:0]_INIT_5B}",
INIT_5C => X"{[8:0]_INIT_5C}",
INIT_5D => X"{[8:0]_INIT_5D}",
INIT_5E => X"{[8:0]_INIT_5E}",
INIT_5F => X"{[8:0]_INIT_5F}",
INIT_60 => X"{[8:0]_INIT_60}",
INIT_61 => X"{[8:0]_INIT_61}",
INIT_62 => X"{[8:0]_INIT_62}",
INIT_63 => X"{[8:0]_INIT_63}",
INIT_64 => X"{[8:0]_INIT_64}",
INIT_65 => X"{[8:0]_INIT_65}",
INIT_66 => X"{[8:0]_INIT_66}",
INIT_67 => X"{[8:0]_INIT_67}",
INIT_68 => X"{[8:0]_INIT_68}",
INIT_69 => X"{[8:0]_INIT_69}",
INIT_6A => X"{[8:0]_INIT_6A}",
INIT_6B => X"{[8:0]_INIT_6B}",
INIT_6C => X"{[8:0]_INIT_6C}",
INIT_6D => X"{[8:0]_INIT_6D}",
INIT_6E => X"{[8:0]_INIT_6E}",
INIT_6F => X"{[8:0]_INIT_6F}",
INIT_70 => X"{[8:0]_INIT_70}",
INIT_71 => X"{[8:0]_INIT_71}",
INIT_72 => X"{[8:0]_INIT_72}",
INIT_73 => X"{[8:0]_INIT_73}",
INIT_74 => X"{[8:0]_INIT_74}",
INIT_75 => X"{[8:0]_INIT_75}",
INIT_76 => X"{[8:0]_INIT_76}",
INIT_77 => X"{[8:0]_INIT_77}",
INIT_78 => X"{[8:0]_INIT_78}",
INIT_79 => X"{[8:0]_INIT_79}",
INIT_7A => X"{[8:0]_INIT_7A}",
INIT_7B => X"{[8:0]_INIT_7B}",
INIT_7C => X"{[8:0]_INIT_7C}",
INIT_7D => X"{[8:0]_INIT_7D}",
INIT_7E => X"{[8:0]_INIT_7E}",
INIT_7F => X"{[8:0]_INIT_7F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}",
INITP_08 => X"{[8:0]_INITP_08}",
INITP_09 => X"{[8:0]_INITP_09}",
INITP_0A => X"{[8:0]_INITP_0A}",
INITP_0B => X"{[8:0]_INITP_0B}",
INITP_0C => X"{[8:0]_INITP_0C}",
INITP_0D => X"{[8:0]_INITP_0D}",
INITP_0E => X"{[8:0]_INITP_0E}",
INITP_0F => X"{[8:0]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
kcpsm6_rom_h: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INIT_40 => X"{[17:9]_INIT_40}",
INIT_41 => X"{[17:9]_INIT_41}",
INIT_42 => X"{[17:9]_INIT_42}",
INIT_43 => X"{[17:9]_INIT_43}",
INIT_44 => X"{[17:9]_INIT_44}",
INIT_45 => X"{[17:9]_INIT_45}",
INIT_46 => X"{[17:9]_INIT_46}",
INIT_47 => X"{[17:9]_INIT_47}",
INIT_48 => X"{[17:9]_INIT_48}",
INIT_49 => X"{[17:9]_INIT_49}",
INIT_4A => X"{[17:9]_INIT_4A}",
INIT_4B => X"{[17:9]_INIT_4B}",
INIT_4C => X"{[17:9]_INIT_4C}",
INIT_4D => X"{[17:9]_INIT_4D}",
INIT_4E => X"{[17:9]_INIT_4E}",
INIT_4F => X"{[17:9]_INIT_4F}",
INIT_50 => X"{[17:9]_INIT_50}",
INIT_51 => X"{[17:9]_INIT_51}",
INIT_52 => X"{[17:9]_INIT_52}",
INIT_53 => X"{[17:9]_INIT_53}",
INIT_54 => X"{[17:9]_INIT_54}",
INIT_55 => X"{[17:9]_INIT_55}",
INIT_56 => X"{[17:9]_INIT_56}",
INIT_57 => X"{[17:9]_INIT_57}",
INIT_58 => X"{[17:9]_INIT_58}",
INIT_59 => X"{[17:9]_INIT_59}",
INIT_5A => X"{[17:9]_INIT_5A}",
INIT_5B => X"{[17:9]_INIT_5B}",
INIT_5C => X"{[17:9]_INIT_5C}",
INIT_5D => X"{[17:9]_INIT_5D}",
INIT_5E => X"{[17:9]_INIT_5E}",
INIT_5F => X"{[17:9]_INIT_5F}",
INIT_60 => X"{[17:9]_INIT_60}",
INIT_61 => X"{[17:9]_INIT_61}",
INIT_62 => X"{[17:9]_INIT_62}",
INIT_63 => X"{[17:9]_INIT_63}",
INIT_64 => X"{[17:9]_INIT_64}",
INIT_65 => X"{[17:9]_INIT_65}",
INIT_66 => X"{[17:9]_INIT_66}",
INIT_67 => X"{[17:9]_INIT_67}",
INIT_68 => X"{[17:9]_INIT_68}",
INIT_69 => X"{[17:9]_INIT_69}",
INIT_6A => X"{[17:9]_INIT_6A}",
INIT_6B => X"{[17:9]_INIT_6B}",
INIT_6C => X"{[17:9]_INIT_6C}",
INIT_6D => X"{[17:9]_INIT_6D}",
INIT_6E => X"{[17:9]_INIT_6E}",
INIT_6F => X"{[17:9]_INIT_6F}",
INIT_70 => X"{[17:9]_INIT_70}",
INIT_71 => X"{[17:9]_INIT_71}",
INIT_72 => X"{[17:9]_INIT_72}",
INIT_73 => X"{[17:9]_INIT_73}",
INIT_74 => X"{[17:9]_INIT_74}",
INIT_75 => X"{[17:9]_INIT_75}",
INIT_76 => X"{[17:9]_INIT_76}",
INIT_77 => X"{[17:9]_INIT_77}",
INIT_78 => X"{[17:9]_INIT_78}",
INIT_79 => X"{[17:9]_INIT_79}",
INIT_7A => X"{[17:9]_INIT_7A}",
INIT_7B => X"{[17:9]_INIT_7B}",
INIT_7C => X"{[17:9]_INIT_7C}",
INIT_7D => X"{[17:9]_INIT_7D}",
INIT_7E => X"{[17:9]_INIT_7E}",
INIT_7F => X"{[17:9]_INIT_7F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}",
INITP_08 => X"{[17:9]_INITP_08}",
INITP_09 => X"{[17:9]_INITP_09}",
INITP_0A => X"{[17:9]_INITP_0A}",
INITP_0B => X"{[17:9]_INITP_0B}",
INITP_0C => X"{[17:9]_INITP_0C}",
INITP_0D => X"{[17:9]_INITP_0D}",
INITP_0E => X"{[17:9]_INITP_0E}",
INITP_0F => X"{[17:9]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate akv7;
--
end generate ram_4k_generate;
--
--
--
--
-- JTAG Loader
--
instantiate_loader : if (C_JTAG_LOADER_ENABLE = 1) generate
--
jtag_loader_6_inst : jtag_loader_6
generic map( C_FAMILY => C_FAMILY,
C_NUM_PICOBLAZE => 1,
C_JTAG_LOADER_ENABLE => C_JTAG_LOADER_ENABLE,
C_BRAM_MAX_ADDR_WIDTH => BRAM_ADDRESS_WIDTH,
C_ADDR_WIDTH_0 => BRAM_ADDRESS_WIDTH)
port map( picoblaze_reset => rdl_bus,
jtag_en => jtag_en,
jtag_din => jtag_din,
jtag_addr => jtag_addr(BRAM_ADDRESS_WIDTH-1 downto 0),
jtag_clk => jtag_clk,
jtag_we => jtag_we,
jtag_dout_0 => jtag_dout,
jtag_dout_1 => jtag_dout, -- ports 1-7 are not used
jtag_dout_2 => jtag_dout, -- in a 1 device debug
jtag_dout_3 => jtag_dout, -- session. However, Synplify
jtag_dout_4 => jtag_dout, -- etc require all ports to
jtag_dout_5 => jtag_dout, -- be connected
jtag_dout_6 => jtag_dout,
jtag_dout_7 => jtag_dout);
--
end generate instantiate_loader;
--
end low_level_definition;
--
--
-------------------------------------------------------------------------------------------
--
-- JTAG Loader
--
-------------------------------------------------------------------------------------------
--
--
-- JTAG Loader 6 - Version 6.00
-- Kris Chaplin 4 February 2010
-- Ken Chapman 15 August 2011 - Revised coding style
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
library unisim;
use unisim.vcomponents.all;
--
entity jtag_loader_6 is
generic( C_JTAG_LOADER_ENABLE : integer := 1;
C_FAMILY : string := "V6";
C_NUM_PICOBLAZE : integer := 1;
C_BRAM_MAX_ADDR_WIDTH : integer := 10;
C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18;
C_JTAG_CHAIN : integer := 2;
C_ADDR_WIDTH_0 : integer := 10;
C_ADDR_WIDTH_1 : integer := 10;
C_ADDR_WIDTH_2 : integer := 10;
C_ADDR_WIDTH_3 : integer := 10;
C_ADDR_WIDTH_4 : integer := 10;
C_ADDR_WIDTH_5 : integer := 10;
C_ADDR_WIDTH_6 : integer := 10;
C_ADDR_WIDTH_7 : integer := 10);
port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
jtag_din : out std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0');
jtag_addr : out std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0) := (others => '0');
jtag_clk : out std_logic := '0';
jtag_we : out std_logic := '0';
jtag_dout_0 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_1 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_2 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_3 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_4 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_5 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_6 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_7 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0));
end jtag_loader_6;
--
architecture Behavioral of jtag_loader_6 is
--
signal num_picoblaze : std_logic_vector(2 downto 0);
signal picoblaze_instruction_data_width : std_logic_vector(4 downto 0);
--
signal drck : std_logic;
signal shift_clk : std_logic;
signal shift_din : std_logic;
signal shift_dout : std_logic;
signal shift : std_logic;
signal capture : std_logic;
--
signal control_reg_ce : std_logic;
signal bram_ce : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
signal bus_zero : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
signal jtag_en_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
signal jtag_en_expanded : std_logic_vector(7 downto 0) := (others => '0');
signal jtag_addr_int : std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0);
signal jtag_din_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal control_din : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0');
signal control_dout : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0');
signal control_dout_int : std_logic_vector(7 downto 0):= (others => '0');
signal bram_dout_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0');
signal jtag_we_int : std_logic;
signal jtag_clk_int : std_logic;
signal bram_ce_valid : std_logic;
signal din_load : std_logic;
--
signal jtag_dout_0_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_1_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_2_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_3_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_4_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_5_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_6_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_7_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal picoblaze_reset_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
--
begin
bus_zero <= (others => '0');
--
jtag_loader_gen: if (C_JTAG_LOADER_ENABLE = 1) generate
--
-- Insert BSCAN primitive for target device architecture.
--
BSCAN_SPARTAN6_gen: if (C_FAMILY="S6") generate
begin
BSCAN_BLOCK_inst : BSCAN_SPARTAN6
generic map ( JTAG_CHAIN => C_JTAG_CHAIN)
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_SPARTAN6_gen;
--
BSCAN_VIRTEX6_gen: if (C_FAMILY="V6") generate
begin
BSCAN_BLOCK_inst: BSCAN_VIRTEX6
generic map( JTAG_CHAIN => C_JTAG_CHAIN,
DISABLE_JTAG => FALSE)
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_VIRTEX6_gen;
--
BSCAN_7SERIES_gen: if (C_FAMILY="7S") generate
begin
BSCAN_BLOCK_inst: BSCANE2
generic map( JTAG_CHAIN => C_JTAG_CHAIN,
DISABLE_JTAG => "FALSE")
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_7SERIES_gen;
--
--
-- Insert clock buffer to ensure reliable shift operations.
--
upload_clock: BUFG
port map( I => drck,
O => shift_clk);
--
--
-- Shift Register
--
--
control_reg_ce_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk = '1' then
if (shift = '1') then
control_reg_ce <= shift_din;
end if;
end if;
end process control_reg_ce_shift;
--
bram_ce_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
if(C_NUM_PICOBLAZE > 1) then
for i in 0 to C_NUM_PICOBLAZE-2 loop
bram_ce(i+1) <= bram_ce(i);
end loop;
end if;
bram_ce(0) <= control_reg_ce;
end if;
end if;
end process bram_ce_shift;
--
bram_we_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
jtag_we_int <= bram_ce(C_NUM_PICOBLAZE-1);
end if;
end if;
end process bram_we_shift;
--
bram_a_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
for i in 0 to C_BRAM_MAX_ADDR_WIDTH-2 loop
jtag_addr_int(i+1) <= jtag_addr_int(i);
end loop;
jtag_addr_int(0) <= jtag_we_int;
end if;
end if;
end process bram_a_shift;
--
bram_d_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (din_load = '1') then
jtag_din_int <= bram_dout_int;
elsif (shift = '1') then
for i in 0 to C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-2 loop
jtag_din_int(i+1) <= jtag_din_int(i);
end loop;
jtag_din_int(0) <= jtag_addr_int(C_BRAM_MAX_ADDR_WIDTH-1);
end if;
end if;
end process bram_d_shift;
--
shift_dout <= jtag_din_int(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1);
--
--
din_load_select:process (bram_ce, din_load, capture, bus_zero, control_reg_ce)
begin
if ( bram_ce = bus_zero ) then
din_load <= capture and control_reg_ce;
else
din_load <= capture;
end if;
end process din_load_select;
--
--
-- Control Registers
--
num_picoblaze <= conv_std_logic_vector(C_NUM_PICOBLAZE-1,3);
picoblaze_instruction_data_width <= conv_std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1,5);
--
control_registers: process(jtag_clk_int)
begin
if (jtag_clk_int'event and jtag_clk_int = '1') then
if (bram_ce_valid = '1') and (jtag_we_int = '0') and (control_reg_ce = '1') then
case (jtag_addr_int(3 downto 0)) is
when "0000" => -- 0 = version - returns (7 downto 4) illustrating number of PB
-- and (3 downto 0) picoblaze instruction data width
control_dout_int <= num_picoblaze & picoblaze_instruction_data_width;
when "0001" => -- 1 = PicoBlaze 0 reset / status
if (C_NUM_PICOBLAZE >= 1) then
control_dout_int <= picoblaze_reset_int(0) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_0-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0010" => -- 2 = PicoBlaze 1 reset / status
if (C_NUM_PICOBLAZE >= 2) then
control_dout_int <= picoblaze_reset_int(1) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_1-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0011" => -- 3 = PicoBlaze 2 reset / status
if (C_NUM_PICOBLAZE >= 3) then
control_dout_int <= picoblaze_reset_int(2) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_2-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0100" => -- 4 = PicoBlaze 3 reset / status
if (C_NUM_PICOBLAZE >= 4) then
control_dout_int <= picoblaze_reset_int(3) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_3-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0101" => -- 5 = PicoBlaze 4 reset / status
if (C_NUM_PICOBLAZE >= 5) then
control_dout_int <= picoblaze_reset_int(4) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_4-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0110" => -- 6 = PicoBlaze 5 reset / status
if (C_NUM_PICOBLAZE >= 6) then
control_dout_int <= picoblaze_reset_int(5) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_5-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0111" => -- 7 = PicoBlaze 6 reset / status
if (C_NUM_PICOBLAZE >= 7) then
control_dout_int <= picoblaze_reset_int(6) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_6-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "1000" => -- 8 = PicoBlaze 7 reset / status
if (C_NUM_PICOBLAZE >= 8) then
control_dout_int <= picoblaze_reset_int(7) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_7-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "1111" => control_dout_int <= conv_std_logic_vector(C_BRAM_MAX_ADDR_WIDTH -1,8);
when others => control_dout_int <= (others => '1');
end case;
else
control_dout_int <= (others => '0');
end if;
end if;
end process control_registers;
--
control_dout(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-8) <= control_dout_int;
--
pb_reset: process(jtag_clk_int)
begin
if (jtag_clk_int'event and jtag_clk_int = '1') then
if (bram_ce_valid = '1') and (jtag_we_int = '1') and (control_reg_ce = '1') then
picoblaze_reset_int(C_NUM_PICOBLAZE-1 downto 0) <= control_din(C_NUM_PICOBLAZE-1 downto 0);
end if;
end if;
end process pb_reset;
--
--
-- Assignments
--
control_dout (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-9 downto 0) <= (others => '0') when (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH > 8);
--
-- Qualify the blockram CS signal with bscan select output
jtag_en_int <= bram_ce when bram_ce_valid = '1' else (others => '0');
--
jtag_en_expanded(C_NUM_PICOBLAZE-1 downto 0) <= jtag_en_int;
jtag_en_expanded(7 downto C_NUM_PICOBLAZE) <= (others => '0') when (C_NUM_PICOBLAZE < 8);
--
bram_dout_int <= control_dout or jtag_dout_0_masked or jtag_dout_1_masked or jtag_dout_2_masked or jtag_dout_3_masked or jtag_dout_4_masked or jtag_dout_5_masked or jtag_dout_6_masked or jtag_dout_7_masked;
--
control_din <= jtag_din_int;
--
jtag_dout_0_masked <= jtag_dout_0 when jtag_en_expanded(0) = '1' else (others => '0');
jtag_dout_1_masked <= jtag_dout_1 when jtag_en_expanded(1) = '1' else (others => '0');
jtag_dout_2_masked <= jtag_dout_2 when jtag_en_expanded(2) = '1' else (others => '0');
jtag_dout_3_masked <= jtag_dout_3 when jtag_en_expanded(3) = '1' else (others => '0');
jtag_dout_4_masked <= jtag_dout_4 when jtag_en_expanded(4) = '1' else (others => '0');
jtag_dout_5_masked <= jtag_dout_5 when jtag_en_expanded(5) = '1' else (others => '0');
jtag_dout_6_masked <= jtag_dout_6 when jtag_en_expanded(6) = '1' else (others => '0');
jtag_dout_7_masked <= jtag_dout_7 when jtag_en_expanded(7) = '1' else (others => '0');
--
jtag_en <= jtag_en_int;
jtag_din <= jtag_din_int;
jtag_addr <= jtag_addr_int;
jtag_clk <= jtag_clk_int;
jtag_we <= jtag_we_int;
picoblaze_reset <= picoblaze_reset_int;
--
end generate jtag_loader_gen;
--
end Behavioral;
--
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
ROM_form.vhd
Template for a KCPSM6 program memory. This template is primarily for use during code
development including generic parameters for the convenient selection of device family,
program memory size and the ability to include the JTAG Loader hardware for rapid
software development.
Kris Chaplin and Ken Chapman (Xilinx Ltd)
17th September 2010 - First Release
4th February 2011 - Correction to definition of 'we_b' in V6/1K/JTAG instance.
3rd March 2011 - Minor adjustments to comments only.
16th August 2011 - Additions and adjustments for support of 7-Series in ISE v13.2.
Simplification of JTAG Loader definition.
23rd November 2012 - 4K program for Spartan-6.
14th March 2013 - Unused address inputs on Virtex-6 and 7-Series BRAMs connected
High to reflect descriptions in UG363 and UG473.
This is a VHDL template file for the KCPSM6 assembler.
This VHDL file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.vhd' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Definition of a program memory for KCPSM6 including generic parameters for the
-- convenient selection of device family, program memory size and the ability to include
-- the JTAG Loader hardware for rapid software development.
--
-- This file is primarily for use during code development and it is recommended that the
-- appropriate simplified program memory definition be used in a final production design.
--
-- Generic Values Comments
-- Parameter Supported
--
-- C_FAMILY "S6" Spartan-6 device
-- "V6" Virtex-6 device
-- "7S" 7-Series device
-- (Artix-7, Kintex-7, Virtex-7 or Zynq)
--
-- C_RAM_SIZE_KWORDS 1, 2 or 4 Size of program memory in K-instructions
--
-- C_JTAG_LOADER_ENABLE 0 or 1 Set to '1' to include JTAG Loader
--
-- Notes
--
-- If your design contains MULTIPLE KCPSM6 instances then only one should have the
-- JTAG Loader enabled at a time (i.e. make sure that C_JTAG_LOADER_ENABLE is only set to
-- '1' on one instance of the program memory). Advanced users may be interested to know
-- that it is possible to connect JTAG Loader to multiple memories and then to use the
-- JTAG Loader utility to specify which memory contents are to be modified. However,
-- this scheme does require some effort to set up and the additional connectivity of the
-- multiple BRAMs can impact the placement, routing and performance of the complete
-- design. Please contact the author at Xilinx for more detailed information.
--
-- Regardless of the size of program memory specified by C_RAM_SIZE_KWORDS, the complete
-- 12-bit address bus is connected to KCPSM6. This enables the generic to be modified
-- without requiring changes to the fundamental hardware definition. However, when the
-- program memory is 1K then only the lower 10-bits of the address are actually used and
-- the valid address range is 000 to 3FF hex. Likewise, for a 2K program only the lower
-- 11-bits of the address are actually used and the valid address range is 000 to 7FF hex.
--
-- Programs are stored in Block Memory (BRAM) and the number of BRAM used depends on the
-- size of the program and the device family.
--
-- In a Spartan-6 device a BRAM is capable of holding 1K instructions. Hence a 2K program
-- will require 2 BRAMs to be used and a 4K program will require 4 BRAMs to be used. It
-- should be noted that a 4K program is not such a natural fit in a Spartan-6 device and
-- the implementation also requires a small amount of logic resulting in slightly lower
-- performance. A Spartan-6 BRAM can also be split into two 9k-bit memories suggesting
-- that a program containing up to 512 instructions could be implemented. However, there
-- is a silicon errata which makes this unsuitable and therefore it is not supported by
-- this file.
--
-- In a Virtex-6 or any 7-Series device a BRAM is capable of holding 2K instructions so
-- obviously a 2K program requires only a single BRAM. Each BRAM can also be divided into
-- 2 smaller memories supporting programs of 1K in half of a 36k-bit BRAM (generally
-- reported as being an 18k-bit BRAM). For a program of 4K instructions, 2 BRAMs are used.
--
--
-- Program defined by '{psmname}.psm'.
--
-- Generated by KCPSM6 Assembler: {timestamp}.
--
-- Assembler used ROM_form template: ROM_form_JTAGLoader_14March13.vhd
--
-- Standard IEEE libraries
--
--
package jtag_loader_pkg is
function addr_width_calc (size_in_k: integer) return integer;
end jtag_loader_pkg;
--
package body jtag_loader_pkg is
function addr_width_calc (size_in_k: integer) return integer is
begin
if (size_in_k = 1) then return 10;
elsif (size_in_k = 2) then return 11;
elsif (size_in_k = 4) then return 12;
else report "Invalid BlockRAM size. Please set to 1, 2 or 4 K words." severity FAILURE;
end if;
return 0;
end function addr_width_calc;
end package body;
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.jtag_loader_pkg.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
generic( C_FAMILY : string := "S6";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
signal address_a : std_logic_vector(15 downto 0);
signal pipe_a11 : std_logic;
signal data_in_a : std_logic_vector(35 downto 0);
signal data_out_a : std_logic_vector(35 downto 0);
signal data_out_a_l : std_logic_vector(35 downto 0);
signal data_out_a_h : std_logic_vector(35 downto 0);
signal data_out_a_ll : std_logic_vector(35 downto 0);
signal data_out_a_lh : std_logic_vector(35 downto 0);
signal data_out_a_hl : std_logic_vector(35 downto 0);
signal data_out_a_hh : std_logic_vector(35 downto 0);
signal address_b : std_logic_vector(15 downto 0);
signal data_in_b : std_logic_vector(35 downto 0);
signal data_in_b_l : std_logic_vector(35 downto 0);
signal data_in_b_ll : std_logic_vector(35 downto 0);
signal data_in_b_hl : std_logic_vector(35 downto 0);
signal data_out_b : std_logic_vector(35 downto 0);
signal data_out_b_l : std_logic_vector(35 downto 0);
signal data_out_b_ll : std_logic_vector(35 downto 0);
signal data_out_b_hl : std_logic_vector(35 downto 0);
signal data_in_b_h : std_logic_vector(35 downto 0);
signal data_in_b_lh : std_logic_vector(35 downto 0);
signal data_in_b_hh : std_logic_vector(35 downto 0);
signal data_out_b_h : std_logic_vector(35 downto 0);
signal data_out_b_lh : std_logic_vector(35 downto 0);
signal data_out_b_hh : std_logic_vector(35 downto 0);
signal enable_b : std_logic;
signal clk_b : std_logic;
signal we_b : std_logic_vector(7 downto 0);
signal we_b_l : std_logic_vector(3 downto 0);
signal we_b_h : std_logic_vector(3 downto 0);
--
signal jtag_addr : std_logic_vector(11 downto 0);
signal jtag_we : std_logic;
signal jtag_we_l : std_logic;
signal jtag_we_h : std_logic;
signal jtag_clk : std_logic;
signal jtag_din : std_logic_vector(17 downto 0);
signal jtag_dout : std_logic_vector(17 downto 0);
signal jtag_dout_1 : std_logic_vector(17 downto 0);
signal jtag_en : std_logic_vector(0 downto 0);
--
signal picoblaze_reset : std_logic_vector(0 downto 0);
signal rdl_bus : std_logic_vector(0 downto 0);
--
constant BRAM_ADDRESS_WIDTH : integer := addr_width_calc(C_RAM_SIZE_KWORDS);
--
--
component jtag_loader_6
generic( C_JTAG_LOADER_ENABLE : integer := 1;
C_FAMILY : string := "V6";
C_NUM_PICOBLAZE : integer := 1;
C_BRAM_MAX_ADDR_WIDTH : integer := 10;
C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18;
C_JTAG_CHAIN : integer := 2;
C_ADDR_WIDTH_0 : integer := 10;
C_ADDR_WIDTH_1 : integer := 10;
C_ADDR_WIDTH_2 : integer := 10;
C_ADDR_WIDTH_3 : integer := 10;
C_ADDR_WIDTH_4 : integer := 10;
C_ADDR_WIDTH_5 : integer := 10;
C_ADDR_WIDTH_6 : integer := 10;
C_ADDR_WIDTH_7 : integer := 10);
port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_din : out STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_addr : out STD_LOGIC_VECTOR(C_BRAM_MAX_ADDR_WIDTH-1 downto 0);
jtag_clk : out std_logic;
jtag_we : out std_logic;
jtag_dout_0 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_1 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_2 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_3 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_4 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_5 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_6 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_7 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0));
end component;
--
begin
--
--
ram_1k_generate : if (C_RAM_SIZE_KWORDS = 1) generate
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "0000";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "0000000000000000000000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "0000";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB16BWER
generic map ( DATA_WIDTH_A => 18,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 18,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a(31 downto 0),
DOPA => data_out_a(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b(31 downto 0),
DOPB => data_out_b(35 downto 32),
DIB => data_in_b(31 downto 0),
DIPB => data_in_b(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(17 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b(17 downto 0) <= data_out_b(17 downto 0);
address_b(13 downto 0) <= "11111111111111";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b(17 downto 0) <= jtag_din(17 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "1111";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
port map( ADDRARDADDR => address_a(13 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(13 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b(3 downto 0),
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(17 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b(17 downto 0) <= data_out_b(17 downto 0);
address_b(13 downto 0) <= "11111111111111";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b(17 downto 0) <= jtag_din(17 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "1111";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
port map( ADDRARDADDR => address_a(13 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(13 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b(3 downto 0),
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
end generate akv7;
--
end generate ram_1k_generate;
--
--
--
ram_2k_generate : if (C_RAM_SIZE_KWORDS = 2) generate
--
--
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(10 downto 0) & "000";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_l(31 downto 0),
DOPA => data_out_a_l(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_l(31 downto 0),
DOPB => data_out_b_l(35 downto 32),
DIB => data_in_b_l(31 downto 0),
DIPB => data_in_b_l(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_h: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_h(31 downto 0),
DOPA => data_out_a_h(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_h(31 downto 0),
DOPB => data_out_b_h(35 downto 32),
DIB => data_in_b_h(31 downto 0),
DIPB => data_in_b_h(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b <= '1' & jtag_addr(10 downto 0) & "1111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INIT_40 => X"{INIT_40}",
INIT_41 => X"{INIT_41}",
INIT_42 => X"{INIT_42}",
INIT_43 => X"{INIT_43}",
INIT_44 => X"{INIT_44}",
INIT_45 => X"{INIT_45}",
INIT_46 => X"{INIT_46}",
INIT_47 => X"{INIT_47}",
INIT_48 => X"{INIT_48}",
INIT_49 => X"{INIT_49}",
INIT_4A => X"{INIT_4A}",
INIT_4B => X"{INIT_4B}",
INIT_4C => X"{INIT_4C}",
INIT_4D => X"{INIT_4D}",
INIT_4E => X"{INIT_4E}",
INIT_4F => X"{INIT_4F}",
INIT_50 => X"{INIT_50}",
INIT_51 => X"{INIT_51}",
INIT_52 => X"{INIT_52}",
INIT_53 => X"{INIT_53}",
INIT_54 => X"{INIT_54}",
INIT_55 => X"{INIT_55}",
INIT_56 => X"{INIT_56}",
INIT_57 => X"{INIT_57}",
INIT_58 => X"{INIT_58}",
INIT_59 => X"{INIT_59}",
INIT_5A => X"{INIT_5A}",
INIT_5B => X"{INIT_5B}",
INIT_5C => X"{INIT_5C}",
INIT_5D => X"{INIT_5D}",
INIT_5E => X"{INIT_5E}",
INIT_5F => X"{INIT_5F}",
INIT_60 => X"{INIT_60}",
INIT_61 => X"{INIT_61}",
INIT_62 => X"{INIT_62}",
INIT_63 => X"{INIT_63}",
INIT_64 => X"{INIT_64}",
INIT_65 => X"{INIT_65}",
INIT_66 => X"{INIT_66}",
INIT_67 => X"{INIT_67}",
INIT_68 => X"{INIT_68}",
INIT_69 => X"{INIT_69}",
INIT_6A => X"{INIT_6A}",
INIT_6B => X"{INIT_6B}",
INIT_6C => X"{INIT_6C}",
INIT_6D => X"{INIT_6D}",
INIT_6E => X"{INIT_6E}",
INIT_6F => X"{INIT_6F}",
INIT_70 => X"{INIT_70}",
INIT_71 => X"{INIT_71}",
INIT_72 => X"{INIT_72}",
INIT_73 => X"{INIT_73}",
INIT_74 => X"{INIT_74}",
INIT_75 => X"{INIT_75}",
INIT_76 => X"{INIT_76}",
INIT_77 => X"{INIT_77}",
INIT_78 => X"{INIT_78}",
INIT_79 => X"{INIT_79}",
INIT_7A => X"{INIT_7A}",
INIT_7B => X"{INIT_7B}",
INIT_7C => X"{INIT_7C}",
INIT_7D => X"{INIT_7D}",
INIT_7E => X"{INIT_7E}",
INIT_7F => X"{INIT_7F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}",
INITP_08 => X"{INITP_08}",
INITP_09 => X"{INITP_09}",
INITP_0A => X"{INITP_0A}",
INITP_0B => X"{INITP_0B}",
INITP_0C => X"{INITP_0C}",
INITP_0D => X"{INITP_0D}",
INITP_0E => X"{INITP_0E}",
INITP_0F => X"{INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b <= '1' & jtag_addr(10 downto 0) & "1111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INIT_40 => X"{INIT_40}",
INIT_41 => X"{INIT_41}",
INIT_42 => X"{INIT_42}",
INIT_43 => X"{INIT_43}",
INIT_44 => X"{INIT_44}",
INIT_45 => X"{INIT_45}",
INIT_46 => X"{INIT_46}",
INIT_47 => X"{INIT_47}",
INIT_48 => X"{INIT_48}",
INIT_49 => X"{INIT_49}",
INIT_4A => X"{INIT_4A}",
INIT_4B => X"{INIT_4B}",
INIT_4C => X"{INIT_4C}",
INIT_4D => X"{INIT_4D}",
INIT_4E => X"{INIT_4E}",
INIT_4F => X"{INIT_4F}",
INIT_50 => X"{INIT_50}",
INIT_51 => X"{INIT_51}",
INIT_52 => X"{INIT_52}",
INIT_53 => X"{INIT_53}",
INIT_54 => X"{INIT_54}",
INIT_55 => X"{INIT_55}",
INIT_56 => X"{INIT_56}",
INIT_57 => X"{INIT_57}",
INIT_58 => X"{INIT_58}",
INIT_59 => X"{INIT_59}",
INIT_5A => X"{INIT_5A}",
INIT_5B => X"{INIT_5B}",
INIT_5C => X"{INIT_5C}",
INIT_5D => X"{INIT_5D}",
INIT_5E => X"{INIT_5E}",
INIT_5F => X"{INIT_5F}",
INIT_60 => X"{INIT_60}",
INIT_61 => X"{INIT_61}",
INIT_62 => X"{INIT_62}",
INIT_63 => X"{INIT_63}",
INIT_64 => X"{INIT_64}",
INIT_65 => X"{INIT_65}",
INIT_66 => X"{INIT_66}",
INIT_67 => X"{INIT_67}",
INIT_68 => X"{INIT_68}",
INIT_69 => X"{INIT_69}",
INIT_6A => X"{INIT_6A}",
INIT_6B => X"{INIT_6B}",
INIT_6C => X"{INIT_6C}",
INIT_6D => X"{INIT_6D}",
INIT_6E => X"{INIT_6E}",
INIT_6F => X"{INIT_6F}",
INIT_70 => X"{INIT_70}",
INIT_71 => X"{INIT_71}",
INIT_72 => X"{INIT_72}",
INIT_73 => X"{INIT_73}",
INIT_74 => X"{INIT_74}",
INIT_75 => X"{INIT_75}",
INIT_76 => X"{INIT_76}",
INIT_77 => X"{INIT_77}",
INIT_78 => X"{INIT_78}",
INIT_79 => X"{INIT_79}",
INIT_7A => X"{INIT_7A}",
INIT_7B => X"{INIT_7B}",
INIT_7C => X"{INIT_7C}",
INIT_7D => X"{INIT_7D}",
INIT_7E => X"{INIT_7E}",
INIT_7F => X"{INIT_7F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}",
INITP_08 => X"{INITP_08}",
INITP_09 => X"{INITP_09}",
INITP_0A => X"{INITP_0A}",
INITP_0B => X"{INITP_0B}",
INITP_0C => X"{INITP_0C}",
INITP_0D => X"{INITP_0D}",
INITP_0E => X"{INITP_0E}",
INITP_0F => X"{INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate akv7;
--
end generate ram_2k_generate;
--
--
ram_4k_generate : if (C_RAM_SIZE_KWORDS = 4) generate
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(10 downto 0) & "000";
data_in_a <= "000000000000000000000000000000000000";
--
s6_a11_flop: FD
port map ( D => address(11),
Q => pipe_a11,
C => clk);
--
s6_4k_mux0_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(0),
I1 => data_out_a_hl(0),
I2 => data_out_a_ll(1),
I3 => data_out_a_hl(1),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(0),
O6 => instruction(1));
--
s6_4k_mux2_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(2),
I1 => data_out_a_hl(2),
I2 => data_out_a_ll(3),
I3 => data_out_a_hl(3),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(2),
O6 => instruction(3));
--
s6_4k_mux4_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(4),
I1 => data_out_a_hl(4),
I2 => data_out_a_ll(5),
I3 => data_out_a_hl(5),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(4),
O6 => instruction(5));
--
s6_4k_mux6_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(6),
I1 => data_out_a_hl(6),
I2 => data_out_a_ll(7),
I3 => data_out_a_hl(7),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(6),
O6 => instruction(7));
--
s6_4k_mux8_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(32),
I1 => data_out_a_hl(32),
I2 => data_out_a_lh(0),
I3 => data_out_a_hh(0),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(8),
O6 => instruction(9));
--
s6_4k_mux10_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(1),
I1 => data_out_a_hh(1),
I2 => data_out_a_lh(2),
I3 => data_out_a_hh(2),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(10),
O6 => instruction(11));
--
s6_4k_mux12_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(3),
I1 => data_out_a_hh(3),
I2 => data_out_a_lh(4),
I3 => data_out_a_hh(4),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(12),
O6 => instruction(13));
--
s6_4k_mux14_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(5),
I1 => data_out_a_hh(5),
I2 => data_out_a_lh(6),
I3 => data_out_a_hh(6),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(14),
O6 => instruction(15));
--
s6_4k_mux16_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(7),
I1 => data_out_a_hh(7),
I2 => data_out_a_lh(32),
I3 => data_out_a_hh(32),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(16),
O6 => instruction(17));
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_ll <= "000" & data_out_b_ll(32) & "000000000000000000000000" & data_out_b_ll(7 downto 0);
data_in_b_lh <= "000" & data_out_b_lh(32) & "000000000000000000000000" & data_out_b_lh(7 downto 0);
data_in_b_hl <= "000" & data_out_b_hl(32) & "000000000000000000000000" & data_out_b_hl(7 downto 0);
data_in_b_hh <= "000" & data_out_b_hh(32) & "000000000000000000000000" & data_out_b_hh(7 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b_l(3 downto 0) <= "0000";
we_b_h(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
jtag_dout <= data_out_b_lh(32) & data_out_b_lh(7 downto 0) & data_out_b_ll(32) & data_out_b_ll(7 downto 0);
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_lh <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_ll <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
data_in_b_hh <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_hl <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000";
--
s6_4k_jtag_we_lut: LUT6_2
generic map (INIT => X"8000000020000000")
port map( I0 => jtag_we,
I1 => jtag_addr(11),
I2 => '1',
I3 => '1',
I4 => '1',
I5 => '1',
O5 => jtag_we_l,
O6 => jtag_we_h);
--
we_b_l(3 downto 0) <= jtag_we_l & jtag_we_l & jtag_we_l & jtag_we_l;
we_b_h(3 downto 0) <= jtag_we_h & jtag_we_h & jtag_we_h & jtag_we_h;
--
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
--
s6_4k_jtag_mux0_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(0),
I1 => data_out_b_hl(0),
I2 => data_out_b_ll(1),
I3 => data_out_b_hl(1),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(0),
O6 => jtag_dout(1));
--
s6_4k_jtag_mux2_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(2),
I1 => data_out_b_hl(2),
I2 => data_out_b_ll(3),
I3 => data_out_b_hl(3),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(2),
O6 => jtag_dout(3));
--
s6_4k_jtag_mux4_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(4),
I1 => data_out_b_hl(4),
I2 => data_out_b_ll(5),
I3 => data_out_b_hl(5),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(4),
O6 => jtag_dout(5));
--
s6_4k_jtag_mux6_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(6),
I1 => data_out_b_hl(6),
I2 => data_out_b_ll(7),
I3 => data_out_b_hl(7),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(6),
O6 => jtag_dout(7));
--
s6_4k_jtag_mux8_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(32),
I1 => data_out_b_hl(32),
I2 => data_out_b_lh(0),
I3 => data_out_b_hh(0),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(8),
O6 => jtag_dout(9));
--
s6_4k_jtag_mux10_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(1),
I1 => data_out_b_hh(1),
I2 => data_out_b_lh(2),
I3 => data_out_b_hh(2),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(10),
O6 => jtag_dout(11));
--
s6_4k_jtag_mux12_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(3),
I1 => data_out_b_hh(3),
I2 => data_out_b_lh(4),
I3 => data_out_b_hh(4),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(12),
O6 => jtag_dout(13));
--
s6_4k_jtag_mux14_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(5),
I1 => data_out_b_hh(5),
I2 => data_out_b_lh(6),
I3 => data_out_b_hh(6),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(14),
O6 => jtag_dout(15));
--
s6_4k_jtag_mux16_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(7),
I1 => data_out_b_hh(7),
I2 => data_out_b_lh(32),
I3 => data_out_b_hh(32),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(16),
O6 => jtag_dout(17));
--
end generate loader;
--
kcpsm6_rom_ll: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_ll(31 downto 0),
DOPA => data_out_a_ll(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_ll(31 downto 0),
DOPB => data_out_b_ll(35 downto 32),
DIB => data_in_b_ll(31 downto 0),
DIPB => data_in_b_ll(35 downto 32),
WEB => we_b_l(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_lh: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_lh(31 downto 0),
DOPA => data_out_a_lh(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_lh(31 downto 0),
DOPB => data_out_b_lh(35 downto 32),
DIB => data_in_b_lh(31 downto 0),
DIPB => data_in_b_lh(35 downto 32),
WEB => we_b_l(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_hl: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[8:0]_INIT_40}",
INIT_01 => X"{[8:0]_INIT_41}",
INIT_02 => X"{[8:0]_INIT_42}",
INIT_03 => X"{[8:0]_INIT_43}",
INIT_04 => X"{[8:0]_INIT_44}",
INIT_05 => X"{[8:0]_INIT_45}",
INIT_06 => X"{[8:0]_INIT_46}",
INIT_07 => X"{[8:0]_INIT_47}",
INIT_08 => X"{[8:0]_INIT_48}",
INIT_09 => X"{[8:0]_INIT_49}",
INIT_0A => X"{[8:0]_INIT_4A}",
INIT_0B => X"{[8:0]_INIT_4B}",
INIT_0C => X"{[8:0]_INIT_4C}",
INIT_0D => X"{[8:0]_INIT_4D}",
INIT_0E => X"{[8:0]_INIT_4E}",
INIT_0F => X"{[8:0]_INIT_4F}",
INIT_10 => X"{[8:0]_INIT_50}",
INIT_11 => X"{[8:0]_INIT_51}",
INIT_12 => X"{[8:0]_INIT_52}",
INIT_13 => X"{[8:0]_INIT_53}",
INIT_14 => X"{[8:0]_INIT_54}",
INIT_15 => X"{[8:0]_INIT_55}",
INIT_16 => X"{[8:0]_INIT_56}",
INIT_17 => X"{[8:0]_INIT_57}",
INIT_18 => X"{[8:0]_INIT_58}",
INIT_19 => X"{[8:0]_INIT_59}",
INIT_1A => X"{[8:0]_INIT_5A}",
INIT_1B => X"{[8:0]_INIT_5B}",
INIT_1C => X"{[8:0]_INIT_5C}",
INIT_1D => X"{[8:0]_INIT_5D}",
INIT_1E => X"{[8:0]_INIT_5E}",
INIT_1F => X"{[8:0]_INIT_5F}",
INIT_20 => X"{[8:0]_INIT_60}",
INIT_21 => X"{[8:0]_INIT_61}",
INIT_22 => X"{[8:0]_INIT_62}",
INIT_23 => X"{[8:0]_INIT_63}",
INIT_24 => X"{[8:0]_INIT_64}",
INIT_25 => X"{[8:0]_INIT_65}",
INIT_26 => X"{[8:0]_INIT_66}",
INIT_27 => X"{[8:0]_INIT_67}",
INIT_28 => X"{[8:0]_INIT_68}",
INIT_29 => X"{[8:0]_INIT_69}",
INIT_2A => X"{[8:0]_INIT_6A}",
INIT_2B => X"{[8:0]_INIT_6B}",
INIT_2C => X"{[8:0]_INIT_6C}",
INIT_2D => X"{[8:0]_INIT_6D}",
INIT_2E => X"{[8:0]_INIT_6E}",
INIT_2F => X"{[8:0]_INIT_6F}",
INIT_30 => X"{[8:0]_INIT_70}",
INIT_31 => X"{[8:0]_INIT_71}",
INIT_32 => X"{[8:0]_INIT_72}",
INIT_33 => X"{[8:0]_INIT_73}",
INIT_34 => X"{[8:0]_INIT_74}",
INIT_35 => X"{[8:0]_INIT_75}",
INIT_36 => X"{[8:0]_INIT_76}",
INIT_37 => X"{[8:0]_INIT_77}",
INIT_38 => X"{[8:0]_INIT_78}",
INIT_39 => X"{[8:0]_INIT_79}",
INIT_3A => X"{[8:0]_INIT_7A}",
INIT_3B => X"{[8:0]_INIT_7B}",
INIT_3C => X"{[8:0]_INIT_7C}",
INIT_3D => X"{[8:0]_INIT_7D}",
INIT_3E => X"{[8:0]_INIT_7E}",
INIT_3F => X"{[8:0]_INIT_7F}",
INITP_00 => X"{[8:0]_INITP_08}",
INITP_01 => X"{[8:0]_INITP_09}",
INITP_02 => X"{[8:0]_INITP_0A}",
INITP_03 => X"{[8:0]_INITP_0B}",
INITP_04 => X"{[8:0]_INITP_0C}",
INITP_05 => X"{[8:0]_INITP_0D}",
INITP_06 => X"{[8:0]_INITP_0E}",
INITP_07 => X"{[8:0]_INITP_0F}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_hl(31 downto 0),
DOPA => data_out_a_hl(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_hl(31 downto 0),
DOPB => data_out_b_hl(35 downto 32),
DIB => data_in_b_hl(31 downto 0),
DIPB => data_in_b_hl(35 downto 32),
WEB => we_b_h(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_hh: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[17:9]_INIT_40}",
INIT_01 => X"{[17:9]_INIT_41}",
INIT_02 => X"{[17:9]_INIT_42}",
INIT_03 => X"{[17:9]_INIT_43}",
INIT_04 => X"{[17:9]_INIT_44}",
INIT_05 => X"{[17:9]_INIT_45}",
INIT_06 => X"{[17:9]_INIT_46}",
INIT_07 => X"{[17:9]_INIT_47}",
INIT_08 => X"{[17:9]_INIT_48}",
INIT_09 => X"{[17:9]_INIT_49}",
INIT_0A => X"{[17:9]_INIT_4A}",
INIT_0B => X"{[17:9]_INIT_4B}",
INIT_0C => X"{[17:9]_INIT_4C}",
INIT_0D => X"{[17:9]_INIT_4D}",
INIT_0E => X"{[17:9]_INIT_4E}",
INIT_0F => X"{[17:9]_INIT_4F}",
INIT_10 => X"{[17:9]_INIT_50}",
INIT_11 => X"{[17:9]_INIT_51}",
INIT_12 => X"{[17:9]_INIT_52}",
INIT_13 => X"{[17:9]_INIT_53}",
INIT_14 => X"{[17:9]_INIT_54}",
INIT_15 => X"{[17:9]_INIT_55}",
INIT_16 => X"{[17:9]_INIT_56}",
INIT_17 => X"{[17:9]_INIT_57}",
INIT_18 => X"{[17:9]_INIT_58}",
INIT_19 => X"{[17:9]_INIT_59}",
INIT_1A => X"{[17:9]_INIT_5A}",
INIT_1B => X"{[17:9]_INIT_5B}",
INIT_1C => X"{[17:9]_INIT_5C}",
INIT_1D => X"{[17:9]_INIT_5D}",
INIT_1E => X"{[17:9]_INIT_5E}",
INIT_1F => X"{[17:9]_INIT_5F}",
INIT_20 => X"{[17:9]_INIT_60}",
INIT_21 => X"{[17:9]_INIT_61}",
INIT_22 => X"{[17:9]_INIT_62}",
INIT_23 => X"{[17:9]_INIT_63}",
INIT_24 => X"{[17:9]_INIT_64}",
INIT_25 => X"{[17:9]_INIT_65}",
INIT_26 => X"{[17:9]_INIT_66}",
INIT_27 => X"{[17:9]_INIT_67}",
INIT_28 => X"{[17:9]_INIT_68}",
INIT_29 => X"{[17:9]_INIT_69}",
INIT_2A => X"{[17:9]_INIT_6A}",
INIT_2B => X"{[17:9]_INIT_6B}",
INIT_2C => X"{[17:9]_INIT_6C}",
INIT_2D => X"{[17:9]_INIT_6D}",
INIT_2E => X"{[17:9]_INIT_6E}",
INIT_2F => X"{[17:9]_INIT_6F}",
INIT_30 => X"{[17:9]_INIT_70}",
INIT_31 => X"{[17:9]_INIT_71}",
INIT_32 => X"{[17:9]_INIT_72}",
INIT_33 => X"{[17:9]_INIT_73}",
INIT_34 => X"{[17:9]_INIT_74}",
INIT_35 => X"{[17:9]_INIT_75}",
INIT_36 => X"{[17:9]_INIT_76}",
INIT_37 => X"{[17:9]_INIT_77}",
INIT_38 => X"{[17:9]_INIT_78}",
INIT_39 => X"{[17:9]_INIT_79}",
INIT_3A => X"{[17:9]_INIT_7A}",
INIT_3B => X"{[17:9]_INIT_7B}",
INIT_3C => X"{[17:9]_INIT_7C}",
INIT_3D => X"{[17:9]_INIT_7D}",
INIT_3E => X"{[17:9]_INIT_7E}",
INIT_3F => X"{[17:9]_INIT_7F}",
INITP_00 => X"{[17:9]_INITP_08}",
INITP_01 => X"{[17:9]_INITP_09}",
INITP_02 => X"{[17:9]_INITP_0A}",
INITP_03 => X"{[17:9]_INITP_0B}",
INITP_04 => X"{[17:9]_INITP_0C}",
INITP_05 => X"{[17:9]_INITP_0D}",
INITP_06 => X"{[17:9]_INITP_0E}",
INITP_07 => X"{[17:9]_INITP_0F}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_hh(31 downto 0),
DOPA => data_out_a_hh(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_hh(31 downto 0),
DOPB => data_out_b_hh(35 downto 32),
DIB => data_in_b_hh(31 downto 0),
DIPB => data_in_b_hh(35 downto 32),
WEB => we_b_h(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a <= '1' & address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b <= '1' & jtag_addr(11 downto 0) & "111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INIT_40 => X"{[8:0]_INIT_40}",
INIT_41 => X"{[8:0]_INIT_41}",
INIT_42 => X"{[8:0]_INIT_42}",
INIT_43 => X"{[8:0]_INIT_43}",
INIT_44 => X"{[8:0]_INIT_44}",
INIT_45 => X"{[8:0]_INIT_45}",
INIT_46 => X"{[8:0]_INIT_46}",
INIT_47 => X"{[8:0]_INIT_47}",
INIT_48 => X"{[8:0]_INIT_48}",
INIT_49 => X"{[8:0]_INIT_49}",
INIT_4A => X"{[8:0]_INIT_4A}",
INIT_4B => X"{[8:0]_INIT_4B}",
INIT_4C => X"{[8:0]_INIT_4C}",
INIT_4D => X"{[8:0]_INIT_4D}",
INIT_4E => X"{[8:0]_INIT_4E}",
INIT_4F => X"{[8:0]_INIT_4F}",
INIT_50 => X"{[8:0]_INIT_50}",
INIT_51 => X"{[8:0]_INIT_51}",
INIT_52 => X"{[8:0]_INIT_52}",
INIT_53 => X"{[8:0]_INIT_53}",
INIT_54 => X"{[8:0]_INIT_54}",
INIT_55 => X"{[8:0]_INIT_55}",
INIT_56 => X"{[8:0]_INIT_56}",
INIT_57 => X"{[8:0]_INIT_57}",
INIT_58 => X"{[8:0]_INIT_58}",
INIT_59 => X"{[8:0]_INIT_59}",
INIT_5A => X"{[8:0]_INIT_5A}",
INIT_5B => X"{[8:0]_INIT_5B}",
INIT_5C => X"{[8:0]_INIT_5C}",
INIT_5D => X"{[8:0]_INIT_5D}",
INIT_5E => X"{[8:0]_INIT_5E}",
INIT_5F => X"{[8:0]_INIT_5F}",
INIT_60 => X"{[8:0]_INIT_60}",
INIT_61 => X"{[8:0]_INIT_61}",
INIT_62 => X"{[8:0]_INIT_62}",
INIT_63 => X"{[8:0]_INIT_63}",
INIT_64 => X"{[8:0]_INIT_64}",
INIT_65 => X"{[8:0]_INIT_65}",
INIT_66 => X"{[8:0]_INIT_66}",
INIT_67 => X"{[8:0]_INIT_67}",
INIT_68 => X"{[8:0]_INIT_68}",
INIT_69 => X"{[8:0]_INIT_69}",
INIT_6A => X"{[8:0]_INIT_6A}",
INIT_6B => X"{[8:0]_INIT_6B}",
INIT_6C => X"{[8:0]_INIT_6C}",
INIT_6D => X"{[8:0]_INIT_6D}",
INIT_6E => X"{[8:0]_INIT_6E}",
INIT_6F => X"{[8:0]_INIT_6F}",
INIT_70 => X"{[8:0]_INIT_70}",
INIT_71 => X"{[8:0]_INIT_71}",
INIT_72 => X"{[8:0]_INIT_72}",
INIT_73 => X"{[8:0]_INIT_73}",
INIT_74 => X"{[8:0]_INIT_74}",
INIT_75 => X"{[8:0]_INIT_75}",
INIT_76 => X"{[8:0]_INIT_76}",
INIT_77 => X"{[8:0]_INIT_77}",
INIT_78 => X"{[8:0]_INIT_78}",
INIT_79 => X"{[8:0]_INIT_79}",
INIT_7A => X"{[8:0]_INIT_7A}",
INIT_7B => X"{[8:0]_INIT_7B}",
INIT_7C => X"{[8:0]_INIT_7C}",
INIT_7D => X"{[8:0]_INIT_7D}",
INIT_7E => X"{[8:0]_INIT_7E}",
INIT_7F => X"{[8:0]_INIT_7F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}",
INITP_08 => X"{[8:0]_INITP_08}",
INITP_09 => X"{[8:0]_INITP_09}",
INITP_0A => X"{[8:0]_INITP_0A}",
INITP_0B => X"{[8:0]_INITP_0B}",
INITP_0C => X"{[8:0]_INITP_0C}",
INITP_0D => X"{[8:0]_INITP_0D}",
INITP_0E => X"{[8:0]_INITP_0E}",
INITP_0F => X"{[8:0]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
kcpsm6_rom_h: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INIT_40 => X"{[17:9]_INIT_40}",
INIT_41 => X"{[17:9]_INIT_41}",
INIT_42 => X"{[17:9]_INIT_42}",
INIT_43 => X"{[17:9]_INIT_43}",
INIT_44 => X"{[17:9]_INIT_44}",
INIT_45 => X"{[17:9]_INIT_45}",
INIT_46 => X"{[17:9]_INIT_46}",
INIT_47 => X"{[17:9]_INIT_47}",
INIT_48 => X"{[17:9]_INIT_48}",
INIT_49 => X"{[17:9]_INIT_49}",
INIT_4A => X"{[17:9]_INIT_4A}",
INIT_4B => X"{[17:9]_INIT_4B}",
INIT_4C => X"{[17:9]_INIT_4C}",
INIT_4D => X"{[17:9]_INIT_4D}",
INIT_4E => X"{[17:9]_INIT_4E}",
INIT_4F => X"{[17:9]_INIT_4F}",
INIT_50 => X"{[17:9]_INIT_50}",
INIT_51 => X"{[17:9]_INIT_51}",
INIT_52 => X"{[17:9]_INIT_52}",
INIT_53 => X"{[17:9]_INIT_53}",
INIT_54 => X"{[17:9]_INIT_54}",
INIT_55 => X"{[17:9]_INIT_55}",
INIT_56 => X"{[17:9]_INIT_56}",
INIT_57 => X"{[17:9]_INIT_57}",
INIT_58 => X"{[17:9]_INIT_58}",
INIT_59 => X"{[17:9]_INIT_59}",
INIT_5A => X"{[17:9]_INIT_5A}",
INIT_5B => X"{[17:9]_INIT_5B}",
INIT_5C => X"{[17:9]_INIT_5C}",
INIT_5D => X"{[17:9]_INIT_5D}",
INIT_5E => X"{[17:9]_INIT_5E}",
INIT_5F => X"{[17:9]_INIT_5F}",
INIT_60 => X"{[17:9]_INIT_60}",
INIT_61 => X"{[17:9]_INIT_61}",
INIT_62 => X"{[17:9]_INIT_62}",
INIT_63 => X"{[17:9]_INIT_63}",
INIT_64 => X"{[17:9]_INIT_64}",
INIT_65 => X"{[17:9]_INIT_65}",
INIT_66 => X"{[17:9]_INIT_66}",
INIT_67 => X"{[17:9]_INIT_67}",
INIT_68 => X"{[17:9]_INIT_68}",
INIT_69 => X"{[17:9]_INIT_69}",
INIT_6A => X"{[17:9]_INIT_6A}",
INIT_6B => X"{[17:9]_INIT_6B}",
INIT_6C => X"{[17:9]_INIT_6C}",
INIT_6D => X"{[17:9]_INIT_6D}",
INIT_6E => X"{[17:9]_INIT_6E}",
INIT_6F => X"{[17:9]_INIT_6F}",
INIT_70 => X"{[17:9]_INIT_70}",
INIT_71 => X"{[17:9]_INIT_71}",
INIT_72 => X"{[17:9]_INIT_72}",
INIT_73 => X"{[17:9]_INIT_73}",
INIT_74 => X"{[17:9]_INIT_74}",
INIT_75 => X"{[17:9]_INIT_75}",
INIT_76 => X"{[17:9]_INIT_76}",
INIT_77 => X"{[17:9]_INIT_77}",
INIT_78 => X"{[17:9]_INIT_78}",
INIT_79 => X"{[17:9]_INIT_79}",
INIT_7A => X"{[17:9]_INIT_7A}",
INIT_7B => X"{[17:9]_INIT_7B}",
INIT_7C => X"{[17:9]_INIT_7C}",
INIT_7D => X"{[17:9]_INIT_7D}",
INIT_7E => X"{[17:9]_INIT_7E}",
INIT_7F => X"{[17:9]_INIT_7F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}",
INITP_08 => X"{[17:9]_INITP_08}",
INITP_09 => X"{[17:9]_INITP_09}",
INITP_0A => X"{[17:9]_INITP_0A}",
INITP_0B => X"{[17:9]_INITP_0B}",
INITP_0C => X"{[17:9]_INITP_0C}",
INITP_0D => X"{[17:9]_INITP_0D}",
INITP_0E => X"{[17:9]_INITP_0E}",
INITP_0F => X"{[17:9]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a <= '1' & address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b <= '1' & jtag_addr(11 downto 0) & "111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INIT_40 => X"{[8:0]_INIT_40}",
INIT_41 => X"{[8:0]_INIT_41}",
INIT_42 => X"{[8:0]_INIT_42}",
INIT_43 => X"{[8:0]_INIT_43}",
INIT_44 => X"{[8:0]_INIT_44}",
INIT_45 => X"{[8:0]_INIT_45}",
INIT_46 => X"{[8:0]_INIT_46}",
INIT_47 => X"{[8:0]_INIT_47}",
INIT_48 => X"{[8:0]_INIT_48}",
INIT_49 => X"{[8:0]_INIT_49}",
INIT_4A => X"{[8:0]_INIT_4A}",
INIT_4B => X"{[8:0]_INIT_4B}",
INIT_4C => X"{[8:0]_INIT_4C}",
INIT_4D => X"{[8:0]_INIT_4D}",
INIT_4E => X"{[8:0]_INIT_4E}",
INIT_4F => X"{[8:0]_INIT_4F}",
INIT_50 => X"{[8:0]_INIT_50}",
INIT_51 => X"{[8:0]_INIT_51}",
INIT_52 => X"{[8:0]_INIT_52}",
INIT_53 => X"{[8:0]_INIT_53}",
INIT_54 => X"{[8:0]_INIT_54}",
INIT_55 => X"{[8:0]_INIT_55}",
INIT_56 => X"{[8:0]_INIT_56}",
INIT_57 => X"{[8:0]_INIT_57}",
INIT_58 => X"{[8:0]_INIT_58}",
INIT_59 => X"{[8:0]_INIT_59}",
INIT_5A => X"{[8:0]_INIT_5A}",
INIT_5B => X"{[8:0]_INIT_5B}",
INIT_5C => X"{[8:0]_INIT_5C}",
INIT_5D => X"{[8:0]_INIT_5D}",
INIT_5E => X"{[8:0]_INIT_5E}",
INIT_5F => X"{[8:0]_INIT_5F}",
INIT_60 => X"{[8:0]_INIT_60}",
INIT_61 => X"{[8:0]_INIT_61}",
INIT_62 => X"{[8:0]_INIT_62}",
INIT_63 => X"{[8:0]_INIT_63}",
INIT_64 => X"{[8:0]_INIT_64}",
INIT_65 => X"{[8:0]_INIT_65}",
INIT_66 => X"{[8:0]_INIT_66}",
INIT_67 => X"{[8:0]_INIT_67}",
INIT_68 => X"{[8:0]_INIT_68}",
INIT_69 => X"{[8:0]_INIT_69}",
INIT_6A => X"{[8:0]_INIT_6A}",
INIT_6B => X"{[8:0]_INIT_6B}",
INIT_6C => X"{[8:0]_INIT_6C}",
INIT_6D => X"{[8:0]_INIT_6D}",
INIT_6E => X"{[8:0]_INIT_6E}",
INIT_6F => X"{[8:0]_INIT_6F}",
INIT_70 => X"{[8:0]_INIT_70}",
INIT_71 => X"{[8:0]_INIT_71}",
INIT_72 => X"{[8:0]_INIT_72}",
INIT_73 => X"{[8:0]_INIT_73}",
INIT_74 => X"{[8:0]_INIT_74}",
INIT_75 => X"{[8:0]_INIT_75}",
INIT_76 => X"{[8:0]_INIT_76}",
INIT_77 => X"{[8:0]_INIT_77}",
INIT_78 => X"{[8:0]_INIT_78}",
INIT_79 => X"{[8:0]_INIT_79}",
INIT_7A => X"{[8:0]_INIT_7A}",
INIT_7B => X"{[8:0]_INIT_7B}",
INIT_7C => X"{[8:0]_INIT_7C}",
INIT_7D => X"{[8:0]_INIT_7D}",
INIT_7E => X"{[8:0]_INIT_7E}",
INIT_7F => X"{[8:0]_INIT_7F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}",
INITP_08 => X"{[8:0]_INITP_08}",
INITP_09 => X"{[8:0]_INITP_09}",
INITP_0A => X"{[8:0]_INITP_0A}",
INITP_0B => X"{[8:0]_INITP_0B}",
INITP_0C => X"{[8:0]_INITP_0C}",
INITP_0D => X"{[8:0]_INITP_0D}",
INITP_0E => X"{[8:0]_INITP_0E}",
INITP_0F => X"{[8:0]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
kcpsm6_rom_h: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INIT_40 => X"{[17:9]_INIT_40}",
INIT_41 => X"{[17:9]_INIT_41}",
INIT_42 => X"{[17:9]_INIT_42}",
INIT_43 => X"{[17:9]_INIT_43}",
INIT_44 => X"{[17:9]_INIT_44}",
INIT_45 => X"{[17:9]_INIT_45}",
INIT_46 => X"{[17:9]_INIT_46}",
INIT_47 => X"{[17:9]_INIT_47}",
INIT_48 => X"{[17:9]_INIT_48}",
INIT_49 => X"{[17:9]_INIT_49}",
INIT_4A => X"{[17:9]_INIT_4A}",
INIT_4B => X"{[17:9]_INIT_4B}",
INIT_4C => X"{[17:9]_INIT_4C}",
INIT_4D => X"{[17:9]_INIT_4D}",
INIT_4E => X"{[17:9]_INIT_4E}",
INIT_4F => X"{[17:9]_INIT_4F}",
INIT_50 => X"{[17:9]_INIT_50}",
INIT_51 => X"{[17:9]_INIT_51}",
INIT_52 => X"{[17:9]_INIT_52}",
INIT_53 => X"{[17:9]_INIT_53}",
INIT_54 => X"{[17:9]_INIT_54}",
INIT_55 => X"{[17:9]_INIT_55}",
INIT_56 => X"{[17:9]_INIT_56}",
INIT_57 => X"{[17:9]_INIT_57}",
INIT_58 => X"{[17:9]_INIT_58}",
INIT_59 => X"{[17:9]_INIT_59}",
INIT_5A => X"{[17:9]_INIT_5A}",
INIT_5B => X"{[17:9]_INIT_5B}",
INIT_5C => X"{[17:9]_INIT_5C}",
INIT_5D => X"{[17:9]_INIT_5D}",
INIT_5E => X"{[17:9]_INIT_5E}",
INIT_5F => X"{[17:9]_INIT_5F}",
INIT_60 => X"{[17:9]_INIT_60}",
INIT_61 => X"{[17:9]_INIT_61}",
INIT_62 => X"{[17:9]_INIT_62}",
INIT_63 => X"{[17:9]_INIT_63}",
INIT_64 => X"{[17:9]_INIT_64}",
INIT_65 => X"{[17:9]_INIT_65}",
INIT_66 => X"{[17:9]_INIT_66}",
INIT_67 => X"{[17:9]_INIT_67}",
INIT_68 => X"{[17:9]_INIT_68}",
INIT_69 => X"{[17:9]_INIT_69}",
INIT_6A => X"{[17:9]_INIT_6A}",
INIT_6B => X"{[17:9]_INIT_6B}",
INIT_6C => X"{[17:9]_INIT_6C}",
INIT_6D => X"{[17:9]_INIT_6D}",
INIT_6E => X"{[17:9]_INIT_6E}",
INIT_6F => X"{[17:9]_INIT_6F}",
INIT_70 => X"{[17:9]_INIT_70}",
INIT_71 => X"{[17:9]_INIT_71}",
INIT_72 => X"{[17:9]_INIT_72}",
INIT_73 => X"{[17:9]_INIT_73}",
INIT_74 => X"{[17:9]_INIT_74}",
INIT_75 => X"{[17:9]_INIT_75}",
INIT_76 => X"{[17:9]_INIT_76}",
INIT_77 => X"{[17:9]_INIT_77}",
INIT_78 => X"{[17:9]_INIT_78}",
INIT_79 => X"{[17:9]_INIT_79}",
INIT_7A => X"{[17:9]_INIT_7A}",
INIT_7B => X"{[17:9]_INIT_7B}",
INIT_7C => X"{[17:9]_INIT_7C}",
INIT_7D => X"{[17:9]_INIT_7D}",
INIT_7E => X"{[17:9]_INIT_7E}",
INIT_7F => X"{[17:9]_INIT_7F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}",
INITP_08 => X"{[17:9]_INITP_08}",
INITP_09 => X"{[17:9]_INITP_09}",
INITP_0A => X"{[17:9]_INITP_0A}",
INITP_0B => X"{[17:9]_INITP_0B}",
INITP_0C => X"{[17:9]_INITP_0C}",
INITP_0D => X"{[17:9]_INITP_0D}",
INITP_0E => X"{[17:9]_INITP_0E}",
INITP_0F => X"{[17:9]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate akv7;
--
end generate ram_4k_generate;
--
--
--
--
-- JTAG Loader
--
instantiate_loader : if (C_JTAG_LOADER_ENABLE = 1) generate
--
jtag_loader_6_inst : jtag_loader_6
generic map( C_FAMILY => C_FAMILY,
C_NUM_PICOBLAZE => 1,
C_JTAG_LOADER_ENABLE => C_JTAG_LOADER_ENABLE,
C_BRAM_MAX_ADDR_WIDTH => BRAM_ADDRESS_WIDTH,
C_ADDR_WIDTH_0 => BRAM_ADDRESS_WIDTH)
port map( picoblaze_reset => rdl_bus,
jtag_en => jtag_en,
jtag_din => jtag_din,
jtag_addr => jtag_addr(BRAM_ADDRESS_WIDTH-1 downto 0),
jtag_clk => jtag_clk,
jtag_we => jtag_we,
jtag_dout_0 => jtag_dout,
jtag_dout_1 => jtag_dout, -- ports 1-7 are not used
jtag_dout_2 => jtag_dout, -- in a 1 device debug
jtag_dout_3 => jtag_dout, -- session. However, Synplify
jtag_dout_4 => jtag_dout, -- etc require all ports to
jtag_dout_5 => jtag_dout, -- be connected
jtag_dout_6 => jtag_dout,
jtag_dout_7 => jtag_dout);
--
end generate instantiate_loader;
--
end low_level_definition;
--
--
-------------------------------------------------------------------------------------------
--
-- JTAG Loader
--
-------------------------------------------------------------------------------------------
--
--
-- JTAG Loader 6 - Version 6.00
-- Kris Chaplin 4 February 2010
-- Ken Chapman 15 August 2011 - Revised coding style
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
library unisim;
use unisim.vcomponents.all;
--
entity jtag_loader_6 is
generic( C_JTAG_LOADER_ENABLE : integer := 1;
C_FAMILY : string := "V6";
C_NUM_PICOBLAZE : integer := 1;
C_BRAM_MAX_ADDR_WIDTH : integer := 10;
C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18;
C_JTAG_CHAIN : integer := 2;
C_ADDR_WIDTH_0 : integer := 10;
C_ADDR_WIDTH_1 : integer := 10;
C_ADDR_WIDTH_2 : integer := 10;
C_ADDR_WIDTH_3 : integer := 10;
C_ADDR_WIDTH_4 : integer := 10;
C_ADDR_WIDTH_5 : integer := 10;
C_ADDR_WIDTH_6 : integer := 10;
C_ADDR_WIDTH_7 : integer := 10);
port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
jtag_din : out std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0');
jtag_addr : out std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0) := (others => '0');
jtag_clk : out std_logic := '0';
jtag_we : out std_logic := '0';
jtag_dout_0 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_1 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_2 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_3 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_4 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_5 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_6 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_7 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0));
end jtag_loader_6;
--
architecture Behavioral of jtag_loader_6 is
--
signal num_picoblaze : std_logic_vector(2 downto 0);
signal picoblaze_instruction_data_width : std_logic_vector(4 downto 0);
--
signal drck : std_logic;
signal shift_clk : std_logic;
signal shift_din : std_logic;
signal shift_dout : std_logic;
signal shift : std_logic;
signal capture : std_logic;
--
signal control_reg_ce : std_logic;
signal bram_ce : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
signal bus_zero : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
signal jtag_en_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
signal jtag_en_expanded : std_logic_vector(7 downto 0) := (others => '0');
signal jtag_addr_int : std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0);
signal jtag_din_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal control_din : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0');
signal control_dout : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0');
signal control_dout_int : std_logic_vector(7 downto 0):= (others => '0');
signal bram_dout_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0');
signal jtag_we_int : std_logic;
signal jtag_clk_int : std_logic;
signal bram_ce_valid : std_logic;
signal din_load : std_logic;
--
signal jtag_dout_0_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_1_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_2_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_3_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_4_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_5_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_6_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_7_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal picoblaze_reset_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
--
begin
bus_zero <= (others => '0');
--
jtag_loader_gen: if (C_JTAG_LOADER_ENABLE = 1) generate
--
-- Insert BSCAN primitive for target device architecture.
--
BSCAN_SPARTAN6_gen: if (C_FAMILY="S6") generate
begin
BSCAN_BLOCK_inst : BSCAN_SPARTAN6
generic map ( JTAG_CHAIN => C_JTAG_CHAIN)
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_SPARTAN6_gen;
--
BSCAN_VIRTEX6_gen: if (C_FAMILY="V6") generate
begin
BSCAN_BLOCK_inst: BSCAN_VIRTEX6
generic map( JTAG_CHAIN => C_JTAG_CHAIN,
DISABLE_JTAG => FALSE)
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_VIRTEX6_gen;
--
BSCAN_7SERIES_gen: if (C_FAMILY="7S") generate
begin
BSCAN_BLOCK_inst: BSCANE2
generic map( JTAG_CHAIN => C_JTAG_CHAIN,
DISABLE_JTAG => "FALSE")
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_7SERIES_gen;
--
--
-- Insert clock buffer to ensure reliable shift operations.
--
upload_clock: BUFG
port map( I => drck,
O => shift_clk);
--
--
-- Shift Register
--
--
control_reg_ce_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk = '1' then
if (shift = '1') then
control_reg_ce <= shift_din;
end if;
end if;
end process control_reg_ce_shift;
--
bram_ce_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
if(C_NUM_PICOBLAZE > 1) then
for i in 0 to C_NUM_PICOBLAZE-2 loop
bram_ce(i+1) <= bram_ce(i);
end loop;
end if;
bram_ce(0) <= control_reg_ce;
end if;
end if;
end process bram_ce_shift;
--
bram_we_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
jtag_we_int <= bram_ce(C_NUM_PICOBLAZE-1);
end if;
end if;
end process bram_we_shift;
--
bram_a_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
for i in 0 to C_BRAM_MAX_ADDR_WIDTH-2 loop
jtag_addr_int(i+1) <= jtag_addr_int(i);
end loop;
jtag_addr_int(0) <= jtag_we_int;
end if;
end if;
end process bram_a_shift;
--
bram_d_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (din_load = '1') then
jtag_din_int <= bram_dout_int;
elsif (shift = '1') then
for i in 0 to C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-2 loop
jtag_din_int(i+1) <= jtag_din_int(i);
end loop;
jtag_din_int(0) <= jtag_addr_int(C_BRAM_MAX_ADDR_WIDTH-1);
end if;
end if;
end process bram_d_shift;
--
shift_dout <= jtag_din_int(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1);
--
--
din_load_select:process (bram_ce, din_load, capture, bus_zero, control_reg_ce)
begin
if ( bram_ce = bus_zero ) then
din_load <= capture and control_reg_ce;
else
din_load <= capture;
end if;
end process din_load_select;
--
--
-- Control Registers
--
num_picoblaze <= conv_std_logic_vector(C_NUM_PICOBLAZE-1,3);
picoblaze_instruction_data_width <= conv_std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1,5);
--
control_registers: process(jtag_clk_int)
begin
if (jtag_clk_int'event and jtag_clk_int = '1') then
if (bram_ce_valid = '1') and (jtag_we_int = '0') and (control_reg_ce = '1') then
case (jtag_addr_int(3 downto 0)) is
when "0000" => -- 0 = version - returns (7 downto 4) illustrating number of PB
-- and (3 downto 0) picoblaze instruction data width
control_dout_int <= num_picoblaze & picoblaze_instruction_data_width;
when "0001" => -- 1 = PicoBlaze 0 reset / status
if (C_NUM_PICOBLAZE >= 1) then
control_dout_int <= picoblaze_reset_int(0) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_0-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0010" => -- 2 = PicoBlaze 1 reset / status
if (C_NUM_PICOBLAZE >= 2) then
control_dout_int <= picoblaze_reset_int(1) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_1-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0011" => -- 3 = PicoBlaze 2 reset / status
if (C_NUM_PICOBLAZE >= 3) then
control_dout_int <= picoblaze_reset_int(2) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_2-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0100" => -- 4 = PicoBlaze 3 reset / status
if (C_NUM_PICOBLAZE >= 4) then
control_dout_int <= picoblaze_reset_int(3) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_3-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0101" => -- 5 = PicoBlaze 4 reset / status
if (C_NUM_PICOBLAZE >= 5) then
control_dout_int <= picoblaze_reset_int(4) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_4-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0110" => -- 6 = PicoBlaze 5 reset / status
if (C_NUM_PICOBLAZE >= 6) then
control_dout_int <= picoblaze_reset_int(5) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_5-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0111" => -- 7 = PicoBlaze 6 reset / status
if (C_NUM_PICOBLAZE >= 7) then
control_dout_int <= picoblaze_reset_int(6) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_6-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "1000" => -- 8 = PicoBlaze 7 reset / status
if (C_NUM_PICOBLAZE >= 8) then
control_dout_int <= picoblaze_reset_int(7) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_7-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "1111" => control_dout_int <= conv_std_logic_vector(C_BRAM_MAX_ADDR_WIDTH -1,8);
when others => control_dout_int <= (others => '1');
end case;
else
control_dout_int <= (others => '0');
end if;
end if;
end process control_registers;
--
control_dout(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-8) <= control_dout_int;
--
pb_reset: process(jtag_clk_int)
begin
if (jtag_clk_int'event and jtag_clk_int = '1') then
if (bram_ce_valid = '1') and (jtag_we_int = '1') and (control_reg_ce = '1') then
picoblaze_reset_int(C_NUM_PICOBLAZE-1 downto 0) <= control_din(C_NUM_PICOBLAZE-1 downto 0);
end if;
end if;
end process pb_reset;
--
--
-- Assignments
--
control_dout (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-9 downto 0) <= (others => '0') when (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH > 8);
--
-- Qualify the blockram CS signal with bscan select output
jtag_en_int <= bram_ce when bram_ce_valid = '1' else (others => '0');
--
jtag_en_expanded(C_NUM_PICOBLAZE-1 downto 0) <= jtag_en_int;
jtag_en_expanded(7 downto C_NUM_PICOBLAZE) <= (others => '0') when (C_NUM_PICOBLAZE < 8);
--
bram_dout_int <= control_dout or jtag_dout_0_masked or jtag_dout_1_masked or jtag_dout_2_masked or jtag_dout_3_masked or jtag_dout_4_masked or jtag_dout_5_masked or jtag_dout_6_masked or jtag_dout_7_masked;
--
control_din <= jtag_din_int;
--
jtag_dout_0_masked <= jtag_dout_0 when jtag_en_expanded(0) = '1' else (others => '0');
jtag_dout_1_masked <= jtag_dout_1 when jtag_en_expanded(1) = '1' else (others => '0');
jtag_dout_2_masked <= jtag_dout_2 when jtag_en_expanded(2) = '1' else (others => '0');
jtag_dout_3_masked <= jtag_dout_3 when jtag_en_expanded(3) = '1' else (others => '0');
jtag_dout_4_masked <= jtag_dout_4 when jtag_en_expanded(4) = '1' else (others => '0');
jtag_dout_5_masked <= jtag_dout_5 when jtag_en_expanded(5) = '1' else (others => '0');
jtag_dout_6_masked <= jtag_dout_6 when jtag_en_expanded(6) = '1' else (others => '0');
jtag_dout_7_masked <= jtag_dout_7 when jtag_en_expanded(7) = '1' else (others => '0');
--
jtag_en <= jtag_en_int;
jtag_din <= jtag_din_int;
jtag_addr <= jtag_addr_int;
jtag_clk <= jtag_clk_int;
jtag_we <= jtag_we_int;
picoblaze_reset <= picoblaze_reset_int;
--
end generate jtag_loader_gen;
--
end Behavioral;
--
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
--!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! @brief Debug Support Unit (DSU) with AXI4 interface.
--! @details DSU provides access to the internal CPU registers via
--! 'Debug port' bus interface available only on <b>RIVER</b> CPU.
--! It is also implements a set of registers collecting bus
--! utilization statistic and additional debug information.
-----------------------------------------------------------------------------
--! VHDL base library.
library ieee;
--! VHDL base types import
use ieee.std_logic_1164.all;
--! VHDL base numeric import
use ieee.numeric_std.all;
--! SoC common functionality library.
library commonlib;
--! SoC common types import
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
use ambalib.types_bus0.all; -- TODO: REMOVE ME when update dsu
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
--! River top level with AMBA interface module declaration
use riverlib.types_river.all;
entity axi_dsu is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port
(
clk : in std_logic;
nrst : in std_logic;
o_cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_dporti : out dport_in_vector;
i_dporto : in dport_out_vector;
-- DMI interface
i_dmi_hartsel : in std_logic_vector(CFG_LOG2_CPU_MAX-1 downto 0);
o_dmi_req_valid : out std_logic;
i_dmi_req_ready : in std_logic;
o_dmi_write : out std_logic;
o_dmi_addr : out std_logic_vector(6 downto 0);
o_dmi_wdata : out std_logic_vector(31 downto 0);
i_dmi_resp_valid : in std_logic;
o_dmi_resp_ready : out std_logic;
i_dmi_rdata : in std_logic_vector(31 downto 0);
-- Platfrom run-time statistic
i_bus_util_w : in std_logic_vector(CFG_BUS0_XMST_TOTAL-1 downto 0);
i_bus_util_r : in std_logic_vector(CFG_BUS0_XMST_TOTAL-1 downto 0)
);
end;
architecture arch_axi_dsu of axi_dsu is
constant xconfig : axi4_slave_config_type := (
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES,
irq_idx => conv_std_logic_vector(0, 8),
xaddr => conv_std_logic_vector(xaddr, CFG_SYSBUS_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_SYSBUS_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_DSU
);
constant zero64 : std_logic_vector(63 downto 0) := (others => '0');
type state_type is (
idle,
wait_write_msb,
check_request,
dmi_request,
dmi_response,
dport_request,
dport_wait_resp,
axi_response,
axi_response_msb
);
type mst_utilization_type is array (0 to CFG_BUS0_XMST_TOTAL-1)
of std_logic_vector(63 downto 0);
type mst_utilization_map_type is array (0 to 2*CFG_BUS0_XMST_TOTAL-1)
of std_logic_vector(63 downto 0);
type registers is record
state : state_type;
r32 : std_logic;
wdata : std_logic_vector(63 downto 0);
-- Platform statistic:
clk_cnt : std_logic_vector(63 downto 0);
util_w_cnt : mst_utilization_type;
util_r_cnt : mst_utilization_type;
addr : std_logic_vector(CFG_DPORT_ADDR_BITS-1 downto 0);
rdata : std_logic_vector(63 downto 0);
write : std_logic;
end record;
constant R_RESET : registers := (
idle, '0', -- state, r32
(others => '0'), -- wdata,
(others => '0'), -- clk_cnt
(others => zero64), (others => zero64),
(others => '0'), -- addr
(others => '0'), -- rdata
'0' -- write
);
signal r, rin: registers;
signal wb_bus_raddr : global_addr_array_type;
signal w_bus_re : std_logic;
signal w_bus_r32 : std_logic;
signal wb_bus_waddr : global_addr_array_type;
signal w_bus_we : std_logic;
signal wb_bus_wstrb : std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
signal wb_bus_wdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
signal w_axi_ready : std_logic;
begin
axi0 : axi4_slave generic map (
async_reset => async_reset
) port map (
i_clk => clk,
i_nrst => nrst,
i_xcfg => xconfig,
i_xslvi => i_axi,
o_xslvo => o_axi,
i_ready => w_axi_ready,
i_rdata => r.rdata,
o_re => w_bus_re,
o_r32 => w_bus_r32,
o_radr => wb_bus_raddr,
o_wadr => wb_bus_waddr,
o_we => w_bus_we,
o_wstrb => wb_bus_wstrb,
o_wdata => wb_bus_wdata
);
comblogic : process(nrst, i_dporto, i_bus_util_w, i_bus_util_r, r,
i_dmi_hartsel, i_dmi_req_ready, i_dmi_resp_valid, i_dmi_rdata,
w_bus_re, w_bus_r32, wb_bus_raddr, wb_bus_waddr,
w_bus_we, wb_bus_wstrb, wb_bus_wdata)
variable v : registers;
variable vdporti : dport_in_vector;
variable wb_bus_util_map : mst_utilization_map_type;
variable cpuidx : integer;
variable v_axi_ready : std_logic;
variable v_dmi_req_valid : std_logic;
variable v_dmi_resp_ready : std_logic;
begin
v := r;
v_axi_ready := '0';
v_dmi_req_valid := '0';
v_dmi_resp_ready := '0';
vdporti := (others => dport_in_none);
cpuidx := conv_integer(i_dmi_hartsel);
-- Update statistic:
v.clk_cnt := r.clk_cnt + 1;
-- TODO: move out these stuffs to bus-tracer
for n in 0 to CFG_BUS0_XMST_TOTAL-1 loop
if i_bus_util_w(n) = '1' then
v.util_w_cnt(n) := r.util_w_cnt(n) + 1;
end if;
if i_bus_util_r(n) = '1' then
v.util_r_cnt(n) := r.util_r_cnt(n) + 1;
end if;
end loop;
for n in 0 to CFG_BUS0_XMST_TOTAL-1 loop
wb_bus_util_map(2*n) := r.util_w_cnt(n);
wb_bus_util_map(2*n+1) := r.util_r_cnt(n);
end loop;
case r.state is
when idle =>
v_axi_ready := '1';
v.addr := (others => '0');
v.wdata := (others => '0');
v.rdata := (others => '0');
if w_bus_we = '1' then
v.write := '1';
v.addr := wb_bus_waddr(0)(CFG_DPORT_ADDR_BITS+2 downto 3);
v.wdata := wb_bus_wdata;
if wb_bus_wstrb = X"FF" then
v.state := check_request;
elsif wb_bus_wstrb(3 downto 0) = X"F" then
v.state := wait_write_msb;
else
-- shouldn't be here, it is better to generate slave error
v.state := axi_response;
end if;
elsif w_bus_re = '1' then
v.write := '0';
v.addr := wb_bus_raddr(0)(CFG_DPORT_ADDR_BITS+2 downto 3);
v.r32 := w_bus_r32; -- burst 2 clocks (very bad style)
v.state := check_request;
end if;
when wait_write_msb =>
v_axi_ready := '1';
if w_bus_we = '1' and wb_bus_wstrb(7 downto 4) = X"F" then
v.wdata(63 downto 32) := wb_bus_wdata(63 downto 32);
v.state := check_request;
end if;
when check_request =>
v.rdata := (others => '0');
if conv_integer(r.addr) < 3*4096 then -- 0x3000 on 3 banks
v.state := dport_request;
else
v.state := dmi_request;
end if;
when dmi_request =>
v_dmi_req_valid := '1';
if i_dmi_req_ready = '1' then
v.state := dmi_response;
end if;
when dmi_response =>
v_dmi_resp_ready := '1';
if i_dmi_resp_valid = '1' then
v.rdata(31 downto 0) := i_dmi_rdata;
if r.write = '1' then
v.state := idle;
else
v.state := axi_response;
end if;
end if;
when dport_request =>
vdporti(cpuidx).req_valid := '1';
vdporti(cpuidx).write := r.write;
vdporti(cpuidx).addr := r.addr;
vdporti(cpuidx).wdata := r.wdata;
if i_dporto(cpuidx).req_ready = '1' then
v.state := dport_wait_resp;
end if;
when dport_wait_resp =>
vdporti(cpuidx).resp_ready := '1';
if i_dporto(cpuidx).resp_valid = '1' then
v.rdata := i_dporto(cpuidx).rdata;
if r.write = '1' then
v.state := idle;
else
v.state := axi_response;
end if;
end if;
when axi_response =>
v_axi_ready := '1';
if r.write = '0' and r.r32 = '1' then
v.state := axi_response_msb; -- burst transaction
else
v.state := idle;
end if;
when axi_response_msb =>
v_axi_ready := '1';
v.state := idle;
when others =>
end case;
if not async_reset and nrst = '0' then
v := R_RESET;
end if;
rin <= v;
o_dmi_req_valid <= v_dmi_req_valid;
o_dmi_write <= r.write;
o_dmi_addr <= r.addr(6 downto 0);
o_dmi_wdata <= r.wdata(31 downto 0);
o_dmi_resp_ready <= v_dmi_resp_ready;
o_dporti <= vdporti;
w_axi_ready <= v_axi_ready;
end process;
o_cfg <= xconfig;
-- registers:
regs : process(clk, nrst)
begin
if async_reset and nrst = '0' then
r <= R_RESET;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06:28:55 11/20/2014
-- Design Name:
-- Module Name: calc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity calc is
generic (clk_frq: Integer := 50_000_000); -- 50 MHz
Port (
rst : in STD_ULOGIC; -- BTN_SOUTH
clk : in STD_ULOGIC;
rot_c : in STD_ULOGIC;
btn_east : in STD_ULOGIC;
btn_west : in STD_ULOGIC;
btn_north : in STD_ULOGIC;
sw : in STD_ULOGIC_VECTOR (3 downto 0);
led : out STD_ULOGIC_VECTOR (7 downto 0));
end calc;
architecture Behavioral of calc is
signal op1 : STD_ULOGIC_VECTOR (3 downto 0);
signal op2 : STD_ULOGIC_VECTOR (3 downto 0);
signal op : STD_ULOGIC_VECTOR (2 downto 0);
signal dbnc_cnt : integer;
signal rot_c_prev : STD_ULOGIC;
signal rot_c_dbnc : STD_ULOGIC;
component ctrl is
Port (
rst : in STD_ULOGIC;
clk : in STD_ULOGIC;
rot_c : in STD_ULOGIC;
btn_east : in STD_ULOGIC;
btn_west : in STD_ULOGIC;
btn_north : in STD_ULOGIC;
sw : in STD_ULOGIC_VECTOR (3 downto 0);
op1 : out STD_ULOGIC_VECTOR (3 downto 0);
op2 : out STD_ULOGIC_VECTOR (3 downto 0);
op : out STD_ULOGIC_VECTOR (2 downto 0)
);
end component ctrl;
component proc is
Port (
op1 : in STD_ULOGIC_VECTOR (3 downto 0);
op2 : in STD_ULOGIC_VECTOR (3 downto 0);
op : in STD_ULOGIC_VECTOR (2 downto 0);
led : out STD_ULOGIC_VECTOR (7 downto 0)
);
end component;
begin
ctrlinst : ctrl
Port Map ( rst => rst ,
clk => clk ,
rot_c => rot_c_dbnc,
btn_east => btn_east ,
btn_west => btn_west ,
btn_north => btn_north,
sw => sw ,
op1 => op1 ,
op2 => op2 ,
op => op
);
procinst : proc
Port Map ( op1 => op1,
op2 => op2,
op => op ,
led => led
);
dbnc_rot_c : process(rot_c, rst, clk)
begin
if rst = '1' then
dbnc_cnt <= 5000000;
rot_c_dbnc <= '0';
elsif rising_edge(clk) then
if dbnc_cnt = 0 then
dbnc_cnt <= 5000000;
rot_c_dbnc <= rot_c_dbnc;
elsif dbnc_cnt < 5000000 then
dbnc_cnt <= dbnc_cnt - 1;
rot_c_dbnc <= rot_c_dbnc;
elsif rot_c_prev /= rot_c then
dbnc_cnt <= dbnc_cnt - 1;
rot_c_dbnc <= rot_c;
else
dbnc_cnt <= 5000000;
rot_c_dbnc <= rot_c_dbnc;
end if;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cronometro is
port (
clock_50: in std_logic;
dificuldade: in std_logic_vector(1 downto 0);
reset: in std_logic;
restante: out std_logic_vector(7 downto 0);
atual: out std_logic_vector(7 downto 0)
);
end cronometro;
architecture circuito of cronometro is
signal clk_1hz: std_logic;
signal contagem: std_logic_vector(7 downto 0);
signal maximo: std_logic_vector(7 downto 0);
component clock_conv
port
(
IN_50MHz : in std_logic;
OUT_0_1Hz : out std_logic;
OUT_1Hz : out std_logic;
OUT_10Hz : out std_logic
);
end component;
begin
converter: clock_conv port map(clock_50, open, clk_1hz, open);
process(dificuldade, clock_50)
begin
-- define o tempo maximo da contagem levando em conta a dificuldade escolhida
case dificuldade is
when "00" =>
maximo <= "00011110";
when "01" =>
maximo <= "00010100";
when "10" =>
maximo <= "00001010";
when "11" =>
maximo <= "00000101";
end case;
end process;
process(clk_1hz, reset)
begin
if (reset = '1') then
-- reset assincrono
contagem <= "00000000";
elsif (rising_edge(clk_1hz)) then
-- se a o tempo atual for maior que o tempo maximo, reseta o tempo atual, senao, adiciona um ao tempo atual
if (contagem >= maximo) then
contagem <= "00000000";
else
contagem <= contagem + '1';
end if;
end if;
end process;
-- para obter o tempo restante, subtraimos o tempo atual do tempo maximo
restante <= maximo - contagem;
atual <= contagem;
end circuito; |
library ieee;
use ieee.std_logic_1164.all;
--XOR is an easy task and can take place everywhere easily. But since in DES it is a separate step, it is implemented separetely.
entity xor_48_bits is
port( data_in: in std_logic_vector(0 to 47);
key: in std_logic_vector(0 to 47);
data_out: out std_logic_vector(0 to 47));
end xor_48_bits;
architecture behavior of xor_48_bits is
begin
data_out<= key xor data_in;
end behavior;
|
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
--procedure str_write(file out_file: TEXT;
-- new_string: in string) is
-- begin
--
-- for i in new_string'range loop
-- print(out_file, new_string(i));
-- if new_string(i) = LF then -- end of string
-- exit;
-- end if;
-- end loop;
--
--end str_write;
end txt_util;
|
------------------------------------------------------------------------------
-- @license MIT
-- @brief
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.global.all;
use work.reg;
entity text2sym_conv_and_stage_freq is
port(
i_clk : in std_logic;
in_rst : in std_logic;
-- Input port.
s_axis_tdata : in std_logic_vector(7 downto 0);
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tlast : in std_logic;
-- Output stuff.
o_stage : out t_stage;
o_pipe_en : out std_logic;
o_pipe_flush : out std_logic;
o_sym : out t_sym
);
end entity text2sym_conv_and_stage_freq;
architecture arch_text2sym_conv_and_stage_freq of
text2sym_conv_and_stage_freq is
type t_states is (
NEW_CHAR,
UPPER_NIBBLE,
LAST_STAGE,
UPPER_NIBBLE_LAST,
FLUSH
);
signal state : t_states;
signal sym : t_sym;
signal en : std_logic;
signal up_nib : t_sym;
signal next_up_nib : t_sym;
signal up_nib_en : std_logic;
signal stage : t_stage;
signal next_stage : t_stage;
signal wrap_stage : t_stage;
signal stage_en : std_logic;
begin
-- Regiser and transition function.
process(i_clk, in_rst)
begin
if in_rst = '0' then
state <= NEW_CHAR;
elsif rising_edge(i_clk) then
case state is
when NEW_CHAR =>
if s_axis_tvalid = '1' then
if s_axis_tlast = '1' then
state <= UPPER_NIBBLE_LAST;
else
state <= UPPER_NIBBLE;
end if;
end if;
when UPPER_NIBBLE =>
if stage = 15 then
state <= LAST_STAGE;
else
state <= NEW_CHAR;
end if;
when LAST_STAGE =>
state <= NEW_CHAR;
when UPPER_NIBBLE_LAST =>
state <= FLUSH;
when FLUSH =>
-- TODO Implement.
state <= NEW_CHAR;
end case;
end if;
end process;
with state select en <=
s_axis_tvalid when NEW_CHAR,
'1' when others;
o_pipe_en <= en;
with state select s_axis_tready <=
'1' when NEW_CHAR,
'0' when others;
with state select o_pipe_flush <=
'1' when FLUSH,
'0' when others;
with state select sym <=
s_axis_tdata(3 downto 0) when NEW_CHAR,
up_nib when others;
o_sym <= sym;
-- Upper nibble.
with state select up_nib_en <=
s_axis_tvalid when NEW_CHAR,
'0' when others;
next_up_nib <= s_axis_tdata(7 downto 4) when up_nib_en = '1' else up_nib;
up_nib_reg: entity reg
generic map(
WIDTH => 4
)
port map(
i_clk => i_clk,
in_rst => in_rst,
i_d => next_up_nib,
o_q => up_nib
);
-- Stage counter.
stage_en <= en;
wrap_stage <= "00000" when stage = 16 else stage + 1;
next_stage <= wrap_stage when stage_en = '1' else stage;
stage_reg: entity reg
generic map(
WIDTH => 5
)
port map(
i_clk => i_clk,
in_rst => in_rst,
i_d => next_stage,
o_q => stage
);
o_stage <= stage;
end architecture arch_text2sym_conv_and_stage_freq;
|
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
USE IEEE.std_logic_signed.all; --math operations for signed std_logic
ENTITY tb_counter_up_down_4bit IS END tb_counter_up_down_4bit;
ARCHITECTURE test OF tb_counter_up_down_4bit IS
COMPONENT counter_up_down_4bit IS
PORT(up, clk, reset : IN STD_LOGIC;
out1: OUT STD_LOGIC;
out2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
SIGNAL up: STD_LOGIC;
SIGNAL reset: STD_LOGIC:='0';
SIGNAL clk: STD_LOGIC:='0';
SIGNAL out1: STD_LOGIC:='0';
SIGNAL out2: STD_LOGIC_VECTOR(3 DOWNTO 0):=(OTHERS=>'0');
BEGIN
T1: counter_up_down_4bit PORT MAP(up, clk, reset, out1, out2);
reset<='1' AFTER 125 ns;
clk<=NOT(clk) AFTER 50 ns;
up<='1',
'0' AFTER 945 ns,
'1' AFTER 1845 ns,
'0' AFTER 2025 ns;
END test;
|
-- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
---------------------------------------------------------------------------------------------------------}}}
entity WG_dispatcher is
-- ports {{{
port(
clk, nrst : in std_logic;
start : in std_logic;
initialize_d0 : in std_logic;
start_exec : out std_logic := '0';
krnl_indx : in integer range 0 to NEW_KRNL_MAX_INDX-1;
krnl_sch_rdAddr : out std_logic_vector(KRNL_SCH_ADDR_W-1 downto 0) := (others => '0');
krnl_sch_rdData : in std_logic_vector(DATA_W-1 downto 0) := (others => '0');
finish : out std_logic := '0';
finish_krnl_indx : out integer range 0 to NEW_KRNL_MAX_INDX-1 := 0;
-- index of kernel whose execution just finished
start_addr : out unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0');
-- cds interface
req : out std_logic_vector(N_CU-1 downto 0) := (others => '0');
ack : in std_logic_vector(N_CU-1 downto 0) := (others => '0');
sch_rqst_n_WFs_m1 : out unsigned(N_WF_CU_W-1 downto 0) := (others=>'0');
wf_active : in wf_active_array(N_CU-1 downto 0) := (others=>(others=>'0'));
wg_info : out unsigned(DATA_W-1 downto 0) := (others=>'0');
rdData_alu_en : out alu_en_vec_type(N_CU-1 downto 0) := (others=>(others=>'0'));
rdAddr_alu_en : in alu_en_rdAddr_type(N_CU-1 downto 0) := (others=>(others=>'0'));
rtm_wrAddr : out unsigned(RTM_ADDR_W-1 downto 0) := (others => '0');
rtm_wrData : out unsigned(RTM_DATA_W-1 downto 0) := (others => '0');
rtm_we : out std_logic := '0'
);
-- }}}
end WG_dispatcher;
architecture Behavioral of WG_dispatcher is
-- internal signals {{{
signal start_exec_i : std_logic := '0';
signal finish_i : std_logic := '0';
signal sch_rqst_n_WFs_m1_i : unsigned(N_WF_CU_W-1 downto 0) := (others=>'0');
-- }}}
-- signals definitions {{{
signal schedulingInProgress : std_logic_vector(N_CU-1 downto 0) := (others=>'0');
signal schedulingInProgress_n : std_logic_vector(N_CU-1 downto 0) := (others=>'0');
signal nDim : integer range 0 to 2 := 0;
type WG_st_sch_type is (idle, read_delay, prepare, seekCV, allocateWFs, checkAgain, wait_wf_active, wait_finish);
signal st_sch, st_sch_n : WG_st_sch_type := idle;
signal st_prepare, st_prepare_d0 : unsigned(NEW_KRNL_DESC_W-1 downto 0) := (others => '0');
signal st_prepare_n : unsigned(NEW_KRNL_DESC_W-1 downto 0) := (others => '0');
signal params : unsigned(DATA_W-1 downto 0) := (others=>'0');
signal params_wrAddr : unsigned(N_PARAMS_W-1 downto 0) := (others=>'0');
signal params_written, params_written_n : std_logic := '0';
signal krnl_infos_we : std_logic := '0';
signal id0_offset : unsigned(DATA_W-1 downto 0) := (others => '0');
signal id1_offset : unsigned(DATA_W-1 downto 0) := (others => '0');
signal id2_offset : unsigned(DATA_W-1 downto 0) := (others => '0');
signal id0_size : unsigned(DATA_W-1 downto 0) := (others => '0');
signal id1_size : unsigned(DATA_W-1 downto 0) := (others => '0');
signal id2_size : unsigned(DATA_W-1 downto 0) := (others => '0');
signal wg_size : unsigned(WG_SIZE_W downto 0) := (others=>'0');
signal wg_size_d0 : integer range 0 to WG_MAX_SIZE := 0;
signal wg_size_d1 : integer range 0 to WG_MAX_SIZE := 0;
signal wg_size_d2 : integer range 0 to WG_MAX_SIZE := 0;
signal start_prepare : std_logic := '0';
signal prepare_params_n, prepare_params : std_logic := '0';
signal krnl_indx_ltchd : integer range 0 to NEW_KRNL_MAX_INDX-1 := 0;
signal addr_first_inst : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0');
signal n_wg_d0_m1 : unsigned(DATA_W-1 downto 0) := (others => '0');
signal n_wg_d1_m1 : unsigned(DATA_W-1 downto 0) := (others => '0');
signal n_wg_d2_m1 : unsigned(DATA_W-1 downto 0) := (others => '0');
signal prepare_fin : std_logic := '0';
signal nDisp_wg_d0 : unsigned(DATA_W-1 downto 0) := (others => '0');
signal nDisp_wg_d1 : unsigned(DATA_W-1 downto 0) := (others => '0');
signal nDisp_wg_d2 : unsigned(DATA_W-1 downto 0) := (others => '0');
signal nDisp_wg_d1_ov : std_logic := '0';
signal nDisp_wg_d0_ov : std_logic := '0';
signal id0,id1,id2 : unsigned(DATA_W-1 downto 0) := (others => '0');
signal nParams : integer range 0 to N_PARAMS := 0;
-- next signals
signal prepare_fin_n, prepare_fin_d0 : std_logic := '0';
signal start_loc_indcs : std_logic := '0';
signal start_prepare_n : std_logic := '0';
signal nDisp_wg_d0_n : unsigned(DATA_W-1 downto 0) := (others => '0');
signal nDisp_wg_d1_n : unsigned(DATA_W-1 downto 0) := (others => '0');
signal nDisp_wg_d2_n : unsigned(DATA_W-1 downto 0) := (others => '0');
signal id0_n,id1_n,id2_n : unsigned(DATA_W-1 downto 0) := (others => '0');
signal nDisp_wg_d0_ov_n : std_logic := '0';
signal nDisp_wg_d1_ov_n : std_logic := '0';
signal req_n : std_logic_vector(N_CU-1 downto 0) := (others => '0');
signal wg_info_n : unsigned(DATA_W-1 downto 0) := (others=>'0');
signal alu_en_rdy : std_logic := '0';
signal start_d0 : std_logic := '0';
-- }}}
-- RTM signals{{{
signal rtm_we_n : std_logic := '0';
signal rtm_wrAddr_n : unsigned(RTM_ADDR_W-1 downto 0) := (others => '0');
signal rtm_wrData_n : unsigned(RTM_DATA_W-1 downto 0) := (others => '0');
--}}}
-- scheduling signals {{{
signal alloc_CV_indx : integer range 0 to N_CU := 0;
signal cd_indx, cd_indx_d0, cd_indx_d1 : unsigned(max(N_CU_W, 1)-1 downto 0) := (others=>'0');
signal wf_active_slctd : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0');
signal n_inactive_wfs : integer range 0 to N_WF_CU := 0;
--}}}
-- loc indices signals {{{
signal loc_indcs_fin : std_logic := '0';
signal loc_indcs_wrAddr : unsigned(RTM_ADDR_W-2 downto 0) := (others => '0');
signal loc_indcs_wrData : unsigned(RTM_DATA_W-1 downto 0) := (others => '0');
signal loc_indcs_we : std_logic := '0';
type loc_indcs_wr_state_type is ( write_size0, write_size1, write_size2, write_wg_size_d0, write_wg_size_d1, write_wg_size_d2, write_n_wgs_d0, write_n_wgs_d1,
write_n_wgs_d2, write_params, write_loc_indcs, write_d0, write_d1, write_d2);
signal loc_indcs_wr_state : loc_indcs_wr_state_type := write_size0;
signal loc_indcs_wr_state_n : loc_indcs_wr_state_type := write_size0;
-- }}}
begin
-- internal signals assignments --------------------------------------------------------------------{{{
assert(RTM_DATA_W >= DATA_W) severity failure;
start_exec <= start_exec_i;
sch_rqst_n_WFs_m1 <= sch_rqst_n_WFs_m1_i;
---------------------------------------------------------------------------------------------------------}}}
-- others {{{
finish_krnl_indx <= krnl_indx_ltchd;
start_addr <= addr_first_inst;
--}}}
-- local indices generator ------------------------------------------------------------------------------------ {{{
loc_indcs_gen: entity loc_indcs_generator port map(
clk => clk,
start => start_loc_indcs,
finish => loc_indcs_fin,
clear_finish => start_exec_i,
n_wf_wg_m1 => sch_rqst_n_WFs_m1_i,
wg_size_d0 => wg_size_d0,
wg_size_d1 => wg_size_d1,
wg_size_d2 => wg_size_d2,
wrAddr => loc_indcs_wrAddr,
we => loc_indcs_we,
wrData => loc_indcs_wrData,
nrst => nrst
);
start_exec_i <= (loc_indcs_fin and alu_en_rdy) or params_written;
process(clk)
begin
if rising_edge(clk) then
finish <= finish_i;
rtm_we <= rtm_we_n;
rtm_wrAddr <= rtm_wrAddr_n;
rtm_wrData <= rtm_wrData_n;
wg_info <= wg_info_n;
start_d0 <= start;
params_written <= params_written_n;
if nrst = '0' then
loc_indcs_wr_state <= write_size0;
else
loc_indcs_wr_state <= loc_indcs_wr_state_n;
end if;
end if;
end process;
process(loc_indcs_wr_state, req_n, id0, id1, id2, start_exec_i, loc_indcs_we, loc_indcs_wrAddr, loc_indcs_wrData, krnl_infos_we, params_wrAddr,
params, prepare_fin_d0, finish_i, wg_size_d0, wg_size_d1, wg_size_d2, id0_size, id1_size, id2_size, n_wg_d0_m1, n_wg_d1_m1, n_wg_d2_m1,
initialize_d0, start_d0)
begin
loc_indcs_wr_state_n <= loc_indcs_wr_state;
rtm_we_n <= loc_indcs_we;
rtm_wrAddr_n(RTM_ADDR_W-2 downto 0) <= loc_indcs_wrAddr;
rtm_wrAddr_n(RTM_ADDR_W-1) <= '0';
rtm_wrData_n <= loc_indcs_wrData;
wg_info_n <= id0;
params_written_n <= '0';
case loc_indcs_wr_state is
when write_size0 =>
rtm_we_n <= krnl_infos_we;
rtm_wrAddr_n(RTM_ADDR_W-1) <= '1';
rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11";
rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'0', others=>'1');
rtm_wrAddr_n(PHASE_W-1 downto 0) <= (others=>'0');
rtm_wrData_n(DATA_W-1 downto 0) <= id0_size;
if krnl_infos_we = '1' then
loc_indcs_wr_state_n <= write_size1;
end if;
if start_d0 = '1' and initialize_d0 = '0' then
loc_indcs_wr_state_n <= write_params;
end if;
when write_size1 =>
rtm_we_n <= krnl_infos_we;
rtm_wrAddr_n(RTM_ADDR_W-1) <= '1';
rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11";
rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'0', others=>'1');
rtm_wrAddr_n(PHASE_W-1 downto 0) <= (0=>'1', others=>'0');
rtm_wrData_n(DATA_W-1 downto 0) <= id1_size;
if krnl_infos_we = '1' then
loc_indcs_wr_state_n <= write_size2;
end if;
when write_size2 =>
rtm_we_n <= krnl_infos_we;
rtm_wrAddr_n(RTM_ADDR_W-1) <= '1';
rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11";
rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'0', others=>'1');
rtm_wrAddr_n(PHASE_W-1 downto 0) <= (1=>'1', others=>'0');
rtm_wrData_n(DATA_W-1 downto 0) <= id2_size;
if krnl_infos_we = '1' then
loc_indcs_wr_state_n <= write_wg_size_d0;
end if;
when write_wg_size_d0 =>
rtm_we_n <= krnl_infos_we;
rtm_wrAddr_n(RTM_ADDR_W-1) <= '1';
rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11";
rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+1=>'1', others=>'0');
rtm_wrAddr_n(PHASE_W-1 downto 0) <= (others=>'0');
rtm_wrData_n(DATA_W-1 downto WG_SIZE_W+1) <= (others=>'0');
rtm_wrData_n(WG_SIZE_W downto 0) <= to_unsigned(wg_size_d0, WG_SIZE_W+1);
if krnl_infos_we = '1' then
loc_indcs_wr_state_n <= write_n_wgs_d0;
end if;
when write_n_wgs_d0 =>
rtm_we_n <= krnl_infos_we;
rtm_wrAddr_n(RTM_ADDR_W-1) <= '1';
rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11";
rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'1', others=>'0');
rtm_wrAddr_n(PHASE_W-1 downto 0) <= (others=>'0');
rtm_wrData_n(DATA_W-1 downto 0) <= n_wg_d0_m1;
if krnl_infos_we = '1' then
loc_indcs_wr_state_n <= write_n_wgs_d1;
end if;
when write_n_wgs_d1 =>
rtm_we_n <= krnl_infos_we;
rtm_wrAddr_n(RTM_ADDR_W-1) <= '1';
rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11";
rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'1', others=>'0');
rtm_wrAddr_n(PHASE_W-1 downto 0) <= (0=>'1', others=>'0');
rtm_wrData_n(DATA_W-1 downto 0) <= n_wg_d1_m1;
if krnl_infos_we = '1' then
loc_indcs_wr_state_n <= write_n_wgs_d2;
end if;
when write_n_wgs_d2 =>
rtm_we_n <= krnl_infos_we;
rtm_wrAddr_n(RTM_ADDR_W-1) <= '1';
rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11";
rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'1', others=>'0');
rtm_wrAddr_n(PHASE_W-1 downto 0) <= (1=>'1', others=>'0');
rtm_wrData_n(DATA_W-1 downto 0) <= n_wg_d2_m1;
if krnl_infos_we = '1' then
loc_indcs_wr_state_n <= write_wg_size_d1;
end if;
when write_wg_size_d1 =>
rtm_we_n <= '1';
rtm_wrAddr_n(RTM_ADDR_W-1) <= '1';
rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11";
rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+1=>'1', others=>'0');
rtm_wrAddr_n(PHASE_W-1 downto 0) <= (0=>'1', others=>'0');
rtm_wrData_n(DATA_W-1 downto WG_SIZE_W+1) <= (others=>'0');
rtm_wrData_n(WG_SIZE_W downto 0) <= to_unsigned(wg_size_d1, WG_SIZE_W+1);
loc_indcs_wr_state_n <= write_wg_size_d2;
when write_wg_size_d2 =>
rtm_we_n <= '1';
rtm_wrAddr_n(RTM_ADDR_W-1) <= '1';
rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11";
rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+1=>'1', others=>'0');
rtm_wrAddr_n(PHASE_W-1 downto 0) <= (1=>'1', others=>'0');
rtm_wrData_n(DATA_W-1 downto WG_SIZE_W+1) <= (others=>'0');
rtm_wrData_n(WG_SIZE_W downto 0) <= to_unsigned(wg_size_d2, WG_SIZE_W+1);
loc_indcs_wr_state_n <= write_params;
when write_params =>
rtm_we_n <= krnl_infos_we;
rtm_wrAddr_n(RTM_ADDR_W-1) <= '1';
rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11";
rtm_wrAddr_n(RTM_ADDR_W-4 downto N_PARAMS_W) <= (others=>'0');
rtm_wrAddr_n(N_PARAMS_W-1 downto 0) <= params_wrAddr;
rtm_wrData_n(DATA_W-1 downto 0) <= params;
if prepare_fin_d0 = '1' then
if initialize_d0 = '0' then
loc_indcs_wr_state_n <= write_d0;
params_written_n <= '1';
else
loc_indcs_wr_state_n <= write_loc_indcs;
end if;
end if;
when write_loc_indcs =>
if start_exec_i = '1' then
loc_indcs_wr_state_n <= write_d0;
end if;
rtm_wrData_n <= loc_indcs_wrData;
when write_d0 => -- rtm_we has not to be set during write_dx because it is done in the CU_schceduler.
-- in case that a WG consists of multiple WFs, the WG's offsets need to written multiple times.
wg_info_n <= id0;
if to_integer(unsigned(req_n)) /= 0 then
loc_indcs_wr_state_n <= write_d1;
end if;
if finish_i = '1' then
loc_indcs_wr_state_n <= write_size0;
end if;
when write_d1 =>
wg_info_n <= id1;
loc_indcs_wr_state_n <= write_d2;
when write_d2 =>
wg_info_n <= id2;
loc_indcs_wr_state_n <= write_d0;
end case;
end process;
---------------------------------------------------------------------------------------------------------------}}}
-- WG scheduler FSM ------------------------------------------------------------------------------------{{{
process(st_sch, start, alloc_CV_indx, start_exec_i, nDisp_wg_d0_ov, nDisp_wg_d1_ov, nDisp_wg_d0, nDisp_wg_d1, nDisp_wg_d2, id0, id1, id2,
id0_offset, id1_offset, id2_offset, n_wg_d0_m1, n_wg_d1_m1, n_wg_d2_m1, wg_size_d0, wg_size_d1, wg_size_d2, wf_active, schedulingInProgress,
initialize_d0) --, alloc_CV_indx_ltchd)
begin
st_sch_n <= st_sch;
start_prepare_n <= '0';
id0_n <= id0;
id1_n <= id1;
id2_n <= id2;
nDisp_wg_d0_n <= nDisp_wg_d0;
nDisp_wg_d1_n <= nDisp_wg_d1;
nDisp_wg_d2_n <= nDisp_wg_d2;
nDisp_wg_d0_ov_n <= nDisp_wg_d0_ov;
nDisp_wg_d1_ov_n <= nDisp_wg_d1_ov;
req_n <= (others=>'0');
finish_i <= '0';
prepare_params_n <= '0';
schedulingInProgress_n <= schedulingInProgress;
-- rtm_we_dx <= (others=>'0');
case st_sch is
when idle =>
if start = '1' then
st_sch_n <= read_delay;
end if;
when read_delay =>
st_sch_n <= prepare;
start_prepare_n <= '1';
if initialize_d0 = '0' then
prepare_params_n <= '1';
end if;
when prepare =>
if start_exec_i = '1' then
st_sch_n <= seekCV;
id0_n <= id0_offset;
id1_n <= id1_offset;
id2_n <= id2_offset;
end if;
when seekCV =>
if alloc_CV_indx /= N_CU then
st_sch_n <= allocateWFs;
req_n(alloc_CV_indx) <= '1';
schedulingInProgress_n(alloc_CV_indx) <= '1';
-- rtm_we_dx(alloc_CV_indx) <= '1';
if nDisp_wg_d0 = n_wg_d0_m1 then
nDisp_wg_d0_ov_n <= '1';
else
nDisp_wg_d0_ov_n <= '0';
end if;
end if;
when allocateWFs =>
st_sch_n <= checkAgain;
-- rtm_we_dx(alloc_CV_indx_ltchd) <= '1';
nDisp_wg_d1_ov_n <= '0';
if nDisp_wg_d0_ov = '1' and nDisp_wg_d1 = n_wg_d1_m1 then
nDisp_wg_d1_ov_n <= '1';
end if;
when checkAgain =>
st_sch_n <= seekCV;
-- rtm_we_dx(alloc_CV_indx_ltchd) <= '1';
if nDisp_wg_d0_ov = '1' then
nDisp_wg_d0_n <= (others => '0');
id0_n <= id0_offset;
nDisp_wg_d1_n <= nDisp_wg_d1 + 1;
id1_n <= id1 + WG_size_d1;
else
nDisp_wg_d0_n <= nDisp_wg_d0 + 1;
id0_n <= id0 + wg_size_d0;
end if;
if nDisp_wg_d1_ov = '1' then
nDisp_wg_d1_n <= (others => '0');
id1_n <= id1_offset;
nDisp_wg_d2_n <= nDisp_wg_d2 + 1;
id2_n <= id2 + WG_size_d2;
if nDisp_wg_d2 = n_wg_d2_m1 then
st_sch_n <= wait_wf_active;
end if;
end if;
when wait_wf_active =>
if schedulingInProgress = (schedulingInProgress'reverse_range=>'0') then
st_sch_n <= wait_finish;
end if;
when wait_finish =>
finish_i <= '1';
st_sch_n <= idle;
for i in 0 to N_CU-1 loop
if to_integer(unsigned(wf_active(i))) /= 0 then
st_sch_n <= wait_finish;
finish_i <= '0';
end if;
end loop;
end case;
end process;
process(clk)
variable tmp : integer range 0 to N_WF_CU := 0;
begin
if rising_edge(clk) then
if nrst = '0' or finish_i = '1' then
nDisp_wg_d0 <= (others => '0');
nDisp_wg_d1 <= (others => '0');
nDisp_wg_d2 <= (others => '0');
nDisp_wg_d0_ov <= '0';
nDisp_wg_d1_ov <= '0';
req <= (others=>'0');
cd_indx <= (others=>'0');
wf_active_slctd <= (others=>'0');
cd_indx_d0 <= (others=>'0');
n_inactive_wfs <= 0;
cd_indx_d1 <= (others=>'0');
alloc_CV_indx <= 0;
schedulingInProgress <= (others=>'0');
else
nDisp_wg_d0 <= nDisp_wg_d0_n;
nDisp_wg_d1 <= nDisp_wg_d1_n;
nDisp_wg_d2 <= nDisp_wg_d2_n;
nDisp_wg_d0_ov <= nDisp_wg_d0_ov_n;
nDisp_wg_d1_ov <= nDisp_wg_d1_ov_n;
req <= req_n;
schedulingInProgress <= schedulingInProgress_n;
for i in 0 to N_CU-1 loop
if ack(i) = '1' then
schedulingInProgress(i) <= '0';
end if;
end loop;
-- stage 0
if N_CU_W > 0 then
cd_indx <= cd_indx+1;
end if;
-- stage 1
wf_active_slctd <= wf_active(to_integer(cd_indx));
cd_indx_d0 <= cd_indx;
-- stage 2
tmp := 0;
for i in 0 to N_WF_CU-1 loop
if wf_active_slctd(i) = '0' then
tmp := tmp + 1;
end if;
end loop;
n_inactive_wfs <= tmp;
cd_indx_d1 <= cd_indx_d0;
-- stage 3
alloc_CV_indx <= N_CU;
if n_inactive_wfs > to_integer(sch_rqst_n_WFs_m1_i) and schedulingInProgress(to_integer(cd_indx_d1)) = '0' then
alloc_CV_indx <= to_integer(cd_indx_d1);
end if;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
id0 <= id0_n;
id1 <= id1_n;
id2 <= id2_n;
prepare_params <= prepare_params_n;
if start = '1' and st_sch = idle then
krnl_indx_ltchd <= krnl_indx;
end if;
if nrst = '0' then
st_sch <= idle;
start_prepare <= '0';
else
st_sch <= st_sch_n;
start_prepare <= start_prepare_n;
end if;
end if;
end process;
------------------------------------------------------------------------------------------------}}}
-- prepare FSM -------------------------------------------------------------------------------{{{
process(clk)
begin
if rising_edge(clk) then
prepare_fin <= prepare_fin_n;
prepare_fin_d0 <= prepare_fin;
start_loc_indcs <= prepare_fin and initialize_d0;
krnl_infos_we <= '0';
if to_integer(st_prepare_d0) = NEW_KRNL_DESC_N_WF then
addr_first_inst <= unsigned(krnl_sch_rdData(ADDR_FIRST_INST_OFFSET+CRAM_ADDR_W-1 downto ADDR_FIRST_INST_OFFSET));
-- addr_last_inst <= to_integer(unsigned(krnl_sch_rdData(ADDR_LAST_INST_OFFSET+CRAM_ADDR_W-1 downto ADDR_LAST_INST_OFFSET)));
sch_rqst_n_WFs_m1_i <= unsigned(krnl_sch_rdData(N_WF_OFFSET+N_WF_CU_W-1 downto N_WF_OFFSET));
end if;
if to_integer(st_prepare_d0) = NEW_KRNL_DESC_ID0_SIZE then
id0_size <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0));
krnl_infos_we <= '1';
end if;
if to_integer(st_prepare_d0) = NEW_KRNL_DESC_ID1_SIZE then
id1_size <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0));
krnl_infos_we <= '1';
end if;
if to_integer(st_prepare_d0) = NEW_KRNL_DESC_ID2_SIZE then
id2_size <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0));
krnl_infos_we <= '1';
end if;
if to_integer(st_prepare_d0) = NEW_KRNL_DESC_ID0_OFFSET then
id0_offset <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0));
end if;
if to_integer(st_prepare_d0) = NEW_KRNL_DESC_ID1_OFFSET then
id1_offset <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0));
end if;
if to_integer(st_prepare_d0) = NEW_KRNL_DESC_ID2_OFFSET then
id2_offset <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0));
end if;
if to_integer(st_prepare_d0) = NEW_KRNL_DESC_WG_SIZE then
krnl_infos_we <= '1';
wg_size_d0 <= to_integer(unsigned(krnl_sch_rdData(WG_SIZE_0_OFFSET+WG_SIZE_W downto WG_SIZE_0_OFFSET))); --WG_SIZE_W+1 bits are assigned
if to_integer(unsigned(krnl_sch_rdData(N_DIM_OFFSET+1 downto N_DIM_OFFSET))) /=0 then -- compare with nDim
wg_size_d1 <= to_integer(unsigned(krnl_sch_rdData(WG_SIZE_1_OFFSET+WG_SIZE_W downto WG_SIZE_1_OFFSET)));
else
wg_size_d1 <= 1;
end if;
if to_integer(unsigned(krnl_sch_rdData(N_DIM_OFFSET+1 downto N_DIM_OFFSET))) = 2 then -- compare with nDim
wg_size_d2 <= to_integer(unsigned(krnl_sch_rdData(WG_SIZE_2_OFFSET+WG_SIZE_W downto WG_SIZE_2_OFFSET)));
else
wg_size_d2 <= 1;
end if;
nDim <= to_integer(unsigned(krnl_sch_rdData(N_DIM_OFFSET+1 downto N_DIM_OFFSET)));
end if;
if to_integer(st_prepare_d0) = NEW_KRNL_DESC_N_WG_0 then
n_wg_d0_m1 <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0));
krnl_infos_we <= '1';
end if;
if to_integer(st_prepare_d0) = NEW_KRNL_DESC_N_WG_1 then
krnl_infos_we <= '1';
if nDim /= 0 then
n_wg_d1_m1 <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0));
else
n_wg_d1_m1 <= (others => '0');
end if;
end if;
if to_integer(st_prepare_d0) = NEW_KRNL_DESC_N_WG_2 then
krnl_infos_we <= '1';
if nDim = 2 then
n_wg_d2_m1 <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0));
else
n_wg_d2_m1 <= (others => '0');
end if;
end if;
if to_integer(st_prepare_d0) = NEW_KRNL_DESC_N_PARAMS then
nParams <= to_integer(unsigned(krnl_sch_rdData(N_PARAMS_OFFSET+N_PARAMS_W-1 downto N_PARAMS_OFFSET)));
wg_size <= unsigned(krnl_sch_rdData(WG_SIZE_OFFSET+WG_SIZE_W downto WG_SIZE_OFFSET));
end if;
if to_integer(st_prepare_d0) >= PARAMS_OFFSET then
params <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0));
krnl_infos_we <= '1';
params_wrAddr <= st_prepare_d0(N_PARAMS_W-1 downto 0);
end if;
if nrst = '0' then
st_prepare <= (others=>'0');
st_prepare_d0 <= (others=>'0');
else
st_prepare <= st_prepare_n;
st_prepare_d0 <= st_prepare;
end if;
end if;
end process;
process(st_prepare, start_prepare, nParams, prepare_params)
begin
st_prepare_n <= st_prepare;
prepare_fin_n <= '0';
case to_integer(st_prepare) is
when 0 =>
if start_prepare = '1' then
if prepare_params = '0' then
st_prepare_n <= st_prepare + 1;
else
st_prepare_n <= (st_prepare_n'high => '1', others=>'0');
end if;
end if;
when others =>
st_prepare_n <= st_prepare + 1;
if st_prepare = (2**(NEW_KRNL_DESC_W-1))+nParams-1 then
prepare_fin_n <= '1';
st_prepare_n <= (others=>'0');
else
end if;
end case;
end process;
krnl_sch_rdAddr(KRNL_SCH_ADDR_W-1 downto NEW_KRNL_DESC_W) <= std_logic_vector(to_unsigned(krnl_indx_ltchd, NEW_KRNL_INDX_W));
krnl_sch_rdAddr(NEW_KRNL_DESC_W-1 downto 0) <= std_logic_vector(st_prepare_n);
--------------------------------------------------------------------------------------------------}}}
-- init alu enable -------------------------------------------------------------------------------------------{{{
init_alu_enable: entity init_alu_en_ram generic map(
N_RD_PORTS => N_CU
)port map(
start => start_loc_indcs,
finish => alu_en_rdy,
clear_finish => start_exec_i,
wg_size => wg_size,
sch_rqst_n_WFs_m1 => sch_rqst_n_WFs_m1_i,
rdData_alu_en => rdData_alu_en,
rdAddr_alu_en => rdAddr_alu_en,
clk => clk,
nrst => nrst
);
---------------------------------------------------------------------------------------------------------}}}
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity ulpi_rx is
generic (
g_allow_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
rx_last : in std_logic;
rx_valid : in std_logic;
rx_store : in std_logic;
pid : out std_logic_vector(3 downto 0);
valid_token : out std_logic;
valid_handsh : out std_logic;
token : out std_logic_vector(10 downto 0);
valid_packet : out std_logic;
data_valid : out std_logic;
data_start : out std_logic;
data_out : out std_logic_vector(7 downto 0);
error : out std_logic );
end ulpi_rx;
architecture gideon of ulpi_rx is
type t_state is (idle, token1, token2, check_token, check_token2, resync,
data, data_check, handshake );
signal state : t_state;
signal token_i : std_logic_vector(10 downto 0) := (others => '0');
signal token_crc : std_logic_vector(4 downto 0) := (others => '0');
signal crc_in : std_logic_vector(4 downto 0);
signal crc_dvalid : std_logic;
signal crc_sync : std_logic;
signal data_crc : std_logic_vector(15 downto 0);
begin
token <= token_i;
data_out <= rx_data;
data_valid <= rx_store when state = data else '0';
process(clock)
begin
if rising_edge(clock) then
data_start <= '0';
error <= '0';
valid_token <= '0';
valid_packet <= '0';
valid_handsh <= '0';
case state is
when idle =>
if rx_valid='1' and rx_store='1' then -- wait for first byte
if rx_data(7 downto 4) = not rx_data(3 downto 0) then
pid <= rx_data(3 downto 0);
if is_handshake(rx_data(3 downto 0)) then
if rx_last = '1' then
valid_handsh <= '1';
else
state <= handshake;
end if;
elsif is_token(rx_data(3 downto 0)) then
if g_allow_token then
state <= token1;
else
error <= '1';
end if;
else
data_start <= '1';
state <= data;
end if;
else -- error in PID
error <= '1';
end if;
end if;
when handshake =>
if rx_store='1' then -- more data? error
error <= '1';
state <= resync;
elsif rx_last = '1' then
valid_handsh <= '1';
state <= idle;
end if;
when token1 =>
if rx_store='1' then
token_i(7 downto 0) <= rx_data;
state <= token2;
end if;
if rx_last='1' then -- should not occur here
error <= '1';
state <= idle; -- good enough?
end if;
when token2 =>
if rx_store='1' then
token_i(10 downto 8) <= rx_data(2 downto 0);
crc_in <= rx_data(7 downto 3);
state <= check_token;
end if;
when data =>
if rx_last='1' then
state <= data_check;
end if;
when data_check =>
if data_crc = X"4FFE" then
valid_packet <= '1';
else
error <= '1';
end if;
state <= idle;
when check_token =>
state <= check_token2; -- delay
when check_token2 =>
if crc_in = token_crc then
valid_token <= '1';
else
error <= '1';
end if;
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
else
state <= resync;
end if;
when resync =>
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
end if;
when others =>
null;
end case;
if reset = '1' then
state <= idle;
pid <= X"0";
end if;
end if;
end process;
r_token: if g_allow_token generate
i_token_crc: entity work.token_crc
port map (
clock => clock,
sync => '1',
token_in => token_i,
crc => token_crc );
end generate;
crc_sync <= '1' when state = idle else '0';
crc_dvalid <= rx_store when state = data else '0';
i_data_crc: entity work.data_crc
port map (
clock => clock,
sync => crc_sync,
valid => crc_dvalid,
data_in => rx_data,
crc => data_crc );
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity ulpi_rx is
generic (
g_allow_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
rx_last : in std_logic;
rx_valid : in std_logic;
rx_store : in std_logic;
pid : out std_logic_vector(3 downto 0);
valid_token : out std_logic;
valid_handsh : out std_logic;
token : out std_logic_vector(10 downto 0);
valid_packet : out std_logic;
data_valid : out std_logic;
data_start : out std_logic;
data_out : out std_logic_vector(7 downto 0);
error : out std_logic );
end ulpi_rx;
architecture gideon of ulpi_rx is
type t_state is (idle, token1, token2, check_token, check_token2, resync,
data, data_check, handshake );
signal state : t_state;
signal token_i : std_logic_vector(10 downto 0) := (others => '0');
signal token_crc : std_logic_vector(4 downto 0) := (others => '0');
signal crc_in : std_logic_vector(4 downto 0);
signal crc_dvalid : std_logic;
signal crc_sync : std_logic;
signal data_crc : std_logic_vector(15 downto 0);
begin
token <= token_i;
data_out <= rx_data;
data_valid <= rx_store when state = data else '0';
process(clock)
begin
if rising_edge(clock) then
data_start <= '0';
error <= '0';
valid_token <= '0';
valid_packet <= '0';
valid_handsh <= '0';
case state is
when idle =>
if rx_valid='1' and rx_store='1' then -- wait for first byte
if rx_data(7 downto 4) = not rx_data(3 downto 0) then
pid <= rx_data(3 downto 0);
if is_handshake(rx_data(3 downto 0)) then
if rx_last = '1' then
valid_handsh <= '1';
else
state <= handshake;
end if;
elsif is_token(rx_data(3 downto 0)) then
if g_allow_token then
state <= token1;
else
error <= '1';
end if;
else
data_start <= '1';
state <= data;
end if;
else -- error in PID
error <= '1';
end if;
end if;
when handshake =>
if rx_store='1' then -- more data? error
error <= '1';
state <= resync;
elsif rx_last = '1' then
valid_handsh <= '1';
state <= idle;
end if;
when token1 =>
if rx_store='1' then
token_i(7 downto 0) <= rx_data;
state <= token2;
end if;
if rx_last='1' then -- should not occur here
error <= '1';
state <= idle; -- good enough?
end if;
when token2 =>
if rx_store='1' then
token_i(10 downto 8) <= rx_data(2 downto 0);
crc_in <= rx_data(7 downto 3);
state <= check_token;
end if;
when data =>
if rx_last='1' then
state <= data_check;
end if;
when data_check =>
if data_crc = X"4FFE" then
valid_packet <= '1';
else
error <= '1';
end if;
state <= idle;
when check_token =>
state <= check_token2; -- delay
when check_token2 =>
if crc_in = token_crc then
valid_token <= '1';
else
error <= '1';
end if;
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
else
state <= resync;
end if;
when resync =>
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
end if;
when others =>
null;
end case;
if reset = '1' then
state <= idle;
pid <= X"0";
end if;
end if;
end process;
r_token: if g_allow_token generate
i_token_crc: entity work.token_crc
port map (
clock => clock,
sync => '1',
token_in => token_i,
crc => token_crc );
end generate;
crc_sync <= '1' when state = idle else '0';
crc_dvalid <= rx_store when state = data else '0';
i_data_crc: entity work.data_crc
port map (
clock => clock,
sync => crc_sync,
valid => crc_dvalid,
data_in => rx_data,
crc => data_crc );
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity ulpi_rx is
generic (
g_allow_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
rx_last : in std_logic;
rx_valid : in std_logic;
rx_store : in std_logic;
pid : out std_logic_vector(3 downto 0);
valid_token : out std_logic;
valid_handsh : out std_logic;
token : out std_logic_vector(10 downto 0);
valid_packet : out std_logic;
data_valid : out std_logic;
data_start : out std_logic;
data_out : out std_logic_vector(7 downto 0);
error : out std_logic );
end ulpi_rx;
architecture gideon of ulpi_rx is
type t_state is (idle, token1, token2, check_token, check_token2, resync,
data, data_check, handshake );
signal state : t_state;
signal token_i : std_logic_vector(10 downto 0) := (others => '0');
signal token_crc : std_logic_vector(4 downto 0) := (others => '0');
signal crc_in : std_logic_vector(4 downto 0);
signal crc_dvalid : std_logic;
signal crc_sync : std_logic;
signal data_crc : std_logic_vector(15 downto 0);
begin
token <= token_i;
data_out <= rx_data;
data_valid <= rx_store when state = data else '0';
process(clock)
begin
if rising_edge(clock) then
data_start <= '0';
error <= '0';
valid_token <= '0';
valid_packet <= '0';
valid_handsh <= '0';
case state is
when idle =>
if rx_valid='1' and rx_store='1' then -- wait for first byte
if rx_data(7 downto 4) = not rx_data(3 downto 0) then
pid <= rx_data(3 downto 0);
if is_handshake(rx_data(3 downto 0)) then
if rx_last = '1' then
valid_handsh <= '1';
else
state <= handshake;
end if;
elsif is_token(rx_data(3 downto 0)) then
if g_allow_token then
state <= token1;
else
error <= '1';
end if;
else
data_start <= '1';
state <= data;
end if;
else -- error in PID
error <= '1';
end if;
end if;
when handshake =>
if rx_store='1' then -- more data? error
error <= '1';
state <= resync;
elsif rx_last = '1' then
valid_handsh <= '1';
state <= idle;
end if;
when token1 =>
if rx_store='1' then
token_i(7 downto 0) <= rx_data;
state <= token2;
end if;
if rx_last='1' then -- should not occur here
error <= '1';
state <= idle; -- good enough?
end if;
when token2 =>
if rx_store='1' then
token_i(10 downto 8) <= rx_data(2 downto 0);
crc_in <= rx_data(7 downto 3);
state <= check_token;
end if;
when data =>
if rx_last='1' then
state <= data_check;
end if;
when data_check =>
if data_crc = X"4FFE" then
valid_packet <= '1';
else
error <= '1';
end if;
state <= idle;
when check_token =>
state <= check_token2; -- delay
when check_token2 =>
if crc_in = token_crc then
valid_token <= '1';
else
error <= '1';
end if;
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
else
state <= resync;
end if;
when resync =>
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
end if;
when others =>
null;
end case;
if reset = '1' then
state <= idle;
pid <= X"0";
end if;
end if;
end process;
r_token: if g_allow_token generate
i_token_crc: entity work.token_crc
port map (
clock => clock,
sync => '1',
token_in => token_i,
crc => token_crc );
end generate;
crc_sync <= '1' when state = idle else '0';
crc_dvalid <= rx_store when state = data else '0';
i_data_crc: entity work.data_crc
port map (
clock => clock,
sync => crc_sync,
valid => crc_dvalid,
data_in => rx_data,
crc => data_crc );
end gideon;
|
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: filtering_algorithm_wrapper - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity filtering_algorithm_wrapper is
port (
clk : in std_logic;
sclr : in std_logic;
start : in std_logic;
select_input : in std_logic_vector(1 downto 0);
select_par : in std_logic_vector(integer(ceil(log2(real(PARALLEL_UNITS))))-1 downto 0);
-- initial parameters
k : in unsigned(INDEX_BITWIDTH-1 downto 0);
root_address : in std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
-- init node and centre memory
wr_init_nd : in std_logic;
wr_data_init : in std_logic_vector(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 downto 0);
wr_address_init : in std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
-- outputs
valid : out std_logic;
clusters_out : out data_type;
distortion_out : out coord_type_ext;
-- processing done
rdy : out std_logic
);
end filtering_algorithm_wrapper;
architecture Behavioral of filtering_algorithm_wrapper is
component filtering_alogrithm_top is
port (
clk : in std_logic;
sclr : in std_logic;
start : in std_logic;
-- initial parameters
k : in centre_index_type;
root_address : in par_node_address_type;
-- init node and centre memory
wr_init_cent : in std_logic;
wr_centre_list_address_init : in centre_list_address_type;
wr_centre_list_data_init : in centre_index_type;
wr_init_node : in std_logic_vector(0 to PARALLEL_UNITS-1);
wr_node_address_init : in par_node_address_type;
wr_node_data_init : in par_node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
-- outputs
valid : out std_logic;
clusters_out : out data_type;
distortion_out : out coord_type_ext;
-- processing done
rdy : out std_logic
);
end component;
signal tmp_clk : std_logic;
signal reg_sclr : std_logic;
signal reg_start : std_logic;
-- initial parameters
signal reg_k : centre_index_type;
signal reg_root_address : node_address_type;
signal tmp_root_address : par_node_address_type;
-- init node and centre memory
signal reg_wr_init_cent : std_logic;
signal reg_wr_centre_list_address_init : centre_list_address_type;
signal reg_wr_centre_list_data_init : centre_index_type;
signal reg_wr_init_node : std_logic_vector(0 to PARALLEL_UNITS-1);
signal reg_wr_node_address_init : node_address_type;
signal tmp_wr_node_address_init : par_node_address_type;
signal reg_wr_node_data_init : node_data_type;
signal tmp_wr_node_data_init : par_node_data_type;
signal reg_wr_init_pos : std_logic;
signal reg_wr_centre_list_pos_address_init : centre_index_type;
signal reg_wr_centre_list_pos_data_init : data_type;
-- outputs
signal tmp_valid : std_logic;
signal reg_valid : std_logic;
signal tmp_clusters_out : data_type;
signal reg_clusters_out : data_type;
signal tmp_distortion_out : coord_type_ext;
signal reg_distortion_out : coord_type_ext;
-- processing done
signal tmp_rdy : std_logic;
signal reg_rdy : std_logic;
begin
ClkBuffer: IBUFG
port map (
I => clk,
O => tmp_clk
);
input_reg : process(tmp_clk)
begin
if rising_edge(tmp_clk) then
if select_input = "00" then
reg_wr_init_cent <= wr_init_nd;
reg_wr_init_pos <= '0';
elsif select_input = "01" then
reg_wr_init_cent <= '0';
reg_wr_init_pos <= '0';
else
reg_wr_init_cent <= '0';
reg_wr_init_pos <= wr_init_nd;
end if;
for I in 0 to PARALLEL_UNITS-1 loop
if select_par = std_logic_vector(to_unsigned(I,integer(ceil(log2(real(PARALLEL_UNITS)))))) then
if select_input = "00" then
reg_wr_init_node(I) <= '0';
elsif select_input = "01" then
reg_wr_init_node(I) <= wr_init_nd;
else
reg_wr_init_node(I) <= '0';
end if;
else
reg_wr_init_node(I) <= '0';
end if;
end loop;
reg_wr_centre_list_address_init <= wr_address_init(CNTR_POINTER_BITWIDTH-1 downto 0);
reg_wr_centre_list_data_init <= unsigned(wr_data_init(INDEX_BITWIDTH-1 downto 0));
reg_wr_node_address_init <= wr_address_init(NODE_POINTER_BITWIDTH-1 downto 0);
reg_wr_node_data_init <= stdlogic_2_nodedata(wr_data_init);
reg_wr_centre_list_pos_address_init <= unsigned(wr_address_init(INDEX_BITWIDTH-1 downto 0));
reg_wr_centre_list_pos_data_init <= stdlogic_2_datapoint(wr_data_init(D*COORD_BITWIDTH-1 downto 0));
reg_sclr <= sclr;
reg_start <= start;
reg_k <= k;
reg_root_address <= root_address;
end if;
end process input_reg;
-- parallel units will be initialiased one after the other (a controlled by reg_wr_init_node)
G0_PAR : for I in 0 to PARALLEL_UNITS-1 generate
tmp_wr_node_address_init(I) <= reg_wr_node_address_init;
tmp_wr_node_data_init(I) <= reg_wr_node_data_init;
tmp_root_address(I) <= reg_root_address;
end generate G0_PAR;
filtering_alogrithm_top_inst : filtering_alogrithm_top
port map(
clk => tmp_clk,
sclr => reg_sclr,
start => reg_start,
-- initial parameters
k => reg_k,
root_address => tmp_root_address,
-- init node and centre memory
wr_init_cent => reg_wr_init_cent,
wr_centre_list_address_init => reg_wr_centre_list_address_init,
wr_centre_list_data_init => reg_wr_centre_list_data_init,
wr_init_node => reg_wr_init_node,
wr_node_address_init => tmp_wr_node_address_init,
wr_node_data_init => tmp_wr_node_data_init,
wr_init_pos => reg_wr_init_pos,
wr_centre_list_pos_address_init => reg_wr_centre_list_pos_address_init,
wr_centre_list_pos_data_init => reg_wr_centre_list_pos_data_init,
-- outputs
valid => tmp_valid,
clusters_out => tmp_clusters_out,
distortion_out => tmp_distortion_out,
-- processing done
rdy => tmp_rdy
);
output_reg : process(tmp_clk)
begin
if rising_edge(tmp_clk) then
reg_valid <= tmp_valid;
reg_clusters_out <= tmp_clusters_out;
reg_distortion_out <= tmp_distortion_out;
reg_rdy <= tmp_rdy;
end if;
end process output_reg;
valid <= reg_valid;
clusters_out <= reg_clusters_out;
distortion_out <= reg_distortion_out;
rdy <= reg_rdy;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc445.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00445ent IS
END c03s02b01x01p19n01i00445ent;
ARCHITECTURE c03s02b01x01p19n01i00445arch OF c03s02b01x01p19n01i00445ent IS
type real_vector is array (natural range <>) of real;
subtype real_vector_st is real_vector(0 to 15);
constant C1 : real := 4.0;
constant C70 : real_vector_st :=(others => C1);
function complex_scalar(s : real_vector_st) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return real_vector_st is
begin
return C70;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : real_vector_st;
signal S2 : real_vector_st;
signal S3 : real_vector_st := C70;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C70) and (S2 = C70))
report "***PASSED TEST: c03s02b01x01p19n01i00445"
severity NOTE;
assert ((S1 = C70) and (S2 = C70))
report "***FAILED TEST: c03s02b01x01p19n01i00445 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00445arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc445.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00445ent IS
END c03s02b01x01p19n01i00445ent;
ARCHITECTURE c03s02b01x01p19n01i00445arch OF c03s02b01x01p19n01i00445ent IS
type real_vector is array (natural range <>) of real;
subtype real_vector_st is real_vector(0 to 15);
constant C1 : real := 4.0;
constant C70 : real_vector_st :=(others => C1);
function complex_scalar(s : real_vector_st) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return real_vector_st is
begin
return C70;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : real_vector_st;
signal S2 : real_vector_st;
signal S3 : real_vector_st := C70;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C70) and (S2 = C70))
report "***PASSED TEST: c03s02b01x01p19n01i00445"
severity NOTE;
assert ((S1 = C70) and (S2 = C70))
report "***FAILED TEST: c03s02b01x01p19n01i00445 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00445arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc445.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00445ent IS
END c03s02b01x01p19n01i00445ent;
ARCHITECTURE c03s02b01x01p19n01i00445arch OF c03s02b01x01p19n01i00445ent IS
type real_vector is array (natural range <>) of real;
subtype real_vector_st is real_vector(0 to 15);
constant C1 : real := 4.0;
constant C70 : real_vector_st :=(others => C1);
function complex_scalar(s : real_vector_st) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return real_vector_st is
begin
return C70;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : real_vector_st;
signal S2 : real_vector_st;
signal S3 : real_vector_st := C70;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C70) and (S2 = C70))
report "***PASSED TEST: c03s02b01x01p19n01i00445"
severity NOTE;
assert ((S1 = C70) and (S2 = C70))
report "***FAILED TEST: c03s02b01x01p19n01i00445 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00445arch;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:19:47 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_processing_system7_0_0/led_controller_design_processing_system7_0_0_stub.vhdl
-- Design : led_controller_design_processing_system7_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity led_controller_design_processing_system7_0_0 is
Port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end led_controller_design_processing_system7_0_0;
architecture stub of led_controller_design_processing_system7_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2017.3";
begin
end;
|
-----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : UART-Model for Simulation
-- Last update : 28.11.2013
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity uart_model is
generic (
SYSTEM_CYCLE_TIME : time := 20 ns; -- 50 MHz
-- file with data to be send to fpga
FILE_NAME_COMMAND : string := "command.txt";
-- file for dump of data, received by pc
FILE_NAME_DUMP : string := "dump.txt";
-- communication speed for uart-link
BAUD_RATE : natural := 9600;
SIMULATION : boolean := true
);
port (
-- global signals
end_simulation : in std_ulogic;
-- uart-pins (pc side)
rx : in std_ulogic;
tx : out std_ulogic
);
end uart_model;
architecture sim of uart_model is
constant MAX_NO_OF_BYTES : natural := 128;
constant UART_BIT_TIME : time := 1 us * 1000000/BAUD_RATE;
file file_command : text open read_mode is FILE_NAME_COMMAND;
file file_dump : text open write_mode is FILE_NAME_DUMP;
type bytelist_t is array (0 to MAX_NO_OF_BYTES-1) of std_ulogic_vector(7 downto 0);
begin
-- send data to fpga
uart_send : process
variable commandlist : bytelist_t;
variable active_line : line;
variable neol : boolean := false;
variable data_value : integer;
variable cnt : natural := 0;
begin
-- set line to "no data"
tx <= '1';
-- preload list with undefined
commandlist := (others => (others => 'U'));
-- read preload file
while not endfile(file_command) loop
-- read line
readline(file_command, active_line);
-- loop until end of line
loop
read(active_line, data_value, neol);
exit when not neol;
-- write command to array
commandlist(cnt) := std_ulogic_vector(to_signed(data_value, 8));
-- increment counter
cnt := cnt + 1;
end loop;
end loop;
file_close(file_command);
-- send data to fpga
for i in 0 to MAX_NO_OF_BYTES-1 loop
-- check if byte is valid, else stop
if commandlist(i)(0) /= 'U' then
-- uart send procedure
-- wait some cycles before start
wait for 10*SYSTEM_CYCLE_TIME;
-- start bit
tx <= '0';
if SIMULATION = false then wait for UART_BIT_TIME;
else wait for SYSTEM_CYCLE_TIME*16;
end if;
-- loop over data
for j in 0 to 7 loop
tx <= commandlist(i)(j);
if SIMULATION = false then wait for UART_BIT_TIME;
else wait for SYSTEM_CYCLE_TIME*16;
end if;
end loop;
-- stop bit
tx <= '1';
if SIMULATION = false then wait for UART_BIT_TIME;
else wait for SYSTEM_CYCLE_TIME*16;
end if;
write(active_line, string'("[UART] Sent "));
write(active_line, to_integer(unsigned(commandlist(i))));
write(active_line, string'(" ("));
write(active_line, to_bitvector(commandlist(i)));
write(active_line, string'(") to FPGA."));
writeline(output, active_line);
-- wait for some cycles before continuing
wait for 10*SYSTEM_CYCLE_TIME;
end if;
end loop;
-- wait forever
wait;
end process uart_send;
-- receive data from fpga
uart_receive : process
variable receivelist : bytelist_t;
variable cnt : integer;
variable active_line : line;
begin
-- initialize receive buffer
receivelist := (others => (others => 'U'));
cnt := 0;
-- always detect in the centre of a bit
if SIMULATION = false then wait for UART_BIT_TIME*0.5;
else wait for SYSTEM_CYCLE_TIME*16*0.5;
end if;
loop
-- stop when simulation is ended
exit when end_simulation = '1';
-- check if space in receive buffer is available, else break
exit when cnt = MAX_NO_OF_BYTES;
-- startbit detected
if rx = '0' then
--wait for first data bit
if SIMULATION = false then wait for UART_BIT_TIME;
else wait for SYSTEM_CYCLE_TIME*16;
end if;
-- receive 8 bit
for i in 0 to 7 loop
receivelist(cnt)(i) := rx;
if SIMULATION = false then wait for UART_BIT_TIME;
else wait for SYSTEM_CYCLE_TIME*16;
end if;
end loop;
-- receive stop bit
if rx /= '1' then
-- stopbit not received!
write(active_line, string'("[UART] Expected Stop-Bit!"));
writeline(output, active_line);
else
write(active_line, string'("[UART] Received "));
write(active_line, to_integer(unsigned(receivelist(cnt))));
write(active_line, string'(" ("));
write(active_line, to_bitvector(receivelist(cnt)));
write(active_line, string'(") from FPGA."));
writeline(output, active_line);
end if;
-- inc counter
cnt := cnt + 1;
else
-- wait a cycle
wait for SYSTEM_CYCLE_TIME;
end if;
end loop;
-- loop over max number of bytes
for i in 0 to MAX_NO_OF_BYTES-1 loop
-- check if recieved byte is valid, else stop
if receivelist(i)(0) /= 'U' then
-- add value to line (will result in one value per line)
write(active_line, to_integer(unsigned(receivelist(i))));
-- write line to file
writeline(file_dump, active_line);
end if;
end loop;
file_close(file_dump);
-- wait forever
wait;
end process uart_receive;
end sim; |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF1_1.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_1
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/RADIX22FFT_SDNF1_1
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_1 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_1_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_9_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_9_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_1_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_1;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_1 IS
-- Signals
SIGNAL twdlXdin_1_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_1_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_9_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_9_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_1_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_1_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_2_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_2_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
twdlXdin_1_re_signed <= signed(twdlXdin_1_re);
twdlXdin_1_im_signed <= signed(twdlXdin_1_im);
twdlXdin_9_re_signed <= signed(twdlXdin_9_re);
twdlXdin_9_im_signed <= signed(twdlXdin_9_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_1_re_signed,
twdlXdin_1_im_signed, twdlXdin_9_re_signed, twdlXdin_9_im_signed,
twdlXdin_1_vld)
VARIABLE add_cast : signed(16 DOWNTO 0);
VARIABLE add_cast_0 : signed(16 DOWNTO 0);
VARIABLE sra_temp : signed(16 DOWNTO 0);
VARIABLE sub_cast : signed(16 DOWNTO 0);
VARIABLE sub_cast_0 : signed(16 DOWNTO 0);
VARIABLE sra_temp_0 : signed(16 DOWNTO 0);
VARIABLE add_cast_1 : signed(16 DOWNTO 0);
VARIABLE add_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp_2 : signed(16 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
add_cast := resize(twdlXdin_1_re_signed, 17);
add_cast_0 := resize(twdlXdin_9_re_signed, 17);
Radix22ButterflyG1_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(twdlXdin_1_re_signed, 17);
sub_cast_0 := resize(twdlXdin_9_re_signed, 17);
Radix22ButterflyG1_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_1 := resize(twdlXdin_1_im_signed, 17);
add_cast_2 := resize(twdlXdin_9_im_signed, 17);
Radix22ButterflyG1_NF_btf1_im_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(twdlXdin_1_im_signed, 17);
sub_cast_2 := resize(twdlXdin_9_im_signed, 17);
Radix22ButterflyG1_NF_btf2_im_reg_next <= sub_cast_1 - sub_cast_2;
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_re_reg, 1);
dout_1_re_tmp <= sra_temp(15 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_im_reg, 1);
dout_1_im_tmp <= sra_temp_0(15 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_re_reg, 1);
dout_2_re_tmp <= sra_temp_1(15 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_im_reg, 1);
dout_2_im_tmp <= sra_temp_2(15 DOWNTO 0);
dout_1_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_1_re <= std_logic_vector(dout_1_re_tmp);
dout_1_im <= std_logic_vector(dout_1_im_tmp);
dout_2_re <= std_logic_vector(dout_2_re_tmp);
dout_2_im <= std_logic_vector(dout_2_im_tmp);
END rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:41:32 02/12/2014
-- Design Name:
-- Module Name: full_adder_1_bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity full_adder_1_bit is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
Sum : out STD_LOGIC);
end full_adder_1_bit;
architecture Behavioral of full_adder_1_bit is
begin
Sum <= (B XOR Cin) XOR A;
Cout <= ((B AND Cin) OR (B AND A) OR (A AND Cin));
end Behavioral;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_avalon_mm;
use bitvis_vip_avalon_mm.transaction_pkg.all;
use bitvis_vip_avalon_mm.vvc_methods_pkg.all;
use bitvis_vip_avalon_mm.td_vvc_framework_common_methods_pkg.all;
use bitvis_vip_avalon_mm.avalon_mm_bfm_pkg.t_avalon_mm_if;
use bitvis_vip_avalon_mm.avalon_mm_bfm_pkg.t_avalon_mm_bfm_config;
use bitvis_vip_avalon_mm.avalon_mm_bfm_pkg.C_AVALON_MM_BFM_CONFIG_DEFAULT;
end context; |
library ieee;
use ieee.std_logic_1164.all;
entity key_permutation_2 is
port( left_half: in std_logic_vector(0 to 27);
right_half: in std_logic_vector(0 to 27);
permuted_key: out std_logic_vector(0 to 47));
end key_permutation_2;
architecture behavior of key_permutation_2 is
signal merged_halfs: std_logic_vector(0 to 55);
begin
merged_halfs(0 to 27)<=left_half;
merged_halfs(28 to 55)<=right_half;
permuted_key(0)<=merged_halfs(13);
permuted_key(1)<=merged_halfs(16);
permuted_key(2)<=merged_halfs(10);
permuted_key(3)<=merged_halfs(23);
permuted_key(4)<=merged_halfs(0);
permuted_key(5)<=merged_halfs(4);
permuted_key(6)<=merged_halfs(2);
permuted_key(7)<=merged_halfs(27);
permuted_key(8)<=merged_halfs(14);
permuted_key(9)<=merged_halfs(5);
permuted_key(10)<=merged_halfs(20);
permuted_key(11)<=merged_halfs(9);
permuted_key(12)<=merged_halfs(22);
permuted_key(13)<=merged_halfs(18);
permuted_key(14)<=merged_halfs(11);
permuted_key(15)<=merged_halfs(3);
permuted_key(16)<=merged_halfs(25);
permuted_key(17)<=merged_halfs(7);
permuted_key(18)<=merged_halfs(15);
permuted_key(19)<=merged_halfs(6);
permuted_key(20)<=merged_halfs(26);
permuted_key(21)<=merged_halfs(19);
permuted_key(22)<=merged_halfs(12);
permuted_key(23)<=merged_halfs(1);
permuted_key(24)<=merged_halfs(40);
permuted_key(25)<=merged_halfs(51);
permuted_key(26)<=merged_halfs(30);
permuted_key(27)<=merged_halfs(36);
permuted_key(28)<=merged_halfs(46);
permuted_key(29)<=merged_halfs(54);
permuted_key(30)<=merged_halfs(29);
permuted_key(31)<=merged_halfs(39);
permuted_key(32)<=merged_halfs(50);
permuted_key(33)<=merged_halfs(44);
permuted_key(34)<=merged_halfs(32);
permuted_key(35)<=merged_halfs(47);
permuted_key(36)<=merged_halfs(43);
permuted_key(37)<=merged_halfs(48);
permuted_key(38)<=merged_halfs(38);
permuted_key(39)<=merged_halfs(55);
permuted_key(40)<=merged_halfs(33);
permuted_key(41)<=merged_halfs(52);
permuted_key(42)<=merged_halfs(45);
permuted_key(43)<=merged_halfs(41);
permuted_key(44)<=merged_halfs(49);
permuted_key(45)<=merged_halfs(35);
permuted_key(46)<=merged_halfs(28);
permuted_key(47)<=merged_halfs(31);
end behavior;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v8_0 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
entity test is
end test;
architecture arch of test is
type natural_vec is array (natural range <>) of natural;
type natural_vec_ptr is access natural_vec;
procedure bad is
variable v : natural_vec_ptr;
begin
v := new natural_vec_ptr(0 to 9); -- Should give an error, gives assertion failed
v := new natural_vec(0 to 9); -- The correct syntax for the above (which works fine)
end procedure;
begin
end arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2828.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity MAP is
end MAP;
ENTITY c13s09b00x00p98n01i02828ent IS
END c13s09b00x00p98n01i02828ent;
ARCHITECTURE c13s09b00x00p98n01i02828arch OF c13s09b00x00p98n01i02828ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p98n01i02828 - Reserved word MAP can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p98n01i02828arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2828.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity MAP is
end MAP;
ENTITY c13s09b00x00p98n01i02828ent IS
END c13s09b00x00p98n01i02828ent;
ARCHITECTURE c13s09b00x00p98n01i02828arch OF c13s09b00x00p98n01i02828ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p98n01i02828 - Reserved word MAP can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p98n01i02828arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2828.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity MAP is
end MAP;
ENTITY c13s09b00x00p98n01i02828ent IS
END c13s09b00x00p98n01i02828ent;
ARCHITECTURE c13s09b00x00p98n01i02828arch OF c13s09b00x00p98n01i02828ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p98n01i02828 - Reserved word MAP can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p98n01i02828arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: netcomp
-- File: netcomp.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler
-- Description: Declaration of netlists components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use work.gencomp.all;
package netcomp is
---------------------------------------------------------------------------
-- netlists ---------------------------------------------------------------
---------------------------------------------------------------------------
component grusbhc_net is
generic (
tech : integer := 0;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
memtech : integer range 0 to NTECH := DEFMEMTECH;
memsel : integer := 0;
syncprst : integer range 0 to 1 := 0;
sysfreq : integer := 65000;
pcidev : integer range 0 to 1 := 0;
debug : integer := 0;
debug_abits : integer := 12);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- grusb_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
suspendm : out std_ulogic;
dbus16_8 : out std_ulogic;
dppulldown : out std_ulogic;
dmpulldown : out std_ulogic;
idpullup : out std_ulogic;
dischrgvbus : out std_ulogic;
chrgvbus : out std_ulogic;
txbitstuffenable : out std_ulogic;
txbitstuffenableh : out std_ulogic;
fslsserialmode : out std_ulogic;
txenablen : out std_ulogic;
txdat : out std_ulogic;
txse0 : out std_ulogic;
-- grusb_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
urstdrive : in std_logic_vector((nports-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic;
-- scan signals
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic;
-- debug signals
debug_raddr : out std_logic_vector(15 downto 0);
debug_waddr : out std_logic_vector(15 downto 0);
debug_wdata : out std_logic_vector(31 downto 0);
debug_we : out std_ulogic;
debug_rdata : in std_logic_vector(31 downto 0));
end component;
component grspwc_net
generic(
tech : integer := 0;
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspwc2_net is
generic(
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
tech : integer;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0;
interruptdist : integer range 0 to 32 := 0;
intscalerbits : integer range 0 to 31 := 0;
intisrtimerbits : integer range 0 to 31 := 0;
intiatimerbits : integer range 0 to 31 := 0;
intctimerbits : integer range 0 to 31 := 0;
tickinasync : integer range 0 to 1 := 0;
pnp : integer range 0 to 2 := 0;
pnpvendid : integer range 0 to 16#FFFF# := 0;
pnpprodid : integer range 0 to 16#FFFF# := 0;
pnpmajorver : integer range 0 to 16#FF# := 0;
pnpminorver : integer range 0 to 16#FF# := 0;
pnppatch : integer range 0 to 16#FF# := 0;
num_txdesc : integer range 64 to 512 := 64;
num_rxdesc : integer range 128 to 1024 := 128
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk : in std_logic_vector(1 downto 0);
txclk : in std_ulogic;
txclkn : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--time iface
tickin : in std_logic;
tickinraw : in std_logic;
timein : in std_logic_vector(7 downto 0);
tickindone : out std_logic;
tickout : out std_logic;
tickoutraw : out std_logic;
timeout : out std_logic_vector(7 downto 0);
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(5 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(5 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(5 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(5 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(9 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(9 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic;
testrst : in std_logic;
testen : in std_logic;
rxdav : out std_logic;
rxdataout : out std_logic_vector(8 downto 0);
loopback : out std_logic;
-- interrupt dist. default values
intpreload : in std_logic_vector(30 downto 0);
inttreload : in std_logic_vector(30 downto 0);
intiareload : in std_logic_vector(30 downto 0);
intcreload : in std_logic_vector(30 downto 0);
irqtxdefault : in std_logic_vector(4 downto 0);
--SpW PnP enable
pnpen : in std_ulogic;
pnpuvendid : in std_logic_vector(15 downto 0);
pnpuprodid : in std_logic_vector(15 downto 0);
pnpusn : in std_logic_vector(31 downto 0)
);
end component;
component grlfpw_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component leon3ft_net
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0
);
port (
clk : in std_ulogic;
gclk : in std_ulogic;
rstn : in std_ulogic;
ahbix : in ahb_mst_in_type;
ahbox : out ahb_mst_out_type;
ahbsix : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss: out std_ulogic;
dbgo_istat_tmiss: out std_ulogic;
dbgo_istat_chold: out std_ulogic;
dbgo_istat_mhold: out std_ulogic;
dbgo_dstat_cmiss: out std_ulogic;
dbgo_dstat_tmiss: out std_ulogic;
dbgo_dstat_chold: out std_ulogic;
dbgo_dstat_mhold: out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic
);
end component;
component ssrctrl_net
generic (
tech: Integer := 0;
bus16: Integer := 1);
port (
rst: in Std_Logic;
clk: in Std_Logic;
n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);
n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hwrite: in Std_Logic;
n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);
n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hready: in Std_Logic;
n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hmastlock:in Std_Logic;
n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);
n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);
n_ahbso_hready: out Std_Logic;
n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);
n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);
n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);
n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);
n_apbi_psel: in Std_Logic_Vector(0 to 15);
n_apbi_penable: in Std_Logic;
n_apbi_paddr: in Std_Logic_Vector(31 downto 0);
n_apbi_pwrite: in Std_Logic;
n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);
n_apbi_pirq: in Std_Logic_Vector(31 downto 0);
n_apbo_prdata: out Std_Logic_Vector(31 downto 0);
n_apbo_pirq: out Std_Logic_Vector(31 downto 0);
n_sri_data: in Std_Logic_Vector(31 downto 0);
n_sri_brdyn: in Std_Logic;
n_sri_bexcn: in Std_Logic;
n_sri_writen: in Std_Logic;
n_sri_wrn: in Std_Logic_Vector(3 downto 0);
n_sri_bwidth: in Std_Logic_Vector(1 downto 0);
n_sri_sd: in Std_Logic_Vector(63 downto 0);
n_sri_cb: in Std_Logic_Vector(7 downto 0);
n_sri_scb: in Std_Logic_Vector(7 downto 0);
n_sri_edac: in Std_Logic;
n_sro_address: out Std_Logic_Vector(31 downto 0);
n_sro_data: out Std_Logic_Vector(31 downto 0);
n_sro_sddata: out Std_Logic_Vector(63 downto 0);
n_sro_ramsn: out Std_Logic_Vector(7 downto 0);
n_sro_ramoen: out Std_Logic_Vector(7 downto 0);
n_sro_ramn: out Std_Logic;
n_sro_romn: out Std_Logic;
n_sro_mben: out Std_Logic_Vector(3 downto 0);
n_sro_iosn: out Std_Logic;
n_sro_romsn: out Std_Logic_Vector(7 downto 0);
n_sro_oen: out Std_Logic;
n_sro_writen: out Std_Logic;
n_sro_wrn: out Std_Logic_Vector(3 downto 0);
n_sro_bdrive: out Std_Logic_Vector(3 downto 0);
n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);
n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);
n_sro_read: out Std_Logic;
n_sro_sa: out Std_Logic_Vector(14 downto 0);
n_sro_cb: out Std_Logic_Vector(7 downto 0);
n_sro_scb: out Std_Logic_Vector(7 downto 0);
n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_ce: out Std_Logic);
end component;
component ftsrctrl_net
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
rombanks : integer range 1 to 8 := 1;
rombanksz : integer range 0 to 15 := 15;
rombankszdef : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 0;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0;
prom8en : integer := 0;
netlist : integer := 0;
tech : integer := 0
);
port (
rst: in Std_ULogic;
clk: in Std_ULogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri_data: in Std_Logic_Vector(31 downto 0); -- Data bus address
sri_brdyn: in Std_Logic;
sri_bexcn: in Std_Logic;
sri_writen: in Std_Logic;
sri_wrn: in Std_Logic_Vector(3 downto 0);
sri_bwidth: in Std_Logic_Vector(1 downto 0);
sri_sd: in Std_Logic_Vector(63 downto 0);
sri_cb: in Std_Logic_Vector(15 downto 0);
sri_scb: in Std_Logic_Vector(15 downto 0);
sri_edac: in Std_Logic;
sro_address: out Std_Logic_Vector(31 downto 0);
sro_data: out Std_Logic_Vector(31 downto 0);
sro_sddata: out Std_Logic_Vector(63 downto 0);
sro_ramsn: out Std_Logic_Vector(7 downto 0);
sro_ramoen: out Std_Logic_Vector(7 downto 0);
sro_ramn: out Std_ULogic;
sro_romn: out Std_ULogic;
sro_mben: out Std_Logic_Vector(3 downto 0);
sro_iosn: out Std_Logic;
sro_romsn: out Std_Logic_Vector(7 downto 0);
sro_oen: out Std_Logic;
sro_writen: out Std_Logic;
sro_wrn: out Std_Logic_Vector(3 downto 0);
sro_bdrive: out Std_Logic_Vector(3 downto 0);
sro_vbdrive: out Std_Logic_Vector(31 downto 0); --vector bus drive
sro_svbdrive: out Std_Logic_Vector(63 downto 0); --vector bus drive sdram
sro_read: out Std_Logic;
sro_sa: out Std_Logic_Vector(14 downto 0);
sro_cb: out Std_Logic_Vector(15 downto 0);
sro_scb: out Std_Logic_Vector(15 downto 0);
sro_vcdrive: out Std_Logic_Vector(15 downto 0); --vector bus drive cb
sro_svcdrive: out Std_Logic_Vector(15 downto 0); --vector bus drive cb sdram
sro_ce: out Std_ULogic;
sdo_sdcke: out Std_Logic_Vector( 1 downto 0); -- clk en
sdo_sdcsn: out Std_Logic_Vector( 1 downto 0); -- chip sel
sdo_sdwen: out Std_ULogic; -- write en
sdo_rasn: out Std_ULogic; -- row addr stb
sdo_casn: out Std_ULogic; -- col addr stb
sdo_dqm: out Std_Logic_Vector(15 downto 0); -- data i/o mask
sdo_bdrive: out Std_ULogic; -- bus drive
sdo_qdrive: out Std_ULogic; -- bus drive
sdo_vbdrive: out Std_Logic_Vector(31 downto 0); -- vector bus drive
sdo_address: out Std_Logic_Vector(16 downto 2); -- address out
sdo_data: out Std_Logic_Vector(127 downto 0); -- data out
sdo_cb: out Std_Logic_Vector(15 downto 0);
sdo_ce: out Std_ULogic;
sdo_ba: out Std_Logic_Vector(2 downto 0)); -- bank address
end component;
component grlfpw4_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0;
wrt : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(63 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(63 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw4_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(63 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(63 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component spictrl_net
generic (
tech : integer range 0 to NTECH := 0;
fdepth : integer range 1 to 7 := 1;
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1;
oepol : integer range 0 to 1 := 0;
odmode : integer range 0 to 1 := 0;
automode : integer range 0 to 1 := 0;
acntbits : integer range 1 to 32 := 32;
aslvsel : integer range 0 to 1 := 0;
twen : integer range 0 to 1 := 1;
maxwlen : integer range 0 to 15 := 0;
automask0 : integer := 0;
automask1 : integer := 0;
automask2 : integer := 0;
automask3 : integer := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0));
end component;
component leon4_net
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic;
gclk : in std_ulogic;
hclken : in std_ulogic;
rstn : in std_ulogic;
ahbix : in ahb_mst_in_type;
ahbox : out ahb_mst_out_type;
ahbsix : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqi_rstvec: in std_logic_vector(31 downto 12);
irqi_iact: in std_ulogic;
irqi_index: in std_logic_vector(3 downto 0);
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
irqo_idle: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss: out std_ulogic;
dbgo_istat_tmiss: out std_ulogic;
dbgo_istat_chold: out std_ulogic;
dbgo_istat_mhold: out std_ulogic;
dbgo_dstat_cmiss: out std_ulogic;
dbgo_dstat_tmiss: out std_ulogic;
dbgo_dstat_chold: out std_ulogic;
dbgo_dstat_mhold: out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic);
end component;
component grpci2_phy_net is
generic(
tech : integer := DEFMEMTECH;
oepol : integer := 0;
bypass : integer range 0 to 1 := 1;
netlist : integer := 0
);
port(
pciclk : in std_logic;
pcii_rst : in std_ulogic;
pcii_gnt : in std_ulogic;
pcii_idsel : in std_ulogic;
pcii_ad : in std_logic_vector(31 downto 0);
pcii_cbe : in std_logic_vector(3 downto 0);
pcii_frame : in std_ulogic;
pcii_irdy : in std_ulogic;
pcii_trdy : in std_ulogic;
pcii_devsel : in std_ulogic;
pcii_stop : in std_ulogic;
pcii_lock : in std_ulogic;
pcii_perr : in std_ulogic;
pcii_serr : in std_ulogic;
pcii_par : in std_ulogic;
pcii_host : in std_ulogic;
pcii_pci66 : in std_ulogic;
pcii_pme_status : in std_ulogic;
pcii_int : in std_logic_vector(3 downto 0);
phyi_pcirstout : in std_logic;
phyi_pciasyncrst : in std_logic;
phyi_pcisoftrst : in std_logic_vector(2 downto 0);
phyi_pciinten : in std_logic_vector(3 downto 0);
phyi_m_request : in std_logic;
phyi_m_mabort : in std_logic;
phyi_pr_m_fstate : in std_logic_vector(1 downto 0);
phyi_pr_m_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_0_last : in std_logic;
phyi_pr_m_cfifo_0_stlast : in std_logic;
phyi_pr_m_cfifo_0_hold : in std_logic;
phyi_pr_m_cfifo_0_valid : in std_logic;
phyi_pr_m_cfifo_0_err : in std_logic;
phyi_pr_m_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_1_last : in std_logic;
phyi_pr_m_cfifo_1_stlast : in std_logic;
phyi_pr_m_cfifo_1_hold : in std_logic;
phyi_pr_m_cfifo_1_valid : in std_logic;
phyi_pr_m_cfifo_1_err : in std_logic;
phyi_pr_m_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_2_last : in std_logic;
phyi_pr_m_cfifo_2_stlast : in std_logic;
phyi_pr_m_cfifo_2_hold : in std_logic;
phyi_pr_m_cfifo_2_valid : in std_logic;
phyi_pr_m_cfifo_2_err : in std_logic;
phyi_pv_m_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_0_last : in std_logic;
phyi_pv_m_cfifo_0_stlast : in std_logic;
phyi_pv_m_cfifo_0_hold : in std_logic;
phyi_pv_m_cfifo_0_valid : in std_logic;
phyi_pv_m_cfifo_0_err : in std_logic;
phyi_pv_m_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_1_last : in std_logic;
phyi_pv_m_cfifo_1_stlast : in std_logic;
phyi_pv_m_cfifo_1_hold : in std_logic;
phyi_pv_m_cfifo_1_valid : in std_logic;
phyi_pv_m_cfifo_1_err : in std_logic;
phyi_pv_m_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_2_last : in std_logic;
phyi_pv_m_cfifo_2_stlast : in std_logic;
phyi_pv_m_cfifo_2_hold : in std_logic;
phyi_pv_m_cfifo_2_valid : in std_logic;
phyi_pv_m_cfifo_2_err : in std_logic;
phyi_pr_m_addr : in std_logic_vector(31 downto 0);
phyi_pr_m_cbe_data : in std_logic_vector(3 downto 0);
phyi_pr_m_cbe_cmd : in std_logic_vector(3 downto 0);
phyi_pr_m_first : in std_logic_vector(1 downto 0);
phyi_pv_m_term : in std_logic_vector(1 downto 0);
phyi_pr_m_ltimer : in std_logic_vector(7 downto 0);
phyi_pr_m_burst : in std_logic;
phyi_pr_m_abort : in std_logic_vector(0 downto 0);
phyi_pr_m_perren : in std_logic_vector(0 downto 0);
phyi_pr_m_done_fifo : in std_logic;
phyi_t_abort : in std_logic;
phyi_t_ready : in std_logic;
phyi_t_retry : in std_logic;
phyi_pr_t_state : in std_logic_vector(2 downto 0);
phyi_pv_t_state : in std_logic_vector(2 downto 0);
phyi_pr_t_fstate : in std_logic_vector(1 downto 0);
phyi_pr_t_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_0_last : in std_logic;
phyi_pr_t_cfifo_0_stlast : in std_logic;
phyi_pr_t_cfifo_0_hold : in std_logic;
phyi_pr_t_cfifo_0_valid : in std_logic;
phyi_pr_t_cfifo_0_err : in std_logic;
phyi_pr_t_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_1_last : in std_logic;
phyi_pr_t_cfifo_1_stlast : in std_logic;
phyi_pr_t_cfifo_1_hold : in std_logic;
phyi_pr_t_cfifo_1_valid : in std_logic;
phyi_pr_t_cfifo_1_err : in std_logic;
phyi_pr_t_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_2_last : in std_logic;
phyi_pr_t_cfifo_2_stlast : in std_logic;
phyi_pr_t_cfifo_2_hold : in std_logic;
phyi_pr_t_cfifo_2_valid : in std_logic;
phyi_pr_t_cfifo_2_err : in std_logic;
phyi_pv_t_diswithout : in std_logic;
phyi_pr_t_stoped : in std_logic;
phyi_pr_t_lcount : in std_logic_vector(2 downto 0);
phyi_pr_t_first_word : in std_logic;
phyi_pr_t_cur_acc_0_read : in std_logic;
phyi_pv_t_hold_write : in std_logic;
phyi_pv_t_hold_reset : in std_logic;
phyi_pr_conf_comm_perren : in std_logic;
phyi_pr_conf_comm_serren : in std_logic;
pcio_aden : out std_ulogic;
pcio_vaden : out std_logic_vector(31 downto 0);
pcio_cbeen : out std_logic_vector(3 downto 0);
pcio_frameen : out std_ulogic;
pcio_irdyen : out std_ulogic;
pcio_trdyen : out std_ulogic;
pcio_devselen : out std_ulogic;
pcio_stopen : out std_ulogic;
pcio_ctrlen : out std_ulogic;
pcio_perren : out std_ulogic;
pcio_paren : out std_ulogic;
pcio_reqen : out std_ulogic;
pcio_locken : out std_ulogic;
pcio_serren : out std_ulogic;
pcio_inten : out std_ulogic;
pcio_vinten : out std_logic_vector(3 downto 0);
pcio_req : out std_ulogic;
pcio_ad : out std_logic_vector(31 downto 0);
pcio_cbe : out std_logic_vector(3 downto 0);
pcio_frame : out std_ulogic;
pcio_irdy : out std_ulogic;
pcio_trdy : out std_ulogic;
pcio_devsel : out std_ulogic;
pcio_stop : out std_ulogic;
pcio_perr : out std_ulogic;
pcio_serr : out std_ulogic;
pcio_par : out std_ulogic;
pcio_lock : out std_ulogic;
pcio_power_state : out std_logic_vector(1 downto 0);
pcio_pme_enable : out std_ulogic;
pcio_pme_clear : out std_ulogic;
pcio_int : out std_ulogic;
pcio_rst : out std_ulogic;
phyo_pciv_rst : out std_ulogic;
phyo_pciv_gnt : out std_ulogic;
phyo_pciv_idsel : out std_ulogic;
phyo_pciv_ad : out std_logic_vector(31 downto 0);
phyo_pciv_cbe : out std_logic_vector(3 downto 0);
phyo_pciv_frame : out std_ulogic;
phyo_pciv_irdy : out std_ulogic;
phyo_pciv_trdy : out std_ulogic;
phyo_pciv_devsel : out std_ulogic;
phyo_pciv_stop : out std_ulogic;
phyo_pciv_lock : out std_ulogic;
phyo_pciv_perr : out std_ulogic;
phyo_pciv_serr : out std_ulogic;
phyo_pciv_par : out std_ulogic;
phyo_pciv_host : out std_ulogic;
phyo_pciv_pci66 : out std_ulogic;
phyo_pciv_pme_status : out std_ulogic;
phyo_pciv_int : out std_logic_vector(3 downto 0);
phyo_pr_m_state : out std_logic_vector(2 downto 0);
phyo_pr_m_last : out std_logic_vector(1 downto 0);
phyo_pr_m_hold : out std_logic_vector(1 downto 0);
phyo_pr_m_term : out std_logic_vector(1 downto 0);
phyo_pr_t_hold : out std_logic_vector(0 downto 0);
phyo_pr_t_stop : out std_logic;
phyo_pr_t_abort : out std_logic;
phyo_pr_t_diswithout : out std_logic;
phyo_pr_t_addr_perr : out std_logic;
phyo_pcirsto : out std_logic_vector(0 downto 0);
phyo_pr_po_ad : out std_logic_vector(31 downto 0);
phyo_pr_po_aden : out std_logic_vector(31 downto 0);
phyo_pr_po_cbe : out std_logic_vector(3 downto 0);
phyo_pr_po_cbeen : out std_logic_vector(3 downto 0);
phyo_pr_po_frame : out std_logic;
phyo_pr_po_frameen : out std_logic;
phyo_pr_po_irdy : out std_logic;
phyo_pr_po_irdyen : out std_logic;
phyo_pr_po_trdy : out std_logic;
phyo_pr_po_trdyen : out std_logic;
phyo_pr_po_stop : out std_logic;
phyo_pr_po_stopen : out std_logic;
phyo_pr_po_devsel : out std_logic;
phyo_pr_po_devselen : out std_logic;
phyo_pr_po_par : out std_logic;
phyo_pr_po_paren : out std_logic;
phyo_pr_po_perr : out std_logic;
phyo_pr_po_perren : out std_logic;
phyo_pr_po_lock : out std_logic;
phyo_pr_po_locken : out std_logic;
phyo_pr_po_req : out std_logic;
phyo_pr_po_reqen : out std_logic;
phyo_pr_po_serren : out std_logic;
phyo_pr_po_inten : out std_logic;
phyo_pr_po_vinten : out std_logic_vector(3 downto 0);
phyo_pio_rst : out std_ulogic;
phyo_pio_gnt : out std_ulogic;
phyo_pio_idsel : out std_ulogic;
phyo_pio_ad : out std_logic_vector(31 downto 0);
phyo_pio_cbe : out std_logic_vector(3 downto 0);
phyo_pio_frame : out std_ulogic;
phyo_pio_irdy : out std_ulogic;
phyo_pio_trdy : out std_ulogic;
phyo_pio_devsel : out std_ulogic;
phyo_pio_stop : out std_ulogic;
phyo_pio_lock : out std_ulogic;
phyo_pio_perr : out std_ulogic;
phyo_pio_serr : out std_ulogic;
phyo_pio_par : out std_ulogic;
phyo_pio_host : out std_ulogic;
phyo_pio_pci66 : out std_ulogic;
phyo_pio_pme_status : out std_ulogic;
phyo_pio_int : out std_logic_vector(3 downto 0);
phyo_poo_ad : out std_logic_vector(31 downto 0);
phyo_poo_aden : out std_logic_vector(31 downto 0);
phyo_poo_cbe : out std_logic_vector(3 downto 0);
phyo_poo_cbeen : out std_logic_vector(3 downto 0);
phyo_poo_frame : out std_logic;
phyo_poo_frameen : out std_logic;
phyo_poo_irdy : out std_logic;
phyo_poo_irdyen : out std_logic;
phyo_poo_trdy : out std_logic;
phyo_poo_trdyen : out std_logic;
phyo_poo_stop : out std_logic;
phyo_poo_stopen : out std_logic;
phyo_poo_devsel : out std_logic;
phyo_poo_devselen : out std_logic;
phyo_poo_par : out std_logic;
phyo_poo_paren : out std_logic;
phyo_poo_perr : out std_logic;
phyo_poo_perren : out std_logic;
phyo_poo_lock : out std_logic;
phyo_poo_locken : out std_logic;
phyo_poo_req : out std_logic;
phyo_poo_reqen : out std_logic;
phyo_poo_serren : out std_logic;
phyo_poo_inten : out std_logic;
phyo_poo_vinten : out std_logic_vector(3 downto 0)
);
end component;
end;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity feedforward_ST_WandB_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 13;
mem_size : integer := 5040
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of feedforward_ST_WandB_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_ST_WandB is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 5040;
AddressWidth : INTEGER := 13);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_ST_WandB is
component feedforward_ST_WandB_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_ST_WandB_ram_U : component feedforward_ST_WandB_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity feedforward_ST_WandB_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 13;
mem_size : integer := 5040
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of feedforward_ST_WandB_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_ST_WandB is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 5040;
AddressWidth : INTEGER := 13);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_ST_WandB is
component feedforward_ST_WandB_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_ST_WandB_ram_U : component feedforward_ST_WandB_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity feedforward_ST_WandB_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 13;
mem_size : integer := 5040
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of feedforward_ST_WandB_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_ST_WandB is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 5040;
AddressWidth : INTEGER := 13);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_ST_WandB is
component feedforward_ST_WandB_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_ST_WandB_ram_U : component feedforward_ST_WandB_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity feedforward_ST_WandB_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 13;
mem_size : integer := 5040
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of feedforward_ST_WandB_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_ST_WandB is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 5040;
AddressWidth : INTEGER := 13);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_ST_WandB is
component feedforward_ST_WandB_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_ST_WandB_ram_U : component feedforward_ST_WandB_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:10:06 12/28/2015
-- Design Name:
-- Module Name: livelli2impulsi - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity livelli2impulsi is
Port ( input : in STD_LOGIC;
clock : in STD_LOGIC;
output : out STD_LOGIC);
end livelli2impulsi;
architecture Behavioral of livelli2impulsi is
signal output_sig : std_logic := '0';
begin
output <= output_sig;
generazione_segnale_impulsivo : process(clock)
variable state : std_logic := '0';
begin
if(rising_edge(clock)) then
if(state = '0' and input = '1') then
output_sig <= '1';
state := '1';
elsif(state = '1' and input = '1') then
output_sig <= '0';
else -- Se input = '0' e si trova in qualsiasi stato
state := '0';
output_sig <= '0';
end if;
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Perform majority voting on read.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity mem_data_triplicator_rd_only is
generic (
-- Memory depth
depth_g : positive := 1048576;
-- Memory data width
width_g : positive := 16);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Interface
addr_i : in std_ulogic_vector(natural(ceil(log2(real(depth_g / 3)))) - 1 downto 0);
rd_en_i : in std_ulogic;
data_o : out std_ulogic_vector(width_g - 1 downto 0);
data_en_o : out std_ulogic;
busy_o : out std_ulogic;
done_o : out std_ulogic;
voted_o : out std_ulogic;
-- Memory interface
mem_addr_o : out std_ulogic_vector(natural(ceil(log2(real(depth_g)))) - 1 downto 0);
mem_rd_en_o : out std_ulogic;
mem_data_i : in std_ulogic_vector(width_g - 1 downto 0);
mem_data_en_i : in std_ulogic;
mem_busy_i : in std_ulogic;
mem_done_i : in std_ulogic);
end entity mem_data_triplicator_rd_only;
architecture rtl of mem_data_triplicator_rd_only is
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal rd_busy : std_ulogic;
signal rd_data_en : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
busy_o <= rd_busy or mem_busy_i;
done_o <= rd_data_en;
data_en_o <= rd_data_en;
------------------------------------------------------------------------------
-- Instances
------------------------------------------------------------------------------
-- Calculate addresses
mem_data_triplicator_addr_inst : entity work.mem_data_triplicator_addr
generic map (
depth_g => depth_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
addr_i => addr_i,
rd_en_i => rd_en_i,
wr_en_i => '0',
mem_addr_o => mem_addr_o,
mem_done_i => mem_done_i);
-- Perform majority voting on read
mem_data_triplicator_rd_inst : entity work.mem_data_triplicator_rd
generic map (
width_g => width_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
rd_en_i => rd_en_i,
data_o => data_o,
data_en_o => rd_data_en,
busy_o => rd_busy,
voted_o => voted_o,
mem_rd_en_o => mem_rd_en_o,
mem_data_i => mem_data_i,
mem_data_en_i => mem_data_en_i);
end architecture rtl;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 08-02-2016
-- Module Name: majority.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1165.all;
entity majority is
port (i1, i2, i3 : in std_logic;
o1 : out std_logic);
end entity;
architecture arch_majority of majority is
signal tmp1 : std_logic;
signal tmp2 : std_logic;
signal tmp3 : std_logic;
begin
tmp1 <= i1 and i2;
tmp2 <= i2 and i3;
tmp3 <= i1 and i3;
o1 <= tmp1 or tmp2 or tmp3 after 2 ns;
end architecture arch_majority;
|
library ieee;
use ieee.std_logic_1164.all;
entity driver is
generic (val : string);
port (o : out std_logic);
end driver;
architecture behav of driver is
begin
drv1: if val = "one" generate
o <= '1';
end generate;
drv0: if val = "zero" generate
o <= '0';
end generate;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity string01 is
port (o : out std_logic);
end string01;
architecture behav of string01 is
begin
e : entity work.driver
generic map (val => "one")
port map (o => o);
end behav;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 27920)
`protect data_block
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.txt_utils.all;
-- A testbench has no ports.
entity Adder_tb is
end Adder_tb;
architecture test of Adder_tb is
-- Declaration of the component that will be instantiated.
component adder
port (src1 : in addr_t; src2 : in addrdiff_t; result : out addrdiff_t);
end component;
-- Specifies which entity is bound with the component.
for instance: Adder use entity work.Adder;
signal src1 : addr_t;
signal src2 : addrdiff_t;
signal result : addr_t;
begin
-- Component instantiation.
instance: Adder port map (src1 => src1, src2 => src2, result => result);
-- This process does the real job.
process
variable error : boolean := false;
variable error_count : integer := 0;
type testcase_t is record
input1 : addr_t;
input2 : addrdiff_t;
output : word_t;
end record;
type testcase_table_t is array (natural range <>) of testcase_t;
constant testcases : testcase_table_t := (
(ZERO, ZERO, ZERO),
(ZERO, NEG_ONE, NEG_ONE),
(NEG_ONE, ZERO, NEG_ONE),
(ZERO, X"0000_0010", X"0000_0010"),
(X"ff00_0000", ZERO, X"ff00_0000"),
(X"bfc0_0000", X"0000_0004", X"bfc0_0004"),
(X"bfc0_000f", X"0000_0004", X"bfc0_0013")
);
begin
for i in testcases'range loop
-- Set the inputs.
src1 <= testcases(i).input1;
src2 <= testcases(i).input2;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
error := result /= testcases(i).output;
if error then
error_count := error_count + 1;
end if;
assert not error report
ANSI_RED & "Failure in testcase " & integer'image(i) &
ANSI_NONE severity note;
end loop;
assert error_count /= 0 report
ANSI_GREEN & "Test's over." & ANSI_NONE
severity note;
assert error_count = 0 report
ANSI_RED & integer'image(error_count) & " testcase(s) failed." & ANSI_NONE
severity failure;
-- Wait forever; this will finish the simulation.
wait;
end process;
end test;
|
-- NEED RESULT: ARCH00287: 'Abs' does not require parentheses around argument passed
-- NEED RESULT: ARCH00287: 'Not' does not require parentheses around argument passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00287
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00287)
-- ENT00287_Test_Bench(ARCH00287_Test_Bench)
--
-- REVISION HISTORY:
--
-- 22-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00287 of E00000 is
begin
P00287 :
process
variable bool1 : boolean := false ;
function fbool1 return boolean is
begin
return false ;
end fbool1 ;
variable int1 : integer := -4 ;
function fint1 ( pint : integer ) return integer is
begin
return - pint ;
end fint1 ;
begin
if abs int1 = 4 and
abs 2 = 2 and
abs fint1 (-10) = 10 and
abs integer'(fint1(10)) = 10 and
abs integer (fint1(3)) = 3 then
test_report ( "ARCH00287" ,
"'Abs' does not require parentheses around argument" ,
true ) ;
end if ;
test_report ( "ARCH00287" ,
"'Not' does not require parentheses around argument" ,
not bool1 and
not false and
not fbool1 and
not boolean'(fbool1) and
not boolean' (fbool1) ) ;
wait ;
end process P00287 ;
end ARCH00287 ;
entity ENT00287_Test_Bench is
end ENT00287_Test_Bench ;
architecture ARCH00287_Test_Bench of ENT00287_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00287 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00287_Test_Bench ;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Dec2_4En is
port( enable : in std_logic;
inputs : in std_logic_vector(1 downto 0);
outputs : out std_logic_vector(3 downto 0));
end Dec2_4En;
architecture RTL of Dec2_4En is
begin
process(enable, inputs)
begin
if (enable = '0') then
outputs <= "0000";
else
if (inputs = "00") then
outputs <= "0001";
elsif (inputs = "01") then
outputs <= "0010";
elsif (inputs = "10") then
outputs <= "0100";
else
outputs <= "1000";
end if;
end if;
end process;
end RTL; |
package pack1 is
procedure read ( x : out integer );
end package;
-------------------------------------------------------------------------------
use work.pack1.all;
package pack2 is
alias read is work.pack1.read [integer];
end package;
-------------------------------------------------------------------------------
use work.pack1.all;
use work.pack2.all;
entity test is
end entity;
architecture test of test is
begin
process is
variable x : integer;
begin
read(x); -- OK
wait;
end process;
end architecture;
|
-- Altera Microperipheral Reference Design Version 0802
--------------------------------------------------------
--
-- FILE NAME : portaout.vhd
-- PROJECT : Altera A8255 Peripheral Interface Adapter
-- PURPOSE : This file contains the entity and architecture
-- for the Port A Output Register of the A8255 design.
--
--Copyright © 2002 Altera Corporation. All rights reserved. Altera products are
--protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
--other intellectual property laws.
--This reference design file, and your use thereof, is subject to and governed by
--the terms and conditions of the applicable Altera Reference Design License Agreement.
--By using this reference design file, you indicate your acceptance of such terms and
--conditions between you and Altera Corporation. In the event that you do not agree with
--such terms and conditions, you may not use the reference design file. Please promptly
--destroy any copies you have made.
--This reference design file being provided on an "as-is" basis and as an accommodation
--and therefore all warranties, representations or guarantees of any kind
--(whether express, implied or statutory) including, without limitation, warranties of
--merchantability, non-infringement, or fitness for a particular purpose, are
--specifically disclaimed. By making this reference design file available, Altera
--expressly does not recommend, suggest or require that this reference design file be
--used in combination with any other product not provided by Altera.
--
--------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY portaout IS
PORT(
RESET : IN std_logic;
CLK : IN std_logic;
DIN : IN std_logic_vector (7 DOWNTO 0);
PortAOutLd : IN std_logic;
PAOUT : OUT std_logic_vector (7 DOWNTO 0)
);
END portaout;
ARCHITECTURE rtl OF portaout IS
SIGNAL PortAOutRegD : std_logic_vector(7 DOWNTO 0);
SIGNAL PortAOutRegQ : std_logic_vector(7 DOWNTO 0);
BEGIN
PAOUT <= PortAOutRegQ;
PortAOutRegProc: PROCESS ( PortAOutLd, PortAOutRegQ, DIN )
BEGIN
IF ( PortAOutLd = '0') THEN
PortAOutRegD <= DIN;
ELSE
PortAOutRegD <= PortAOutRegQ;
END IF;
END PROCESS;
PortAOutRegSynchProc: PROCESS ( RESET, CLK )
BEGIN
IF (RESET = '1') THEN
PortAOutRegQ <= "00000000";
ELSIF ( CLK'EVENT and CLK = '1') THEN
PortAOutRegQ <= PortAOutRegD;
END IF;
END PROCESS;
END rtl;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: div
-- File: div.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implemets a divide unit to execute the
-- UDIV/SDIV instructions. Divide leaves Y
-- register intact but does not produce a remainder.
-- Overflow detection is performed according to the
-- SPARC V8 manual, method B (page 116)
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use work.config.all;
use work.iface.all;
entity div is
port (
rst : in std_logic;
clk : in clk_type;
holdn : in std_logic;
divi : in div_in_type;
divo : out div_out_type
);
end;
architecture rtl of div is
type div_regtype is record
x : std_logic_vector(64 downto 0);
state : std_logic_vector(2 downto 0);
zero : std_logic;
zero2 : std_logic;
qzero : std_logic;
qmsb : std_logic;
ovf : std_logic;
neg : std_logic;
cnt : std_logic_vector(4 downto 0);
end record;
signal r, rin : div_regtype;
signal addin1, addin2, addout: std_logic_vector(32 downto 0);
signal addsub : std_logic;
begin
divcomb : process (r, rst, divi, addout)
variable v : div_regtype;
variable vready : std_logic;
variable vaddin1, vaddin2, vaddout: std_logic_vector(32 downto 0);
variable vaddsub, ymsb, remsign : std_logic;
constant Zero: std_logic_vector(32 downto 0) := "000000000000000000000000000000000";
begin
vready := '0'; v := r;
if addout = Zero then v.zero := '1'; else v.zero := '0'; end if;
v.zero2 := r.zero;
remsign := '0';
vaddin1 := r.x(63 downto 31); vaddin2 := divi.op2;
vaddsub := not (divi.op2(32) xor r.x(64));
case r.state is
when "000" =>
v.cnt := "00000";
if (divi.start = '1') then
v.x(64) := divi.y(32); v.state := "001";
end if;
when "001" =>
v.x := divi.y & divi.op1(31 downto 0);
v.neg := divi.op2(32) xor divi.y(32);
if divi.signed = '1' then
vaddin1 := divi.y(31 downto 0) & divi.op1(31);
v.ovf := not (addout(32) xor divi.y(32));
else
vaddin1 := divi.y; vaddsub := '1';
v.ovf := not addout(32);
end if;
v.state := "010";
when "010" =>
if ((divi.signed and r.neg and r.zero) = '1') and (divi.op1 = Zero) then v.ovf := '0'; end if;
v.qmsb := vaddsub; v.qzero := '1';
v.x(64 downto 32) := addout;
v.x(31 downto 0) := r.x(30 downto 0) & vaddsub;
v.state := "011";
-- pragma translate_off
if not is_x(r.cnt) then
-- pragma translate_on
v.cnt := r.cnt + 1;
-- pragma translate_off
end if;
-- pragma translate_on
when "011" =>
v.qzero := r.qzero and (vaddsub xor r.qmsb);
v.x(64 downto 32) := addout;
v.x(31 downto 0) := r.x(30 downto 0) & vaddsub;
if (r.cnt = "11111") then v.state := "100"; else
-- pragma translate_off
if not is_x(r.cnt) then
-- pragma translate_on
v.cnt := r.cnt + 1;
-- pragma translate_off
end if;
-- pragma translate_on
end if;
when others =>
vaddin1 := ((not r.x(31)) & r.x(30 downto 0) & '1');
vaddsub := r.x(31); vaddin2 := (others => '0'); vaddin2(0) := '1';
remsign := r.x(64) xor divi.op2(32);
if (r.zero = '0') and ( ((divi.signed = '0') and (r.x(64) /= r.neg)) or
((divi.signed = '1') and (remsign /= r.neg)) or (r.zero2 = '1'))
then
v.x(64 downto 32) := addout;
else
v.x(64 downto 32) := vaddin1; v.qzero := '0';
end if;
if (r.ovf = '1') then
v.x(63 downto 32) := (others => '1');
if divi.signed = '1' then
if r.neg = '1' then v.x(62 downto 32) := (others => '0');
else v.x(63) := '0'; end if;
end if;
end if;
vready := '1';
v.state := "000";
end case;
divo.icc <= r.x(63) & r.qzero & r.ovf & '0';
if (rst = '0') or (divi.flush = '1') then v.state := "000"; end if;
rin <= v;
divo.ready <= vready;
divo.result(31 downto 0) <= r.x(63 downto 32);
addin1 <= vaddin1; addin2 <= vaddin2; addsub <= vaddsub;
end process;
divadd : process(addin1, addin2, addsub)
variable b : std_logic_vector(32 downto 0);
begin
if addsub = '1' then b := not addin2; else b := addin2; end if;
-- pragma translate_off
if not (is_x(addin1 & b & addsub)) then
-- pragma translate_on
addout <= addin1 + b + addsub;
-- pragma translate_off
else
addout <= (others => 'X');
end if;
-- pragma translate_on
end process;
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') or GATEDCLK then r <= rin; end if;
end if;
end process;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: div
-- File: div.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implemets a divide unit to execute the
-- UDIV/SDIV instructions. Divide leaves Y
-- register intact but does not produce a remainder.
-- Overflow detection is performed according to the
-- SPARC V8 manual, method B (page 116)
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use work.config.all;
use work.iface.all;
entity div is
port (
rst : in std_logic;
clk : in clk_type;
holdn : in std_logic;
divi : in div_in_type;
divo : out div_out_type
);
end;
architecture rtl of div is
type div_regtype is record
x : std_logic_vector(64 downto 0);
state : std_logic_vector(2 downto 0);
zero : std_logic;
zero2 : std_logic;
qzero : std_logic;
qmsb : std_logic;
ovf : std_logic;
neg : std_logic;
cnt : std_logic_vector(4 downto 0);
end record;
signal r, rin : div_regtype;
signal addin1, addin2, addout: std_logic_vector(32 downto 0);
signal addsub : std_logic;
begin
divcomb : process (r, rst, divi, addout)
variable v : div_regtype;
variable vready : std_logic;
variable vaddin1, vaddin2, vaddout: std_logic_vector(32 downto 0);
variable vaddsub, ymsb, remsign : std_logic;
constant Zero: std_logic_vector(32 downto 0) := "000000000000000000000000000000000";
begin
vready := '0'; v := r;
if addout = Zero then v.zero := '1'; else v.zero := '0'; end if;
v.zero2 := r.zero;
remsign := '0';
vaddin1 := r.x(63 downto 31); vaddin2 := divi.op2;
vaddsub := not (divi.op2(32) xor r.x(64));
case r.state is
when "000" =>
v.cnt := "00000";
if (divi.start = '1') then
v.x(64) := divi.y(32); v.state := "001";
end if;
when "001" =>
v.x := divi.y & divi.op1(31 downto 0);
v.neg := divi.op2(32) xor divi.y(32);
if divi.signed = '1' then
vaddin1 := divi.y(31 downto 0) & divi.op1(31);
v.ovf := not (addout(32) xor divi.y(32));
else
vaddin1 := divi.y; vaddsub := '1';
v.ovf := not addout(32);
end if;
v.state := "010";
when "010" =>
if ((divi.signed and r.neg and r.zero) = '1') and (divi.op1 = Zero) then v.ovf := '0'; end if;
v.qmsb := vaddsub; v.qzero := '1';
v.x(64 downto 32) := addout;
v.x(31 downto 0) := r.x(30 downto 0) & vaddsub;
v.state := "011";
-- pragma translate_off
if not is_x(r.cnt) then
-- pragma translate_on
v.cnt := r.cnt + 1;
-- pragma translate_off
end if;
-- pragma translate_on
when "011" =>
v.qzero := r.qzero and (vaddsub xor r.qmsb);
v.x(64 downto 32) := addout;
v.x(31 downto 0) := r.x(30 downto 0) & vaddsub;
if (r.cnt = "11111") then v.state := "100"; else
-- pragma translate_off
if not is_x(r.cnt) then
-- pragma translate_on
v.cnt := r.cnt + 1;
-- pragma translate_off
end if;
-- pragma translate_on
end if;
when others =>
vaddin1 := ((not r.x(31)) & r.x(30 downto 0) & '1');
vaddsub := r.x(31); vaddin2 := (others => '0'); vaddin2(0) := '1';
remsign := r.x(64) xor divi.op2(32);
if (r.zero = '0') and ( ((divi.signed = '0') and (r.x(64) /= r.neg)) or
((divi.signed = '1') and (remsign /= r.neg)) or (r.zero2 = '1'))
then
v.x(64 downto 32) := addout;
else
v.x(64 downto 32) := vaddin1; v.qzero := '0';
end if;
if (r.ovf = '1') then
v.x(63 downto 32) := (others => '1');
if divi.signed = '1' then
if r.neg = '1' then v.x(62 downto 32) := (others => '0');
else v.x(63) := '0'; end if;
end if;
end if;
vready := '1';
v.state := "000";
end case;
divo.icc <= r.x(63) & r.qzero & r.ovf & '0';
if (rst = '0') or (divi.flush = '1') then v.state := "000"; end if;
rin <= v;
divo.ready <= vready;
divo.result(31 downto 0) <= r.x(63 downto 32);
addin1 <= vaddin1; addin2 <= vaddin2; addsub <= vaddsub;
end process;
divadd : process(addin1, addin2, addsub)
variable b : std_logic_vector(32 downto 0);
begin
if addsub = '1' then b := not addin2; else b := addin2; end if;
-- pragma translate_off
if not (is_x(addin1 & b & addsub)) then
-- pragma translate_on
addout <= addin1 + b + addsub;
-- pragma translate_off
else
addout <= (others => 'X');
end if;
-- pragma translate_on
end process;
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') or GATEDCLK then r <= rin; end if;
end if;
end process;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: div
-- File: div.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implemets a divide unit to execute the
-- UDIV/SDIV instructions. Divide leaves Y
-- register intact but does not produce a remainder.
-- Overflow detection is performed according to the
-- SPARC V8 manual, method B (page 116)
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use work.config.all;
use work.iface.all;
entity div is
port (
rst : in std_logic;
clk : in clk_type;
holdn : in std_logic;
divi : in div_in_type;
divo : out div_out_type
);
end;
architecture rtl of div is
type div_regtype is record
x : std_logic_vector(64 downto 0);
state : std_logic_vector(2 downto 0);
zero : std_logic;
zero2 : std_logic;
qzero : std_logic;
qmsb : std_logic;
ovf : std_logic;
neg : std_logic;
cnt : std_logic_vector(4 downto 0);
end record;
signal r, rin : div_regtype;
signal addin1, addin2, addout: std_logic_vector(32 downto 0);
signal addsub : std_logic;
begin
divcomb : process (r, rst, divi, addout)
variable v : div_regtype;
variable vready : std_logic;
variable vaddin1, vaddin2, vaddout: std_logic_vector(32 downto 0);
variable vaddsub, ymsb, remsign : std_logic;
constant Zero: std_logic_vector(32 downto 0) := "000000000000000000000000000000000";
begin
vready := '0'; v := r;
if addout = Zero then v.zero := '1'; else v.zero := '0'; end if;
v.zero2 := r.zero;
remsign := '0';
vaddin1 := r.x(63 downto 31); vaddin2 := divi.op2;
vaddsub := not (divi.op2(32) xor r.x(64));
case r.state is
when "000" =>
v.cnt := "00000";
if (divi.start = '1') then
v.x(64) := divi.y(32); v.state := "001";
end if;
when "001" =>
v.x := divi.y & divi.op1(31 downto 0);
v.neg := divi.op2(32) xor divi.y(32);
if divi.signed = '1' then
vaddin1 := divi.y(31 downto 0) & divi.op1(31);
v.ovf := not (addout(32) xor divi.y(32));
else
vaddin1 := divi.y; vaddsub := '1';
v.ovf := not addout(32);
end if;
v.state := "010";
when "010" =>
if ((divi.signed and r.neg and r.zero) = '1') and (divi.op1 = Zero) then v.ovf := '0'; end if;
v.qmsb := vaddsub; v.qzero := '1';
v.x(64 downto 32) := addout;
v.x(31 downto 0) := r.x(30 downto 0) & vaddsub;
v.state := "011";
-- pragma translate_off
if not is_x(r.cnt) then
-- pragma translate_on
v.cnt := r.cnt + 1;
-- pragma translate_off
end if;
-- pragma translate_on
when "011" =>
v.qzero := r.qzero and (vaddsub xor r.qmsb);
v.x(64 downto 32) := addout;
v.x(31 downto 0) := r.x(30 downto 0) & vaddsub;
if (r.cnt = "11111") then v.state := "100"; else
-- pragma translate_off
if not is_x(r.cnt) then
-- pragma translate_on
v.cnt := r.cnt + 1;
-- pragma translate_off
end if;
-- pragma translate_on
end if;
when others =>
vaddin1 := ((not r.x(31)) & r.x(30 downto 0) & '1');
vaddsub := r.x(31); vaddin2 := (others => '0'); vaddin2(0) := '1';
remsign := r.x(64) xor divi.op2(32);
if (r.zero = '0') and ( ((divi.signed = '0') and (r.x(64) /= r.neg)) or
((divi.signed = '1') and (remsign /= r.neg)) or (r.zero2 = '1'))
then
v.x(64 downto 32) := addout;
else
v.x(64 downto 32) := vaddin1; v.qzero := '0';
end if;
if (r.ovf = '1') then
v.x(63 downto 32) := (others => '1');
if divi.signed = '1' then
if r.neg = '1' then v.x(62 downto 32) := (others => '0');
else v.x(63) := '0'; end if;
end if;
end if;
vready := '1';
v.state := "000";
end case;
divo.icc <= r.x(63) & r.qzero & r.ovf & '0';
if (rst = '0') or (divi.flush = '1') then v.state := "000"; end if;
rin <= v;
divo.ready <= vready;
divo.result(31 downto 0) <= r.x(63 downto 32);
addin1 <= vaddin1; addin2 <= vaddin2; addsub <= vaddsub;
end process;
divadd : process(addin1, addin2, addsub)
variable b : std_logic_vector(32 downto 0);
begin
if addsub = '1' then b := not addin2; else b := addin2; end if;
-- pragma translate_off
if not (is_x(addin1 & b & addsub)) then
-- pragma translate_on
addout <= addin1 + b + addsub;
-- pragma translate_off
else
addout <= (others => 'X');
end if;
-- pragma translate_on
end process;
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') or GATEDCLK then r <= rin; end if;
end if;
end process;
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
package CONV_PACK_execute_block is
-- define attributes
attribute ENUM_ENCODING : STRING;
-- define any necessary types
type aluOp is (NOP, SLLS, SRLS, SRAS, ADDS, ADDUS, SUBS, SUBUS, ANDS, ORS,
XORS, SEQS, SNES, SLTS, SGTS, SLES, SGES, MOVI2SS, MOVS2IS, MOVFS, MOVDS,
MOVFP2IS, MOVI2FP, MOVI2TS, MOVT2IS, SLTUS, SGTUS, SLEUS, SGEUS, MULTU,
MULTS);
attribute ENUM_ENCODING of aluOp : type is
"00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110";
-- Declarations for conversion functions.
function aluOp_to_std_logic_vector(arg : in aluOp) return std_logic_vector;
end CONV_PACK_execute_block;
package body CONV_PACK_execute_block is
-- enum type to std_logic_vector function
function aluOp_to_std_logic_vector(arg : in aluOp) return std_logic_vector
is
-- synopsys built_in SYN_FEED_THRU;
begin
case arg is
when NOP => return "00000";
when SLLS => return "00001";
when SRLS => return "00010";
when SRAS => return "00011";
when ADDS => return "00100";
when ADDUS => return "00101";
when SUBS => return "00110";
when SUBUS => return "00111";
when ANDS => return "01000";
when ORS => return "01001";
when XORS => return "01010";
when SEQS => return "01011";
when SNES => return "01100";
when SLTS => return "01101";
when SGTS => return "01110";
when SLES => return "01111";
when SGES => return "10000";
when MOVI2SS => return "10001";
when MOVS2IS => return "10010";
when MOVFS => return "10011";
when MOVDS => return "10100";
when MOVFP2IS => return "10101";
when MOVI2FP => return "10110";
when MOVI2TS => return "10111";
when MOVT2IS => return "11000";
when SLTUS => return "11001";
when SGTUS => return "11010";
when SLEUS => return "11011";
when SGEUS => return "11100";
when MULTU => return "11101";
when MULTS => return "11110";
when others => assert FALSE -- this should not happen.
report "un-convertible value"
severity warning;
return "00000";
end case;
end;
end CONV_PACK_execute_block;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_63 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_63;
architecture SYN_BEHAVIORAL of FA_63 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_62 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_62;
architecture SYN_BEHAVIORAL of FA_62 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_61 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_61;
architecture SYN_BEHAVIORAL of FA_61 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_60 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_60;
architecture SYN_BEHAVIORAL of FA_60 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_59 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_59;
architecture SYN_BEHAVIORAL of FA_59 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n3, n4, n5, n6 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : OR2_X1 port map( A1 => B, A2 => A, ZN => n5);
U3 : NAND2_X1 port map( A1 => Ci, A2 => n5, ZN => n3);
U4 : NAND2_X1 port map( A1 => n3, A2 => n4, ZN => Co);
U5 : NAND2_X1 port map( A1 => B, A2 => A, ZN => n4);
U6 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_58 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_58;
architecture SYN_BEHAVIORAL of FA_58 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U3 : NAND2_X1 port map( A1 => n4, A2 => n5, ZN => Co);
U2 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n5);
U4 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n4);
U5 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_57 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_57;
architecture SYN_BEHAVIORAL of FA_57 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_56 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_56;
architecture SYN_BEHAVIORAL of FA_56 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XOR2_X1 port map( A => B, B => A, Z => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_55 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_55;
architecture SYN_BEHAVIORAL of FA_55 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_54 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_54;
architecture SYN_BEHAVIORAL of FA_54 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_53 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_53;
architecture SYN_BEHAVIORAL of FA_53 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_52 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_52;
architecture SYN_BEHAVIORAL of FA_52 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => B, A2 => A, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_51 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_51;
architecture SYN_BEHAVIORAL of FA_51 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_50 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_50;
architecture SYN_BEHAVIORAL of FA_50 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_49 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_49;
architecture SYN_BEHAVIORAL of FA_49 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_48 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_48;
architecture SYN_BEHAVIORAL of FA_48 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XOR2_X1 port map( A => A, B => B, Z => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_47 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_47;
architecture SYN_BEHAVIORAL of FA_47 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n5, n6, n7 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n6, A2 => n5, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n7, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n7);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n5);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n6);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_46 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_46;
architecture SYN_BEHAVIORAL of FA_46 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_45 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_45;
architecture SYN_BEHAVIORAL of FA_45 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_44 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_44;
architecture SYN_BEHAVIORAL of FA_44 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XNOR2_X1 port map( A => A, B => B, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_43 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_43;
architecture SYN_BEHAVIORAL of FA_43 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_42 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_42;
architecture SYN_BEHAVIORAL of FA_42 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_41 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_41;
architecture SYN_BEHAVIORAL of FA_41 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_40 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_40;
architecture SYN_BEHAVIORAL of FA_40 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => B, B => A, Z => S);
U2 : AND2_X1 port map( A1 => B, A2 => A, ZN => Co);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_39 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_39;
architecture SYN_BEHAVIORAL of FA_39 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_38 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_38;
architecture SYN_BEHAVIORAL of FA_38 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_37 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_37;
architecture SYN_BEHAVIORAL of FA_37 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n4, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n4);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_36 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_36;
architecture SYN_BEHAVIORAL of FA_36 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_35 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_35;
architecture SYN_BEHAVIORAL of FA_35 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_34 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_34;
architecture SYN_BEHAVIORAL of FA_34 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_33 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_33;
architecture SYN_BEHAVIORAL of FA_33 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n4, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n4);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_32 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_32;
architecture SYN_BEHAVIORAL of FA_32 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => B, B => A, Z => S);
U2 : AND2_X1 port map( A1 => B, A2 => A, ZN => Co);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_31 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_31;
architecture SYN_BEHAVIORAL of FA_31 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_30 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_30;
architecture SYN_BEHAVIORAL of FA_30 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U4 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_29 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_29;
architecture SYN_BEHAVIORAL of FA_29 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_28 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_28;
architecture SYN_BEHAVIORAL of FA_28 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_27 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_27;
architecture SYN_BEHAVIORAL of FA_27 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_26 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_26;
architecture SYN_BEHAVIORAL of FA_26 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U4 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_25 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_25;
architecture SYN_BEHAVIORAL of FA_25 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_24 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_24;
architecture SYN_BEHAVIORAL of FA_24 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XOR2_X1 port map( A => B, B => A, Z => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_23 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_23;
architecture SYN_BEHAVIORAL of FA_23 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : OAI21_X1 port map( B1 => B, B2 => A, A => Ci, ZN => n5);
U4 : XNOR2_X1 port map( A => A, B => B, ZN => n6);
U5 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_22 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_22;
architecture SYN_BEHAVIORAL of FA_22 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_21 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_21;
architecture SYN_BEHAVIORAL of FA_21 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_20 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_20;
architecture SYN_BEHAVIORAL of FA_20 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => B, A2 => A, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_19 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_19;
architecture SYN_BEHAVIORAL of FA_19 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : OAI21_X1 port map( B1 => B, B2 => A, A => Ci, ZN => n5);
U2 : XNOR2_X1 port map( A => A, B => B, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_18 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_18;
architecture SYN_BEHAVIORAL of FA_18 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_17 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_17;
architecture SYN_BEHAVIORAL of FA_17 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_16 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_16;
architecture SYN_BEHAVIORAL of FA_16 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XOR2_X1 port map( A => B, B => A, Z => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_15 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_15;
architecture SYN_BEHAVIORAL of FA_15 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_14 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_14;
architecture SYN_BEHAVIORAL of FA_14 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_13 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_13;
architecture SYN_BEHAVIORAL of FA_13 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_12 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_12;
architecture SYN_BEHAVIORAL of FA_12 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : OR2_X1 port map( A1 => B, A2 => A, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_11 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_11;
architecture SYN_BEHAVIORAL of FA_11 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_10 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_10;
architecture SYN_BEHAVIORAL of FA_10 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_9 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_9;
architecture SYN_BEHAVIORAL of FA_9 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_8 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_8;
architecture SYN_BEHAVIORAL of FA_8 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => A, A2 => B, ZN => Co);
U2 : XOR2_X1 port map( A => B, B => A, Z => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_7 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_7;
architecture SYN_BEHAVIORAL of FA_7 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_6 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_6;
architecture SYN_BEHAVIORAL of FA_6 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_5 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_5;
architecture SYN_BEHAVIORAL of FA_5 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_4 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_4;
architecture SYN_BEHAVIORAL of FA_4 is
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
begin
U2 : XNOR2_X1 port map( A => B, B => A, ZN => S);
U1 : OR2_X1 port map( A1 => B, A2 => A, ZN => Co);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_3 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_3;
architecture SYN_BEHAVIORAL of FA_3 is
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_2 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_2;
architecture SYN_BEHAVIORAL of FA_2 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n4, n5, n6 : std_logic;
begin
U5 : OAI21_X1 port map( B1 => A, B2 => B, A => Ci, ZN => n5);
U4 : NAND2_X1 port map( A1 => A, A2 => B, ZN => n4);
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n6);
U1 : XNOR2_X1 port map( A => Ci, B => n6, ZN => S);
U3 : NAND2_X1 port map( A1 => n5, A2 => n4, ZN => Co);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_1 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_1;
architecture SYN_BEHAVIORAL of FA_1 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U2 : XNOR2_X1 port map( A => B, B => A, ZN => n3);
U1 : XNOR2_X1 port map( A => Ci, B => n3, ZN => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_7 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_7;
architecture SYN_Bhe of mux21_SIZE4_7 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U3 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
U4 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_6 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_6;
architecture SYN_Bhe of mux21_SIZE4_6 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U3 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
U4 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_5 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_5;
architecture SYN_Bhe of mux21_SIZE4_5 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U3 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
U4 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_4 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_4;
architecture SYN_Bhe of mux21_SIZE4_4 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U4 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
U3 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_3 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_3;
architecture SYN_Bhe of mux21_SIZE4_3 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
signal n1, n2, n3, n4, n5 : std_logic;
begin
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U3 : INV_X1 port map( A => IN0(0), ZN => n2);
U4 : OR2_X1 port map( A1 => CTRL, A2 => n4, ZN => n1);
U5 : NAND2_X1 port map( A1 => n1, A2 => n5, ZN => OUT1(1));
U6 : INV_X1 port map( A => IN0(1), ZN => n4);
U7 : NAND2_X1 port map( A1 => CTRL, A2 => IN1(0), ZN => n3);
U8 : OAI21_X1 port map( B1 => CTRL, B2 => n2, A => n3, ZN => OUT1(0));
U9 : NAND2_X1 port map( A1 => CTRL, A2 => IN1(1), ZN => n5);
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_2 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_2;
architecture SYN_Bhe of mux21_SIZE4_2 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U3 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
U4 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_1 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_1;
architecture SYN_Bhe of mux21_SIZE4_1 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U1 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
U2 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U3 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U4 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_15 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_15;
architecture SYN_STRUCTURAL of RCA_N4_15 is
component FA_57
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_58
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_59
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_60
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561359 : std_logic;
begin
FAI_1 : FA_60 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_59 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_58 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_57 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561359);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_14 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_14;
architecture SYN_STRUCTURAL of RCA_N4_14 is
component FA_53
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_54
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_55
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_56
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561358 : std_logic;
begin
FAI_1 : FA_56 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_55 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_54 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_53 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561358);
n1 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_13 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_13;
architecture SYN_STRUCTURAL of RCA_N4_13 is
component FA_49
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_50
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_51
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_52
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561357 : std_logic;
begin
FAI_1 : FA_52 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_51 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_50 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_49 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561357);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_12 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_12;
architecture SYN_STRUCTURAL of RCA_N4_12 is
component FA_45
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_46
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_47
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_48
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n2, CTMP_3_port, CTMP_2_port, n1, net561356 : std_logic;
begin
FAI_1 : FA_48 port map( A => A(0), B => B(0), Ci => n2, S => S(0), Co => n1)
;
FAI_2 : FA_47 port map( A => A(1), B => B(1), Ci => n1, S => S(1), Co =>
CTMP_2_port);
FAI_3 : FA_46 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_45 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561356);
n2 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_11 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_11;
architecture SYN_STRUCTURAL of RCA_N4_11 is
component FA_41
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_42
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_43
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_44
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561355 : std_logic;
begin
FAI_1 : FA_44 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_43 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_42 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_41 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561355);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_10 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_10;
architecture SYN_STRUCTURAL of RCA_N4_10 is
component FA_37
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_38
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_39
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_40
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n2, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561354 : std_logic;
begin
FAI_1 : FA_40 port map( A => A(0), B => B(0), Ci => n2, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_39 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_38 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_37 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561354);
n2 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_9 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_9;
architecture SYN_STRUCTURAL of RCA_N4_9 is
component FA_33
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_34
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_35
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_36
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n2, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561353 : std_logic;
begin
FAI_1 : FA_36 port map( A => A(0), B => B(0), Ci => n2, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_35 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_34 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_33 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561353);
n2 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_8 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_8;
architecture SYN_STRUCTURAL of RCA_N4_8 is
component FA_29
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_30
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_31
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_32
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561352 : std_logic;
begin
FAI_1 : FA_32 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_31 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_30 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_29 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561352);
n1 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_7 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_7;
architecture SYN_STRUCTURAL of RCA_N4_7 is
component FA_25
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_26
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_27
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_28
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561351 : std_logic;
begin
FAI_1 : FA_28 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_27 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_26 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_25 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561351);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_6 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_6;
architecture SYN_STRUCTURAL of RCA_N4_6 is
component FA_21
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_22
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_23
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_24
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561350 : std_logic;
begin
FAI_1 : FA_24 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_23 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_22 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_21 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561350);
n1 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_5 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_5;
architecture SYN_STRUCTURAL of RCA_N4_5 is
component FA_17
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_18
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_19
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_20
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561349 : std_logic;
begin
FAI_1 : FA_20 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_19 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_18 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_17 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561349);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_4 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_4;
architecture SYN_STRUCTURAL of RCA_N4_4 is
component FA_13
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_14
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_15
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_16
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561348 : std_logic;
begin
FAI_1 : FA_16 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_15 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_14 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_13 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561348);
n1 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_3 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_3;
architecture SYN_STRUCTURAL of RCA_N4_3 is
component FA_9
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_10
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_11
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_12
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561347 : std_logic;
begin
FAI_1 : FA_12 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_11 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_10 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_9 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561347);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_2 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_2;
architecture SYN_STRUCTURAL of RCA_N4_2 is
component FA_5
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_6
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_7
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_8
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561346 : std_logic;
begin
FAI_1 : FA_8 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_7 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_6 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_5 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561346);
n1 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_1 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_1;
architecture SYN_STRUCTURAL of RCA_N4_1 is
component FA_1
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_2
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_3
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_4
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561345 : std_logic;
begin
FAI_1 : FA_4 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_3 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_2 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_1 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561345);
n1 <= '1';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shift_N9_1 is
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (8 downto 0);
SO : out std_logic);
end shift_N9_1;
architecture SYN_archi of shift_N9_1 is
component SDFF_X2
port( D, SI, SE, CK : in std_logic; Q, QN : out std_logic);
end component;
component SDFF_X1
port( D, SI, SE, CK : in std_logic; Q, QN : out std_logic);
end component;
signal tmp_8_port, tmp_7_port, tmp_6_port, tmp_5_port, tmp_4_port,
tmp_3_port, tmp_2_port, tmp_1_port, n2, n3, n4, n5, n6, n7, n8, n9, n10,
n11 : std_logic;
begin
tmp_reg_3_inst : SDFF_X1 port map( D => tmp_4_port, SI => D(3), SE => ALOAD,
CK => Clock, Q => tmp_3_port, QN => n11);
tmp_reg_7_inst : SDFF_X1 port map( D => tmp_8_port, SI => D(7), SE => ALOAD,
CK => Clock, Q => tmp_7_port, QN => n10);
tmp_reg_5_inst : SDFF_X1 port map( D => tmp_6_port, SI => D(5), SE => ALOAD,
CK => Clock, Q => tmp_5_port, QN => n9);
tmp_reg_4_inst : SDFF_X1 port map( D => tmp_5_port, SI => D(4), SE => ALOAD,
CK => Clock, Q => tmp_4_port, QN => n8);
tmp_reg_8_inst : SDFF_X1 port map( D => n6, SI => D(8), SE => ALOAD, CK =>
Clock, Q => tmp_8_port, QN => n7);
tmp_reg_6_inst : SDFF_X1 port map( D => tmp_7_port, SI => D(6), SE => ALOAD,
CK => Clock, Q => tmp_6_port, QN => n5);
tmp_reg_1_inst : SDFF_X1 port map( D => tmp_2_port, SI => D(1), SE => ALOAD,
CK => Clock, Q => tmp_1_port, QN => n4);
tmp_reg_2_inst : SDFF_X1 port map( D => tmp_3_port, SI => D(2), SE => ALOAD,
CK => Clock, Q => tmp_2_port, QN => n3);
tmp_reg_0_inst : SDFF_X2 port map( D => tmp_1_port, SI => D(0), SE => ALOAD,
CK => Clock, Q => SO, QN => n2);
n6 <= '0';
end SYN_archi;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_8 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_8;
architecture SYN_bhe of booth_encoder_8 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n9, n10, n11, n12 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n9, B1 => n12,
B2 => n11, B3 => B_in(2), ZN => A_out(0));
U6 : INV_X1 port map( A => B_in(1), ZN => n11);
U3 : INV_X1 port map( A => B_in(2), ZN => n9);
U4 : INV_X1 port map( A => B_in(0), ZN => n12);
U5 : OAI221_X1 port map( B1 => B_in(1), B2 => n12, C1 => n11, C2 => B_in(2),
A => n10, ZN => A_out(2));
U7 : NAND2_X1 port map( A1 => B_in(2), A2 => n12, ZN => n10);
U8 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n9, ZN =>
A_out(1));
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_7 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_7;
architecture SYN_bhe of booth_encoder_7 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n8, n9, n10, n11 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n11,
B2 => n10, B3 => B_in(2), ZN => A_out(0));
U6 : INV_X1 port map( A => B_in(1), ZN => n10);
U3 : INV_X1 port map( A => B_in(0), ZN => n11);
U4 : INV_X1 port map( A => B_in(2), ZN => n8);
U5 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
U7 : OAI221_X1 port map( B1 => B_in(1), B2 => n11, C1 => n10, C2 => B_in(2),
A => n9, ZN => A_out(2));
U8 : NAND2_X1 port map( A1 => B_in(2), A2 => n11, ZN => n9);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_6 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_6;
architecture SYN_bhe of booth_encoder_6 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n8, n9, n10, n11 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n11,
B2 => n10, B3 => B_in(2), ZN => A_out(0));
U3 : INV_X1 port map( A => B_in(2), ZN => n8);
U4 : INV_X1 port map( A => B_in(1), ZN => n10);
U5 : INV_X1 port map( A => B_in(0), ZN => n11);
U6 : OAI221_X1 port map( B1 => B_in(1), B2 => n11, C1 => n10, C2 => B_in(2),
A => n9, ZN => A_out(2));
U7 : NAND2_X1 port map( A1 => B_in(2), A2 => n11, ZN => n9);
U8 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_5 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_5;
architecture SYN_bhe of booth_encoder_5 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n8, n9, n10, n11 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n11,
B2 => n10, B3 => B_in(2), ZN => A_out(0));
U3 : INV_X1 port map( A => B_in(2), ZN => n8);
U4 : INV_X1 port map( A => B_in(1), ZN => n10);
U5 : INV_X1 port map( A => B_in(0), ZN => n11);
U6 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
U7 : OAI221_X1 port map( B1 => B_in(1), B2 => n11, C1 => n10, C2 => B_in(2),
A => n9, ZN => A_out(2));
U8 : NAND2_X1 port map( A1 => B_in(2), A2 => n11, ZN => n9);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_4 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_4;
architecture SYN_bhe of booth_encoder_4 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n8, n9, n10, n11 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n11,
B2 => n10, B3 => B_in(2), ZN => A_out(0));
U3 : INV_X1 port map( A => B_in(2), ZN => n8);
U4 : INV_X1 port map( A => B_in(1), ZN => n10);
U5 : INV_X1 port map( A => B_in(0), ZN => n11);
U6 : OAI221_X1 port map( B1 => B_in(1), B2 => n11, C1 => n10, C2 => B_in(2),
A => n9, ZN => A_out(2));
U7 : NAND2_X1 port map( A1 => B_in(2), A2 => n11, ZN => n9);
U8 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_3 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_3;
architecture SYN_bhe of booth_encoder_3 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n8, n9, n10, n11 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n11,
B2 => n10, B3 => B_in(2), ZN => A_out(0));
U3 : INV_X1 port map( A => B_in(1), ZN => n10);
U4 : INV_X1 port map( A => B_in(0), ZN => n11);
U5 : INV_X1 port map( A => B_in(2), ZN => n8);
U6 : OAI221_X1 port map( B1 => B_in(1), B2 => n11, C1 => n10, C2 => B_in(2),
A => n9, ZN => A_out(2));
U7 : NAND2_X1 port map( A1 => B_in(2), A2 => n11, ZN => n9);
U8 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_2 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_2;
architecture SYN_bhe of booth_encoder_2 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n8, n9, n10, n11 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n11,
B2 => n10, B3 => B_in(2), ZN => A_out(0));
U3 : INV_X1 port map( A => B_in(1), ZN => n10);
U4 : INV_X1 port map( A => B_in(0), ZN => n11);
U5 : INV_X1 port map( A => B_in(2), ZN => n8);
U6 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
U7 : OAI221_X1 port map( B1 => B_in(1), B2 => n11, C1 => n10, C2 => B_in(2),
A => n9, ZN => A_out(2));
U8 : NAND2_X1 port map( A1 => B_in(2), A2 => n11, ZN => n9);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_1 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_1;
architecture SYN_bhe of booth_encoder_1 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal n7, n8, n9 : std_logic;
begin
U9 : OAI33_X1 port map( A1 => B_in(0), A2 => B_in(1), A3 => n8, B1 => n9, B2
=> n8, B3 => B_in(2), ZN => A_out(0));
U4 : NAND2_X1 port map( A1 => B_in(2), A2 => n9, ZN => n7);
U3 : OAI221_X1 port map( B1 => B_in(1), B2 => n9, C1 => n8, C2 => B_in(2), A
=> n7, ZN => A_out(2));
U5 : INV_X1 port map( A => B_in(0), ZN => n9);
U6 : INV_X1 port map( A => B_in(1), ZN => n8);
U7 : AOI21_X1 port map( B1 => B_in(0), B2 => B_in(1), A => n8, ZN =>
A_out(1));
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_7 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_7;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_7 is
component mux21_SIZE4_7
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_13
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_14
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561343, net561344 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_14 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561344);
rca_carry : RCA_N4_13 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561343);
outmux : mux21_SIZE4_7 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_6 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_6;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_6 is
component mux21_SIZE4_6
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_11
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_12
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561341, net561342 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_12 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561342);
rca_carry : RCA_N4_11 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561341);
outmux : mux21_SIZE4_6 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_5 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_5;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_5 is
component mux21_SIZE4_5
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_9
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_10
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561339, net561340 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_10 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561340);
rca_carry : RCA_N4_9 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561339);
outmux : mux21_SIZE4_5 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_4 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_4;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_4 is
component mux21_SIZE4_4
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_7
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_8
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561337, net561338 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_8 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561338);
rca_carry : RCA_N4_7 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561337);
outmux : mux21_SIZE4_4 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_3 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_3;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_3 is
component mux21_SIZE4_3
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_5
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_6
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561335, net561336 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_6 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561336);
rca_carry : RCA_N4_5 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561335);
outmux : mux21_SIZE4_3 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_2 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_2;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_2 is
component mux21_SIZE4_2
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_3
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_4
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561333, net561334 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_4 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561334);
rca_carry : RCA_N4_3 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561333);
outmux : mux21_SIZE4_2 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_1 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_1;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_1 is
component mux21_SIZE4_1
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_1
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_2
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561331, net561332 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_2 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561332);
rca_carry : RCA_N4_1 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561331);
outmux : mux21_SIZE4_1 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_26 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_26;
architecture SYN_beh of pg_26 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : INV_X1 port map( A => n3, ZN => g_out);
U2 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U3 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_25 is
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out std_logic
);
end pg_25;
architecture SYN_beh of pg_25 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U2 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => g_out_BAR);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_24 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_24;
architecture SYN_beh of pg_24 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : INV_X1 port map( A => g, ZN => n3);
U2 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U4 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_23 is
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out std_logic
);
end pg_23;
architecture SYN_beh of pg_23 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => g_out_BAR);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_22 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_22;
architecture SYN_beh of pg_22 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U2 : INV_X1 port map( A => g, ZN => n3);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U4 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_21 is
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out std_logic
);
end pg_21;
architecture SYN_beh of pg_21 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => g_out_BAR);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_20 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_20;
architecture SYN_beh of pg_20 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
signal n3, n4 : std_logic;
begin
U1 : CLKBUF_X1 port map( A => p, Z => n3);
U2 : INV_X1 port map( A => n4, ZN => g_out);
U3 : AND2_X1 port map( A1 => n3, A2 => p_prec, ZN => p_out);
U4 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => n4);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_19 is
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out std_logic
);
end pg_19;
architecture SYN_beh of pg_19 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => g_out_BAR);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_18 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_18;
architecture SYN_beh of pg_18 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
U3 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_17 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_17;
architecture SYN_beh of pg_17 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : INV_X1 port map( A => n3, ZN => g_out);
U2 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_16 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_16;
architecture SYN_beh of pg_16 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_15 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_15;
architecture SYN_beh of pg_15 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : INV_X1 port map( A => n3, ZN => g_out);
U2 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_14 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_14;
architecture SYN_beh of pg_14 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_13 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_13;
architecture SYN_beh of pg_13 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_12 is
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end pg_12;
architecture SYN_beh of pg_12 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : NAND2_X1 port map( A1 => n3, A2 => g_BAR, ZN => g_out);
U3 : NAND2_X1 port map( A1 => p, A2 => g_prec, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_11 is
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end pg_11;
architecture SYN_beh of pg_11 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U3 : NAND2_X1 port map( A1 => n2, A2 => g_BAR, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_10 is
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end pg_10;
architecture SYN_beh of pg_10 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U2 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U3 : NAND2_X1 port map( A1 => n2, A2 => g_BAR, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_9 is
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end pg_9;
architecture SYN_beh of pg_9 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : NAND2_X1 port map( A1 => n2, A2 => g_BAR, ZN => g_out);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_8 is
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out std_logic
);
end pg_8;
architecture SYN_beh of pg_8 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => p_prec, A2 => p, ZN => p_out);
U2 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => g_out_BAR);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_7 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_7;
architecture SYN_beh of pg_7 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_6 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_6;
architecture SYN_beh of pg_6 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_5 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_5;
architecture SYN_beh of pg_5 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : INV_X1 port map( A => g, ZN => n2);
U2 : NAND2_X1 port map( A1 => n3, A2 => n2, ZN => g_out);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n3);
U4 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_4 is
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end pg_4;
architecture SYN_beh of pg_4 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U3 : NAND2_X1 port map( A1 => n2, A2 => g_BAR, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_3 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_3;
architecture SYN_beh of pg_3 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_2 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_2;
architecture SYN_beh of pg_2 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => g, ZN => n3);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U4 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_1 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_1;
architecture SYN_beh of pg_1 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U3 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n3);
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_9 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_9;
architecture SYN_beh of g_9 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n2 : std_logic;
begin
U1 : AOI21_X1 port map( B1 => g_prec, B2 => p, A => g, ZN => n2);
U2 : INV_X1 port map( A => n2, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_8 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_8;
architecture SYN_beh of g_8 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : NAND2_X1 port map( A1 => n3, A2 => n2, ZN => g_out);
U2 : INV_X1 port map( A => g, ZN => n2);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_7 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_7;
architecture SYN_beh of g_7 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : NAND2_X1 port map( A1 => n3, A2 => n2, ZN => g_out);
U2 : INV_X1 port map( A => g, ZN => n2);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_6 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_6;
architecture SYN_beh of g_6 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : INV_X1 port map( A => n3, ZN => g_out);
U2 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_5 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_5;
architecture SYN_beh of g_5 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => g_out);
U2 : INV_X1 port map( A => g, ZN => n3);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_4 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_4;
architecture SYN_beh of g_4 is
component NAND2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : INV_X1 port map( A => g, ZN => n3);
U2 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n2);
U3 : NAND2_X2 port map( A1 => n2, A2 => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_3 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_3;
architecture SYN_beh of g_3 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : INV_X1 port map( A => g, ZN => n2);
U2 : NAND2_X1 port map( A1 => n3, A2 => n2, ZN => g_out);
U3 : NAND2_X1 port map( A1 => g_prec, A2 => p, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_2 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_2;
architecture SYN_beh of g_2 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : NAND2_X1 port map( A1 => p, A2 => g_prec, ZN => n3);
U2 : INV_X1 port map( A => g, ZN => n2);
U3 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_1 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_1;
architecture SYN_beh of g_1 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n3 : std_logic;
begin
U1 : INV_X1 port map( A => n3, ZN => g_out);
U2 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => n3);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_31 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_31;
architecture SYN_beh of pg_net_31 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => a, B => b, Z => p_out);
U2 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_30 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_30;
architecture SYN_beh of pg_net_30 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n1 : std_logic;
begin
U1 : INV_X1 port map( A => a, ZN => n1);
U2 : XNOR2_X1 port map( A => b, B => n1, ZN => p_out);
U3 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_29 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_29;
architecture SYN_beh of pg_net_29 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_28 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_28;
architecture SYN_beh of pg_net_28 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_27 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_27;
architecture SYN_beh of pg_net_27 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n1 : std_logic;
begin
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
U2 : INV_X1 port map( A => a, ZN => n1);
U3 : XNOR2_X1 port map( A => b, B => n1, ZN => p_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_26 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_26;
architecture SYN_beh of pg_net_26 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_25 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_25;
architecture SYN_beh of pg_net_25 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => a, B => b, Z => p_out);
U2 : AND2_X1 port map( A1 => a, A2 => b, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_24 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_24;
architecture SYN_beh of pg_net_24 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_23 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_23;
architecture SYN_beh of pg_net_23 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_22 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_22;
architecture SYN_beh of pg_net_22 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_21 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_21;
architecture SYN_beh of pg_net_21 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal n1 : std_logic;
begin
U1 : INV_X1 port map( A => a, ZN => n1);
U2 : XNOR2_X1 port map( A => b, B => n1, ZN => p_out);
U3 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_20 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_20;
architecture SYN_beh of pg_net_20 is
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n1 : std_logic;
begin
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
U2 : INV_X1 port map( A => a, ZN => n1);
U3 : XNOR2_X1 port map( A => b, B => n1, ZN => p_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_19 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_19;
architecture SYN_beh of pg_net_19 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_18 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_18;
architecture SYN_beh of pg_net_18 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_17 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_17;
architecture SYN_beh of pg_net_17 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U2 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_16 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_16;
architecture SYN_beh of pg_net_16 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U2 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_15 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_15;
architecture SYN_beh of pg_net_15 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_14 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_14;
architecture SYN_beh of pg_net_14 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U2 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_13 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_13;
architecture SYN_beh of pg_net_13 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_12 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_12;
architecture SYN_beh of pg_net_12 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => a, B => b, Z => p_out);
U2 : AND2_X1 port map( A1 => a, A2 => b, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_11 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_11;
architecture SYN_beh of pg_net_11 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_10 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_10;
architecture SYN_beh of pg_net_10 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_9 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_9;
architecture SYN_beh of pg_net_9 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_8 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_8;
architecture SYN_beh of pg_net_8 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_7 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_7;
architecture SYN_beh of pg_net_7 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_6 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_6;
architecture SYN_beh of pg_net_6 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U1 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U2 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_5 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_5;
architecture SYN_beh of pg_net_5 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_4 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_4;
architecture SYN_beh of pg_net_4 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_3 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_3;
architecture SYN_beh of pg_net_3 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_2 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_2;
architecture SYN_beh of pg_net_2 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
begin
U2 : XOR2_X1 port map( A => b, B => a, Z => p_out);
U1 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_1 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_1;
architecture SYN_beh of pg_net_1 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
signal n1 : std_logic;
begin
U1 : XNOR2_X1 port map( A => b, B => n1, ZN => p_out);
U2 : INV_X1 port map( A => a, ZN => n1);
U3 : AND2_X1 port map( A1 => b, A2 => a, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux41_MUX_SIZE32_1 is
port( IN0, IN1, IN2, IN3 : in std_logic_vector (31 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (31 downto
0));
end mux41_MUX_SIZE32_1;
architecture SYN_bhe of mux41_MUX_SIZE32_1 is
component AOI222_X1
port( A1, A2, B1, B2, C1, C2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X2
port( A : in std_logic; Z : out std_logic);
end component;
component AND2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component CLKBUF_X3
port( A : in std_logic; Z : out std_logic);
end component;
component NOR2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component OR3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n38, n39, n40, n41, n53, n54, n55, n57, n61, n63, n64, n65, n66, n68,
n69, n70, n71, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92
, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117,
n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129, n130,
n131, n132, n135, n136, n137, n138, n139, n141, n142, n143, n144, n145,
n146, n147, n148, n149 : std_logic;
begin
U21 : INV_X1 port map( A => n143, ZN => OUT1(29));
U15 : INV_X1 port map( A => n145, ZN => OUT1(31));
U1 : BUF_X2 port map( A => n148, Z => n128);
U2 : NAND2_X1 port map( A1 => n83, A2 => IN2(12), ZN => n38);
U3 : AOI21_X1 port map( B1 => n127, B2 => IN0(12), A => n96, ZN => n39);
U4 : NAND2_X1 port map( A1 => n38, A2 => n39, ZN => OUT1(12));
U5 : AOI222_X1 port map( A1 => n130, A2 => IN1(23), B1 => n127, B2 =>
IN0(23), C1 => IN2(23), C2 => n83, ZN => n40);
U6 : INV_X1 port map( A => n40, ZN => OUT1(23));
U7 : AOI222_X1 port map( A1 => n126, A2 => IN0(30), B1 => n125, B2 =>
IN2(30), C1 => IN1(30), C2 => n71, ZN => n41);
U8 : INV_X1 port map( A => n41, ZN => OUT1(30));
U9 : BUF_X1 port map( A => n148, Z => n127);
U10 : NOR2_X2 port map( A1 => n81, A2 => CTRL(0), ZN => n83);
U11 : OR3_X1 port map( A1 => n93, A2 => n94, A3 => n95, ZN => OUT1(16));
U12 : NAND3_X1 port map( A1 => n53, A2 => n54, A3 => n55, ZN => OUT1(15));
U13 : OR3_X1 port map( A1 => n112, A2 => n113, A3 => n114, ZN => OUT1(17));
U14 : OR3_X1 port map( A1 => n97, A2 => n98, A3 => n99, ZN => OUT1(26));
U16 : BUF_X2 port map( A => n61, Z => n125);
U17 : NAND2_X1 port map( A1 => n131, A2 => IN1(15), ZN => n53);
U18 : NAND2_X1 port map( A1 => n83, A2 => IN2(15), ZN => n54);
U19 : NAND2_X1 port map( A1 => n127, A2 => IN0(15), ZN => n55);
U20 : AOI222_X1 port map( A1 => n57, A2 => IN1(29), B1 => n128, B2 =>
IN0(29), C1 => n125, C2 => IN2(29), ZN => n143);
U22 : AOI222_X1 port map( A1 => n57, A2 => IN1(31), B1 => n128, B2 =>
IN0(31), C1 => n125, C2 => IN2(31), ZN => n145);
U23 : CLKBUF_X1 port map( A => n129, Z => n57);
U24 : BUF_X1 port map( A => n149, Z => n131);
U25 : NOR2_X1 port map( A1 => n64, A2 => CTRL(0), ZN => n61);
U26 : BUF_X2 port map( A => n61, Z => n63);
U27 : NAND2_X1 port map( A1 => n63, A2 => IN2(0), ZN => n68);
U28 : NAND2_X1 port map( A1 => n125, A2 => IN2(1), ZN => n70);
U29 : NAND2_X1 port map( A1 => n125, A2 => IN2(21), ZN => n90);
U30 : NAND2_X1 port map( A1 => n125, A2 => IN2(13), ZN => n124);
U31 : AND2_X1 port map( A1 => n63, A2 => IN2(16), ZN => n95);
U32 : AOI222_X1 port map( A1 => n130, A2 => IN1(4), B1 => n127, B2 => IN0(4)
, C1 => n63, C2 => IN2(4), ZN => n147);
U33 : AOI222_X1 port map( A1 => n71, A2 => IN1(19), B1 => n127, B2 =>
IN0(19), C1 => n63, C2 => IN2(19), ZN => n136);
U34 : NAND2_X1 port map( A1 => n125, A2 => IN2(8), ZN => n85);
U35 : NAND3_X1 port map( A1 => n66, A2 => n68, A3 => n65, ZN => OUT1(0));
U36 : INV_X1 port map( A => CTRL(1), ZN => n64);
U37 : NAND2_X1 port map( A1 => n131, A2 => IN1(0), ZN => n65);
U38 : NAND2_X1 port map( A1 => n128, A2 => IN0(0), ZN => n66);
U39 : AOI22_X1 port map( A1 => n131, A2 => IN1(1), B1 => n127, B2 => IN0(1),
ZN => n69);
U40 : NAND2_X1 port map( A1 => n69, A2 => n70, ZN => OUT1(1));
U41 : INV_X1 port map( A => n146, ZN => OUT1(3));
U42 : AOI222_X1 port map( A1 => n130, A2 => IN1(28), B1 => n126, B2 =>
IN0(28), C1 => n83, C2 => IN2(28), ZN => n142);
U43 : BUF_X2 port map( A => n149, Z => n71);
U44 : NOR2_X2 port map( A1 => CTRL(1), A2 => CTRL(0), ZN => n148);
U45 : CLKBUF_X3 port map( A => n148, Z => n126);
U46 : BUF_X2 port map( A => n149, Z => n130);
U47 : AND2_X2 port map( A1 => CTRL(0), A2 => n82, ZN => n149);
U48 : BUF_X2 port map( A => n149, Z => n129);
U49 : INV_X1 port map( A => n138, ZN => OUT1(24));
U50 : INV_X1 port map( A => n139, ZN => OUT1(25));
U51 : AND2_X1 port map( A1 => n83, A2 => IN2(26), ZN => n99);
U52 : AND2_X1 port map( A1 => n127, A2 => IN0(26), ZN => n98);
U53 : AND2_X1 port map( A1 => n129, A2 => IN1(26), ZN => n97);
U54 : INV_X1 port map( A => n141, ZN => OUT1(27));
U55 : INV_X1 port map( A => n142, ZN => OUT1(28));
U56 : INV_X1 port map( A => n137, ZN => OUT1(20));
U57 : AND2_X1 port map( A1 => n129, A2 => IN1(12), ZN => n96);
U58 : INV_X1 port map( A => n147, ZN => OUT1(4));
U59 : INV_X1 port map( A => n144, ZN => OUT1(2));
U60 : INV_X1 port map( A => n136, ZN => OUT1(19));
U61 : AND2_X1 port map( A1 => n127, A2 => IN0(16), ZN => n94);
U62 : AND2_X1 port map( A1 => n130, A2 => IN1(16), ZN => n93);
U63 : AND2_X1 port map( A1 => n83, A2 => IN2(17), ZN => n114);
U64 : AND2_X1 port map( A1 => n127, A2 => IN0(17), ZN => n113);
U65 : AND2_X1 port map( A1 => n129, A2 => IN1(17), ZN => n112);
U66 : INV_X1 port map( A => n135, ZN => OUT1(18));
U67 : INV_X1 port map( A => CTRL(1), ZN => n81);
U68 : INV_X1 port map( A => CTRL(1), ZN => n82);
U69 : INV_X1 port map( A => n132, ZN => OUT1(10));
U70 : NAND3_X1 port map( A1 => n106, A2 => n107, A3 => n108, ZN => OUT1(6));
U71 : NAND3_X1 port map( A1 => n109, A2 => n110, A3 => n111, ZN => OUT1(7));
U72 : NAND3_X1 port map( A1 => n119, A2 => n120, A3 => n121, ZN => OUT1(9));
U73 : NAND3_X1 port map( A1 => n115, A2 => n116, A3 => n117, ZN => OUT1(14))
;
U74 : NAND3_X1 port map( A1 => n100, A2 => n101, A3 => n102, ZN => OUT1(11))
;
U75 : NAND3_X1 port map( A1 => n122, A2 => n123, A3 => n124, ZN => OUT1(13))
;
U76 : NAND3_X1 port map( A1 => n103, A2 => n104, A3 => n105, ZN => OUT1(5));
U77 : AOI222_X1 port map( A1 => n129, A2 => IN1(25), B1 => n128, B2 =>
IN0(25), C1 => n125, C2 => IN2(25), ZN => n139);
U78 : AOI222_X1 port map( A1 => n71, A2 => IN1(3), B1 => n126, B2 => IN0(3),
C1 => n83, C2 => IN2(3), ZN => n146);
U79 : AOI222_X1 port map( A1 => n130, A2 => IN1(18), B1 => n126, B2 =>
IN0(18), C1 => n63, C2 => IN2(18), ZN => n135);
U80 : NAND3_X1 port map( A1 => n84, A2 => n85, A3 => n86, ZN => OUT1(8));
U81 : NAND2_X1 port map( A1 => n130, A2 => IN1(8), ZN => n84);
U82 : NAND2_X1 port map( A1 => n126, A2 => IN0(8), ZN => n86);
U83 : NAND3_X1 port map( A1 => n87, A2 => n88, A3 => n89, ZN => OUT1(22));
U84 : NAND2_X1 port map( A1 => n125, A2 => IN2(22), ZN => n87);
U85 : NAND2_X1 port map( A1 => n71, A2 => IN1(22), ZN => n88);
U86 : NAND2_X1 port map( A1 => n126, A2 => IN0(22), ZN => n89);
U87 : NAND3_X1 port map( A1 => n90, A2 => n91, A3 => n92, ZN => OUT1(21));
U88 : NAND2_X1 port map( A1 => n71, A2 => IN1(21), ZN => n91);
U89 : NAND2_X1 port map( A1 => n126, A2 => IN0(21), ZN => n92);
U90 : NAND2_X1 port map( A1 => n71, A2 => IN1(11), ZN => n100);
U91 : NAND2_X1 port map( A1 => n126, A2 => IN0(11), ZN => n101);
U92 : NAND2_X1 port map( A1 => n125, A2 => IN2(11), ZN => n102);
U93 : NAND2_X1 port map( A1 => n129, A2 => IN1(5), ZN => n103);
U94 : NAND2_X1 port map( A1 => n126, A2 => IN0(5), ZN => n104);
U95 : NAND2_X1 port map( A1 => n63, A2 => IN2(5), ZN => n105);
U96 : NAND2_X1 port map( A1 => n129, A2 => IN1(6), ZN => n106);
U97 : NAND2_X1 port map( A1 => n128, A2 => IN0(6), ZN => n107);
U98 : NAND2_X1 port map( A1 => n83, A2 => IN2(6), ZN => n108);
U99 : NAND2_X1 port map( A1 => n130, A2 => IN1(7), ZN => n109);
U100 : NAND2_X1 port map( A1 => n126, A2 => IN0(7), ZN => n110);
U101 : NAND2_X1 port map( A1 => n83, A2 => IN2(7), ZN => n111);
U102 : NAND2_X1 port map( A1 => n129, A2 => IN1(14), ZN => n115);
U103 : NAND2_X1 port map( A1 => n128, A2 => IN0(14), ZN => n116);
U104 : NAND2_X1 port map( A1 => n125, A2 => IN2(14), ZN => n117);
U105 : NAND2_X1 port map( A1 => n129, A2 => IN1(9), ZN => n119);
U106 : NAND2_X1 port map( A1 => n128, A2 => IN0(9), ZN => n120);
U107 : NAND2_X1 port map( A1 => n125, A2 => IN2(9), ZN => n121);
U108 : NAND2_X1 port map( A1 => n130, A2 => IN1(13), ZN => n122);
U109 : NAND2_X1 port map( A1 => n126, A2 => IN0(13), ZN => n123);
U110 : AOI222_X1 port map( A1 => n130, A2 => IN1(24), B1 => n128, B2 =>
IN0(24), C1 => n125, C2 => IN2(24), ZN => n138);
U111 : AOI222_X1 port map( A1 => n71, A2 => IN1(2), B1 => n126, B2 => IN0(2)
, C1 => n125, C2 => IN2(2), ZN => n144);
U112 : AOI222_X1 port map( A1 => n71, A2 => IN1(27), B1 => n126, B2 =>
IN0(27), C1 => n83, C2 => IN2(27), ZN => n141);
U113 : AOI222_X1 port map( A1 => n130, A2 => IN1(20), B1 => n127, B2 =>
IN0(20), C1 => n83, C2 => IN2(20), ZN => n137);
U114 : AOI222_X1 port map( A1 => n129, A2 => IN1(10), B1 => n127, B2 =>
IN0(10), C1 => n83, C2 => IN2(10), ZN => n132);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_1 is
port( IN0, IN1 : in std_logic_vector (31 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (31 downto 0));
end mux21_1;
architecture SYN_Bhe of mux21_1 is
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
signal n1 : std_logic;
begin
U1 : MUX2_X1 port map( A => IN0(9), B => IN1(9), S => CTRL, Z => OUT1(9));
U2 : MUX2_X1 port map( A => IN0(8), B => IN1(8), S => CTRL, Z => OUT1(8));
U3 : MUX2_X1 port map( A => IN0(7), B => IN1(7), S => CTRL, Z => OUT1(7));
U4 : MUX2_X1 port map( A => IN0(6), B => IN1(6), S => CTRL, Z => OUT1(6));
U5 : MUX2_X1 port map( A => IN0(5), B => IN1(5), S => CTRL, Z => OUT1(5));
U6 : MUX2_X1 port map( A => IN0(4), B => IN1(4), S => CTRL, Z => OUT1(4));
U7 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
U8 : MUX2_X1 port map( A => IN0(31), B => IN1(31), S => CTRL, Z => OUT1(31))
;
U9 : MUX2_X1 port map( A => IN0(30), B => IN1(30), S => CTRL, Z => OUT1(30))
;
U10 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U12 : MUX2_X1 port map( A => IN0(28), B => IN1(28), S => CTRL, Z => OUT1(28)
);
U13 : MUX2_X1 port map( A => IN0(27), B => IN1(27), S => CTRL, Z => OUT1(27)
);
U14 : MUX2_X1 port map( A => IN0(26), B => IN1(26), S => CTRL, Z => OUT1(26)
);
U15 : MUX2_X1 port map( A => IN0(25), B => IN1(25), S => CTRL, Z => OUT1(25)
);
U16 : MUX2_X1 port map( A => IN0(24), B => IN1(24), S => CTRL, Z => OUT1(24)
);
U17 : MUX2_X1 port map( A => IN0(23), B => IN1(23), S => CTRL, Z => OUT1(23)
);
U18 : MUX2_X1 port map( A => IN0(22), B => IN1(22), S => CTRL, Z => OUT1(22)
);
U19 : MUX2_X1 port map( A => IN0(21), B => IN1(21), S => CTRL, Z => OUT1(21)
);
U20 : MUX2_X1 port map( A => IN0(20), B => IN1(20), S => CTRL, Z => OUT1(20)
);
U21 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
U22 : MUX2_X1 port map( A => IN0(19), B => IN1(19), S => CTRL, Z => OUT1(19)
);
U23 : MUX2_X1 port map( A => IN0(18), B => IN1(18), S => CTRL, Z => OUT1(18)
);
U24 : MUX2_X1 port map( A => IN0(17), B => IN1(17), S => CTRL, Z => OUT1(17)
);
U25 : MUX2_X1 port map( A => IN0(16), B => IN1(16), S => CTRL, Z => OUT1(16)
);
U26 : MUX2_X1 port map( A => IN0(15), B => IN1(15), S => CTRL, Z => OUT1(15)
);
U27 : MUX2_X1 port map( A => IN0(14), B => IN1(14), S => CTRL, Z => OUT1(14)
);
U28 : MUX2_X1 port map( A => IN0(13), B => IN1(13), S => CTRL, Z => OUT1(13)
);
U29 : MUX2_X1 port map( A => IN0(12), B => IN1(12), S => CTRL, Z => OUT1(12)
);
U30 : MUX2_X1 port map( A => IN0(11), B => IN1(11), S => CTRL, Z => OUT1(11)
);
U31 : MUX2_X1 port map( A => IN0(10), B => IN1(10), S => CTRL, Z => OUT1(10)
);
U11 : MUX2_X1 port map( A => IN0(29), B => IN1(29), S => CTRL, Z => OUT1(29)
);
U32 : INV_X1 port map( A => IN0(0), ZN => n1);
U33 : NOR2_X1 port map( A1 => CTRL, A2 => n1, ZN => OUT1(0));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity FA_0 is
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end FA_0;
architecture SYN_BEHAVIORAL of FA_0 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
begin
U1 : AND2_X1 port map( A1 => B, A2 => A, ZN => Co);
U2 : XOR2_X1 port map( A => B, B => A, Z => S);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_SIZE4_0 is
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end mux21_SIZE4_0;
architecture SYN_Bhe of mux21_SIZE4_0 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
begin
U2 : MUX2_X1 port map( A => IN0(2), B => IN1(2), S => CTRL, Z => OUT1(2));
U3 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
U4 : MUX2_X1 port map( A => IN0(0), B => IN1(0), S => CTRL, Z => OUT1(0));
U1 : MUX2_X1 port map( A => IN0(3), B => IN1(3), S => CTRL, Z => OUT1(3));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity RCA_N4_0 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_N4_0;
architecture SYN_STRUCTURAL of RCA_N4_0 is
component FA_61
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_62
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_63
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
component FA_0
port( A, B, Ci : in std_logic; S, Co : out std_logic);
end component;
signal n1, CTMP_3_port, CTMP_2_port, CTMP_1_port, net561330 : std_logic;
begin
FAI_1 : FA_0 port map( A => A(0), B => B(0), Ci => n1, S => S(0), Co =>
CTMP_1_port);
FAI_2 : FA_63 port map( A => A(1), B => B(1), Ci => CTMP_1_port, S => S(1),
Co => CTMP_2_port);
FAI_3 : FA_62 port map( A => A(2), B => B(2), Ci => CTMP_2_port, S => S(2),
Co => CTMP_3_port);
FAI_4 : FA_61 port map( A => A(3), B => B(3), Ci => CTMP_3_port, S => S(3),
Co => net561330);
n1 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_sel_gen_N4_0 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end carry_sel_gen_N4_0;
architecture SYN_STRUCTURAL of carry_sel_gen_N4_0 is
component mux21_SIZE4_0
port( IN0, IN1 : in std_logic_vector (3 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (3 downto 0));
end component;
component RCA_N4_15
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_N4_0
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, nocarry_sum_to_mux_3_port,
nocarry_sum_to_mux_2_port, nocarry_sum_to_mux_1_port,
nocarry_sum_to_mux_0_port, carry_sum_to_mux_3_port,
carry_sum_to_mux_2_port, carry_sum_to_mux_1_port, carry_sum_to_mux_0_port
, net561328, net561329 : std_logic;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
rca_nocarry : RCA_N4_0 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
nocarry_sum_to_mux_3_port, S(2) =>
nocarry_sum_to_mux_2_port, S(1) =>
nocarry_sum_to_mux_1_port, S(0) =>
nocarry_sum_to_mux_0_port, Co => net561329);
rca_carry : RCA_N4_15 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
carry_sum_to_mux_3_port, S(2) =>
carry_sum_to_mux_2_port, S(1) =>
carry_sum_to_mux_1_port, S(0) =>
carry_sum_to_mux_0_port, Co => net561328);
outmux : mux21_SIZE4_0 port map( IN0(3) => nocarry_sum_to_mux_3_port, IN0(2)
=> nocarry_sum_to_mux_2_port, IN0(1) =>
nocarry_sum_to_mux_1_port, IN0(0) =>
nocarry_sum_to_mux_0_port, IN1(3) =>
carry_sum_to_mux_3_port, IN1(2) =>
carry_sum_to_mux_2_port, IN1(1) =>
carry_sum_to_mux_1_port, IN1(0) =>
carry_sum_to_mux_0_port, CTRL => Ci, OUT1(3) => S(3)
, OUT1(2) => S(2), OUT1(1) => S(1), OUT1(0) => S(0))
;
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_0 is
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic);
end pg_0;
architecture SYN_beh of pg_0 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2, n3 : std_logic;
begin
U1 : AND2_X1 port map( A1 => p, A2 => p_prec, ZN => p_out);
U2 : INV_X1 port map( A => g, ZN => n3);
U3 : NAND2_X1 port map( A1 => p, A2 => g_prec, ZN => n2);
U4 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity g_0 is
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end g_0;
architecture SYN_beh of g_0 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal n2 : std_logic;
begin
U1 : AOI21_X1 port map( B1 => p, B2 => g_prec, A => g, ZN => n2);
U2 : INV_X1 port map( A => n2, ZN => g_out);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity pg_net_0 is
port( a, b : in std_logic; g_out, p_out : out std_logic);
end pg_net_0;
architecture SYN_beh of pg_net_0 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n1, n2 : std_logic;
begin
U1 : NOR2_X1 port map( A1 => n2, A2 => n1, ZN => g_out);
U2 : XNOR2_X1 port map( A => n1, B => b, ZN => p_out);
U3 : INV_X1 port map( A => a, ZN => n1);
U4 : INV_X1 port map( A => b, ZN => n2);
end SYN_beh;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shift_thirdLevel is
port( sel : in std_logic_vector (2 downto 0); A : in std_logic_vector (38
downto 0); Y : out std_logic_vector (31 downto 0));
end shift_thirdLevel;
architecture SYN_behav of shift_thirdLevel is
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component OAI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component OAI222_X1
port( A1, A2, B1, B2, C1, C2 : in std_logic; ZN : out std_logic);
end component;
signal n17, n18, n20, n21, n22, n23, n24, n25, n26, n28, n29, n31, n32, n33,
n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n48, n49
, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63,
n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78
, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92,
n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117,
n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129,
n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, n140, n141 :
std_logic;
begin
U144 : AOI22_X1 port map( A1 => n135, A2 => A(0), B1 => n40, B2 => A(2), ZN
=> n129);
U140 : AOI22_X1 port map( A1 => n137, A2 => A(4), B1 => n23, B2 => A(6), ZN
=> n130);
U137 : OAI22_X1 port map( A1 => A(1), A2 => n134, B1 => A(3), B2 => n26, ZN
=> n132);
U136 : AOI21_X1 port map( B1 => n23, B2 => n36, A => n132, ZN => n131);
U135 : OAI21_X1 port map( B1 => A(5), B2 => n136, A => n131, ZN => n93);
U134 : OAI222_X1 port map( A1 => n141, A2 => n129, B1 => n141, B2 => n130,
C1 => n138, C2 => n93, ZN => Y(0));
U29 : AOI22_X1 port map( A1 => n135, A2 => A(32), B1 => n40, B2 => A(34), ZN
=> n49);
U28 : AOI22_X1 port map( A1 => n137, A2 => A(36), B1 => n23, B2 => A(38), ZN
=> n50);
U33 : OAI22_X1 port map( A1 => A(33), A2 => n26, B1 => A(37), B2 => n33, ZN
=> n55);
U32 : AOI21_X1 port map( B1 => n135, B2 => n54, A => n55, ZN => n53);
U31 : OAI21_X1 port map( B1 => A(35), B2 => n136, A => n53, ZN => n51);
U27 : OAI222_X1 port map( A1 => n138, A2 => n49, B1 => n138, B2 => n50, C1
=> n51, C2 => n141, ZN => Y(31));
U93 : OAI22_X1 port map( A1 => A(19), A2 => n134, B1 => A(21), B2 => n26, ZN
=> n101);
U92 : AOI21_X1 port map( B1 => n23, B2 => n78, A => n101, ZN => n100);
U91 : OAI21_X1 port map( B1 => A(23), B2 => n136, A => n100, ZN => n96);
U89 : OAI22_X1 port map( A1 => A(20), A2 => n134, B1 => A(22), B2 => n26, ZN
=> n98);
U88 : AOI21_X1 port map( B1 => n137, B2 => n82, A => n98, ZN => n97);
U87 : OAI21_X1 port map( B1 => A(26), B2 => n33, A => n97, ZN => n90);
U86 : AOI22_X1 port map( A1 => sel(0), A2 => n96, B1 => n90, B2 => n140, ZN
=> Y(19));
U80 : OAI22_X1 port map( A1 => A(21), A2 => n134, B1 => A(23), B2 => n26, ZN
=> n92);
U79 : AOI21_X1 port map( B1 => n137, B2 => n78, A => n92, ZN => n91);
U78 : OAI21_X1 port map( B1 => A(27), B2 => n33, A => n91, ZN => n87);
U77 : AOI22_X1 port map( A1 => n139, A2 => n90, B1 => n87, B2 => n140, ZN =>
Y(20));
U76 : OAI22_X1 port map( A1 => A(22), A2 => n134, B1 => A(28), B2 => n33, ZN
=> n89);
U75 : AOI21_X1 port map( B1 => n40, B2 => n82, A => n89, ZN => n88);
U74 : OAI21_X1 port map( B1 => A(26), B2 => n21, A => n88, ZN => n84);
U73 : AOI22_X1 port map( A1 => n139, A2 => n87, B1 => n84, B2 => n140, ZN =>
Y(21));
U38 : OAI22_X1 port map( A1 => A(5), A2 => n26, B1 => A(3), B2 => n134, ZN
=> n58);
U37 : AOI21_X1 port map( B1 => n137, B2 => n36, A => n58, ZN => n57);
U36 : OAI21_X1 port map( B1 => A(9), B2 => n33, A => n57, ZN => n45);
U26 : OAI22_X1 port map( A1 => A(6), A2 => n26, B1 => A(4), B2 => n134, ZN
=> n48);
U25 : AOI21_X1 port map( B1 => n137, B2 => n31, A => n48, ZN => n46);
U24 : OAI21_X1 port map( B1 => A(10), B2 => n33, A => n46, ZN => n42);
U23 : AOI22_X1 port map( A1 => n138, A2 => n45, B1 => n42, B2 => n140, ZN =>
Y(3));
U72 : OAI22_X1 port map( A1 => A(23), A2 => n134, B1 => A(29), B2 => n33, ZN
=> n86);
U71 : AOI21_X1 port map( B1 => n40, B2 => n78, A => n86, ZN => n85);
U70 : OAI21_X1 port map( B1 => A(27), B2 => n21, A => n85, ZN => n80);
U69 : AOI22_X1 port map( A1 => n139, A2 => n84, B1 => n80, B2 => n140, ZN =>
Y(22));
U68 : OAI22_X1 port map( A1 => A(26), A2 => n26, B1 => A(30), B2 => n33, ZN
=> n83);
U67 : AOI21_X1 port map( B1 => n135, B2 => n82, A => n83, ZN => n81);
U66 : OAI21_X1 port map( B1 => A(28), B2 => n136, A => n81, ZN => n76);
U64 : OAI22_X1 port map( A1 => A(27), A2 => n26, B1 => A(31), B2 => n33, ZN
=> n79);
U63 : AOI21_X1 port map( B1 => n135, B2 => n78, A => n79, ZN => n77);
U62 : OAI21_X1 port map( B1 => A(29), B2 => n136, A => n77, ZN => n73);
U61 : AOI22_X1 port map( A1 => sel(0), A2 => n76, B1 => n73, B2 => n140, ZN
=> Y(24));
U111 : OAI22_X1 port map( A1 => A(15), A2 => n134, B1 => A(21), B2 => n33,
ZN => n115);
U110 : AOI21_X1 port map( B1 => n40, B2 => n107, A => n115, ZN => n114);
U109 : OAI21_X1 port map( B1 => A(19), B2 => n21, A => n114, ZN => n109);
U107 : OAI22_X1 port map( A1 => A(18), A2 => n26, B1 => A(22), B2 => n33, ZN
=> n112);
U106 : AOI21_X1 port map( B1 => n135, B2 => n111, A => n112, ZN => n110);
U105 : OAI21_X1 port map( B1 => A(20), B2 => n21, A => n110, ZN => n105);
U104 : AOI22_X1 port map( A1 => n139, A2 => n109, B1 => n105, B2 => n141, ZN
=> Y(15));
U10 : OAI22_X1 port map( A1 => A(14), A2 => n33, B1 => A(10), B2 => n26, ZN
=> n32);
U9 : AOI21_X1 port map( B1 => n135, B2 => n31, A => n32, ZN => n29);
U8 : OAI21_X1 port map( B1 => A(12), B2 => n136, A => n29, ZN => n20);
U5 : OAI22_X1 port map( A1 => A(11), A2 => n26, B1 => A(9), B2 => n134, ZN
=> n25);
U4 : AOI21_X1 port map( B1 => n23, B2 => n24, A => n25, ZN => n22);
U3 : OAI21_X1 port map( B1 => A(13), B2 => n136, A => n22, ZN => n17);
U2 : AOI22_X1 port map( A1 => n138, A2 => n20, B1 => n17, B2 => n140, ZN =>
Y(8));
U18 : OAI22_X1 port map( A1 => A(6), A2 => n134, B1 => A(12), B2 => n33, ZN
=> n41);
U17 : AOI21_X1 port map( B1 => n40, B2 => n31, A => n41, ZN => n39);
U16 : OAI21_X1 port map( B1 => A(10), B2 => n136, A => n39, ZN => n34);
U14 : OAI22_X1 port map( A1 => A(13), A2 => n33, B1 => A(9), B2 => n26, ZN
=> n37);
U13 : AOI21_X1 port map( B1 => n135, B2 => n36, A => n37, ZN => n35);
U12 : OAI21_X1 port map( B1 => A(11), B2 => n136, A => n35, ZN => n28);
U11 : AOI22_X1 port map( A1 => n138, A2 => n34, B1 => n28, B2 => n140, ZN =>
Y(6));
U59 : OAI22_X1 port map( A1 => A(26), A2 => n134, B1 => A(28), B2 => n26, ZN
=> n75);
U58 : AOI21_X1 port map( B1 => n23, B2 => n61, A => n75, ZN => n74);
U57 : OAI21_X1 port map( B1 => A(30), B2 => n136, A => n74, ZN => n70);
U56 : AOI22_X1 port map( A1 => sel(0), A2 => n73, B1 => n70, B2 => n140, ZN
=> Y(25));
U103 : OAI22_X1 port map( A1 => A(19), A2 => n26, B1 => A(23), B2 => n33, ZN
=> n108);
U102 : AOI21_X1 port map( B1 => n135, B2 => n107, A => n108, ZN => n106);
U101 : OAI21_X1 port map( B1 => A(21), B2 => n21, A => n106, ZN => n102);
U98 : OAI22_X1 port map( A1 => A(18), A2 => n134, B1 => A(20), B2 => n26, ZN
=> n104);
U97 : AOI21_X1 port map( B1 => n23, B2 => n82, A => n104, ZN => n103);
U96 : OAI21_X1 port map( B1 => A(22), B2 => n21, A => n103, ZN => n99);
U95 : AOI22_X1 port map( A1 => n139, A2 => n102, B1 => n99, B2 => n140, ZN
=> Y(17));
U123 : OAI22_X1 port map( A1 => A(14), A2 => n26, B1 => A(12), B2 => n134,
ZN => n124);
U122 : AOI21_X1 port map( B1 => n137, B2 => n111, A => n124, ZN => n123);
U121 : OAI21_X1 port map( B1 => A(18), B2 => n33, A => n123, ZN => n119);
U119 : OAI22_X1 port map( A1 => A(15), A2 => n26, B1 => A(13), B2 => n134,
ZN => n121);
U118 : AOI21_X1 port map( B1 => n137, B2 => n107, A => n121, ZN => n120);
U117 : OAI21_X1 port map( B1 => A(19), B2 => n33, A => n120, ZN => n116);
U116 : AOI22_X1 port map( A1 => n139, A2 => n119, B1 => n116, B2 => n141, ZN
=> Y(12));
U100 : AOI22_X1 port map( A1 => n139, A2 => n105, B1 => n102, B2 => n140, ZN
=> Y(16));
U50 : OAI22_X1 port map( A1 => A(28), A2 => n134, B1 => A(30), B2 => n26, ZN
=> n69);
U49 : AOI21_X1 port map( B1 => n137, B2 => n61, A => n69, ZN => n68);
U48 : OAI21_X1 port map( B1 => A(34), B2 => n33, A => n68, ZN => n63);
U46 : OAI22_X1 port map( A1 => A(31), A2 => n26, B1 => A(35), B2 => n33, ZN
=> n66);
U45 : AOI21_X1 port map( B1 => n135, B2 => n65, A => n66, ZN => n64);
U44 : OAI21_X1 port map( B1 => A(33), B2 => n136, A => n64, ZN => n59);
U43 : AOI22_X1 port map( A1 => n139, A2 => n63, B1 => n59, B2 => n140, ZN =>
Y(28));
U22 : OAI22_X1 port map( A1 => A(5), A2 => n134, B1 => A(11), B2 => n33, ZN
=> n44);
U21 : AOI21_X1 port map( B1 => n40, B2 => n36, A => n44, ZN => n43);
U20 : OAI21_X1 port map( B1 => A(9), B2 => n136, A => n43, ZN => n38);
U19 : AOI22_X1 port map( A1 => n138, A2 => n42, B1 => n38, B2 => n140, ZN =>
Y(4));
U54 : OAI22_X1 port map( A1 => A(27), A2 => n134, B1 => A(33), B2 => n33, ZN
=> n72);
U53 : AOI21_X1 port map( B1 => n40, B2 => n65, A => n72, ZN => n71);
U52 : OAI21_X1 port map( B1 => A(31), B2 => n136, A => n71, ZN => n67);
U47 : AOI22_X1 port map( A1 => n139, A2 => n67, B1 => n63, B2 => n140, ZN =>
Y(27));
U15 : AOI22_X1 port map( A1 => n138, A2 => n38, B1 => n34, B2 => n140, ZN =>
Y(5));
U115 : OAI22_X1 port map( A1 => A(14), A2 => n134, B1 => A(20), B2 => n33,
ZN => n118);
U114 : AOI21_X1 port map( B1 => n40, B2 => n111, A => n118, ZN => n117);
U113 : OAI21_X1 port map( B1 => A(18), B2 => n21, A => n117, ZN => n113);
U112 : AOI22_X1 port map( A1 => n139, A2 => n116, B1 => n113, B2 => n141, ZN
=> Y(13));
U132 : OAI22_X1 port map( A1 => A(12), A2 => n26, B1 => A(10), B2 => n134,
ZN => n128);
U131 : AOI21_X1 port map( B1 => n23, B2 => n111, A => n128, ZN => n127);
U130 : OAI21_X1 port map( B1 => A(14), B2 => n21, A => n127, ZN => n18);
U1 : AOI22_X1 port map( A1 => n139, A2 => n17, B1 => n18, B2 => n140, ZN =>
Y(9));
U7 : AOI22_X1 port map( A1 => n138, A2 => n28, B1 => n20, B2 => n140, ZN =>
Y(7));
U108 : AOI22_X1 port map( A1 => n139, A2 => n113, B1 => n109, B2 => n141, ZN
=> Y(14));
U90 : AOI22_X1 port map( A1 => n139, A2 => n99, B1 => n96, B2 => n140, ZN =>
Y(18));
U65 : AOI22_X1 port map( A1 => sel(0), A2 => n80, B1 => n76, B2 => n140, ZN
=> Y(23));
U51 : AOI22_X1 port map( A1 => n139, A2 => n70, B1 => n67, B2 => n140, ZN =>
Y(26));
U42 : OAI22_X1 port map( A1 => A(30), A2 => n134, B1 => A(36), B2 => n33, ZN
=> n62);
U41 : AOI21_X1 port map( B1 => n40, B2 => n61, A => n62, ZN => n60);
U40 : OAI21_X1 port map( B1 => A(34), B2 => n136, A => n60, ZN => n52);
U39 : AOI22_X1 port map( A1 => n138, A2 => n59, B1 => n52, B2 => n140, ZN =>
Y(29));
U84 : OAI22_X1 port map( A1 => A(4), A2 => n26, B1 => A(2), B2 => n134, ZN
=> n95);
U83 : AOI21_X1 port map( B1 => n23, B2 => n31, A => n95, ZN => n94);
U82 : OAI21_X1 port map( B1 => A(6), B2 => n136, A => n94, ZN => n56);
U35 : AOI22_X1 port map( A1 => n138, A2 => n56, B1 => n45, B2 => n140, ZN =>
Y(2));
U81 : AOI22_X1 port map( A1 => sel(0), A2 => n93, B1 => n56, B2 => n140, ZN
=> Y(1));
U30 : AOI22_X1 port map( A1 => n138, A2 => n52, B1 => n51, B2 => n140, ZN =>
Y(30));
U128 : OAI22_X1 port map( A1 => A(13), A2 => n26, B1 => A(11), B2 => n134,
ZN => n126);
U127 : AOI21_X1 port map( B1 => n23, B2 => n107, A => n126, ZN => n125);
U126 : OAI21_X1 port map( B1 => A(15), B2 => n21, A => n125, ZN => n122);
U120 : AOI22_X1 port map( A1 => n139, A2 => n122, B1 => n119, B2 => n141, ZN
=> Y(11));
U125 : AOI22_X1 port map( A1 => n139, A2 => n18, B1 => n122, B2 => n141, ZN
=> Y(10));
U146 : INV_X1 port map( A => sel(2), ZN => n133);
U138 : INV_X1 port map( A => n40, ZN => n26);
U34 : INV_X1 port map( A => A(31), ZN => n54);
U124 : INV_X1 port map( A => n23, ZN => n33);
U94 : INV_X1 port map( A => A(25), ZN => n78);
U99 : INV_X1 port map( A => A(24), ZN => n82);
U85 : INV_X1 port map( A => A(8), ZN => n31);
U129 : INV_X1 port map( A => A(17), ZN => n107);
U133 : INV_X1 port map( A => A(16), ZN => n111);
U6 : INV_X1 port map( A => A(15), ZN => n24);
U60 : INV_X1 port map( A => A(32), ZN => n61);
U55 : INV_X1 port map( A => A(29), ZN => n65);
U139 : INV_X1 port map( A => A(7), ZN => n36);
U141 : INV_X1 port map( A => n135, ZN => n134);
U142 : BUF_X1 port map( A => sel(0), Z => n138);
U143 : BUF_X1 port map( A => sel(0), Z => n139);
U145 : INV_X1 port map( A => n138, ZN => n140);
U147 : INV_X1 port map( A => n137, ZN => n136);
U148 : INV_X1 port map( A => n21, ZN => n137);
U149 : NAND2_X1 port map( A1 => n133, A2 => sel(1), ZN => n21);
U150 : NOR2_X1 port map( A1 => sel(1), A2 => n133, ZN => n40);
U151 : AND2_X1 port map( A1 => sel(2), A2 => sel(1), ZN => n135);
U152 : INV_X1 port map( A => n139, ZN => n141);
U153 : NOR2_X1 port map( A1 => sel(2), A2 => sel(1), ZN => n23);
end SYN_behav;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shift_secondLevel is
port( sel : in std_logic_vector (1 downto 0); mask00, mask08, mask16 : in
std_logic_vector (38 downto 0); Y : out std_logic_vector (38 downto
0));
end shift_secondLevel;
architecture SYN_behav of shift_secondLevel is
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component NOR2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component BUF_X2
port( A : in std_logic; Z : out std_logic);
end component;
component AOI222_X1
port( A1, A2, B1, B2, C1, C2 : in std_logic; ZN : out std_logic);
end component;
signal n41, n42, n43, n44, n45, n47, n48, n49, n50, n51, n52, n53, n54, n55,
n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70
, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n46,
n84, n92 : std_logic;
begin
U79 : AOI222_X1 port map( A1 => n84, A2 => mask00(0), B1 => n43, B2 =>
mask16(0), C1 => n44, C2 => mask08(0), ZN => n82);
U35 : AOI222_X1 port map( A1 => n84, A2 => mask00(2), B1 => n43, B2 =>
mask16(2), C1 => n92, C2 => mask08(2), ZN => n60);
U13 : AOI222_X1 port map( A1 => n84, A2 => mask00(4), B1 => n43, B2 =>
mask16(4), C1 => n92, C2 => mask08(4), ZN => n49);
U9 : AOI222_X1 port map( A1 => n84, A2 => mask00(6), B1 => n43, B2 =>
mask16(6), C1 => n92, C2 => mask08(6), ZN => n47);
U11 : AOI222_X1 port map( A1 => n84, A2 => mask00(5), B1 => n43, B2 =>
mask16(5), C1 => n92, C2 => mask08(5), ZN => n48);
U57 : AOI222_X1 port map( A1 => n84, A2 => mask00(1), B1 => n43, B2 =>
mask16(1), C1 => n44, C2 => mask08(1), ZN => n71);
U15 : AOI222_X1 port map( A1 => n84, A2 => mask00(3), B1 => n43, B2 =>
mask16(3), C1 => n92, C2 => mask08(3), ZN => n50);
U29 : AOI222_X1 port map( A1 => n84, A2 => mask00(32), B1 => n43, B2 =>
mask16(32), C1 => n92, C2 => mask08(32), ZN => n57);
U25 : AOI222_X1 port map( A1 => n84, A2 => mask00(34), B1 => n43, B2 =>
mask16(34), C1 => n92, C2 => mask08(34), ZN => n55);
U21 : AOI222_X1 port map( A1 => n84, A2 => mask00(36), B1 => n43, B2 =>
mask16(36), C1 => n92, C2 => mask08(36), ZN => n53);
U17 : AOI222_X1 port map( A1 => n84, A2 => mask00(38), B1 => n43, B2 =>
mask16(38), C1 => n92, C2 => mask08(38), ZN => n51);
U23 : AOI222_X1 port map( A1 => n84, A2 => mask00(35), B1 => n43, B2 =>
mask16(35), C1 => n92, C2 => mask08(35), ZN => n54);
U31 : AOI222_X1 port map( A1 => n84, A2 => mask00(31), B1 => n43, B2 =>
mask16(31), C1 => n92, C2 => mask08(31), ZN => n58);
U27 : AOI222_X1 port map( A1 => n84, A2 => mask00(33), B1 => n43, B2 =>
mask16(33), C1 => n92, C2 => mask08(33), ZN => n56);
U19 : AOI222_X1 port map( A1 => n84, A2 => mask00(37), B1 => n43, B2 =>
mask16(37), C1 => n92, C2 => mask08(37), ZN => n52);
U49 : AOI222_X1 port map( A1 => n84, A2 => mask00(23), B1 => n43, B2 =>
mask16(23), C1 => n44, C2 => mask08(23), ZN => n67);
U45 : AOI222_X1 port map( A1 => n84, A2 => mask00(25), B1 => n43, B2 =>
mask16(25), C1 => n92, C2 => mask08(25), ZN => n65);
U59 : AOI222_X1 port map( A1 => n84, A2 => mask00(19), B1 => n43, B2 =>
mask16(19), C1 => n44, C2 => mask08(19), ZN => n72);
U53 : AOI222_X1 port map( A1 => n84, A2 => mask00(21), B1 => n43, B2 =>
mask16(21), C1 => n44, C2 => mask08(21), ZN => n69);
U43 : AOI222_X1 port map( A1 => n84, A2 => mask00(26), B1 => n43, B2 =>
mask16(26), C1 => n92, C2 => mask08(26), ZN => n64);
U47 : AOI222_X1 port map( A1 => n84, A2 => mask00(24), B1 => n43, B2 =>
mask16(24), C1 => n92, C2 => mask08(24), ZN => n66);
U55 : AOI222_X1 port map( A1 => n84, A2 => mask00(20), B1 => n43, B2 =>
mask16(20), C1 => n44, C2 => mask08(20), ZN => n70);
U51 : AOI222_X1 port map( A1 => n84, A2 => mask00(22), B1 => n43, B2 =>
mask16(22), C1 => n92, C2 => mask08(22), ZN => n68);
U41 : AOI222_X1 port map( A1 => n84, A2 => mask00(27), B1 => n43, B2 =>
mask16(27), C1 => n92, C2 => mask08(27), ZN => n63);
U39 : AOI222_X1 port map( A1 => n84, A2 => mask00(28), B1 => n43, B2 =>
mask16(28), C1 => n92, C2 => mask08(28), ZN => n62);
U3 : AOI222_X1 port map( A1 => n84, A2 => mask00(9), B1 => n43, B2 =>
mask16(9), C1 => n92, C2 => mask08(9), ZN => n41);
U77 : AOI222_X1 port map( A1 => n84, A2 => mask00(10), B1 => n43, B2 =>
mask16(10), C1 => n44, C2 => mask08(10), ZN => n81);
U5 : AOI222_X1 port map( A1 => n84, A2 => mask00(8), B1 => n43, B2 =>
mask16(8), C1 => n92, C2 => mask08(8), ZN => n45);
U37 : AOI222_X1 port map( A1 => n84, A2 => mask00(29), B1 => n43, B2 =>
mask16(29), C1 => n92, C2 => mask08(29), ZN => n61);
U33 : AOI222_X1 port map( A1 => n84, A2 => mask00(30), B1 => n43, B2 =>
mask16(30), C1 => n44, C2 => mask08(30), ZN => n59);
U63 : AOI222_X1 port map( A1 => n84, A2 => mask00(17), B1 => n43, B2 =>
mask16(17), C1 => n44, C2 => mask08(17), ZN => n74);
U67 : AOI222_X1 port map( A1 => n84, A2 => mask00(15), B1 => n43, B2 =>
mask16(15), C1 => n92, C2 => mask08(15), ZN => n76);
U65 : AOI222_X1 port map( A1 => n84, A2 => mask00(16), B1 => n43, B2 =>
mask16(16), C1 => n44, C2 => mask08(16), ZN => n75);
U61 : AOI222_X1 port map( A1 => n84, A2 => mask00(18), B1 => n43, B2 =>
mask16(18), C1 => n92, C2 => mask08(18), ZN => n73);
U73 : AOI222_X1 port map( A1 => n84, A2 => mask00(12), B1 => n43, B2 =>
mask16(12), C1 => n44, C2 => mask08(12), ZN => n79);
U69 : AOI222_X1 port map( A1 => n84, A2 => mask00(14), B1 => n43, B2 =>
mask16(14), C1 => n44, C2 => mask08(14), ZN => n77);
U71 : AOI222_X1 port map( A1 => n84, A2 => mask00(13), B1 => n43, B2 =>
mask16(13), C1 => n44, C2 => mask08(13), ZN => n78);
U75 : AOI222_X1 port map( A1 => n84, A2 => mask00(11), B1 => n43, B2 =>
mask16(11), C1 => n44, C2 => mask08(11), ZN => n80);
U78 : INV_X1 port map( A => n82, ZN => Y(0));
U34 : INV_X1 port map( A => n60, ZN => Y(2));
U12 : INV_X1 port map( A => n49, ZN => Y(4));
U8 : INV_X1 port map( A => n47, ZN => Y(6));
U10 : INV_X1 port map( A => n48, ZN => Y(5));
U56 : INV_X1 port map( A => n71, ZN => Y(1));
U14 : INV_X1 port map( A => n50, ZN => Y(3));
U28 : INV_X1 port map( A => n57, ZN => Y(32));
U24 : INV_X1 port map( A => n55, ZN => Y(34));
U20 : INV_X1 port map( A => n53, ZN => Y(36));
U16 : INV_X1 port map( A => n51, ZN => Y(38));
U22 : INV_X1 port map( A => n54, ZN => Y(35));
U30 : INV_X1 port map( A => n58, ZN => Y(31));
U26 : INV_X1 port map( A => n56, ZN => Y(33));
U18 : INV_X1 port map( A => n52, ZN => Y(37));
U48 : INV_X1 port map( A => n67, ZN => Y(23));
U44 : INV_X1 port map( A => n65, ZN => Y(25));
U58 : INV_X1 port map( A => n72, ZN => Y(19));
U52 : INV_X1 port map( A => n69, ZN => Y(21));
U42 : INV_X1 port map( A => n64, ZN => Y(26));
U46 : INV_X1 port map( A => n66, ZN => Y(24));
U54 : INV_X1 port map( A => n70, ZN => Y(20));
U50 : INV_X1 port map( A => n68, ZN => Y(22));
U40 : INV_X1 port map( A => n63, ZN => Y(27));
U38 : INV_X1 port map( A => n62, ZN => Y(28));
U2 : INV_X1 port map( A => n41, ZN => Y(9));
U76 : INV_X1 port map( A => n81, ZN => Y(10));
U4 : INV_X1 port map( A => n45, ZN => Y(8));
U36 : INV_X1 port map( A => n61, ZN => Y(29));
U32 : INV_X1 port map( A => n59, ZN => Y(30));
U62 : INV_X1 port map( A => n74, ZN => Y(17));
U66 : INV_X1 port map( A => n76, ZN => Y(15));
U64 : INV_X1 port map( A => n75, ZN => Y(16));
U60 : INV_X1 port map( A => n73, ZN => Y(18));
U72 : INV_X1 port map( A => n79, ZN => Y(12));
U68 : INV_X1 port map( A => n77, ZN => Y(14));
U70 : INV_X1 port map( A => n78, ZN => Y(13));
U74 : INV_X1 port map( A => n80, ZN => Y(11));
U6 : AOI222_X1 port map( A1 => n92, A2 => mask08(7), B1 => mask00(7), B2 =>
n84, C1 => mask16(7), C2 => n43, ZN => n46);
U7 : INV_X1 port map( A => n46, ZN => Y(7));
U80 : BUF_X2 port map( A => n42, Z => n84);
U81 : BUF_X1 port map( A => n44, Z => n92);
U82 : AND2_X2 port map( A1 => n83, A2 => sel(1), ZN => n43);
U83 : NOR2_X2 port map( A1 => sel(1), A2 => n83, ZN => n44);
U84 : INV_X1 port map( A => sel(0), ZN => n83);
U85 : NOR2_X1 port map( A1 => sel(1), A2 => sel(0), ZN => n42);
end SYN_behav;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shift_firstLevel is
port( A : in std_logic_vector (31 downto 0); sel : in std_logic_vector (1
downto 0); mask00, mask08, mask16 : out std_logic_vector (38 downto
0));
end shift_firstLevel;
architecture SYN_behav of shift_firstLevel is
component NOR2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component INV_X2
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
signal mask08_38_port, mask08_37_port, mask08_36_port, mask08_35_port,
mask08_34_port, mask08_33_port, mask08_32_port, mask08_31_port,
mask08_23_port, mask08_22_port, mask08_21_port, mask08_20_port,
mask08_19_port, mask08_18_port, mask08_17_port, mask08_16_port,
mask08_15_port, mask08_7_port, mask08_6_port, mask08_5_port,
mask08_4_port, mask08_3_port, mask08_2_port, mask08_1_port, mask08_0_port
, mask16_38_port, mask16_37_port, mask16_36_port, mask16_35_port,
mask16_34_port, mask16_33_port, mask16_32_port, mask16_31_port,
mask16_30_port, mask16_29_port, mask16_28_port, mask16_27_port,
mask16_26_port, mask16_25_port, mask16_24_port, mask16_23_port,
mask16_15_port, mask16_14_port, mask16_13_port, mask16_12_port,
mask16_11_port, mask16_10_port, mask16_9_port, mask16_8_port,
mask16_7_port, mask16_6_port, mask16_5_port, mask16_4_port, mask16_3_port
, mask16_2_port, mask16_1_port, mask16_0_port, n36, n37, n38, n39, n40,
n41, n42, n43, mask16_18_port, n45, n46, n47, n48, n49, n50, n51, n52,
n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67
, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81,
n82, n83, n84, n85, n88, n89, n90, n91, n92, n93, n94, n95, n86, n87, n96
: std_logic;
begin
mask08 <= ( mask08_38_port, mask08_37_port, mask08_36_port, mask08_35_port,
mask08_34_port, mask08_33_port, mask08_32_port, mask08_31_port,
mask16_38_port, mask16_37_port, mask16_36_port, mask16_35_port,
mask16_34_port, mask16_33_port, mask16_32_port, mask08_23_port,
mask08_22_port, mask08_21_port, mask08_20_port, mask08_19_port,
mask08_18_port, mask08_17_port, mask08_16_port, mask08_15_port,
mask16_6_port, mask16_5_port, mask16_4_port, mask16_3_port, mask16_2_port
, mask16_1_port, mask16_0_port, mask08_7_port, mask08_6_port,
mask08_5_port, mask08_4_port, mask08_3_port, mask08_2_port, mask08_1_port
, mask08_0_port );
mask16 <= ( mask16_38_port, mask16_37_port, mask16_36_port, mask16_35_port,
mask16_34_port, mask16_33_port, mask16_32_port, mask16_31_port,
mask16_30_port, mask16_29_port, mask16_28_port, mask16_27_port,
mask16_26_port, mask16_25_port, mask16_24_port, mask16_23_port,
mask16_18_port, mask16_18_port, mask16_18_port, mask16_18_port,
mask16_18_port, mask16_18_port, mask16_18_port, mask16_15_port,
mask16_14_port, mask16_13_port, mask16_12_port, mask16_11_port,
mask16_10_port, mask16_9_port, mask16_8_port, mask16_7_port,
mask16_6_port, mask16_5_port, mask16_4_port, mask16_3_port, mask16_2_port
, mask16_1_port, mask16_0_port );
U137 : NAND2_X1 port map( A1 => sel(0), A2 => A(16), ZN => n67);
U62 : NAND2_X1 port map( A1 => sel(0), A2 => A(8), ZN => n84);
U131 : NAND2_X1 port map( A1 => sel(0), A2 => A(18), ZN => n53);
U155 : NAND2_X1 port map( A1 => sel(0), A2 => A(10), ZN => n81);
U125 : NAND2_X1 port map( A1 => sel(0), A2 => A(20), ZN => n41);
U149 : NAND2_X1 port map( A1 => sel(0), A2 => A(12), ZN => n71);
U119 : NAND2_X1 port map( A1 => sel(0), A2 => A(22), ZN => n39);
U143 : NAND2_X1 port map( A1 => sel(0), A2 => A(14), ZN => n69);
U122 : NAND2_X1 port map( A1 => sel(0), A2 => A(21), ZN => n40);
U146 : NAND2_X1 port map( A1 => sel(0), A2 => A(13), ZN => n70);
U67 : NAND2_X1 port map( A1 => n87, A2 => A(0), ZN => n60);
U116 : NAND2_X1 port map( A1 => sel(0), A2 => A(23), ZN => n38);
U140 : NAND2_X1 port map( A1 => sel(0), A2 => A(15), ZN => n68);
U134 : NAND2_X1 port map( A1 => sel(0), A2 => A(17), ZN => n61);
U59 : NAND2_X1 port map( A1 => sel(0), A2 => A(9), ZN => n83);
U129 : NAND2_X1 port map( A1 => sel(0), A2 => A(19), ZN => n42);
U152 : NAND2_X1 port map( A1 => sel(0), A2 => A(11), ZN => n72);
U91 : NAND2_X1 port map( A1 => sel(0), A2 => A(31), ZN => n82);
U85 : AOI21_X1 port map( B1 => A(25), B2 => n85, A => mask16_18_port, ZN =>
n94);
U138 : NAND2_X1 port map( A1 => n85, A2 => A(9), ZN => n50);
U15 : NAND2_X1 port map( A1 => n50, A2 => n96, ZN => mask16_32_port);
U112 : NAND2_X1 port map( A1 => n87, A2 => A(17), ZN => n79);
U44 : NAND2_X1 port map( A1 => n79, A2 => n96, ZN => mask08_32_port);
U81 : AOI21_X1 port map( B1 => A(27), B2 => n85, A => mask16_18_port, ZN =>
n92);
U132 : NAND2_X1 port map( A1 => n87, A2 => A(11), ZN => n48);
U13 : NAND2_X1 port map( A1 => n48, A2 => n96, ZN => mask16_34_port);
U106 : NAND2_X1 port map( A1 => n87, A2 => A(19), ZN => n77);
U42 : NAND2_X1 port map( A1 => n77, A2 => n96, ZN => mask08_34_port);
U77 : AOI21_X1 port map( B1 => A(29), B2 => n85, A => mask16_18_port, ZN =>
n90);
U124 : NAND2_X1 port map( A1 => n87, A2 => A(13), ZN => n46);
U11 : NAND2_X1 port map( A1 => n46, A2 => n96, ZN => mask16_36_port);
U100 : NAND2_X1 port map( A1 => n87, A2 => A(21), ZN => n75);
U40 : NAND2_X1 port map( A1 => n75, A2 => n96, ZN => mask08_36_port);
U73 : AOI21_X1 port map( B1 => A(31), B2 => n85, A => mask16_18_port, ZN =>
n88);
U118 : NAND2_X1 port map( A1 => n87, A2 => A(15), ZN => n43);
U9 : NAND2_X1 port map( A1 => n43, A2 => n96, ZN => mask16_38_port);
U93 : NAND2_X1 port map( A1 => n85, A2 => A(23), ZN => n73);
U38 : NAND2_X1 port map( A1 => n73, A2 => n96, ZN => mask08_38_port);
U79 : AOI21_X1 port map( B1 => A(28), B2 => n85, A => mask16_18_port, ZN =>
n91);
U128 : NAND2_X1 port map( A1 => n87, A2 => A(12), ZN => n47);
U12 : NAND2_X1 port map( A1 => n47, A2 => n96, ZN => mask16_35_port);
U103 : NAND2_X1 port map( A1 => n87, A2 => A(20), ZN => n76);
U41 : NAND2_X1 port map( A1 => n76, A2 => n96, ZN => mask08_35_port);
U89 : AOI21_X1 port map( B1 => A(24), B2 => n85, A => mask16_15_port, ZN =>
n95);
U141 : NAND2_X1 port map( A1 => n87, A2 => A(8), ZN => n51);
U16 : NAND2_X1 port map( A1 => n51, A2 => n96, ZN => mask16_31_port);
U115 : NAND2_X1 port map( A1 => n87, A2 => A(16), ZN => n80);
U45 : NAND2_X1 port map( A1 => n80, A2 => n96, ZN => mask08_31_port);
U83 : AOI21_X1 port map( B1 => A(26), B2 => n85, A => mask16_18_port, ZN =>
n93);
U135 : NAND2_X1 port map( A1 => n85, A2 => A(10), ZN => n49);
U14 : NAND2_X1 port map( A1 => n49, A2 => n96, ZN => mask16_33_port);
U109 : NAND2_X1 port map( A1 => n87, A2 => A(18), ZN => n78);
U43 : NAND2_X1 port map( A1 => n78, A2 => n96, ZN => mask08_33_port);
U75 : AOI21_X1 port map( B1 => A(30), B2 => n85, A => mask16_18_port, ZN =>
n89);
U121 : NAND2_X1 port map( A1 => n87, A2 => A(14), ZN => n45);
U10 : NAND2_X1 port map( A1 => n45, A2 => n96, ZN => mask16_37_port);
U97 : NAND2_X1 port map( A1 => n87, A2 => A(22), ZN => n74);
U39 : NAND2_X1 port map( A1 => n74, A2 => n96, ZN => mask08_37_port);
U114 : NAND2_X1 port map( A1 => n38, A2 => n80, ZN => mask00(23));
U25 : NAND2_X1 port map( A1 => n96, A2 => n60, ZN => mask16_23_port);
U47 : NAND2_X1 port map( A1 => n51, A2 => n82, ZN => mask08_23_port);
U110 : NAND2_X1 port map( A1 => sel(0), A2 => A(25), ZN => n36);
U108 : NAND2_X1 port map( A1 => n36, A2 => n78, ZN => mask00(25));
U60 : NAND2_X1 port map( A1 => n85, A2 => A(2), ZN => n58);
U23 : NAND2_X1 port map( A1 => n96, A2 => n58, ZN => mask16_25_port);
U127 : NAND2_X1 port map( A1 => n42, A2 => n47, ZN => mask00(19));
U153 : NAND2_X1 port map( A1 => n85, A2 => A(4), ZN => n56);
U104 : NAND2_X1 port map( A1 => sel(0), A2 => A(27), ZN => n65);
U52 : NAND2_X1 port map( A1 => n56, A2 => n65, ZN => mask08_19_port);
U120 : NAND2_X1 port map( A1 => n40, A2 => n45, ZN => mask00(21));
U147 : NAND2_X1 port map( A1 => n85, A2 => A(6), ZN => n54);
U98 : NAND2_X1 port map( A1 => sel(0), A2 => A(29), ZN => n63);
U49 : NAND2_X1 port map( A1 => n54, A2 => n63, ZN => mask08_21_port);
U107 : NAND2_X1 port map( A1 => sel(0), A2 => A(26), ZN => n66);
U105 : NAND2_X1 port map( A1 => n66, A2 => n77, ZN => mask00(26));
U156 : NAND2_X1 port map( A1 => n87, A2 => A(3), ZN => n57);
U22 : NAND2_X1 port map( A1 => n57, A2 => n96, ZN => mask16_26_port);
U113 : NAND2_X1 port map( A1 => sel(0), A2 => A(24), ZN => n37);
U111 : NAND2_X1 port map( A1 => n37, A2 => n79, ZN => mask00(24));
U63 : NAND2_X1 port map( A1 => n85, A2 => A(1), ZN => n59);
U24 : NAND2_X1 port map( A1 => n96, A2 => n59, ZN => mask16_24_port);
U123 : NAND2_X1 port map( A1 => n41, A2 => n46, ZN => mask00(20));
U150 : NAND2_X1 port map( A1 => n85, A2 => A(5), ZN => n55);
U101 : NAND2_X1 port map( A1 => sel(0), A2 => A(28), ZN => n64);
U50 : NAND2_X1 port map( A1 => n55, A2 => n64, ZN => mask08_20_port);
U117 : NAND2_X1 port map( A1 => n39, A2 => n43, ZN => mask00(22));
U144 : NAND2_X1 port map( A1 => n85, A2 => A(7), ZN => n52);
U94 : NAND2_X1 port map( A1 => sel(0), A2 => A(30), ZN => n62);
U48 : NAND2_X1 port map( A1 => n52, A2 => n62, ZN => mask08_22_port);
U102 : NAND2_X1 port map( A1 => n65, A2 => n76, ZN => mask00(27));
U21 : NAND2_X1 port map( A1 => n56, A2 => n96, ZN => mask16_27_port);
U99 : NAND2_X1 port map( A1 => n64, A2 => n75, ZN => mask00(28));
U20 : NAND2_X1 port map( A1 => n55, A2 => n96, ZN => mask16_28_port);
U58 : NAND2_X1 port map( A1 => n58, A2 => n83, ZN => mask00(9));
U154 : NAND2_X1 port map( A1 => n57, A2 => n81, ZN => mask00(10));
U61 : NAND2_X1 port map( A1 => n59, A2 => n84, ZN => mask00(8));
U96 : NAND2_X1 port map( A1 => n63, A2 => n74, ZN => mask00(29));
U19 : NAND2_X1 port map( A1 => n54, A2 => n96, ZN => mask16_29_port);
U92 : NAND2_X1 port map( A1 => n62, A2 => n73, ZN => mask00(30));
U17 : NAND2_X1 port map( A1 => n52, A2 => n96, ZN => mask16_30_port);
U133 : NAND2_X1 port map( A1 => n49, A2 => n61, ZN => mask00(17));
U54 : NAND2_X1 port map( A1 => n36, A2 => n58, ZN => mask08_17_port);
U139 : NAND2_X1 port map( A1 => n51, A2 => n68, ZN => mask00(15));
U56 : NAND2_X1 port map( A1 => n38, A2 => n60, ZN => mask08_15_port);
U136 : NAND2_X1 port map( A1 => n50, A2 => n67, ZN => mask00(16));
U55 : NAND2_X1 port map( A1 => n37, A2 => n59, ZN => mask08_16_port);
U130 : NAND2_X1 port map( A1 => n48, A2 => n53, ZN => mask00(18));
U53 : NAND2_X1 port map( A1 => n57, A2 => n66, ZN => mask08_18_port);
U148 : NAND2_X1 port map( A1 => n55, A2 => n71, ZN => mask00(12));
U142 : NAND2_X1 port map( A1 => n52, A2 => n69, ZN => mask00(14));
U145 : NAND2_X1 port map( A1 => n54, A2 => n70, ZN => mask00(13));
U151 : NAND2_X1 port map( A1 => n56, A2 => n72, ZN => mask00(11));
U158 : AND2_X1 port map( A1 => sel(0), A2 => A(0), ZN => mask00(0));
U32 : INV_X1 port map( A => n67, ZN => mask16_0_port);
U57 : INV_X1 port map( A => n84, ZN => mask08_0_port);
U95 : AND2_X1 port map( A1 => sel(0), A2 => A(2), ZN => mask00(2));
U18 : INV_X1 port map( A => n53, ZN => mask16_2_port);
U46 : INV_X1 port map( A => n81, ZN => mask08_2_port);
U70 : AND2_X1 port map( A1 => sel(0), A2 => A(4), ZN => mask00(4));
U7 : INV_X1 port map( A => n41, ZN => mask16_4_port);
U36 : INV_X1 port map( A => n71, ZN => mask08_4_port);
U68 : AND2_X1 port map( A1 => sel(0), A2 => A(6), ZN => mask00(6));
U5 : INV_X1 port map( A => n39, ZN => mask16_6_port);
U34 : INV_X1 port map( A => n69, ZN => mask08_6_port);
U69 : AND2_X1 port map( A1 => sel(0), A2 => A(5), ZN => mask00(5));
U6 : INV_X1 port map( A => n40, ZN => mask16_5_port);
U35 : INV_X1 port map( A => n70, ZN => mask08_5_port);
U126 : AND2_X1 port map( A1 => sel(0), A2 => A(1), ZN => mask00(1));
U26 : INV_X1 port map( A => n61, ZN => mask16_1_port);
U51 : INV_X1 port map( A => n83, ZN => mask08_1_port);
U71 : AND2_X1 port map( A1 => sel(0), A2 => A(3), ZN => mask00(3));
U8 : INV_X1 port map( A => n42, ZN => mask16_3_port);
U37 : INV_X1 port map( A => n72, ZN => mask08_3_port);
U90 : INV_X1 port map( A => n82, ZN => mask16_15_port);
U84 : INV_X1 port map( A => n94, ZN => mask00(32));
U80 : INV_X1 port map( A => n92, ZN => mask00(34));
U76 : INV_X1 port map( A => n90, ZN => mask00(36));
U72 : INV_X1 port map( A => n88, ZN => mask00(38));
U78 : INV_X1 port map( A => n91, ZN => mask00(35));
U88 : INV_X1 port map( A => n95, ZN => mask00(31));
U82 : INV_X1 port map( A => n93, ZN => mask00(33));
U74 : INV_X1 port map( A => n89, ZN => mask00(37));
U2 : INV_X1 port map( A => n36, ZN => mask16_9_port);
U31 : INV_X1 port map( A => n66, ZN => mask16_10_port);
U3 : INV_X1 port map( A => n37, ZN => mask16_8_port);
U29 : INV_X1 port map( A => n64, ZN => mask16_12_port);
U27 : INV_X1 port map( A => n62, ZN => mask16_14_port);
U28 : INV_X1 port map( A => n63, ZN => mask16_13_port);
U30 : INV_X1 port map( A => n65, ZN => mask16_11_port);
U4 : INV_X1 port map( A => n68, ZN => mask08_7_port);
U33 : INV_X1 port map( A => n38, ZN => mask16_7_port);
U64 : NAND2_X1 port map( A1 => sel(0), A2 => A(7), ZN => n86);
U65 : NAND2_X1 port map( A1 => n60, A2 => n86, ZN => mask00(7));
U66 : AND2_X2 port map( A1 => sel(1), A2 => mask16_15_port, ZN =>
mask16_18_port);
U86 : INV_X2 port map( A => mask16_18_port, ZN => n96);
U87 : BUF_X1 port map( A => n85, Z => n87);
U157 : NOR2_X2 port map( A1 => sel(0), A2 => sel(1), ZN => n85);
end SYN_behav;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity sum_gen_N32 is
port( A, B : in std_logic_vector (31 downto 0); Cin : in std_logic_vector
(8 downto 0); S : out std_logic_vector (31 downto 0));
end sum_gen_N32;
architecture SYN_STRUCTURAL of sum_gen_N32 is
component carry_sel_gen_N4_1
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_2
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_3
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_4
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_5
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_6
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_7
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component carry_sel_gen_N4_0
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal net539424, net539425, net539426, net539427, net539428, net539429,
net539430, net539431 : std_logic;
begin
csel_N_0 : carry_sel_gen_N4_0 port map( A(3) => A(3), A(2) => A(2), A(1) =>
A(1), A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1)
=> B(1), B(0) => B(0), Ci => Cin(0), S(3) => S(3),
S(2) => S(2), S(1) => S(1), S(0) => S(0), Co =>
net539431);
csel_N_1 : carry_sel_gen_N4_7 port map( A(3) => A(7), A(2) => A(6), A(1) =>
A(5), A(0) => A(4), B(3) => B(7), B(2) => B(6), B(1)
=> B(5), B(0) => B(4), Ci => Cin(1), S(3) => S(7),
S(2) => S(6), S(1) => S(5), S(0) => S(4), Co =>
net539430);
csel_N_2 : carry_sel_gen_N4_6 port map( A(3) => A(11), A(2) => A(10), A(1)
=> A(9), A(0) => A(8), B(3) => B(11), B(2) => B(10),
B(1) => B(9), B(0) => B(8), Ci => Cin(2), S(3) =>
S(11), S(2) => S(10), S(1) => S(9), S(0) => S(8), Co
=> net539429);
csel_N_3 : carry_sel_gen_N4_5 port map( A(3) => A(15), A(2) => A(14), A(1)
=> A(13), A(0) => A(12), B(3) => B(15), B(2) =>
B(14), B(1) => B(13), B(0) => B(12), Ci => Cin(3),
S(3) => S(15), S(2) => S(14), S(1) => S(13), S(0) =>
S(12), Co => net539428);
csel_N_4 : carry_sel_gen_N4_4 port map( A(3) => A(19), A(2) => A(18), A(1)
=> A(17), A(0) => A(16), B(3) => B(19), B(2) =>
B(18), B(1) => B(17), B(0) => B(16), Ci => Cin(4),
S(3) => S(19), S(2) => S(18), S(1) => S(17), S(0) =>
S(16), Co => net539427);
csel_N_5 : carry_sel_gen_N4_3 port map( A(3) => A(23), A(2) => A(22), A(1)
=> A(21), A(0) => A(20), B(3) => B(23), B(2) =>
B(22), B(1) => B(21), B(0) => B(20), Ci => Cin(5),
S(3) => S(23), S(2) => S(22), S(1) => S(21), S(0) =>
S(20), Co => net539426);
csel_N_6 : carry_sel_gen_N4_2 port map( A(3) => A(27), A(2) => A(26), A(1)
=> A(25), A(0) => A(24), B(3) => B(27), B(2) =>
B(26), B(1) => B(25), B(0) => B(24), Ci => Cin(6),
S(3) => S(27), S(2) => S(26), S(1) => S(25), S(0) =>
S(24), Co => net539425);
csel_N_7 : carry_sel_gen_N4_1 port map( A(3) => A(31), A(2) => A(30), A(1)
=> A(29), A(0) => A(28), B(3) => B(31), B(2) =>
B(30), B(1) => B(29), B(0) => B(28), Ci => Cin(7),
S(3) => S(31), S(2) => S(30), S(1) => S(29), S(0) =>
S(28), Co => net539424);
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity carry_tree_N32_logN5 is
port( A, B : in std_logic_vector (31 downto 0); Cin : in std_logic; Cout :
out std_logic_vector (7 downto 0));
end carry_tree_N32_logN5;
architecture SYN_arch of carry_tree_N32_logN5 is
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component pg_1
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_2
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_3
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_4
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end component;
component pg_5
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component g_1
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_2
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_3
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_4
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_5
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_6
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_7
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component pg_6
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_7
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_8
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out
std_logic);
end component;
component pg_9
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end component;
component pg_10
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end component;
component pg_11
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end component;
component pg_12
port( p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic;
g_BAR : in std_logic);
end component;
component g_8
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component pg_13
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_14
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_15
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_16
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_17
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_18
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_19
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out
std_logic);
end component;
component pg_20
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_21
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out
std_logic);
end component;
component pg_22
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_23
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out
std_logic);
end component;
component pg_24
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_25
port( g, p, g_prec, p_prec : in std_logic; p_out, g_out_BAR : out
std_logic);
end component;
component pg_26
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component pg_0
port( g, p, g_prec, p_prec : in std_logic; g_out, p_out : out std_logic
);
end component;
component g_9
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component g_0
port( g, p, g_prec : in std_logic; g_out : out std_logic);
end component;
component pg_net_1
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_2
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_3
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_4
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_5
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_6
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_7
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_8
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_9
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_10
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_11
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_12
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_13
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_14
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_15
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_16
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_17
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_18
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_19
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_20
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_21
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_22
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_23
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_24
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_25
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_26
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_27
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_28
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_29
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_30
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_31
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
component pg_net_0
port( a, b : in std_logic; g_out, p_out : out std_logic);
end component;
signal Cout_7_port, Cout_6_port, Cout_5_port, Cout_4_port, n9, Cout_2_port,
n10, n11, p_net_31_port, p_net_30_port, p_net_29_port, p_net_28_port,
p_net_27_port, p_net_26_port, p_net_25_port, p_net_24_port, p_net_23_port
, p_net_22_port, p_net_21_port, p_net_20_port, p_net_19_port,
p_net_18_port, p_net_17_port, p_net_16_port, p_net_15_port, p_net_14_port
, p_net_13_port, p_net_12_port, p_net_11_port, p_net_10_port,
p_net_9_port, p_net_8_port, p_net_7_port, p_net_6_port, p_net_5_port,
p_net_4_port, p_net_3_port, p_net_2_port, p_net_1_port, g_net_31_port,
g_net_30_port, g_net_29_port, g_net_28_port, g_net_27_port, g_net_26_port
, g_net_25_port, g_net_24_port, g_net_23_port, g_net_22_port,
g_net_21_port, g_net_20_port, g_net_19_port, g_net_18_port, g_net_17_port
, g_net_16_port, g_net_15_port, g_net_14_port, g_net_13_port,
g_net_12_port, g_net_11_port, g_net_10_port, g_net_9_port, g_net_8_port,
g_net_7_port, g_net_6_port, g_net_5_port, g_net_4_port, g_net_3_port,
g_net_2_port, g_net_1_port, g_net_0_port, magic_pro_1_port,
magic_pro_0_port, pg_1_15_1_port, pg_1_15_0_port, pg_1_14_1_port,
pg_1_14_0_port, pg_1_13_1_port, pg_1_13_0_port, pg_1_12_1_port,
pg_1_12_0_port, pg_1_11_1_port, pg_1_11_0_port, pg_1_10_1_port,
pg_1_10_0_port, pg_1_9_1_port, pg_1_9_0_port, pg_1_8_1_port,
pg_1_8_0_port, pg_1_7_1_port, pg_1_7_0_port, pg_1_6_1_port, pg_1_6_0_port
, pg_1_5_1_port, pg_1_5_0_port, pg_1_4_1_port, pg_1_4_0_port,
pg_1_3_1_port, pg_1_3_0_port, pg_1_2_1_port, pg_1_2_0_port, pg_1_1_1_port
, pg_1_1_0_port, pg_1_0_0_port, pg_n_4_7_1_port, pg_n_4_7_0_port,
pg_n_4_6_1_port, pg_n_4_6_0_port, pg_n_3_7_1_port, pg_n_3_7_0_port,
pg_n_3_5_1_port, pg_n_3_5_0_port, pg_n_3_3_1_port, pg_n_3_3_0_port,
pg_n_2_7_1_port, pg_n_2_7_0_port, pg_n_2_6_1_port, pg_n_2_6_0_port,
pg_n_2_5_1_port, pg_n_2_5_0_port, pg_n_2_4_1_port, pg_n_2_4_0_port,
pg_n_2_3_1_port, pg_n_2_3_0_port, pg_n_2_2_1_port, pg_n_2_2_0_port,
pg_n_2_1_1_port, pg_n_2_1_0_port, n1, Cout_3_port, Cout_1_port, n5,
Cout_0_port, n7, n8 : std_logic;
begin
Cout <= ( Cout_7_port, Cout_6_port, Cout_5_port, Cout_4_port, Cout_3_port,
Cout_2_port, Cout_1_port, Cout_0_port );
pg_net_x_1 : pg_net_0 port map( a => A(1), b => B(1), g_out => g_net_1_port,
p_out => p_net_1_port);
pg_net_x_2 : pg_net_31 port map( a => A(2), b => B(2), g_out => g_net_2_port
, p_out => p_net_2_port);
pg_net_x_3 : pg_net_30 port map( a => A(3), b => B(3), g_out => g_net_3_port
, p_out => p_net_3_port);
pg_net_x_4 : pg_net_29 port map( a => A(4), b => B(4), g_out => g_net_4_port
, p_out => p_net_4_port);
pg_net_x_5 : pg_net_28 port map( a => A(5), b => B(5), g_out => g_net_5_port
, p_out => p_net_5_port);
pg_net_x_6 : pg_net_27 port map( a => A(6), b => B(6), g_out => g_net_6_port
, p_out => p_net_6_port);
pg_net_x_7 : pg_net_26 port map( a => A(7), b => B(7), g_out => g_net_7_port
, p_out => p_net_7_port);
pg_net_x_8 : pg_net_25 port map( a => A(8), b => B(8), g_out => g_net_8_port
, p_out => p_net_8_port);
pg_net_x_9 : pg_net_24 port map( a => A(9), b => B(9), g_out => g_net_9_port
, p_out => p_net_9_port);
pg_net_x_10 : pg_net_23 port map( a => A(10), b => B(10), g_out =>
g_net_10_port, p_out => p_net_10_port);
pg_net_x_11 : pg_net_22 port map( a => A(11), b => B(11), g_out =>
g_net_11_port, p_out => p_net_11_port);
pg_net_x_12 : pg_net_21 port map( a => A(12), b => B(12), g_out =>
g_net_12_port, p_out => p_net_12_port);
pg_net_x_13 : pg_net_20 port map( a => A(13), b => B(13), g_out =>
g_net_13_port, p_out => p_net_13_port);
pg_net_x_14 : pg_net_19 port map( a => A(14), b => B(14), g_out =>
g_net_14_port, p_out => p_net_14_port);
pg_net_x_15 : pg_net_18 port map( a => A(15), b => B(15), g_out =>
g_net_15_port, p_out => p_net_15_port);
pg_net_x_16 : pg_net_17 port map( a => A(16), b => B(16), g_out =>
g_net_16_port, p_out => p_net_16_port);
pg_net_x_17 : pg_net_16 port map( a => A(17), b => B(17), g_out =>
g_net_17_port, p_out => p_net_17_port);
pg_net_x_18 : pg_net_15 port map( a => A(18), b => B(18), g_out =>
g_net_18_port, p_out => p_net_18_port);
pg_net_x_19 : pg_net_14 port map( a => A(19), b => B(19), g_out =>
g_net_19_port, p_out => p_net_19_port);
pg_net_x_20 : pg_net_13 port map( a => A(20), b => B(20), g_out =>
g_net_20_port, p_out => p_net_20_port);
pg_net_x_21 : pg_net_12 port map( a => A(21), b => B(21), g_out =>
g_net_21_port, p_out => p_net_21_port);
pg_net_x_22 : pg_net_11 port map( a => A(22), b => B(22), g_out =>
g_net_22_port, p_out => p_net_22_port);
pg_net_x_23 : pg_net_10 port map( a => A(23), b => B(23), g_out =>
g_net_23_port, p_out => p_net_23_port);
pg_net_x_24 : pg_net_9 port map( a => A(24), b => B(24), g_out =>
g_net_24_port, p_out => p_net_24_port);
pg_net_x_25 : pg_net_8 port map( a => A(25), b => B(25), g_out =>
g_net_25_port, p_out => p_net_25_port);
pg_net_x_26 : pg_net_7 port map( a => A(26), b => B(26), g_out =>
g_net_26_port, p_out => p_net_26_port);
pg_net_x_27 : pg_net_6 port map( a => A(27), b => B(27), g_out =>
g_net_27_port, p_out => p_net_27_port);
pg_net_x_28 : pg_net_5 port map( a => A(28), b => B(28), g_out =>
g_net_28_port, p_out => p_net_28_port);
pg_net_x_29 : pg_net_4 port map( a => A(29), b => B(29), g_out =>
g_net_29_port, p_out => p_net_29_port);
pg_net_x_30 : pg_net_3 port map( a => A(30), b => B(30), g_out =>
g_net_30_port, p_out => p_net_30_port);
pg_net_x_31 : pg_net_2 port map( a => A(31), b => B(31), g_out =>
g_net_31_port, p_out => p_net_31_port);
pg_net_0_MAGIC : pg_net_1 port map( a => A(0), b => B(0), g_out =>
magic_pro_0_port, p_out => magic_pro_1_port);
xG_0_0_MAGIC : g_0 port map( g => magic_pro_0_port, p => magic_pro_1_port,
g_prec => Cin, g_out => g_net_0_port);
xG_1_0 : g_9 port map( g => g_net_1_port, p => p_net_1_port, g_prec =>
g_net_0_port, g_out => pg_1_0_0_port);
xPG_1_1 : pg_0 port map( g => g_net_3_port, p => p_net_3_port, g_prec =>
g_net_2_port, p_prec => p_net_2_port, g_out =>
pg_1_1_0_port, p_out => pg_1_1_1_port);
xPG_1_2 : pg_26 port map( g => g_net_5_port, p => p_net_5_port, g_prec =>
g_net_4_port, p_prec => p_net_4_port, g_out =>
pg_1_2_0_port, p_out => pg_1_2_1_port);
xPG_1_3 : pg_25 port map( g => g_net_7_port, p => p_net_7_port, g_prec =>
g_net_6_port, p_prec => p_net_6_port, p_out =>
pg_1_3_1_port, g_out_BAR => pg_1_3_0_port);
xPG_1_4 : pg_24 port map( g => g_net_9_port, p => p_net_9_port, g_prec =>
g_net_8_port, p_prec => p_net_8_port, g_out =>
pg_1_4_0_port, p_out => pg_1_4_1_port);
xPG_1_5 : pg_23 port map( g => g_net_11_port, p => p_net_11_port, g_prec =>
g_net_10_port, p_prec => p_net_10_port, p_out =>
pg_1_5_1_port, g_out_BAR => pg_1_5_0_port);
xPG_1_6 : pg_22 port map( g => g_net_13_port, p => p_net_13_port, g_prec =>
g_net_12_port, p_prec => p_net_12_port, g_out =>
pg_1_6_0_port, p_out => pg_1_6_1_port);
xPG_1_7 : pg_21 port map( g => g_net_15_port, p => p_net_15_port, g_prec =>
g_net_14_port, p_prec => p_net_14_port, p_out =>
pg_1_7_1_port, g_out_BAR => pg_1_7_0_port);
xPG_1_8 : pg_20 port map( g => g_net_17_port, p => p_net_17_port, g_prec =>
g_net_16_port, p_prec => p_net_16_port, g_out =>
pg_1_8_0_port, p_out => pg_1_8_1_port);
xPG_1_9 : pg_19 port map( g => g_net_19_port, p => p_net_19_port, g_prec =>
g_net_18_port, p_prec => p_net_18_port, p_out =>
pg_1_9_1_port, g_out_BAR => pg_1_9_0_port);
xPG_1_10 : pg_18 port map( g => g_net_21_port, p => p_net_21_port, g_prec =>
g_net_20_port, p_prec => p_net_20_port, g_out =>
pg_1_10_0_port, p_out => pg_1_10_1_port);
xPG_1_11 : pg_17 port map( g => g_net_23_port, p => p_net_23_port, g_prec =>
g_net_22_port, p_prec => p_net_22_port, g_out =>
pg_1_11_0_port, p_out => pg_1_11_1_port);
xPG_1_12 : pg_16 port map( g => g_net_25_port, p => p_net_25_port, g_prec =>
g_net_24_port, p_prec => p_net_24_port, g_out =>
pg_1_12_0_port, p_out => pg_1_12_1_port);
xPG_1_13 : pg_15 port map( g => g_net_27_port, p => p_net_27_port, g_prec =>
g_net_26_port, p_prec => p_net_26_port, g_out =>
pg_1_13_0_port, p_out => pg_1_13_1_port);
xPG_1_14 : pg_14 port map( g => g_net_29_port, p => p_net_29_port, g_prec =>
g_net_28_port, p_prec => p_net_28_port, g_out =>
pg_1_14_0_port, p_out => pg_1_14_1_port);
xPG_1_15 : pg_13 port map( g => g_net_31_port, p => p_net_31_port, g_prec =>
g_net_30_port, p_prec => p_net_30_port, g_out =>
pg_1_15_0_port, p_out => pg_1_15_1_port);
xG_2_0 : g_8 port map( g => pg_1_1_0_port, p => pg_1_1_1_port, g_prec =>
pg_1_0_0_port, g_out => n11);
xPG_2_1 : pg_12 port map( p => pg_1_3_1_port, g_prec => pg_1_2_0_port,
p_prec => pg_1_2_1_port, g_out => pg_n_2_1_0_port,
p_out => pg_n_2_1_1_port, g_BAR => pg_1_3_0_port);
xPG_2_2 : pg_11 port map( p => pg_1_5_1_port, g_prec => pg_1_4_0_port,
p_prec => pg_1_4_1_port, g_out => pg_n_2_2_0_port,
p_out => pg_n_2_2_1_port, g_BAR => pg_1_5_0_port);
xPG_2_3 : pg_10 port map( p => pg_1_7_1_port, g_prec => pg_1_6_0_port,
p_prec => pg_1_6_1_port, g_out => pg_n_2_3_0_port,
p_out => pg_n_2_3_1_port, g_BAR => pg_1_7_0_port);
xPG_2_4 : pg_9 port map( p => pg_1_9_1_port, g_prec => pg_1_8_0_port, p_prec
=> pg_1_8_1_port, g_out => pg_n_2_4_0_port, p_out =>
pg_n_2_4_1_port, g_BAR => pg_1_9_0_port);
xPG_2_5 : pg_8 port map( g => pg_1_11_0_port, p => pg_1_11_1_port, g_prec =>
pg_1_10_0_port, p_prec => pg_1_10_1_port, p_out =>
pg_n_2_5_1_port, g_out_BAR => pg_n_2_5_0_port);
xPG_2_6 : pg_7 port map( g => pg_1_13_0_port, p => pg_1_13_1_port, g_prec =>
pg_1_12_0_port, p_prec => pg_1_12_1_port, g_out =>
pg_n_2_6_0_port, p_out => pg_n_2_6_1_port);
xPG_2_7 : pg_6 port map( g => pg_1_15_0_port, p => pg_1_15_1_port, g_prec =>
pg_1_14_0_port, p_prec => pg_1_14_1_port, g_out =>
pg_n_2_7_0_port, p_out => pg_n_2_7_1_port);
xG_3_1 : g_7 port map( g => pg_n_2_1_0_port, p => pg_n_2_1_1_port, g_prec =>
n11, g_out => n10);
xG_4_2 : g_6 port map( g => pg_n_2_2_0_port, p => pg_n_2_2_1_port, g_prec =>
n8, g_out => Cout_2_port);
xG_4_3 : g_5 port map( g => pg_n_3_3_0_port, p => pg_n_3_3_1_port, g_prec =>
n10, g_out => n9);
xG_5_4 : g_4 port map( g => n5, p => pg_n_2_4_1_port, g_prec => n9, g_out =>
Cout_4_port);
xG_5_5 : g_3 port map( g => n7, p => pg_n_3_5_1_port, g_prec => n9, g_out =>
Cout_5_port);
xG_5_6 : g_2 port map( g => pg_n_4_6_0_port, p => pg_n_4_6_1_port, g_prec =>
n9, g_out => Cout_6_port);
xG_5_7 : g_1 port map( g => pg_n_4_7_0_port, p => pg_n_4_7_1_port, g_prec =>
n1, g_out => Cout_7_port);
xPG_3_3 : pg_5 port map( g => pg_n_2_3_0_port, p => pg_n_2_3_1_port, g_prec
=> pg_n_2_2_0_port, p_prec => pg_n_2_2_1_port, g_out
=> pg_n_3_3_0_port, p_out => pg_n_3_3_1_port);
xPG_3_5 : pg_4 port map( p => pg_n_2_5_1_port, g_prec => pg_n_2_4_0_port,
p_prec => pg_n_2_4_1_port, g_out => pg_n_3_5_0_port,
p_out => pg_n_3_5_1_port, g_BAR => pg_n_2_5_0_port);
xPG_3_7 : pg_3 port map( g => pg_n_2_7_0_port, p => pg_n_2_7_1_port, g_prec
=> pg_n_2_6_0_port, p_prec => pg_n_2_6_1_port, g_out
=> pg_n_3_7_0_port, p_out => pg_n_3_7_1_port);
xPG_4_6 : pg_2 port map( g => pg_n_2_6_0_port, p => pg_n_2_6_1_port, g_prec
=> pg_n_3_5_0_port, p_prec => pg_n_3_5_1_port, g_out
=> pg_n_4_6_0_port, p_out => pg_n_4_6_1_port);
xPG_4_7 : pg_1 port map( g => pg_n_3_7_0_port, p => pg_n_3_7_1_port, g_prec
=> n7, p_prec => pg_n_3_5_1_port, g_out =>
pg_n_4_7_0_port, p_out => pg_n_4_7_1_port);
U1 : CLKBUF_X1 port map( A => Cout_3_port, Z => n1);
U2 : BUF_X1 port map( A => n9, Z => Cout_3_port);
U3 : CLKBUF_X1 port map( A => pg_n_3_5_0_port, Z => n7);
U4 : CLKBUF_X1 port map( A => n11, Z => Cout_0_port);
U5 : CLKBUF_X1 port map( A => pg_n_2_4_0_port, Z => n5);
U6 : CLKBUF_X1 port map( A => n8, Z => Cout_1_port);
U7 : CLKBUF_X1 port map( A => n10, Z => n8);
end SYN_arch;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity xor_gen_N32 is
port( A : in std_logic_vector (31 downto 0); B : in std_logic; S : out
std_logic_vector (31 downto 0));
end xor_gen_N32;
architecture SYN_bhe of xor_gen_N32 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component BUF_X2
port( A : in std_logic; Z : out std_logic);
end component;
component XNOR2_X2
port( A, B : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component INV_X2
port( A : in std_logic; ZN : out std_logic);
end component;
component XOR2_X2
port( A, B : in std_logic; Z : out std_logic);
end component;
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
signal n13, n1, n2, n3, n4, n6, n7, n8, n9, n10, n11 : std_logic;
begin
U8 : XOR2_X1 port map( A => B, B => A(31), Z => S(31));
U9 : XOR2_X1 port map( A => B, B => A(30), Z => S(30));
U12 : XOR2_X1 port map( A => B, B => A(28), Z => S(28));
U15 : XOR2_X1 port map( A => B, B => A(25), Z => S(25));
U17 : XOR2_X1 port map( A => B, B => A(23), Z => S(23));
U26 : XOR2_X1 port map( A => A(15), B => B, Z => S(15));
U30 : XOR2_X1 port map( A => B, B => A(11), Z => S(11));
U16 : XOR2_X1 port map( A => B, B => A(24), Z => S(24));
U1 : XOR2_X1 port map( A => A(20), B => B, Z => S(20));
U2 : XNOR2_X1 port map( A => n2, B => A(3), ZN => S(3));
U3 : MUX2_X1 port map( A => B, B => n2, S => A(7), Z => S(7));
U4 : XNOR2_X1 port map( A => A(8), B => n2, ZN => S(8));
U5 : XOR2_X1 port map( A => B, B => A(29), Z => S(29));
U6 : XOR2_X1 port map( A => B, B => A(26), Z => S(26));
U7 : XNOR2_X1 port map( A => A(27), B => n2, ZN => S(27));
U10 : XOR2_X2 port map( A => B, B => A(22), Z => S(22));
U11 : OAI21_X1 port map( B1 => A(13), B2 => n2, A => n4, ZN => S(13));
U13 : OAI21_X1 port map( B1 => n2, B2 => A(0), A => n1, ZN => S(0));
U14 : NAND2_X1 port map( A1 => A(0), A2 => n2, ZN => n1);
U18 : XNOR2_X2 port map( A => A(19), B => n2, ZN => S(19));
U19 : INV_X2 port map( A => B, ZN => n2);
U20 : XNOR2_X2 port map( A => A(12), B => n2, ZN => S(12));
U21 : XNOR2_X2 port map( A => A(21), B => n2, ZN => S(21));
U22 : XNOR2_X1 port map( A => A(17), B => n2, ZN => S(17));
U23 : XNOR2_X2 port map( A => A(16), B => n2, ZN => S(16));
U24 : XOR2_X1 port map( A => B, B => A(18), Z => S(18));
U25 : XOR2_X1 port map( A => A(2), B => B, Z => S(2));
U27 : BUF_X2 port map( A => n13, Z => S(6));
U28 : INV_X1 port map( A => A(9), ZN => n9);
U29 : INV_X1 port map( A => A(14), ZN => n6);
U31 : NAND2_X1 port map( A1 => A(1), A2 => n2, ZN => n3);
U32 : OAI21_X1 port map( B1 => A(1), B2 => n2, A => n3, ZN => S(1));
U33 : NAND2_X1 port map( A1 => A(13), A2 => n2, ZN => n4);
U34 : NAND2_X1 port map( A1 => n10, A2 => n11, ZN => S(9));
U35 : NAND2_X1 port map( A1 => n7, A2 => n8, ZN => S(14));
U36 : XOR2_X1 port map( A => B, B => A(10), Z => S(10));
U37 : XOR2_X1 port map( A => B, B => A(5), Z => S(5));
U38 : XOR2_X1 port map( A => B, B => A(6), Z => n13);
U39 : XOR2_X1 port map( A => A(4), B => B, Z => S(4));
U40 : NAND2_X1 port map( A1 => B, A2 => n6, ZN => n7);
U41 : NAND2_X1 port map( A1 => A(14), A2 => n2, ZN => n8);
U42 : NAND2_X1 port map( A1 => B, A2 => n9, ZN => n10);
U43 : NAND2_X1 port map( A1 => n2, A2 => A(9), ZN => n11);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity ff32_en_SIZE32 is
port( D : in std_logic_vector (31 downto 0); en, clk, rst : in std_logic;
Q : out std_logic_vector (31 downto 0));
end ff32_en_SIZE32;
architecture SYN_behavioral of ff32_en_SIZE32 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X2
port( A : in std_logic; ZN : out std_logic);
end component;
component DFFR_X1
port( D, CK, RN : in std_logic; Q, QN : out std_logic);
end component;
signal n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78,
n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93
, n94, n95, n97, net549739, net549740, net549741, net549742, net549743,
net549744, net549745, net549746, net549747, net549748, net549749,
net549750, net549751, net549752, net549753, net549754, net549755,
net549756, net549757, net549758, net549759, net549760, net549761,
net549762, net549763, net549764, net549765, net549766, net549767,
net549768, net549769, net549770, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11
, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26,
n27, n28, n29, n30, n31, n32, n33, n1, n34 : std_logic;
begin
Q_reg_31_inst : DFFR_X1 port map( D => n97, CK => clk, RN => n34, Q => Q(31)
, QN => net549770);
Q_reg_30_inst : DFFR_X1 port map( D => n95, CK => clk, RN => n34, Q => Q(30)
, QN => net549769);
Q_reg_29_inst : DFFR_X1 port map( D => n94, CK => clk, RN => n34, Q => Q(29)
, QN => net549768);
Q_reg_28_inst : DFFR_X1 port map( D => n93, CK => clk, RN => n34, Q => Q(28)
, QN => net549767);
Q_reg_27_inst : DFFR_X1 port map( D => n92, CK => clk, RN => n34, Q => Q(27)
, QN => net549766);
Q_reg_26_inst : DFFR_X1 port map( D => n91, CK => clk, RN => n34, Q => Q(26)
, QN => net549765);
Q_reg_25_inst : DFFR_X1 port map( D => n90, CK => clk, RN => n34, Q => Q(25)
, QN => net549764);
Q_reg_24_inst : DFFR_X1 port map( D => n89, CK => clk, RN => n34, Q => Q(24)
, QN => net549763);
Q_reg_23_inst : DFFR_X1 port map( D => n88, CK => clk, RN => n34, Q => Q(23)
, QN => net549762);
Q_reg_22_inst : DFFR_X1 port map( D => n87, CK => clk, RN => n34, Q => Q(22)
, QN => net549761);
Q_reg_21_inst : DFFR_X1 port map( D => n86, CK => clk, RN => n34, Q => Q(21)
, QN => net549760);
Q_reg_19_inst : DFFR_X1 port map( D => n84, CK => clk, RN => n34, Q => Q(19)
, QN => net549758);
Q_reg_18_inst : DFFR_X1 port map( D => n83, CK => clk, RN => n34, Q => Q(18)
, QN => net549757);
Q_reg_17_inst : DFFR_X1 port map( D => n82, CK => clk, RN => n34, Q => Q(17)
, QN => net549756);
Q_reg_16_inst : DFFR_X1 port map( D => n81, CK => clk, RN => n34, Q => Q(16)
, QN => net549755);
Q_reg_15_inst : DFFR_X1 port map( D => n80, CK => clk, RN => n34, Q => Q(15)
, QN => net549754);
Q_reg_14_inst : DFFR_X1 port map( D => n79, CK => clk, RN => n34, Q => Q(14)
, QN => net549753);
Q_reg_13_inst : DFFR_X1 port map( D => n78, CK => clk, RN => n34, Q => Q(13)
, QN => net549752);
Q_reg_12_inst : DFFR_X1 port map( D => n77, CK => clk, RN => n34, Q => Q(12)
, QN => net549751);
Q_reg_11_inst : DFFR_X1 port map( D => n76, CK => clk, RN => n34, Q => Q(11)
, QN => net549750);
Q_reg_10_inst : DFFR_X1 port map( D => n75, CK => clk, RN => n34, Q => Q(10)
, QN => net549749);
Q_reg_9_inst : DFFR_X1 port map( D => n74, CK => clk, RN => n34, Q => Q(9),
QN => net549748);
Q_reg_8_inst : DFFR_X1 port map( D => n73, CK => clk, RN => n34, Q => Q(8),
QN => net549747);
Q_reg_7_inst : DFFR_X1 port map( D => n72, CK => clk, RN => n34, Q => Q(7),
QN => net549746);
Q_reg_6_inst : DFFR_X1 port map( D => n71, CK => clk, RN => n34, Q => Q(6),
QN => net549745);
Q_reg_5_inst : DFFR_X1 port map( D => n70, CK => clk, RN => n34, Q => Q(5),
QN => net549744);
Q_reg_4_inst : DFFR_X1 port map( D => n69, CK => clk, RN => n34, Q => Q(4),
QN => net549743);
Q_reg_3_inst : DFFR_X1 port map( D => n68, CK => clk, RN => n34, Q => Q(3),
QN => net549742);
Q_reg_2_inst : DFFR_X1 port map( D => n67, CK => clk, RN => n34, Q => Q(2),
QN => net549741);
Q_reg_1_inst : DFFR_X1 port map( D => n66, CK => clk, RN => n34, Q => Q(1),
QN => net549740);
Q_reg_0_inst : DFFR_X1 port map( D => n65, CK => clk, RN => n34, Q => Q(0),
QN => net549739);
U9 : OAI21_X1 port map( B1 => en, B2 => net549767, A => n5, ZN => n93);
U21 : OAI21_X1 port map( B1 => en, B2 => net549761, A => n11, ZN => n87);
U7 : OAI21_X1 port map( B1 => en, B2 => net549768, A => n4, ZN => n94);
U2 : OAI21_X1 port map( B1 => en, B2 => net549770, A => n2, ZN => n97);
U17 : OAI21_X1 port map( B1 => en, B2 => net549763, A => n9, ZN => n89);
U11 : OAI21_X1 port map( B1 => en, B2 => net549766, A => n6, ZN => n92);
U19 : OAI21_X1 port map( B1 => en, B2 => net549762, A => n10, ZN => n88);
U13 : OAI21_X1 port map( B1 => en, B2 => net549765, A => n7, ZN => n91);
U40 : NAND2_X1 port map( A1 => en, A2 => D(13), ZN => n20);
U39 : OAI21_X1 port map( B1 => en, B2 => net549752, A => n20, ZN => n78);
U36 : NAND2_X1 port map( A1 => en, A2 => D(15), ZN => n18);
U35 : OAI21_X1 port map( B1 => en, B2 => net549754, A => n18, ZN => n80);
U32 : NAND2_X1 port map( A1 => en, A2 => D(17), ZN => n16);
U31 : OAI21_X1 port map( B1 => en, B2 => net549756, A => n16, ZN => n82);
U30 : NAND2_X1 port map( A1 => en, A2 => D(18), ZN => n15);
U29 : OAI21_X1 port map( B1 => en, B2 => net549757, A => n15, ZN => n83);
U34 : NAND2_X1 port map( A1 => en, A2 => D(16), ZN => n17);
U33 : OAI21_X1 port map( B1 => en, B2 => net549755, A => n17, ZN => n81);
U27 : OAI21_X1 port map( B1 => en, B2 => net549758, A => n14, ZN => n84);
U38 : NAND2_X1 port map( A1 => en, A2 => D(14), ZN => n19);
U37 : OAI21_X1 port map( B1 => en, B2 => net549753, A => n19, ZN => n79);
U42 : NAND2_X1 port map( A1 => en, A2 => D(12), ZN => n21);
U41 : OAI21_X1 port map( B1 => en, B2 => net549751, A => n21, ZN => n77);
U44 : NAND2_X1 port map( A1 => en, A2 => D(11), ZN => n22);
U43 : OAI21_X1 port map( B1 => en, B2 => net549750, A => n22, ZN => n76);
U50 : NAND2_X1 port map( A1 => en, A2 => D(8), ZN => n25);
U49 : OAI21_X1 port map( B1 => en, B2 => net549747, A => n25, ZN => n73);
U48 : NAND2_X1 port map( A1 => en, A2 => D(9), ZN => n24);
U47 : OAI21_X1 port map( B1 => en, B2 => net549748, A => n24, ZN => n74);
U46 : NAND2_X1 port map( A1 => en, A2 => D(10), ZN => n23);
U45 : OAI21_X1 port map( B1 => en, B2 => net549749, A => n23, ZN => n75);
U52 : NAND2_X1 port map( A1 => en, A2 => D(7), ZN => n26);
U51 : OAI21_X1 port map( B1 => en, B2 => net549746, A => n26, ZN => n72);
U54 : NAND2_X1 port map( A1 => en, A2 => D(6), ZN => n27);
U53 : OAI21_X1 port map( B1 => en, B2 => net549745, A => n27, ZN => n71);
U60 : NAND2_X1 port map( A1 => en, A2 => D(3), ZN => n30);
U59 : OAI21_X1 port map( B1 => en, B2 => net549742, A => n30, ZN => n68);
U56 : NAND2_X1 port map( A1 => en, A2 => D(5), ZN => n28);
U55 : OAI21_X1 port map( B1 => en, B2 => net549744, A => n28, ZN => n70);
U58 : NAND2_X1 port map( A1 => en, A2 => D(4), ZN => n29);
U57 : OAI21_X1 port map( B1 => en, B2 => net549743, A => n29, ZN => n69);
U62 : NAND2_X1 port map( A1 => en, A2 => D(2), ZN => n31);
U61 : OAI21_X1 port map( B1 => en, B2 => net549741, A => n31, ZN => n67);
U64 : NAND2_X1 port map( A1 => en, A2 => D(1), ZN => n32);
U63 : OAI21_X1 port map( B1 => en, B2 => net549740, A => n32, ZN => n66);
U66 : NAND2_X1 port map( A1 => en, A2 => D(0), ZN => n33);
U65 : OAI21_X1 port map( B1 => en, B2 => net549739, A => n33, ZN => n65);
Q_reg_20_inst : DFFR_X1 port map( D => n85, CK => clk, RN => n34, Q => Q(20)
, QN => net549759);
U3 : NAND2_X1 port map( A1 => en, A2 => D(21), ZN => n1);
U4 : OAI21_X1 port map( B1 => en, B2 => net549760, A => n1, ZN => n86);
U5 : INV_X2 port map( A => rst, ZN => n34);
U6 : OAI21_X1 port map( B1 => en, B2 => net549769, A => n3, ZN => n95);
U8 : NAND2_X1 port map( A1 => en, A2 => D(30), ZN => n3);
U10 : OAI21_X1 port map( B1 => en, B2 => net549764, A => n8, ZN => n90);
U12 : NAND2_X1 port map( A1 => en, A2 => D(25), ZN => n8);
U14 : NAND2_X1 port map( A1 => en, A2 => D(24), ZN => n9);
U15 : NAND2_X1 port map( A1 => en, A2 => D(26), ZN => n7);
U16 : OAI21_X1 port map( B1 => en, B2 => net549759, A => n13, ZN => n85);
U18 : NAND2_X1 port map( A1 => en, A2 => D(20), ZN => n13);
U20 : NAND2_X1 port map( A1 => en, A2 => D(27), ZN => n6);
U22 : NAND2_X1 port map( A1 => en, A2 => D(23), ZN => n10);
U23 : NAND2_X1 port map( A1 => en, A2 => D(19), ZN => n14);
U24 : NAND2_X1 port map( A1 => en, A2 => D(22), ZN => n11);
U25 : NAND2_X1 port map( A1 => en, A2 => D(28), ZN => n5);
U26 : NAND2_X1 port map( A1 => en, A2 => D(29), ZN => n4);
U28 : NAND2_X1 port map( A1 => en, A2 => D(31), ZN => n2);
end SYN_behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity piso_r_2_N32 is
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (31 downto 0);
SO : out std_logic_vector (31 downto 0));
end piso_r_2_N32;
architecture SYN_archi of piso_r_2_N32 is
component SDFF_X1
port( D, SI, SE, CK : in std_logic; Q, QN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
signal SO_31_port, SO_30_port, SO_29_port, SO_28_port, SO_27_port,
SO_26_port, SO_25_port, SO_24_port, SO_23_port, SO_22_port, SO_21_port,
SO_20_port, SO_19_port, SO_18_port, SO_17_port, SO_16_port, SO_15_port,
SO_14_port, SO_13_port, SO_12_port, SO_11_port, SO_10_port, SO_9_port,
SO_8_port, SO_7_port, SO_6_port, SO_5_port, SO_4_port, SO_3_port,
SO_2_port, SO_1_port, SO_0_port, N3, N4, N5, N6, N7, N8, N9, N10, N11,
N12, N13, N14, N15, N16, N17, N18, N19, N20, N21, N22, N23, N24, N25, N26
, N27, N28, N29, N30, N31, N32, net549709, net549710, net549711,
net549712, net549713, net549714, net549715, net549716, net549717,
net549718, net549719, net549720, net549721, net549722, net549723,
net549724, net549725, net549726, net549727, net549728, net549729,
net549730, net549731, net549732, net549733, net549734, net549735,
net549736, net549737, net549738, n1, n3_port, n4_port, n5_port, n6_port,
n9_port, n10_port, n11_port, n12_port, n13_port, n14_port, n15_port,
n16_port, n17_port, n19_port, n20_port, n21_port, n22_port, n23_port,
n24_port, n25_port, n26_port, n27_port, n28_port, n29_port, n30_port,
n31_port, n32_port, n2, n7_port : std_logic;
begin
SO <= ( SO_31_port, SO_30_port, SO_29_port, SO_28_port, SO_27_port,
SO_26_port, SO_25_port, SO_24_port, SO_23_port, SO_22_port, SO_21_port,
SO_20_port, SO_19_port, SO_18_port, SO_17_port, SO_16_port, SO_15_port,
SO_14_port, SO_13_port, SO_12_port, SO_11_port, SO_10_port, SO_9_port,
SO_8_port, SO_7_port, SO_6_port, SO_5_port, SO_4_port, SO_3_port,
SO_2_port, SO_1_port, SO_0_port );
tmp_reg_1_inst : DFF_X1 port map( D => N4, CK => Clock, Q => SO_1_port, QN
=> net549738);
tmp_reg_3_inst : DFF_X1 port map( D => N6, CK => Clock, Q => SO_3_port, QN
=> net549737);
tmp_reg_5_inst : DFF_X1 port map( D => N8, CK => Clock, Q => SO_5_port, QN
=> net549736);
tmp_reg_7_inst : DFF_X1 port map( D => N10, CK => Clock, Q => SO_7_port, QN
=> net549735);
tmp_reg_9_inst : DFF_X1 port map( D => N12, CK => Clock, Q => SO_9_port, QN
=> net549734);
tmp_reg_11_inst : DFF_X1 port map( D => N14, CK => Clock, Q => SO_11_port,
QN => net549733);
tmp_reg_13_inst : DFF_X1 port map( D => N16, CK => Clock, Q => SO_13_port,
QN => net549732);
tmp_reg_15_inst : DFF_X1 port map( D => N18, CK => Clock, Q => SO_15_port,
QN => net549731);
tmp_reg_17_inst : DFF_X1 port map( D => N20, CK => Clock, Q => SO_17_port,
QN => net549730);
tmp_reg_19_inst : DFF_X1 port map( D => N22, CK => Clock, Q => SO_19_port,
QN => net549729);
tmp_reg_21_inst : DFF_X1 port map( D => N24, CK => Clock, Q => SO_21_port,
QN => net549728);
tmp_reg_23_inst : DFF_X1 port map( D => N26, CK => Clock, Q => SO_23_port,
QN => net549727);
tmp_reg_25_inst : DFF_X1 port map( D => N28, CK => Clock, Q => SO_25_port,
QN => net549726);
tmp_reg_27_inst : DFF_X1 port map( D => N30, CK => Clock, Q => SO_27_port,
QN => net549725);
tmp_reg_29_inst : DFF_X1 port map( D => N32, CK => Clock, Q => SO_29_port,
QN => net549724);
tmp_reg_0_inst : DFF_X1 port map( D => N3, CK => Clock, Q => SO_0_port, QN
=> net549723);
tmp_reg_2_inst : DFF_X1 port map( D => N5, CK => Clock, Q => SO_2_port, QN
=> net549722);
tmp_reg_4_inst : DFF_X1 port map( D => N7, CK => Clock, Q => SO_4_port, QN
=> net549721);
tmp_reg_6_inst : DFF_X1 port map( D => N9, CK => Clock, Q => SO_6_port, QN
=> net549720);
tmp_reg_8_inst : DFF_X1 port map( D => N11, CK => Clock, Q => SO_8_port, QN
=> net549719);
tmp_reg_10_inst : DFF_X1 port map( D => N13, CK => Clock, Q => SO_10_port,
QN => net549718);
tmp_reg_12_inst : DFF_X1 port map( D => N15, CK => Clock, Q => SO_12_port,
QN => net549717);
tmp_reg_14_inst : DFF_X1 port map( D => N17, CK => Clock, Q => SO_14_port,
QN => net549716);
tmp_reg_16_inst : DFF_X1 port map( D => N19, CK => Clock, Q => SO_16_port,
QN => net549715);
tmp_reg_18_inst : DFF_X1 port map( D => N21, CK => Clock, Q => SO_18_port,
QN => net549714);
tmp_reg_20_inst : DFF_X1 port map( D => N23, CK => Clock, Q => SO_20_port,
QN => net549713);
tmp_reg_22_inst : DFF_X1 port map( D => N25, CK => Clock, Q => SO_22_port,
QN => net549712);
tmp_reg_24_inst : DFF_X1 port map( D => N27, CK => Clock, Q => SO_24_port,
QN => net549711);
tmp_reg_26_inst : DFF_X1 port map( D => N29, CK => Clock, Q => SO_26_port,
QN => net549710);
tmp_reg_28_inst : DFF_X1 port map( D => N31, CK => Clock, Q => SO_28_port,
QN => net549709);
U26 : NAND2_X1 port map( A1 => ALOAD, A2 => D(26), ZN => n12_port);
U25 : OAI21_X1 port map( B1 => ALOAD, B2 => net549711, A => n12_port, ZN =>
N29);
U30 : NAND2_X1 port map( A1 => ALOAD, A2 => D(24), ZN => n14_port);
U29 : OAI21_X1 port map( B1 => ALOAD, B2 => net549712, A => n14_port, ZN =>
N27);
U32 : NAND2_X1 port map( A1 => ALOAD, A2 => D(23), ZN => n15_port);
U31 : OAI21_X1 port map( B1 => ALOAD, B2 => net549728, A => n15_port, ZN =>
N26);
U36 : NAND2_X1 port map( A1 => ALOAD, A2 => D(21), ZN => n17_port);
U35 : OAI21_X1 port map( B1 => ALOAD, B2 => net549729, A => n17_port, ZN =>
N24);
U38 : NAND2_X1 port map( A1 => ALOAD, A2 => D(20), ZN => n19_port);
U37 : OAI21_X1 port map( B1 => ALOAD, B2 => net549714, A => n19_port, ZN =>
N23);
U42 : NAND2_X1 port map( A1 => ALOAD, A2 => D(18), ZN => n21_port);
U41 : OAI21_X1 port map( B1 => ALOAD, B2 => net549715, A => n21_port, ZN =>
N21);
U44 : NAND2_X1 port map( A1 => ALOAD, A2 => D(17), ZN => n22_port);
U43 : OAI21_X1 port map( B1 => ALOAD, B2 => net549731, A => n22_port, ZN =>
N20);
U34 : NAND2_X1 port map( A1 => ALOAD, A2 => D(22), ZN => n16_port);
U33 : OAI21_X1 port map( B1 => ALOAD, B2 => net549713, A => n16_port, ZN =>
N25);
U46 : NAND2_X1 port map( A1 => ALOAD, A2 => D(16), ZN => n23_port);
U45 : OAI21_X1 port map( B1 => ALOAD, B2 => net549716, A => n23_port, ZN =>
N19);
U19 : NAND2_X1 port map( A1 => ALOAD, A2 => D(29), ZN => n9_port);
U18 : OAI21_X1 port map( B1 => ALOAD, B2 => net549725, A => n9_port, ZN =>
N32);
U23 : NAND2_X1 port map( A1 => ALOAD, A2 => D(27), ZN => n11_port);
U22 : OAI21_X1 port map( B1 => ALOAD, B2 => net549726, A => n11_port, ZN =>
N30);
U28 : NAND2_X1 port map( A1 => ALOAD, A2 => D(25), ZN => n13_port);
U27 : OAI21_X1 port map( B1 => ALOAD, B2 => net549727, A => n13_port, ZN =>
N28);
U21 : NAND2_X1 port map( A1 => ALOAD, A2 => D(28), ZN => n10_port);
U20 : OAI21_X1 port map( B1 => ALOAD, B2 => net549710, A => n10_port, ZN =>
N31);
U40 : NAND2_X1 port map( A1 => ALOAD, A2 => D(19), ZN => n20_port);
U39 : OAI21_X1 port map( B1 => ALOAD, B2 => net549730, A => n20_port, ZN =>
N22);
U12 : NAND2_X1 port map( A1 => ALOAD, A2 => D(2), ZN => n6_port);
U11 : OAI21_X1 port map( B1 => ALOAD, B2 => net549723, A => n6_port, ZN =>
N5);
U50 : NAND2_X1 port map( A1 => ALOAD, A2 => D(14), ZN => n25_port);
U49 : OAI21_X1 port map( B1 => ALOAD, B2 => net549717, A => n25_port, ZN =>
N17);
U54 : NAND2_X1 port map( A1 => ALOAD, A2 => D(12), ZN => n27_port);
U53 : OAI21_X1 port map( B1 => ALOAD, B2 => net549718, A => n27_port, ZN =>
N15);
U58 : NAND2_X1 port map( A1 => ALOAD, A2 => D(10), ZN => n29_port);
U57 : OAI21_X1 port map( B1 => ALOAD, B2 => net549719, A => n29_port, ZN =>
N13);
U62 : NAND2_X1 port map( A1 => ALOAD, A2 => D(8), ZN => n31_port);
U61 : OAI21_X1 port map( B1 => ALOAD, B2 => net549720, A => n31_port, ZN =>
N11);
U4 : NAND2_X1 port map( A1 => ALOAD, A2 => D(6), ZN => n1);
U3 : OAI21_X1 port map( B1 => ALOAD, B2 => net549721, A => n1, ZN => N9);
U8 : NAND2_X1 port map( A1 => ALOAD, A2 => D(4), ZN => n4_port);
U7 : OAI21_X1 port map( B1 => ALOAD, B2 => net549722, A => n4_port, ZN => N7
);
U64 : NAND2_X1 port map( A1 => ALOAD, A2 => D(7), ZN => n32_port);
U63 : OAI21_X1 port map( B1 => ALOAD, B2 => net549736, A => n32_port, ZN =>
N10);
U48 : NAND2_X1 port map( A1 => ALOAD, A2 => D(15), ZN => n24_port);
U47 : OAI21_X1 port map( B1 => ALOAD, B2 => net549732, A => n24_port, ZN =>
N18);
U52 : NAND2_X1 port map( A1 => ALOAD, A2 => D(13), ZN => n26_port);
U51 : OAI21_X1 port map( B1 => ALOAD, B2 => net549733, A => n26_port, ZN =>
N16);
U56 : NAND2_X1 port map( A1 => ALOAD, A2 => D(11), ZN => n28_port);
U55 : OAI21_X1 port map( B1 => ALOAD, B2 => net549734, A => n28_port, ZN =>
N14);
U60 : NAND2_X1 port map( A1 => ALOAD, A2 => D(9), ZN => n30_port);
U59 : OAI21_X1 port map( B1 => ALOAD, B2 => net549735, A => n30_port, ZN =>
N12);
U10 : NAND2_X1 port map( A1 => ALOAD, A2 => D(3), ZN => n5_port);
U9 : OAI21_X1 port map( B1 => ALOAD, B2 => net549738, A => n5_port, ZN => N6
);
U6 : NAND2_X1 port map( A1 => ALOAD, A2 => D(5), ZN => n3_port);
U5 : OAI21_X1 port map( B1 => ALOAD, B2 => net549737, A => n3_port, ZN => N8
);
U24 : AND2_X1 port map( A1 => ALOAD, A2 => D(0), ZN => N3);
U13 : AND2_X1 port map( A1 => ALOAD, A2 => D(1), ZN => N4);
tmp_reg_31_inst : SDFF_X1 port map( D => SO_29_port, SI => D(31), SE =>
ALOAD, CK => Clock, Q => SO_31_port, QN => n7_port);
tmp_reg_30_inst : SDFF_X1 port map( D => SO_28_port, SI => D(30), SE =>
ALOAD, CK => Clock, Q => SO_30_port, QN => n2);
end SYN_archi;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shift_N9_2 is
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (8 downto 0);
SO : out std_logic);
end shift_N9_2;
architecture SYN_archi of shift_N9_2 is
component SDFF_X1
port( D, SI, SE, CK : in std_logic; Q, QN : out std_logic);
end component;
signal tmp_8_port, tmp_7_port, tmp_6_port, tmp_5_port, tmp_4_port,
tmp_3_port, tmp_2_port, tmp_1_port, n2, n3, n4, n5, n6, n7, n8, n9, n10,
n11 : std_logic;
begin
tmp_reg_7_inst : SDFF_X1 port map( D => tmp_8_port, SI => D(7), SE => ALOAD,
CK => Clock, Q => tmp_7_port, QN => n11);
tmp_reg_0_inst : SDFF_X1 port map( D => tmp_1_port, SI => D(0), SE => ALOAD,
CK => Clock, Q => SO, QN => n10);
tmp_reg_6_inst : SDFF_X1 port map( D => tmp_7_port, SI => D(6), SE => ALOAD,
CK => Clock, Q => tmp_6_port, QN => n9);
tmp_reg_2_inst : SDFF_X1 port map( D => tmp_3_port, SI => D(2), SE => ALOAD,
CK => Clock, Q => tmp_2_port, QN => n8);
tmp_reg_5_inst : SDFF_X1 port map( D => tmp_6_port, SI => D(5), SE => ALOAD,
CK => Clock, Q => tmp_5_port, QN => n7);
tmp_reg_4_inst : SDFF_X1 port map( D => tmp_5_port, SI => D(4), SE => ALOAD,
CK => Clock, Q => tmp_4_port, QN => n6);
tmp_reg_3_inst : SDFF_X1 port map( D => tmp_4_port, SI => D(3), SE => ALOAD,
CK => Clock, Q => tmp_3_port, QN => n5);
tmp_reg_8_inst : SDFF_X1 port map( D => n3, SI => D(8), SE => ALOAD, CK =>
Clock, Q => tmp_8_port, QN => n4);
tmp_reg_1_inst : SDFF_X1 port map( D => tmp_2_port, SI => D(1), SE => ALOAD,
CK => Clock, Q => tmp_1_port, QN => n2);
n3 <= '0';
end SYN_archi;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shift_N9_0 is
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (8 downto 0);
SO : out std_logic);
end shift_N9_0;
architecture SYN_archi of shift_N9_0 is
component SDFF_X2
port( D, SI, SE, CK : in std_logic; Q, QN : out std_logic);
end component;
component SDFF_X1
port( D, SI, SE, CK : in std_logic; Q, QN : out std_logic);
end component;
signal tmp_8_port, tmp_7_port, tmp_6_port, tmp_5_port, tmp_4_port,
tmp_3_port, tmp_2_port, tmp_1_port, n2, n3, n4, n5, n6, n7, n8, n9, n10,
n11 : std_logic;
begin
tmp_reg_7_inst : SDFF_X1 port map( D => tmp_8_port, SI => D(7), SE => ALOAD,
CK => Clock, Q => tmp_7_port, QN => n11);
tmp_reg_3_inst : SDFF_X1 port map( D => tmp_4_port, SI => D(3), SE => ALOAD,
CK => Clock, Q => tmp_3_port, QN => n10);
tmp_reg_4_inst : SDFF_X1 port map( D => tmp_5_port, SI => D(4), SE => ALOAD,
CK => Clock, Q => tmp_4_port, QN => n9);
tmp_reg_5_inst : SDFF_X1 port map( D => tmp_6_port, SI => D(5), SE => ALOAD,
CK => Clock, Q => tmp_5_port, QN => n8);
tmp_reg_6_inst : SDFF_X1 port map( D => tmp_7_port, SI => D(6), SE => ALOAD,
CK => Clock, Q => tmp_6_port, QN => n7);
tmp_reg_1_inst : SDFF_X1 port map( D => tmp_2_port, SI => D(1), SE => ALOAD,
CK => Clock, Q => tmp_1_port, QN => n6);
tmp_reg_2_inst : SDFF_X1 port map( D => tmp_3_port, SI => D(2), SE => ALOAD,
CK => Clock, Q => tmp_2_port, QN => n5);
tmp_reg_8_inst : SDFF_X1 port map( D => n3, SI => D(8), SE => ALOAD, CK =>
Clock, Q => tmp_8_port, QN => n4);
tmp_reg_0_inst : SDFF_X2 port map( D => tmp_1_port, SI => D(0), SE => ALOAD,
CK => Clock, Q => SO, QN => n2);
n3 <= '0';
end SYN_archi;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity booth_encoder_0 is
port( B_in : in std_logic_vector (2 downto 0); A_out : out std_logic_vector
(2 downto 0));
end booth_encoder_0;
architecture SYN_bhe of booth_encoder_0 is
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
signal N53, N57, n5, n6 : std_logic;
begin
A_out <= ( N57, B_in(2), N53 );
U3 : INV_X1 port map( A => B_in(1), ZN => n5);
U4 : INV_X1 port map( A => B_in(2), ZN => n6);
U5 : NAND2_X1 port map( A1 => n6, A2 => n5, ZN => N57);
U6 : NOR2_X1 port map( A1 => B_in(1), A2 => n6, ZN => N53);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity logic_unit_SIZE32 is
port( IN1, IN2 : in std_logic_vector (31 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (31 downto
0));
end logic_unit_SIZE32;
architecture SYN_Bhe of logic_unit_SIZE32 is
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component OAI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X2
port( A : in std_logic; Z : out std_logic);
end component;
component INV_X2
port( A : in std_logic; ZN : out std_logic);
end component;
signal n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31
, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45,
n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60
, n61, n62, n63, n64, n166, n167, n169 : std_logic;
begin
U25 : AOI21_X1 port map( B1 => IN2(31), B2 => IN1(31), A => CTRL(0), ZN =>
n17);
U24 : OAI22_X1 port map( A1 => IN1(31), A2 => IN2(31), B1 => n2, B2 => n17,
ZN => n18);
U23 : AOI21_X1 port map( B1 => n169, B2 => n17, A => n18, ZN => OUT1(31));
U65 : AOI21_X1 port map( B1 => n2, B2 => n45, A => n46, ZN => OUT1(19));
U61 : AOI21_X1 port map( B1 => IN2(20), B2 => IN1(20), A => CTRL(0), ZN =>
n41);
U60 : OAI22_X1 port map( A1 => IN1(20), A2 => IN2(20), B1 => n169, B2 => n41
, ZN => n42);
U59 : AOI21_X1 port map( B1 => n169, B2 => n41, A => n42, ZN => OUT1(20));
U56 : AOI21_X1 port map( B1 => n2, B2 => n39, A => n40, ZN => OUT1(21));
U20 : AOI21_X1 port map( B1 => n169, B2 => n15, A => n16, ZN => OUT1(3));
U54 : OAI22_X1 port map( A1 => IN1(22), A2 => IN2(22), B1 => n169, B2 => n37
, ZN => n38);
U53 : AOI21_X1 port map( B1 => n169, B2 => n37, A => n38, ZN => OUT1(22));
U49 : AOI21_X1 port map( B1 => IN2(24), B2 => IN1(24), A => CTRL(0), ZN =>
n33);
U48 : OAI22_X1 port map( A1 => IN1(24), A2 => IN2(24), B1 => n2, B2 => n33,
ZN => n34);
U47 : AOI21_X1 port map( B1 => n169, B2 => n33, A => n34, ZN => OUT1(24));
U77 : AOI21_X1 port map( B1 => n169, B2 => n53, A => n54, ZN => OUT1(15));
U5 : AOI21_X1 port map( B1 => n2, B2 => n5, A => n6, ZN => OUT1(8));
U11 : AOI21_X1 port map( B1 => n2, B2 => n9, A => n10, ZN => OUT1(6));
U46 : AOI21_X1 port map( B1 => IN2(25), B2 => IN1(25), A => CTRL(0), ZN =>
n31);
U45 : OAI22_X1 port map( A1 => IN1(25), A2 => IN2(25), B1 => n2, B2 => n31,
ZN => n32);
U44 : AOI21_X1 port map( B1 => n169, B2 => n31, A => n32, ZN => OUT1(25));
U71 : AOI21_X1 port map( B1 => n169, B2 => n49, A => n50, ZN => OUT1(17));
U86 : AOI21_X1 port map( B1 => n2, B2 => n59, A => n60, ZN => OUT1(12));
U76 : AOI21_X1 port map( B1 => IN2(16), B2 => IN1(16), A => CTRL(0), ZN =>
n51);
U75 : OAI22_X1 port map( A1 => IN1(16), A2 => IN2(16), B1 => n2, B2 => n51,
ZN => n52);
U74 : AOI21_X1 port map( B1 => n169, B2 => n51, A => n52, ZN => OUT1(16));
U37 : AOI21_X1 port map( B1 => IN2(28), B2 => IN1(28), A => CTRL(0), ZN =>
n25);
U36 : OAI22_X1 port map( A1 => IN1(28), A2 => IN2(28), B1 => n2, B2 => n25,
ZN => n26);
U35 : AOI21_X1 port map( B1 => n169, B2 => n25, A => n26, ZN => OUT1(28));
U19 : AOI21_X1 port map( B1 => IN2(4), B2 => IN1(4), A => CTRL(0), ZN => n13
);
U18 : OAI22_X1 port map( A1 => IN1(4), A2 => IN2(4), B1 => n169, B2 => n13,
ZN => n14);
U17 : AOI21_X1 port map( B1 => n169, B2 => n13, A => n14, ZN => OUT1(4));
U40 : AOI21_X1 port map( B1 => IN2(27), B2 => IN1(27), A => CTRL(0), ZN =>
n27);
U39 : OAI22_X1 port map( A1 => IN1(27), A2 => IN2(27), B1 => n2, B2 => n27,
ZN => n28);
U38 : AOI21_X1 port map( B1 => n2, B2 => n27, A => n28, ZN => OUT1(27));
U14 : AOI21_X1 port map( B1 => n2, B2 => n11, A => n12, ZN => OUT1(5));
U83 : AOI21_X1 port map( B1 => n169, B2 => n57, A => n58, ZN => OUT1(13));
U2 : AOI21_X1 port map( B1 => n2, B2 => n3, A => n4, ZN => OUT1(9));
U8 : AOI21_X1 port map( B1 => n169, B2 => n7, A => n8, ZN => OUT1(7));
U80 : AOI21_X1 port map( B1 => n2, B2 => n55, A => n56, ZN => OUT1(14));
U68 : AOI21_X1 port map( B1 => n169, B2 => n47, A => n48, ZN => OUT1(18));
U50 : AOI21_X1 port map( B1 => n169, B2 => n35, A => n36, ZN => OUT1(23));
U41 : AOI21_X1 port map( B1 => n2, B2 => n29, A => n30, ZN => OUT1(26));
U34 : AOI21_X1 port map( B1 => IN2(29), B2 => IN1(29), A => CTRL(0), ZN =>
n23);
U33 : OAI22_X1 port map( A1 => IN1(29), A2 => IN2(29), B1 => n2, B2 => n23,
ZN => n24);
U32 : AOI21_X1 port map( B1 => n169, B2 => n23, A => n24, ZN => OUT1(29));
U31 : AOI21_X1 port map( B1 => IN2(2), B2 => IN1(2), A => CTRL(0), ZN => n21
);
U30 : OAI22_X1 port map( A1 => IN1(2), A2 => IN2(2), B1 => n2, B2 => n21, ZN
=> n22);
U29 : AOI21_X1 port map( B1 => n2, B2 => n21, A => n22, ZN => OUT1(2));
U62 : AOI21_X1 port map( B1 => n169, B2 => n43, A => n44, ZN => OUT1(1));
U28 : AOI21_X1 port map( B1 => IN2(30), B2 => IN1(30), A => CTRL(0), ZN =>
n19);
U27 : OAI22_X1 port map( A1 => IN1(30), A2 => IN2(30), B1 => n2, B2 => n19,
ZN => n20);
U26 : AOI21_X1 port map( B1 => n2, B2 => n19, A => n20, ZN => OUT1(30));
U89 : AOI21_X1 port map( B1 => n169, B2 => n61, A => n62, ZN => OUT1(11));
U92 : AOI21_X1 port map( B1 => n169, B2 => n63, A => n64, ZN => OUT1(10));
U3 : AOI21_X1 port map( B1 => IN1(0), B2 => IN2(0), A => CTRL(0), ZN => n166
);
U4 : OAI22_X1 port map( A1 => IN2(0), A2 => IN1(0), B1 => n2, B2 => n166, ZN
=> n167);
U6 : AOI21_X1 port map( B1 => n2, B2 => n166, A => n167, ZN => OUT1(0));
U7 : INV_X2 port map( A => CTRL(1), ZN => n2);
U9 : BUF_X2 port map( A => n2, Z => n169);
U10 : OAI22_X1 port map( A1 => IN1(18), A2 => IN2(18), B1 => n169, B2 => n47
, ZN => n48);
U12 : AOI21_X1 port map( B1 => IN2(18), B2 => IN1(18), A => CTRL(0), ZN =>
n47);
U13 : OAI22_X1 port map( A1 => IN1(10), A2 => IN2(10), B1 => n2, B2 => n63,
ZN => n64);
U15 : AOI21_X1 port map( B1 => IN2(10), B2 => IN1(10), A => CTRL(0), ZN =>
n63);
U16 : OAI22_X1 port map( A1 => IN1(21), A2 => IN2(21), B1 => n169, B2 => n39
, ZN => n40);
U21 : AOI21_X1 port map( B1 => IN2(21), B2 => IN1(21), A => CTRL(0), ZN =>
n39);
U22 : OAI22_X1 port map( A1 => IN1(26), A2 => IN2(26), B1 => n169, B2 => n29
, ZN => n30);
U42 : AOI21_X1 port map( B1 => IN2(26), B2 => IN1(26), A => CTRL(0), ZN =>
n29);
U43 : OAI22_X1 port map( A1 => IN1(12), A2 => IN2(12), B1 => n2, B2 => n59,
ZN => n60);
U51 : AOI21_X1 port map( B1 => IN2(12), B2 => IN1(12), A => CTRL(0), ZN =>
n59);
U52 : OAI22_X1 port map( A1 => IN1(3), A2 => IN2(3), B1 => n169, B2 => n15,
ZN => n16);
U55 : AOI21_X1 port map( B1 => IN2(3), B2 => IN1(3), A => CTRL(0), ZN => n15
);
U57 : OAI22_X1 port map( A1 => IN1(1), A2 => IN2(1), B1 => n169, B2 => n43,
ZN => n44);
U58 : AOI21_X1 port map( B1 => IN2(1), B2 => IN1(1), A => CTRL(0), ZN => n43
);
U63 : OAI22_X1 port map( A1 => IN1(17), A2 => IN2(17), B1 => n169, B2 => n49
, ZN => n50);
U64 : AOI21_X1 port map( B1 => IN2(17), B2 => IN1(17), A => CTRL(0), ZN =>
n49);
U66 : OAI22_X1 port map( A1 => IN1(14), A2 => IN2(14), B1 => n2, B2 => n55,
ZN => n56);
U67 : AOI21_X1 port map( B1 => IN2(14), B2 => IN1(14), A => CTRL(0), ZN =>
n55);
U69 : OAI22_X1 port map( A1 => IN1(23), A2 => IN2(23), B1 => n169, B2 => n35
, ZN => n36);
U70 : AOI21_X1 port map( B1 => IN2(23), B2 => IN1(23), A => CTRL(0), ZN =>
n35);
U72 : OAI22_X1 port map( A1 => IN1(13), A2 => IN2(13), B1 => n2, B2 => n57,
ZN => n58);
U73 : AOI21_X1 port map( B1 => IN2(13), B2 => IN1(13), A => CTRL(0), ZN =>
n57);
U78 : OAI22_X1 port map( A1 => IN1(8), A2 => IN2(8), B1 => n2, B2 => n5, ZN
=> n6);
U79 : AOI21_X1 port map( B1 => IN2(8), B2 => IN1(8), A => CTRL(0), ZN => n5)
;
U81 : OAI22_X1 port map( A1 => IN1(6), A2 => IN2(6), B1 => n2, B2 => n9, ZN
=> n10);
U82 : AOI21_X1 port map( B1 => IN2(6), B2 => IN1(6), A => CTRL(0), ZN => n9)
;
U84 : OAI22_X1 port map( A1 => IN1(19), A2 => IN2(19), B1 => n169, B2 => n45
, ZN => n46);
U85 : AOI21_X1 port map( B1 => IN2(19), B2 => IN1(19), A => CTRL(0), ZN =>
n45);
U87 : OAI22_X1 port map( A1 => IN1(15), A2 => IN2(15), B1 => n2, B2 => n53,
ZN => n54);
U88 : AOI21_X1 port map( B1 => IN2(15), B2 => IN1(15), A => CTRL(0), ZN =>
n53);
U90 : AOI21_X1 port map( B1 => IN2(22), B2 => IN1(22), A => CTRL(0), ZN =>
n37);
U91 : OAI22_X1 port map( A1 => IN1(11), A2 => IN2(11), B1 => n2, B2 => n61,
ZN => n62);
U93 : AOI21_X1 port map( B1 => IN2(11), B2 => IN1(11), A => CTRL(0), ZN =>
n61);
U94 : OAI22_X1 port map( A1 => IN1(7), A2 => IN2(7), B1 => n2, B2 => n7, ZN
=> n8);
U95 : AOI21_X1 port map( B1 => IN2(7), B2 => IN1(7), A => CTRL(0), ZN => n7)
;
U96 : OAI22_X1 port map( A1 => IN1(9), A2 => IN2(9), B1 => n2, B2 => n3, ZN
=> n4);
U97 : AOI21_X1 port map( B1 => IN2(9), B2 => IN1(9), A => CTRL(0), ZN => n3)
;
U98 : OAI22_X1 port map( A1 => IN1(5), A2 => IN2(5), B1 => n169, B2 => n11,
ZN => n12);
U99 : AOI21_X1 port map( B1 => IN2(5), B2 => IN1(5), A => CTRL(0), ZN => n11
);
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity shifter is
port( A : in std_logic_vector (31 downto 0); B : in std_logic_vector (4
downto 0); LOGIC_ARITH, LEFT_RIGHT : in std_logic; OUTPUT : out
std_logic_vector (31 downto 0));
end shifter;
architecture SYN_struct of shifter is
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component shift_thirdLevel
port( sel : in std_logic_vector (2 downto 0); A : in std_logic_vector
(38 downto 0); Y : out std_logic_vector (31 downto 0));
end component;
component shift_secondLevel
port( sel : in std_logic_vector (1 downto 0); mask00, mask08, mask16 :
in std_logic_vector (38 downto 0); Y : out std_logic_vector (38
downto 0));
end component;
component shift_firstLevel
port( A : in std_logic_vector (31 downto 0); sel : in std_logic_vector
(1 downto 0); mask00, mask08, mask16 : out std_logic_vector (38
downto 0));
end component;
signal s3_2_port, s3_1_port, s3_0_port, m0_38_port, m0_37_port, m0_36_port,
m0_35_port, m0_34_port, m0_33_port, m0_32_port, m0_31_port, m0_30_port,
m0_29_port, m0_28_port, m0_27_port, m0_26_port, m0_25_port, m0_24_port,
m0_23_port, m0_22_port, m0_21_port, m0_20_port, m0_19_port, m0_18_port,
m0_17_port, m0_16_port, m0_15_port, m0_14_port, m0_13_port, m0_12_port,
m0_11_port, m0_10_port, m0_9_port, m0_8_port, m0_7_port, m0_6_port,
m0_5_port, m0_4_port, m0_3_port, m0_2_port, m0_1_port, m0_0_port,
m8_38_port, m8_37_port, m8_36_port, m8_35_port, m8_34_port, m8_33_port,
m8_32_port, m8_31_port, m8_30_port, m8_29_port, m8_28_port, m8_27_port,
m8_26_port, m8_25_port, m8_24_port, m8_23_port, m8_22_port, m8_21_port,
m8_20_port, m8_19_port, m8_18_port, m8_17_port, m8_16_port, m8_15_port,
m8_14_port, m8_13_port, m8_12_port, m8_11_port, m8_10_port, m8_9_port,
m8_8_port, m8_7_port, m8_6_port, m8_5_port, m8_4_port, m8_3_port,
m8_2_port, m8_1_port, m8_0_port, m16_38_port, m16_37_port, m16_36_port,
m16_35_port, m16_34_port, m16_33_port, m16_32_port, m16_31_port,
m16_30_port, m16_29_port, m16_28_port, m16_27_port, m16_26_port,
m16_25_port, m16_24_port, m16_23_port, m16_15_port, m16_14_port,
m16_13_port, m16_12_port, m16_11_port, m16_10_port, m16_9_port,
m16_8_port, m16_7_port, m16_6_port, m16_5_port, m16_4_port, m16_3_port,
m16_2_port, m16_1_port, m16_0_port, y_38_port, y_37_port, y_36_port,
y_35_port, y_34_port, y_33_port, y_32_port, y_31_port, y_30_port,
y_29_port, y_28_port, y_27_port, y_26_port, y_25_port, y_24_port,
y_23_port, y_22_port, y_21_port, y_20_port, y_19_port, y_18_port,
y_17_port, y_16_port, y_15_port, y_14_port, y_13_port, y_12_port,
y_11_port, y_10_port, y_9_port, y_8_port, y_7_port, y_6_port, y_5_port,
y_4_port, y_3_port, y_2_port, y_1_port, y_0_port, n5, n7, n8, n9, n2, n3,
n4, n6, n10, n11, n12, n14 : std_logic;
begin
IL : shift_firstLevel port map( A(31) => A(31), A(30) => A(30), A(29) =>
A(29), A(28) => A(28), A(27) => A(27), A(26) =>
A(26), A(25) => A(25), A(24) => A(24), A(23) =>
A(23), A(22) => A(22), A(21) => A(21), A(20) =>
A(20), A(19) => A(19), A(18) => A(18), A(17) =>
A(17), A(16) => A(16), A(15) => A(15), A(14) =>
A(14), A(13) => A(13), A(12) => A(12), A(11) =>
A(11), A(10) => A(10), A(9) => A(9), A(8) => A(8),
A(7) => A(7), A(6) => A(6), A(5) => A(5), A(4) =>
A(4), A(3) => A(3), A(2) => A(2), A(1) => A(1), A(0)
=> A(0), sel(1) => LOGIC_ARITH, sel(0) => LEFT_RIGHT
, mask00(38) => m0_38_port, mask00(37) => m0_37_port
, mask00(36) => m0_36_port, mask00(35) => m0_35_port
, mask00(34) => m0_34_port, mask00(33) => m0_33_port
, mask00(32) => m0_32_port, mask00(31) => m0_31_port
, mask00(30) => m0_30_port, mask00(29) => m0_29_port
, mask00(28) => m0_28_port, mask00(27) => m0_27_port
, mask00(26) => m0_26_port, mask00(25) => m0_25_port
, mask00(24) => m0_24_port, mask00(23) => m0_23_port
, mask00(22) => m0_22_port, mask00(21) => m0_21_port
, mask00(20) => m0_20_port, mask00(19) => m0_19_port
, mask00(18) => m0_18_port, mask00(17) => m0_17_port
, mask00(16) => m0_16_port, mask00(15) => m0_15_port
, mask00(14) => m0_14_port, mask00(13) => m0_13_port
, mask00(12) => m0_12_port, mask00(11) => m0_11_port
, mask00(10) => m0_10_port, mask00(9) => m0_9_port,
mask00(8) => m0_8_port, mask00(7) => m0_7_port,
mask00(6) => m0_6_port, mask00(5) => m0_5_port,
mask00(4) => m0_4_port, mask00(3) => m0_3_port,
mask00(2) => m0_2_port, mask00(1) => m0_1_port,
mask00(0) => m0_0_port, mask08(38) => m8_38_port,
mask08(37) => m8_37_port, mask08(36) => m8_36_port,
mask08(35) => m8_35_port, mask08(34) => m8_34_port,
mask08(33) => m8_33_port, mask08(32) => m8_32_port,
mask08(31) => m8_31_port, mask08(30) => m8_30_port,
mask08(29) => m8_29_port, mask08(28) => m8_28_port,
mask08(27) => m8_27_port, mask08(26) => m8_26_port,
mask08(25) => m8_25_port, mask08(24) => m8_24_port,
mask08(23) => m8_23_port, mask08(22) => m8_22_port,
mask08(21) => m8_21_port, mask08(20) => m8_20_port,
mask08(19) => m8_19_port, mask08(18) => m8_18_port,
mask08(17) => m8_17_port, mask08(16) => m8_16_port,
mask08(15) => m8_15_port, mask08(14) => m8_14_port,
mask08(13) => m8_13_port, mask08(12) => m8_12_port,
mask08(11) => m8_11_port, mask08(10) => m8_10_port,
mask08(9) => m8_9_port, mask08(8) => m8_8_port,
mask08(7) => m8_7_port, mask08(6) => m8_6_port,
mask08(5) => m8_5_port, mask08(4) => m8_4_port,
mask08(3) => m8_3_port, mask08(2) => m8_2_port,
mask08(1) => m8_1_port, mask08(0) => m8_0_port,
mask16(38) => m16_38_port, mask16(37) => m16_37_port
, mask16(36) => m16_36_port, mask16(35) =>
m16_35_port, mask16(34) => m16_34_port, mask16(33)
=> m16_33_port, mask16(32) => m16_32_port,
mask16(31) => m16_31_port, mask16(30) => m16_30_port
, mask16(29) => m16_29_port, mask16(28) =>
m16_28_port, mask16(27) => m16_27_port, mask16(26)
=> m16_26_port, mask16(25) => m16_25_port,
mask16(24) => m16_24_port, mask16(23) => m16_23_port
, mask16(22) => n3, mask16(21) => n11, mask16(20) =>
n6, mask16(19) => n2, mask16(18) => n12, mask16(17)
=> n4, mask16(16) => n10, mask16(15) => m16_15_port,
mask16(14) => m16_14_port, mask16(13) => m16_13_port
, mask16(12) => m16_12_port, mask16(11) =>
m16_11_port, mask16(10) => m16_10_port, mask16(9) =>
m16_9_port, mask16(8) => m16_8_port, mask16(7) =>
m16_7_port, mask16(6) => m16_6_port, mask16(5) =>
m16_5_port, mask16(4) => m16_4_port, mask16(3) =>
m16_3_port, mask16(2) => m16_2_port, mask16(1) =>
m16_1_port, mask16(0) => m16_0_port);
IIL : shift_secondLevel port map( sel(1) => B(4), sel(0) => B(3), mask00(38)
=> m0_38_port, mask00(37) => m0_37_port, mask00(36)
=> m0_36_port, mask00(35) => m0_35_port, mask00(34)
=> m0_34_port, mask00(33) => m0_33_port, mask00(32)
=> m0_32_port, mask00(31) => m0_31_port, mask00(30)
=> m0_30_port, mask00(29) => m0_29_port, mask00(28)
=> m0_28_port, mask00(27) => m0_27_port, mask00(26)
=> m0_26_port, mask00(25) => m0_25_port, mask00(24)
=> m0_24_port, mask00(23) => m0_23_port, mask00(22)
=> m0_22_port, mask00(21) => m0_21_port, mask00(20)
=> m0_20_port, mask00(19) => m0_19_port, mask00(18)
=> m0_18_port, mask00(17) => m0_17_port, mask00(16)
=> m0_16_port, mask00(15) => m0_15_port, mask00(14)
=> m0_14_port, mask00(13) => m0_13_port, mask00(12)
=> m0_12_port, mask00(11) => m0_11_port, mask00(10)
=> m0_10_port, mask00(9) => m0_9_port, mask00(8) =>
m0_8_port, mask00(7) => m0_7_port, mask00(6) =>
m0_6_port, mask00(5) => m0_5_port, mask00(4) =>
m0_4_port, mask00(3) => m0_3_port, mask00(2) =>
m0_2_port, mask00(1) => m0_1_port, mask00(0) =>
m0_0_port, mask08(38) => m8_38_port, mask08(37) =>
m8_37_port, mask08(36) => m8_36_port, mask08(35) =>
m8_35_port, mask08(34) => m8_34_port, mask08(33) =>
m8_33_port, mask08(32) => m8_32_port, mask08(31) =>
m8_31_port, mask08(30) => m8_30_port, mask08(29) =>
m8_29_port, mask08(28) => m8_28_port, mask08(27) =>
m8_27_port, mask08(26) => m8_26_port, mask08(25) =>
m8_25_port, mask08(24) => m8_24_port, mask08(23) =>
m8_23_port, mask08(22) => m8_22_port, mask08(21) =>
m8_21_port, mask08(20) => m8_20_port, mask08(19) =>
m8_19_port, mask08(18) => m8_18_port, mask08(17) =>
m8_17_port, mask08(16) => m8_16_port, mask08(15) =>
m8_15_port, mask08(14) => m8_14_port, mask08(13) =>
m8_13_port, mask08(12) => m8_12_port, mask08(11) =>
m8_11_port, mask08(10) => m8_10_port, mask08(9) =>
m8_9_port, mask08(8) => m8_8_port, mask08(7) =>
m8_7_port, mask08(6) => m8_6_port, mask08(5) =>
m8_5_port, mask08(4) => m8_4_port, mask08(3) =>
m8_3_port, mask08(2) => m8_2_port, mask08(1) =>
m8_1_port, mask08(0) => m8_0_port, mask16(38) =>
m16_38_port, mask16(37) => m16_37_port, mask16(36)
=> m16_36_port, mask16(35) => m16_35_port,
mask16(34) => m16_34_port, mask16(33) => m16_33_port
, mask16(32) => m16_32_port, mask16(31) =>
m16_31_port, mask16(30) => m16_30_port, mask16(29)
=> m16_29_port, mask16(28) => m16_28_port,
mask16(27) => m16_27_port, mask16(26) => m16_26_port
, mask16(25) => m16_25_port, mask16(24) =>
m16_24_port, mask16(23) => m16_23_port, mask16(22)
=> n3, mask16(21) => n11, mask16(20) => n6,
mask16(19) => n2, mask16(18) => n12, mask16(17) =>
n4, mask16(16) => n10, mask16(15) => m16_15_port,
mask16(14) => m16_14_port, mask16(13) => m16_13_port
, mask16(12) => m16_12_port, mask16(11) =>
m16_11_port, mask16(10) => m16_10_port, mask16(9) =>
m16_9_port, mask16(8) => m16_8_port, mask16(7) =>
m16_7_port, mask16(6) => m16_6_port, mask16(5) =>
m16_5_port, mask16(4) => m16_4_port, mask16(3) =>
m16_3_port, mask16(2) => m16_2_port, mask16(1) =>
m16_1_port, mask16(0) => m16_0_port, Y(38) =>
y_38_port, Y(37) => y_37_port, Y(36) => y_36_port,
Y(35) => y_35_port, Y(34) => y_34_port, Y(33) =>
y_33_port, Y(32) => y_32_port, Y(31) => y_31_port,
Y(30) => y_30_port, Y(29) => y_29_port, Y(28) =>
y_28_port, Y(27) => y_27_port, Y(26) => y_26_port,
Y(25) => y_25_port, Y(24) => y_24_port, Y(23) =>
y_23_port, Y(22) => y_22_port, Y(21) => y_21_port,
Y(20) => y_20_port, Y(19) => y_19_port, Y(18) =>
y_18_port, Y(17) => y_17_port, Y(16) => y_16_port,
Y(15) => y_15_port, Y(14) => y_14_port, Y(13) =>
y_13_port, Y(12) => y_12_port, Y(11) => y_11_port,
Y(10) => y_10_port, Y(9) => y_9_port, Y(8) =>
y_8_port, Y(7) => y_7_port, Y(6) => y_6_port, Y(5)
=> y_5_port, Y(4) => y_4_port, Y(3) => y_3_port,
Y(2) => y_2_port, Y(1) => y_1_port, Y(0) => y_0_port
);
IIIL : shift_thirdLevel port map( sel(2) => s3_2_port, sel(1) => s3_1_port,
sel(0) => s3_0_port, A(38) => y_38_port, A(37) =>
y_37_port, A(36) => y_36_port, A(35) => y_35_port,
A(34) => y_34_port, A(33) => y_33_port, A(32) =>
y_32_port, A(31) => y_31_port, A(30) => y_30_port,
A(29) => y_29_port, A(28) => y_28_port, A(27) =>
y_27_port, A(26) => y_26_port, A(25) => y_25_port,
A(24) => y_24_port, A(23) => y_23_port, A(22) =>
y_22_port, A(21) => y_21_port, A(20) => y_20_port,
A(19) => y_19_port, A(18) => y_18_port, A(17) =>
y_17_port, A(16) => y_16_port, A(15) => y_15_port,
A(14) => y_14_port, A(13) => y_13_port, A(12) =>
y_12_port, A(11) => y_11_port, A(10) => y_10_port,
A(9) => y_9_port, A(8) => y_8_port, A(7) => y_7_port
, A(6) => y_6_port, A(5) => y_5_port, A(4) =>
y_4_port, A(3) => y_3_port, A(2) => y_2_port, A(1)
=> y_1_port, A(0) => y_0_port, Y(31) => OUTPUT(31),
Y(30) => OUTPUT(30), Y(29) => OUTPUT(29), Y(28) =>
OUTPUT(28), Y(27) => OUTPUT(27), Y(26) => OUTPUT(26)
, Y(25) => OUTPUT(25), Y(24) => OUTPUT(24), Y(23) =>
OUTPUT(23), Y(22) => OUTPUT(22), Y(21) => OUTPUT(21)
, Y(20) => OUTPUT(20), Y(19) => OUTPUT(19), Y(18) =>
OUTPUT(18), Y(17) => OUTPUT(17), Y(16) => OUTPUT(16)
, Y(15) => OUTPUT(15), Y(14) => OUTPUT(14), Y(13) =>
OUTPUT(13), Y(12) => OUTPUT(12), Y(11) => OUTPUT(11)
, Y(10) => OUTPUT(10), Y(9) => OUTPUT(9), Y(8) =>
OUTPUT(8), Y(7) => OUTPUT(7), Y(6) => OUTPUT(6),
Y(5) => OUTPUT(5), Y(4) => OUTPUT(4), Y(3) =>
OUTPUT(3), Y(2) => OUTPUT(2), Y(1) => OUTPUT(1),
Y(0) => OUTPUT(0));
U1 : AOI22_X1 port map( A1 => B(2), A2 => n5, B1 => n14, B2 => n7, ZN =>
s3_2_port);
U8 : OR2_X1 port map( A1 => LOGIC_ARITH, A2 => LEFT_RIGHT, ZN => n5);
U2 : INV_X1 port map( A => B(2), ZN => n7);
U3 : INV_X1 port map( A => B(1), ZN => n8);
U4 : INV_X1 port map( A => B(0), ZN => n9);
U5 : INV_X1 port map( A => LEFT_RIGHT, ZN => n14);
U6 : AOI22_X1 port map( A1 => B(0), A2 => n5, B1 => n14, B2 => n9, ZN =>
s3_0_port);
U7 : AOI22_X1 port map( A1 => B(1), A2 => n5, B1 => n14, B2 => n8, ZN =>
s3_1_port);
end SYN_struct;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity comparator_M32 is
port( C, V : in std_logic; SUM : in std_logic_vector (31 downto 0); sel :
in std_logic_vector (2 downto 0); sign : in std_logic; S : out
std_logic);
end comparator_M32;
architecture SYN_BEHAVIORAL of comparator_M32 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI211_X1
port( C1, C2, A, B : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component AND4_X1
port( A1, A2, A3, A4 : in std_logic; ZN : out std_logic);
end component;
component AND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component NOR4_X1
port( A1, A2, A3, A4 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OR3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
signal n3, n11, n12, n23, n22, n21, n20, n19, n18, n17, n16, n25, n26, n27,
n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41 :
std_logic;
begin
U21 : NOR2_X1 port map( A1 => sel(2), A2 => sel(1), ZN => n3);
U1 : INV_X1 port map( A => sel(2), ZN => n36);
U2 : OR2_X1 port map( A1 => sel(0), A2 => sel(2), ZN => n25);
U3 : NAND2_X1 port map( A1 => n38, A2 => n25, ZN => n34);
U4 : OR3_X1 port map( A1 => SUM(4), A2 => SUM(5), A3 => SUM(3), ZN => n29);
U5 : NOR4_X1 port map( A1 => SUM(9), A2 => SUM(8), A3 => SUM(7), A4 =>
SUM(6), ZN => n17);
U6 : NOR2_X1 port map( A1 => SUM(31), A2 => n29, ZN => n16);
U7 : NOR4_X1 port map( A1 => SUM(30), A2 => SUM(2), A3 => SUM(29), A4 =>
SUM(28), ZN => n19);
U8 : NOR4_X1 port map( A1 => SUM(27), A2 => SUM(26), A3 => SUM(25), A4 =>
SUM(24), ZN => n18);
U9 : AND2_X1 port map( A1 => n16, A2 => n17, ZN => n28);
U10 : NOR4_X1 port map( A1 => SUM(17), A2 => SUM(19), A3 => SUM(18), A4 =>
SUM(1), ZN => n20);
U11 : NOR4_X1 port map( A1 => SUM(12), A2 => SUM(11), A3 => SUM(10), A4 =>
SUM(0), ZN => n22);
U12 : NOR4_X1 port map( A1 => SUM(16), A2 => SUM(15), A3 => SUM(14), A4 =>
SUM(13), ZN => n23);
U13 : NOR4_X1 port map( A1 => SUM(23), A2 => SUM(22), A3 => SUM(20), A4 =>
SUM(21), ZN => n21);
U14 : AND3_X1 port map( A1 => n28, A2 => n18, A3 => n19, ZN => n27);
U15 : AND4_X1 port map( A1 => n21, A2 => n23, A3 => n22, A4 => n20, ZN =>
n26);
U16 : NAND2_X1 port map( A1 => n26, A2 => n27, ZN => n30);
U17 : XNOR2_X1 port map( A => n30, B => n40, ZN => n38);
U18 : OAI21_X1 port map( B1 => n31, B2 => sel(0), A => n3, ZN => n33);
U19 : CLKBUF_X1 port map( A => n30, Z => n31);
U20 : OAI22_X1 port map( A1 => n37, A2 => n3, B1 => n32, B2 => n33, ZN => S)
;
U22 : NAND2_X1 port map( A1 => n11, A2 => n41, ZN => n32);
U23 : NAND2_X1 port map( A1 => n32, A2 => n36, ZN => n35);
U24 : AND2_X1 port map( A1 => n34, A2 => n35, ZN => n37);
U25 : OR2_X1 port map( A1 => C, A2 => sign, ZN => n41);
U26 : INV_X1 port map( A => n39, ZN => n40);
U27 : OAI21_X1 port map( B1 => sel(0), B2 => sel(1), A => sel(2), ZN => n39)
;
U28 : OAI211_X1 port map( C1 => SUM(31), C2 => V, A => n12, B => sign, ZN =>
n11);
U29 : NAND2_X1 port map( A1 => SUM(31), A2 => V, ZN => n12);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity p4add_N32_logN5 is
port( A, B : in std_logic_vector (31 downto 0); Cin, sign : in std_logic;
S : out std_logic_vector (31 downto 0); Cout : out std_logic);
end p4add_N32_logN5;
architecture SYN_STRUCTURAL of p4add_N32_logN5 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component sum_gen_N32
port( A, B : in std_logic_vector (31 downto 0); Cin : in
std_logic_vector (8 downto 0); S : out std_logic_vector (31 downto
0));
end component;
component carry_tree_N32_logN5
port( A, B : in std_logic_vector (31 downto 0); Cin : in std_logic;
Cout : out std_logic_vector (7 downto 0));
end component;
component xor_gen_N32
port( A : in std_logic_vector (31 downto 0); B : in std_logic; S : out
std_logic_vector (31 downto 0));
end component;
signal new_B_31_port, new_B_30_port, new_B_29_port, new_B_28_port,
new_B_27_port, new_B_26_port, new_B_25_port, new_B_24_port, new_B_23_port
, new_B_22_port, new_B_21_port, new_B_20_port, new_B_18_port,
new_B_16_port, new_B_14_port, new_B_13_port, new_B_12_port, new_B_11_port
, new_B_10_port, new_B_9_port, new_B_8_port, new_B_7_port, new_B_6_port,
new_B_5_port, new_B_4_port, new_B_3_port, new_B_2_port, new_B_1_port,
new_B_0_port, carry_pro_7_port, carry_pro_6_port, carry_pro_5_port,
carry_pro_4_port, carry_pro_3_port, carry_pro_2_port, carry_pro_1_port,
n1, n2, n3, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26 : std_logic;
begin
xor32 : xor_gen_N32 port map( A(31) => B(31), A(30) => B(30), A(29) => B(29)
, A(28) => B(28), A(27) => B(27), A(26) => B(26),
A(25) => B(25), A(24) => B(24), A(23) => B(23),
A(22) => B(22), A(21) => B(21), A(20) => B(20),
A(19) => B(19), A(18) => B(18), A(17) => B(17),
A(16) => B(16), A(15) => B(15), A(14) => B(14),
A(13) => B(13), A(12) => B(12), A(11) => B(11),
A(10) => B(10), A(9) => B(9), A(8) => B(8), A(7) =>
B(7), A(6) => B(6), A(5) => B(5), A(4) => B(4), A(3)
=> B(3), A(2) => B(2), A(1) => B(1), A(0) => B(0), B
=> sign, S(31) => new_B_31_port, S(30) =>
new_B_30_port, S(29) => new_B_29_port, S(28) =>
new_B_28_port, S(27) => new_B_27_port, S(26) =>
new_B_26_port, S(25) => new_B_25_port, S(24) =>
new_B_24_port, S(23) => new_B_23_port, S(22) =>
new_B_22_port, S(21) => new_B_21_port, S(20) =>
new_B_20_port, S(19) => n13, S(18) => new_B_18_port,
S(17) => n9, S(16) => new_B_16_port, S(15) => n3,
S(14) => new_B_14_port, S(13) => new_B_13_port,
S(12) => new_B_12_port, S(11) => new_B_11_port,
S(10) => new_B_10_port, S(9) => new_B_9_port, S(8)
=> new_B_8_port, S(7) => new_B_7_port, S(6) =>
new_B_6_port, S(5) => new_B_5_port, S(4) =>
new_B_4_port, S(3) => new_B_3_port, S(2) =>
new_B_2_port, S(1) => new_B_1_port, S(0) =>
new_B_0_port);
ct : carry_tree_N32_logN5 port map( A(31) => A(31), A(30) => A(30), A(29) =>
A(29), A(28) => A(28), A(27) => A(27), A(26) =>
A(26), A(25) => A(25), A(24) => A(24), A(23) =>
A(23), A(22) => A(22), A(21) => A(21), A(20) =>
A(20), A(19) => A(19), A(18) => A(18), A(17) =>
A(17), A(16) => A(16), A(15) => A(15), A(14) =>
A(14), A(13) => A(13), A(12) => A(12), A(11) =>
A(11), A(10) => A(10), A(9) => A(9), A(8) => A(8),
A(7) => A(7), A(6) => A(6), A(5) => A(5), A(4) =>
A(4), A(3) => A(3), A(2) => A(2), A(1) => A(1), A(0)
=> A(0), B(31) => new_B_31_port, B(30) =>
new_B_30_port, B(29) => new_B_29_port, B(28) =>
new_B_28_port, B(27) => new_B_27_port, B(26) =>
new_B_26_port, B(25) => new_B_25_port, B(24) =>
new_B_24_port, B(23) => new_B_23_port, B(22) =>
new_B_22_port, B(21) => new_B_21_port, B(20) =>
new_B_20_port, B(19) => n13, B(18) => new_B_18_port,
B(17) => n9, B(16) => new_B_16_port, B(15) => n3,
B(14) => new_B_14_port, B(13) => new_B_13_port,
B(12) => new_B_12_port, B(11) => new_B_11_port,
B(10) => new_B_10_port, B(9) => new_B_9_port, B(8)
=> new_B_8_port, B(7) => new_B_7_port, B(6) =>
new_B_6_port, B(5) => new_B_5_port, B(4) =>
new_B_4_port, B(3) => new_B_3_port, B(2) =>
new_B_2_port, B(1) => new_B_1_port, B(0) =>
new_B_0_port, Cin => n20, Cout(7) => Cout, Cout(6)
=> carry_pro_7_port, Cout(5) => carry_pro_6_port,
Cout(4) => carry_pro_5_port, Cout(3) =>
carry_pro_4_port, Cout(2) => carry_pro_3_port,
Cout(1) => carry_pro_2_port, Cout(0) =>
carry_pro_1_port);
add : sum_gen_N32 port map( A(31) => A(31), A(30) => A(30), A(29) => A(29),
A(28) => A(28), A(27) => A(27), A(26) => A(26),
A(25) => A(25), A(24) => A(24), A(23) => A(23),
A(22) => A(22), A(21) => A(21), A(20) => A(20),
A(19) => A(19), A(18) => A(18), A(17) => A(17),
A(16) => A(16), A(15) => A(15), A(14) => A(14),
A(13) => A(13), A(12) => A(12), A(11) => A(11),
A(10) => A(10), A(9) => A(9), A(8) => A(8), A(7) =>
A(7), A(6) => A(6), A(5) => A(5), A(4) => A(4), A(3)
=> A(3), A(2) => A(2), A(1) => A(1), A(0) => A(0),
B(31) => new_B_31_port, B(30) => new_B_30_port,
B(29) => new_B_29_port, B(28) => new_B_28_port,
B(27) => new_B_27_port, B(26) => n1, B(25) => n14,
B(24) => new_B_24_port, B(23) => new_B_23_port,
B(22) => new_B_22_port, B(21) => new_B_21_port,
B(20) => new_B_20_port, B(19) => n13, B(18) => n8,
B(17) => n22, B(16) => new_B_16_port, B(15) => n3,
B(14) => n16, B(13) => n6, B(12) => new_B_12_port,
B(11) => n2, B(10) => n17, B(9) => n15, B(8) => n5,
B(7) => n25, B(6) => new_B_6_port, B(5) => n19, B(4)
=> n23, B(3) => n12, B(2) => n11, B(1) => n24, B(0)
=> n10, Cin(8) => n26, Cin(7) => carry_pro_7_port,
Cin(6) => carry_pro_6_port, Cin(5) =>
carry_pro_5_port, Cin(4) => carry_pro_4_port, Cin(3)
=> carry_pro_3_port, Cin(2) => carry_pro_2_port,
Cin(1) => carry_pro_1_port, Cin(0) => n20, S(31) =>
S(31), S(30) => S(30), S(29) => S(29), S(28) =>
S(28), S(27) => S(27), S(26) => S(26), S(25) =>
S(25), S(24) => S(24), S(23) => S(23), S(22) =>
S(22), S(21) => S(21), S(20) => S(20), S(19) =>
S(19), S(18) => S(18), S(17) => S(17), S(16) =>
S(16), S(15) => S(15), S(14) => S(14), S(13) =>
S(13), S(12) => S(12), S(11) => S(11), S(10) =>
S(10), S(9) => S(9), S(8) => S(8), S(7) => S(7),
S(6) => S(6), S(5) => S(5), S(4) => S(4), S(3) =>
S(3), S(2) => S(2), S(1) => S(1), S(0) => S(0));
U1 : BUF_X1 port map( A => new_B_26_port, Z => n1);
U2 : CLKBUF_X1 port map( A => new_B_11_port, Z => n2);
U3 : INV_X1 port map( A => new_B_1_port, ZN => n7);
U4 : BUF_X1 port map( A => new_B_14_port, Z => n16);
U5 : BUF_X1 port map( A => new_B_4_port, Z => n23);
U6 : BUF_X1 port map( A => sign, Z => n20);
U7 : BUF_X1 port map( A => new_B_8_port, Z => n5);
U8 : BUF_X1 port map( A => new_B_13_port, Z => n6);
U9 : CLKBUF_X1 port map( A => new_B_0_port, Z => n10);
U10 : CLKBUF_X1 port map( A => new_B_18_port, Z => n8);
U11 : BUF_X1 port map( A => new_B_2_port, Z => n11);
U12 : CLKBUF_X1 port map( A => new_B_3_port, Z => n12);
U13 : CLKBUF_X1 port map( A => new_B_25_port, Z => n14);
U14 : CLKBUF_X1 port map( A => new_B_7_port, Z => n25);
U15 : INV_X1 port map( A => n18, ZN => n19);
U16 : INV_X1 port map( A => new_B_5_port, ZN => n18);
U17 : CLKBUF_X1 port map( A => new_B_9_port, Z => n15);
U18 : CLKBUF_X1 port map( A => new_B_10_port, Z => n17);
U19 : INV_X1 port map( A => n21, ZN => n22);
U20 : INV_X1 port map( A => n9, ZN => n21);
U21 : INV_X1 port map( A => n7, ZN => n24);
n26 <= '0';
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity simple_booth_add_ext_N16 is
port( Clock, Reset, sign, enable : in std_logic; valid : out std_logic; A,
B : in std_logic_vector (15 downto 0); A_to_add, B_to_add : out
std_logic_vector (31 downto 0); sign_to_add : out std_logic;
final_out : out std_logic_vector (31 downto 0); ACC_from_add : in
std_logic_vector (31 downto 0));
end simple_booth_add_ext_N16;
architecture SYN_struct of simple_booth_add_ext_N16 is
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OR2_X4
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NOR3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component BUF_X8
port( A : in std_logic; Z : out std_logic);
end component;
component OAI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component OAI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
component OAI211_X1
port( C1, C2, A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component DFFS_X1
port( D, CK, SN : in std_logic; Q, QN : out std_logic);
end component;
component NAND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component ff32_en_SIZE32
port( D : in std_logic_vector (31 downto 0); en, clk, rst : in std_logic
; Q : out std_logic_vector (31 downto 0));
end component;
component mux21_1
port( IN0, IN1 : in std_logic_vector (31 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (31 downto 0));
end component;
component piso_r_2_N32
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (31 downto 0)
; SO : out std_logic_vector (31 downto 0));
end component;
component shift_N9_1
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (8 downto 0);
SO : out std_logic);
end component;
component shift_N9_2
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (8 downto 0);
SO : out std_logic);
end component;
component shift_N9_0
port( Clock, ALOAD : in std_logic; D : in std_logic_vector (8 downto 0);
SO : out std_logic);
end component;
component booth_encoder_1
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_2
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_3
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_4
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_5
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_6
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_7
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_8
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component booth_encoder_0
port( B_in : in std_logic_vector (2 downto 0); A_out : out
std_logic_vector (2 downto 0));
end component;
component DFFR_X1
port( D, CK, RN : in std_logic; Q, QN : out std_logic);
end component;
signal X_Logic0_port, valid_port, A_to_add_31_port, A_to_add_30_port,
A_to_add_29_port, A_to_add_28_port, A_to_add_27_port, A_to_add_26_port,
A_to_add_25_port, A_to_add_24_port, A_to_add_23_port, A_to_add_22_port,
A_to_add_21_port, A_to_add_20_port, A_to_add_19_port, A_to_add_18_port,
A_to_add_17_port, A_to_add_16_port, A_to_add_15_port, A_to_add_14_port,
A_to_add_13_port, A_to_add_12_port, A_to_add_11_port, A_to_add_10_port,
A_to_add_9_port, A_to_add_8_port, A_to_add_7_port, A_to_add_6_port,
A_to_add_5_port, A_to_add_4_port, A_to_add_3_port, A_to_add_2_port,
A_to_add_1_port, A_to_add_0_port, enc_N2_in_2_port, piso_0_in_8_port,
piso_0_in_7_port, piso_0_in_6_port, piso_0_in_5_port, piso_0_in_4_port,
piso_0_in_3_port, piso_0_in_2_port, piso_0_in_1_port, piso_0_in_0_port,
piso_1_in_8_port, piso_1_in_7_port, piso_1_in_6_port, piso_1_in_5_port,
piso_1_in_4_port, piso_1_in_3_port, piso_1_in_2_port, piso_1_in_1_port,
piso_1_in_0_port, piso_2_in_8_port, piso_2_in_7_port, piso_2_in_6_port,
piso_2_in_5_port, piso_2_in_4_port, piso_2_in_3_port, piso_2_in_2_port,
piso_2_in_1_port, piso_2_in_0_port, load, extend_vector_15_port,
A_to_mux_31_port, A_to_mux_30_port, A_to_mux_29_port, A_to_mux_28_port,
A_to_mux_27_port, A_to_mux_26_port, A_to_mux_25_port, A_to_mux_24_port,
A_to_mux_23_port, A_to_mux_22_port, A_to_mux_21_port, A_to_mux_20_port,
A_to_mux_19_port, A_to_mux_18_port, A_to_mux_17_port, A_to_mux_16_port,
A_to_mux_15_port, A_to_mux_14_port, A_to_mux_13_port, A_to_mux_12_port,
A_to_mux_11_port, A_to_mux_10_port, A_to_mux_9_port, A_to_mux_8_port,
A_to_mux_7_port, A_to_mux_6_port, A_to_mux_5_port, A_to_mux_4_port,
A_to_mux_3_port, A_to_mux_2_port, A_to_mux_1_port, A_to_mux_0_port,
input_mux_sel_2_port, input_mux_sel_0, next_accumulate_31_port,
next_accumulate_30_port, next_accumulate_29_port, next_accumulate_28_port
, next_accumulate_27_port, next_accumulate_26_port,
next_accumulate_25_port, next_accumulate_24_port, next_accumulate_23_port
, next_accumulate_22_port, next_accumulate_21_port,
next_accumulate_20_port, next_accumulate_19_port, next_accumulate_18_port
, next_accumulate_17_port, next_accumulate_16_port,
next_accumulate_15_port, next_accumulate_14_port, next_accumulate_13_port
, next_accumulate_12_port, next_accumulate_11_port,
next_accumulate_10_port, next_accumulate_9_port, next_accumulate_8_port,
next_accumulate_7_port, next_accumulate_6_port, next_accumulate_5_port,
next_accumulate_4_port, next_accumulate_3_port, next_accumulate_2_port,
next_accumulate_1_port, next_accumulate_0_port, reg_enable, count_4_port,
count_3_port, count_1_port, count_0_port, N21, N23, N24, n49, n50, n51,
n52, n54, n11, n12, n13, net549699, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n55, n56, n57, n58, n59, n60, n61, n63, n64, n65, n66
, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n79, n81, n82,
sub_213_n3, sub_213_n2, n14, n15, n16, n17, n18, n22, n23_port, net561327
: std_logic;
begin
valid <= valid_port;
A_to_add <= ( A_to_add_31_port, A_to_add_30_port, A_to_add_29_port,
A_to_add_28_port, A_to_add_27_port, A_to_add_26_port, A_to_add_25_port,
A_to_add_24_port, A_to_add_23_port, A_to_add_22_port, A_to_add_21_port,
A_to_add_20_port, A_to_add_19_port, A_to_add_18_port, A_to_add_17_port,
A_to_add_16_port, A_to_add_15_port, A_to_add_14_port, A_to_add_13_port,
A_to_add_12_port, A_to_add_11_port, A_to_add_10_port, A_to_add_9_port,
A_to_add_8_port, A_to_add_7_port, A_to_add_6_port, A_to_add_5_port,
A_to_add_4_port, A_to_add_3_port, A_to_add_2_port, A_to_add_1_port,
A_to_add_0_port );
X_Logic0_port <= '0';
count_reg_1_inst : DFFR_X1 port map( D => n51, CK => Clock, RN => n23_port,
Q => count_1_port, QN => n13);
count_reg_2_inst : DFFR_X1 port map( D => n50, CK => Clock, RN => n23_port,
Q => net561327, QN => n11);
count_reg_4_inst : DFFR_X1 port map( D => n49, CK => Clock, RN => n23_port,
Q => count_4_port, QN => n12);
U85 : MUX2_X1 port map( A => A_to_add_9_port, B => ACC_from_add(9), S =>
input_mux_sel_2_port, Z => final_out(9));
U86 : MUX2_X1 port map( A => A_to_add_8_port, B => ACC_from_add(8), S =>
input_mux_sel_2_port, Z => final_out(8));
U87 : MUX2_X1 port map( A => A_to_add_7_port, B => ACC_from_add(7), S =>
input_mux_sel_2_port, Z => final_out(7));
U88 : MUX2_X1 port map( A => A_to_add_6_port, B => ACC_from_add(6), S =>
input_mux_sel_2_port, Z => final_out(6));
U89 : MUX2_X1 port map( A => A_to_add_5_port, B => ACC_from_add(5), S =>
input_mux_sel_2_port, Z => final_out(5));
U90 : MUX2_X1 port map( A => A_to_add_4_port, B => ACC_from_add(4), S =>
input_mux_sel_2_port, Z => final_out(4));
U91 : MUX2_X1 port map( A => A_to_add_3_port, B => ACC_from_add(3), S =>
input_mux_sel_2_port, Z => final_out(3));
U92 : MUX2_X1 port map( A => A_to_add_31_port, B => ACC_from_add(31), S =>
input_mux_sel_2_port, Z => final_out(31));
U93 : MUX2_X1 port map( A => A_to_add_30_port, B => ACC_from_add(30), S =>
input_mux_sel_2_port, Z => final_out(30));
U94 : MUX2_X1 port map( A => A_to_add_2_port, B => ACC_from_add(2), S =>
input_mux_sel_2_port, Z => final_out(2));
U95 : MUX2_X1 port map( A => A_to_add_29_port, B => ACC_from_add(29), S =>
input_mux_sel_2_port, Z => final_out(29));
U96 : MUX2_X1 port map( A => A_to_add_28_port, B => ACC_from_add(28), S =>
input_mux_sel_2_port, Z => final_out(28));
U97 : MUX2_X1 port map( A => A_to_add_27_port, B => ACC_from_add(27), S =>
input_mux_sel_2_port, Z => final_out(27));
U98 : MUX2_X1 port map( A => A_to_add_26_port, B => ACC_from_add(26), S =>
input_mux_sel_2_port, Z => final_out(26));
U99 : MUX2_X1 port map( A => A_to_add_25_port, B => ACC_from_add(25), S =>
input_mux_sel_2_port, Z => final_out(25));
U100 : MUX2_X1 port map( A => A_to_add_24_port, B => ACC_from_add(24), S =>
input_mux_sel_2_port, Z => final_out(24));
U101 : MUX2_X1 port map( A => A_to_add_23_port, B => ACC_from_add(23), S =>
input_mux_sel_2_port, Z => final_out(23));
U102 : MUX2_X1 port map( A => A_to_add_22_port, B => ACC_from_add(22), S =>
input_mux_sel_2_port, Z => final_out(22));
U103 : MUX2_X1 port map( A => A_to_add_21_port, B => ACC_from_add(21), S =>
input_mux_sel_2_port, Z => final_out(21));
U104 : MUX2_X1 port map( A => A_to_add_20_port, B => ACC_from_add(20), S =>
input_mux_sel_2_port, Z => final_out(20));
U105 : MUX2_X1 port map( A => A_to_add_1_port, B => ACC_from_add(1), S =>
input_mux_sel_2_port, Z => final_out(1));
U106 : MUX2_X1 port map( A => A_to_add_19_port, B => ACC_from_add(19), S =>
input_mux_sel_2_port, Z => final_out(19));
U107 : MUX2_X1 port map( A => A_to_add_18_port, B => ACC_from_add(18), S =>
input_mux_sel_2_port, Z => final_out(18));
U108 : MUX2_X1 port map( A => A_to_add_17_port, B => ACC_from_add(17), S =>
input_mux_sel_2_port, Z => final_out(17));
U109 : MUX2_X1 port map( A => A_to_add_16_port, B => ACC_from_add(16), S =>
input_mux_sel_2_port, Z => final_out(16));
U110 : MUX2_X1 port map( A => A_to_add_15_port, B => ACC_from_add(15), S =>
input_mux_sel_2_port, Z => final_out(15));
U111 : MUX2_X1 port map( A => A_to_add_14_port, B => ACC_from_add(14), S =>
input_mux_sel_2_port, Z => final_out(14));
U112 : MUX2_X1 port map( A => A_to_add_13_port, B => ACC_from_add(13), S =>
input_mux_sel_2_port, Z => final_out(13));
U113 : MUX2_X1 port map( A => A_to_add_12_port, B => ACC_from_add(12), S =>
input_mux_sel_2_port, Z => final_out(12));
U114 : MUX2_X1 port map( A => A_to_add_11_port, B => ACC_from_add(11), S =>
input_mux_sel_2_port, Z => final_out(11));
U115 : MUX2_X1 port map( A => A_to_add_10_port, B => ACC_from_add(10), S =>
input_mux_sel_2_port, Z => final_out(10));
encod_0_0 : booth_encoder_0 port map( B_in(2) => B(1), B_in(1) => B(0),
B_in(0) => X_Logic0_port, A_out(2) =>
piso_2_in_0_port, A_out(1) => piso_1_in_0_port,
A_out(0) => piso_0_in_0_port);
encod_i_1 : booth_encoder_8 port map( B_in(2) => B(3), B_in(1) => B(2),
B_in(0) => B(1), A_out(2) => piso_2_in_1_port,
A_out(1) => piso_1_in_1_port, A_out(0) =>
piso_0_in_1_port);
encod_i_2 : booth_encoder_7 port map( B_in(2) => B(5), B_in(1) => B(4),
B_in(0) => B(3), A_out(2) => piso_2_in_2_port,
A_out(1) => piso_1_in_2_port, A_out(0) =>
piso_0_in_2_port);
encod_i_3 : booth_encoder_6 port map( B_in(2) => B(7), B_in(1) => B(6),
B_in(0) => B(5), A_out(2) => piso_2_in_3_port,
A_out(1) => piso_1_in_3_port, A_out(0) =>
piso_0_in_3_port);
encod_i_4 : booth_encoder_5 port map( B_in(2) => B(9), B_in(1) => B(8),
B_in(0) => B(7), A_out(2) => piso_2_in_4_port,
A_out(1) => piso_1_in_4_port, A_out(0) =>
piso_0_in_4_port);
encod_i_5 : booth_encoder_4 port map( B_in(2) => B(11), B_in(1) => B(10),
B_in(0) => B(9), A_out(2) => piso_2_in_5_port,
A_out(1) => piso_1_in_5_port, A_out(0) =>
piso_0_in_5_port);
encod_i_6 : booth_encoder_3 port map( B_in(2) => B(13), B_in(1) => B(12),
B_in(0) => B(11), A_out(2) => piso_2_in_6_port,
A_out(1) => piso_1_in_6_port, A_out(0) =>
piso_0_in_6_port);
encod_i_7 : booth_encoder_2 port map( B_in(2) => B(15), B_in(1) => B(14),
B_in(0) => B(13), A_out(2) => piso_2_in_7_port,
A_out(1) => piso_1_in_7_port, A_out(0) =>
piso_0_in_7_port);
encod_i_8 : booth_encoder_1 port map( B_in(2) => enc_N2_in_2_port, B_in(1)
=> enc_N2_in_2_port, B_in(0) => B(15), A_out(2) =>
piso_2_in_8_port, A_out(1) => piso_1_in_8_port,
A_out(0) => piso_0_in_8_port);
piso_0 : shift_N9_0 port map( Clock => Clock, ALOAD => n22, D(8) =>
piso_0_in_8_port, D(7) => piso_0_in_7_port, D(6) =>
piso_0_in_6_port, D(5) => piso_0_in_5_port, D(4) =>
piso_0_in_4_port, D(3) => piso_0_in_3_port, D(2) =>
piso_0_in_2_port, D(1) => piso_0_in_1_port, D(0) =>
piso_0_in_0_port, SO => input_mux_sel_0);
piso_1 : shift_N9_2 port map( Clock => Clock, ALOAD => n22, D(8) =>
piso_1_in_8_port, D(7) => piso_1_in_7_port, D(6) =>
piso_1_in_6_port, D(5) => piso_1_in_5_port, D(4) =>
piso_1_in_4_port, D(3) => piso_1_in_3_port, D(2) =>
piso_1_in_2_port, D(1) => piso_1_in_1_port, D(0) =>
piso_1_in_0_port, SO => sign_to_add);
piso_2 : shift_N9_1 port map( Clock => Clock, ALOAD => n22, D(8) =>
piso_2_in_8_port, D(7) => piso_2_in_7_port, D(6) =>
piso_2_in_6_port, D(5) => piso_2_in_5_port, D(4) =>
piso_2_in_4_port, D(3) => piso_2_in_3_port, D(2) =>
piso_2_in_2_port, D(1) => piso_2_in_1_port, D(0) =>
piso_2_in_0_port, SO => input_mux_sel_2_port);
A_reg : piso_r_2_N32 port map( Clock => Clock, ALOAD => n22, D(31) =>
extend_vector_15_port, D(30) =>
extend_vector_15_port, D(29) =>
extend_vector_15_port, D(28) =>
extend_vector_15_port, D(27) =>
extend_vector_15_port, D(26) =>
extend_vector_15_port, D(25) =>
extend_vector_15_port, D(24) =>
extend_vector_15_port, D(23) =>
extend_vector_15_port, D(22) =>
extend_vector_15_port, D(21) =>
extend_vector_15_port, D(20) =>
extend_vector_15_port, D(19) =>
extend_vector_15_port, D(18) =>
extend_vector_15_port, D(17) =>
extend_vector_15_port, D(16) =>
extend_vector_15_port, D(15) => A(15), D(14) =>
A(14), D(13) => A(13), D(12) => A(12), D(11) =>
A(11), D(10) => A(10), D(9) => A(9), D(8) => A(8),
D(7) => A(7), D(6) => A(6), D(5) => A(5), D(4) =>
A(4), D(3) => A(3), D(2) => A(2), D(1) => A(1), D(0)
=> A(0), SO(31) => A_to_mux_31_port, SO(30) =>
A_to_mux_30_port, SO(29) => A_to_mux_29_port, SO(28)
=> A_to_mux_28_port, SO(27) => A_to_mux_27_port,
SO(26) => A_to_mux_26_port, SO(25) =>
A_to_mux_25_port, SO(24) => A_to_mux_24_port, SO(23)
=> A_to_mux_23_port, SO(22) => A_to_mux_22_port,
SO(21) => A_to_mux_21_port, SO(20) =>
A_to_mux_20_port, SO(19) => A_to_mux_19_port, SO(18)
=> A_to_mux_18_port, SO(17) => A_to_mux_17_port,
SO(16) => A_to_mux_16_port, SO(15) =>
A_to_mux_15_port, SO(14) => A_to_mux_14_port, SO(13)
=> A_to_mux_13_port, SO(12) => A_to_mux_12_port,
SO(11) => A_to_mux_11_port, SO(10) =>
A_to_mux_10_port, SO(9) => A_to_mux_9_port, SO(8) =>
A_to_mux_8_port, SO(7) => A_to_mux_7_port, SO(6) =>
A_to_mux_6_port, SO(5) => A_to_mux_5_port, SO(4) =>
A_to_mux_4_port, SO(3) => A_to_mux_3_port, SO(2) =>
A_to_mux_2_port, SO(1) => A_to_mux_1_port, SO(0) =>
A_to_mux_0_port);
INPUTMUX : mux21_1 port map( IN0(31) => A_to_mux_31_port, IN0(30) =>
A_to_mux_30_port, IN0(29) => A_to_mux_29_port,
IN0(28) => A_to_mux_28_port, IN0(27) =>
A_to_mux_27_port, IN0(26) => A_to_mux_26_port,
IN0(25) => A_to_mux_25_port, IN0(24) =>
A_to_mux_24_port, IN0(23) => A_to_mux_23_port,
IN0(22) => A_to_mux_22_port, IN0(21) =>
A_to_mux_21_port, IN0(20) => A_to_mux_20_port,
IN0(19) => A_to_mux_19_port, IN0(18) =>
A_to_mux_18_port, IN0(17) => A_to_mux_17_port,
IN0(16) => A_to_mux_16_port, IN0(15) =>
A_to_mux_15_port, IN0(14) => A_to_mux_14_port,
IN0(13) => A_to_mux_13_port, IN0(12) =>
A_to_mux_12_port, IN0(11) => A_to_mux_11_port,
IN0(10) => A_to_mux_10_port, IN0(9) =>
A_to_mux_9_port, IN0(8) => A_to_mux_8_port, IN0(7)
=> A_to_mux_7_port, IN0(6) => A_to_mux_6_port,
IN0(5) => A_to_mux_5_port, IN0(4) => A_to_mux_4_port
, IN0(3) => A_to_mux_3_port, IN0(2) =>
A_to_mux_2_port, IN0(1) => A_to_mux_1_port, IN0(0)
=> A_to_mux_0_port, IN1(31) => A_to_mux_30_port,
IN1(30) => A_to_mux_29_port, IN1(29) =>
A_to_mux_28_port, IN1(28) => A_to_mux_27_port,
IN1(27) => A_to_mux_26_port, IN1(26) =>
A_to_mux_25_port, IN1(25) => A_to_mux_24_port,
IN1(24) => A_to_mux_23_port, IN1(23) =>
A_to_mux_22_port, IN1(22) => A_to_mux_21_port,
IN1(21) => A_to_mux_20_port, IN1(20) =>
A_to_mux_19_port, IN1(19) => A_to_mux_18_port,
IN1(18) => A_to_mux_17_port, IN1(17) =>
A_to_mux_16_port, IN1(16) => A_to_mux_15_port,
IN1(15) => A_to_mux_14_port, IN1(14) =>
A_to_mux_13_port, IN1(13) => A_to_mux_12_port,
IN1(12) => A_to_mux_11_port, IN1(11) =>
A_to_mux_10_port, IN1(10) => A_to_mux_9_port, IN1(9)
=> A_to_mux_8_port, IN1(8) => A_to_mux_7_port,
IN1(7) => A_to_mux_6_port, IN1(6) => A_to_mux_5_port
, IN1(5) => A_to_mux_4_port, IN1(4) =>
A_to_mux_3_port, IN1(3) => A_to_mux_2_port, IN1(2)
=> A_to_mux_1_port, IN1(1) => A_to_mux_0_port,
IN1(0) => X_Logic0_port, CTRL => input_mux_sel_0,
OUT1(31) => B_to_add(31), OUT1(30) => B_to_add(30),
OUT1(29) => B_to_add(29), OUT1(28) => B_to_add(28),
OUT1(27) => B_to_add(27), OUT1(26) => B_to_add(26),
OUT1(25) => B_to_add(25), OUT1(24) => B_to_add(24),
OUT1(23) => B_to_add(23), OUT1(22) => B_to_add(22),
OUT1(21) => B_to_add(21), OUT1(20) => B_to_add(20),
OUT1(19) => B_to_add(19), OUT1(18) => B_to_add(18),
OUT1(17) => B_to_add(17), OUT1(16) => B_to_add(16),
OUT1(15) => B_to_add(15), OUT1(14) => B_to_add(14),
OUT1(13) => B_to_add(13), OUT1(12) => B_to_add(12),
OUT1(11) => B_to_add(11), OUT1(10) => B_to_add(10),
OUT1(9) => B_to_add(9), OUT1(8) => B_to_add(8),
OUT1(7) => B_to_add(7), OUT1(6) => B_to_add(6),
OUT1(5) => B_to_add(5), OUT1(4) => B_to_add(4),
OUT1(3) => B_to_add(3), OUT1(2) => B_to_add(2),
OUT1(1) => B_to_add(1), OUT1(0) => B_to_add(0));
ACCUMULATOR : ff32_en_SIZE32 port map( D(31) => next_accumulate_31_port,
D(30) => next_accumulate_30_port, D(29) =>
next_accumulate_29_port, D(28) =>
next_accumulate_28_port, D(27) =>
next_accumulate_27_port, D(26) =>
next_accumulate_26_port, D(25) =>
next_accumulate_25_port, D(24) =>
next_accumulate_24_port, D(23) =>
next_accumulate_23_port, D(22) =>
next_accumulate_22_port, D(21) =>
next_accumulate_21_port, D(20) =>
next_accumulate_20_port, D(19) =>
next_accumulate_19_port, D(18) =>
next_accumulate_18_port, D(17) =>
next_accumulate_17_port, D(16) =>
next_accumulate_16_port, D(15) =>
next_accumulate_15_port, D(14) =>
next_accumulate_14_port, D(13) =>
next_accumulate_13_port, D(12) =>
next_accumulate_12_port, D(11) =>
next_accumulate_11_port, D(10) =>
next_accumulate_10_port, D(9) =>
next_accumulate_9_port, D(8) =>
next_accumulate_8_port, D(7) =>
next_accumulate_7_port, D(6) =>
next_accumulate_6_port, D(5) =>
next_accumulate_5_port, D(4) =>
next_accumulate_4_port, D(3) =>
next_accumulate_3_port, D(2) =>
next_accumulate_2_port, D(1) =>
next_accumulate_1_port, D(0) =>
next_accumulate_0_port, en => reg_enable, clk =>
Clock, rst => Reset, Q(31) => A_to_add_31_port,
Q(30) => A_to_add_30_port, Q(29) => A_to_add_29_port
, Q(28) => A_to_add_28_port, Q(27) =>
A_to_add_27_port, Q(26) => A_to_add_26_port, Q(25)
=> A_to_add_25_port, Q(24) => A_to_add_24_port,
Q(23) => A_to_add_23_port, Q(22) => A_to_add_22_port
, Q(21) => A_to_add_21_port, Q(20) =>
A_to_add_20_port, Q(19) => A_to_add_19_port, Q(18)
=> A_to_add_18_port, Q(17) => A_to_add_17_port,
Q(16) => A_to_add_16_port, Q(15) => A_to_add_15_port
, Q(14) => A_to_add_14_port, Q(13) =>
A_to_add_13_port, Q(12) => A_to_add_12_port, Q(11)
=> A_to_add_11_port, Q(10) => A_to_add_10_port, Q(9)
=> A_to_add_9_port, Q(8) => A_to_add_8_port, Q(7) =>
A_to_add_7_port, Q(6) => A_to_add_6_port, Q(5) =>
A_to_add_5_port, Q(4) => A_to_add_4_port, Q(3) =>
A_to_add_3_port, Q(2) => A_to_add_2_port, Q(1) =>
A_to_add_1_port, Q(0) => A_to_add_0_port);
U34 : NOR2_X1 port map( A1 => n22, A2 => n59, ZN => next_accumulate_24_port)
;
U36 : NOR2_X1 port map( A1 => n22, A2 => n60, ZN => next_accumulate_23_port)
;
U58 : NOR2_X1 port map( A1 => n22, A2 => n71, ZN => next_accumulate_13_port)
;
U54 : NOR2_X1 port map( A1 => n22, A2 => n69, ZN => next_accumulate_15_port)
;
U48 : NOR2_X1 port map( A1 => n22, A2 => n66, ZN => next_accumulate_18_port)
;
U46 : NOR2_X1 port map( A1 => n22, A2 => n65, ZN => next_accumulate_19_port)
;
U60 : NOR2_X1 port map( A1 => n22, A2 => n72, ZN => next_accumulate_12_port)
;
U62 : NOR2_X1 port map( A1 => n22, A2 => n73, ZN => next_accumulate_11_port)
;
U6 : NOR2_X1 port map( A1 => n22, A2 => n39, ZN => next_accumulate_8_port);
U4 : NOR2_X1 port map( A1 => n22, A2 => n38, ZN => next_accumulate_9_port);
U64 : NOR2_X1 port map( A1 => n22, A2 => n74, ZN => next_accumulate_10_port)
;
U8 : NOR2_X1 port map( A1 => n22, A2 => n40, ZN => next_accumulate_7_port);
U10 : NOR2_X1 port map( A1 => n22, A2 => n41, ZN => next_accumulate_6_port);
U16 : NOR2_X1 port map( A1 => n22, A2 => n44, ZN => next_accumulate_3_port);
U12 : NOR2_X1 port map( A1 => n22, A2 => n42, ZN => next_accumulate_5_port);
U14 : NOR2_X1 port map( A1 => n22, A2 => n43, ZN => next_accumulate_4_port);
U22 : NOR2_X1 port map( A1 => n22, A2 => n47, ZN => next_accumulate_2_port);
U44 : NOR2_X1 port map( A1 => n22, A2 => n64, ZN => next_accumulate_1_port);
U66 : NOR2_X1 port map( A1 => n22, A2 => n75, ZN => next_accumulate_0_port);
U78 : AND3_X1 port map( A1 => n81, A2 => N21, A3 => net549699, ZN =>
valid_port);
U72 : AOI21_X1 port map( B1 => enable, B2 => N24, A => valid_port, ZN => n77
);
U71 : OAI21_X1 port map( B1 => net549699, B2 => enable, A => n77, ZN => n52)
;
U76 : NAND2_X1 port map( A1 => enable, A2 => N23, ZN => n79);
U75 : OAI22_X1 port map( A1 => n79, A2 => valid_port, B1 => enable, B2 =>
n11, ZN => n50);
U69 : AOI21_X1 port map( B1 => enable, B2 => N21, A => valid_port, ZN => n76
);
U68 : OAI21_X1 port map( B1 => N21, B2 => enable, A => n76, ZN => n54);
U59 : INV_X1 port map( A => ACC_from_add(13), ZN => n71);
U55 : INV_X1 port map( A => ACC_from_add(15), ZN => n69);
U63 : INV_X1 port map( A => ACC_from_add(11), ZN => n73);
U7 : INV_X1 port map( A => ACC_from_add(8), ZN => n39);
U5 : INV_X1 port map( A => ACC_from_add(9), ZN => n38);
U65 : INV_X1 port map( A => ACC_from_add(10), ZN => n74);
U9 : INV_X1 port map( A => ACC_from_add(7), ZN => n40);
U11 : INV_X1 port map( A => ACC_from_add(6), ZN => n41);
U17 : INV_X1 port map( A => ACC_from_add(3), ZN => n44);
U13 : INV_X1 port map( A => ACC_from_add(5), ZN => n42);
U15 : INV_X1 port map( A => ACC_from_add(4), ZN => n43);
U23 : INV_X1 port map( A => ACC_from_add(2), ZN => n47);
U45 : INV_X1 port map( A => ACC_from_add(1), ZN => n64);
U67 : INV_X1 port map( A => ACC_from_add(0), ZN => n75);
U79 : INV_X1 port map( A => n82, ZN => n81);
sub_213_U4 : OAI21_X1 port map( B1 => sub_213_n3, B2 => n11, A => sub_213_n2
, ZN => N23);
sub_213_U3 : XNOR2_X1 port map( A => count_3_port, B => sub_213_n2, ZN =>
N24);
sub_213_U5 : NAND2_X1 port map( A1 => sub_213_n3, A2 => n11, ZN =>
sub_213_n2);
sub_213_U9 : NOR2_X1 port map( A1 => count_1_port, A2 => count_0_port, ZN =>
sub_213_n3);
U84 : NAND3_X1 port map( A1 => n13, A2 => n11, A3 => n12, ZN => n82);
count_reg_0_inst : DFFS_X1 port map( D => n54, CK => Clock, SN => n23_port,
Q => count_0_port, QN => N21);
count_reg_3_inst : DFFS_X1 port map( D => n52, CK => Clock, SN => n23_port,
Q => count_3_port, QN => net549699);
U3 : NOR2_X1 port map( A1 => sub_213_n2, A2 => count_3_port, ZN => n14);
U18 : NAND2_X1 port map( A1 => n14, A2 => count_4_port, ZN => n15);
U19 : OAI211_X1 port map( C1 => n14, C2 => count_4_port, A => n15, B =>
enable, ZN => n16);
U20 : OAI22_X1 port map( A1 => enable, A2 => n12, B1 => valid_port, B2 =>
n16, ZN => n49);
U21 : MUX2_X1 port map( A => A_to_add_0_port, B => ACC_from_add(0), S =>
input_mux_sel_2_port, Z => final_out(0));
U24 : INV_X1 port map( A => ACC_from_add(21), ZN => n17);
U25 : NOR2_X1 port map( A1 => n22, A2 => n17, ZN => next_accumulate_21_port)
;
U26 : OAI221_X1 port map( B1 => sub_213_n3, B2 => count_1_port, C1 =>
sub_213_n3, C2 => count_0_port, A => enable, ZN =>
n18);
U27 : OAI22_X1 port map( A1 => enable, A2 => n13, B1 => valid_port, B2 =>
n18, ZN => n51);
U28 : BUF_X8 port map( A => load, Z => n22);
U29 : NOR3_X1 port map( A1 => N21, A2 => net549699, A3 => n82, ZN => load);
U30 : INV_X1 port map( A => Reset, ZN => n23_port);
U31 : AND2_X1 port map( A1 => sign, A2 => A(15), ZN => extend_vector_15_port
);
U32 : AND2_X1 port map( A1 => sign, A2 => B(15), ZN => enc_N2_in_2_port);
U33 : INV_X1 port map( A => ACC_from_add(12), ZN => n72);
U35 : NOR2_X1 port map( A1 => n22, A2 => n46, ZN => next_accumulate_30_port)
;
U37 : INV_X1 port map( A => ACC_from_add(30), ZN => n46);
U38 : INV_X1 port map( A => ACC_from_add(14), ZN => n70);
U39 : INV_X1 port map( A => ACC_from_add(19), ZN => n65);
U40 : INV_X1 port map( A => ACC_from_add(16), ZN => n68);
U41 : INV_X1 port map( A => ACC_from_add(25), ZN => n58);
U42 : INV_X1 port map( A => ACC_from_add(18), ZN => n66);
U43 : INV_X1 port map( A => ACC_from_add(17), ZN => n67);
U47 : INV_X1 port map( A => ACC_from_add(26), ZN => n57);
U49 : INV_X1 port map( A => ACC_from_add(23), ZN => n60);
U50 : INV_X1 port map( A => ACC_from_add(27), ZN => n56);
U51 : INV_X1 port map( A => ACC_from_add(24), ZN => n59);
U52 : INV_X1 port map( A => ACC_from_add(31), ZN => n45);
U53 : INV_X1 port map( A => ACC_from_add(20), ZN => n63);
U56 : INV_X1 port map( A => ACC_from_add(29), ZN => n48);
U57 : INV_X1 port map( A => ACC_from_add(22), ZN => n61);
U61 : INV_X1 port map( A => ACC_from_add(28), ZN => n55);
U70 : OR2_X4 port map( A1 => n22, A2 => input_mux_sel_2_port, ZN =>
reg_enable);
U73 : NOR2_X1 port map( A1 => n22, A2 => n70, ZN => next_accumulate_14_port)
;
U74 : NOR2_X1 port map( A1 => n22, A2 => n68, ZN => next_accumulate_16_port)
;
U77 : NOR2_X1 port map( A1 => n22, A2 => n58, ZN => next_accumulate_25_port)
;
U80 : NOR2_X1 port map( A1 => n22, A2 => n67, ZN => next_accumulate_17_port)
;
U81 : NOR2_X1 port map( A1 => n22, A2 => n57, ZN => next_accumulate_26_port)
;
U82 : NOR2_X1 port map( A1 => n22, A2 => n56, ZN => next_accumulate_27_port)
;
U83 : NOR2_X1 port map( A1 => n22, A2 => n61, ZN => next_accumulate_22_port)
;
U116 : NOR2_X1 port map( A1 => n22, A2 => n48, ZN => next_accumulate_29_port
);
U117 : NOR2_X1 port map( A1 => n22, A2 => n55, ZN => next_accumulate_28_port
);
U118 : NOR2_X1 port map( A1 => n22, A2 => n63, ZN => next_accumulate_20_port
);
U119 : NOR2_X1 port map( A1 => n22, A2 => n45, ZN => next_accumulate_31_port
);
end SYN_struct;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux41_MUX_SIZE32_0 is
port( IN0, IN1, IN2, IN3 : in std_logic_vector (31 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (31 downto
0));
end mux41_MUX_SIZE32_0;
architecture SYN_bhe of mux41_MUX_SIZE32_0 is
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X2
port( A : in std_logic; Z : out std_logic);
end component;
component AOI222_X1
port( A1, A2, B1, B2, C1, C2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62
, n63, n64, n65, n66, n67, n69, n68, n70, n71, n72, n73, n74, n75, n76,
n77 : std_logic;
begin
U42 : AOI222_X1 port map( A1 => n77, A2 => IN1(1), B1 => n76, B2 => IN0(1),
C1 => n73, C2 => IN2(1), ZN => n57);
U46 : AOI222_X1 port map( A1 => n77, A2 => IN1(18), B1 => n76, B2 => IN0(18)
, C1 => n73, C2 => IN2(18), ZN => n59);
U48 : AOI222_X1 port map( A1 => n77, A2 => IN1(17), B1 => n76, B2 => IN0(17)
, C1 => n73, C2 => IN2(17), ZN => n60);
U50 : AOI222_X1 port map( A1 => n77, A2 => IN1(16), B1 => n76, B2 => IN0(16)
, C1 => n73, C2 => IN2(16), ZN => n61);
U44 : AOI222_X1 port map( A1 => n77, A2 => IN1(19), B1 => n76, B2 => IN0(19)
, C1 => n73, C2 => IN2(19), ZN => n58);
U20 : AOI222_X1 port map( A1 => n68, A2 => IN1(2), B1 => n70, B2 => IN0(2),
C1 => n74, C2 => IN2(2), ZN => n46);
U14 : AOI222_X1 port map( A1 => n68, A2 => IN1(3), B1 => n70, B2 => IN0(3),
C1 => n75, C2 => IN2(3), ZN => n43);
U6 : AOI222_X1 port map( A1 => n68, A2 => IN1(7), B1 => n70, B2 => IN0(7),
C1 => n75, C2 => IN2(7), ZN => n39);
U10 : AOI222_X1 port map( A1 => n68, A2 => IN1(5), B1 => n70, B2 => IN0(5),
C1 => n75, C2 => IN2(5), ZN => n41);
U12 : AOI222_X1 port map( A1 => n68, A2 => IN1(4), B1 => n70, B2 => IN0(4),
C1 => n75, C2 => IN2(4), ZN => n42);
U58 : AOI222_X1 port map( A1 => n77, A2 => IN1(12), B1 => n76, B2 => IN0(12)
, C1 => n73, C2 => IN2(12), ZN => n65);
U56 : AOI222_X1 port map( A1 => n77, A2 => IN1(13), B1 => n76, B2 => IN0(13)
, C1 => n73, C2 => IN2(13), ZN => n64);
U52 : AOI222_X1 port map( A1 => n77, A2 => IN1(15), B1 => n76, B2 => IN0(15)
, C1 => n73, C2 => IN2(15), ZN => n62);
U54 : AOI222_X1 port map( A1 => n77, A2 => IN1(14), B1 => n76, B2 => IN0(14)
, C1 => n73, C2 => IN2(14), ZN => n63);
U62 : AOI222_X1 port map( A1 => n77, A2 => IN1(10), B1 => n76, B2 => IN0(10)
, C1 => n73, C2 => IN2(10), ZN => n67);
U60 : AOI222_X1 port map( A1 => n77, A2 => IN1(11), B1 => n76, B2 => IN0(11)
, C1 => n73, C2 => IN2(11), ZN => n66);
U4 : AOI222_X1 port map( A1 => n68, A2 => IN1(8), B1 => n70, B2 => IN0(8),
C1 => n75, C2 => IN2(8), ZN => n38);
U2 : AOI222_X1 port map( A1 => n68, A2 => IN1(9), B1 => n70, B2 => IN0(9),
C1 => n75, C2 => IN2(9), ZN => n34);
U36 : AOI222_X1 port map( A1 => n68, A2 => IN1(22), B1 => n70, B2 => IN0(22)
, C1 => n74, C2 => IN2(22), ZN => n54);
U38 : AOI222_X1 port map( A1 => n68, A2 => IN1(21), B1 => n70, B2 => IN0(21)
, C1 => n74, C2 => IN2(21), ZN => n55);
U40 : AOI222_X1 port map( A1 => n68, A2 => IN1(20), B1 => n70, B2 => IN0(20)
, C1 => n74, C2 => IN2(20), ZN => n56);
U34 : AOI222_X1 port map( A1 => n68, A2 => IN1(23), B1 => n70, B2 => IN0(23)
, C1 => n74, C2 => IN2(23), ZN => n53);
U18 : AOI222_X1 port map( A1 => n68, A2 => IN1(30), B1 => n70, B2 => IN0(30)
, C1 => n74, C2 => IN2(30), ZN => n45);
U22 : AOI222_X1 port map( A1 => n68, A2 => IN1(29), B1 => n70, B2 => IN0(29)
, C1 => n74, C2 => IN2(29), ZN => n47);
U24 : AOI222_X1 port map( A1 => n68, A2 => IN1(28), B1 => n70, B2 => IN0(28)
, C1 => n74, C2 => IN2(28), ZN => n48);
U16 : AOI222_X1 port map( A1 => n68, A2 => IN1(31), B1 => n70, B2 => IN0(31)
, C1 => n75, C2 => IN2(31), ZN => n44);
U26 : AOI222_X1 port map( A1 => n68, A2 => IN1(27), B1 => n70, B2 => IN0(27)
, C1 => n74, C2 => IN2(27), ZN => n49);
U28 : AOI222_X1 port map( A1 => n68, A2 => IN1(26), B1 => n70, B2 => IN0(26)
, C1 => n74, C2 => IN2(26), ZN => n50);
U30 : AOI222_X1 port map( A1 => n68, A2 => IN1(25), B1 => n70, B2 => IN0(25)
, C1 => n74, C2 => IN2(25), ZN => n51);
U32 : AOI222_X1 port map( A1 => n68, A2 => IN1(24), B1 => n70, B2 => IN0(24)
, C1 => n74, C2 => IN2(24), ZN => n52);
U66 : NOR2_X1 port map( A1 => CTRL(1), A2 => CTRL(0), ZN => n36);
U68 : INV_X1 port map( A => CTRL(1), ZN => n69);
U67 : AND2_X1 port map( A1 => n69, A2 => CTRL(0), ZN => n35);
U41 : INV_X1 port map( A => n57, ZN => OUT1(1));
U45 : INV_X1 port map( A => n59, ZN => OUT1(18));
U47 : INV_X1 port map( A => n60, ZN => OUT1(17));
U49 : INV_X1 port map( A => n61, ZN => OUT1(16));
U43 : INV_X1 port map( A => n58, ZN => OUT1(19));
U19 : INV_X1 port map( A => n46, ZN => OUT1(2));
U13 : INV_X1 port map( A => n43, ZN => OUT1(3));
U7 : INV_X1 port map( A => n40, ZN => OUT1(6));
U5 : INV_X1 port map( A => n39, ZN => OUT1(7));
U9 : INV_X1 port map( A => n41, ZN => OUT1(5));
U11 : INV_X1 port map( A => n42, ZN => OUT1(4));
U57 : INV_X1 port map( A => n65, ZN => OUT1(12));
U55 : INV_X1 port map( A => n64, ZN => OUT1(13));
U51 : INV_X1 port map( A => n62, ZN => OUT1(15));
U53 : INV_X1 port map( A => n63, ZN => OUT1(14));
U61 : INV_X1 port map( A => n67, ZN => OUT1(10));
U59 : INV_X1 port map( A => n66, ZN => OUT1(11));
U3 : INV_X1 port map( A => n38, ZN => OUT1(8));
U1 : INV_X1 port map( A => n34, ZN => OUT1(9));
U35 : INV_X1 port map( A => n54, ZN => OUT1(22));
U37 : INV_X1 port map( A => n55, ZN => OUT1(21));
U39 : INV_X1 port map( A => n56, ZN => OUT1(20));
U33 : INV_X1 port map( A => n53, ZN => OUT1(23));
U17 : INV_X1 port map( A => n45, ZN => OUT1(30));
U21 : INV_X1 port map( A => n47, ZN => OUT1(29));
U23 : INV_X1 port map( A => n48, ZN => OUT1(28));
U15 : INV_X1 port map( A => n44, ZN => OUT1(31));
U25 : INV_X1 port map( A => n49, ZN => OUT1(27));
U27 : INV_X1 port map( A => n50, ZN => OUT1(26));
U29 : INV_X1 port map( A => n51, ZN => OUT1(25));
U31 : INV_X1 port map( A => n52, ZN => OUT1(24));
U8 : BUF_X2 port map( A => n35, Z => n68);
U63 : BUF_X1 port map( A => n36, Z => n76);
U64 : BUF_X2 port map( A => n36, Z => n70);
U65 : BUF_X2 port map( A => n35, Z => n77);
U69 : AOI222_X1 port map( A1 => n68, A2 => IN1(6), B1 => n70, B2 => IN0(6),
C1 => n75, C2 => IN2(6), ZN => n40);
U70 : BUF_X2 port map( A => n37, Z => n75);
U71 : BUF_X2 port map( A => n37, Z => n74);
U72 : BUF_X2 port map( A => n37, Z => n73);
U73 : NOR2_X1 port map( A1 => CTRL(0), A2 => n69, ZN => n37);
U74 : NAND2_X1 port map( A1 => n73, A2 => IN2(0), ZN => n71);
U75 : NAND2_X1 port map( A1 => n71, A2 => n72, ZN => OUT1(0));
U76 : AOI22_X1 port map( A1 => n77, A2 => IN1(0), B1 => n76, B2 => IN0(0),
ZN => n72);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux41_MUX_SIZE5 is
port( IN0, IN1, IN2, IN3 : in std_logic_vector (4 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (4 downto
0));
end mux41_MUX_SIZE5;
architecture SYN_bhe of mux41_MUX_SIZE5 is
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
signal n2, n3, n4, n5, n6, n8, n9, n10, n11, n12, n13, n14, n15, n16 :
std_logic;
begin
U1 : NAND2_X1 port map( A1 => n2, A2 => n3, ZN => OUT1(4));
U4 : NAND2_X1 port map( A1 => n8, A2 => n9, ZN => OUT1(3));
U7 : NAND2_X1 port map( A1 => n10, A2 => n11, ZN => OUT1(2));
U10 : NAND2_X1 port map( A1 => n12, A2 => n13, ZN => OUT1(1));
U17 : AOI22_X1 port map( A1 => n5, A2 => IN2(0), B1 => n6, B2 => IN1(0), ZN
=> n14);
U13 : NAND2_X1 port map( A1 => n14, A2 => n15, ZN => OUT1(0));
U19 : NOR2_X1 port map( A1 => CTRL(0), A2 => n16, ZN => n5);
U20 : INV_X1 port map( A => CTRL(1), ZN => n16);
U18 : AND2_X1 port map( A1 => n16, A2 => CTRL(0), ZN => n6);
U16 : AND2_X1 port map( A1 => CTRL(0), A2 => CTRL(1), ZN => n4);
U2 : INV_X1 port map( A => n4, ZN => n15);
U3 : AOI21_X1 port map( B1 => n5, B2 => IN2(1), A => n4, ZN => n13);
U5 : NAND2_X1 port map( A1 => n6, A2 => IN1(1), ZN => n12);
U6 : AOI21_X1 port map( B1 => n5, B2 => IN2(2), A => n4, ZN => n11);
U8 : NAND2_X1 port map( A1 => n6, A2 => IN1(2), ZN => n10);
U9 : AOI21_X1 port map( B1 => n5, B2 => IN2(3), A => n4, ZN => n9);
U11 : NAND2_X1 port map( A1 => n6, A2 => IN1(3), ZN => n8);
U12 : AOI21_X1 port map( B1 => n5, B2 => IN2(4), A => n4, ZN => n3);
U14 : NAND2_X1 port map( A1 => n6, A2 => IN1(4), ZN => n2);
end SYN_bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity real_alu_DATA_SIZE32 is
port( IN1, IN2 : in std_logic_vector (31 downto 0); ALUW_i : in
std_logic_vector (12 downto 0); DOUT : out std_logic_vector (31
downto 0); stall_o : out std_logic; Clock, Reset : in std_logic);
end real_alu_DATA_SIZE32;
architecture SYN_Bhe of real_alu_DATA_SIZE32 is
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI222_X1
port( A1, A2, B1, B2, C1, C2 : in std_logic; ZN : out std_logic);
end component;
component NOR3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component NAND2_X4
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X2
port( A : in std_logic; Z : out std_logic);
end component;
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
component INV_X2
port( A : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component logic_unit_SIZE32
port( IN1, IN2 : in std_logic_vector (31 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (31
downto 0));
end component;
component shifter
port( A : in std_logic_vector (31 downto 0); B : in std_logic_vector (4
downto 0); LOGIC_ARITH, LEFT_RIGHT : in std_logic; OUTPUT : out
std_logic_vector (31 downto 0));
end component;
component comparator_M32
port( C, V : in std_logic; SUM : in std_logic_vector (31 downto 0); sel
: in std_logic_vector (2 downto 0); sign : in std_logic; S : out
std_logic);
end component;
component p4add_N32_logN5
port( A, B : in std_logic_vector (31 downto 0); Cin, sign : in std_logic
; S : out std_logic_vector (31 downto 0); Cout : out std_logic);
end component;
component simple_booth_add_ext_N16
port( Clock, Reset, sign, enable : in std_logic; valid : out std_logic;
A, B : in std_logic_vector (15 downto 0); A_to_add, B_to_add : out
std_logic_vector (31 downto 0); sign_to_add : out std_logic;
final_out : out std_logic_vector (31 downto 0); ACC_from_add : in
std_logic_vector (31 downto 0));
end component;
component NAND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component OAI33_X1
port( A1, A2, A3, B1, B2, B3 : in std_logic; ZN : out std_logic);
end component;
signal X_Logic0_port, mux_A_31_port, mux_A_30_port, mux_A_29_port,
mux_A_28_port, mux_A_27_port, mux_A_26_port, mux_A_25_port, mux_A_24_port
, mux_A_23_port, mux_A_22_port, mux_A_21_port, mux_A_20_port,
mux_A_19_port, mux_A_18_port, mux_A_17_port, mux_A_16_port, mux_A_15_port
, mux_A_14_port, mux_A_13_port, mux_A_12_port, mux_A_11_port,
mux_A_10_port, mux_A_9_port, mux_A_8_port, mux_A_7_port, mux_A_6_port,
mux_A_5_port, mux_A_4_port, mux_A_3_port, mux_A_2_port, mux_A_1_port,
mux_A_0_port, A_booth_to_add_31_port, A_booth_to_add_30_port,
A_booth_to_add_29_port, A_booth_to_add_28_port, A_booth_to_add_27_port,
A_booth_to_add_26_port, A_booth_to_add_25_port, A_booth_to_add_24_port,
A_booth_to_add_23_port, A_booth_to_add_22_port, A_booth_to_add_21_port,
A_booth_to_add_20_port, A_booth_to_add_19_port, A_booth_to_add_18_port,
A_booth_to_add_17_port, A_booth_to_add_16_port, A_booth_to_add_15_port,
A_booth_to_add_14_port, A_booth_to_add_13_port, A_booth_to_add_12_port,
A_booth_to_add_11_port, A_booth_to_add_10_port, A_booth_to_add_9_port,
A_booth_to_add_8_port, A_booth_to_add_7_port, A_booth_to_add_6_port,
A_booth_to_add_5_port, A_booth_to_add_4_port, A_booth_to_add_3_port,
A_booth_to_add_2_port, A_booth_to_add_1_port, A_booth_to_add_0_port,
mux_B_31_port, mux_B_30_port, mux_B_29_port, mux_B_28_port, mux_B_27_port
, mux_B_26_port, mux_B_25_port, mux_B_24_port, mux_B_23_port,
mux_B_22_port, mux_B_21_port, mux_B_20_port, mux_B_19_port, mux_B_18_port
, mux_B_17_port, mux_B_16_port, mux_B_15_port, mux_B_14_port,
mux_B_13_port, mux_B_12_port, mux_B_11_port, mux_B_10_port, mux_B_9_port,
mux_B_8_port, mux_B_7_port, mux_B_6_port, mux_B_5_port, mux_B_4_port,
mux_B_3_port, mux_B_2_port, mux_B_1_port, mux_B_0_port,
B_booth_to_add_31_port, B_booth_to_add_30_port, B_booth_to_add_29_port,
B_booth_to_add_28_port, B_booth_to_add_27_port, B_booth_to_add_26_port,
B_booth_to_add_25_port, B_booth_to_add_24_port, B_booth_to_add_23_port,
B_booth_to_add_22_port, B_booth_to_add_21_port, B_booth_to_add_20_port,
B_booth_to_add_19_port, B_booth_to_add_18_port, B_booth_to_add_17_port,
B_booth_to_add_16_port, B_booth_to_add_15_port, B_booth_to_add_14_port,
B_booth_to_add_13_port, B_booth_to_add_12_port, B_booth_to_add_11_port,
B_booth_to_add_10_port, B_booth_to_add_9_port, B_booth_to_add_8_port,
B_booth_to_add_7_port, B_booth_to_add_6_port, B_booth_to_add_5_port,
B_booth_to_add_4_port, B_booth_to_add_3_port, B_booth_to_add_2_port,
B_booth_to_add_1_port, B_booth_to_add_0_port, mux_sign, sign_booth_to_add
, valid_from_booth, mult_out_31_port, mult_out_30_port, mult_out_29_port,
mult_out_28_port, mult_out_27_port, mult_out_26_port, mult_out_25_port,
mult_out_24_port, mult_out_23_port, mult_out_22_port, mult_out_21_port,
mult_out_20_port, mult_out_19_port, mult_out_18_port, mult_out_17_port,
mult_out_16_port, mult_out_15_port, mult_out_14_port, mult_out_13_port,
mult_out_12_port, mult_out_11_port, mult_out_10_port, mult_out_9_port,
mult_out_8_port, mult_out_7_port, mult_out_6_port, mult_out_5_port,
mult_out_4_port, mult_out_3_port, mult_out_2_port, mult_out_1_port,
mult_out_0_port, sum_out_31_port, sum_out_30_port, sum_out_29_port,
sum_out_28_port, sum_out_27_port, sum_out_26_port, sum_out_25_port,
sum_out_24_port, sum_out_23_port, sum_out_22_port, sum_out_21_port,
sum_out_20_port, sum_out_18_port, sum_out_17_port, sum_out_16_port,
sum_out_15_port, sum_out_14_port, sum_out_13_port, sum_out_12_port,
sum_out_11_port, sum_out_10_port, sum_out_9_port, sum_out_8_port,
sum_out_7_port, sum_out_6_port, sum_out_5_port, sum_out_4_port,
sum_out_3_port, sum_out_2_port, sum_out_1_port, sum_out_0_port,
carry_from_adder, overflow, comp_out, shift_out_31_port,
shift_out_30_port, shift_out_29_port, shift_out_28_port,
shift_out_27_port, shift_out_26_port, shift_out_25_port,
shift_out_24_port, shift_out_23_port, shift_out_22_port,
shift_out_21_port, shift_out_20_port, shift_out_19_port,
shift_out_18_port, shift_out_17_port, shift_out_16_port,
shift_out_15_port, shift_out_14_port, shift_out_13_port,
shift_out_12_port, shift_out_11_port, shift_out_10_port, shift_out_9_port
, shift_out_8_port, shift_out_7_port, shift_out_6_port, shift_out_5_port,
shift_out_4_port, shift_out_3_port, shift_out_2_port, shift_out_1_port,
shift_out_0_port, lu_out_31_port, lu_out_30_port, lu_out_29_port,
lu_out_28_port, lu_out_27_port, lu_out_26_port, lu_out_25_port,
lu_out_24_port, lu_out_23_port, lu_out_22_port, lu_out_21_port,
lu_out_20_port, lu_out_19_port, lu_out_18_port, lu_out_17_port,
lu_out_16_port, lu_out_15_port, lu_out_14_port, lu_out_13_port,
lu_out_12_port, lu_out_11_port, lu_out_10_port, lu_out_9_port,
lu_out_8_port, lu_out_7_port, lu_out_6_port, lu_out_5_port, lu_out_4_port
, lu_out_3_port, lu_out_2_port, lu_out_1_port, lu_out_0_port, n9, n10,
n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25
, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39,
n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54
, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68,
n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83
, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97,
n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108, n112,
n113, n115, n109, n110, n111, n114, n116, n117, n118, n119, n120, n121,
n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145,
n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157,
n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169,
n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181,
n182, n183, n184, n185, n186, n187 : std_logic;
begin
X_Logic0_port <= '0';
U112 : OAI33_X1 port map( A1 => n9, A2 => n10, A3 => IN1(31), B1 =>
sum_out_31_port, B2 => n11, B3 => IN2(31), ZN =>
overflow);
U140 : MUX2_X1 port map( A => IN2(14), B => B_booth_to_add_14_port, S =>
ALUW_i(1), Z => mux_B_14_port);
U143 : MUX2_X1 port map( A => IN2(11), B => B_booth_to_add_11_port, S =>
ALUW_i(1), Z => mux_B_11_port);
U146 : MUX2_X1 port map( A => IN1(9), B => A_booth_to_add_9_port, S =>
ALUW_i(1), Z => mux_A_9_port);
U147 : MUX2_X1 port map( A => IN1(8), B => A_booth_to_add_8_port, S =>
ALUW_i(1), Z => mux_A_8_port);
U148 : MUX2_X1 port map( A => IN1(7), B => A_booth_to_add_7_port, S =>
ALUW_i(1), Z => mux_A_7_port);
U151 : MUX2_X1 port map( A => IN1(4), B => A_booth_to_add_4_port, S =>
ALUW_i(1), Z => mux_A_4_port);
U152 : MUX2_X1 port map( A => IN1(3), B => A_booth_to_add_3_port, S =>
ALUW_i(1), Z => mux_A_3_port);
U153 : MUX2_X1 port map( A => IN1(31), B => A_booth_to_add_31_port, S =>
ALUW_i(1), Z => mux_A_31_port);
U154 : MUX2_X1 port map( A => IN1(30), B => A_booth_to_add_30_port, S =>
ALUW_i(1), Z => mux_A_30_port);
U156 : MUX2_X1 port map( A => IN1(29), B => A_booth_to_add_29_port, S =>
ALUW_i(1), Z => mux_A_29_port);
U157 : MUX2_X1 port map( A => IN1(28), B => A_booth_to_add_28_port, S =>
ALUW_i(1), Z => mux_A_28_port);
U158 : MUX2_X1 port map( A => IN1(27), B => A_booth_to_add_27_port, S =>
ALUW_i(1), Z => mux_A_27_port);
U159 : MUX2_X1 port map( A => IN1(26), B => A_booth_to_add_26_port, S =>
ALUW_i(1), Z => mux_A_26_port);
U160 : MUX2_X1 port map( A => IN1(25), B => A_booth_to_add_25_port, S =>
ALUW_i(1), Z => mux_A_25_port);
U161 : MUX2_X1 port map( A => IN1(24), B => A_booth_to_add_24_port, S =>
ALUW_i(1), Z => mux_A_24_port);
U162 : MUX2_X1 port map( A => IN1(23), B => A_booth_to_add_23_port, S =>
ALUW_i(1), Z => mux_A_23_port);
U163 : MUX2_X1 port map( A => IN1(22), B => A_booth_to_add_22_port, S =>
ALUW_i(1), Z => mux_A_22_port);
U164 : MUX2_X1 port map( A => IN1(21), B => A_booth_to_add_21_port, S =>
ALUW_i(1), Z => mux_A_21_port);
U165 : MUX2_X1 port map( A => IN1(20), B => A_booth_to_add_20_port, S =>
ALUW_i(1), Z => mux_A_20_port);
U167 : MUX2_X1 port map( A => IN1(19), B => A_booth_to_add_19_port, S =>
ALUW_i(1), Z => mux_A_19_port);
U169 : MUX2_X1 port map( A => IN1(17), B => A_booth_to_add_17_port, S =>
ALUW_i(1), Z => mux_A_17_port);
U170 : MUX2_X1 port map( A => IN1(16), B => A_booth_to_add_16_port, S =>
ALUW_i(1), Z => mux_A_16_port);
U171 : MUX2_X1 port map( A => IN1(15), B => A_booth_to_add_15_port, S =>
ALUW_i(1), Z => mux_A_15_port);
U172 : MUX2_X1 port map( A => IN1(14), B => A_booth_to_add_14_port, S =>
ALUW_i(1), Z => mux_A_14_port);
U174 : MUX2_X1 port map( A => IN1(12), B => A_booth_to_add_12_port, S =>
ALUW_i(1), Z => mux_A_12_port);
U175 : MUX2_X1 port map( A => IN1(11), B => A_booth_to_add_11_port, S =>
ALUW_i(1), Z => mux_A_11_port);
U178 : NAND3_X1 port map( A1 => n12, A2 => n13, A3 => n14, ZN => DOUT(9));
U179 : NAND3_X1 port map( A1 => n20, A2 => n21, A3 => n22, ZN => DOUT(8));
U180 : NAND3_X1 port map( A1 => n23, A2 => n24, A3 => n25, ZN => DOUT(7));
U181 : NAND3_X1 port map( A1 => n26, A2 => n27, A3 => n28, ZN => DOUT(6));
U182 : NAND3_X1 port map( A1 => n29, A2 => n30, A3 => n31, ZN => DOUT(5));
U183 : NAND3_X1 port map( A1 => n32, A2 => n33, A3 => n34, ZN => DOUT(4));
U184 : NAND3_X1 port map( A1 => n35, A2 => n36, A3 => n37, ZN => DOUT(3));
U185 : NAND3_X1 port map( A1 => n40, A2 => n41, A3 => n42, ZN => DOUT(30));
U186 : NAND3_X1 port map( A1 => n43, A2 => n44, A3 => n45, ZN => DOUT(2));
U187 : NAND3_X1 port map( A1 => n46, A2 => n47, A3 => n48, ZN => DOUT(29));
U188 : NAND3_X1 port map( A1 => n49, A2 => n50, A3 => n51, ZN => DOUT(28));
U189 : NAND3_X1 port map( A1 => n52, A2 => n53, A3 => n54, ZN => DOUT(27));
U190 : NAND3_X1 port map( A1 => n55, A2 => n56, A3 => n57, ZN => DOUT(26));
U191 : NAND3_X1 port map( A1 => n58, A2 => n59, A3 => n60, ZN => DOUT(25));
U192 : NAND3_X1 port map( A1 => n61, A2 => n62, A3 => n63, ZN => DOUT(24));
U193 : NAND3_X1 port map( A1 => n64, A2 => n65, A3 => n66, ZN => DOUT(23));
U194 : NAND3_X1 port map( A1 => n67, A2 => n68, A3 => n69, ZN => DOUT(22));
U195 : NAND3_X1 port map( A1 => n70, A2 => n71, A3 => n72, ZN => DOUT(21));
U196 : NAND3_X1 port map( A1 => n73, A2 => n74, A3 => n75, ZN => DOUT(20));
U197 : NAND3_X1 port map( A1 => n76, A2 => n77, A3 => n78, ZN => DOUT(1));
U198 : NAND3_X1 port map( A1 => n79, A2 => n80, A3 => n81, ZN => DOUT(19));
U199 : NAND3_X1 port map( A1 => n82, A2 => n83, A3 => n84, ZN => DOUT(18));
U200 : NAND3_X1 port map( A1 => n85, A2 => n86, A3 => n87, ZN => DOUT(17));
U201 : NAND3_X1 port map( A1 => n88, A2 => n89, A3 => n90, ZN => DOUT(16));
U202 : NAND3_X1 port map( A1 => n91, A2 => n92, A3 => n93, ZN => DOUT(15));
U203 : NAND3_X1 port map( A1 => n94, A2 => n95, A3 => n96, ZN => DOUT(14));
U204 : NAND3_X1 port map( A1 => n97, A2 => n98, A3 => n99, ZN => DOUT(13));
U205 : NAND3_X1 port map( A1 => n100, A2 => n101, A3 => n102, ZN => DOUT(12)
);
U206 : NAND3_X1 port map( A1 => n103, A2 => n104, A3 => n105, ZN => DOUT(11)
);
U207 : NAND3_X1 port map( A1 => n106, A2 => n107, A3 => n108, ZN => DOUT(10)
);
MULT : simple_booth_add_ext_N16 port map( Clock => Clock, Reset => Reset,
sign => ALUW_i(0), enable => ALUW_i(1), valid =>
valid_from_booth, A(15) => IN1(15), A(14) => IN1(14)
, A(13) => IN1(13), A(12) => IN1(12), A(11) =>
IN1(11), A(10) => IN1(10), A(9) => IN1(9), A(8) =>
IN1(8), A(7) => IN1(7), A(6) => IN1(6), A(5) =>
IN1(5), A(4) => IN1(4), A(3) => IN1(3), A(2) =>
IN1(2), A(1) => IN1(1), A(0) => IN1(0), B(15) =>
n177, B(14) => IN2(14), B(13) => IN2(13), B(12) =>
n170, B(11) => n175, B(10) => n147, B(9) => n176,
B(8) => IN2(8), B(7) => n171, B(6) => n173, B(5) =>
n183, B(4) => n178, B(3) => n180, B(2) => n186, B(1)
=> n181, B(0) => n184, A_to_add(31) =>
A_booth_to_add_31_port, A_to_add(30) =>
A_booth_to_add_30_port, A_to_add(29) =>
A_booth_to_add_29_port, A_to_add(28) =>
A_booth_to_add_28_port, A_to_add(27) =>
A_booth_to_add_27_port, A_to_add(26) =>
A_booth_to_add_26_port, A_to_add(25) =>
A_booth_to_add_25_port, A_to_add(24) =>
A_booth_to_add_24_port, A_to_add(23) =>
A_booth_to_add_23_port, A_to_add(22) =>
A_booth_to_add_22_port, A_to_add(21) =>
A_booth_to_add_21_port, A_to_add(20) =>
A_booth_to_add_20_port, A_to_add(19) =>
A_booth_to_add_19_port, A_to_add(18) =>
A_booth_to_add_18_port, A_to_add(17) =>
A_booth_to_add_17_port, A_to_add(16) =>
A_booth_to_add_16_port, A_to_add(15) =>
A_booth_to_add_15_port, A_to_add(14) =>
A_booth_to_add_14_port, A_to_add(13) =>
A_booth_to_add_13_port, A_to_add(12) =>
A_booth_to_add_12_port, A_to_add(11) =>
A_booth_to_add_11_port, A_to_add(10) =>
A_booth_to_add_10_port, A_to_add(9) =>
A_booth_to_add_9_port, A_to_add(8) =>
A_booth_to_add_8_port, A_to_add(7) =>
A_booth_to_add_7_port, A_to_add(6) =>
A_booth_to_add_6_port, A_to_add(5) =>
A_booth_to_add_5_port, A_to_add(4) =>
A_booth_to_add_4_port, A_to_add(3) =>
A_booth_to_add_3_port, A_to_add(2) =>
A_booth_to_add_2_port, A_to_add(1) =>
A_booth_to_add_1_port, A_to_add(0) =>
A_booth_to_add_0_port, B_to_add(31) =>
B_booth_to_add_31_port, B_to_add(30) =>
B_booth_to_add_30_port, B_to_add(29) =>
B_booth_to_add_29_port, B_to_add(28) =>
B_booth_to_add_28_port, B_to_add(27) =>
B_booth_to_add_27_port, B_to_add(26) =>
B_booth_to_add_26_port, B_to_add(25) =>
B_booth_to_add_25_port, B_to_add(24) =>
B_booth_to_add_24_port, B_to_add(23) =>
B_booth_to_add_23_port, B_to_add(22) =>
B_booth_to_add_22_port, B_to_add(21) =>
B_booth_to_add_21_port, B_to_add(20) =>
B_booth_to_add_20_port, B_to_add(19) =>
B_booth_to_add_19_port, B_to_add(18) =>
B_booth_to_add_18_port, B_to_add(17) =>
B_booth_to_add_17_port, B_to_add(16) =>
B_booth_to_add_16_port, B_to_add(15) =>
B_booth_to_add_15_port, B_to_add(14) =>
B_booth_to_add_14_port, B_to_add(13) =>
B_booth_to_add_13_port, B_to_add(12) =>
B_booth_to_add_12_port, B_to_add(11) =>
B_booth_to_add_11_port, B_to_add(10) =>
B_booth_to_add_10_port, B_to_add(9) =>
B_booth_to_add_9_port, B_to_add(8) =>
B_booth_to_add_8_port, B_to_add(7) =>
B_booth_to_add_7_port, B_to_add(6) =>
B_booth_to_add_6_port, B_to_add(5) =>
B_booth_to_add_5_port, B_to_add(4) =>
B_booth_to_add_4_port, B_to_add(3) =>
B_booth_to_add_3_port, B_to_add(2) =>
B_booth_to_add_2_port, B_to_add(1) =>
B_booth_to_add_1_port, B_to_add(0) =>
B_booth_to_add_0_port, sign_to_add =>
sign_booth_to_add, final_out(31) => mult_out_31_port
, final_out(30) => mult_out_30_port, final_out(29)
=> mult_out_29_port, final_out(28) =>
mult_out_28_port, final_out(27) => mult_out_27_port,
final_out(26) => mult_out_26_port, final_out(25) =>
mult_out_25_port, final_out(24) => mult_out_24_port,
final_out(23) => mult_out_23_port, final_out(22) =>
mult_out_22_port, final_out(21) => mult_out_21_port,
final_out(20) => mult_out_20_port, final_out(19) =>
mult_out_19_port, final_out(18) => mult_out_18_port,
final_out(17) => mult_out_17_port, final_out(16) =>
mult_out_16_port, final_out(15) => mult_out_15_port,
final_out(14) => mult_out_14_port, final_out(13) =>
mult_out_13_port, final_out(12) => mult_out_12_port,
final_out(11) => mult_out_11_port, final_out(10) =>
mult_out_10_port, final_out(9) => mult_out_9_port,
final_out(8) => mult_out_8_port, final_out(7) =>
mult_out_7_port, final_out(6) => mult_out_6_port,
final_out(5) => mult_out_5_port, final_out(4) =>
mult_out_4_port, final_out(3) => mult_out_3_port,
final_out(2) => mult_out_2_port, final_out(1) =>
mult_out_1_port, final_out(0) => mult_out_0_port,
ACC_from_add(31) => n185, ACC_from_add(30) =>
sum_out_30_port, ACC_from_add(29) => n168,
ACC_from_add(28) => n172, ACC_from_add(27) =>
sum_out_27_port, ACC_from_add(26) => sum_out_26_port
, ACC_from_add(25) => n149, ACC_from_add(24) => n150
, ACC_from_add(23) => sum_out_23_port,
ACC_from_add(22) => n169, ACC_from_add(21) => n174,
ACC_from_add(20) => n179, ACC_from_add(19) => n120,
ACC_from_add(18) => sum_out_18_port,
ACC_from_add(17) => sum_out_17_port,
ACC_from_add(16) => sum_out_16_port,
ACC_from_add(15) => sum_out_15_port,
ACC_from_add(14) => sum_out_14_port,
ACC_from_add(13) => sum_out_13_port,
ACC_from_add(12) => sum_out_12_port,
ACC_from_add(11) => sum_out_11_port,
ACC_from_add(10) => sum_out_10_port, ACC_from_add(9)
=> sum_out_9_port, ACC_from_add(8) => sum_out_8_port
, ACC_from_add(7) => sum_out_7_port, ACC_from_add(6)
=> sum_out_6_port, ACC_from_add(5) => sum_out_5_port
, ACC_from_add(4) => sum_out_4_port, ACC_from_add(3)
=> sum_out_3_port, ACC_from_add(2) => sum_out_2_port
, ACC_from_add(1) => sum_out_1_port, ACC_from_add(0)
=> sum_out_0_port);
ADDER : p4add_N32_logN5 port map( A(31) => mux_A_31_port, A(30) =>
mux_A_30_port, A(29) => mux_A_29_port, A(28) =>
mux_A_28_port, A(27) => mux_A_27_port, A(26) =>
mux_A_26_port, A(25) => mux_A_25_port, A(24) =>
mux_A_24_port, A(23) => mux_A_23_port, A(22) =>
mux_A_22_port, A(21) => mux_A_21_port, A(20) =>
mux_A_20_port, A(19) => mux_A_19_port, A(18) =>
mux_A_18_port, A(17) => mux_A_17_port, A(16) =>
mux_A_16_port, A(15) => mux_A_15_port, A(14) =>
mux_A_14_port, A(13) => mux_A_13_port, A(12) =>
mux_A_12_port, A(11) => mux_A_11_port, A(10) =>
mux_A_10_port, A(9) => mux_A_9_port, A(8) =>
mux_A_8_port, A(7) => mux_A_7_port, A(6) =>
mux_A_6_port, A(5) => mux_A_5_port, A(4) =>
mux_A_4_port, A(3) => mux_A_3_port, A(2) =>
mux_A_2_port, A(1) => mux_A_1_port, A(0) =>
mux_A_0_port, B(31) => mux_B_31_port, B(30) =>
mux_B_30_port, B(29) => mux_B_29_port, B(28) =>
mux_B_28_port, B(27) => mux_B_27_port, B(26) =>
mux_B_26_port, B(25) => mux_B_25_port, B(24) =>
mux_B_24_port, B(23) => mux_B_23_port, B(22) =>
mux_B_22_port, B(21) => mux_B_21_port, B(20) =>
mux_B_20_port, B(19) => mux_B_19_port, B(18) =>
mux_B_18_port, B(17) => mux_B_17_port, B(16) =>
mux_B_16_port, B(15) => mux_B_15_port, B(14) =>
mux_B_14_port, B(13) => mux_B_13_port, B(12) =>
mux_B_12_port, B(11) => mux_B_11_port, B(10) =>
mux_B_10_port, B(9) => mux_B_9_port, B(8) =>
mux_B_8_port, B(7) => mux_B_7_port, B(6) =>
mux_B_6_port, B(5) => mux_B_5_port, B(4) =>
mux_B_4_port, B(3) => mux_B_3_port, B(2) =>
mux_B_2_port, B(1) => mux_B_1_port, B(0) =>
mux_B_0_port, Cin => X_Logic0_port, sign => mux_sign
, S(31) => sum_out_31_port, S(30) => sum_out_30_port
, S(29) => sum_out_29_port, S(28) => sum_out_28_port
, S(27) => sum_out_27_port, S(26) => sum_out_26_port
, S(25) => sum_out_25_port, S(24) => sum_out_24_port
, S(23) => sum_out_23_port, S(22) => sum_out_22_port
, S(21) => sum_out_21_port, S(20) => sum_out_20_port
, S(19) => n120, S(18) => sum_out_18_port, S(17) =>
sum_out_17_port, S(16) => sum_out_16_port, S(15) =>
sum_out_15_port, S(14) => sum_out_14_port, S(13) =>
sum_out_13_port, S(12) => sum_out_12_port, S(11) =>
sum_out_11_port, S(10) => sum_out_10_port, S(9) =>
sum_out_9_port, S(8) => sum_out_8_port, S(7) =>
sum_out_7_port, S(6) => sum_out_6_port, S(5) =>
sum_out_5_port, S(4) => sum_out_4_port, S(3) =>
sum_out_3_port, S(2) => sum_out_2_port, S(1) =>
sum_out_1_port, S(0) => sum_out_0_port, Cout =>
carry_from_adder);
COMP : comparator_M32 port map( C => carry_from_adder, V => overflow,
SUM(31) => sum_out_31_port, SUM(30) =>
sum_out_30_port, SUM(29) => sum_out_29_port, SUM(28)
=> sum_out_28_port, SUM(27) => sum_out_27_port,
SUM(26) => sum_out_26_port, SUM(25) =>
sum_out_25_port, SUM(24) => sum_out_24_port, SUM(23)
=> sum_out_23_port, SUM(22) => sum_out_22_port,
SUM(21) => sum_out_21_port, SUM(20) =>
sum_out_20_port, SUM(19) => n120, SUM(18) =>
sum_out_18_port, SUM(17) => sum_out_17_port, SUM(16)
=> sum_out_16_port, SUM(15) => sum_out_15_port,
SUM(14) => sum_out_14_port, SUM(13) =>
sum_out_13_port, SUM(12) => sum_out_12_port, SUM(11)
=> sum_out_11_port, SUM(10) => sum_out_10_port,
SUM(9) => sum_out_9_port, SUM(8) => sum_out_8_port,
SUM(7) => sum_out_7_port, SUM(6) => sum_out_6_port,
SUM(5) => sum_out_5_port, SUM(4) => sum_out_4_port,
SUM(3) => sum_out_3_port, SUM(2) => sum_out_2_port,
SUM(1) => sum_out_1_port, SUM(0) => sum_out_0_port,
sel(2) => ALUW_i(4), sel(1) => ALUW_i(3), sel(0) =>
ALUW_i(2), sign => ALUW_i(0), S => comp_out);
SHIFT : shifter port map( A(31) => IN1(31), A(30) => IN1(30), A(29) =>
IN1(29), A(28) => IN1(28), A(27) => IN1(27), A(26)
=> IN1(26), A(25) => IN1(25), A(24) => IN1(24),
A(23) => IN1(23), A(22) => IN1(22), A(21) => IN1(21)
, A(20) => IN1(20), A(19) => IN1(19), A(18) =>
IN1(18), A(17) => IN1(17), A(16) => IN1(16), A(15)
=> IN1(15), A(14) => IN1(14), A(13) => IN1(13),
A(12) => IN1(12), A(11) => IN1(11), A(10) => IN1(10)
, A(9) => IN1(9), A(8) => IN1(8), A(7) => IN1(7),
A(6) => IN1(6), A(5) => IN1(5), A(4) => IN1(4), A(3)
=> IN1(3), A(2) => IN1(2), A(1) => IN1(1), A(0) =>
IN1(0), B(4) => n178, B(3) => n180, B(2) => n186,
B(1) => n181, B(0) => n184, LOGIC_ARITH => ALUW_i(8)
, LEFT_RIGHT => ALUW_i(9), OUTPUT(31) =>
shift_out_31_port, OUTPUT(30) => shift_out_30_port,
OUTPUT(29) => shift_out_29_port, OUTPUT(28) =>
shift_out_28_port, OUTPUT(27) => shift_out_27_port,
OUTPUT(26) => shift_out_26_port, OUTPUT(25) =>
shift_out_25_port, OUTPUT(24) => shift_out_24_port,
OUTPUT(23) => shift_out_23_port, OUTPUT(22) =>
shift_out_22_port, OUTPUT(21) => shift_out_21_port,
OUTPUT(20) => shift_out_20_port, OUTPUT(19) =>
shift_out_19_port, OUTPUT(18) => shift_out_18_port,
OUTPUT(17) => shift_out_17_port, OUTPUT(16) =>
shift_out_16_port, OUTPUT(15) => shift_out_15_port,
OUTPUT(14) => shift_out_14_port, OUTPUT(13) =>
shift_out_13_port, OUTPUT(12) => shift_out_12_port,
OUTPUT(11) => shift_out_11_port, OUTPUT(10) =>
shift_out_10_port, OUTPUT(9) => shift_out_9_port,
OUTPUT(8) => shift_out_8_port, OUTPUT(7) =>
shift_out_7_port, OUTPUT(6) => shift_out_6_port,
OUTPUT(5) => shift_out_5_port, OUTPUT(4) =>
shift_out_4_port, OUTPUT(3) => shift_out_3_port,
OUTPUT(2) => shift_out_2_port, OUTPUT(1) =>
shift_out_1_port, OUTPUT(0) => shift_out_0_port);
LU : logic_unit_SIZE32 port map( IN1(31) => IN1(31), IN1(30) => IN1(30),
IN1(29) => IN1(29), IN1(28) => IN1(28), IN1(27) =>
IN1(27), IN1(26) => IN1(26), IN1(25) => IN1(25),
IN1(24) => IN1(24), IN1(23) => IN1(23), IN1(22) =>
IN1(22), IN1(21) => IN1(21), IN1(20) => IN1(20),
IN1(19) => IN1(19), IN1(18) => IN1(18), IN1(17) =>
IN1(17), IN1(16) => IN1(16), IN1(15) => IN1(15),
IN1(14) => IN1(14), IN1(13) => IN1(13), IN1(12) =>
IN1(12), IN1(11) => IN1(11), IN1(10) => IN1(10),
IN1(9) => IN1(9), IN1(8) => IN1(8), IN1(7) => IN1(7)
, IN1(6) => IN1(6), IN1(5) => IN1(5), IN1(4) =>
IN1(4), IN1(3) => IN1(3), IN1(2) => IN1(2), IN1(1)
=> IN1(1), IN1(0) => IN1(0), IN2(31) => IN2(31),
IN2(30) => IN2(30), IN2(29) => IN2(29), IN2(28) =>
IN2(28), IN2(27) => IN2(27), IN2(26) => IN2(26),
IN2(25) => IN2(25), IN2(24) => IN2(24), IN2(23) =>
IN2(23), IN2(22) => IN2(22), IN2(21) => IN2(21),
IN2(20) => IN2(20), IN2(19) => n148, IN2(18) =>
IN2(18), IN2(17) => n146, IN2(16) => IN2(16),
IN2(15) => n177, IN2(14) => IN2(14), IN2(13) =>
IN2(13), IN2(12) => n170, IN2(11) => n175, IN2(10)
=> n147, IN2(9) => n176, IN2(8) => IN2(8), IN2(7) =>
n171, IN2(6) => n173, IN2(5) => n183, IN2(4) => n178
, IN2(3) => n180, IN2(2) => n186, IN2(1) => n181,
IN2(0) => n184, CTRL(1) => ALUW_i(6), CTRL(0) =>
ALUW_i(5), OUT1(31) => lu_out_31_port, OUT1(30) =>
lu_out_30_port, OUT1(29) => lu_out_29_port, OUT1(28)
=> lu_out_28_port, OUT1(27) => lu_out_27_port,
OUT1(26) => lu_out_26_port, OUT1(25) =>
lu_out_25_port, OUT1(24) => lu_out_24_port, OUT1(23)
=> lu_out_23_port, OUT1(22) => lu_out_22_port,
OUT1(21) => lu_out_21_port, OUT1(20) =>
lu_out_20_port, OUT1(19) => lu_out_19_port, OUT1(18)
=> lu_out_18_port, OUT1(17) => lu_out_17_port,
OUT1(16) => lu_out_16_port, OUT1(15) =>
lu_out_15_port, OUT1(14) => lu_out_14_port, OUT1(13)
=> lu_out_13_port, OUT1(12) => lu_out_12_port,
OUT1(11) => lu_out_11_port, OUT1(10) =>
lu_out_10_port, OUT1(9) => lu_out_9_port, OUT1(8) =>
lu_out_8_port, OUT1(7) => lu_out_7_port, OUT1(6) =>
lu_out_6_port, OUT1(5) => lu_out_5_port, OUT1(4) =>
lu_out_4_port, OUT1(3) => lu_out_3_port, OUT1(2) =>
lu_out_2_port, OUT1(1) => lu_out_1_port, OUT1(0) =>
lu_out_0_port);
U141 : MUX2_X1 port map( A => IN2(13), B => B_booth_to_add_13_port, S =>
ALUW_i(1), Z => mux_B_13_port);
U137 : MUX2_X1 port map( A => IN2(17), B => B_booth_to_add_17_port, S =>
ALUW_i(1), Z => mux_B_17_port);
U129 : MUX2_X1 port map( A => IN2(24), B => B_booth_to_add_24_port, S =>
ALUW_i(1), Z => mux_B_24_port);
U128 : MUX2_X1 port map( A => IN2(25), B => B_booth_to_add_25_port, S =>
ALUW_i(1), Z => mux_B_25_port);
U127 : MUX2_X1 port map( A => IN2(26), B => B_booth_to_add_26_port, S =>
ALUW_i(1), Z => mux_B_26_port);
U126 : MUX2_X1 port map( A => IN2(27), B => B_booth_to_add_27_port, S =>
ALUW_i(1), Z => mux_B_27_port);
U125 : MUX2_X1 port map( A => IN2(28), B => B_booth_to_add_28_port, S =>
ALUW_i(1), Z => mux_B_28_port);
U122 : MUX2_X1 port map( A => IN2(30), B => B_booth_to_add_30_port, S =>
ALUW_i(1), Z => mux_B_30_port);
U121 : MUX2_X1 port map( A => IN2(31), B => B_booth_to_add_31_port, S =>
ALUW_i(1), Z => mux_B_31_port);
U118 : MUX2_X1 port map( A => IN2(5), B => B_booth_to_add_5_port, S =>
ALUW_i(1), Z => mux_B_5_port);
U117 : MUX2_X1 port map( A => IN2(6), B => B_booth_to_add_6_port, S =>
ALUW_i(1), Z => mux_B_6_port);
U135 : MUX2_X1 port map( A => IN2(19), B => B_booth_to_add_19_port, S =>
ALUW_i(1), Z => mux_B_19_port);
U131 : MUX2_X1 port map( A => IN2(22), B => B_booth_to_add_22_port, S =>
ALUW_i(1), Z => mux_B_22_port);
U29 : AOI22_X1 port map( A1 => n187, A2 => lu_out_31_port, B1 => n123, B2 =>
IN2(31), ZN => n39);
U28 : NAND2_X1 port map( A1 => n38, A2 => n39, ZN => DOUT(31));
U70 : AOI22_X1 port map( A1 => n122, A2 => shift_out_19_port, B1 => n121, B2
=> mult_out_19_port, ZN => n81);
U65 : AOI22_X1 port map( A1 => n187, A2 => lu_out_20_port, B1 => n123, B2 =>
IN2(20), ZN => n74);
U64 : AOI22_X1 port map( A1 => n122, A2 => shift_out_20_port, B1 => n121, B2
=> mult_out_20_port, ZN => n75);
U61 : AOI22_X1 port map( A1 => n122, A2 => shift_out_21_port, B1 => n121, B2
=> mult_out_21_port, ZN => n72);
U27 : NAND2_X1 port map( A1 => sum_out_3_port, A2 => n124, ZN => n35);
U25 : AOI22_X1 port map( A1 => n15, A2 => shift_out_3_port, B1 => n121, B2
=> mult_out_3_port, ZN => n37);
U59 : AOI22_X1 port map( A1 => n187, A2 => lu_out_22_port, B1 => n123, B2 =>
IN2(22), ZN => n68);
U58 : AOI22_X1 port map( A1 => n122, A2 => shift_out_22_port, B1 => n121, B2
=> mult_out_22_port, ZN => n69);
U53 : AOI22_X1 port map( A1 => n187, A2 => lu_out_24_port, B1 => n123, B2 =>
IN2(24), ZN => n62);
U52 : AOI22_X1 port map( A1 => n122, A2 => shift_out_24_port, B1 => n121, B2
=> mult_out_24_port, ZN => n63);
U84 : NAND2_X1 port map( A1 => sum_out_15_port, A2 => n124, ZN => n91);
U82 : AOI22_X1 port map( A1 => n122, A2 => shift_out_15_port, B1 => n121, B2
=> mult_out_15_port, ZN => n93);
U12 : NAND2_X1 port map( A1 => sum_out_8_port, A2 => n124, ZN => n20);
U10 : AOI22_X1 port map( A1 => n122, A2 => shift_out_8_port, B1 => n121, B2
=> mult_out_8_port, ZN => n22);
U18 : NAND2_X1 port map( A1 => sum_out_6_port, A2 => n124, ZN => n26);
U16 : AOI22_X1 port map( A1 => n15, A2 => shift_out_6_port, B1 => n121, B2
=> mult_out_6_port, ZN => n28);
U50 : AOI22_X1 port map( A1 => n187, A2 => lu_out_25_port, B1 => n123, B2 =>
IN2(25), ZN => n59);
U49 : AOI22_X1 port map( A1 => n122, A2 => shift_out_25_port, B1 => n121, B2
=> mult_out_25_port, ZN => n60);
U78 : NAND2_X1 port map( A1 => sum_out_17_port, A2 => n124, ZN => n85);
U76 : AOI22_X1 port map( A1 => n122, A2 => shift_out_17_port, B1 => n16, B2
=> mult_out_17_port, ZN => n87);
U91 : AOI22_X1 port map( A1 => n122, A2 => shift_out_12_port, B1 => n121, B2
=> mult_out_12_port, ZN => n102);
U80 : AOI22_X1 port map( A1 => n187, A2 => lu_out_16_port, B1 => n123, B2 =>
IN2(16), ZN => n89);
U79 : AOI22_X1 port map( A1 => n122, A2 => shift_out_16_port, B1 => n121, B2
=> mult_out_16_port, ZN => n90);
U42 : NAND2_X1 port map( A1 => n172, A2 => n124, ZN => n49);
U41 : AOI22_X1 port map( A1 => n187, A2 => lu_out_28_port, B1 => n123, B2 =>
IN2(28), ZN => n50);
U40 : AOI22_X1 port map( A1 => n15, A2 => shift_out_28_port, B1 => n121, B2
=> mult_out_28_port, ZN => n51);
U24 : NAND2_X1 port map( A1 => sum_out_4_port, A2 => n124, ZN => n32);
U23 : AOI22_X1 port map( A1 => n187, A2 => lu_out_4_port, B1 => n123, B2 =>
n178, ZN => n33);
U22 : AOI22_X1 port map( A1 => n122, A2 => shift_out_4_port, B1 => n121, B2
=> mult_out_4_port, ZN => n34);
U45 : NAND2_X1 port map( A1 => sum_out_27_port, A2 => n124, ZN => n52);
U44 : AOI22_X1 port map( A1 => n187, A2 => lu_out_27_port, B1 => n123, B2 =>
IN2(27), ZN => n53);
U43 : AOI22_X1 port map( A1 => n122, A2 => shift_out_27_port, B1 => n121, B2
=> mult_out_27_port, ZN => n54);
U21 : NAND2_X1 port map( A1 => sum_out_5_port, A2 => n124, ZN => n29);
U19 : AOI22_X1 port map( A1 => n122, A2 => shift_out_5_port, B1 => n121, B2
=> mult_out_5_port, ZN => n31);
U90 : NAND2_X1 port map( A1 => sum_out_13_port, A2 => n124, ZN => n97);
U88 : AOI22_X1 port map( A1 => n122, A2 => shift_out_13_port, B1 => n121, B2
=> mult_out_13_port, ZN => n99);
U9 : NAND2_X1 port map( A1 => sum_out_9_port, A2 => n124, ZN => n12);
U7 : AOI22_X1 port map( A1 => n122, A2 => shift_out_9_port, B1 => n121, B2
=> mult_out_9_port, ZN => n14);
U15 : NAND2_X1 port map( A1 => sum_out_7_port, A2 => n124, ZN => n23);
U13 : AOI22_X1 port map( A1 => n122, A2 => shift_out_7_port, B1 => n121, B2
=> mult_out_7_port, ZN => n25);
U87 : NAND2_X1 port map( A1 => sum_out_14_port, A2 => n124, ZN => n94);
U85 : AOI22_X1 port map( A1 => n122, A2 => shift_out_14_port, B1 => n121, B2
=> mult_out_14_port, ZN => n96);
U73 : AOI22_X1 port map( A1 => n122, A2 => shift_out_18_port, B1 => n16, B2
=> mult_out_18_port, ZN => n84);
U55 : AOI22_X1 port map( A1 => n122, A2 => shift_out_23_port, B1 => n121, B2
=> mult_out_23_port, ZN => n66);
U46 : AOI22_X1 port map( A1 => n122, A2 => shift_out_26_port, B1 => n16, B2
=> mult_out_26_port, ZN => n57);
U38 : AOI22_X1 port map( A1 => n187, A2 => lu_out_29_port, B1 => n123, B2 =>
IN2(29), ZN => n47);
U37 : AOI22_X1 port map( A1 => n122, A2 => shift_out_29_port, B1 => n121, B2
=> mult_out_29_port, ZN => n48);
U36 : NAND2_X1 port map( A1 => sum_out_2_port, A2 => n124, ZN => n43);
U35 : AOI22_X1 port map( A1 => n187, A2 => lu_out_2_port, B1 => n123, B2 =>
n186, ZN => n44);
U34 : AOI22_X1 port map( A1 => n122, A2 => shift_out_2_port, B1 => n121, B2
=> mult_out_2_port, ZN => n45);
U69 : NAND2_X1 port map( A1 => sum_out_1_port, A2 => n124, ZN => n76);
U67 : AOI22_X1 port map( A1 => n122, A2 => shift_out_1_port, B1 => n121, B2
=> mult_out_1_port, ZN => n78);
U32 : AOI22_X1 port map( A1 => n187, A2 => lu_out_30_port, B1 => n123, B2 =>
IN2(30), ZN => n41);
U31 : AOI22_X1 port map( A1 => n122, A2 => shift_out_30_port, B1 => n121, B2
=> mult_out_30_port, ZN => n42);
U96 : NAND2_X1 port map( A1 => sum_out_11_port, A2 => n124, ZN => n103);
U94 : AOI22_X1 port map( A1 => n122, A2 => shift_out_11_port, B1 => n121, B2
=> mult_out_11_port, ZN => n105);
U99 : NAND2_X1 port map( A1 => sum_out_10_port, A2 => n124, ZN => n106);
U97 : AOI22_X1 port map( A1 => n122, A2 => shift_out_10_port, B1 => n121, B2
=> mult_out_10_port, ZN => n108);
U108 : NOR3_X1 port map( A1 => ALUW_i(12), A2 => ALUW_i(11), A3 => n115, ZN
=> n17);
U166 : MUX2_X1 port map( A => IN1(1), B => A_booth_to_add_1_port, S =>
ALUW_i(1), Z => mux_A_1_port);
U168 : MUX2_X1 port map( A => IN1(18), B => A_booth_to_add_18_port, S =>
ALUW_i(1), Z => mux_A_18_port);
U173 : MUX2_X1 port map( A => IN1(13), B => A_booth_to_add_13_port, S =>
ALUW_i(1), Z => mux_A_13_port);
U176 : MUX2_X1 port map( A => IN1(10), B => A_booth_to_add_10_port, S =>
ALUW_i(1), Z => mux_A_10_port);
U149 : MUX2_X1 port map( A => IN1(6), B => A_booth_to_add_6_port, S =>
ALUW_i(1), Z => mux_A_6_port);
U5 : INV_X1 port map( A => IN2(31), ZN => n10);
U4 : INV_X1 port map( A => IN1(31), ZN => n11);
U111 : INV_X1 port map( A => ALUW_i(10), ZN => n115);
U105 : INV_X1 port map( A => ALUW_i(12), ZN => n112);
U2 : NAND2_X1 port map( A1 => ALUW_i(1), A2 => B_booth_to_add_3_port, ZN =>
n109);
U3 : NAND2_X1 port map( A1 => n132, A2 => n109, ZN => mux_B_3_port);
U6 : AOI22_X1 port map( A1 => ALUW_i(1), A2 => B_booth_to_add_8_port, B1 =>
n127, B2 => IN2(8), ZN => n110);
U8 : INV_X1 port map( A => n110, ZN => mux_B_8_port);
U11 : INV_X1 port map( A => ALUW_i(1), ZN => n111);
U14 : NOR2_X1 port map( A1 => valid_from_booth, A2 => n111, ZN => stall_o);
U17 : AOI22_X1 port map( A1 => ALUW_i(1), A2 => B_booth_to_add_29_port, B1
=> n127, B2 => IN2(29), ZN => n114);
U20 : INV_X1 port map( A => n114, ZN => mux_B_29_port);
U26 : INV_X1 port map( A => ALUW_i(11), ZN => n116);
U30 : NOR3_X1 port map( A1 => ALUW_i(12), A2 => n115, A3 => n116, ZN => n143
);
U33 : AOI22_X1 port map( A1 => A_booth_to_add_2_port, A2 => ALUW_i(1), B1 =>
n127, B2 => IN1(2), ZN => n117);
U39 : INV_X1 port map( A => n117, ZN => mux_A_2_port);
U47 : AOI222_X1 port map( A1 => sum_out_0_port, A2 => n124, B1 => n184, B2
=> n123, C1 => n17, C2 => lu_out_0_port, ZN => n118)
;
U48 : INV_X1 port map( A => n118, ZN => n119);
U51 : AOI21_X1 port map( B1 => n121, B2 => mult_out_0_port, A => n119, ZN =>
n141);
U54 : CLKBUF_X1 port map( A => sum_out_20_port, Z => n179);
U56 : INV_X2 port map( A => ALUW_i(1), ZN => n127);
U57 : BUF_X1 port map( A => sum_out_21_port, Z => n174);
U60 : BUF_X1 port map( A => IN2(1), Z => n181);
U62 : MUX2_X1 port map( A => IN1(0), B => A_booth_to_add_0_port, S =>
ALUW_i(1), Z => mux_A_0_port);
U63 : BUF_X2 port map( A => n16, Z => n121);
U66 : BUF_X2 port map( A => n18, Z => n123);
U68 : BUF_X2 port map( A => n19, Z => n124);
U71 : BUF_X1 port map( A => IN2(2), Z => n186);
U72 : BUF_X1 port map( A => IN2(15), Z => n177);
U74 : MUX2_X1 port map( A => IN1(5), B => A_booth_to_add_5_port, S =>
ALUW_i(1), Z => mux_A_5_port);
U75 : BUF_X2 port map( A => n17, Z => n187);
U77 : BUF_X2 port map( A => n15, Z => n122);
U81 : BUF_X1 port map( A => IN2(4), Z => n178);
U83 : NAND2_X1 port map( A1 => n139, A2 => n140, ZN => mux_B_0_port);
U86 : NAND2_X1 port map( A1 => n144, A2 => n145, ZN => DOUT(0));
U89 : NAND2_X1 port map( A1 => IN2(4), A2 => n127, ZN => n125);
U92 : NAND2_X1 port map( A1 => n125, A2 => n126, ZN => mux_B_4_port);
U93 : NAND2_X1 port map( A1 => B_booth_to_add_4_port, A2 => ALUW_i(1), ZN =>
n126);
U95 : NAND2_X1 port map( A1 => B_booth_to_add_20_port, A2 => ALUW_i(1), ZN
=> n129);
U98 : NAND2_X1 port map( A1 => IN2(20), A2 => n127, ZN => n128);
U100 : NAND2_X1 port map( A1 => n128, A2 => n129, ZN => mux_B_20_port);
U101 : NAND2_X1 port map( A1 => B_booth_to_add_7_port, A2 => ALUW_i(1), ZN
=> n130);
U102 : NAND2_X1 port map( A1 => n131, A2 => n130, ZN => mux_B_7_port);
U103 : NAND2_X1 port map( A1 => IN2(7), A2 => n127, ZN => n131);
U104 : NAND2_X1 port map( A1 => IN2(3), A2 => n127, ZN => n132);
U106 : NAND2_X1 port map( A1 => B_booth_to_add_9_port, A2 => ALUW_i(1), ZN
=> n133);
U107 : NAND2_X1 port map( A1 => n134, A2 => n133, ZN => mux_B_9_port);
U109 : NAND2_X1 port map( A1 => IN2(9), A2 => n127, ZN => n134);
U110 : NAND2_X1 port map( A1 => B_booth_to_add_12_port, A2 => ALUW_i(1), ZN
=> n136);
U113 : NAND2_X1 port map( A1 => IN2(12), A2 => n127, ZN => n135);
U114 : NAND2_X1 port map( A1 => n135, A2 => n136, ZN => mux_B_12_port);
U115 : NAND2_X1 port map( A1 => B_booth_to_add_23_port, A2 => ALUW_i(1), ZN
=> n138);
U116 : NAND2_X1 port map( A1 => IN2(23), A2 => n127, ZN => n137);
U119 : NAND2_X1 port map( A1 => n137, A2 => n138, ZN => mux_B_23_port);
U120 : NAND2_X1 port map( A1 => B_booth_to_add_0_port, A2 => ALUW_i(1), ZN
=> n140);
U123 : NAND2_X1 port map( A1 => IN2(0), A2 => n127, ZN => n139);
U124 : NAND2_X1 port map( A1 => shift_out_0_port, A2 => n15, ZN => n142);
U130 : AND2_X1 port map( A1 => n142, A2 => n141, ZN => n145);
U132 : NAND2_X1 port map( A1 => comp_out, A2 => n143, ZN => n144);
U133 : NAND2_X4 port map( A1 => n156, A2 => n157, ZN => mux_sign);
U134 : CLKBUF_X1 port map( A => IN2(17), Z => n146);
U136 : CLKBUF_X1 port map( A => IN2(10), Z => n147);
U138 : CLKBUF_X1 port map( A => IN2(19), Z => n148);
U139 : BUF_X1 port map( A => sum_out_25_port, Z => n149);
U142 : BUF_X1 port map( A => sum_out_24_port, Z => n150);
U144 : CLKBUF_X1 port map( A => IN2(11), Z => n175);
U145 : CLKBUF_X1 port map( A => IN2(7), Z => n171);
U150 : CLKBUF_X1 port map( A => IN2(9), Z => n176);
U155 : CLKBUF_X1 port map( A => IN2(5), Z => n183);
U177 : CLKBUF_X1 port map( A => IN2(12), Z => n170);
U208 : CLKBUF_X1 port map( A => IN2(6), Z => n173);
U209 : INV_X1 port map( A => n182, ZN => n185);
U210 : CLKBUF_X1 port map( A => n9, Z => n182);
U211 : CLKBUF_X1 port map( A => sum_out_29_port, Z => n168);
U212 : CLKBUF_X1 port map( A => sum_out_22_port, Z => n169);
U213 : CLKBUF_X1 port map( A => sum_out_28_port, Z => n172);
U214 : INV_X1 port map( A => ALUW_i(11), ZN => n113);
U215 : CLKBUF_X1 port map( A => IN2(3), Z => n180);
U216 : CLKBUF_X1 port map( A => IN2(0), Z => n184);
U217 : INV_X1 port map( A => sum_out_31_port, ZN => n9);
U218 : OR2_X1 port map( A1 => ALUW_i(1), A2 => n155, ZN => n157);
U219 : INV_X1 port map( A => ALUW_i(7), ZN => n155);
U220 : NOR2_X1 port map( A1 => n123, A2 => n112, ZN => n16);
U221 : NOR3_X1 port map( A1 => ALUW_i(10), A2 => ALUW_i(12), A3 => n113, ZN
=> n15);
U222 : NAND2_X1 port map( A1 => ALUW_i(1), A2 => sign_booth_to_add, ZN =>
n156);
U223 : NOR3_X1 port map( A1 => ALUW_i(10), A2 => ALUW_i(12), A3 =>
ALUW_i(11), ZN => n19);
U224 : NOR3_X1 port map( A1 => ALUW_i(10), A2 => ALUW_i(11), A3 => n112, ZN
=> n18);
U225 : NAND2_X1 port map( A1 => IN2(16), A2 => n127, ZN => n151);
U226 : NAND2_X1 port map( A1 => n151, A2 => n152, ZN => mux_B_16_port);
U227 : NAND2_X1 port map( A1 => B_booth_to_add_16_port, A2 => ALUW_i(1), ZN
=> n152);
U228 : NAND2_X1 port map( A1 => IN2(18), A2 => n127, ZN => n153);
U229 : NAND2_X1 port map( A1 => n153, A2 => n154, ZN => mux_B_18_port);
U230 : NAND2_X1 port map( A1 => B_booth_to_add_18_port, A2 => ALUW_i(1), ZN
=> n154);
U231 : NAND2_X1 port map( A1 => B_booth_to_add_1_port, A2 => ALUW_i(1), ZN
=> n159);
U232 : NAND2_X1 port map( A1 => B_booth_to_add_2_port, A2 => ALUW_i(1), ZN
=> n161);
U233 : NAND2_X1 port map( A1 => B_booth_to_add_21_port, A2 => ALUW_i(1), ZN
=> n165);
U234 : NAND2_X1 port map( A1 => B_booth_to_add_15_port, A2 => ALUW_i(1), ZN
=> n167);
U235 : NAND2_X1 port map( A1 => IN2(1), A2 => n127, ZN => n158);
U236 : NAND2_X1 port map( A1 => n158, A2 => n159, ZN => mux_B_1_port);
U237 : NAND2_X1 port map( A1 => IN2(2), A2 => n127, ZN => n160);
U238 : NAND2_X1 port map( A1 => n160, A2 => n161, ZN => mux_B_2_port);
U239 : NAND2_X1 port map( A1 => IN2(10), A2 => n127, ZN => n162);
U240 : NAND2_X1 port map( A1 => n162, A2 => n163, ZN => mux_B_10_port);
U241 : NAND2_X1 port map( A1 => B_booth_to_add_10_port, A2 => ALUW_i(1), ZN
=> n163);
U242 : NAND2_X1 port map( A1 => IN2(21), A2 => n127, ZN => n164);
U243 : NAND2_X1 port map( A1 => n164, A2 => n165, ZN => mux_B_21_port);
U244 : NAND2_X1 port map( A1 => IN2(15), A2 => n127, ZN => n166);
U245 : NAND2_X1 port map( A1 => n166, A2 => n167, ZN => mux_B_15_port);
U246 : AOI22_X1 port map( A1 => n187, A2 => lu_out_18_port, B1 => n123, B2
=> IN2(18), ZN => n83);
U247 : NAND2_X1 port map( A1 => n169, A2 => n124, ZN => n67);
U248 : AOI22_X1 port map( A1 => n17, A2 => lu_out_10_port, B1 => n123, B2 =>
n147, ZN => n107);
U249 : NAND2_X1 port map( A1 => sum_out_26_port, A2 => n124, ZN => n55);
U250 : AOI22_X1 port map( A1 => n187, A2 => lu_out_21_port, B1 => n123, B2
=> IN2(21), ZN => n71);
U251 : AOI22_X1 port map( A1 => n187, A2 => lu_out_26_port, B1 => n123, B2
=> IN2(26), ZN => n56);
U252 : NAND2_X1 port map( A1 => n168, A2 => n124, ZN => n46);
U253 : AOI22_X1 port map( A1 => n187, A2 => lu_out_12_port, B1 => n123, B2
=> n170, ZN => n101);
U254 : NAND2_X1 port map( A1 => n179, A2 => n124, ZN => n73);
U255 : NAND2_X1 port map( A1 => n174, A2 => n124, ZN => n70);
U256 : NAND2_X1 port map( A1 => sum_out_12_port, A2 => n124, ZN => n100);
U257 : AOI22_X1 port map( A1 => n187, A2 => lu_out_3_port, B1 => n123, B2 =>
n180, ZN => n36);
U258 : AOI22_X1 port map( A1 => n187, A2 => lu_out_1_port, B1 => n123, B2 =>
n181, ZN => n77);
U259 : AOI22_X1 port map( A1 => n187, A2 => lu_out_17_port, B1 => n123, B2
=> n146, ZN => n86);
U260 : AOI22_X1 port map( A1 => n17, A2 => lu_out_14_port, B1 => n123, B2 =>
IN2(14), ZN => n95);
U261 : AOI22_X1 port map( A1 => n187, A2 => lu_out_23_port, B1 => n123, B2
=> IN2(23), ZN => n65);
U262 : AOI22_X1 port map( A1 => n187, A2 => lu_out_13_port, B1 => n123, B2
=> IN2(13), ZN => n98);
U263 : NAND2_X1 port map( A1 => n120, A2 => n124, ZN => n79);
U264 : AOI22_X1 port map( A1 => n187, A2 => lu_out_8_port, B1 => n123, B2 =>
IN2(8), ZN => n21);
U265 : AOI22_X1 port map( A1 => n187, A2 => lu_out_6_port, B1 => n123, B2 =>
n173, ZN => n27);
U266 : AOI22_X1 port map( A1 => n187, A2 => lu_out_19_port, B1 => n123, B2
=> n148, ZN => n80);
U267 : NAND2_X1 port map( A1 => sum_out_16_port, A2 => n124, ZN => n88);
U268 : NAND2_X1 port map( A1 => sum_out_18_port, A2 => n124, ZN => n82);
U269 : AOI22_X1 port map( A1 => n187, A2 => lu_out_15_port, B1 => n123, B2
=> n177, ZN => n92);
U270 : AOI22_X1 port map( A1 => n187, A2 => lu_out_11_port, B1 => n123, B2
=> n175, ZN => n104);
U271 : AOI22_X1 port map( A1 => n187, A2 => lu_out_7_port, B1 => n123, B2 =>
n171, ZN => n24);
U272 : NAND2_X1 port map( A1 => n149, A2 => n124, ZN => n58);
U273 : NAND2_X1 port map( A1 => sum_out_23_port, A2 => n124, ZN => n64);
U274 : NAND2_X1 port map( A1 => sum_out_30_port, A2 => n124, ZN => n40);
U275 : AOI222_X1 port map( A1 => n185, A2 => n124, B1 => n122, B2 =>
shift_out_31_port, C1 => n121, C2 =>
mult_out_31_port, ZN => n38);
U276 : AOI22_X1 port map( A1 => n187, A2 => lu_out_9_port, B1 => n123, B2 =>
n176, ZN => n13);
U277 : NAND2_X1 port map( A1 => n150, A2 => n124, ZN => n61);
U278 : AOI22_X1 port map( A1 => n187, A2 => lu_out_5_port, B1 => n123, B2 =>
n183, ZN => n30);
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity mux21_0 is
port( IN0, IN1 : in std_logic_vector (31 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (31 downto 0));
end mux21_0;
architecture SYN_Bhe of mux21_0 is
component MUX2_X1
port( A, B, S : in std_logic; Z : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component MUX2_X2
port( A, B, S : in std_logic; Z : out std_logic);
end component;
signal n4, n5, n6, n7, n8, n9, n10, n11, n12 : std_logic;
begin
U5 : MUX2_X1 port map( A => IN0(5), B => IN1(5), S => CTRL, Z => OUT1(5));
U6 : MUX2_X1 port map( A => IN0(4), B => IN1(4), S => CTRL, Z => OUT1(4));
U8 : MUX2_X1 port map( A => IN0(31), B => IN1(31), S => CTRL, Z => OUT1(31))
;
U9 : MUX2_X1 port map( A => IN0(30), B => IN1(30), S => CTRL, Z => OUT1(30))
;
U11 : MUX2_X1 port map( A => IN0(29), B => IN1(29), S => CTRL, Z => OUT1(29)
);
U13 : MUX2_X1 port map( A => IN0(27), B => IN1(27), S => CTRL, Z => OUT1(27)
);
U14 : MUX2_X1 port map( A => IN0(26), B => IN1(26), S => CTRL, Z => OUT1(26)
);
U15 : MUX2_X1 port map( A => IN0(25), B => IN1(25), S => CTRL, Z => OUT1(25)
);
U16 : MUX2_X1 port map( A => IN0(24), B => IN1(24), S => CTRL, Z => OUT1(24)
);
U20 : MUX2_X1 port map( A => IN0(20), B => IN1(20), S => CTRL, Z => OUT1(20)
);
U23 : MUX2_X1 port map( A => IN0(18), B => IN1(18), S => CTRL, Z => OUT1(18)
);
U1 : MUX2_X1 port map( A => IN0(16), B => IN1(16), S => CTRL, Z => OUT1(16))
;
U2 : MUX2_X1 port map( A => IN0(22), B => IN1(22), S => CTRL, Z => OUT1(22))
;
U3 : MUX2_X2 port map( A => IN0(23), B => IN1(23), S => CTRL, Z => OUT1(23))
;
U4 : MUX2_X2 port map( A => IN0(13), B => IN1(13), S => CTRL, Z => OUT1(13))
;
U7 : MUX2_X2 port map( A => IN0(14), B => IN1(14), S => CTRL, Z => OUT1(14))
;
U10 : MUX2_X1 port map( A => IN0(17), B => IN1(17), S => CTRL, Z => OUT1(17)
);
U12 : MUX2_X1 port map( A => IN0(15), B => IN1(15), S => CTRL, Z => OUT1(15)
);
U17 : MUX2_X1 port map( A => IN0(10), B => IN1(10), S => CTRL, Z => OUT1(10)
);
U18 : MUX2_X1 port map( A => IN0(8), B => IN1(8), S => CTRL, Z => OUT1(8));
U19 : MUX2_X1 port map( A => IN0(19), B => IN1(19), S => CTRL, Z => OUT1(19)
);
U21 : INV_X1 port map( A => CTRL, ZN => n4);
U22 : NAND2_X1 port map( A1 => n5, A2 => n6, ZN => OUT1(0));
U24 : NAND2_X1 port map( A1 => CTRL, A2 => IN1(0), ZN => n6);
U25 : NAND2_X1 port map( A1 => IN0(0), A2 => n4, ZN => n5);
U26 : NAND2_X1 port map( A1 => IN0(3), A2 => n4, ZN => n7);
U27 : NAND2_X1 port map( A1 => CTRL, A2 => IN1(3), ZN => n8);
U28 : NAND2_X1 port map( A1 => n7, A2 => n8, ZN => OUT1(3));
U29 : NAND2_X1 port map( A1 => n9, A2 => n10, ZN => OUT1(2));
U30 : MUX2_X1 port map( A => IN0(28), B => IN1(28), S => CTRL, Z => OUT1(28)
);
U31 : MUX2_X1 port map( A => IN0(21), B => IN1(21), S => CTRL, Z => OUT1(21)
);
U32 : NAND2_X1 port map( A1 => CTRL, A2 => IN1(2), ZN => n10);
U33 : NAND2_X1 port map( A1 => IN0(2), A2 => n4, ZN => n9);
U34 : MUX2_X1 port map( A => IN0(12), B => IN1(12), S => CTRL, Z => OUT1(12)
);
U35 : MUX2_X1 port map( A => IN0(7), B => IN1(7), S => CTRL, Z => OUT1(7));
U36 : NAND2_X1 port map( A1 => n11, A2 => n12, ZN => OUT1(6));
U37 : MUX2_X1 port map( A => IN0(11), B => IN1(11), S => CTRL, Z => OUT1(11)
);
U38 : MUX2_X1 port map( A => IN0(9), B => IN1(9), S => CTRL, Z => OUT1(9));
U39 : NAND2_X1 port map( A1 => IN0(6), A2 => n4, ZN => n11);
U40 : NAND2_X1 port map( A1 => IN1(6), A2 => CTRL, ZN => n12);
U41 : MUX2_X1 port map( A => IN0(1), B => IN1(1), S => CTRL, Z => OUT1(1));
end SYN_Bhe;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_execute_block.all;
entity execute_block is
port( IMM_i, A_i : in std_logic_vector (31 downto 0); rB_i, rC_i : in
std_logic_vector (4 downto 0); MUXED_B_i : in std_logic_vector (31
downto 0); S_MUX_ALUIN_i : in std_logic; FW_X_i, FW_W_i : in
std_logic_vector (31 downto 0); S_FW_A_i, S_FW_B_i : in
std_logic_vector (1 downto 0); muxed_dest : out std_logic_vector (4
downto 0); muxed_B : out std_logic_vector (31 downto 0);
S_MUX_DEST_i : in std_logic_vector (1 downto 0); OP : in aluOp;
ALUW_i : in std_logic_vector (12 downto 0); DOUT : out
std_logic_vector (31 downto 0); stall_o : out std_logic; Clock,
Reset : in std_logic);
end execute_block;
architecture SYN_struct of execute_block is
component mux41_MUX_SIZE32_1
port( IN0, IN1, IN2, IN3 : in std_logic_vector (31 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (31
downto 0));
end component;
component mux41_MUX_SIZE32_0
port( IN0, IN1, IN2, IN3 : in std_logic_vector (31 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (31
downto 0));
end component;
component mux41_MUX_SIZE5
port( IN0, IN1, IN2, IN3 : in std_logic_vector (4 downto 0); CTRL : in
std_logic_vector (1 downto 0); OUT1 : out std_logic_vector (4
downto 0));
end component;
component real_alu_DATA_SIZE32
port( IN1, IN2 : in std_logic_vector (31 downto 0); ALUW_i : in
std_logic_vector (12 downto 0); DOUT : out std_logic_vector (31
downto 0); stall_o : out std_logic; Clock, Reset : in std_logic);
end component;
component mux21_0
port( IN0, IN1 : in std_logic_vector (31 downto 0); CTRL : in std_logic;
OUT1 : out std_logic_vector (31 downto 0));
end component;
signal X_Logic1_port, X_Logic0_port, muxed_B_31_port, muxed_B_30_port,
muxed_B_29_port, muxed_B_28_port, muxed_B_27_port, muxed_B_25_port,
muxed_B_24_port, muxed_B_23_port, muxed_B_22_port, muxed_B_21_port,
muxed_B_20_port, muxed_B_19_port, muxed_B_18_port, muxed_B_16_port,
muxed_B_14_port, muxed_B_13_port, muxed_B_12_port, muxed_B_11_port,
muxed_B_10_port, muxed_B_9_port, muxed_B_8_port, muxed_B_7_port,
muxed_B_6_port, muxed_B_5_port, muxed_B_4_port, muxed_B_3_port,
muxed_B_2_port, muxed_B_1_port, muxed_B_0_port, FWB2alu_31_port,
FWB2alu_30_port, FWB2alu_29_port, FWB2alu_28_port, FWB2alu_27_port,
FWB2alu_26_port, FWB2alu_25_port, FWB2alu_24_port, FWB2alu_23_port,
FWB2alu_22_port, FWB2alu_21_port, FWB2alu_20_port, FWB2alu_19_port,
FWB2alu_18_port, FWB2alu_17_port, FWB2alu_16_port, FWB2alu_15_port,
FWB2alu_14_port, FWB2alu_13_port, FWB2alu_12_port, FWB2alu_11_port,
FWB2alu_10_port, FWB2alu_9_port, FWB2alu_8_port, FWB2alu_7_port,
FWB2alu_6_port, FWB2alu_5_port, FWB2alu_4_port, FWB2alu_3_port,
FWB2alu_2_port, FWB2alu_1_port, FWB2alu_0_port, FWA2alu_31_port,
FWA2alu_30_port, FWA2alu_29_port, FWA2alu_28_port, FWA2alu_27_port,
FWA2alu_26_port, FWA2alu_25_port, FWA2alu_24_port, FWA2alu_23_port,
FWA2alu_22_port, FWA2alu_21_port, FWA2alu_20_port, FWA2alu_19_port,
FWA2alu_18_port, FWA2alu_17_port, FWA2alu_16_port, FWA2alu_15_port,
FWA2alu_14_port, FWA2alu_13_port, FWA2alu_12_port, FWA2alu_11_port,
FWA2alu_10_port, FWA2alu_9_port, FWA2alu_8_port, FWA2alu_7_port,
FWA2alu_6_port, FWA2alu_5_port, FWA2alu_4_port, FWA2alu_3_port,
FWA2alu_2_port, FWA2alu_1_port, FWA2alu_0_port, net536481, net536482,
net536483, net536484, net536485, n1, muxed_B_15_port, muxed_B_17_port,
muxed_B_26_port : std_logic;
begin
muxed_B <= ( muxed_B_31_port, muxed_B_30_port, muxed_B_29_port,
muxed_B_28_port, muxed_B_27_port, muxed_B_26_port, muxed_B_25_port,
muxed_B_24_port, muxed_B_23_port, muxed_B_22_port, muxed_B_21_port,
muxed_B_20_port, muxed_B_19_port, muxed_B_18_port, muxed_B_17_port,
muxed_B_16_port, muxed_B_15_port, muxed_B_14_port, muxed_B_13_port,
muxed_B_12_port, muxed_B_11_port, muxed_B_10_port, muxed_B_9_port,
muxed_B_8_port, muxed_B_7_port, muxed_B_6_port, muxed_B_5_port,
muxed_B_4_port, muxed_B_3_port, muxed_B_2_port, muxed_B_1_port,
muxed_B_0_port );
(net536481, net536482, net536483, net536484, net536485) <=
aluOp_to_std_logic_vector(OP);
X_Logic1_port <= '1';
X_Logic0_port <= '0';
n1 <= '0';
ALUIN_MUX : mux21_0 port map( IN0(31) => muxed_B_31_port, IN0(30) =>
muxed_B_30_port, IN0(29) => muxed_B_29_port, IN0(28)
=> muxed_B_28_port, IN0(27) => muxed_B_27_port,
IN0(26) => muxed_B_26_port, IN0(25) =>
muxed_B_25_port, IN0(24) => muxed_B_24_port, IN0(23)
=> muxed_B_23_port, IN0(22) => muxed_B_22_port,
IN0(21) => muxed_B_21_port, IN0(20) =>
muxed_B_20_port, IN0(19) => muxed_B_19_port, IN0(18)
=> muxed_B_18_port, IN0(17) => muxed_B_17_port,
IN0(16) => muxed_B_16_port, IN0(15) =>
muxed_B_15_port, IN0(14) => muxed_B_14_port, IN0(13)
=> muxed_B_13_port, IN0(12) => muxed_B_12_port,
IN0(11) => muxed_B_11_port, IN0(10) =>
muxed_B_10_port, IN0(9) => muxed_B_9_port, IN0(8) =>
muxed_B_8_port, IN0(7) => muxed_B_7_port, IN0(6) =>
muxed_B_6_port, IN0(5) => muxed_B_5_port, IN0(4) =>
muxed_B_4_port, IN0(3) => muxed_B_3_port, IN0(2) =>
muxed_B_2_port, IN0(1) => muxed_B_1_port, IN0(0) =>
muxed_B_0_port, IN1(31) => IMM_i(31), IN1(30) =>
IMM_i(30), IN1(29) => IMM_i(29), IN1(28) =>
IMM_i(28), IN1(27) => IMM_i(27), IN1(26) =>
IMM_i(26), IN1(25) => IMM_i(25), IN1(24) =>
IMM_i(24), IN1(23) => IMM_i(23), IN1(22) =>
IMM_i(22), IN1(21) => IMM_i(21), IN1(20) =>
IMM_i(20), IN1(19) => IMM_i(19), IN1(18) =>
IMM_i(18), IN1(17) => IMM_i(17), IN1(16) =>
IMM_i(16), IN1(15) => IMM_i(15), IN1(14) =>
IMM_i(14), IN1(13) => IMM_i(13), IN1(12) =>
IMM_i(12), IN1(11) => IMM_i(11), IN1(10) =>
IMM_i(10), IN1(9) => IMM_i(9), IN1(8) => IMM_i(8),
IN1(7) => IMM_i(7), IN1(6) => IMM_i(6), IN1(5) =>
IMM_i(5), IN1(4) => IMM_i(4), IN1(3) => IMM_i(3),
IN1(2) => IMM_i(2), IN1(1) => IMM_i(1), IN1(0) =>
IMM_i(0), CTRL => S_MUX_ALUIN_i, OUT1(31) =>
FWB2alu_31_port, OUT1(30) => FWB2alu_30_port,
OUT1(29) => FWB2alu_29_port, OUT1(28) =>
FWB2alu_28_port, OUT1(27) => FWB2alu_27_port,
OUT1(26) => FWB2alu_26_port, OUT1(25) =>
FWB2alu_25_port, OUT1(24) => FWB2alu_24_port,
OUT1(23) => FWB2alu_23_port, OUT1(22) =>
FWB2alu_22_port, OUT1(21) => FWB2alu_21_port,
OUT1(20) => FWB2alu_20_port, OUT1(19) =>
FWB2alu_19_port, OUT1(18) => FWB2alu_18_port,
OUT1(17) => FWB2alu_17_port, OUT1(16) =>
FWB2alu_16_port, OUT1(15) => FWB2alu_15_port,
OUT1(14) => FWB2alu_14_port, OUT1(13) =>
FWB2alu_13_port, OUT1(12) => FWB2alu_12_port,
OUT1(11) => FWB2alu_11_port, OUT1(10) =>
FWB2alu_10_port, OUT1(9) => FWB2alu_9_port, OUT1(8)
=> FWB2alu_8_port, OUT1(7) => FWB2alu_7_port,
OUT1(6) => FWB2alu_6_port, OUT1(5) => FWB2alu_5_port
, OUT1(4) => FWB2alu_4_port, OUT1(3) =>
FWB2alu_3_port, OUT1(2) => FWB2alu_2_port, OUT1(1)
=> FWB2alu_1_port, OUT1(0) => FWB2alu_0_port);
ALU : real_alu_DATA_SIZE32 port map( IN1(31) => FWA2alu_31_port, IN1(30) =>
FWA2alu_30_port, IN1(29) => FWA2alu_29_port, IN1(28)
=> FWA2alu_28_port, IN1(27) => FWA2alu_27_port,
IN1(26) => FWA2alu_26_port, IN1(25) =>
FWA2alu_25_port, IN1(24) => FWA2alu_24_port, IN1(23)
=> FWA2alu_23_port, IN1(22) => FWA2alu_22_port,
IN1(21) => FWA2alu_21_port, IN1(20) =>
FWA2alu_20_port, IN1(19) => FWA2alu_19_port, IN1(18)
=> FWA2alu_18_port, IN1(17) => FWA2alu_17_port,
IN1(16) => FWA2alu_16_port, IN1(15) =>
FWA2alu_15_port, IN1(14) => FWA2alu_14_port, IN1(13)
=> FWA2alu_13_port, IN1(12) => FWA2alu_12_port,
IN1(11) => FWA2alu_11_port, IN1(10) =>
FWA2alu_10_port, IN1(9) => FWA2alu_9_port, IN1(8) =>
FWA2alu_8_port, IN1(7) => FWA2alu_7_port, IN1(6) =>
FWA2alu_6_port, IN1(5) => FWA2alu_5_port, IN1(4) =>
FWA2alu_4_port, IN1(3) => FWA2alu_3_port, IN1(2) =>
FWA2alu_2_port, IN1(1) => FWA2alu_1_port, IN1(0) =>
FWA2alu_0_port, IN2(31) => FWB2alu_31_port, IN2(30)
=> FWB2alu_30_port, IN2(29) => FWB2alu_29_port,
IN2(28) => FWB2alu_28_port, IN2(27) =>
FWB2alu_27_port, IN2(26) => FWB2alu_26_port, IN2(25)
=> FWB2alu_25_port, IN2(24) => FWB2alu_24_port,
IN2(23) => FWB2alu_23_port, IN2(22) =>
FWB2alu_22_port, IN2(21) => FWB2alu_21_port, IN2(20)
=> FWB2alu_20_port, IN2(19) => FWB2alu_19_port,
IN2(18) => FWB2alu_18_port, IN2(17) =>
FWB2alu_17_port, IN2(16) => FWB2alu_16_port, IN2(15)
=> FWB2alu_15_port, IN2(14) => FWB2alu_14_port,
IN2(13) => FWB2alu_13_port, IN2(12) =>
FWB2alu_12_port, IN2(11) => FWB2alu_11_port, IN2(10)
=> FWB2alu_10_port, IN2(9) => FWB2alu_9_port, IN2(8)
=> FWB2alu_8_port, IN2(7) => FWB2alu_7_port, IN2(6)
=> FWB2alu_6_port, IN2(5) => FWB2alu_5_port, IN2(4)
=> FWB2alu_4_port, IN2(3) => FWB2alu_3_port, IN2(2)
=> FWB2alu_2_port, IN2(1) => FWB2alu_1_port, IN2(0)
=> FWB2alu_0_port, ALUW_i(12) => ALUW_i(12),
ALUW_i(11) => ALUW_i(11), ALUW_i(10) => ALUW_i(10),
ALUW_i(9) => ALUW_i(9), ALUW_i(8) => ALUW_i(8),
ALUW_i(7) => ALUW_i(7), ALUW_i(6) => ALUW_i(6),
ALUW_i(5) => ALUW_i(5), ALUW_i(4) => ALUW_i(4),
ALUW_i(3) => ALUW_i(3), ALUW_i(2) => ALUW_i(2),
ALUW_i(1) => ALUW_i(1), ALUW_i(0) => ALUW_i(0),
DOUT(31) => DOUT(31), DOUT(30) => DOUT(30), DOUT(29)
=> DOUT(29), DOUT(28) => DOUT(28), DOUT(27) =>
DOUT(27), DOUT(26) => DOUT(26), DOUT(25) => DOUT(25)
, DOUT(24) => DOUT(24), DOUT(23) => DOUT(23),
DOUT(22) => DOUT(22), DOUT(21) => DOUT(21), DOUT(20)
=> DOUT(20), DOUT(19) => DOUT(19), DOUT(18) =>
DOUT(18), DOUT(17) => DOUT(17), DOUT(16) => DOUT(16)
, DOUT(15) => DOUT(15), DOUT(14) => DOUT(14),
DOUT(13) => DOUT(13), DOUT(12) => DOUT(12), DOUT(11)
=> DOUT(11), DOUT(10) => DOUT(10), DOUT(9) =>
DOUT(9), DOUT(8) => DOUT(8), DOUT(7) => DOUT(7),
DOUT(6) => DOUT(6), DOUT(5) => DOUT(5), DOUT(4) =>
DOUT(4), DOUT(3) => DOUT(3), DOUT(2) => DOUT(2),
DOUT(1) => DOUT(1), DOUT(0) => DOUT(0), stall_o =>
stall_o, Clock => Clock, Reset => Reset);
MUXDEST : mux41_MUX_SIZE5 port map( IN0(4) => X_Logic0_port, IN0(3) =>
X_Logic0_port, IN0(2) => X_Logic0_port, IN0(1) =>
X_Logic0_port, IN0(0) => X_Logic0_port, IN1(4) =>
rC_i(4), IN1(3) => rC_i(3), IN1(2) => rC_i(2),
IN1(1) => rC_i(1), IN1(0) => rC_i(0), IN2(4) =>
rB_i(4), IN2(3) => rB_i(3), IN2(2) => rB_i(2),
IN2(1) => rB_i(1), IN2(0) => rB_i(0), IN3(4) =>
X_Logic1_port, IN3(3) => X_Logic1_port, IN3(2) =>
X_Logic1_port, IN3(1) => X_Logic1_port, IN3(0) =>
X_Logic1_port, CTRL(1) => S_MUX_DEST_i(1), CTRL(0)
=> S_MUX_DEST_i(0), OUT1(4) => muxed_dest(4),
OUT1(3) => muxed_dest(3), OUT1(2) => muxed_dest(2),
OUT1(1) => muxed_dest(1), OUT1(0) => muxed_dest(0));
MUX_FWA : mux41_MUX_SIZE32_0 port map( IN0(31) => A_i(31), IN0(30) =>
A_i(30), IN0(29) => A_i(29), IN0(28) => A_i(28),
IN0(27) => A_i(27), IN0(26) => A_i(26), IN0(25) =>
A_i(25), IN0(24) => A_i(24), IN0(23) => A_i(23),
IN0(22) => A_i(22), IN0(21) => A_i(21), IN0(20) =>
A_i(20), IN0(19) => A_i(19), IN0(18) => A_i(18),
IN0(17) => A_i(17), IN0(16) => A_i(16), IN0(15) =>
A_i(15), IN0(14) => A_i(14), IN0(13) => A_i(13),
IN0(12) => A_i(12), IN0(11) => A_i(11), IN0(10) =>
A_i(10), IN0(9) => A_i(9), IN0(8) => A_i(8), IN0(7)
=> A_i(7), IN0(6) => A_i(6), IN0(5) => A_i(5),
IN0(4) => A_i(4), IN0(3) => A_i(3), IN0(2) => A_i(2)
, IN0(1) => A_i(1), IN0(0) => A_i(0), IN1(31) =>
FW_X_i(31), IN1(30) => FW_X_i(30), IN1(29) =>
FW_X_i(29), IN1(28) => FW_X_i(28), IN1(27) =>
FW_X_i(27), IN1(26) => FW_X_i(26), IN1(25) =>
FW_X_i(25), IN1(24) => FW_X_i(24), IN1(23) =>
FW_X_i(23), IN1(22) => FW_X_i(22), IN1(21) =>
FW_X_i(21), IN1(20) => FW_X_i(20), IN1(19) =>
FW_X_i(19), IN1(18) => FW_X_i(18), IN1(17) =>
FW_X_i(17), IN1(16) => FW_X_i(16), IN1(15) =>
FW_X_i(15), IN1(14) => FW_X_i(14), IN1(13) =>
FW_X_i(13), IN1(12) => FW_X_i(12), IN1(11) =>
FW_X_i(11), IN1(10) => FW_X_i(10), IN1(9) =>
FW_X_i(9), IN1(8) => FW_X_i(8), IN1(7) => FW_X_i(7),
IN1(6) => FW_X_i(6), IN1(5) => FW_X_i(5), IN1(4) =>
FW_X_i(4), IN1(3) => FW_X_i(3), IN1(2) => FW_X_i(2),
IN1(1) => FW_X_i(1), IN1(0) => FW_X_i(0), IN2(31) =>
FW_W_i(31), IN2(30) => FW_W_i(30), IN2(29) =>
FW_W_i(29), IN2(28) => FW_W_i(28), IN2(27) =>
FW_W_i(27), IN2(26) => FW_W_i(26), IN2(25) =>
FW_W_i(25), IN2(24) => FW_W_i(24), IN2(23) =>
FW_W_i(23), IN2(22) => FW_W_i(22), IN2(21) =>
FW_W_i(21), IN2(20) => FW_W_i(20), IN2(19) =>
FW_W_i(19), IN2(18) => FW_W_i(18), IN2(17) =>
FW_W_i(17), IN2(16) => FW_W_i(16), IN2(15) =>
FW_W_i(15), IN2(14) => FW_W_i(14), IN2(13) =>
FW_W_i(13), IN2(12) => FW_W_i(12), IN2(11) =>
FW_W_i(11), IN2(10) => FW_W_i(10), IN2(9) =>
FW_W_i(9), IN2(8) => FW_W_i(8), IN2(7) => FW_W_i(7),
IN2(6) => FW_W_i(6), IN2(5) => FW_W_i(5), IN2(4) =>
FW_W_i(4), IN2(3) => FW_W_i(3), IN2(2) => FW_W_i(2),
IN2(1) => FW_W_i(1), IN2(0) => FW_W_i(0), IN3(31) =>
n1, IN3(30) => n1, IN3(29) => n1, IN3(28) => n1,
IN3(27) => n1, IN3(26) => n1, IN3(25) => n1, IN3(24)
=> n1, IN3(23) => n1, IN3(22) => n1, IN3(21) => n1,
IN3(20) => n1, IN3(19) => n1, IN3(18) => n1, IN3(17)
=> n1, IN3(16) => n1, IN3(15) => n1, IN3(14) => n1,
IN3(13) => n1, IN3(12) => n1, IN3(11) => n1, IN3(10)
=> n1, IN3(9) => n1, IN3(8) => n1, IN3(7) => n1,
IN3(6) => n1, IN3(5) => n1, IN3(4) => n1, IN3(3) =>
n1, IN3(2) => n1, IN3(1) => n1, IN3(0) => n1,
CTRL(1) => S_FW_A_i(1), CTRL(0) => S_FW_A_i(0),
OUT1(31) => FWA2alu_31_port, OUT1(30) =>
FWA2alu_30_port, OUT1(29) => FWA2alu_29_port,
OUT1(28) => FWA2alu_28_port, OUT1(27) =>
FWA2alu_27_port, OUT1(26) => FWA2alu_26_port,
OUT1(25) => FWA2alu_25_port, OUT1(24) =>
FWA2alu_24_port, OUT1(23) => FWA2alu_23_port,
OUT1(22) => FWA2alu_22_port, OUT1(21) =>
FWA2alu_21_port, OUT1(20) => FWA2alu_20_port,
OUT1(19) => FWA2alu_19_port, OUT1(18) =>
FWA2alu_18_port, OUT1(17) => FWA2alu_17_port,
OUT1(16) => FWA2alu_16_port, OUT1(15) =>
FWA2alu_15_port, OUT1(14) => FWA2alu_14_port,
OUT1(13) => FWA2alu_13_port, OUT1(12) =>
FWA2alu_12_port, OUT1(11) => FWA2alu_11_port,
OUT1(10) => FWA2alu_10_port, OUT1(9) =>
FWA2alu_9_port, OUT1(8) => FWA2alu_8_port, OUT1(7)
=> FWA2alu_7_port, OUT1(6) => FWA2alu_6_port,
OUT1(5) => FWA2alu_5_port, OUT1(4) => FWA2alu_4_port
, OUT1(3) => FWA2alu_3_port, OUT1(2) =>
FWA2alu_2_port, OUT1(1) => FWA2alu_1_port, OUT1(0)
=> FWA2alu_0_port);
MUX_FWB : mux41_MUX_SIZE32_1 port map( IN0(31) => MUXED_B_i(31), IN0(30) =>
MUXED_B_i(30), IN0(29) => MUXED_B_i(29), IN0(28) =>
MUXED_B_i(28), IN0(27) => MUXED_B_i(27), IN0(26) =>
MUXED_B_i(26), IN0(25) => MUXED_B_i(25), IN0(24) =>
MUXED_B_i(24), IN0(23) => MUXED_B_i(23), IN0(22) =>
MUXED_B_i(22), IN0(21) => MUXED_B_i(21), IN0(20) =>
MUXED_B_i(20), IN0(19) => MUXED_B_i(19), IN0(18) =>
MUXED_B_i(18), IN0(17) => MUXED_B_i(17), IN0(16) =>
MUXED_B_i(16), IN0(15) => MUXED_B_i(15), IN0(14) =>
MUXED_B_i(14), IN0(13) => MUXED_B_i(13), IN0(12) =>
MUXED_B_i(12), IN0(11) => MUXED_B_i(11), IN0(10) =>
MUXED_B_i(10), IN0(9) => MUXED_B_i(9), IN0(8) =>
MUXED_B_i(8), IN0(7) => MUXED_B_i(7), IN0(6) =>
MUXED_B_i(6), IN0(5) => MUXED_B_i(5), IN0(4) =>
MUXED_B_i(4), IN0(3) => MUXED_B_i(3), IN0(2) =>
MUXED_B_i(2), IN0(1) => MUXED_B_i(1), IN0(0) =>
MUXED_B_i(0), IN1(31) => FW_X_i(31), IN1(30) =>
FW_X_i(30), IN1(29) => FW_X_i(29), IN1(28) =>
FW_X_i(28), IN1(27) => FW_X_i(27), IN1(26) =>
FW_X_i(26), IN1(25) => FW_X_i(25), IN1(24) =>
FW_X_i(24), IN1(23) => FW_X_i(23), IN1(22) =>
FW_X_i(22), IN1(21) => FW_X_i(21), IN1(20) =>
FW_X_i(20), IN1(19) => FW_X_i(19), IN1(18) =>
FW_X_i(18), IN1(17) => FW_X_i(17), IN1(16) =>
FW_X_i(16), IN1(15) => FW_X_i(15), IN1(14) =>
FW_X_i(14), IN1(13) => FW_X_i(13), IN1(12) =>
FW_X_i(12), IN1(11) => FW_X_i(11), IN1(10) =>
FW_X_i(10), IN1(9) => FW_X_i(9), IN1(8) => FW_X_i(8)
, IN1(7) => FW_X_i(7), IN1(6) => FW_X_i(6), IN1(5)
=> FW_X_i(5), IN1(4) => FW_X_i(4), IN1(3) =>
FW_X_i(3), IN1(2) => FW_X_i(2), IN1(1) => FW_X_i(1),
IN1(0) => FW_X_i(0), IN2(31) => FW_W_i(31), IN2(30)
=> FW_W_i(30), IN2(29) => FW_W_i(29), IN2(28) =>
FW_W_i(28), IN2(27) => FW_W_i(27), IN2(26) =>
FW_W_i(26), IN2(25) => FW_W_i(25), IN2(24) =>
FW_W_i(24), IN2(23) => FW_W_i(23), IN2(22) =>
FW_W_i(22), IN2(21) => FW_W_i(21), IN2(20) =>
FW_W_i(20), IN2(19) => FW_W_i(19), IN2(18) =>
FW_W_i(18), IN2(17) => FW_W_i(17), IN2(16) =>
FW_W_i(16), IN2(15) => FW_W_i(15), IN2(14) =>
FW_W_i(14), IN2(13) => FW_W_i(13), IN2(12) =>
FW_W_i(12), IN2(11) => FW_W_i(11), IN2(10) =>
FW_W_i(10), IN2(9) => FW_W_i(9), IN2(8) => FW_W_i(8)
, IN2(7) => FW_W_i(7), IN2(6) => FW_W_i(6), IN2(5)
=> FW_W_i(5), IN2(4) => FW_W_i(4), IN2(3) =>
FW_W_i(3), IN2(2) => FW_W_i(2), IN2(1) => FW_W_i(1),
IN2(0) => FW_W_i(0), IN3(31) => n1, IN3(30) => n1,
IN3(29) => n1, IN3(28) => n1, IN3(27) => n1, IN3(26)
=> n1, IN3(25) => n1, IN3(24) => n1, IN3(23) => n1,
IN3(22) => n1, IN3(21) => n1, IN3(20) => n1, IN3(19)
=> n1, IN3(18) => n1, IN3(17) => n1, IN3(16) => n1,
IN3(15) => n1, IN3(14) => n1, IN3(13) => n1, IN3(12)
=> n1, IN3(11) => n1, IN3(10) => n1, IN3(9) => n1,
IN3(8) => n1, IN3(7) => n1, IN3(6) => n1, IN3(5) =>
n1, IN3(4) => n1, IN3(3) => n1, IN3(2) => n1, IN3(1)
=> n1, IN3(0) => n1, CTRL(1) => S_FW_B_i(1), CTRL(0)
=> S_FW_B_i(0), OUT1(31) => muxed_B_31_port,
OUT1(30) => muxed_B_30_port, OUT1(29) =>
muxed_B_29_port, OUT1(28) => muxed_B_28_port,
OUT1(27) => muxed_B_27_port, OUT1(26) =>
muxed_B_26_port, OUT1(25) => muxed_B_25_port,
OUT1(24) => muxed_B_24_port, OUT1(23) =>
muxed_B_23_port, OUT1(22) => muxed_B_22_port,
OUT1(21) => muxed_B_21_port, OUT1(20) =>
muxed_B_20_port, OUT1(19) => muxed_B_19_port,
OUT1(18) => muxed_B_18_port, OUT1(17) =>
muxed_B_17_port, OUT1(16) => muxed_B_16_port,
OUT1(15) => muxed_B_15_port, OUT1(14) =>
muxed_B_14_port, OUT1(13) => muxed_B_13_port,
OUT1(12) => muxed_B_12_port, OUT1(11) =>
muxed_B_11_port, OUT1(10) => muxed_B_10_port,
OUT1(9) => muxed_B_9_port, OUT1(8) => muxed_B_8_port
, OUT1(7) => muxed_B_7_port, OUT1(6) =>
muxed_B_6_port, OUT1(5) => muxed_B_5_port, OUT1(4)
=> muxed_B_4_port, OUT1(3) => muxed_B_3_port,
OUT1(2) => muxed_B_2_port, OUT1(1) => muxed_B_1_port
, OUT1(0) => muxed_B_0_port);
end SYN_struct;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 00:52:18 04/10/2009
-- Design Name:
-- Module Name: Gate_Xor - Behavioral
-- Project Name: XOR Gate
-- Target Devices:
-- Tool versions:
-- Description: An XOR logic gate with two inputs
--
-- Dependencies: None
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Gate_Xor is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Q : out STD_LOGIC);
end Gate_Xor;
architecture Behavioral of Gate_Xor is
begin
Q <= (A xor B);
end Behavioral;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: BusPLL.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.0 Build 156 04/24/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY BusPLL IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC
);
END BusPLL;
ARCHITECTURE SYN OF buspll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire2 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c0 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 5,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
lpm_hint => "CBX_MODULE_PREFIX=BusPLL",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED"
)
PORT MAP (
areset => areset,
inclk => sub_wire4,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "BusPLL.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: GEN_FILE: TYPE_NORMAL BusPLL.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BusPLL.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BusPLL.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BusPLL.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BusPLL.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BusPLL_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
ENTITY pong IS
PORT(
clock : IN STD_LOGIC;
-- Puertos VGA
vga_red : OUT STD_LOGIC;
vga_green : OUT STD_LOGIC;
vga_blue : OUT STD_LOGIC;
vga_blank : OUT STD_LOGIC;
vga_hs : OUT STD_LOGIC;
vga_vs : OUT STD_LOGIC;
vga_clk : OUT STD_LOGIC;
-- Controles de juego
btn_up1 : IN STD_LOGIC;
btn_down1 : IN STD_LOGIC;
btn_up2 : IN STD_LOGIC;
btn_down2 : IN STD_LOGIC;
-- Marcados de 7 segmentos
hex00 : OUT STD_LOGIC;
hex01 : OUT STD_LOGIC;
hex02 : OUT STD_LOGIC;
hex03 : OUT STD_LOGIC;
hex04 : OUT STD_LOGIC;
hex05 : OUT STD_LOGIC;
hex06 : OUT STD_LOGIC;
hex20 : OUT STD_LOGIC;
hex21 : OUT STD_LOGIC;
hex22 : OUT STD_LOGIC;
hex23 : OUT STD_LOGIC;
hex24 : OUT STD_LOGIC;
hex25 : OUT STD_LOGIC;
hex26 : OUT STD_LOGIC
);
END pong;
ARCHITECTURE funcional OF pong IS
-- Escenario
COMPONENT escenario
PORT (
vert_sync : IN STD_LOGIC;
pixel_row : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
pixel_column : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
Red : OUT STD_LOGIC;
Green : OUT STD_LOGIC;
Blue : OUT STD_LOGIC;
-- Controles del juego
btn_up1 : IN STD_LOGIC;
btn_down1 : IN STD_LOGIC;
btn_up2 : IN STD_LOGIC;
btn_down2 : IN STD_LOGIC;
-- Marcados de 7 segmentos
hex00 : OUT STD_LOGIC;
hex01 : OUT STD_LOGIC;
hex02 : OUT STD_LOGIC;
hex03 : OUT STD_LOGIC;
hex04 : OUT STD_LOGIC;
hex05 : OUT STD_LOGIC;
hex06 : OUT STD_LOGIC;
hex20 : OUT STD_LOGIC;
hex21 : OUT STD_LOGIC;
hex22 : OUT STD_LOGIC;
hex23 : OUT STD_LOGIC;
hex24 : OUT STD_LOGIC;
hex25 : OUT STD_LOGIC;
hex26 : OUT STD_LOGIC
);
END COMPONENT;
-- PLL para adaptar reloj (50 MHz -> 25 MHz)
COMPONENT vga_PLL
PORT(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END COMPONENT;
-- Controlador de VGA
COMPONENT vga_sync
PORT(
clock_25Mhz : IN STD_LOGIC;
red : IN STD_LOGIC;
green : IN STD_LOGIC;
blue : IN STD_LOGIC;
vga_red : OUT STD_LOGIC;
vga_green : OUT STD_LOGIC;
vga_blue : OUT STD_LOGIC;
vga_blank : OUT STD_LOGIC;
vga_hs : OUT STD_LOGIC;
vga_vs : OUT STD_LOGIC;
vga_clk : OUT STD_LOGIC;
pixel_row : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
pixel_column : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
-- Variables
SIGNAL clock_25MHz : STD_LOGIC;
SIGNAL Red_Data : STD_LOGIC;
SIGNAL Green_Data : STD_LOGIC;
SIGNAL Blue_Data : STD_LOGIC;
SIGNAL vert_sync : STD_LOGIC;
SIGNAL pixel_col : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL pixel_row : STD_LOGIC_VECTOR(9 DOWNTO 0);
BEGIN
vga_vs <= vert_sync;
-- Conexión de componentes
PLL: vga_pll PORT MAP (
inclk0 => clock,
c0 => clock_25Mhz
);
SYNC: VGA_SYNC PORT MAP (
clock_25Mhz => clock_25MHz,
red => red_data,
green => green_data,
blue => blue_data,
vga_red => vga_red,
vga_green => vga_green,
vga_blue => vga_blue,
vga_blank => vga_blank,
vga_hs => vga_hs,
vga_vs => vert_sync,
vga_clk => vga_clk,
pixel_row => pixel_row,
pixel_column => pixel_col
);
ESCE: escenario PORT MAP (
Red => red_data,
Green => green_data,
Blue => blue_data,
vert_sync => vert_sync,
pixel_row => pixel_row,
pixel_column => pixel_col,
btn_up1 => btn_up1,
btn_down1 => btn_down1,
btn_up2 => btn_up2,
btn_down2 => btn_down2,
hex00 => hex00,
hex01 => hex01,
hex02 => hex02,
hex03 => hex03,
hex04 => hex04,
hex05 => hex05,
hex06 => hex06,
hex20 => hex20,
hex21 => hex21,
hex22 => hex22,
hex23 => hex23,
hex24 => hex24,
hex25 => hex25,
hex26 => hex26
);
END funcional; |
--
-- (C) Alvaro Lopes <[email protected]> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end entity;
architecture beh of sid_filters is
alias filt: std_logic_vector(3 downto 0) is Res_Filt(3 downto 0);
alias res: std_logic_vector(3 downto 0) is Res_Filt(7 downto 4);
alias voice3off: std_logic is Mode_Vol(7);
alias volume: std_logic_vector(3 downto 0) is Mode_Vol(3 downto 0);
alias hp_bp_lp: std_logic_vector(2 downto 0) is Mode_Vol(6 downto 4);
constant mixer_DC: integer := -475; -- NOTE to self: this might be wrong.
component sid_coeffs is
port (
clk: in std_logic;
addr: in integer range 0 to 2047;
val: out std_logic_vector(15 downto 0)
);
end component;
type regs_type is record
Vhp: signed(17 downto 0);
Vbp: signed(17 downto 0);
dVbp: signed(17 downto 0);
Vlp: signed(17 downto 0);
dVlp: signed(17 downto 0);
Vi: signed(17 downto 0);
Vnf: signed(17 downto 0);
Vf: signed(17 downto 0);
w0: signed(17 downto 0);
q: signed(17 downto 0);
vout:signed(18 downto 0);
state: integer;
done: std_logic;
end record;
signal dVhp_debug: signed(31 downto 0);
signal dVbp_debug: signed(31 downto 0);
signal addr: integer range 0 to 2047;
signal val: std_logic_vector(15 downto 0);
type divmul_t is array(0 to 15) of integer;
constant divmul: divmul_t := (
1448, 1323, 1218, 1128, 1051, 984, 925, 872, 825, 783, 745, 710, 679, 650, 624, 599
);
signal r: regs_type;
signal mula: signed(17 downto 0);
signal mulb: signed(17 downto 0);
signal mulr: signed(35 downto 0);
signal mulen: std_logic;
function s13_to_18(a: in signed(12 downto 0)) return signed is
variable r: signed(17 downto 0);
begin
r(12 downto 0):=a;
r(13):=a(12);
r(14):=a(12);
r(15):=a(12);
r(16):=a(12);
r(17):=a(12);
return r;
end function;
-- Debugging
signal dbg_Vlp, dbg_Vhp, dbg_Vbp: signed(17 downto 0);
signal fc: std_logic_vector(10 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if mulen='1' then
mulr <= mula * mulb;
end if;
end if;
end process;
fc <= Fc_hi & Fc_lo(2 downto 0);
c: sid_coeffs
port map (
clk => clk,
addr => addr,
val => val
);
addr <= to_integer(unsigned(fc));
process(clk, rst, r, input_valid, val, filt, voice1, voice2, voice3, voice3off, mulr, ext_in, hp_bp_lp, Mode_Vol)
variable w: regs_type;
begin
w:=r;
mula <= (others => 'X');
mulb <= (others => 'X');
mulen <= '0';
case r.state is
when 0 =>
w.done := '0';
if input_valid = '1' then
w.state := 1;
-- Reset Vin, Vnf
w.vi := (others => '0');
w.vnf := (others => '0');
end if;
when 1 =>
-- already have W0 ready. Always positive
w.w0 := "00" & signed(val);
-- 1st accumulation
if filt(0)='1' then
w.vi := r.vi + s13_to_18(voice1);
else
w.vnf := r.vnf + s13_to_18(voice1);
end if;
w.state := 2;
when 2 =>
-- 2nd accumulation
if filt(1)='1' then
w.vi := r.vi + s13_to_18(voice2);
else
w.vnf := r.vnf + s13_to_18(voice2);
end if;
-- Mult
mula <= r.w0;
mulb <= r.vhp;
mulen <= '1';
w.state := 3;
when 3 =>
-- 3rd accumulation
if filt(2)='1' then
w.vi := r.vi + s13_to_18(voice3);
else
if voice3off='0' then
w.vnf := r.vnf + s13_to_18(voice3);
end if;
end if;
-- Mult
mula <= r.w0;
mulb <= r.vbp;
mulen <= '1';
w.dVbp := mulr(35) & mulr(35 downto 19);
w.state := 4;
when 4 =>
-- 4th accumulation
if filt(3)='1' then
w.vi := r.vi + s13_to_18(ext_in);
else
w.vnf := r.vnf + s13_to_18(ext_in);
end if;
w.dVlp := mulr(35) & mulr(35 downto 19);
w.Vbp := r.Vbp - r.dVbp;
-- Get Q, synchronous.
w.q := to_signed(divmul(to_integer(unsigned(res))), 18);
w.state := 5;
when 5 =>
-- Ok, we have all summed. We performed multiplications for dVbp and dVlp.
-- new Vbp already computed.
mulen <= '1';
mula <= r.q;
mulb <= r.Vbp;
w.vlp := r.Vlp - r.dVlp;
-- Start computing output;
if hp_bp_lp(1)='1' then
w.Vf := r.Vbp;
else
w.Vf := (others => '0');
end if;
w.state := 6;
when 6 =>
-- Adjust Vbp*Q, shift by 10
w.Vhp := (mulr(35)&mulr(35)&mulr(25 downto 10)) - r.vlp;
if hp_bp_lp(0)='1' then
w.Vf := r.Vf + r.Vlp;
end if;
w.state := 7;
when 7 =>
w.Vhp := r.Vhp - r.Vi;
w.state := 8;
when 8 =>
if hp_bp_lp(2)='1' then
w.Vf := r.Vf + r.Vhp;
end if;
w.state := 9;
when 9 =>
w.Vf := r.Vf + r.Vnf;
w.state := 10;
when 10 =>
-- Add mixer DC
w.Vf := r.Vf + to_signed(mixer_DC, r.Vf'LENGTH);
w.state := 11;
when 11 =>
-- Process volume
mulen <= '1';
mula <= r.Vf;
mulb <= (others => '0');
mulb(3 downto 0) <= signed(volume);
w.state := 12;
when 12 =>
w.done := '1';
w.vout(18) := mulr(35);
w.vout(17 downto 0) := mulr(17 downto 0);
w.state := 0;
when others =>
end case;
if rst='1' then
w.done := '0';
w.state := 0;
w.Vlp := (others => '0');
w.Vbp := (others => '0');
w.Vhp := (others => '0');
end if;
if rising_edge(clk) then
r<=w;
if r.state=8 then
dbg_Vbp <= r.vbp;
dbg_Vhp <= r.vhp;
dbg_Vlp <= r.vlp;
end if;
end if;
end process;
sound <= r.vout;
valid <= r.done;
end beh;
|
--
-- (C) Alvaro Lopes <[email protected]> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end entity;
architecture beh of sid_filters is
alias filt: std_logic_vector(3 downto 0) is Res_Filt(3 downto 0);
alias res: std_logic_vector(3 downto 0) is Res_Filt(7 downto 4);
alias voice3off: std_logic is Mode_Vol(7);
alias volume: std_logic_vector(3 downto 0) is Mode_Vol(3 downto 0);
alias hp_bp_lp: std_logic_vector(2 downto 0) is Mode_Vol(6 downto 4);
constant mixer_DC: integer := -475; -- NOTE to self: this might be wrong.
component sid_coeffs is
port (
clk: in std_logic;
addr: in integer range 0 to 2047;
val: out std_logic_vector(15 downto 0)
);
end component;
type regs_type is record
Vhp: signed(17 downto 0);
Vbp: signed(17 downto 0);
dVbp: signed(17 downto 0);
Vlp: signed(17 downto 0);
dVlp: signed(17 downto 0);
Vi: signed(17 downto 0);
Vnf: signed(17 downto 0);
Vf: signed(17 downto 0);
w0: signed(17 downto 0);
q: signed(17 downto 0);
vout:signed(18 downto 0);
state: integer;
done: std_logic;
end record;
signal dVhp_debug: signed(31 downto 0);
signal dVbp_debug: signed(31 downto 0);
signal addr: integer range 0 to 2047;
signal val: std_logic_vector(15 downto 0);
type divmul_t is array(0 to 15) of integer;
constant divmul: divmul_t := (
1448, 1323, 1218, 1128, 1051, 984, 925, 872, 825, 783, 745, 710, 679, 650, 624, 599
);
signal r: regs_type;
signal mula: signed(17 downto 0);
signal mulb: signed(17 downto 0);
signal mulr: signed(35 downto 0);
signal mulen: std_logic;
function s13_to_18(a: in signed(12 downto 0)) return signed is
variable r: signed(17 downto 0);
begin
r(12 downto 0):=a;
r(13):=a(12);
r(14):=a(12);
r(15):=a(12);
r(16):=a(12);
r(17):=a(12);
return r;
end function;
-- Debugging
signal dbg_Vlp, dbg_Vhp, dbg_Vbp: signed(17 downto 0);
signal fc: std_logic_vector(10 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if mulen='1' then
mulr <= mula * mulb;
end if;
end if;
end process;
fc <= Fc_hi & Fc_lo(2 downto 0);
c: sid_coeffs
port map (
clk => clk,
addr => addr,
val => val
);
addr <= to_integer(unsigned(fc));
process(clk, rst, r, input_valid, val, filt, voice1, voice2, voice3, voice3off, mulr, ext_in, hp_bp_lp, Mode_Vol)
variable w: regs_type;
begin
w:=r;
mula <= (others => 'X');
mulb <= (others => 'X');
mulen <= '0';
case r.state is
when 0 =>
w.done := '0';
if input_valid = '1' then
w.state := 1;
-- Reset Vin, Vnf
w.vi := (others => '0');
w.vnf := (others => '0');
end if;
when 1 =>
-- already have W0 ready. Always positive
w.w0 := "00" & signed(val);
-- 1st accumulation
if filt(0)='1' then
w.vi := r.vi + s13_to_18(voice1);
else
w.vnf := r.vnf + s13_to_18(voice1);
end if;
w.state := 2;
when 2 =>
-- 2nd accumulation
if filt(1)='1' then
w.vi := r.vi + s13_to_18(voice2);
else
w.vnf := r.vnf + s13_to_18(voice2);
end if;
-- Mult
mula <= r.w0;
mulb <= r.vhp;
mulen <= '1';
w.state := 3;
when 3 =>
-- 3rd accumulation
if filt(2)='1' then
w.vi := r.vi + s13_to_18(voice3);
else
if voice3off='0' then
w.vnf := r.vnf + s13_to_18(voice3);
end if;
end if;
-- Mult
mula <= r.w0;
mulb <= r.vbp;
mulen <= '1';
w.dVbp := mulr(35) & mulr(35 downto 19);
w.state := 4;
when 4 =>
-- 4th accumulation
if filt(3)='1' then
w.vi := r.vi + s13_to_18(ext_in);
else
w.vnf := r.vnf + s13_to_18(ext_in);
end if;
w.dVlp := mulr(35) & mulr(35 downto 19);
w.Vbp := r.Vbp - r.dVbp;
-- Get Q, synchronous.
w.q := to_signed(divmul(to_integer(unsigned(res))), 18);
w.state := 5;
when 5 =>
-- Ok, we have all summed. We performed multiplications for dVbp and dVlp.
-- new Vbp already computed.
mulen <= '1';
mula <= r.q;
mulb <= r.Vbp;
w.vlp := r.Vlp - r.dVlp;
-- Start computing output;
if hp_bp_lp(1)='1' then
w.Vf := r.Vbp;
else
w.Vf := (others => '0');
end if;
w.state := 6;
when 6 =>
-- Adjust Vbp*Q, shift by 10
w.Vhp := (mulr(35)&mulr(35)&mulr(25 downto 10)) - r.vlp;
if hp_bp_lp(0)='1' then
w.Vf := r.Vf + r.Vlp;
end if;
w.state := 7;
when 7 =>
w.Vhp := r.Vhp - r.Vi;
w.state := 8;
when 8 =>
if hp_bp_lp(2)='1' then
w.Vf := r.Vf + r.Vhp;
end if;
w.state := 9;
when 9 =>
w.Vf := r.Vf + r.Vnf;
w.state := 10;
when 10 =>
-- Add mixer DC
w.Vf := r.Vf + to_signed(mixer_DC, r.Vf'LENGTH);
w.state := 11;
when 11 =>
-- Process volume
mulen <= '1';
mula <= r.Vf;
mulb <= (others => '0');
mulb(3 downto 0) <= signed(volume);
w.state := 12;
when 12 =>
w.done := '1';
w.vout(18) := mulr(35);
w.vout(17 downto 0) := mulr(17 downto 0);
w.state := 0;
when others =>
end case;
if rst='1' then
w.done := '0';
w.state := 0;
w.Vlp := (others => '0');
w.Vbp := (others => '0');
w.Vhp := (others => '0');
end if;
if rising_edge(clk) then
r<=w;
if r.state=8 then
dbg_Vbp <= r.vbp;
dbg_Vhp <= r.vhp;
dbg_Vlp <= r.vlp;
end if;
end if;
end process;
sound <= r.vout;
valid <= r.done;
end beh;
|
--
-- (C) Alvaro Lopes <[email protected]> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end entity;
architecture beh of sid_filters is
alias filt: std_logic_vector(3 downto 0) is Res_Filt(3 downto 0);
alias res: std_logic_vector(3 downto 0) is Res_Filt(7 downto 4);
alias voice3off: std_logic is Mode_Vol(7);
alias volume: std_logic_vector(3 downto 0) is Mode_Vol(3 downto 0);
alias hp_bp_lp: std_logic_vector(2 downto 0) is Mode_Vol(6 downto 4);
constant mixer_DC: integer := -475; -- NOTE to self: this might be wrong.
component sid_coeffs is
port (
clk: in std_logic;
addr: in integer range 0 to 2047;
val: out std_logic_vector(15 downto 0)
);
end component;
type regs_type is record
Vhp: signed(17 downto 0);
Vbp: signed(17 downto 0);
dVbp: signed(17 downto 0);
Vlp: signed(17 downto 0);
dVlp: signed(17 downto 0);
Vi: signed(17 downto 0);
Vnf: signed(17 downto 0);
Vf: signed(17 downto 0);
w0: signed(17 downto 0);
q: signed(17 downto 0);
vout:signed(18 downto 0);
state: integer;
done: std_logic;
end record;
signal dVhp_debug: signed(31 downto 0);
signal dVbp_debug: signed(31 downto 0);
signal addr: integer range 0 to 2047;
signal val: std_logic_vector(15 downto 0);
type divmul_t is array(0 to 15) of integer;
constant divmul: divmul_t := (
1448, 1323, 1218, 1128, 1051, 984, 925, 872, 825, 783, 745, 710, 679, 650, 624, 599
);
signal r: regs_type;
signal mula: signed(17 downto 0);
signal mulb: signed(17 downto 0);
signal mulr: signed(35 downto 0);
signal mulen: std_logic;
function s13_to_18(a: in signed(12 downto 0)) return signed is
variable r: signed(17 downto 0);
begin
r(12 downto 0):=a;
r(13):=a(12);
r(14):=a(12);
r(15):=a(12);
r(16):=a(12);
r(17):=a(12);
return r;
end function;
-- Debugging
signal dbg_Vlp, dbg_Vhp, dbg_Vbp: signed(17 downto 0);
signal fc: std_logic_vector(10 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if mulen='1' then
mulr <= mula * mulb;
end if;
end if;
end process;
fc <= Fc_hi & Fc_lo(2 downto 0);
c: sid_coeffs
port map (
clk => clk,
addr => addr,
val => val
);
addr <= to_integer(unsigned(fc));
process(clk, rst, r, input_valid, val, filt, voice1, voice2, voice3, voice3off, mulr, ext_in, hp_bp_lp, Mode_Vol)
variable w: regs_type;
begin
w:=r;
mula <= (others => 'X');
mulb <= (others => 'X');
mulen <= '0';
case r.state is
when 0 =>
w.done := '0';
if input_valid = '1' then
w.state := 1;
-- Reset Vin, Vnf
w.vi := (others => '0');
w.vnf := (others => '0');
end if;
when 1 =>
-- already have W0 ready. Always positive
w.w0 := "00" & signed(val);
-- 1st accumulation
if filt(0)='1' then
w.vi := r.vi + s13_to_18(voice1);
else
w.vnf := r.vnf + s13_to_18(voice1);
end if;
w.state := 2;
when 2 =>
-- 2nd accumulation
if filt(1)='1' then
w.vi := r.vi + s13_to_18(voice2);
else
w.vnf := r.vnf + s13_to_18(voice2);
end if;
-- Mult
mula <= r.w0;
mulb <= r.vhp;
mulen <= '1';
w.state := 3;
when 3 =>
-- 3rd accumulation
if filt(2)='1' then
w.vi := r.vi + s13_to_18(voice3);
else
if voice3off='0' then
w.vnf := r.vnf + s13_to_18(voice3);
end if;
end if;
-- Mult
mula <= r.w0;
mulb <= r.vbp;
mulen <= '1';
w.dVbp := mulr(35) & mulr(35 downto 19);
w.state := 4;
when 4 =>
-- 4th accumulation
if filt(3)='1' then
w.vi := r.vi + s13_to_18(ext_in);
else
w.vnf := r.vnf + s13_to_18(ext_in);
end if;
w.dVlp := mulr(35) & mulr(35 downto 19);
w.Vbp := r.Vbp - r.dVbp;
-- Get Q, synchronous.
w.q := to_signed(divmul(to_integer(unsigned(res))), 18);
w.state := 5;
when 5 =>
-- Ok, we have all summed. We performed multiplications for dVbp and dVlp.
-- new Vbp already computed.
mulen <= '1';
mula <= r.q;
mulb <= r.Vbp;
w.vlp := r.Vlp - r.dVlp;
-- Start computing output;
if hp_bp_lp(1)='1' then
w.Vf := r.Vbp;
else
w.Vf := (others => '0');
end if;
w.state := 6;
when 6 =>
-- Adjust Vbp*Q, shift by 10
w.Vhp := (mulr(35)&mulr(35)&mulr(25 downto 10)) - r.vlp;
if hp_bp_lp(0)='1' then
w.Vf := r.Vf + r.Vlp;
end if;
w.state := 7;
when 7 =>
w.Vhp := r.Vhp - r.Vi;
w.state := 8;
when 8 =>
if hp_bp_lp(2)='1' then
w.Vf := r.Vf + r.Vhp;
end if;
w.state := 9;
when 9 =>
w.Vf := r.Vf + r.Vnf;
w.state := 10;
when 10 =>
-- Add mixer DC
w.Vf := r.Vf + to_signed(mixer_DC, r.Vf'LENGTH);
w.state := 11;
when 11 =>
-- Process volume
mulen <= '1';
mula <= r.Vf;
mulb <= (others => '0');
mulb(3 downto 0) <= signed(volume);
w.state := 12;
when 12 =>
w.done := '1';
w.vout(18) := mulr(35);
w.vout(17 downto 0) := mulr(17 downto 0);
w.state := 0;
when others =>
end case;
if rst='1' then
w.done := '0';
w.state := 0;
w.Vlp := (others => '0');
w.Vbp := (others => '0');
w.Vhp := (others => '0');
end if;
if rising_edge(clk) then
r<=w;
if r.state=8 then
dbg_Vbp <= r.vbp;
dbg_Vhp <= r.vhp;
dbg_Vlp <= r.vlp;
end if;
end if;
end process;
sound <= r.vout;
valid <= r.done;
end beh;
|
--
-- (C) Alvaro Lopes <[email protected]> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end entity;
architecture beh of sid_filters is
alias filt: std_logic_vector(3 downto 0) is Res_Filt(3 downto 0);
alias res: std_logic_vector(3 downto 0) is Res_Filt(7 downto 4);
alias voice3off: std_logic is Mode_Vol(7);
alias volume: std_logic_vector(3 downto 0) is Mode_Vol(3 downto 0);
alias hp_bp_lp: std_logic_vector(2 downto 0) is Mode_Vol(6 downto 4);
constant mixer_DC: integer := -475; -- NOTE to self: this might be wrong.
component sid_coeffs is
port (
clk: in std_logic;
addr: in integer range 0 to 2047;
val: out std_logic_vector(15 downto 0)
);
end component;
type regs_type is record
Vhp: signed(17 downto 0);
Vbp: signed(17 downto 0);
dVbp: signed(17 downto 0);
Vlp: signed(17 downto 0);
dVlp: signed(17 downto 0);
Vi: signed(17 downto 0);
Vnf: signed(17 downto 0);
Vf: signed(17 downto 0);
w0: signed(17 downto 0);
q: signed(17 downto 0);
vout:signed(18 downto 0);
state: integer;
done: std_logic;
end record;
signal dVhp_debug: signed(31 downto 0);
signal dVbp_debug: signed(31 downto 0);
signal addr: integer range 0 to 2047;
signal val: std_logic_vector(15 downto 0);
type divmul_t is array(0 to 15) of integer;
constant divmul: divmul_t := (
1448, 1323, 1218, 1128, 1051, 984, 925, 872, 825, 783, 745, 710, 679, 650, 624, 599
);
signal r: regs_type;
signal mula: signed(17 downto 0);
signal mulb: signed(17 downto 0);
signal mulr: signed(35 downto 0);
signal mulen: std_logic;
function s13_to_18(a: in signed(12 downto 0)) return signed is
variable r: signed(17 downto 0);
begin
r(12 downto 0):=a;
r(13):=a(12);
r(14):=a(12);
r(15):=a(12);
r(16):=a(12);
r(17):=a(12);
return r;
end function;
-- Debugging
signal dbg_Vlp, dbg_Vhp, dbg_Vbp: signed(17 downto 0);
signal fc: std_logic_vector(10 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if mulen='1' then
mulr <= mula * mulb;
end if;
end if;
end process;
fc <= Fc_hi & Fc_lo(2 downto 0);
c: sid_coeffs
port map (
clk => clk,
addr => addr,
val => val
);
addr <= to_integer(unsigned(fc));
process(clk, rst, r, input_valid, val, filt, voice1, voice2, voice3, voice3off, mulr, ext_in, hp_bp_lp, Mode_Vol)
variable w: regs_type;
begin
w:=r;
mula <= (others => 'X');
mulb <= (others => 'X');
mulen <= '0';
case r.state is
when 0 =>
w.done := '0';
if input_valid = '1' then
w.state := 1;
-- Reset Vin, Vnf
w.vi := (others => '0');
w.vnf := (others => '0');
end if;
when 1 =>
-- already have W0 ready. Always positive
w.w0 := "00" & signed(val);
-- 1st accumulation
if filt(0)='1' then
w.vi := r.vi + s13_to_18(voice1);
else
w.vnf := r.vnf + s13_to_18(voice1);
end if;
w.state := 2;
when 2 =>
-- 2nd accumulation
if filt(1)='1' then
w.vi := r.vi + s13_to_18(voice2);
else
w.vnf := r.vnf + s13_to_18(voice2);
end if;
-- Mult
mula <= r.w0;
mulb <= r.vhp;
mulen <= '1';
w.state := 3;
when 3 =>
-- 3rd accumulation
if filt(2)='1' then
w.vi := r.vi + s13_to_18(voice3);
else
if voice3off='0' then
w.vnf := r.vnf + s13_to_18(voice3);
end if;
end if;
-- Mult
mula <= r.w0;
mulb <= r.vbp;
mulen <= '1';
w.dVbp := mulr(35) & mulr(35 downto 19);
w.state := 4;
when 4 =>
-- 4th accumulation
if filt(3)='1' then
w.vi := r.vi + s13_to_18(ext_in);
else
w.vnf := r.vnf + s13_to_18(ext_in);
end if;
w.dVlp := mulr(35) & mulr(35 downto 19);
w.Vbp := r.Vbp - r.dVbp;
-- Get Q, synchronous.
w.q := to_signed(divmul(to_integer(unsigned(res))), 18);
w.state := 5;
when 5 =>
-- Ok, we have all summed. We performed multiplications for dVbp and dVlp.
-- new Vbp already computed.
mulen <= '1';
mula <= r.q;
mulb <= r.Vbp;
w.vlp := r.Vlp - r.dVlp;
-- Start computing output;
if hp_bp_lp(1)='1' then
w.Vf := r.Vbp;
else
w.Vf := (others => '0');
end if;
w.state := 6;
when 6 =>
-- Adjust Vbp*Q, shift by 10
w.Vhp := (mulr(35)&mulr(35)&mulr(25 downto 10)) - r.vlp;
if hp_bp_lp(0)='1' then
w.Vf := r.Vf + r.Vlp;
end if;
w.state := 7;
when 7 =>
w.Vhp := r.Vhp - r.Vi;
w.state := 8;
when 8 =>
if hp_bp_lp(2)='1' then
w.Vf := r.Vf + r.Vhp;
end if;
w.state := 9;
when 9 =>
w.Vf := r.Vf + r.Vnf;
w.state := 10;
when 10 =>
-- Add mixer DC
w.Vf := r.Vf + to_signed(mixer_DC, r.Vf'LENGTH);
w.state := 11;
when 11 =>
-- Process volume
mulen <= '1';
mula <= r.Vf;
mulb <= (others => '0');
mulb(3 downto 0) <= signed(volume);
w.state := 12;
when 12 =>
w.done := '1';
w.vout(18) := mulr(35);
w.vout(17 downto 0) := mulr(17 downto 0);
w.state := 0;
when others =>
end case;
if rst='1' then
w.done := '0';
w.state := 0;
w.Vlp := (others => '0');
w.Vbp := (others => '0');
w.Vhp := (others => '0');
end if;
if rising_edge(clk) then
r<=w;
if r.state=8 then
dbg_Vbp <= r.vbp;
dbg_Vhp <= r.vhp;
dbg_Vlp <= r.vlp;
end if;
end if;
end process;
sound <= r.vout;
valid <= r.done;
end beh;
|
--
-- (C) Alvaro Lopes <[email protected]> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end entity;
architecture beh of sid_filters is
alias filt: std_logic_vector(3 downto 0) is Res_Filt(3 downto 0);
alias res: std_logic_vector(3 downto 0) is Res_Filt(7 downto 4);
alias voice3off: std_logic is Mode_Vol(7);
alias volume: std_logic_vector(3 downto 0) is Mode_Vol(3 downto 0);
alias hp_bp_lp: std_logic_vector(2 downto 0) is Mode_Vol(6 downto 4);
constant mixer_DC: integer := -475; -- NOTE to self: this might be wrong.
component sid_coeffs is
port (
clk: in std_logic;
addr: in integer range 0 to 2047;
val: out std_logic_vector(15 downto 0)
);
end component;
type regs_type is record
Vhp: signed(17 downto 0);
Vbp: signed(17 downto 0);
dVbp: signed(17 downto 0);
Vlp: signed(17 downto 0);
dVlp: signed(17 downto 0);
Vi: signed(17 downto 0);
Vnf: signed(17 downto 0);
Vf: signed(17 downto 0);
w0: signed(17 downto 0);
q: signed(17 downto 0);
vout:signed(18 downto 0);
state: integer;
done: std_logic;
end record;
signal dVhp_debug: signed(31 downto 0);
signal dVbp_debug: signed(31 downto 0);
signal addr: integer range 0 to 2047;
signal val: std_logic_vector(15 downto 0);
type divmul_t is array(0 to 15) of integer;
constant divmul: divmul_t := (
1448, 1323, 1218, 1128, 1051, 984, 925, 872, 825, 783, 745, 710, 679, 650, 624, 599
);
signal r: regs_type;
signal mula: signed(17 downto 0);
signal mulb: signed(17 downto 0);
signal mulr: signed(35 downto 0);
signal mulen: std_logic;
function s13_to_18(a: in signed(12 downto 0)) return signed is
variable r: signed(17 downto 0);
begin
r(12 downto 0):=a;
r(13):=a(12);
r(14):=a(12);
r(15):=a(12);
r(16):=a(12);
r(17):=a(12);
return r;
end function;
-- Debugging
signal dbg_Vlp, dbg_Vhp, dbg_Vbp: signed(17 downto 0);
signal fc: std_logic_vector(10 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if mulen='1' then
mulr <= mula * mulb;
end if;
end if;
end process;
fc <= Fc_hi & Fc_lo(2 downto 0);
c: sid_coeffs
port map (
clk => clk,
addr => addr,
val => val
);
addr <= to_integer(unsigned(fc));
process(clk, rst, r, input_valid, val, filt, voice1, voice2, voice3, voice3off, mulr, ext_in, hp_bp_lp, Mode_Vol)
variable w: regs_type;
begin
w:=r;
mula <= (others => 'X');
mulb <= (others => 'X');
mulen <= '0';
case r.state is
when 0 =>
w.done := '0';
if input_valid = '1' then
w.state := 1;
-- Reset Vin, Vnf
w.vi := (others => '0');
w.vnf := (others => '0');
end if;
when 1 =>
-- already have W0 ready. Always positive
w.w0 := "00" & signed(val);
-- 1st accumulation
if filt(0)='1' then
w.vi := r.vi + s13_to_18(voice1);
else
w.vnf := r.vnf + s13_to_18(voice1);
end if;
w.state := 2;
when 2 =>
-- 2nd accumulation
if filt(1)='1' then
w.vi := r.vi + s13_to_18(voice2);
else
w.vnf := r.vnf + s13_to_18(voice2);
end if;
-- Mult
mula <= r.w0;
mulb <= r.vhp;
mulen <= '1';
w.state := 3;
when 3 =>
-- 3rd accumulation
if filt(2)='1' then
w.vi := r.vi + s13_to_18(voice3);
else
if voice3off='0' then
w.vnf := r.vnf + s13_to_18(voice3);
end if;
end if;
-- Mult
mula <= r.w0;
mulb <= r.vbp;
mulen <= '1';
w.dVbp := mulr(35) & mulr(35 downto 19);
w.state := 4;
when 4 =>
-- 4th accumulation
if filt(3)='1' then
w.vi := r.vi + s13_to_18(ext_in);
else
w.vnf := r.vnf + s13_to_18(ext_in);
end if;
w.dVlp := mulr(35) & mulr(35 downto 19);
w.Vbp := r.Vbp - r.dVbp;
-- Get Q, synchronous.
w.q := to_signed(divmul(to_integer(unsigned(res))), 18);
w.state := 5;
when 5 =>
-- Ok, we have all summed. We performed multiplications for dVbp and dVlp.
-- new Vbp already computed.
mulen <= '1';
mula <= r.q;
mulb <= r.Vbp;
w.vlp := r.Vlp - r.dVlp;
-- Start computing output;
if hp_bp_lp(1)='1' then
w.Vf := r.Vbp;
else
w.Vf := (others => '0');
end if;
w.state := 6;
when 6 =>
-- Adjust Vbp*Q, shift by 10
w.Vhp := (mulr(35)&mulr(35)&mulr(25 downto 10)) - r.vlp;
if hp_bp_lp(0)='1' then
w.Vf := r.Vf + r.Vlp;
end if;
w.state := 7;
when 7 =>
w.Vhp := r.Vhp - r.Vi;
w.state := 8;
when 8 =>
if hp_bp_lp(2)='1' then
w.Vf := r.Vf + r.Vhp;
end if;
w.state := 9;
when 9 =>
w.Vf := r.Vf + r.Vnf;
w.state := 10;
when 10 =>
-- Add mixer DC
w.Vf := r.Vf + to_signed(mixer_DC, r.Vf'LENGTH);
w.state := 11;
when 11 =>
-- Process volume
mulen <= '1';
mula <= r.Vf;
mulb <= (others => '0');
mulb(3 downto 0) <= signed(volume);
w.state := 12;
when 12 =>
w.done := '1';
w.vout(18) := mulr(35);
w.vout(17 downto 0) := mulr(17 downto 0);
w.state := 0;
when others =>
end case;
if rst='1' then
w.done := '0';
w.state := 0;
w.Vlp := (others => '0');
w.Vbp := (others => '0');
w.Vhp := (others => '0');
end if;
if rising_edge(clk) then
r<=w;
if r.state=8 then
dbg_Vbp <= r.vbp;
dbg_Vhp <= r.vhp;
dbg_Vlp <= r.vlp;
end if;
end if;
end process;
sound <= r.vout;
valid <= r.done;
end beh;
|
--
-- (C) Alvaro Lopes <[email protected]> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end entity;
architecture beh of sid_filters is
alias filt: std_logic_vector(3 downto 0) is Res_Filt(3 downto 0);
alias res: std_logic_vector(3 downto 0) is Res_Filt(7 downto 4);
alias voice3off: std_logic is Mode_Vol(7);
alias volume: std_logic_vector(3 downto 0) is Mode_Vol(3 downto 0);
alias hp_bp_lp: std_logic_vector(2 downto 0) is Mode_Vol(6 downto 4);
constant mixer_DC: integer := -475; -- NOTE to self: this might be wrong.
component sid_coeffs is
port (
clk: in std_logic;
addr: in integer range 0 to 2047;
val: out std_logic_vector(15 downto 0)
);
end component;
type regs_type is record
Vhp: signed(17 downto 0);
Vbp: signed(17 downto 0);
dVbp: signed(17 downto 0);
Vlp: signed(17 downto 0);
dVlp: signed(17 downto 0);
Vi: signed(17 downto 0);
Vnf: signed(17 downto 0);
Vf: signed(17 downto 0);
w0: signed(17 downto 0);
q: signed(17 downto 0);
vout:signed(18 downto 0);
state: integer;
done: std_logic;
end record;
signal dVhp_debug: signed(31 downto 0);
signal dVbp_debug: signed(31 downto 0);
signal addr: integer range 0 to 2047;
signal val: std_logic_vector(15 downto 0);
type divmul_t is array(0 to 15) of integer;
constant divmul: divmul_t := (
1448, 1323, 1218, 1128, 1051, 984, 925, 872, 825, 783, 745, 710, 679, 650, 624, 599
);
signal r: regs_type;
signal mula: signed(17 downto 0);
signal mulb: signed(17 downto 0);
signal mulr: signed(35 downto 0);
signal mulen: std_logic;
function s13_to_18(a: in signed(12 downto 0)) return signed is
variable r: signed(17 downto 0);
begin
r(12 downto 0):=a;
r(13):=a(12);
r(14):=a(12);
r(15):=a(12);
r(16):=a(12);
r(17):=a(12);
return r;
end function;
-- Debugging
signal dbg_Vlp, dbg_Vhp, dbg_Vbp: signed(17 downto 0);
signal fc: std_logic_vector(10 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if mulen='1' then
mulr <= mula * mulb;
end if;
end if;
end process;
fc <= Fc_hi & Fc_lo(2 downto 0);
c: sid_coeffs
port map (
clk => clk,
addr => addr,
val => val
);
addr <= to_integer(unsigned(fc));
process(clk, rst, r, input_valid, val, filt, voice1, voice2, voice3, voice3off, mulr, ext_in, hp_bp_lp, Mode_Vol)
variable w: regs_type;
begin
w:=r;
mula <= (others => 'X');
mulb <= (others => 'X');
mulen <= '0';
case r.state is
when 0 =>
w.done := '0';
if input_valid = '1' then
w.state := 1;
-- Reset Vin, Vnf
w.vi := (others => '0');
w.vnf := (others => '0');
end if;
when 1 =>
-- already have W0 ready. Always positive
w.w0 := "00" & signed(val);
-- 1st accumulation
if filt(0)='1' then
w.vi := r.vi + s13_to_18(voice1);
else
w.vnf := r.vnf + s13_to_18(voice1);
end if;
w.state := 2;
when 2 =>
-- 2nd accumulation
if filt(1)='1' then
w.vi := r.vi + s13_to_18(voice2);
else
w.vnf := r.vnf + s13_to_18(voice2);
end if;
-- Mult
mula <= r.w0;
mulb <= r.vhp;
mulen <= '1';
w.state := 3;
when 3 =>
-- 3rd accumulation
if filt(2)='1' then
w.vi := r.vi + s13_to_18(voice3);
else
if voice3off='0' then
w.vnf := r.vnf + s13_to_18(voice3);
end if;
end if;
-- Mult
mula <= r.w0;
mulb <= r.vbp;
mulen <= '1';
w.dVbp := mulr(35) & mulr(35 downto 19);
w.state := 4;
when 4 =>
-- 4th accumulation
if filt(3)='1' then
w.vi := r.vi + s13_to_18(ext_in);
else
w.vnf := r.vnf + s13_to_18(ext_in);
end if;
w.dVlp := mulr(35) & mulr(35 downto 19);
w.Vbp := r.Vbp - r.dVbp;
-- Get Q, synchronous.
w.q := to_signed(divmul(to_integer(unsigned(res))), 18);
w.state := 5;
when 5 =>
-- Ok, we have all summed. We performed multiplications for dVbp and dVlp.
-- new Vbp already computed.
mulen <= '1';
mula <= r.q;
mulb <= r.Vbp;
w.vlp := r.Vlp - r.dVlp;
-- Start computing output;
if hp_bp_lp(1)='1' then
w.Vf := r.Vbp;
else
w.Vf := (others => '0');
end if;
w.state := 6;
when 6 =>
-- Adjust Vbp*Q, shift by 10
w.Vhp := (mulr(35)&mulr(35)&mulr(25 downto 10)) - r.vlp;
if hp_bp_lp(0)='1' then
w.Vf := r.Vf + r.Vlp;
end if;
w.state := 7;
when 7 =>
w.Vhp := r.Vhp - r.Vi;
w.state := 8;
when 8 =>
if hp_bp_lp(2)='1' then
w.Vf := r.Vf + r.Vhp;
end if;
w.state := 9;
when 9 =>
w.Vf := r.Vf + r.Vnf;
w.state := 10;
when 10 =>
-- Add mixer DC
w.Vf := r.Vf + to_signed(mixer_DC, r.Vf'LENGTH);
w.state := 11;
when 11 =>
-- Process volume
mulen <= '1';
mula <= r.Vf;
mulb <= (others => '0');
mulb(3 downto 0) <= signed(volume);
w.state := 12;
when 12 =>
w.done := '1';
w.vout(18) := mulr(35);
w.vout(17 downto 0) := mulr(17 downto 0);
w.state := 0;
when others =>
end case;
if rst='1' then
w.done := '0';
w.state := 0;
w.Vlp := (others => '0');
w.Vbp := (others => '0');
w.Vhp := (others => '0');
end if;
if rising_edge(clk) then
r<=w;
if r.state=8 then
dbg_Vbp <= r.vbp;
dbg_Vhp <= r.vhp;
dbg_Vlp <= r.vlp;
end if;
end if;
end process;
sound <= r.vout;
valid <= r.done;
end beh;
|
--
-- (C) Alvaro Lopes <[email protected]> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end entity;
architecture beh of sid_filters is
alias filt: std_logic_vector(3 downto 0) is Res_Filt(3 downto 0);
alias res: std_logic_vector(3 downto 0) is Res_Filt(7 downto 4);
alias voice3off: std_logic is Mode_Vol(7);
alias volume: std_logic_vector(3 downto 0) is Mode_Vol(3 downto 0);
alias hp_bp_lp: std_logic_vector(2 downto 0) is Mode_Vol(6 downto 4);
constant mixer_DC: integer := -475; -- NOTE to self: this might be wrong.
component sid_coeffs is
port (
clk: in std_logic;
addr: in integer range 0 to 2047;
val: out std_logic_vector(15 downto 0)
);
end component;
type regs_type is record
Vhp: signed(17 downto 0);
Vbp: signed(17 downto 0);
dVbp: signed(17 downto 0);
Vlp: signed(17 downto 0);
dVlp: signed(17 downto 0);
Vi: signed(17 downto 0);
Vnf: signed(17 downto 0);
Vf: signed(17 downto 0);
w0: signed(17 downto 0);
q: signed(17 downto 0);
vout:signed(18 downto 0);
state: integer;
done: std_logic;
end record;
signal dVhp_debug: signed(31 downto 0);
signal dVbp_debug: signed(31 downto 0);
signal addr: integer range 0 to 2047;
signal val: std_logic_vector(15 downto 0);
type divmul_t is array(0 to 15) of integer;
constant divmul: divmul_t := (
1448, 1323, 1218, 1128, 1051, 984, 925, 872, 825, 783, 745, 710, 679, 650, 624, 599
);
signal r: regs_type;
signal mula: signed(17 downto 0);
signal mulb: signed(17 downto 0);
signal mulr: signed(35 downto 0);
signal mulen: std_logic;
function s13_to_18(a: in signed(12 downto 0)) return signed is
variable r: signed(17 downto 0);
begin
r(12 downto 0):=a;
r(13):=a(12);
r(14):=a(12);
r(15):=a(12);
r(16):=a(12);
r(17):=a(12);
return r;
end function;
-- Debugging
signal dbg_Vlp, dbg_Vhp, dbg_Vbp: signed(17 downto 0);
signal fc: std_logic_vector(10 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if mulen='1' then
mulr <= mula * mulb;
end if;
end if;
end process;
fc <= Fc_hi & Fc_lo(2 downto 0);
c: sid_coeffs
port map (
clk => clk,
addr => addr,
val => val
);
addr <= to_integer(unsigned(fc));
process(clk, rst, r, input_valid, val, filt, voice1, voice2, voice3, voice3off, mulr, ext_in, hp_bp_lp, Mode_Vol)
variable w: regs_type;
begin
w:=r;
mula <= (others => 'X');
mulb <= (others => 'X');
mulen <= '0';
case r.state is
when 0 =>
w.done := '0';
if input_valid = '1' then
w.state := 1;
-- Reset Vin, Vnf
w.vi := (others => '0');
w.vnf := (others => '0');
end if;
when 1 =>
-- already have W0 ready. Always positive
w.w0 := "00" & signed(val);
-- 1st accumulation
if filt(0)='1' then
w.vi := r.vi + s13_to_18(voice1);
else
w.vnf := r.vnf + s13_to_18(voice1);
end if;
w.state := 2;
when 2 =>
-- 2nd accumulation
if filt(1)='1' then
w.vi := r.vi + s13_to_18(voice2);
else
w.vnf := r.vnf + s13_to_18(voice2);
end if;
-- Mult
mula <= r.w0;
mulb <= r.vhp;
mulen <= '1';
w.state := 3;
when 3 =>
-- 3rd accumulation
if filt(2)='1' then
w.vi := r.vi + s13_to_18(voice3);
else
if voice3off='0' then
w.vnf := r.vnf + s13_to_18(voice3);
end if;
end if;
-- Mult
mula <= r.w0;
mulb <= r.vbp;
mulen <= '1';
w.dVbp := mulr(35) & mulr(35 downto 19);
w.state := 4;
when 4 =>
-- 4th accumulation
if filt(3)='1' then
w.vi := r.vi + s13_to_18(ext_in);
else
w.vnf := r.vnf + s13_to_18(ext_in);
end if;
w.dVlp := mulr(35) & mulr(35 downto 19);
w.Vbp := r.Vbp - r.dVbp;
-- Get Q, synchronous.
w.q := to_signed(divmul(to_integer(unsigned(res))), 18);
w.state := 5;
when 5 =>
-- Ok, we have all summed. We performed multiplications for dVbp and dVlp.
-- new Vbp already computed.
mulen <= '1';
mula <= r.q;
mulb <= r.Vbp;
w.vlp := r.Vlp - r.dVlp;
-- Start computing output;
if hp_bp_lp(1)='1' then
w.Vf := r.Vbp;
else
w.Vf := (others => '0');
end if;
w.state := 6;
when 6 =>
-- Adjust Vbp*Q, shift by 10
w.Vhp := (mulr(35)&mulr(35)&mulr(25 downto 10)) - r.vlp;
if hp_bp_lp(0)='1' then
w.Vf := r.Vf + r.Vlp;
end if;
w.state := 7;
when 7 =>
w.Vhp := r.Vhp - r.Vi;
w.state := 8;
when 8 =>
if hp_bp_lp(2)='1' then
w.Vf := r.Vf + r.Vhp;
end if;
w.state := 9;
when 9 =>
w.Vf := r.Vf + r.Vnf;
w.state := 10;
when 10 =>
-- Add mixer DC
w.Vf := r.Vf + to_signed(mixer_DC, r.Vf'LENGTH);
w.state := 11;
when 11 =>
-- Process volume
mulen <= '1';
mula <= r.Vf;
mulb <= (others => '0');
mulb(3 downto 0) <= signed(volume);
w.state := 12;
when 12 =>
w.done := '1';
w.vout(18) := mulr(35);
w.vout(17 downto 0) := mulr(17 downto 0);
w.state := 0;
when others =>
end case;
if rst='1' then
w.done := '0';
w.state := 0;
w.Vlp := (others => '0');
w.Vbp := (others => '0');
w.Vhp := (others => '0');
end if;
if rising_edge(clk) then
r<=w;
if r.state=8 then
dbg_Vbp <= r.vbp;
dbg_Vhp <= r.vhp;
dbg_Vlp <= r.vlp;
end if;
end if;
end process;
sound <= r.vout;
valid <= r.done;
end beh;
|
--
-- (C) Alvaro Lopes <[email protected]> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end entity;
architecture beh of sid_filters is
alias filt: std_logic_vector(3 downto 0) is Res_Filt(3 downto 0);
alias res: std_logic_vector(3 downto 0) is Res_Filt(7 downto 4);
alias voice3off: std_logic is Mode_Vol(7);
alias volume: std_logic_vector(3 downto 0) is Mode_Vol(3 downto 0);
alias hp_bp_lp: std_logic_vector(2 downto 0) is Mode_Vol(6 downto 4);
constant mixer_DC: integer := -475; -- NOTE to self: this might be wrong.
component sid_coeffs is
port (
clk: in std_logic;
addr: in integer range 0 to 2047;
val: out std_logic_vector(15 downto 0)
);
end component;
type regs_type is record
Vhp: signed(17 downto 0);
Vbp: signed(17 downto 0);
dVbp: signed(17 downto 0);
Vlp: signed(17 downto 0);
dVlp: signed(17 downto 0);
Vi: signed(17 downto 0);
Vnf: signed(17 downto 0);
Vf: signed(17 downto 0);
w0: signed(17 downto 0);
q: signed(17 downto 0);
vout:signed(18 downto 0);
state: integer;
done: std_logic;
end record;
signal dVhp_debug: signed(31 downto 0);
signal dVbp_debug: signed(31 downto 0);
signal addr: integer range 0 to 2047;
signal val: std_logic_vector(15 downto 0);
type divmul_t is array(0 to 15) of integer;
constant divmul: divmul_t := (
1448, 1323, 1218, 1128, 1051, 984, 925, 872, 825, 783, 745, 710, 679, 650, 624, 599
);
signal r: regs_type;
signal mula: signed(17 downto 0);
signal mulb: signed(17 downto 0);
signal mulr: signed(35 downto 0);
signal mulen: std_logic;
function s13_to_18(a: in signed(12 downto 0)) return signed is
variable r: signed(17 downto 0);
begin
r(12 downto 0):=a;
r(13):=a(12);
r(14):=a(12);
r(15):=a(12);
r(16):=a(12);
r(17):=a(12);
return r;
end function;
-- Debugging
signal dbg_Vlp, dbg_Vhp, dbg_Vbp: signed(17 downto 0);
signal fc: std_logic_vector(10 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if mulen='1' then
mulr <= mula * mulb;
end if;
end if;
end process;
fc <= Fc_hi & Fc_lo(2 downto 0);
c: sid_coeffs
port map (
clk => clk,
addr => addr,
val => val
);
addr <= to_integer(unsigned(fc));
process(clk, rst, r, input_valid, val, filt, voice1, voice2, voice3, voice3off, mulr, ext_in, hp_bp_lp, Mode_Vol)
variable w: regs_type;
begin
w:=r;
mula <= (others => 'X');
mulb <= (others => 'X');
mulen <= '0';
case r.state is
when 0 =>
w.done := '0';
if input_valid = '1' then
w.state := 1;
-- Reset Vin, Vnf
w.vi := (others => '0');
w.vnf := (others => '0');
end if;
when 1 =>
-- already have W0 ready. Always positive
w.w0 := "00" & signed(val);
-- 1st accumulation
if filt(0)='1' then
w.vi := r.vi + s13_to_18(voice1);
else
w.vnf := r.vnf + s13_to_18(voice1);
end if;
w.state := 2;
when 2 =>
-- 2nd accumulation
if filt(1)='1' then
w.vi := r.vi + s13_to_18(voice2);
else
w.vnf := r.vnf + s13_to_18(voice2);
end if;
-- Mult
mula <= r.w0;
mulb <= r.vhp;
mulen <= '1';
w.state := 3;
when 3 =>
-- 3rd accumulation
if filt(2)='1' then
w.vi := r.vi + s13_to_18(voice3);
else
if voice3off='0' then
w.vnf := r.vnf + s13_to_18(voice3);
end if;
end if;
-- Mult
mula <= r.w0;
mulb <= r.vbp;
mulen <= '1';
w.dVbp := mulr(35) & mulr(35 downto 19);
w.state := 4;
when 4 =>
-- 4th accumulation
if filt(3)='1' then
w.vi := r.vi + s13_to_18(ext_in);
else
w.vnf := r.vnf + s13_to_18(ext_in);
end if;
w.dVlp := mulr(35) & mulr(35 downto 19);
w.Vbp := r.Vbp - r.dVbp;
-- Get Q, synchronous.
w.q := to_signed(divmul(to_integer(unsigned(res))), 18);
w.state := 5;
when 5 =>
-- Ok, we have all summed. We performed multiplications for dVbp and dVlp.
-- new Vbp already computed.
mulen <= '1';
mula <= r.q;
mulb <= r.Vbp;
w.vlp := r.Vlp - r.dVlp;
-- Start computing output;
if hp_bp_lp(1)='1' then
w.Vf := r.Vbp;
else
w.Vf := (others => '0');
end if;
w.state := 6;
when 6 =>
-- Adjust Vbp*Q, shift by 10
w.Vhp := (mulr(35)&mulr(35)&mulr(25 downto 10)) - r.vlp;
if hp_bp_lp(0)='1' then
w.Vf := r.Vf + r.Vlp;
end if;
w.state := 7;
when 7 =>
w.Vhp := r.Vhp - r.Vi;
w.state := 8;
when 8 =>
if hp_bp_lp(2)='1' then
w.Vf := r.Vf + r.Vhp;
end if;
w.state := 9;
when 9 =>
w.Vf := r.Vf + r.Vnf;
w.state := 10;
when 10 =>
-- Add mixer DC
w.Vf := r.Vf + to_signed(mixer_DC, r.Vf'LENGTH);
w.state := 11;
when 11 =>
-- Process volume
mulen <= '1';
mula <= r.Vf;
mulb <= (others => '0');
mulb(3 downto 0) <= signed(volume);
w.state := 12;
when 12 =>
w.done := '1';
w.vout(18) := mulr(35);
w.vout(17 downto 0) := mulr(17 downto 0);
w.state := 0;
when others =>
end case;
if rst='1' then
w.done := '0';
w.state := 0;
w.Vlp := (others => '0');
w.Vbp := (others => '0');
w.Vhp := (others => '0');
end if;
if rising_edge(clk) then
r<=w;
if r.state=8 then
dbg_Vbp <= r.vbp;
dbg_Vhp <= r.vhp;
dbg_Vlp <= r.vlp;
end if;
end if;
end process;
sound <= r.vout;
valid <= r.done;
end beh;
|
--
-- (C) Alvaro Lopes <[email protected]> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end entity;
architecture beh of sid_filters is
alias filt: std_logic_vector(3 downto 0) is Res_Filt(3 downto 0);
alias res: std_logic_vector(3 downto 0) is Res_Filt(7 downto 4);
alias voice3off: std_logic is Mode_Vol(7);
alias volume: std_logic_vector(3 downto 0) is Mode_Vol(3 downto 0);
alias hp_bp_lp: std_logic_vector(2 downto 0) is Mode_Vol(6 downto 4);
constant mixer_DC: integer := -475; -- NOTE to self: this might be wrong.
component sid_coeffs is
port (
clk: in std_logic;
addr: in integer range 0 to 2047;
val: out std_logic_vector(15 downto 0)
);
end component;
type regs_type is record
Vhp: signed(17 downto 0);
Vbp: signed(17 downto 0);
dVbp: signed(17 downto 0);
Vlp: signed(17 downto 0);
dVlp: signed(17 downto 0);
Vi: signed(17 downto 0);
Vnf: signed(17 downto 0);
Vf: signed(17 downto 0);
w0: signed(17 downto 0);
q: signed(17 downto 0);
vout:signed(18 downto 0);
state: integer;
done: std_logic;
end record;
signal dVhp_debug: signed(31 downto 0);
signal dVbp_debug: signed(31 downto 0);
signal addr: integer range 0 to 2047;
signal val: std_logic_vector(15 downto 0);
type divmul_t is array(0 to 15) of integer;
constant divmul: divmul_t := (
1448, 1323, 1218, 1128, 1051, 984, 925, 872, 825, 783, 745, 710, 679, 650, 624, 599
);
signal r: regs_type;
signal mula: signed(17 downto 0);
signal mulb: signed(17 downto 0);
signal mulr: signed(35 downto 0);
signal mulen: std_logic;
function s13_to_18(a: in signed(12 downto 0)) return signed is
variable r: signed(17 downto 0);
begin
r(12 downto 0):=a;
r(13):=a(12);
r(14):=a(12);
r(15):=a(12);
r(16):=a(12);
r(17):=a(12);
return r;
end function;
-- Debugging
signal dbg_Vlp, dbg_Vhp, dbg_Vbp: signed(17 downto 0);
signal fc: std_logic_vector(10 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if mulen='1' then
mulr <= mula * mulb;
end if;
end if;
end process;
fc <= Fc_hi & Fc_lo(2 downto 0);
c: sid_coeffs
port map (
clk => clk,
addr => addr,
val => val
);
addr <= to_integer(unsigned(fc));
process(clk, rst, r, input_valid, val, filt, voice1, voice2, voice3, voice3off, mulr, ext_in, hp_bp_lp, Mode_Vol)
variable w: regs_type;
begin
w:=r;
mula <= (others => 'X');
mulb <= (others => 'X');
mulen <= '0';
case r.state is
when 0 =>
w.done := '0';
if input_valid = '1' then
w.state := 1;
-- Reset Vin, Vnf
w.vi := (others => '0');
w.vnf := (others => '0');
end if;
when 1 =>
-- already have W0 ready. Always positive
w.w0 := "00" & signed(val);
-- 1st accumulation
if filt(0)='1' then
w.vi := r.vi + s13_to_18(voice1);
else
w.vnf := r.vnf + s13_to_18(voice1);
end if;
w.state := 2;
when 2 =>
-- 2nd accumulation
if filt(1)='1' then
w.vi := r.vi + s13_to_18(voice2);
else
w.vnf := r.vnf + s13_to_18(voice2);
end if;
-- Mult
mula <= r.w0;
mulb <= r.vhp;
mulen <= '1';
w.state := 3;
when 3 =>
-- 3rd accumulation
if filt(2)='1' then
w.vi := r.vi + s13_to_18(voice3);
else
if voice3off='0' then
w.vnf := r.vnf + s13_to_18(voice3);
end if;
end if;
-- Mult
mula <= r.w0;
mulb <= r.vbp;
mulen <= '1';
w.dVbp := mulr(35) & mulr(35 downto 19);
w.state := 4;
when 4 =>
-- 4th accumulation
if filt(3)='1' then
w.vi := r.vi + s13_to_18(ext_in);
else
w.vnf := r.vnf + s13_to_18(ext_in);
end if;
w.dVlp := mulr(35) & mulr(35 downto 19);
w.Vbp := r.Vbp - r.dVbp;
-- Get Q, synchronous.
w.q := to_signed(divmul(to_integer(unsigned(res))), 18);
w.state := 5;
when 5 =>
-- Ok, we have all summed. We performed multiplications for dVbp and dVlp.
-- new Vbp already computed.
mulen <= '1';
mula <= r.q;
mulb <= r.Vbp;
w.vlp := r.Vlp - r.dVlp;
-- Start computing output;
if hp_bp_lp(1)='1' then
w.Vf := r.Vbp;
else
w.Vf := (others => '0');
end if;
w.state := 6;
when 6 =>
-- Adjust Vbp*Q, shift by 10
w.Vhp := (mulr(35)&mulr(35)&mulr(25 downto 10)) - r.vlp;
if hp_bp_lp(0)='1' then
w.Vf := r.Vf + r.Vlp;
end if;
w.state := 7;
when 7 =>
w.Vhp := r.Vhp - r.Vi;
w.state := 8;
when 8 =>
if hp_bp_lp(2)='1' then
w.Vf := r.Vf + r.Vhp;
end if;
w.state := 9;
when 9 =>
w.Vf := r.Vf + r.Vnf;
w.state := 10;
when 10 =>
-- Add mixer DC
w.Vf := r.Vf + to_signed(mixer_DC, r.Vf'LENGTH);
w.state := 11;
when 11 =>
-- Process volume
mulen <= '1';
mula <= r.Vf;
mulb <= (others => '0');
mulb(3 downto 0) <= signed(volume);
w.state := 12;
when 12 =>
w.done := '1';
w.vout(18) := mulr(35);
w.vout(17 downto 0) := mulr(17 downto 0);
w.state := 0;
when others =>
end case;
if rst='1' then
w.done := '0';
w.state := 0;
w.Vlp := (others => '0');
w.Vbp := (others => '0');
w.Vhp := (others => '0');
end if;
if rising_edge(clk) then
r<=w;
if r.state=8 then
dbg_Vbp <= r.vbp;
dbg_Vhp <= r.vhp;
dbg_Vlp <= r.vlp;
end if;
end if;
end process;
sound <= r.vout;
valid <= r.done;
end beh;
|
--
-- (C) Alvaro Lopes <[email protected]> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end entity;
architecture beh of sid_filters is
alias filt: std_logic_vector(3 downto 0) is Res_Filt(3 downto 0);
alias res: std_logic_vector(3 downto 0) is Res_Filt(7 downto 4);
alias voice3off: std_logic is Mode_Vol(7);
alias volume: std_logic_vector(3 downto 0) is Mode_Vol(3 downto 0);
alias hp_bp_lp: std_logic_vector(2 downto 0) is Mode_Vol(6 downto 4);
constant mixer_DC: integer := -475; -- NOTE to self: this might be wrong.
component sid_coeffs is
port (
clk: in std_logic;
addr: in integer range 0 to 2047;
val: out std_logic_vector(15 downto 0)
);
end component;
type regs_type is record
Vhp: signed(17 downto 0);
Vbp: signed(17 downto 0);
dVbp: signed(17 downto 0);
Vlp: signed(17 downto 0);
dVlp: signed(17 downto 0);
Vi: signed(17 downto 0);
Vnf: signed(17 downto 0);
Vf: signed(17 downto 0);
w0: signed(17 downto 0);
q: signed(17 downto 0);
vout:signed(18 downto 0);
state: integer;
done: std_logic;
end record;
signal dVhp_debug: signed(31 downto 0);
signal dVbp_debug: signed(31 downto 0);
signal addr: integer range 0 to 2047;
signal val: std_logic_vector(15 downto 0);
type divmul_t is array(0 to 15) of integer;
constant divmul: divmul_t := (
1448, 1323, 1218, 1128, 1051, 984, 925, 872, 825, 783, 745, 710, 679, 650, 624, 599
);
signal r: regs_type;
signal mula: signed(17 downto 0);
signal mulb: signed(17 downto 0);
signal mulr: signed(35 downto 0);
signal mulen: std_logic;
function s13_to_18(a: in signed(12 downto 0)) return signed is
variable r: signed(17 downto 0);
begin
r(12 downto 0):=a;
r(13):=a(12);
r(14):=a(12);
r(15):=a(12);
r(16):=a(12);
r(17):=a(12);
return r;
end function;
-- Debugging
signal dbg_Vlp, dbg_Vhp, dbg_Vbp: signed(17 downto 0);
signal fc: std_logic_vector(10 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if mulen='1' then
mulr <= mula * mulb;
end if;
end if;
end process;
fc <= Fc_hi & Fc_lo(2 downto 0);
c: sid_coeffs
port map (
clk => clk,
addr => addr,
val => val
);
addr <= to_integer(unsigned(fc));
process(clk, rst, r, input_valid, val, filt, voice1, voice2, voice3, voice3off, mulr, ext_in, hp_bp_lp, Mode_Vol)
variable w: regs_type;
begin
w:=r;
mula <= (others => 'X');
mulb <= (others => 'X');
mulen <= '0';
case r.state is
when 0 =>
w.done := '0';
if input_valid = '1' then
w.state := 1;
-- Reset Vin, Vnf
w.vi := (others => '0');
w.vnf := (others => '0');
end if;
when 1 =>
-- already have W0 ready. Always positive
w.w0 := "00" & signed(val);
-- 1st accumulation
if filt(0)='1' then
w.vi := r.vi + s13_to_18(voice1);
else
w.vnf := r.vnf + s13_to_18(voice1);
end if;
w.state := 2;
when 2 =>
-- 2nd accumulation
if filt(1)='1' then
w.vi := r.vi + s13_to_18(voice2);
else
w.vnf := r.vnf + s13_to_18(voice2);
end if;
-- Mult
mula <= r.w0;
mulb <= r.vhp;
mulen <= '1';
w.state := 3;
when 3 =>
-- 3rd accumulation
if filt(2)='1' then
w.vi := r.vi + s13_to_18(voice3);
else
if voice3off='0' then
w.vnf := r.vnf + s13_to_18(voice3);
end if;
end if;
-- Mult
mula <= r.w0;
mulb <= r.vbp;
mulen <= '1';
w.dVbp := mulr(35) & mulr(35 downto 19);
w.state := 4;
when 4 =>
-- 4th accumulation
if filt(3)='1' then
w.vi := r.vi + s13_to_18(ext_in);
else
w.vnf := r.vnf + s13_to_18(ext_in);
end if;
w.dVlp := mulr(35) & mulr(35 downto 19);
w.Vbp := r.Vbp - r.dVbp;
-- Get Q, synchronous.
w.q := to_signed(divmul(to_integer(unsigned(res))), 18);
w.state := 5;
when 5 =>
-- Ok, we have all summed. We performed multiplications for dVbp and dVlp.
-- new Vbp already computed.
mulen <= '1';
mula <= r.q;
mulb <= r.Vbp;
w.vlp := r.Vlp - r.dVlp;
-- Start computing output;
if hp_bp_lp(1)='1' then
w.Vf := r.Vbp;
else
w.Vf := (others => '0');
end if;
w.state := 6;
when 6 =>
-- Adjust Vbp*Q, shift by 10
w.Vhp := (mulr(35)&mulr(35)&mulr(25 downto 10)) - r.vlp;
if hp_bp_lp(0)='1' then
w.Vf := r.Vf + r.Vlp;
end if;
w.state := 7;
when 7 =>
w.Vhp := r.Vhp - r.Vi;
w.state := 8;
when 8 =>
if hp_bp_lp(2)='1' then
w.Vf := r.Vf + r.Vhp;
end if;
w.state := 9;
when 9 =>
w.Vf := r.Vf + r.Vnf;
w.state := 10;
when 10 =>
-- Add mixer DC
w.Vf := r.Vf + to_signed(mixer_DC, r.Vf'LENGTH);
w.state := 11;
when 11 =>
-- Process volume
mulen <= '1';
mula <= r.Vf;
mulb <= (others => '0');
mulb(3 downto 0) <= signed(volume);
w.state := 12;
when 12 =>
w.done := '1';
w.vout(18) := mulr(35);
w.vout(17 downto 0) := mulr(17 downto 0);
w.state := 0;
when others =>
end case;
if rst='1' then
w.done := '0';
w.state := 0;
w.Vlp := (others => '0');
w.Vbp := (others => '0');
w.Vhp := (others => '0');
end if;
if rising_edge(clk) then
r<=w;
if r.state=8 then
dbg_Vbp <= r.vbp;
dbg_Vhp <= r.vhp;
dbg_Vlp <= r.vlp;
end if;
end if;
end process;
sound <= r.vout;
valid <= r.done;
end beh;
|
--
-- (C) Alvaro Lopes <[email protected]> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end entity;
architecture beh of sid_filters is
alias filt: std_logic_vector(3 downto 0) is Res_Filt(3 downto 0);
alias res: std_logic_vector(3 downto 0) is Res_Filt(7 downto 4);
alias voice3off: std_logic is Mode_Vol(7);
alias volume: std_logic_vector(3 downto 0) is Mode_Vol(3 downto 0);
alias hp_bp_lp: std_logic_vector(2 downto 0) is Mode_Vol(6 downto 4);
constant mixer_DC: integer := -475; -- NOTE to self: this might be wrong.
component sid_coeffs is
port (
clk: in std_logic;
addr: in integer range 0 to 2047;
val: out std_logic_vector(15 downto 0)
);
end component;
type regs_type is record
Vhp: signed(17 downto 0);
Vbp: signed(17 downto 0);
dVbp: signed(17 downto 0);
Vlp: signed(17 downto 0);
dVlp: signed(17 downto 0);
Vi: signed(17 downto 0);
Vnf: signed(17 downto 0);
Vf: signed(17 downto 0);
w0: signed(17 downto 0);
q: signed(17 downto 0);
vout:signed(18 downto 0);
state: integer;
done: std_logic;
end record;
signal dVhp_debug: signed(31 downto 0);
signal dVbp_debug: signed(31 downto 0);
signal addr: integer range 0 to 2047;
signal val: std_logic_vector(15 downto 0);
type divmul_t is array(0 to 15) of integer;
constant divmul: divmul_t := (
1448, 1323, 1218, 1128, 1051, 984, 925, 872, 825, 783, 745, 710, 679, 650, 624, 599
);
signal r: regs_type;
signal mula: signed(17 downto 0);
signal mulb: signed(17 downto 0);
signal mulr: signed(35 downto 0);
signal mulen: std_logic;
function s13_to_18(a: in signed(12 downto 0)) return signed is
variable r: signed(17 downto 0);
begin
r(12 downto 0):=a;
r(13):=a(12);
r(14):=a(12);
r(15):=a(12);
r(16):=a(12);
r(17):=a(12);
return r;
end function;
-- Debugging
signal dbg_Vlp, dbg_Vhp, dbg_Vbp: signed(17 downto 0);
signal fc: std_logic_vector(10 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if mulen='1' then
mulr <= mula * mulb;
end if;
end if;
end process;
fc <= Fc_hi & Fc_lo(2 downto 0);
c: sid_coeffs
port map (
clk => clk,
addr => addr,
val => val
);
addr <= to_integer(unsigned(fc));
process(clk, rst, r, input_valid, val, filt, voice1, voice2, voice3, voice3off, mulr, ext_in, hp_bp_lp, Mode_Vol)
variable w: regs_type;
begin
w:=r;
mula <= (others => 'X');
mulb <= (others => 'X');
mulen <= '0';
case r.state is
when 0 =>
w.done := '0';
if input_valid = '1' then
w.state := 1;
-- Reset Vin, Vnf
w.vi := (others => '0');
w.vnf := (others => '0');
end if;
when 1 =>
-- already have W0 ready. Always positive
w.w0 := "00" & signed(val);
-- 1st accumulation
if filt(0)='1' then
w.vi := r.vi + s13_to_18(voice1);
else
w.vnf := r.vnf + s13_to_18(voice1);
end if;
w.state := 2;
when 2 =>
-- 2nd accumulation
if filt(1)='1' then
w.vi := r.vi + s13_to_18(voice2);
else
w.vnf := r.vnf + s13_to_18(voice2);
end if;
-- Mult
mula <= r.w0;
mulb <= r.vhp;
mulen <= '1';
w.state := 3;
when 3 =>
-- 3rd accumulation
if filt(2)='1' then
w.vi := r.vi + s13_to_18(voice3);
else
if voice3off='0' then
w.vnf := r.vnf + s13_to_18(voice3);
end if;
end if;
-- Mult
mula <= r.w0;
mulb <= r.vbp;
mulen <= '1';
w.dVbp := mulr(35) & mulr(35 downto 19);
w.state := 4;
when 4 =>
-- 4th accumulation
if filt(3)='1' then
w.vi := r.vi + s13_to_18(ext_in);
else
w.vnf := r.vnf + s13_to_18(ext_in);
end if;
w.dVlp := mulr(35) & mulr(35 downto 19);
w.Vbp := r.Vbp - r.dVbp;
-- Get Q, synchronous.
w.q := to_signed(divmul(to_integer(unsigned(res))), 18);
w.state := 5;
when 5 =>
-- Ok, we have all summed. We performed multiplications for dVbp and dVlp.
-- new Vbp already computed.
mulen <= '1';
mula <= r.q;
mulb <= r.Vbp;
w.vlp := r.Vlp - r.dVlp;
-- Start computing output;
if hp_bp_lp(1)='1' then
w.Vf := r.Vbp;
else
w.Vf := (others => '0');
end if;
w.state := 6;
when 6 =>
-- Adjust Vbp*Q, shift by 10
w.Vhp := (mulr(35)&mulr(35)&mulr(25 downto 10)) - r.vlp;
if hp_bp_lp(0)='1' then
w.Vf := r.Vf + r.Vlp;
end if;
w.state := 7;
when 7 =>
w.Vhp := r.Vhp - r.Vi;
w.state := 8;
when 8 =>
if hp_bp_lp(2)='1' then
w.Vf := r.Vf + r.Vhp;
end if;
w.state := 9;
when 9 =>
w.Vf := r.Vf + r.Vnf;
w.state := 10;
when 10 =>
-- Add mixer DC
w.Vf := r.Vf + to_signed(mixer_DC, r.Vf'LENGTH);
w.state := 11;
when 11 =>
-- Process volume
mulen <= '1';
mula <= r.Vf;
mulb <= (others => '0');
mulb(3 downto 0) <= signed(volume);
w.state := 12;
when 12 =>
w.done := '1';
w.vout(18) := mulr(35);
w.vout(17 downto 0) := mulr(17 downto 0);
w.state := 0;
when others =>
end case;
if rst='1' then
w.done := '0';
w.state := 0;
w.Vlp := (others => '0');
w.Vbp := (others => '0');
w.Vhp := (others => '0');
end if;
if rising_edge(clk) then
r<=w;
if r.state=8 then
dbg_Vbp <= r.vbp;
dbg_Vhp <= r.vhp;
dbg_Vlp <= r.vlp;
end if;
end if;
end process;
sound <= r.vout;
valid <= r.done;
end beh;
|
--
-- (C) Alvaro Lopes <[email protected]> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end entity;
architecture beh of sid_filters is
alias filt: std_logic_vector(3 downto 0) is Res_Filt(3 downto 0);
alias res: std_logic_vector(3 downto 0) is Res_Filt(7 downto 4);
alias voice3off: std_logic is Mode_Vol(7);
alias volume: std_logic_vector(3 downto 0) is Mode_Vol(3 downto 0);
alias hp_bp_lp: std_logic_vector(2 downto 0) is Mode_Vol(6 downto 4);
constant mixer_DC: integer := -475; -- NOTE to self: this might be wrong.
component sid_coeffs is
port (
clk: in std_logic;
addr: in integer range 0 to 2047;
val: out std_logic_vector(15 downto 0)
);
end component;
type regs_type is record
Vhp: signed(17 downto 0);
Vbp: signed(17 downto 0);
dVbp: signed(17 downto 0);
Vlp: signed(17 downto 0);
dVlp: signed(17 downto 0);
Vi: signed(17 downto 0);
Vnf: signed(17 downto 0);
Vf: signed(17 downto 0);
w0: signed(17 downto 0);
q: signed(17 downto 0);
vout:signed(18 downto 0);
state: integer;
done: std_logic;
end record;
signal dVhp_debug: signed(31 downto 0);
signal dVbp_debug: signed(31 downto 0);
signal addr: integer range 0 to 2047;
signal val: std_logic_vector(15 downto 0);
type divmul_t is array(0 to 15) of integer;
constant divmul: divmul_t := (
1448, 1323, 1218, 1128, 1051, 984, 925, 872, 825, 783, 745, 710, 679, 650, 624, 599
);
signal r: regs_type;
signal mula: signed(17 downto 0);
signal mulb: signed(17 downto 0);
signal mulr: signed(35 downto 0);
signal mulen: std_logic;
function s13_to_18(a: in signed(12 downto 0)) return signed is
variable r: signed(17 downto 0);
begin
r(12 downto 0):=a;
r(13):=a(12);
r(14):=a(12);
r(15):=a(12);
r(16):=a(12);
r(17):=a(12);
return r;
end function;
-- Debugging
signal dbg_Vlp, dbg_Vhp, dbg_Vbp: signed(17 downto 0);
signal fc: std_logic_vector(10 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if mulen='1' then
mulr <= mula * mulb;
end if;
end if;
end process;
fc <= Fc_hi & Fc_lo(2 downto 0);
c: sid_coeffs
port map (
clk => clk,
addr => addr,
val => val
);
addr <= to_integer(unsigned(fc));
process(clk, rst, r, input_valid, val, filt, voice1, voice2, voice3, voice3off, mulr, ext_in, hp_bp_lp, Mode_Vol)
variable w: regs_type;
begin
w:=r;
mula <= (others => 'X');
mulb <= (others => 'X');
mulen <= '0';
case r.state is
when 0 =>
w.done := '0';
if input_valid = '1' then
w.state := 1;
-- Reset Vin, Vnf
w.vi := (others => '0');
w.vnf := (others => '0');
end if;
when 1 =>
-- already have W0 ready. Always positive
w.w0 := "00" & signed(val);
-- 1st accumulation
if filt(0)='1' then
w.vi := r.vi + s13_to_18(voice1);
else
w.vnf := r.vnf + s13_to_18(voice1);
end if;
w.state := 2;
when 2 =>
-- 2nd accumulation
if filt(1)='1' then
w.vi := r.vi + s13_to_18(voice2);
else
w.vnf := r.vnf + s13_to_18(voice2);
end if;
-- Mult
mula <= r.w0;
mulb <= r.vhp;
mulen <= '1';
w.state := 3;
when 3 =>
-- 3rd accumulation
if filt(2)='1' then
w.vi := r.vi + s13_to_18(voice3);
else
if voice3off='0' then
w.vnf := r.vnf + s13_to_18(voice3);
end if;
end if;
-- Mult
mula <= r.w0;
mulb <= r.vbp;
mulen <= '1';
w.dVbp := mulr(35) & mulr(35 downto 19);
w.state := 4;
when 4 =>
-- 4th accumulation
if filt(3)='1' then
w.vi := r.vi + s13_to_18(ext_in);
else
w.vnf := r.vnf + s13_to_18(ext_in);
end if;
w.dVlp := mulr(35) & mulr(35 downto 19);
w.Vbp := r.Vbp - r.dVbp;
-- Get Q, synchronous.
w.q := to_signed(divmul(to_integer(unsigned(res))), 18);
w.state := 5;
when 5 =>
-- Ok, we have all summed. We performed multiplications for dVbp and dVlp.
-- new Vbp already computed.
mulen <= '1';
mula <= r.q;
mulb <= r.Vbp;
w.vlp := r.Vlp - r.dVlp;
-- Start computing output;
if hp_bp_lp(1)='1' then
w.Vf := r.Vbp;
else
w.Vf := (others => '0');
end if;
w.state := 6;
when 6 =>
-- Adjust Vbp*Q, shift by 10
w.Vhp := (mulr(35)&mulr(35)&mulr(25 downto 10)) - r.vlp;
if hp_bp_lp(0)='1' then
w.Vf := r.Vf + r.Vlp;
end if;
w.state := 7;
when 7 =>
w.Vhp := r.Vhp - r.Vi;
w.state := 8;
when 8 =>
if hp_bp_lp(2)='1' then
w.Vf := r.Vf + r.Vhp;
end if;
w.state := 9;
when 9 =>
w.Vf := r.Vf + r.Vnf;
w.state := 10;
when 10 =>
-- Add mixer DC
w.Vf := r.Vf + to_signed(mixer_DC, r.Vf'LENGTH);
w.state := 11;
when 11 =>
-- Process volume
mulen <= '1';
mula <= r.Vf;
mulb <= (others => '0');
mulb(3 downto 0) <= signed(volume);
w.state := 12;
when 12 =>
w.done := '1';
w.vout(18) := mulr(35);
w.vout(17 downto 0) := mulr(17 downto 0);
w.state := 0;
when others =>
end case;
if rst='1' then
w.done := '0';
w.state := 0;
w.Vlp := (others => '0');
w.Vbp := (others => '0');
w.Vhp := (others => '0');
end if;
if rising_edge(clk) then
r<=w;
if r.state=8 then
dbg_Vbp <= r.vbp;
dbg_Vhp <= r.vhp;
dbg_Vlp <= r.vlp;
end if;
end if;
end process;
sound <= r.vout;
valid <= r.done;
end beh;
|
--
-- (C) Alvaro Lopes <[email protected]> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end entity;
architecture beh of sid_filters is
alias filt: std_logic_vector(3 downto 0) is Res_Filt(3 downto 0);
alias res: std_logic_vector(3 downto 0) is Res_Filt(7 downto 4);
alias voice3off: std_logic is Mode_Vol(7);
alias volume: std_logic_vector(3 downto 0) is Mode_Vol(3 downto 0);
alias hp_bp_lp: std_logic_vector(2 downto 0) is Mode_Vol(6 downto 4);
constant mixer_DC: integer := -475; -- NOTE to self: this might be wrong.
component sid_coeffs is
port (
clk: in std_logic;
addr: in integer range 0 to 2047;
val: out std_logic_vector(15 downto 0)
);
end component;
type regs_type is record
Vhp: signed(17 downto 0);
Vbp: signed(17 downto 0);
dVbp: signed(17 downto 0);
Vlp: signed(17 downto 0);
dVlp: signed(17 downto 0);
Vi: signed(17 downto 0);
Vnf: signed(17 downto 0);
Vf: signed(17 downto 0);
w0: signed(17 downto 0);
q: signed(17 downto 0);
vout:signed(18 downto 0);
state: integer;
done: std_logic;
end record;
signal dVhp_debug: signed(31 downto 0);
signal dVbp_debug: signed(31 downto 0);
signal addr: integer range 0 to 2047;
signal val: std_logic_vector(15 downto 0);
type divmul_t is array(0 to 15) of integer;
constant divmul: divmul_t := (
1448, 1323, 1218, 1128, 1051, 984, 925, 872, 825, 783, 745, 710, 679, 650, 624, 599
);
signal r: regs_type;
signal mula: signed(17 downto 0);
signal mulb: signed(17 downto 0);
signal mulr: signed(35 downto 0);
signal mulen: std_logic;
function s13_to_18(a: in signed(12 downto 0)) return signed is
variable r: signed(17 downto 0);
begin
r(12 downto 0):=a;
r(13):=a(12);
r(14):=a(12);
r(15):=a(12);
r(16):=a(12);
r(17):=a(12);
return r;
end function;
-- Debugging
signal dbg_Vlp, dbg_Vhp, dbg_Vbp: signed(17 downto 0);
signal fc: std_logic_vector(10 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if mulen='1' then
mulr <= mula * mulb;
end if;
end if;
end process;
fc <= Fc_hi & Fc_lo(2 downto 0);
c: sid_coeffs
port map (
clk => clk,
addr => addr,
val => val
);
addr <= to_integer(unsigned(fc));
process(clk, rst, r, input_valid, val, filt, voice1, voice2, voice3, voice3off, mulr, ext_in, hp_bp_lp, Mode_Vol)
variable w: regs_type;
begin
w:=r;
mula <= (others => 'X');
mulb <= (others => 'X');
mulen <= '0';
case r.state is
when 0 =>
w.done := '0';
if input_valid = '1' then
w.state := 1;
-- Reset Vin, Vnf
w.vi := (others => '0');
w.vnf := (others => '0');
end if;
when 1 =>
-- already have W0 ready. Always positive
w.w0 := "00" & signed(val);
-- 1st accumulation
if filt(0)='1' then
w.vi := r.vi + s13_to_18(voice1);
else
w.vnf := r.vnf + s13_to_18(voice1);
end if;
w.state := 2;
when 2 =>
-- 2nd accumulation
if filt(1)='1' then
w.vi := r.vi + s13_to_18(voice2);
else
w.vnf := r.vnf + s13_to_18(voice2);
end if;
-- Mult
mula <= r.w0;
mulb <= r.vhp;
mulen <= '1';
w.state := 3;
when 3 =>
-- 3rd accumulation
if filt(2)='1' then
w.vi := r.vi + s13_to_18(voice3);
else
if voice3off='0' then
w.vnf := r.vnf + s13_to_18(voice3);
end if;
end if;
-- Mult
mula <= r.w0;
mulb <= r.vbp;
mulen <= '1';
w.dVbp := mulr(35) & mulr(35 downto 19);
w.state := 4;
when 4 =>
-- 4th accumulation
if filt(3)='1' then
w.vi := r.vi + s13_to_18(ext_in);
else
w.vnf := r.vnf + s13_to_18(ext_in);
end if;
w.dVlp := mulr(35) & mulr(35 downto 19);
w.Vbp := r.Vbp - r.dVbp;
-- Get Q, synchronous.
w.q := to_signed(divmul(to_integer(unsigned(res))), 18);
w.state := 5;
when 5 =>
-- Ok, we have all summed. We performed multiplications for dVbp and dVlp.
-- new Vbp already computed.
mulen <= '1';
mula <= r.q;
mulb <= r.Vbp;
w.vlp := r.Vlp - r.dVlp;
-- Start computing output;
if hp_bp_lp(1)='1' then
w.Vf := r.Vbp;
else
w.Vf := (others => '0');
end if;
w.state := 6;
when 6 =>
-- Adjust Vbp*Q, shift by 10
w.Vhp := (mulr(35)&mulr(35)&mulr(25 downto 10)) - r.vlp;
if hp_bp_lp(0)='1' then
w.Vf := r.Vf + r.Vlp;
end if;
w.state := 7;
when 7 =>
w.Vhp := r.Vhp - r.Vi;
w.state := 8;
when 8 =>
if hp_bp_lp(2)='1' then
w.Vf := r.Vf + r.Vhp;
end if;
w.state := 9;
when 9 =>
w.Vf := r.Vf + r.Vnf;
w.state := 10;
when 10 =>
-- Add mixer DC
w.Vf := r.Vf + to_signed(mixer_DC, r.Vf'LENGTH);
w.state := 11;
when 11 =>
-- Process volume
mulen <= '1';
mula <= r.Vf;
mulb <= (others => '0');
mulb(3 downto 0) <= signed(volume);
w.state := 12;
when 12 =>
w.done := '1';
w.vout(18) := mulr(35);
w.vout(17 downto 0) := mulr(17 downto 0);
w.state := 0;
when others =>
end case;
if rst='1' then
w.done := '0';
w.state := 0;
w.Vlp := (others => '0');
w.Vbp := (others => '0');
w.Vhp := (others => '0');
end if;
if rising_edge(clk) then
r<=w;
if r.state=8 then
dbg_Vbp <= r.vbp;
dbg_Vhp <= r.vhp;
dbg_Vlp <= r.vlp;
end if;
end if;
end process;
sound <= r.vout;
valid <= r.done;
end beh;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/Complex3Multiply_block8.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply_block8
-- Source Path: fft_16_bit/FFT HDL Optimized/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply_block8 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din2_re_dly3 : IN std_logic_vector(19 DOWNTO 0); -- sfix20
din2_im_dly3 : IN std_logic_vector(19 DOWNTO 0); -- sfix20
di2_vld_dly3 : IN std_logic;
twdl_3_14_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_14_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_14_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_14_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin2_vld : OUT std_logic
);
END Complex3Multiply_block8;
ARCHITECTURE rtl OF Complex3Multiply_block8 IS
-- Signals
SIGNAL din2_re_dly3_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL din2_im_dly3_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_sum : signed(20 DOWNTO 0); -- sfix21
SIGNAL twdl_3_14_re_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_re_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_14_im_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_im_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL adder_add_cast : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL adder_add_cast_1 : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL twdl_sum : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(20 DOWNTO 0); -- sfix21
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(17 DOWNTO 0); -- sfix18
SIGNAL prodOfRe : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL prodOfIm : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL prodOfSum : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Add_multRes_re_reg1 : signed(37 DOWNTO 0); -- sfix38
SIGNAL Complex3Add_multRes_re_reg2 : signed(37 DOWNTO 0); -- sfix38
SIGNAL Complex3Add_multRes_im_reg : signed(39 DOWNTO 0); -- sfix40
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prod_vld_reg2 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Add_tmpResult_reg_next : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL Complex3Add_multRes_re_reg1_next : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL Complex3Add_multRes_re_reg2_next : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL Complex3Add_multRes_im_reg_next : signed(39 DOWNTO 0); -- sfix40_En15
SIGNAL Complex3Add_prod_vld_reg1_next : std_logic;
SIGNAL Complex3Add_prod_vld_reg2_next : std_logic;
SIGNAL Complex3Add_prodOfSum_reg_next : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL multResFP_re : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL multResFP_im : signed(39 DOWNTO 0); -- sfix40_En15
SIGNAL twdlXdin_14_re_tmp : signed(19 DOWNTO 0); -- sfix20
SIGNAL twdlXdin_14_im_tmp : signed(19 DOWNTO 0); -- sfix20
BEGIN
din2_re_dly3_signed <= signed(din2_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#00000#, 20);
ELSE
din_re_reg <= din2_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din2_im_dly3_signed <= signed(din2_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#00000#, 20);
ELSE
din_im_reg <= din2_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
din_sum <= resize(din_re_reg, 21) + resize(din_im_reg, 21);
twdl_3_14_re_signed <= signed(twdl_3_14_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSE
twdl_re_reg <= twdl_3_14_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_14_im_signed <= signed(twdl_3_14_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSE
twdl_im_reg <= twdl_3_14_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast <= resize(twdl_re_reg, 18);
adder_add_cast_1 <= resize(twdl_im_reg, 18);
twdl_sum <= adder_add_cast + adder_add_cast_1;
-- Complex3Multiply
Complex3Multiply_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly1 <= di2_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 39);
Complex3Add_tmpResult_reg <= to_signed(0, 39);
Complex3Add_multRes_re_reg1 <= to_signed(0, 38);
Complex3Add_multRes_re_reg2 <= to_signed(0, 38);
Complex3Add_multRes_im_reg <= to_signed(0, 40);
Complex3Add_prod_vld_reg1 <= '0';
Complex3Add_prod_vld_reg2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prod_vld_reg1 <= Complex3Add_prod_vld_reg1_next;
Complex3Add_prod_vld_reg2 <= Complex3Add_prod_vld_reg2_next;
Complex3Add_prodOfSum_reg <= Complex3Add_prodOfSum_reg_next;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_output : PROCESS (Complex3Add_tmpResult_reg, Complex3Add_multRes_re_reg1,
Complex3Add_multRes_re_reg2, Complex3Add_multRes_im_reg,
Complex3Add_prod_vld_reg1, Complex3Add_prod_vld_reg2,
Complex3Add_prodOfSum_reg, prodOfRe, prodOfIm, prodOfSum, prod_vld)
VARIABLE sub_cast : signed(37 DOWNTO 0);
VARIABLE sub_cast_0 : signed(37 DOWNTO 0);
VARIABLE sub_cast_1 : signed(39 DOWNTO 0);
VARIABLE sub_cast_2 : signed(39 DOWNTO 0);
VARIABLE add_cast : signed(37 DOWNTO 0);
VARIABLE add_cast_0 : signed(37 DOWNTO 0);
VARIABLE add_temp : signed(37 DOWNTO 0);
BEGIN
Complex3Add_tmpResult_reg_next <= Complex3Add_tmpResult_reg;
Complex3Add_multRes_re_reg1_next <= Complex3Add_multRes_re_reg1;
Complex3Add_prodOfSum_reg_next <= Complex3Add_prodOfSum_reg;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
IF prod_vld = '1' THEN
sub_cast := resize(prodOfRe, 38);
sub_cast_0 := resize(prodOfIm, 38);
Complex3Add_multRes_re_reg1_next <= sub_cast - sub_cast_0;
END IF;
sub_cast_1 := resize(Complex3Add_prodOfSum_reg, 40);
sub_cast_2 := resize(Complex3Add_tmpResult_reg, 40);
Complex3Add_multRes_im_reg_next <= sub_cast_1 - sub_cast_2;
IF prod_vld = '1' THEN
add_cast := resize(prodOfRe, 38);
add_cast_0 := resize(prodOfIm, 38);
add_temp := add_cast + add_cast_0;
Complex3Add_tmpResult_reg_next <= resize(add_temp, 39);
END IF;
IF prod_vld = '1' THEN
Complex3Add_prodOfSum_reg_next <= prodOfSum;
END IF;
Complex3Add_prod_vld_reg2_next <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1_next <= prod_vld;
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin2_vld <= Complex3Add_prod_vld_reg2;
END PROCESS Complex3Add_output;
twdlXdin_14_re_tmp <= multResFP_re(34 DOWNTO 15);
twdlXdin_14_re <= std_logic_vector(twdlXdin_14_re_tmp);
twdlXdin_14_im_tmp <= multResFP_im(34 DOWNTO 15);
twdlXdin_14_im <= std_logic_vector(twdlXdin_14_im_tmp);
END rtl;
|
--============================================================================
--!
--! \file <FILE_NAME>
--!
--! \project <PROJECT_NAME>
--!
--! \langv VHDL-1993
--!
--! \brief <BRIEF_DESCRIPTION>.
--!
--! \details <DETAILED_DESCRIPTION>.
--!
--! \bug <BUGS_OR_KNOWN_ISSUES>.
--!
--! \see <REFERENCES>
--!
--! \copyright <COPYRIGHT_OR_LICENSE>
--!
--! Revision history:
--!
--! \version <VERSION>
--! \date <YYYY-MM-DD>
--! \author <AUTHOR_NAME>
--! \brief Create file.
--!
--============================================================================
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
package <PACKAGE_IDENTIFIER> is
component <MODULE_IDENTIFIER> is
generic (
my_generic : integer := 0
);
port (
my_port : std_logic
);
end component <MODULE_IDENTIFIER>;
end package <PACKAGE_IDENTIFIER>;
package body <PACKAGE_IDENTIFIER> is
end package body <PACKAGE_IDENTIFIER>;
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library work;
use work.<PACKAGE_IDENTIFIER>.all;
entity <MODULE_IDENTIFIER> is
generic (
<GENERIC_IDENTIFIER> : integer := 0
);
port (
<PORT_IDENTIFIER> : std_logic
);
begin
end entity <MODULE_IDENTIFIER>;
architecture <BEHAVIORAL|RTL|STRUCT> of <MODULE_IDENTIFIER> is
begin
end architecture <BEHAVIORAL|RTL|STRUCT>;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2534.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p13n02i02534ent IS
END c07s03b05x00p13n02i02534ent;
ARCHITECTURE c07s03b05x00p13n02i02534arch OF c07s03b05x00p13n02i02534ent IS
type Memory is array (Integer range <>) of Integer;
subtype T1 is Memory (1 to 6) ;
subtype T2 is Memory (2 to 4) ;
BEGIN
TESTING: PROCESS
variable V1 : T1 ;
variable V2 : T2 := (2,3,6) ;
BEGIN
V1 := Memory (V2) ; -- Failure_here
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c07s03b05x00p13n02i02534 - Bounds of the result are different from the index subtype of the target."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p13n02i02534arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2534.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p13n02i02534ent IS
END c07s03b05x00p13n02i02534ent;
ARCHITECTURE c07s03b05x00p13n02i02534arch OF c07s03b05x00p13n02i02534ent IS
type Memory is array (Integer range <>) of Integer;
subtype T1 is Memory (1 to 6) ;
subtype T2 is Memory (2 to 4) ;
BEGIN
TESTING: PROCESS
variable V1 : T1 ;
variable V2 : T2 := (2,3,6) ;
BEGIN
V1 := Memory (V2) ; -- Failure_here
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c07s03b05x00p13n02i02534 - Bounds of the result are different from the index subtype of the target."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p13n02i02534arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2534.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p13n02i02534ent IS
END c07s03b05x00p13n02i02534ent;
ARCHITECTURE c07s03b05x00p13n02i02534arch OF c07s03b05x00p13n02i02534ent IS
type Memory is array (Integer range <>) of Integer;
subtype T1 is Memory (1 to 6) ;
subtype T2 is Memory (2 to 4) ;
BEGIN
TESTING: PROCESS
variable V1 : T1 ;
variable V2 : T2 := (2,3,6) ;
BEGIN
V1 := Memory (V2) ; -- Failure_here
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c07s03b05x00p13n02i02534 - Bounds of the result are different from the index subtype of the target."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p13n02i02534arch;
|
Subsets and Splits